On Sun, Jun 5, 2022 at 9:12 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This issue concerns the value of mtval for illegal
> instruction exceptions, and came with a great test case.
> The fix is just two lines, in the first patch, but
> I noticed some cleanups on the way.
>
>
> r~
>
>
> Richard Henderson (3):
> target/riscv: Set env->bins in gen_exception_illegal
> target/riscv: Remove generate_exception_mtval
> target/riscv: Minimize the calls to decode_save_opc
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/translate.c | 31 +++++------
> .../riscv/insn_trans/trans_privileged.c.inc | 4 ++
> target/riscv/insn_trans/trans_rvh.c.inc | 2 +
> target/riscv/insn_trans/trans_rvi.c.inc | 2 +
> tests/tcg/riscv64/Makefile.softmmu-target | 21 ++++++++
> tests/tcg/riscv64/issue1060.S | 53 +++++++++++++++++++
> tests/tcg/riscv64/semihost.ld | 21 ++++++++
> 7 files changed, 116 insertions(+), 18 deletions(-)
> create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
> create mode 100644 tests/tcg/riscv64/issue1060.S
> create mode 100644 tests/tcg/riscv64/semihost.ld
>
> --
> 2.34.1
>
>