[PULL 000/117] target-arm queue
[PULL 00/72] target-arm queue
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Massive pullreq but almost all of that is RTH's SVE
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
refactoring patchset. The other interesting thing here is
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handling series. (Lots more in my to-review queue, but I don't
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the fix for compiling on aarch64 macos.
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like pullreqs growing too close to a hundred patches at a time :-))
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4
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit f7a1ea403e0282a7f57edd4298c4f65f24165da5:
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-29 16:34:56 -0700)
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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11
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220530
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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for you to fetch changes up to b1071174d2a2ab371082b7d4b5f19e98edc61ac6:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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target/arm: Remove aa64_sve check from before disas_sve (2022-05-30 17:05:12 +0100)
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MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
21
target-arm queue:
22
* docs/system/arm: Add FEAT_HCX to list of emulated features
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
23
* target/arm/hvf: Include missing "cpregs.h"
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
24
* hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
25
* SVE: refactor to use TRANS/TRANS_FEAT macros and push
25
* fpu: Minor NaN-related cleanups
26
SVE feature check down to individual insn level
26
* MAINTAINERS: email address updates
27
27
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----------------------------------------------------------------
28
----------------------------------------------------------------
29
Icenowy Zheng (1):
29
Bernhard Beschow (5):
30
hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
30
hw/net/lan9118: Extract lan9118_phy
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
31
35
32
Peter Maydell (1):
36
Leif Lindholm (1):
33
docs/system/arm: Add FEAT_HCX to list of emulated features
37
MAINTAINERS: update email address for Leif Lindholm
34
38
35
Philippe Mathieu-Daudé (1):
39
Peter Maydell (54):
36
target/arm/hvf: Include missing "cpregs.h"
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
42
softfloat: Allow runtime choice of inf * 0 + NaN result
43
tests/fp: Explicitly set inf-zero-nan rule
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
37
94
38
Richard Henderson (114):
95
Richard Henderson (11):
39
target/arm: Introduce TRANS, TRANS_FEAT
96
target/arm: Copy entire float_status in is_ebf
40
target/arm: Move null function and sve check into gen_gvec_ool_zz
97
softfloat: Inline pickNaNMulAdd
41
target/arm: Use TRANS_FEAT for gen_gvec_ool_zz
98
softfloat: Use goto for default nan case in pick_nan_muladd
42
target/arm: Move null function and sve check into gen_gvec_ool_zzz
99
softfloat: Remove which from parts_pick_nan_muladd
43
target/arm: Introduce gen_gvec_ool_arg_zzz
100
softfloat: Pad array size in pick_nan_muladd
44
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz
101
softfloat: Move propagateFloatx80NaN to softfloat.c
45
target/arm: Use TRANS_FEAT for do_sve2_zzz_ool
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
46
target/arm: Move null function and sve check into gen_gvec_ool_zzzz
103
softfloat: Inline pickNaN
47
target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz
104
softfloat: Share code between parts_pick_nan cases
48
target/arm: Introduce gen_gvec_ool_arg_zzzz
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
49
target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool
106
softfloat: Replace WHICH with RET in parts_pick_nan
50
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz
51
target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz
52
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz
53
target/arm: Use TRANS_FEAT for do_sve2_zzz_data
54
target/arm: Use TRANS_FEAT for do_sve2_zzzz_data
55
target/arm: Use TRANS_FEAT for do_sve2_zzw_data
56
target/arm: Use TRANS_FEAT for USDOT_zzzz
57
target/arm: Move null function and sve check into gen_gvec_ool_zzp
58
target/arm: Introduce gen_gvec_ool_arg_zpz
59
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz
60
target/arm: Use TRANS_FEAT for do_sve2_zpz_data
61
target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi
62
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi
63
target/arm: Move null function and sve check into gen_gvec_ool_zzzp
64
target/arm: Introduce gen_gvec_ool_arg_zpzz
65
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz
66
target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool
67
target/arm: Merge gen_gvec_fn_zz into do_mov_z
68
target/arm: Move null function and sve check into gen_gvec_fn_zzz
69
target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz
70
target/arm: More use of gen_gvec_fn_arg_zzz
71
target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz
72
target/arm: Use TRANS_FEAT for do_sve2_fn_zzz
73
target/arm: Use TRANS_FEAT for RAX1
74
target/arm: Introduce gen_gvec_fn_arg_zzzz
75
target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn
76
target/arm: Introduce gen_gvec_fn_zzi
77
target/arm: Use TRANS_FEAT for do_zz_dbm
78
target/arm: Hoist sve access check through do_sel_z
79
target/arm: Introduce gen_gvec_fn_arg_zzi
80
target/arm: Use TRANS_FEAT for do_sve2_fn2i
81
target/arm: Use TRANS_FEAT for do_vpz_ool
82
target/arm: Use TRANS_FEAT for do_shift_imm
83
target/arm: Introduce do_shift_zpzi
84
target/arm: Use TRANS_FEAT for do_shift_zpzi
85
target/arm: Use TRANS_FEAT for do_zpzzz_ool
86
target/arm: Move sve check into do_index
87
target/arm: Use TRANS_FEAT for do_index
88
target/arm: Use TRANS_FEAT for do_adr
89
target/arm: Use TRANS_FEAT for do_predset
90
target/arm: Use TRANS_FEAT for RDFFR, WRFFR
91
target/arm: Use TRANS_FEAT for do_pfirst_pnext
92
target/arm: Use TRANS_FEAT for do_EXT
93
target/arm: Use TRANS_FEAT for do_perm_pred3
94
target/arm: Use TRANS_FEAT for do_perm_pred2
95
target/arm: Move sve zip high_ofs into simd_data
96
target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q
97
target/arm: Use TRANS_FEAT for do_zip, do_zip_q
98
target/arm: Use TRANS_FEAT for do_clast_vector
99
target/arm: Use TRANS_FEAT for do_clast_fp
100
target/arm: Use TRANS_FEAT for do_clast_general
101
target/arm: Use TRANS_FEAT for do_last_fp
102
target/arm: Use TRANS_FEAT for do_last_general
103
target/arm: Use TRANS_FEAT for SPLICE
104
target/arm: Use TRANS_FEAT for do_ppzz_flags
105
target/arm: Use TRANS_FEAT for do_sve2_ppzz_flags
106
target/arm: Use TRANS_FEAT for do_ppzi_flags
107
target/arm: Use TRANS_FEAT for do_brk2, do_brk3
108
target/arm: Use TRANS_FEAT for MUL_zzi
109
target/arm: Reject dup_i w/ shifted byte early
110
target/arm: Reject add/sub w/ shifted byte early
111
target/arm: Reject copy w/ shifted byte early
112
target/arm: Use TRANS_FEAT for ADD_zzi
113
target/arm: Use TRANS_FEAT for do_zzi_sat
114
target/arm: Use TRANS_FEAT for do_zzi_ool
115
target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz
116
target/arm: Use TRANS_FEAT for FMMLA
117
target/arm: Move sve check into gen_gvec_fn_ppp
118
target/arm: Implement NOT (prediates) alias
119
target/arm: Use TRANS_FEAT for SEL_zpzz
120
target/arm: Use TRANS_FEAT for MOVPRFX
121
target/arm: Use TRANS_FEAT for FMLA
122
target/arm: Use TRANS_FEAT for BFMLA
123
target/arm: Rename do_zzz_fp to gen_gvec_ool_fpst_arg_zzz
124
target/arm: Use TRANS_FEAT for DO_FP3
125
target/arm: Use TRANS_FEAT for FMUL_zzx
126
target/arm: Use TRANS_FEAT for FTMAD
127
target/arm: Move null function and sve check into do_reduce
128
target/arm: Use TRANS_FEAT for do_reduce
129
target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE
130
target/arm: Expand frint_fns for MO_8
131
target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz
132
target/arm: Move null function and sve check into do_frint_mode
133
target/arm: Use TRANS_FEAT for do_frint_mode
134
target/arm: Use TRANS_FEAT for FLOGB
135
target/arm: Use TRANS_FEAT for do_ppz_fp
136
target/arm: Rename do_zpzz_ptr to gen_gvec_fpst_arg_zpzz
137
target/arm: Use TRANS_FEAT for gen_gvec_fpst_arg_zpzz
138
target/arm: Use TRANS_FEAT for FCADD
139
target/arm: Introduce gen_gvec_fpst_zzzzp
140
target/arm: Use TRANS_FEAT for gen_gvec_fpst_zzzzp
141
target/arm: Move null function and sve check into do_fp_imm
142
target/arm: Use TRANS_FEAT for DO_FP_IMM
143
target/arm: Use TRANS_FEAT for DO_FPCMP
144
target/arm: Remove assert in trans_FCMLA_zzxz
145
target/arm: Use TRANS_FEAT for FCMLA_zzxz
146
target/arm: Use TRANS_FEAT for do_narrow_extract
147
target/arm: Use TRANS_FEAT for do_shll_tb
148
target/arm: Use TRANS_FEAT for do_shr_narrow
149
target/arm: Use TRANS_FEAT for do_FMLAL_zzzw
150
target/arm: Use TRANS_FEAT for do_FMLAL_zzxw
151
target/arm: Add sve feature check for remaining trans_* functions
152
target/arm: Remove aa64_sve check from before disas_sve
153
107
154
docs/system/arm/emulation.rst | 1 +
108
Vikram Garhwal (1):
155
target/arm/translate.h | 11 +
109
MAINTAINERS: Add correct email address for Vikram Garhwal
156
target/arm/sve.decode | 57 +-
157
hw/sd/allwinner-sdhost.c | 7 +
158
target/arm/hvf/hvf.c | 1 +
159
target/arm/sve_helper.c | 6 +-
160
target/arm/translate-a64.c | 2 +-
161
target/arm/translate-sve.c | 5367 +++++++++++++++--------------------------
162
8 files changed, 2067 insertions(+), 3385 deletions(-)
163
110
111
MAINTAINERS | 4 +-
112
include/fpu/softfloat-helpers.h | 38 +++-
113
include/fpu/softfloat-types.h | 89 +++++++-
114
include/hw/net/imx_fec.h | 9 +-
115
include/hw/net/lan9118_phy.h | 37 ++++
116
include/hw/net/mii.h | 6 +
117
target/mips/fpu_helper.h | 20 ++
118
target/sparc/helper.h | 4 +-
119
fpu/softfloat.c | 19 ++
120
hw/net/imx_fec.c | 146 ++------------
121
hw/net/lan9118.c | 137 ++-----------
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
123
linux-user/arm/nwfpe/fpa11.c | 5 +
124
target/alpha/cpu.c | 2 +
125
target/arm/cpu.c | 10 +
126
target/arm/tcg/vec_helper.c | 20 +-
127
target/hexagon/cpu.c | 2 +
128
target/hppa/fpu_helper.c | 12 ++
129
target/i386/tcg/fpu_helper.c | 12 ++
130
target/loongarch/tcg/fpu_helper.c | 14 +-
131
target/m68k/cpu.c | 14 +-
132
target/m68k/fpu_helper.c | 6 +-
133
target/m68k/helper.c | 6 +-
134
target/microblaze/cpu.c | 2 +
135
target/mips/msa.c | 10 +
136
target/openrisc/cpu.c | 2 +
137
target/ppc/cpu_init.c | 19 ++
138
target/ppc/fpu_helper.c | 3 +-
139
target/riscv/cpu.c | 2 +
140
target/rx/cpu.c | 2 +
141
target/s390x/cpu.c | 5 +
142
target/sh4/cpu.c | 2 +
143
target/sparc/cpu.c | 6 +
144
target/sparc/fop_helper.c | 8 +-
145
target/sparc/translate.c | 4 +-
146
target/tricore/helper.c | 2 +
147
target/xtensa/cpu.c | 4 +
148
target/xtensa/fpu_helper.c | 3 +-
149
tests/fp/fp-bench.c | 7 +
150
tests/fp/fp-test-log2.c | 1 +
151
tests/fp/fp-test.c | 7 +
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
154
.mailmap | 5 +-
155
hw/net/Kconfig | 5 +
156
hw/net/meson.build | 1 +
157
hw/net/trace-events | 10 +-
158
47 files changed, 778 insertions(+), 730 deletions(-)
159
create mode 100644 include/hw/net/lan9118_phy.h
160
create mode 100644 hw/net/lan9118_phy.c
diff view generated by jsdifflib
[PULL 026/117] target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Rename the function to match gen_gvec_ool_arg_zpz,
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
and move to be adjacent.
4
a common implementation by extracting a device model into its own files.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Some migration state has been moved into the new device model which breaks
7
Message-id: 20220527181907.189259-24-richard.henderson@linaro.org
7
migration compatibility for the following machines:
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
13
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
16
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
22
---
11
target/arm/translate-sve.c | 29 ++++++++++++++---------------
23
include/hw/net/lan9118_phy.h | 37 ++++++++
12
1 file changed, 14 insertions(+), 15 deletions(-)
24
hw/net/lan9118.c | 137 +++++-----------------------
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
26
hw/net/Kconfig | 4 +
27
hw/net/meson.build | 1 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
13
31
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
15
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
77
--- a/hw/net/lan9118.c
17
+++ b/target/arm/translate-sve.c
78
+++ b/hw/net/lan9118.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn,
79
@@ -XXX,XX +XXX,XX @@
19
return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data);
80
#include "net/net.h"
81
#include "net/eth.h"
82
#include "hw/irq.h"
83
+#include "hw/net/lan9118_phy.h"
84
#include "hw/net/lan9118.h"
85
#include "hw/ptimer.h"
86
#include "hw/qdev-properties.h"
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
88
#define MAC_CR_RXEN 0x00000004
89
#define MAC_CR_RESERVED 0x7f404213
90
91
-#define PHY_INT_ENERGYON 0x80
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
93
-#define PHY_INT_FAULT 0x20
94
-#define PHY_INT_DOWN 0x10
95
-#define PHY_INT_AUTONEG_LP 0x08
96
-#define PHY_INT_PARFAULT 0x04
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
20
}
141
}
21
142
22
+static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
143
-static void phy_update_irq(lan9118_state *s)
23
+ arg_rpri_esz *a)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
24
+{
145
{
25
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
146
- if (s->phy_int & s->phy_int_mask) {
26
+}
147
+ lan9118_state *s = opaque;
27
148
+
28
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
149
+ if (level) {
29
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
150
s->int_sts |= PHY_INT;
30
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
151
} else {
31
return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
152
s->int_sts &= ~PHY_INT;
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
154
lan9118_update(s);
32
}
155
}
33
156
34
-static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
157
-static void phy_update_link(lan9118_state *s)
35
- gen_helper_gvec_3 *fn)
36
-{
158
-{
37
- return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
159
- /* Autonegotiation status mirrors link status. */
160
- if (qemu_get_queue(s->nic)->link_down) {
161
- s->phy_status &= ~0x0024;
162
- s->phy_int |= PHY_INT_DOWN;
163
- } else {
164
- s->phy_status |= 0x0024;
165
- s->phy_int |= PHY_INT_ENERGYON;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
167
- }
168
- phy_update_irq(s);
38
-}
169
-}
39
-
170
-
40
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
171
static void lan9118_set_link(NetClientState *nc)
41
{
172
{
42
static gen_helper_gvec_3 * const fns[4] = {
173
- phy_update_link(qemu_get_nic_opaque(nc));
43
@@ -XXX,XX +XXX,XX @@ static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
174
-}
44
/* Shift by element size is architecturally valid. For
175
-
45
arithmetic right-shift, it's the same as by one less. */
176
-static void phy_reset(lan9118_state *s)
46
a->imm = MIN(a->imm, (8 << a->esz) - 1);
177
-{
47
- return do_zpzi_ool(s, a, fns[a->esz]);
178
- s->phy_status = 0x7809;
48
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
49
}
186
}
50
187
51
static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
188
static void lan9118_reset(DeviceState *d)
52
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
53
if (a->imm >= (8 << a->esz)) {
190
s->read_word_n = 0;
54
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
191
s->write_word_n = 0;
192
193
- phy_reset(s);
194
-
195
s->eeprom_writable = 0;
196
lan9118_reload_eeprom(s);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
199
uint32_t status;
200
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
202
- if (s->phy_control & 0x4000) {
203
+ if (s->mii.control & 0x4000) {
204
/* This assumes the receive routine doesn't touch the VLANClient. */
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
55
} else {
206
} else {
56
- return do_zpzi_ool(s, a, fns[a->esz]);
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
57
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
58
}
208
}
59
}
209
}
60
210
61
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
62
if (a->imm >= (8 << a->esz)) {
212
-{
63
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
213
- uint32_t val;
64
} else {
214
-
65
- return do_zpzi_ool(s, a, fns[a->esz]);
215
- switch (reg) {
66
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
216
- case 0: /* Basic Control */
67
}
217
- return s->phy_control;
68
}
218
- case 1: /* Basic Status */
69
219
- return s->phy_status;
70
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
220
- case 2: /* ID1 */
71
if (a->imm >= (8 << a->esz)) {
221
- return 0x0007;
72
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
222
- case 3: /* ID2 */
73
} else {
223
- return 0xc0d1;
74
- return do_zpzi_ool(s, a, fns[a->esz]);
224
- case 4: /* Auto-neg advertisement */
75
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
225
- return s->phy_advertise;
76
}
226
- case 5: /* Auto-neg Link Partner Ability */
77
}
227
- return 0x0f71;
78
228
- case 6: /* Auto-neg Expansion */
79
@@ -XXX,XX +XXX,XX @@ static bool trans_SQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
229
- return 1;
80
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
230
- /* TODO 17, 18, 27, 29, 30, 31 */
81
return false;
231
- case 29: /* Interrupt source. */
82
}
232
- val = s->phy_int;
83
- return do_zpzi_ool(s, a, fns[a->esz]);
233
- s->phy_int = 0;
84
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
234
- phy_update_irq(s);
85
}
235
- return val;
86
236
- case 30: /* Interrupt mask */
87
static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
237
- return s->phy_int_mask;
88
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
238
- default:
89
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
239
- qemu_log_mask(LOG_GUEST_ERROR,
90
return false;
240
- "do_phy_read: PHY read reg %d\n", reg);
91
}
241
- return 0;
92
- return do_zpzi_ool(s, a, fns[a->esz]);
242
- }
93
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
243
-}
94
}
244
-
95
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
96
static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
246
-{
97
@@ -XXX,XX +XXX,XX @@ static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
247
- switch (reg) {
98
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
248
- case 0: /* Basic Control */
99
return false;
249
- if (val & 0x8000) {
100
}
250
- phy_reset(s);
101
- return do_zpzi_ool(s, a, fns[a->esz]);
251
- break;
102
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
252
- }
103
}
253
- s->phy_control = val & 0x7980;
104
254
- /* Complete autonegotiation immediately. */
105
static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
255
- if (val & 0x1000) {
106
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
256
- s->phy_status |= 0x0020;
107
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
257
- }
108
return false;
258
- break;
109
}
259
- case 4: /* Auto-neg advertisement */
110
- return do_zpzi_ool(s, a, fns[a->esz]);
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
111
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
261
- break;
112
}
262
- /* TODO 17, 18, 27, 31 */
113
263
- case 30: /* Interrupt mask */
114
static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
264
- s->phy_int_mask = val & 0xff;
115
@@ -XXX,XX +XXX,XX @@ static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
265
- phy_update_irq(s);
116
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
266
- break;
117
return false;
267
- default:
118
}
268
- qemu_log_mask(LOG_GUEST_ERROR,
119
- return do_zpzi_ool(s, a, fns[a->esz]);
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
120
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
270
- }
121
}
271
-}
122
272
-
123
/*
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
274
{
275
switch (reg) {
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
277
if (val & 2) {
278
DPRINTF("PHY write %d = 0x%04x\n",
279
(val >> 6) & 0x1f, s->mac_mii_data);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
282
} else {
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
285
DPRINTF("PHY read %d = 0x%04x\n",
286
(val >> 6) & 0x1f, s->mac_mii_data);
287
}
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
289
break;
290
case CSR_PMT_CTRL:
291
if (val & 0x400) {
292
- phy_reset(s);
293
+ lan9118_phy_reset(&s->mii);
294
}
295
s->pmt_ctrl &= ~0x34e;
296
s->pmt_ctrl |= (val & 0x34e);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
298
const MemoryRegionOps *mem_ops =
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
300
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
304
+ return;
305
+ }
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
307
+
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
312
new file mode 100644
313
index XXXXXXX..XXXXXXX
314
--- /dev/null
315
+++ b/hw/net/lan9118_phy.c
316
@@ -XXX,XX +XXX,XX @@
317
+/*
318
+ * SMSC LAN9118 PHY emulation
319
+ *
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
324
+ *
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
326
+ * GNU GPL, version 2 or (at your option) any later version.
327
+ */
328
+
329
+#include "qemu/osdep.h"
330
+#include "hw/net/lan9118_phy.h"
331
+#include "hw/irq.h"
332
+#include "hw/resettable.h"
333
+#include "migration/vmstate.h"
334
+#include "qemu/log.h"
335
+
336
+#define PHY_INT_ENERGYON (1 << 7)
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
338
+#define PHY_INT_FAULT (1 << 5)
339
+#define PHY_INT_DOWN (1 << 4)
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
341
+#define PHY_INT_PARFAULT (1 << 2)
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
343
+
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
345
+{
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
347
+}
348
+
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
350
+{
351
+ uint16_t val;
352
+
353
+ switch (reg) {
354
+ case 0: /* Basic Control */
355
+ return s->control;
356
+ case 1: /* Basic Status */
357
+ return s->status;
358
+ case 2: /* ID1 */
359
+ return 0x0007;
360
+ case 3: /* ID2 */
361
+ return 0xc0d1;
362
+ case 4: /* Auto-neg advertisement */
363
+ return s->advertise;
364
+ case 5: /* Auto-neg Link Partner Ability */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
408
+ }
409
+}
410
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
412
+{
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/net/Kconfig
489
+++ b/hw/net/Kconfig
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
491
config SMC91C111
492
bool
493
494
+config LAN9118_PHY
495
+ bool
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
124
--
515
--
125
2.25.1
516
2.34.1
diff view generated by jsdifflib
[PULL 098/117] target/arm: Use TRANS_FEAT for do_frint_mode
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
Message-id: 20220527181907.189259-96-richard.henderson@linaro.org
4
imx_fec having more logging and tracing. Merge these improvements into
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
7
Some migration state how resides in the new device model which breaks migration
8
compatibility for the following machines:
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
13
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
19
---
8
target/arm/translate-sve.c | 53 ++++++++++----------------------------
20
include/hw/net/imx_fec.h | 9 ++-
9
1 file changed, 14 insertions(+), 39 deletions(-)
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
10
26
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
12
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
29
--- a/include/hw/net/imx_fec.h
14
+++ b/target/arm/translate-sve.c
30
+++ b/include/hw/net/imx_fec.h
15
@@ -XXX,XX +XXX,XX @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
16
return true;
32
#define TYPE_IMX_ENET "imx.enet"
17
}
33
18
34
#include "hw/sysbus.h"
19
-static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
35
+#include "hw/net/lan9118_phy.h"
36
+#include "hw/irq.h"
37
#include "net/net.h"
38
39
#define ENET_EIR 1
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
42
uint32_t tx_ring_num;
43
44
- uint32_t phy_status;
45
- uint32_t phy_control;
46
- uint32_t phy_advertise;
47
- uint32_t phy_int;
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
20
-{
104
-{
21
- return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
22
-}
123
-}
23
-
124
-
24
-static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
125
-static void imx_phy_reset(IMXFECState *s)
25
-{
126
-{
26
- return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
127
- trace_imx_phy_reset();
27
-}
128
-
28
-
129
- s->phy_status = 0x7809;
29
-static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
130
- s->phy_control = 0x3000;
30
-{
131
- s->phy_advertise = 0x01e1;
31
- return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
132
- s->phy_int_mask = 0;
32
-}
133
- s->phy_int = 0;
33
-
134
- imx_phy_update_link(s);
34
-static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
35
-{
136
+ nc->link_down);
36
- return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
137
}
37
-}
138
38
-
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
39
-static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
140
{
40
-{
141
- uint32_t val;
41
- return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
142
uint32_t phy = reg / 32;
42
-}
143
43
+TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a,
144
if (!s->phy_connected) {
44
+ float_round_nearest_even, frint_fns[a->esz])
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
45
+TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a,
146
46
+ float_round_up, frint_fns[a->esz])
147
reg %= 32;
47
+TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a,
148
48
+ float_round_down, frint_fns[a->esz])
149
- switch (reg) {
49
+TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a,
150
- case 0: /* Basic Control */
50
+ float_round_to_zero, frint_fns[a->esz])
151
- val = s->phy_control;
51
+TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a,
152
- break;
52
+ float_round_ties_away, frint_fns[a->esz])
153
- case 1: /* Basic Status */
53
154
- val = s->phy_status;
54
static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
155
- break;
55
NULL, gen_helper_sve_frecpx_h,
156
- case 2: /* ID1 */
56
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
157
- val = 0x0007;
57
TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
158
- break;
58
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
159
- case 3: /* ID2 */
59
160
- val = 0xc0d1;
60
-static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a)
161
- break;
61
-{
162
- case 4: /* Auto-neg advertisement */
62
- if (!dc_isar_feature(aa64_sve2, s)) {
163
- val = s->phy_advertise;
63
- return false;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
64
- }
192
- }
65
- return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve_fcvt_ds);
193
-
66
-}
194
- trace_imx_phy_read(val, phy, reg);
67
-
195
-
68
-static bool trans_FCVTXNT_ds(DisasContext *s, arg_rpr_esz *a)
196
- return val;
69
-{
197
+ return lan9118_phy_read(&s->mii, reg);
70
- if (!dc_isar_feature(aa64_sve2, s)) {
198
}
71
- return false;
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
72
- }
237
- }
73
- return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve2_fcvtnt_ds);
238
+ lan9118_phy_write(&s->mii, reg, val);
74
-}
239
}
75
+TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
240
76
+ float_round_to_odd, gen_helper_sve_fcvt_ds)
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
77
+TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
78
+ float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
243
79
244
s->rx_descriptor = 0;
80
static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a)
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
81
{
353
{
354
+ trace_lan9118_phy_write(val, reg);
355
+
356
switch (reg) {
357
case 0: /* Basic Control */
358
if (val & 0x8000) {
359
lan9118_phy_reset(s);
360
- break;
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
82
--
471
--
83
2.25.1
472
2.34.1
diff view generated by jsdifflib
[PULL 099/117] target/arm: Use TRANS_FEAT for FLOGB
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
Message-id: 20220527181907.189259-97-richard.henderson@linaro.org
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
5
6
Fixes: 2a424990170b "LAN9118 emulation"
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
target/arm/translate-sve.c | 29 ++++++-----------------------
13
hw/net/lan9118_phy.c | 2 +-
9
1 file changed, 6 insertions(+), 23 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
10
15
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
18
--- a/hw/net/lan9118_phy.c
14
+++ b/target/arm/translate-sve.c
19
+++ b/hw/net/lan9118_phy.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
16
TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
21
val = s->advertise;
17
float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
22
break;
18
23
case 5: /* Auto-neg Link Partner Ability */
19
-static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a)
24
- val = 0x0f71;
20
-{
25
+ val = 0x0fe1;
21
- static gen_helper_gvec_3_ptr * const fns[] = {
26
break;
22
- NULL, gen_helper_flogb_h,
27
case 6: /* Auto-neg Expansion */
23
- gen_helper_flogb_s, gen_helper_flogb_d
28
val = 1;
24
- };
25
-
26
- if (!dc_isar_feature(aa64_sve2, s) || fns[a->esz] == NULL) {
27
- return false;
28
- }
29
- if (sve_access_check(s)) {
30
- TCGv_ptr status =
31
- fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
32
- unsigned vsz = vec_full_reg_size(s);
33
-
34
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
35
- vec_full_reg_offset(s, a->rn),
36
- pred_full_reg_offset(s, a->pg),
37
- status, vsz, vsz, 0, fns[a->esz]);
38
- tcg_temp_free_ptr(status);
39
- }
40
- return true;
41
-}
42
+static gen_helper_gvec_3_ptr * const flogb_fns[] = {
43
+ NULL, gen_helper_flogb_h,
44
+ gen_helper_flogb_s, gen_helper_flogb_d
45
+};
46
+TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
47
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
48
49
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
50
{
51
--
29
--
52
2.25.1
30
2.34.1
diff view generated by jsdifflib
[PULL 096/117] target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Rename the function to match other expansion function and
3
Prefer named constants over magic values for better readability.
4
move to be adjacent. Split out gen_gvec_fpst_zzp as a
5
helper while we're at it.
6
4
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-94-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-sve.c | 392 ++++++++++++-------------------------
11
include/hw/net/mii.h | 6 +++++
13
1 file changed, 129 insertions(+), 263 deletions(-)
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
14
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
17
--- a/include/hw/net/mii.h
18
+++ b/target/arm/translate-sve.c
18
+++ b/include/hw/net/mii.h
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
19
@@ -XXX,XX +XXX,XX @@
20
return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
21
}
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
22
22
23
+static bool gen_gvec_fpst_zzp(DisasContext *s, gen_helper_gvec_3_ptr *fn,
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
24
+ int rd, int rn, int pg, int data,
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
25
+ ARMFPStatusFlavour flavour)
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
26
+{
26
#define MII_ANAR_TXFD (1 << 8)
27
+ if (fn == NULL) {
27
@@ -XXX,XX +XXX,XX @@
28
+ return false;
28
#define MII_ANAR_10FD (1 << 6)
29
+ }
29
#define MII_ANAR_10 (1 << 5)
30
+ if (sve_access_check(s)) {
30
#define MII_ANAR_CSMACD (1 << 0)
31
+ unsigned vsz = vec_full_reg_size(s);
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
+ TCGv_ptr status = fpstatus_ptr(flavour);
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
33
+
42
+
34
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
43
/* RealTek 8211E */
35
+ vec_full_reg_offset(s, rn),
44
#define RTL8211E_PHYID1 0x001c
36
+ pred_full_reg_offset(s, pg),
45
#define RTL8211E_PHYID2 0xc915
37
+ status, vsz, vsz, data, fn);
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
38
+ tcg_temp_free_ptr(status);
47
index XXXXXXX..XXXXXXX 100644
39
+ }
48
--- a/hw/net/lan9118_phy.c
40
+ return true;
49
+++ b/hw/net/lan9118_phy.c
41
+}
50
@@ -XXX,XX +XXX,XX @@
42
+
51
43
+static bool gen_gvec_fpst_arg_zpz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
52
#include "qemu/osdep.h"
44
+ arg_rpr_esz *a, int data,
53
#include "hw/net/lan9118_phy.h"
45
+ ARMFPStatusFlavour flavour)
54
+#include "hw/net/mii.h"
46
+{
55
#include "hw/irq.h"
47
+ return gen_gvec_fpst_zzp(s, fn, a->rd, a->rn, a->pg, data, flavour);
56
#include "hw/resettable.h"
48
+}
57
#include "migration/vmstate.h"
49
+
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
50
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
59
uint16_t val;
51
static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
60
52
int rd, int rn, int rm, int pg, int data)
61
switch (reg) {
53
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
62
- case 0: /* Basic Control */
54
*** SVE Floating Point Unary Operations Predicated Group
63
+ case MII_BMCR:
55
*/
64
val = s->control;
56
65
break;
57
-static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
66
- case 1: /* Basic Status */
58
- bool is_fp16, gen_helper_gvec_3_ptr *fn)
67
+ case MII_BMSR:
59
-{
68
val = s->status;
60
- if (sve_access_check(s)) {
69
break;
61
- unsigned vsz = vec_full_reg_size(s);
70
- case 2: /* ID1 */
62
- TCGv_ptr status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
71
- val = 0x0007;
63
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
72
+ case MII_PHYID1:
64
- vec_full_reg_offset(s, rn),
73
+ val = SMSCLAN9118_PHYID1;
65
- pred_full_reg_offset(s, pg),
74
break;
66
- status, vsz, vsz, 0, fn);
75
- case 3: /* ID2 */
67
- tcg_temp_free_ptr(status);
76
- val = 0xc0d1;
68
- }
77
+ case MII_PHYID2:
69
- return true;
78
+ val = SMSCLAN9118_PHYID2;
70
-}
79
break;
71
+TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
80
- case 4: /* Auto-neg advertisement */
72
+ gen_helper_sve_fcvt_sh, a, 0, FPST_FPCR)
81
+ case MII_ANAR:
73
+TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
82
val = s->advertise;
74
+ gen_helper_sve_fcvt_hs, a, 0, FPST_FPCR)
83
break;
75
84
- case 5: /* Auto-neg Link Partner Ability */
76
-static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a)
85
- val = 0x0fe1;
77
-{
86
+ case MII_ANLPAR:
78
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
79
-}
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
80
+TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
81
+ gen_helper_sve_bfcvt, a, 0, FPST_FPCR)
90
break;
82
91
- case 6: /* Auto-neg Expansion */
83
-static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a)
92
- val = 1;
84
-{
93
+ case MII_ANER:
85
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hs);
94
+ val = MII_ANER_NWAY;
86
-}
95
break;
87
+TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
96
case 29: /* Interrupt source. */
88
+ gen_helper_sve_fcvt_dh, a, 0, FPST_FPCR)
97
val = s->ints;
89
+TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
90
+ gen_helper_sve_fcvt_hd, a, 0, FPST_FPCR)
99
trace_lan9118_phy_write(val, reg);
91
+TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
100
92
+ gen_helper_sve_fcvt_ds, a, 0, FPST_FPCR)
101
switch (reg) {
93
+TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
102
- case 0: /* Basic Control */
94
+ gen_helper_sve_fcvt_sd, a, 0, FPST_FPCR)
103
- if (val & 0x8000) {
95
104
+ case MII_BMCR:
96
-static bool trans_BFCVT(DisasContext *s, arg_rpr_esz *a)
105
+ if (val & MII_BMCR_RESET) {
97
-{
106
lan9118_phy_reset(s);
98
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
107
} else {
99
- return false;
108
- s->control = val & 0x7980;
100
- }
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
101
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvt);
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
102
-}
111
+ MII_BMCR_CTST);
103
+TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
112
/* Complete autonegotiation immediately. */
104
+ gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16)
113
- if (val & 0x1000) {
105
+TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
114
- s->status |= 0x0020;
106
+ gen_helper_sve_fcvtzu_hh, a, 0, FPST_FPCR_F16)
115
+ if (val & MII_BMCR_AUTOEN) {
107
+TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
116
+ s->status |= MII_BMSR_AN_COMP;
108
+ gen_helper_sve_fcvtzs_hs, a, 0, FPST_FPCR_F16)
117
}
109
+TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
118
}
110
+ gen_helper_sve_fcvtzu_hs, a, 0, FPST_FPCR_F16)
119
break;
111
+TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
120
- case 4: /* Auto-neg advertisement */
112
+ gen_helper_sve_fcvtzs_hd, a, 0, FPST_FPCR_F16)
121
- s->advertise = (val & 0x2d7f) | 0x80;
113
+TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
122
+ case MII_ANAR:
114
+ gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16)
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
115
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
116
-static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a)
125
+ MII_ANAR_SELECT))
117
-{
126
+ | MII_ANAR_TX;
118
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
127
break;
119
-}
128
case 30: /* Interrupt mask */
120
+TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
129
s->int_mask = val & 0xff;
121
+ gen_helper_sve_fcvtzs_ss, a, 0, FPST_FPCR)
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
122
+TRANS_FEAT(FCVTZU_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
131
/* Autonegotiation status mirrors link status. */
123
+ gen_helper_sve_fcvtzu_ss, a, 0, FPST_FPCR)
132
if (link_down) {
124
+TRANS_FEAT(FCVTZS_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
133
trace_lan9118_phy_update_link("down");
125
+ gen_helper_sve_fcvtzs_sd, a, 0, FPST_FPCR)
134
- s->status &= ~0x0024;
126
+TRANS_FEAT(FCVTZU_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
127
+ gen_helper_sve_fcvtzu_sd, a, 0, FPST_FPCR)
136
s->ints |= PHY_INT_DOWN;
128
+TRANS_FEAT(FCVTZS_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
137
} else {
129
+ gen_helper_sve_fcvtzs_ds, a, 0, FPST_FPCR)
138
trace_lan9118_phy_update_link("up");
130
+TRANS_FEAT(FCVTZU_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
139
- s->status |= 0x0024;
131
+ gen_helper_sve_fcvtzu_ds, a, 0, FPST_FPCR)
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
132
141
s->ints |= PHY_INT_ENERGYON;
133
-static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a)
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
134
-{
143
}
135
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hd);
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
136
-}
137
-
138
-static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a)
139
-{
140
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_ds);
141
-}
142
-
143
-static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a)
144
-{
145
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sd);
146
-}
147
-
148
-static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a)
149
-{
150
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hh);
151
-}
152
-
153
-static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a)
154
-{
155
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hh);
156
-}
157
-
158
-static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a)
159
-{
160
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hs);
161
-}
162
-
163
-static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a)
164
-{
165
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hs);
166
-}
167
-
168
-static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a)
169
-{
170
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hd);
171
-}
172
-
173
-static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a)
174
-{
175
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hd);
176
-}
177
-
178
-static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a)
179
-{
180
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ss);
181
-}
182
-
183
-static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a)
184
-{
185
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ss);
186
-}
187
-
188
-static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a)
189
-{
190
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_sd);
191
-}
192
-
193
-static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a)
194
-{
195
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_sd);
196
-}
197
-
198
-static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a)
199
-{
200
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ds);
201
-}
202
-
203
-static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a)
204
-{
205
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ds);
206
-}
207
-
208
-static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a)
209
-{
210
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_dd);
211
-}
212
-
213
-static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a)
214
-{
215
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd);
216
-}
217
+TRANS_FEAT(FCVTZS_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
218
+ gen_helper_sve_fcvtzs_dd, a, 0, FPST_FPCR)
219
+TRANS_FEAT(FCVTZU_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
220
+ gen_helper_sve_fcvtzu_dd, a, 0, FPST_FPCR)
221
222
static gen_helper_gvec_3_ptr * const frint_fns[] = {
223
NULL,
224
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3_ptr * const frint_fns[] = {
225
gen_helper_sve_frint_s,
226
gen_helper_sve_frint_d
227
};
228
+TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz],
229
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
230
231
-static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)
232
-{
233
- if (a->esz == 0) {
234
- return false;
235
- }
236
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,
237
- frint_fns[a->esz]);
238
-}
239
-
240
-static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)
241
-{
242
- static gen_helper_gvec_3_ptr * const fns[3] = {
243
- gen_helper_sve_frintx_h,
244
- gen_helper_sve_frintx_s,
245
- gen_helper_sve_frintx_d
246
- };
247
- if (a->esz == 0) {
248
- return false;
249
- }
250
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
251
-}
252
+static gen_helper_gvec_3_ptr * const frintx_fns[] = {
253
+ NULL,
254
+ gen_helper_sve_frintx_h,
255
+ gen_helper_sve_frintx_s,
256
+ gen_helper_sve_frintx_d
257
+};
258
+TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
259
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
260
261
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
262
int mode, gen_helper_gvec_3_ptr *fn)
263
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
264
return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
265
}
266
267
-static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)
268
-{
269
- static gen_helper_gvec_3_ptr * const fns[3] = {
270
- gen_helper_sve_frecpx_h,
271
- gen_helper_sve_frecpx_s,
272
- gen_helper_sve_frecpx_d
273
- };
274
- if (a->esz == 0) {
275
- return false;
276
- }
277
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
278
-}
279
+static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
280
+ NULL, gen_helper_sve_frecpx_h,
281
+ gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d,
282
+};
283
+TRANS_FEAT(FRECPX, aa64_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz],
284
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
285
286
-static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a)
287
-{
288
- static gen_helper_gvec_3_ptr * const fns[3] = {
289
- gen_helper_sve_fsqrt_h,
290
- gen_helper_sve_fsqrt_s,
291
- gen_helper_sve_fsqrt_d
292
- };
293
- if (a->esz == 0) {
294
- return false;
295
- }
296
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
297
-}
298
+static gen_helper_gvec_3_ptr * const fsqrt_fns[] = {
299
+ NULL, gen_helper_sve_fsqrt_h,
300
+ gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d,
301
+};
302
+TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz],
303
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
304
305
-static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a)
306
-{
307
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh);
308
-}
309
+TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
310
+ gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16)
311
+TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
312
+ gen_helper_sve_scvt_sh, a, 0, FPST_FPCR_F16)
313
+TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
314
+ gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16)
315
316
-static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a)
317
-{
318
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh);
319
-}
320
+TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
321
+ gen_helper_sve_scvt_ss, a, 0, FPST_FPCR)
322
+TRANS_FEAT(SCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
323
+ gen_helper_sve_scvt_ds, a, 0, FPST_FPCR)
324
325
-static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a)
326
-{
327
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh);
328
-}
329
+TRANS_FEAT(SCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
330
+ gen_helper_sve_scvt_sd, a, 0, FPST_FPCR)
331
+TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
332
+ gen_helper_sve_scvt_dd, a, 0, FPST_FPCR)
333
334
-static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a)
335
-{
336
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss);
337
-}
338
+TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
339
+ gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16)
340
+TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
341
+ gen_helper_sve_ucvt_sh, a, 0, FPST_FPCR_F16)
342
+TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
343
+ gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16)
344
345
-static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a)
346
-{
347
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds);
348
-}
349
+TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
350
+ gen_helper_sve_ucvt_ss, a, 0, FPST_FPCR)
351
+TRANS_FEAT(UCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
352
+ gen_helper_sve_ucvt_ds, a, 0, FPST_FPCR)
353
+TRANS_FEAT(UCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
354
+ gen_helper_sve_ucvt_sd, a, 0, FPST_FPCR)
355
356
-static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a)
357
-{
358
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd);
359
-}
360
-
361
-static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a)
362
-{
363
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd);
364
-}
365
-
366
-static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a)
367
-{
368
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh);
369
-}
370
-
371
-static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a)
372
-{
373
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh);
374
-}
375
-
376
-static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a)
377
-{
378
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh);
379
-}
380
-
381
-static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a)
382
-{
383
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss);
384
-}
385
-
386
-static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a)
387
-{
388
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds);
389
-}
390
-
391
-static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a)
392
-{
393
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd);
394
-}
395
-
396
-static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a)
397
-{
398
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd);
399
-}
400
+TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
401
+ gen_helper_sve_ucvt_dd, a, 0, FPST_FPCR)
402
403
/*
404
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
405
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
406
407
TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
408
409
-static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
410
-{
411
- if (!dc_isar_feature(aa64_sve2, s)) {
412
- return false;
413
- }
414
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_sh);
415
-}
416
+TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz,
417
+ gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR)
418
+TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz,
419
+ gen_helper_sve2_fcvtnt_ds, a, 0, FPST_FPCR)
420
421
-static bool trans_BFCVTNT(DisasContext *s, arg_rpr_esz *a)
422
-{
423
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
424
- return false;
425
- }
426
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvtnt);
427
-}
428
+TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
429
+ gen_helper_sve_bfcvtnt, a, 0, FPST_FPCR)
430
431
-static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a)
432
-{
433
- if (!dc_isar_feature(aa64_sve2, s)) {
434
- return false;
435
- }
436
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_ds);
437
-}
438
-
439
-static bool trans_FCVTLT_hs(DisasContext *s, arg_rpr_esz *a)
440
-{
441
- if (!dc_isar_feature(aa64_sve2, s)) {
442
- return false;
443
- }
444
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_hs);
445
-}
446
-
447
-static bool trans_FCVTLT_sd(DisasContext *s, arg_rpr_esz *a)
448
-{
449
- if (!dc_isar_feature(aa64_sve2, s)) {
450
- return false;
451
- }
452
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_sd);
453
-}
454
+TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
455
+ gen_helper_sve2_fcvtlt_hs, a, 0, FPST_FPCR)
456
+TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
457
+ gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
458
459
static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a)
460
{
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
461
--
166
--
462
2.25.1
167
2.34.1
diff view generated by jsdifflib
[PULL 035/117] target/arm: More use of gen_gvec_fn_arg_zzz
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Two uses of gen_gvec_fn_zzz can pass on arg_rrr_esz instead.
3
The real device advertises this mode and the device model already advertises
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-33-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/translate-sve.c | 4 ++--
13
hw/net/lan9118_phy.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
14
1 file changed, 2 insertions(+), 2 deletions(-)
12
15
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
18
--- a/hw/net/lan9118_phy.c
16
+++ b/target/arm/translate-sve.c
19
+++ b/hw/net/lan9118_phy.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
18
if (!dc_isar_feature(aa64_sve2, s)) {
21
break;
19
return false;
22
case MII_ANAR:
20
}
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
21
- return gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
22
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_mul, a);
25
- MII_ANAR_SELECT))
23
}
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
24
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
25
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
28
| MII_ANAR_TX;
26
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
29
break;
27
if (!dc_isar_feature(aa64_sve2, s)) {
30
case 30: /* Interrupt mask */
28
return false;
29
}
30
- return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
31
+ return gen_gvec_fn_arg_zzz(s, fn, a);
32
}
33
34
static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
35
--
31
--
36
2.25.1
32
2.34.1
diff view generated by jsdifflib
[PULL 092/117] target/arm: Move null function and sve check into do_reduce
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
2
6
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
For the cases where the infzero test in pickNaNMulAdd was
4
Message-id: 20220527181907.189259-90-richard.henderson@linaro.org
8
returning 2, we can delete the check entirely and allow the
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
13
14
For Arm, this looks like it might be a behaviour change because we
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
7
---
37
---
8
target/arm/translate-sve.c | 30 +++++++++++++++++-------------
38
fpu/softfloat-parts.c.inc | 13 +++++++------
9
1 file changed, 17 insertions(+), 13 deletions(-)
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
10
41
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
44
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/translate-sve.c
45
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
16
typedef void gen_helper_fp_reduce(TCGv_i64, TCGv_ptr, TCGv_ptr,
47
int ab_mask, int abc_mask)
17
TCGv_ptr, TCGv_i32);
18
19
-static void do_reduce(DisasContext *s, arg_rpr_esz *a,
20
+static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
21
gen_helper_fp_reduce *fn)
22
{
48
{
23
- unsigned vsz = vec_full_reg_size(s);
49
int which;
24
- unsigned p2vsz = pow2ceil(vsz);
50
+ bool infzero = (ab_mask == float_cmask_infzero);
25
- TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
51
26
+ unsigned vsz, p2vsz;
52
if (unlikely(abc_mask & float_cmask_snan)) {
27
+ TCGv_i32 t_desc;
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
28
TCGv_ptr t_zn, t_pg, status;
54
}
29
TCGv_i64 temp;
55
30
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
31
+ if (fn == NULL) {
57
- ab_mask == float_cmask_infzero, s);
32
+ return false;
58
+ if (infzero) {
33
+ }
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
34
+ if (!sve_access_check(s)) {
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
35
+ return true;
36
+ }
61
+ }
37
+
62
+
38
+ vsz = vec_full_reg_size(s);
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
39
+ p2vsz = pow2ceil(vsz);
64
40
+ t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
65
if (s->default_nan_mode || which == 3) {
41
temp = tcg_temp_new_i64();
66
- /*
42
t_zn = tcg_temp_new_ptr();
67
- * Note that this check is after pickNaNMulAdd so that function
43
t_pg = tcg_temp_new_ptr();
68
- * has an opportunity to set the Invalid flag for infzero.
44
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
69
- */
45
70
parts_default_nan(a, s);
46
write_fp_dreg(s, a->rd, temp);
71
return a;
47
tcg_temp_free_i64(temp);
72
}
48
+ return true;
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
49
}
74
index XXXXXXX..XXXXXXX 100644
50
75
--- a/fpu/softfloat-specialize.c.inc
51
#define DO_VPZ(NAME, name) \
76
+++ b/fpu/softfloat-specialize.c.inc
52
static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
53
{ \
78
* the default NaN
54
- static gen_helper_fp_reduce * const fns[3] = { \
79
*/
55
- gen_helper_sve_##name##_h, \
80
if (infzero && is_qnan(c_cls)) {
56
+ static gen_helper_fp_reduce * const fns[4] = { \
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
57
+ NULL, gen_helper_sve_##name##_h, \
82
return 3;
58
gen_helper_sve_##name##_s, \
83
}
59
gen_helper_sve_##name##_d, \
84
60
}; \
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
61
- if (a->esz == 0) { \
86
* case sets InvalidOp and returns the default NaN
62
- return false; \
87
*/
63
- } \
88
if (infzero) {
64
- if (sve_access_check(s)) { \
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
65
- do_reduce(s, a, fns[a->esz - 1]); \
90
return 3;
66
- } \
91
}
67
- return true; \
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
68
+ return do_reduce(s, a, fns[a->esz]); \
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
69
}
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
70
95
* case sets InvalidOp and returns the input value 'c'
71
DO_VPZ(FADDV, faddv)
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
129
}
130
#elif defined(TARGET_RISCV)
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
132
- if (infzero) {
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
72
--
165
--
73
2.25.1
166
2.34.1
diff view generated by jsdifflib
[PULL 095/117] target/arm: Expand frint_fns for MO_8
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
2
5
3
Simplify indexing of this array. This will allow folding
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
4
of the illegal esz == 0 into the normal fn == NULL check.
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
5
9
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Since RiscV always uses default_nan_mode, this allows us to remove
7
Message-id: 20220527181907.189259-93-richard.henderson@linaro.org
11
its ifdef case from pickNaNMulAdd().
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
10
---
16
---
11
target/arm/translate-sve.c | 15 ++++++++-------
17
fpu/softfloat-parts.c.inc | 8 ++++++--
12
1 file changed, 8 insertions(+), 7 deletions(-)
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
13
20
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
23
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-sve.c
24
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a)
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd);
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
20
}
21
22
-static gen_helper_gvec_3_ptr * const frint_fns[3] = {
23
+static gen_helper_gvec_3_ptr * const frint_fns[] = {
24
+ NULL,
25
gen_helper_sve_frint_h,
26
gen_helper_sve_frint_s,
27
gen_helper_sve_frint_d
28
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)
29
return false;
30
}
27
}
31
return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,
28
32
- frint_fns[a->esz - 1]);
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
33
+ frint_fns[a->esz]);
30
+ if (s->default_nan_mode) {
34
}
31
+ which = 3;
35
32
+ } else {
36
static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
37
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
34
+ }
38
if (a->esz == 0) {
35
39
return false;
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
40
}
41
- return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz - 1]);
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
+ return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
42
index XXXXXXX..XXXXXXX 100644
43
}
43
--- a/fpu/softfloat-specialize.c.inc
44
44
+++ b/fpu/softfloat-specialize.c.inc
45
static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
if (a->esz == 0) {
47
bool infzero, float_status *status)
48
return false;
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
49
}
62
}
50
- return do_frint_mode(s, a, float_round_up, frint_fns[a->esz - 1]);
63
-#elif defined(TARGET_RISCV)
51
+ return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
64
- return 3; /* default NaN */
52
}
65
#elif defined(TARGET_S390X)
53
66
if (infzero) {
54
static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
67
return 3;
55
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
56
if (a->esz == 0) {
57
return false;
58
}
59
- return do_frint_mode(s, a, float_round_down, frint_fns[a->esz - 1]);
60
+ return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
61
}
62
63
static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
64
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
65
if (a->esz == 0) {
66
return false;
67
}
68
- return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz - 1]);
69
+ return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
70
}
71
72
static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
73
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
74
if (a->esz == 0) {
75
return false;
76
}
77
- return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz - 1]);
78
+ return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
79
}
80
81
static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)
82
--
68
--
83
2.25.1
69
2.34.1
diff view generated by jsdifflib
[PULL 013/117] target/arm: Introduce gen_gvec_ool_arg_zzzz
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
From: Richard Henderson <richard.henderson@linaro.org>
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
Use gen_gvec_ool_arg_zzzz instead of gen_gvec_ool_zzzz
3
architectures thus do different things:
4
when the arguments come from arg_rrrr_esz.
4
* some return the default NaN
5
5
* some return the input NaN
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
* Arm returns the default NaN if the input NaN is quiet,
7
Message-id: 20220527181907.189259-11-richard.henderson@linaro.org
7
and the input NaN if it is signalling
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
10
---
33
---
11
target/arm/translate-sve.c | 16 ++++++++++------
34
include/fpu/softfloat-helpers.h | 11 ++++
12
1 file changed, 10 insertions(+), 6 deletions(-)
35
include/fpu/softfloat-types.h | 23 +++++++++
13
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
15
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
41
--- a/include/fpu/softfloat-helpers.h
17
+++ b/target/arm/translate-sve.c
42
+++ b/include/fpu/softfloat-helpers.h
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
19
return true;
44
status->float_2nan_prop_rule = rule;
20
}
45
}
21
46
22
+static bool gen_gvec_ool_arg_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
23
+ arg_rrrr_esz *a, int data)
48
+ float_status *status)
24
+{
49
+{
25
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
50
+ status->float_infzeronan_rule = rule;
26
+}
51
+}
27
+
52
+
28
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
53
static inline void set_flush_to_zero(bool val, float_status *status)
29
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
54
{
30
int rd, int rn, int pg, int data)
55
status->flush_to_zero = val;
31
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
32
if (!dc_isar_feature(aa64_sve2, s)) {
57
return status->float_2nan_prop_rule;
33
return false;
34
}
35
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
36
+ return gen_gvec_ool_arg_zzzz(s, fn, a, data);
37
}
58
}
38
59
39
static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
40
@@ -XXX,XX +XXX,XX @@ static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
61
+{
41
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
62
+ return status->float_infzeronan_rule;
42
return false;
63
+}
43
}
64
+
44
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
65
static inline bool get_flush_to_zero(float_status *status)
45
+ return gen_gvec_ool_arg_zzzz(s, fn, a, data);
66
{
46
}
67
return status->flush_to_zero;
47
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
48
static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
69
index XXXXXXX..XXXXXXX 100644
49
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
70
--- a/include/fpu/softfloat-types.h
50
if (!dc_isar_feature(aa64_sve_bf16, s)) {
71
+++ b/include/fpu/softfloat-types.h
51
return false;
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
52
}
73
float_2nan_prop_x87,
53
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
74
} Float2NaNPropRule;
54
- a->rd, a->rn, a->rm, a->ra, 0);
75
55
+ return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfdot, a, 0);
76
+/*
56
}
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
57
78
+ * This must be a NaN, but implementations differ on whether this
58
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
79
+ * is the input NaN or the default NaN.
59
@@ -XXX,XX +XXX,XX @@ static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
80
+ *
60
if (!dc_isar_feature(aa64_sve_bf16, s)) {
81
+ * You don't need to set this if default_nan_mode is enabled.
61
return false;
82
+ * When not in default-NaN mode, it is an error for the target
62
}
83
+ * not to set the rule in float_status if it uses muladd, and we
63
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
84
+ * will assert if we need to handle an input NaN and no rule was
64
- a->rd, a->rn, a->rm, a->ra, 0);
85
+ * selected.
65
+ return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfmmla, a, 0);
86
+ */
66
}
87
+typedef enum __attribute__((__packed__)) {
67
88
+ /* No propagation rule specified */
68
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
69
--
256
--
70
2.25.1
257
2.34.1
diff view generated by jsdifflib
[PULL 094/117] target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
2
5
3
Rename do_zz_fp to gen_gvec_fpst_arg_zz, and move up.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Split out gen_gvec_fpst_zz as a helper while we're at it.
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
5
13
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
7
Message-id: 20220527181907.189259-92-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 77 ++++++++++++++++++--------------------
12
1 file changed, 36 insertions(+), 41 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
16
--- a/tests/fp/fp-bench.c
17
+++ b/target/arm/translate-sve.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
return true;
19
{
20
}
20
bench_func_t f;
21
21
22
+static bool gen_gvec_fpst_zz(DisasContext *s, gen_helper_gvec_2_ptr *fn,
22
+ /*
23
+ int rd, int rn, int data,
23
+ * These implementation-defined choices for various things IEEE
24
+ ARMFPStatusFlavour flavour)
24
+ * doesn't specify match those used by the Arm architecture.
25
+{
25
+ */
26
+ if (fn == NULL) {
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ return false;
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
+ }
28
29
+ if (sve_access_check(s)) {
29
f = bench_funcs[operation][precision];
30
+ unsigned vsz = vec_full_reg_size(s);
30
g_assert(f);
31
+ TCGv_ptr status = fpstatus_ptr(flavour);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
+
32
index XXXXXXX..XXXXXXX 100644
33
+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
33
--- a/tests/fp/fp-test.c
34
+ vec_full_reg_offset(s, rn),
34
+++ b/tests/fp/fp-test.c
35
+ status, vsz, vsz, data, fn);
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
+ tcg_temp_free_ptr(status);
36
{
37
+ }
37
unsigned int i;
38
+ return true;
38
39
+}
39
+ /*
40
+
40
+ * These implementation-defined choices for various things IEEE
41
+static bool gen_gvec_fpst_arg_zz(DisasContext *s, gen_helper_gvec_2_ptr *fn,
41
+ * doesn't specify match those used by the Arm architecture.
42
+ arg_rr_esz *a, int data)
42
+ */
43
+{
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ return gen_gvec_fpst_zz(s, fn, a->rd, a->rn, data,
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
45
46
+}
46
genCases_setLevel(test_level);
47
+
47
verCases_maxErrorCount = n_max_errors;
48
/* Invoke an out-of-line helper on 3 Zregs. */
49
static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
50
int rd, int rn, int rm, int data)
51
@@ -XXX,XX +XXX,XX @@ DO_VPZ(FMAXV, fmaxv)
52
*** SVE Floating Point Unary Operations - Unpredicated Group
53
*/
54
55
-static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)
56
-{
57
- unsigned vsz = vec_full_reg_size(s);
58
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
59
+static gen_helper_gvec_2_ptr * const frecpe_fns[] = {
60
+ NULL, gen_helper_gvec_frecpe_h,
61
+ gen_helper_gvec_frecpe_s, gen_helper_gvec_frecpe_d,
62
+};
63
+TRANS_FEAT(FRECPE, aa64_sve, gen_gvec_fpst_arg_zz, frecpe_fns[a->esz], a, 0)
64
65
- tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),
66
- vec_full_reg_offset(s, a->rn),
67
- status, vsz, vsz, 0, fn);
68
- tcg_temp_free_ptr(status);
69
-}
70
-
71
-static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a)
72
-{
73
- static gen_helper_gvec_2_ptr * const fns[3] = {
74
- gen_helper_gvec_frecpe_h,
75
- gen_helper_gvec_frecpe_s,
76
- gen_helper_gvec_frecpe_d,
77
- };
78
- if (a->esz == 0) {
79
- return false;
80
- }
81
- if (sve_access_check(s)) {
82
- do_zz_fp(s, a, fns[a->esz - 1]);
83
- }
84
- return true;
85
-}
86
-
87
-static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a)
88
-{
89
- static gen_helper_gvec_2_ptr * const fns[3] = {
90
- gen_helper_gvec_frsqrte_h,
91
- gen_helper_gvec_frsqrte_s,
92
- gen_helper_gvec_frsqrte_d,
93
- };
94
- if (a->esz == 0) {
95
- return false;
96
- }
97
- if (sve_access_check(s)) {
98
- do_zz_fp(s, a, fns[a->esz - 1]);
99
- }
100
- return true;
101
-}
102
+static gen_helper_gvec_2_ptr * const frsqrte_fns[] = {
103
+ NULL, gen_helper_gvec_frsqrte_h,
104
+ gen_helper_gvec_frsqrte_s, gen_helper_gvec_frsqrte_d,
105
+};
106
+TRANS_FEAT(FRSQRTE, aa64_sve, gen_gvec_fpst_arg_zz, frsqrte_fns[a->esz], a, 0)
107
108
/*
109
*** SVE Floating Point Compare with Zero Group
110
--
48
--
111
2.25.1
49
2.34.1
diff view generated by jsdifflib
[PULL 093/117] target/arm: Use TRANS_FEAT for do_reduce
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-91-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 14 ++++++--------
8
target/arm/cpu.c | 3 +++
9
1 file changed, 6 insertions(+), 8 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/arm/cpu.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/arm/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
21
+ * and the input NaN if it is signalling
22
*/
23
static void arm_set_default_fp_behaviours(float_status *s)
24
{
25
set_float_detect_tininess(float_tininess_before_rounding, s);
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
16
}
28
}
17
29
18
#define DO_VPZ(NAME, name) \
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
19
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
20
-{ \
32
index XXXXXXX..XXXXXXX 100644
21
- static gen_helper_fp_reduce * const fns[4] = { \
33
--- a/fpu/softfloat-specialize.c.inc
22
- NULL, gen_helper_sve_##name##_h, \
34
+++ b/fpu/softfloat-specialize.c.inc
23
- gen_helper_sve_##name##_s, \
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
24
- gen_helper_sve_##name##_d, \
36
/*
25
+ static gen_helper_fp_reduce * const name##_fns[4] = { \
37
* Temporarily fall back to ifdef ladder
26
+ NULL, gen_helper_sve_##name##_h, \
38
*/
27
+ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
39
-#if defined(TARGET_ARM)
28
}; \
40
- /*
29
- return do_reduce(s, a, fns[a->esz]); \
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
30
-}
42
- * but (inf,zero,snan) returns the input NaN.
31
+ TRANS_FEAT(NAME, aa64_sve, do_reduce, a, name##_fns[a->esz])
43
- */
32
44
- rule = float_infzeronan_dnan_if_qnan;
33
DO_VPZ(FADDV, faddv)
45
-#elif defined(TARGET_MIPS)
34
DO_VPZ(FMINNMV, fminnmv)
46
+#if defined(TARGET_MIPS)
35
@@ -XXX,XX +XXX,XX @@ DO_VPZ(FMAXNMV, fmaxnmv)
47
if (snan_bit_is_one(status)) {
36
DO_VPZ(FMINV, fminv)
48
/*
37
DO_VPZ(FMAXV, fmaxv)
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
38
39
+#undef DO_VPZ
40
+
41
/*
42
*** SVE Floating Point Unary Operations - Unpredicated Group
43
*/
44
--
50
--
45
2.25.1
51
2.34.1
diff view generated by jsdifflib
[PULL 097/117] target/arm: Move null function and sve check into do_frint_mode
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-95-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 52 +++++++++++++++++---------------------
8
target/s390x/cpu.c | 2 ++
9
1 file changed, 23 insertions(+), 29 deletions(-)
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/s390x/cpu.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/s390x/cpu.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
16
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
17
set_float_detect_tininess(float_tininess_before_rounding,
17
int mode, gen_helper_gvec_3_ptr *fn)
18
&env->fpu_status);
18
{
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
19
- if (sve_access_check(s)) {
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
20
- unsigned vsz = vec_full_reg_size(s);
21
+ &env->fpu_status);
21
- TCGv_i32 tmode = tcg_const_i32(mode);
22
/* fall through */
22
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
23
case RESET_TYPE_S390_CPU_NORMAL:
23
+ unsigned vsz;
24
env->psw.mask &= ~PSW_MASK_RI;
24
+ TCGv_i32 tmode;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
+ TCGv_ptr status;
26
index XXXXXXX..XXXXXXX 100644
26
27
--- a/fpu/softfloat-specialize.c.inc
27
- gen_helper_set_rmode(tmode, tmode, status);
28
+++ b/fpu/softfloat-specialize.c.inc
28
-
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
30
* a default NaN
30
- vec_full_reg_offset(s, a->rn),
31
*/
31
- pred_full_reg_offset(s, a->pg),
32
rule = float_infzeronan_dnan_never;
32
- status, vsz, vsz, 0, fn);
33
-#elif defined(TARGET_S390X)
33
-
34
- rule = float_infzeronan_dnan_always;
34
- gen_helper_set_rmode(tmode, tmode, status);
35
#endif
35
- tcg_temp_free_i32(tmode);
36
- tcg_temp_free_ptr(status);
37
+ if (fn == NULL) {
38
+ return false;
39
}
36
}
40
+ if (!sve_access_check(s)) {
41
+ return true;
42
+ }
43
+
44
+ vsz = vec_full_reg_size(s);
45
+ tmode = tcg_const_i32(mode);
46
+ status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
47
+
48
+ gen_helper_set_rmode(tmode, tmode, status);
49
+
50
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
51
+ vec_full_reg_offset(s, a->rn),
52
+ pred_full_reg_offset(s, a->pg),
53
+ status, vsz, vsz, 0, fn);
54
+
55
+ gen_helper_set_rmode(tmode, tmode, status);
56
+ tcg_temp_free_i32(tmode);
57
+ tcg_temp_free_ptr(status);
58
return true;
59
}
60
61
static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
62
{
63
- if (a->esz == 0) {
64
- return false;
65
- }
66
return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
67
}
68
69
static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
70
{
71
- if (a->esz == 0) {
72
- return false;
73
- }
74
return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
75
}
76
77
static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
78
{
79
- if (a->esz == 0) {
80
- return false;
81
- }
82
return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
83
}
84
85
static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
86
{
87
- if (a->esz == 0) {
88
- return false;
89
- }
90
return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
91
}
92
93
static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
94
{
95
- if (a->esz == 0) {
96
- return false;
97
- }
98
return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
99
}
100
37
101
--
38
--
102
2.25.1
39
2.34.1
diff view generated by jsdifflib
[PULL 091/117] target/arm: Use TRANS_FEAT for FTMAD
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-89-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 29 +++++++----------------------
8
target/ppc/cpu_init.c | 7 +++++++
9
1 file changed, 7 insertions(+), 22 deletions(-)
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/ppc/cpu_init.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/ppc/cpu_init.c
15
@@ -XXX,XX +XXX,XX @@ DO_PPZ(FCMNE_ppz0, fcmne0)
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
16
*** SVE floating-point trig multiply-add coefficient
17
*/
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
18
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
19
-static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a)
20
+ /*
20
-{
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
21
- static gen_helper_gvec_3_ptr * const fns[3] = {
22
+ * to return an input NaN if we have one (ie c) rather than generating
22
- gen_helper_sve_ftmad_h,
23
+ * a default NaN
23
- gen_helper_sve_ftmad_s,
24
+ */
24
- gen_helper_sve_ftmad_d,
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
25
- };
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
26
-
27
27
- if (a->esz == 0) {
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
28
- return false;
29
ppc_spr_t *spr = &env->spr_cb[i];
29
- }
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
- if (sve_access_check(s)) {
31
index XXXXXXX..XXXXXXX 100644
31
- unsigned vsz = vec_full_reg_size(s);
32
--- a/fpu/softfloat-specialize.c.inc
32
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
33
+++ b/fpu/softfloat-specialize.c.inc
33
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
- vec_full_reg_offset(s, a->rn),
35
*/
35
- vec_full_reg_offset(s, a->rm),
36
rule = float_infzeronan_dnan_never;
36
- status, vsz, vsz, a->imm, fns[a->esz - 1]);
37
}
37
- tcg_temp_free_ptr(status);
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
38
- }
39
+#elif defined(TARGET_SPARC) || \
39
- return true;
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
40
-}
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
41
+static gen_helper_gvec_3_ptr * const ftmad_fns[4] = {
42
/*
42
+ NULL, gen_helper_sve_ftmad_h,
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
43
+ gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d,
44
* case sets InvalidOp and returns the input value 'c'
44
+};
45
*/
45
+TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
46
- /*
46
+ ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
47
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
48
- * to return an input NaN if we have one (ie c) rather than generating
48
49
- * a default NaN
49
/*
50
- */
50
*** SVE Floating Point Accumulating Reduction Group
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
51
--
54
--
52
2.25.1
55
2.34.1
diff view generated by jsdifflib
[PULL 088/117] target/arm: Rename do_zzz_fp to gen_gvec_ool_fpst_arg_zzz
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
Rename the function to match gen_gvec_ool_arg_zzz,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
and move to be adjacent. Split out gen_gvec_fpst_zzz
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
as a helper while we're at it.
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
6
12
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
8
Message-id: 20220527181907.189259-86-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 50 +++++++++++++++++++++++---------------
13
1 file changed, 30 insertions(+), 20 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
15
--- a/target/mips/fpu_helper.h
18
+++ b/target/arm/translate-sve.c
16
+++ b/target/mips/fpu_helper.h
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
20
return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
21
}
37
}
22
38
23
+/* Invoke an out-of-line helper on 3 Zregs, plus float_status. */
39
static inline void restore_fp_status(CPUMIPSState *env)
24
+static bool gen_gvec_fpst_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
25
+ int rd, int rn, int rm,
41
index XXXXXXX..XXXXXXX 100644
26
+ int data, ARMFPStatusFlavour flavour)
42
--- a/target/mips/msa.c
27
+{
43
+++ b/target/mips/msa.c
28
+ if (fn == NULL) {
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
29
+ return false;
45
30
+ }
46
/* set proper signanling bit meaning ("1" means "quiet") */
31
+ if (sve_access_check(s)) {
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ TCGv_ptr status = fpstatus_ptr(flavour);
34
+
48
+
35
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
49
+ /* Inf * 0 + NaN returns the input NaN */
36
+ vec_full_reg_offset(s, rn),
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
37
+ vec_full_reg_offset(s, rm),
51
+ &env->active_tc.msa_fp_status);
38
+ status, vsz, vsz, data, fn);
39
+
40
+ tcg_temp_free_ptr(status);
41
+ }
42
+ return true;
43
+}
44
+
45
+static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
46
+ arg_rrr_esz *a, int data)
47
+{
48
+ return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data,
49
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
50
+}
51
+
52
/* Invoke an out-of-line helper on 4 Zregs. */
53
static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
54
int rd, int rn, int rm, int ra, int data)
55
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
56
*** SVE Floating Point Arithmetic - Unpredicated Group
57
*/
58
59
-static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a,
60
- gen_helper_gvec_3_ptr *fn)
61
-{
62
- if (fn == NULL) {
63
- return false;
64
- }
65
- if (sve_access_check(s)) {
66
- unsigned vsz = vec_full_reg_size(s);
67
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
68
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
69
- vec_full_reg_offset(s, a->rn),
70
- vec_full_reg_offset(s, a->rm),
71
- status, vsz, vsz, 0, fn);
72
- tcg_temp_free_ptr(status);
73
- }
74
- return true;
75
-}
76
-
77
-
78
#define DO_FP3(NAME, name) \
79
static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
80
{ \
81
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
82
NULL, gen_helper_gvec_##name##_h, \
83
gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \
84
}; \
85
- return do_zzz_fp(s, a, fns[a->esz]); \
86
+ return gen_gvec_fpst_arg_zzz(s, fns[a->esz], a, 0); \
87
}
52
}
88
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
89
DO_FP3(FADD_zzz, fadd)
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
90
--
80
--
91
2.25.1
81
2.34.1
diff view generated by jsdifflib
[PULL 090/117] target/arm: Use TRANS_FEAT for FMUL_zzx
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-88-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 26 +++++++-------------------
8
target/sparc/cpu.c | 2 ++
9
1 file changed, 7 insertions(+), 19 deletions(-)
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/sparc/cpu.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/sparc/cpu.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMLS_zzxz, aa64_sve, do_FMLA_zzxz, a, true)
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
16
*** SVE Floating Point Multiply Indexed Group
17
* the CPU state struct so it won't get zeroed on reset.
17
*/
18
*/
18
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
19
-static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a)
20
+ /* For inf * 0 + NaN, return the input NaN */
20
-{
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
21
- static gen_helper_gvec_3_ptr * const fns[3] = {
22
22
- gen_helper_gvec_fmul_idx_h,
23
cpu_exec_realizefn(cs, &local_err);
23
- gen_helper_gvec_fmul_idx_s,
24
if (local_err != NULL) {
24
- gen_helper_gvec_fmul_idx_d,
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
- };
26
index XXXXXXX..XXXXXXX 100644
26
-
27
--- a/fpu/softfloat-specialize.c.inc
27
- if (sve_access_check(s)) {
28
+++ b/fpu/softfloat-specialize.c.inc
28
- unsigned vsz = vec_full_reg_size(s);
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
30
/*
30
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
31
* Temporarily fall back to ifdef ladder
31
- vec_full_reg_offset(s, a->rn),
32
*/
32
- vec_full_reg_offset(s, a->rm),
33
-#if defined(TARGET_SPARC) || \
33
- status, vsz, vsz, a->index, fns[a->esz - 1]);
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
- tcg_temp_free_ptr(status);
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
- }
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
- return true;
37
/*
37
-}
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
+static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = {
39
+ NULL, gen_helper_gvec_fmul_idx_h,
40
+ gen_helper_gvec_fmul_idx_s, gen_helper_gvec_fmul_idx_d,
41
+};
42
+TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
43
+ fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index,
44
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
45
46
/*
47
*** SVE Floating Point Fast Reduction Group
48
--
39
--
49
2.25.1
40
2.34.1
diff view generated by jsdifflib
[PULL 089/117] target/arm: Use TRANS_FEAT for DO_FP3
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-87-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 7 ++-----
8
target/xtensa/cpu.c | 2 ++
9
1 file changed, 2 insertions(+), 5 deletions(-)
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/xtensa/cpu.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/xtensa/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
16
*/
17
reset_mmu(env);
17
18
cs->halted = env->runstall;
18
#define DO_FP3(NAME, name) \
19
#endif
19
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
20
+ /* For inf * 0 + NaN, return the input NaN */
20
-{ \
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
21
- static gen_helper_gvec_3_ptr * const fns[4] = { \
22
set_no_signaling_nans(!dfpu, &env->fp_status);
22
+ static gen_helper_gvec_3_ptr * const name##_fns[4] = { \
23
xtensa_use_first_nan(env, !dfpu);
23
NULL, gen_helper_gvec_##name##_h, \
24
}
24
gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
}; \
26
index XXXXXXX..XXXXXXX 100644
26
- return gen_gvec_fpst_arg_zzz(s, fns[a->esz], a, 0); \
27
--- a/fpu/softfloat-specialize.c.inc
27
-}
28
+++ b/fpu/softfloat-specialize.c.inc
28
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_arg_zzz, name##_fns[a->esz], a, 0)
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
30
/*
30
DO_FP3(FADD_zzz, fadd)
31
* Temporarily fall back to ifdef ladder
31
DO_FP3(FSUB_zzz, fsub)
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
32
--
38
--
33
2.25.1
39
2.34.1
diff view generated by jsdifflib
[PULL 087/117] target/arm: Use TRANS_FEAT for BFMLA
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-85-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 28 ++++------------------------
7
target/i386/tcg/fpu_helper.c | 7 +++++++
9
1 file changed, 4 insertions(+), 24 deletions(-)
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
16
*/
17
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
{
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
19
+ /*
20
- return false;
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
- }
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal,
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
a->rd, a->rn, a->rm, a->ra, sel, FPST_FPCR);
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
24
}
26
}
25
27
26
-static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
28
static inline uint8_t save_exception_flags(CPUX86State *env)
27
-{
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
- return do_BFMLAL_zzzw(s, a, false);
30
index XXXXXXX..XXXXXXX 100644
29
-}
31
--- a/fpu/softfloat-specialize.c.inc
30
-
32
+++ b/fpu/softfloat-specialize.c.inc
31
-static bool trans_BFMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
-{
34
* Temporarily fall back to ifdef ladder
33
- return do_BFMLAL_zzzw(s, a, true);
35
*/
34
-}
36
#if defined(TARGET_HPPA) || \
35
+TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false)
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
+TRANS_FEAT(BFMLALT_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, true)
38
+ defined(TARGET_LOONGARCH)
37
39
/*
38
static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
{
41
* case sets InvalidOp and returns the input value 'c'
40
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
41
- return false;
42
- }
43
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx,
44
a->rd, a->rn, a->rm, a->ra,
45
(a->index << 1) | sel, FPST_FPCR);
46
}
47
48
-static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
49
-{
50
- return do_BFMLAL_zzxw(s, a, false);
51
-}
52
-
53
-static bool trans_BFMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a)
54
-{
55
- return do_BFMLAL_zzxw(s, a, true);
56
-}
57
+TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
58
+TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true)
59
--
42
--
60
2.25.1
43
2.34.1
diff view generated by jsdifflib
[PULL 086/117] target/arm: Use TRANS_FEAT for FMLA
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-84-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 11 ++---------
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
9
1 file changed, 2 insertions(+), 9 deletions(-)
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub)
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
}
24
}
18
25
19
-static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
26
int ieee_ex_to_loongarch(int xcpt)
20
-{
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
21
- return do_FMLA_zzxz(s, a, false);
28
index XXXXXXX..XXXXXXX 100644
22
-}
29
--- a/fpu/softfloat-specialize.c.inc
23
-
30
+++ b/fpu/softfloat-specialize.c.inc
24
-static bool trans_FMLS_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
25
-{
32
/*
26
- return do_FMLA_zzxz(s, a, true);
33
* Temporarily fall back to ifdef ladder
27
-}
34
*/
28
+TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false)
35
-#if defined(TARGET_HPPA) || \
29
+TRANS_FEAT(FMLS_zzxz, aa64_sve, do_FMLA_zzxz, a, true)
36
- defined(TARGET_LOONGARCH)
30
37
- /*
31
/*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
32
*** SVE Floating Point Multiply Indexed Group
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
33
--
45
--
34
2.25.1
46
2.34.1
diff view generated by jsdifflib
[PULL 079/117] target/arm: Use TRANS_FEAT for do_zzi_ool
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
As this is the last target to be converted to explicitly setting
4
Message-id: 20220527181907.189259-77-richard.henderson@linaro.org
5
the rule, we can remove the fallback code in pickNaNMulAdd()
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
entirely.
7
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
7
---
11
---
8
target/arm/translate-sve.c | 7 ++-----
12
target/hppa/fpu_helper.c | 2 ++
9
1 file changed, 2 insertions(+), 5 deletions(-)
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
10
15
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
18
--- a/target/hppa/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
19
+++ b/target/hppa/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
16
}
26
}
17
27
18
#define DO_ZZI(NAME, name) \
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
19
-static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a) \
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
20
-{ \
30
index XXXXXXX..XXXXXXX 100644
21
- static gen_helper_gvec_2i * const fns[4] = { \
31
--- a/fpu/softfloat-specialize.c.inc
22
+ static gen_helper_gvec_2i * const name##i_fns[4] = { \
32
+++ b/fpu/softfloat-specialize.c.inc
23
gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
24
gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
25
}; \
35
bool infzero, float_status *status)
26
- return do_zzi_ool(s, a, fns[a->esz]); \
36
{
27
-}
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
28
+ TRANS_FEAT(NAME##_zzi, aa64_sve, do_zzi_ool, a, name##i_fns[a->esz])
38
-
29
39
/*
30
DO_ZZI(SMAX, smax)
40
* We guarantee not to require the target to tell us how to
31
DO_ZZI(UMAX, umax)
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
32
--
65
--
33
2.25.1
66
2.34.1
diff view generated by jsdifflib
[PULL 085/117] target/arm: Use TRANS_FEAT for MOVPRFX
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-83-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
7
---
9
---
8
target/arm/translate-sve.c | 17 +++--------------
10
fpu/softfloat-parts.c.inc | 5 +++--
9
1 file changed, 3 insertions(+), 14 deletions(-)
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
10
13
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
16
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/translate-sve.c
17
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
16
* In the meantime, just emit the moves.
19
{
17
*/
20
int which;
18
21
bool infzero = (ab_mask == float_cmask_infzero);
19
-static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a)
22
+ bool have_snan = (abc_mask & float_cmask_snan);
20
-{
23
21
- return do_mov_z(s, a->rd, a->rn);
24
- if (unlikely(abc_mask & float_cmask_snan)) {
22
-}
25
+ if (unlikely(have_snan)) {
23
-
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
24
-static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
27
}
25
-{
28
26
- return do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
27
-}
30
if (s->default_nan_mode) {
28
-
31
which = 3;
29
-static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
32
} else {
30
-{
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
31
- return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
32
-}
35
}
33
+TRANS_FEAT(MOVPRFX, aa64_sve, do_mov_z, a->rd, a->rn)
36
34
+TRANS_FEAT(MOVPRFX_m, aa64_sve, do_sel_z, a->rd, a->rn, a->rd, a->pg, a->esz)
37
if (which == 3) {
35
+TRANS_FEAT(MOVPRFX_z, aa64_sve, do_movz_zpz, a->rd, a->rn, a->pg, a->esz, false)
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
39
index XXXXXXX..XXXXXXX 100644
37
/*
40
--- a/fpu/softfloat-specialize.c.inc
38
* SVE2 Integer Multiply - Unpredicated
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
39
--
51
--
40
2.25.1
52
2.34.1
diff view generated by jsdifflib
[PULL 016/117] target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
Rename the function to match gen_gvec_ool_arg_zzzz,
3
are NaNs. As a result different architectures have ended up with
4
and move to be adjacent.
4
different rules for propagating NaNs.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
Message-id: 20220527181907.189259-14-richard.henderson@linaro.org
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
We want to make the propagation rule instead be selectable at
9
runtime, because:
10
* this will let us have multiple targets in one QEMU binary
11
* the Arm FEAT_AFP architectural feature includes letting
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
10
---
27
---
11
target/arm/translate-sve.c | 18 +++++++++---------
28
include/fpu/softfloat-helpers.h | 11 +++
12
1 file changed, 9 insertions(+), 9 deletions(-)
29
include/fpu/softfloat-types.h | 55 +++++++++++
13
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
15
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
35
--- a/include/fpu/softfloat-helpers.h
17
+++ b/target/arm/translate-sve.c
36
+++ b/include/fpu/softfloat-helpers.h
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
19
return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
38
status->float_2nan_prop_rule = rule;
20
}
39
}
21
40
22
+static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
23
+ arg_rrxr_esz *a)
42
+ float_status *status)
24
+{
43
+{
25
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
44
+ status->float_3nan_prop_rule = rule;
26
+}
45
+}
27
+
46
+
28
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
29
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
48
float_status *status)
30
int rd, int rn, int pg, int data)
49
{
31
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
32
* SVE Multiply - Indexed
51
return status->float_2nan_prop_rule;
52
}
53
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
55
+{
56
+ return status->float_3nan_prop_rule;
57
+}
58
+
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
60
{
61
return status->float_infzeronan_rule;
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
71
+
72
/*
73
* Software IEC/IEEE floating-point types.
33
*/
74
*/
34
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
35
-static bool do_zzxz_ool(DisasContext *s, arg_rrxr_esz *a,
76
float_2nan_prop_x87,
36
- gen_helper_gvec_4 *fn)
77
} Float2NaNPropRule;
37
-{
78
38
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
79
+/*
39
-}
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
158
}
159
}
160
161
+ if (rule == float_3nan_prop_none) {
162
#if defined(TARGET_ARM)
40
-
163
-
41
#define DO_RRXR(NAME, FUNC) \
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
42
static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
43
- { return do_zzxz_ool(s, a, FUNC); }
166
- */
44
+ { return gen_gvec_ool_arg_zzxz(s, FUNC, a); }
167
- if (is_snan(c_cls)) {
45
168
- return 2;
46
DO_RRXR(trans_SDOT_zzxw_s, gen_helper_gvec_sdot_idx_b)
169
- } else if (is_snan(a_cls)) {
47
DO_RRXR(trans_SDOT_zzxw_d, gen_helper_gvec_sdot_idx_h)
170
- return 0;
48
@@ -XXX,XX +XXX,XX @@ static bool trans_SUDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
171
- } else if (is_snan(b_cls)) {
49
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
172
- return 1;
50
return false;
173
- } else if (is_qnan(c_cls)) {
51
}
174
- return 2;
52
- return do_zzxz_ool(s, a, gen_helper_gvec_sudot_idx_b);
175
- } else if (is_qnan(a_cls)) {
53
+ return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_sudot_idx_b, a);
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
321
+ }
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
54
}
337
}
55
338
56
static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
339
/*----------------------------------------------------------------------------
57
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
58
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
59
return false;
60
}
61
- return do_zzxz_ool(s, a, gen_helper_gvec_usdot_idx_b);
62
+ return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_usdot_idx_b, a);
63
}
64
65
#undef DO_RRXR
66
--
340
--
67
2.25.1
341
2.34.1
diff view generated by jsdifflib
[PULL 084/117] target/arm: Use TRANS_FEAT for SEL_zpzz
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
2
4
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-82-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
7
---
8
---
8
target/arm/translate-sve.c | 5 +----
9
tests/fp/fp-bench.c | 1 +
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
10
12
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
15
--- a/tests/fp/fp-bench.c
14
+++ b/target/arm/translate-sve.c
16
+++ b/tests/fp/fp-bench.c
15
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_4 * const udiv_fns[4] = {
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
16
};
18
* doesn't specify match those used by the Arm architecture.
17
TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
19
*/
18
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
19
-static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
20
-{
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
21
- return do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
23
22
-}
24
f = bench_funcs[operation][precision];
23
+TRANS_FEAT(SEL_zpzz, aa64_sve, do_sel_z, a->rd, a->rn, a->rm, a->pg, a->esz)
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
24
26
index XXXXXXX..XXXXXXX 100644
25
/*
27
--- a/tests/fp/fp-test.c
26
*** SVE Integer Arithmetic - Unary Predicated Group
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
27
--
37
--
28
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 078/117] target/arm: Use TRANS_FEAT for do_zzi_sat
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-76-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 23 ++++-------------------
8
target/arm/cpu.c | 5 +++++
9
1 file changed, 4 insertions(+), 19 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/arm/cpu.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/arm/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
16
return true;
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
17
}
33
}
18
34
19
-static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a)
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
20
-{
36
index XXXXXXX..XXXXXXX 100644
21
- return do_zzi_sat(s, a, false, false);
37
--- a/fpu/softfloat-specialize.c.inc
22
-}
38
+++ b/fpu/softfloat-specialize.c.inc
23
-
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
24
-static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a)
40
}
25
-{
41
26
- return do_zzi_sat(s, a, true, false);
42
if (rule == float_3nan_prop_none) {
27
-}
43
-#if defined(TARGET_ARM)
28
-
44
- /*
29
-static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a)
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
30
-{
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
31
- return do_zzi_sat(s, a, false, true);
47
- */
32
-}
48
- rule = float_3nan_prop_s_cab;
33
-
49
-#elif defined(TARGET_MIPS)
34
-static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a)
50
+#if defined(TARGET_MIPS)
35
-{
51
if (snan_bit_is_one(status)) {
36
- return do_zzi_sat(s, a, true, true);
52
rule = float_3nan_prop_s_abc;
37
-}
53
} else {
38
+TRANS_FEAT(SQADD_zzi, aa64_sve, do_zzi_sat, a, false, false)
39
+TRANS_FEAT(UQADD_zzi, aa64_sve, do_zzi_sat, a, true, false)
40
+TRANS_FEAT(SQSUB_zzi, aa64_sve, do_zzi_sat, a, false, true)
41
+TRANS_FEAT(UQSUB_zzi, aa64_sve, do_zzi_sat, a, true, true)
42
43
static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
44
{
45
--
54
--
46
2.25.1
55
2.34.1
diff view generated by jsdifflib
[PULL 077/117] target/arm: Use TRANS_FEAT for ADD_zzi
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-75-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 5 +----
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
1 file changed, 1 insertion(+), 4 deletions(-)
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
return true;
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
17
}
21
}
18
22
19
-static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
23
int ieee_ex_to_loongarch(int xcpt)
20
-{
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
21
- return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
25
index XXXXXXX..XXXXXXX 100644
22
-}
26
--- a/fpu/softfloat-specialize.c.inc
23
+TRANS_FEAT(ADD_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_addi, a)
27
+++ b/fpu/softfloat-specialize.c.inc
24
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
25
static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a)
29
} else {
26
{
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
27
--
37
--
28
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 076/117] target/arm: Reject copy w/ shifted byte early
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Remove the unparsed extractions in trans_CPY_{m,z}_i which are intended
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
to reject an 8-bit shift of an 8-bit constant for 8-bit element.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
5
11
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
7
Message-id: 20220527181907.189259-74-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/sve.decode | 10 ++++++++--
12
target/arm/translate-sve.c | 6 ------
13
2 files changed, 8 insertions(+), 8 deletions(-)
14
15
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve.decode
14
--- a/target/ppc/cpu_init.c
18
+++ b/target/arm/sve.decode
15
+++ b/target/ppc/cpu_init.c
19
@@ -XXX,XX +XXX,XX @@ DUPM 00000101 11 0000 dbm:13 rd:5
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
20
FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
17
*/
21
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
22
# SVE copy integer immediate (predicated)
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
23
-CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
20
+ /*
24
-CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
21
+ * NaN propagation for fused multiply-add:
25
+{
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
26
+ INVALID 00000101 00 01 ---- 01 1 -------- -----
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
27
+ CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
24
+ * whereas QEMU labels the operands as (a * b) + c.
28
+}
25
+ */
29
+{
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
30
+ INVALID 00000101 00 01 ---- 00 1 -------- -----
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
31
+ CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
28
/*
32
+}
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
33
30
* to return an input NaN if we have one (ie c) rather than generating
34
### SVE Permute - Extract Group
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
35
36
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
37
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/translate-sve.c
33
--- a/fpu/softfloat-specialize.c.inc
39
+++ b/target/arm/translate-sve.c
34
+++ b/fpu/softfloat-specialize.c.inc
40
@@ -XXX,XX +XXX,XX @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
41
36
} else {
42
static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a)
37
rule = float_3nan_prop_s_cab;
43
{
38
}
44
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
39
-#elif defined(TARGET_PPC)
45
- return false;
40
- /*
46
- }
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
47
if (sve_access_check(s)) {
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
48
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm));
43
- */
49
}
44
- rule = float_3nan_prop_acb;
50
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
45
#elif defined(TARGET_S390X)
51
gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d,
46
rule = float_3nan_prop_s_abc;
52
};
47
#elif defined(TARGET_SPARC)
53
54
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
55
- return false;
56
- }
57
if (sve_access_check(s)) {
58
unsigned vsz = vec_full_reg_size(s);
59
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
60
--
48
--
61
2.25.1
49
2.34.1
diff view generated by jsdifflib
[PULL 075/117] target/arm: Reject add/sub w/ shifted byte early
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Remove the unparsed extractions in trans_ADD_zzi, trans_SUBR_zzi,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
and do_zzi_sat which are intended to reject an 8-bit shift of an
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
8-bit constant for 8-bit element.
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
6
11
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
8
Message-id: 20220527181907.189259-73-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sve.decode | 35 ++++++++++++++++++++++++++++-------
13
target/arm/translate-sve.c | 9 ---------
14
2 files changed, 28 insertions(+), 16 deletions(-)
15
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve.decode
14
--- a/target/s390x/cpu.c
19
+++ b/target/arm/sve.decode
15
+++ b/target/s390x/cpu.c
20
@@ -XXX,XX +XXX,XX @@ FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
21
}
17
set_float_detect_tininess(float_tininess_before_rounding,
22
18
&env->fpu_status);
23
# SVE integer add/subtract immediate (unpredicated)
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
24
-ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
25
-SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
26
-SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
22
&env->fpu_status);
27
-SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
23
/* fall through */
28
-UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
29
-SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
30
-UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
31
+{
32
+ INVALID 00100101 00 100 000 11 1 -------- -----
33
+ ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
34
+}
35
+{
36
+ INVALID 00100101 00 100 001 11 1 -------- -----
37
+ SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
38
+}
39
+{
40
+ INVALID 00100101 00 100 011 11 1 -------- -----
41
+ SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
42
+}
43
+{
44
+ INVALID 00100101 00 100 100 11 1 -------- -----
45
+ SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
46
+}
47
+{
48
+ INVALID 00100101 00 100 101 11 1 -------- -----
49
+ UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
50
+}
51
+{
52
+ INVALID 00100101 00 100 110 11 1 -------- -----
53
+ SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
54
+}
55
+{
56
+ INVALID 00100101 00 100 111 11 1 -------- -----
57
+ UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
58
+}
59
60
# SVE integer min/max immediate (unpredicated)
61
SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
62
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
63
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/translate-sve.c
26
--- a/fpu/softfloat-specialize.c.inc
65
+++ b/target/arm/translate-sve.c
27
+++ b/fpu/softfloat-specialize.c.inc
66
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
67
29
} else {
68
static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
30
rule = float_3nan_prop_s_cab;
69
{
31
}
70
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
32
-#elif defined(TARGET_S390X)
71
- return false;
33
- rule = float_3nan_prop_s_abc;
72
- }
34
#elif defined(TARGET_SPARC)
73
return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
35
rule = float_3nan_prop_s_cba;
74
}
36
#elif defined(TARGET_XTENSA)
75
76
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
77
.scalar_first = true }
78
};
79
80
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
81
- return false;
82
- }
83
if (sve_access_check(s)) {
84
unsigned vsz = vec_full_reg_size(s);
85
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
86
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a)
87
88
static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
89
{
90
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
91
- return false;
92
- }
93
if (sve_access_check(s)) {
94
do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
95
tcg_constant_i64(a->imm), u, d);
96
--
37
--
97
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 074/117] target/arm: Reject dup_i w/ shifted byte early
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Remove the unparsed extraction in trans_DUP_i,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
which is intended to reject an 8-bit shift of
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
an 8-bit constant for 8-bit element.
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
6
11
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
8
Message-id: 20220527181907.189259-72-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sve.decode | 5 ++++-
13
target/arm/translate-sve.c | 10 ++++++----
14
2 files changed, 10 insertions(+), 5 deletions(-)
15
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve.decode
14
--- a/target/sparc/cpu.c
19
+++ b/target/arm/sve.decode
15
+++ b/target/sparc/cpu.c
20
@@ -XXX,XX +XXX,XX @@ WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
21
FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
17
* the CPU state struct so it won't get zeroed on reset.
22
18
*/
23
# SVE broadcast integer immediate (unpredicated)
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
24
-DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
25
+{
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
26
+ INVALID 00100101 00 111 00 011 1 -------- -----
22
/* For inf * 0 + NaN, return the input NaN */
27
+ DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
28
+}
24
29
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
# SVE integer add/subtract immediate (unpredicated)
31
ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
32
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate-sve.c
27
--- a/fpu/softfloat-specialize.c.inc
35
+++ b/target/arm/translate-sve.c
28
+++ b/fpu/softfloat-specialize.c.inc
36
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
37
0x1111111111111111ull, 0x0101010101010101ull
30
} else {
38
};
31
rule = float_3nan_prop_s_cab;
39
32
}
40
+static bool trans_INVALID(DisasContext *s, arg_INVALID *a)
33
-#elif defined(TARGET_SPARC)
41
+{
34
- rule = float_3nan_prop_s_cba;
42
+ unallocated_encoding(s);
35
#elif defined(TARGET_XTENSA)
43
+ return true;
36
if (status->use_first_nan) {
44
+}
37
rule = float_3nan_prop_abc;
45
+
46
/*
47
*** SVE Logical - Unpredicated Group
48
*/
49
@@ -XXX,XX +XXX,XX @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
50
51
static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
52
{
53
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
54
- return false;
55
- }
56
if (sve_access_check(s)) {
57
unsigned vsz = vec_full_reg_size(s);
58
int dofs = vec_full_reg_offset(s, a->rd);
59
-
60
tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm);
61
}
62
return true;
63
--
38
--
64
2.25.1
39
2.34.1
diff view generated by jsdifflib
[PULL 073/117] target/arm: Use TRANS_FEAT for MUL_zzi
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-71-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 10 +---------
8
target/mips/fpu_helper.h | 4 ++++
9
1 file changed, 1 insertion(+), 9 deletions(-)
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
10
12
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
15
--- a/target/mips/fpu_helper.h
14
+++ b/target/arm/translate-sve.c
16
+++ b/target/mips/fpu_helper.h
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
16
return true;
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
17
}
32
}
18
33
19
-static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a)
34
static inline void restore_fp_status(CPUMIPSState *env)
20
-{
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
21
- if (sve_access_check(s)) {
36
index XXXXXXX..XXXXXXX 100644
22
- unsigned vsz = vec_full_reg_size(s);
37
--- a/target/mips/msa.c
23
- tcg_gen_gvec_muli(a->esz, vec_full_reg_offset(s, a->rd),
38
+++ b/target/mips/msa.c
24
- vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz);
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
25
- }
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
26
- return true;
41
&env->active_tc.msa_fp_status);
27
-}
42
28
+TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a)
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
29
44
+ &env->active_tc.msa_fp_status);
30
static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
45
+
31
{
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
}
55
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
32
--
68
--
33
2.25.1
69
2.34.1
diff view generated by jsdifflib
[PULL 080/117] target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Use these for the several varieties of floating-point
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
multiply-add instructions.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
7
---
8
target/xtensa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
5
11
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
7
Message-id: 20220527181907.189259-78-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 140 ++++++++++++++-----------------------
12
1 file changed, 53 insertions(+), 87 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
14
--- a/target/xtensa/fpu_helper.c
17
+++ b/target/arm/translate-sve.c
15
+++ b/target/xtensa/fpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
19
return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
20
}
22
}
21
23
22
+/* Invoke an out-of-line helper on 4 Zregs, plus a pointer. */
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
23
+static bool gen_gvec_ptr_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
24
+ int rd, int rn, int rm, int ra,
26
index XXXXXXX..XXXXXXX 100644
25
+ int data, TCGv_ptr ptr)
27
--- a/fpu/softfloat-specialize.c.inc
26
+{
28
+++ b/fpu/softfloat-specialize.c.inc
27
+ if (fn == NULL) {
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
28
+ return false;
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd),
33
+ vec_full_reg_offset(s, rn),
34
+ vec_full_reg_offset(s, rm),
35
+ vec_full_reg_offset(s, ra),
36
+ ptr, vsz, vsz, data, fn);
37
+ }
38
+ return true;
39
+}
40
+
41
+static bool gen_gvec_fpst_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
42
+ int rd, int rn, int rm, int ra,
43
+ int data, ARMFPStatusFlavour flavour)
44
+{
45
+ TCGv_ptr status = fpstatus_ptr(flavour);
46
+ bool ret = gen_gvec_ptr_zzzz(s, fn, rd, rn, rm, ra, data, status);
47
+ tcg_temp_free_ptr(status);
48
+ return ret;
49
+}
50
+
51
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
52
static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
53
int rd, int rn, int pg, int data)
54
@@ -XXX,XX +XXX,XX @@ DO_SVE2_RRXR_ROT(CDOT_zzxw_d, gen_helper_sve2_cdot_idx_d)
55
56
static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub)
57
{
58
- static gen_helper_gvec_4_ptr * const fns[3] = {
59
+ static gen_helper_gvec_4_ptr * const fns[4] = {
60
+ NULL,
61
gen_helper_gvec_fmla_idx_h,
62
gen_helper_gvec_fmla_idx_s,
63
gen_helper_gvec_fmla_idx_d,
64
};
65
-
66
- if (sve_access_check(s)) {
67
- unsigned vsz = vec_full_reg_size(s);
68
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
69
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
70
- vec_full_reg_offset(s, a->rn),
71
- vec_full_reg_offset(s, a->rm),
72
- vec_full_reg_offset(s, a->ra),
73
- status, vsz, vsz, (a->index << 1) | sub,
74
- fns[a->esz - 1]);
75
- tcg_temp_free_ptr(status);
76
- }
77
- return true;
78
+ return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
79
+ (a->index << 1) | sub,
80
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
81
}
82
83
static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
84
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
85
86
static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
87
{
88
- static gen_helper_gvec_4_ptr * const fns[2] = {
89
+ static gen_helper_gvec_4_ptr * const fns[4] = {
90
+ NULL,
91
gen_helper_gvec_fcmlah_idx,
92
gen_helper_gvec_fcmlas_idx,
93
+ NULL,
94
};
95
96
- tcg_debug_assert(a->esz == 1 || a->esz == 2);
97
tcg_debug_assert(a->rd == a->ra);
98
- if (sve_access_check(s)) {
99
- unsigned vsz = vec_full_reg_size(s);
100
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
101
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
102
- vec_full_reg_offset(s, a->rn),
103
- vec_full_reg_offset(s, a->rm),
104
- vec_full_reg_offset(s, a->ra),
105
- status, vsz, vsz,
106
- a->index * 4 + a->rot,
107
- fns[a->esz - 1]);
108
- tcg_temp_free_ptr(status);
109
- }
110
- return true;
111
+
112
+ return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
113
+ a->index * 4 + a->rot,
114
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
115
}
116
117
/*
118
@@ -XXX,XX +XXX,XX @@ static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
119
return false;
120
}
30
}
121
31
122
- if (sve_access_check(s)) {
32
if (rule == float_3nan_prop_none) {
123
- unsigned vsz = vec_full_reg_size(s);
33
-#if defined(TARGET_XTENSA)
124
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
34
- if (status->use_first_nan) {
125
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
35
- rule = float_3nan_prop_abc;
126
- vec_full_reg_offset(s, a->rn),
36
- } else {
127
- vec_full_reg_offset(s, a->rm),
37
- rule = float_3nan_prop_cba;
128
- vec_full_reg_offset(s, a->ra),
38
- }
129
- status, vsz, vsz, 0, fn);
39
-#else
130
- tcg_temp_free_ptr(status);
40
rule = float_3nan_prop_abc;
131
- }
41
-#endif
132
- return true;
133
+ return gen_gvec_fpst_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR);
134
}
135
136
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
137
@@ -XXX,XX +XXX,XX @@ static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
138
if (!dc_isar_feature(aa64_sve2, s)) {
139
return false;
140
}
42
}
141
- if (sve_access_check(s)) {
43
142
- unsigned vsz = vec_full_reg_size(s);
44
assert(rule != float_3nan_prop_none);
143
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
144
- vec_full_reg_offset(s, a->rn),
145
- vec_full_reg_offset(s, a->rm),
146
- vec_full_reg_offset(s, a->ra),
147
- cpu_env, vsz, vsz, (sel << 1) | sub,
148
- gen_helper_sve2_fmlal_zzzw_s);
149
- }
150
- return true;
151
+ return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s,
152
+ a->rd, a->rn, a->rm, a->ra,
153
+ (sel << 1) | sub, cpu_env);
154
}
155
156
static bool trans_FMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
157
@@ -XXX,XX +XXX,XX @@ static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel)
158
if (!dc_isar_feature(aa64_sve2, s)) {
159
return false;
160
}
161
- if (sve_access_check(s)) {
162
- unsigned vsz = vec_full_reg_size(s);
163
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
164
- vec_full_reg_offset(s, a->rn),
165
- vec_full_reg_offset(s, a->rm),
166
- vec_full_reg_offset(s, a->ra),
167
- cpu_env, vsz, vsz,
168
- (a->index << 2) | (sel << 1) | sub,
169
- gen_helper_sve2_fmlal_zzxw_s);
170
- }
171
- return true;
172
+ return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s,
173
+ a->rd, a->rn, a->rm, a->ra,
174
+ (a->index << 2) | (sel << 1) | sub, cpu_env);
175
}
176
177
static bool trans_FMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
178
@@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
179
if (!dc_isar_feature(aa64_sve_bf16, s)) {
180
return false;
181
}
182
- if (sve_access_check(s)) {
183
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
184
- unsigned vsz = vec_full_reg_size(s);
185
-
186
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
187
- vec_full_reg_offset(s, a->rn),
188
- vec_full_reg_offset(s, a->rm),
189
- vec_full_reg_offset(s, a->ra),
190
- status, vsz, vsz, sel,
191
- gen_helper_gvec_bfmlal);
192
- tcg_temp_free_ptr(status);
193
- }
194
- return true;
195
+ return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal,
196
+ a->rd, a->rn, a->rm, a->ra, sel, FPST_FPCR);
197
}
198
199
static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
200
@@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
201
if (!dc_isar_feature(aa64_sve_bf16, s)) {
202
return false;
203
}
204
- if (sve_access_check(s)) {
205
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
206
- unsigned vsz = vec_full_reg_size(s);
207
-
208
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
209
- vec_full_reg_offset(s, a->rn),
210
- vec_full_reg_offset(s, a->rm),
211
- vec_full_reg_offset(s, a->ra),
212
- status, vsz, vsz, (a->index << 1) | sel,
213
- gen_helper_gvec_bfmlal_idx);
214
- tcg_temp_free_ptr(status);
215
- }
216
- return true;
217
+ return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx,
218
+ a->rd, a->rn, a->rm, a->ra,
219
+ (a->index << 1) | sel, FPST_FPCR);
220
}
221
222
static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
223
--
45
--
224
2.25.1
46
2.34.1
diff view generated by jsdifflib
[PULL 072/117] target/arm: Use TRANS_FEAT for do_brk2, do_brk3
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-70-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
7
---
9
---
8
target/arm/translate-sve.c | 45 ++++++++++++--------------------------
10
target/i386/tcg/fpu_helper.c | 1 +
9
1 file changed, 14 insertions(+), 31 deletions(-)
11
1 file changed, 1 insertion(+)
10
12
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
15
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
16
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
return true;
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
17
}
22
}
18
23
19
-static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a)
24
static inline uint8_t save_exception_flags(CPUX86State *env)
20
-{
21
- return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas);
22
-}
23
+TRANS_FEAT(BRKPA, aa64_sve, do_brk3, a,
24
+ gen_helper_sve_brkpa, gen_helper_sve_brkpas)
25
+TRANS_FEAT(BRKPB, aa64_sve, do_brk3, a,
26
+ gen_helper_sve_brkpb, gen_helper_sve_brkpbs)
27
28
-static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a)
29
-{
30
- return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs);
31
-}
32
+TRANS_FEAT(BRKA_m, aa64_sve, do_brk2, a,
33
+ gen_helper_sve_brka_m, gen_helper_sve_brkas_m)
34
+TRANS_FEAT(BRKB_m, aa64_sve, do_brk2, a,
35
+ gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m)
36
37
-static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a)
38
-{
39
- return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m);
40
-}
41
+TRANS_FEAT(BRKA_z, aa64_sve, do_brk2, a,
42
+ gen_helper_sve_brka_z, gen_helper_sve_brkas_z)
43
+TRANS_FEAT(BRKB_z, aa64_sve, do_brk2, a,
44
+ gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z)
45
46
-static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a)
47
-{
48
- return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m);
49
-}
50
-
51
-static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a)
52
-{
53
- return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z);
54
-}
55
-
56
-static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a)
57
-{
58
- return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z);
59
-}
60
-
61
-static bool trans_BRKN(DisasContext *s, arg_rpr_s *a)
62
-{
63
- return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns);
64
-}
65
+TRANS_FEAT(BRKN, aa64_sve, do_brk2, a,
66
+ gen_helper_sve_brkn, gen_helper_sve_brkns)
67
68
/*
69
*** SVE Predicate Count Group
70
--
25
--
71
2.25.1
26
2.34.1
diff view generated by jsdifflib
[PULL 071/117] target/arm: Use TRANS_FEAT for do_ppzi_flags
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
HPPA is the only target that was using the default branch of the
4
Message-id: 20220527181907.189259-69-richard.henderson@linaro.org
5
ifdef ladder (other targets either do not use muladd or set
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
7
---
16
---
8
target/arm/translate-sve.c | 8 +++-----
17
target/hppa/fpu_helper.c | 8 ++++++++
9
1 file changed, 3 insertions(+), 5 deletions(-)
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
10
20
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
23
--- a/target/hppa/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
24
+++ b/target/hppa/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
16
}
39
}
17
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
18
#define DO_PPZI(NAME, name) \
41
index XXXXXXX..XXXXXXX 100644
19
-static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a) \
42
--- a/fpu/softfloat-specialize.c.inc
20
-{ \
43
+++ b/fpu/softfloat-specialize.c.inc
21
- static gen_helper_gvec_flags_3 * const fns[4] = { \
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
22
+ static gen_helper_gvec_flags_3 * const name##_ppzi_fns[4] = { \
45
}
23
gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \
46
}
24
gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \
47
25
}; \
48
- if (rule == float_3nan_prop_none) {
26
- return do_ppzi_flags(s, a, fns[a->esz]); \
49
- rule = float_3nan_prop_abc;
27
-}
50
- }
28
+ TRANS_FEAT(NAME##_ppzi, aa64_sve, do_ppzi_flags, a, \
51
-
29
+ name##_ppzi_fns[a->esz])
52
assert(rule != float_3nan_prop_none);
30
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
31
DO_PPZI(CMPEQ, cmpeq)
54
/* We have at least one SNaN input and should prefer it */
32
DO_PPZI(CMPNE, cmpne)
33
--
55
--
34
2.25.1
56
2.34.1
diff view generated by jsdifflib
[PULL 067/117] target/arm: Use TRANS_FEAT for do_last_general
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
2
6
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-65-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
7
---
10
---
8
target/arm/translate-sve.c | 11 ++---------
11
include/fpu/softfloat-helpers.h | 5 -----
9
1 file changed, 2 insertions(+), 9 deletions(-)
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
10
15
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
18
--- a/include/fpu/softfloat-helpers.h
14
+++ b/target/arm/translate-sve.c
19
+++ b/include/fpu/softfloat-helpers.h
15
@@ -XXX,XX +XXX,XX @@ static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before)
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
16
return true;
21
status->snan_bit_is_one = val;
17
}
22
}
18
23
19
-static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a)
24
-static inline void set_use_first_nan(bool val, float_status *status)
20
-{
25
-{
21
- return do_last_general(s, a, false);
26
- status->use_first_nan = val;
22
-}
27
-}
23
-
28
-
24
-static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a)
29
static inline void set_no_signaling_nans(bool val, float_status *status)
25
-{
26
- return do_last_general(s, a, true);
27
-}
28
+TRANS_FEAT(LASTA_r, aa64_sve, do_last_general, a, false)
29
+TRANS_FEAT(LASTB_r, aa64_sve, do_last_general, a, true)
30
31
static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a)
32
{
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
33
--
56
--
34
2.25.1
57
2.34.1
diff view generated by jsdifflib
[PULL 070/117] target/arm: Use TRANS_FEAT for do_sve2_ppzz_flags
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
2
8
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
4
Message-id: 20220527181907.189259-68-richard.henderson@linaro.org
10
earlier, and thus can pass it to floatx80_default_nan().
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
7
---
15
---
8
target/arm/translate-sve.c | 28 ++++++++--------------------
16
target/m68k/cpu.c | 12 +++++++-----
9
1 file changed, 8 insertions(+), 20 deletions(-)
17
1 file changed, 7 insertions(+), 5 deletions(-)
10
18
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
21
--- a/target/m68k/cpu.c
14
+++ b/target/arm/translate-sve.c
22
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt)
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
DO_SVE2_ZZZ_NARROW(RSUBHNB, rsubhnb)
24
CPUState *cs = CPU(obj);
17
DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt)
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
18
26
CPUM68KState *env = cpu_env(cs);
19
-static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
27
- floatx80 nan = floatx80_default_nan(NULL);
20
- gen_helper_gvec_flags_4 *fn)
28
+ floatx80 nan;
21
-{
29
int i;
22
- if (!dc_isar_feature(aa64_sve2, s)) {
30
23
- return false;
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
24
- }
38
- }
25
- return do_ppzz_flags(s, a, fn);
39
- cpu_m68k_set_fpcr(env, 0);
26
-}
40
/*
27
+static gen_helper_gvec_flags_4 * const match_fns[4] = {
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
28
+ gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
29
+};
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
30
+TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
44
* preceding paragraph for nonsignaling NaNs.
31
45
*/
32
-#define DO_SVE2_PPZZ_MATCH(NAME, name) \
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
33
-static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
47
+
34
-{ \
48
+ nan = floatx80_default_nan(&env->fp_status);
35
- static gen_helper_gvec_flags_4 * const fns[4] = { \
49
+ for (i = 0; i < 8; i++) {
36
- gen_helper_sve2_##name##_ppzz_b, gen_helper_sve2_##name##_ppzz_h, \
50
+ env->fregs[i].d = nan;
37
- NULL, NULL \
51
+ }
38
- }; \
52
+ cpu_m68k_set_fpcr(env, 0);
39
- return do_sve2_ppzz_flags(s, a, fns[a->esz]); \
53
env->fpsr = 0;
40
-}
54
41
-
55
/* TODO: We should set PC from the interrupt vector. */
42
-DO_SVE2_PPZZ_MATCH(MATCH, match)
43
-DO_SVE2_PPZZ_MATCH(NMATCH, nmatch)
44
+static gen_helper_gvec_flags_4 * const nmatch_fns[4] = {
45
+ gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL
46
+};
47
+TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
48
49
static gen_helper_gvec_4 * const histcnt_fns[4] = {
50
NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
51
--
56
--
52
2.25.1
57
2.34.1
diff view generated by jsdifflib
[PULL 069/117] target/arm: Use TRANS_FEAT for do_ppzz_flags
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
From: Richard Henderson <richard.henderson@linaro.org>
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
2
4
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
floatx80 is used only by:
4
Message-id: 20220527181907.189259-67-richard.henderson@linaro.org
6
i386
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
7
---
40
---
8
target/arm/translate-sve.c | 28 ++++++++++++----------------
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
9
1 file changed, 12 insertions(+), 16 deletions(-)
42
1 file changed, 10 insertions(+), 10 deletions(-)
10
43
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
12
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
46
--- a/fpu/softfloat-specialize.c.inc
14
+++ b/target/arm/translate-sve.c
47
+++ b/fpu/softfloat-specialize.c.inc
15
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
16
}
74
}
17
75
18
#define DO_PPZZ(NAME, name) \
19
-static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \
20
-{ \
21
- static gen_helper_gvec_flags_4 * const fns[4] = { \
22
- gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \
23
- gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \
24
- }; \
25
- return do_ppzz_flags(s, a, fns[a->esz]); \
26
-}
27
+ static gen_helper_gvec_flags_4 * const name##_ppzz_fns[4] = { \
28
+ gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \
29
+ gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \
30
+ }; \
31
+ TRANS_FEAT(NAME##_ppzz, aa64_sve, do_ppzz_flags, \
32
+ a, name##_ppzz_fns[a->esz])
33
34
DO_PPZZ(CMPEQ, cmpeq)
35
DO_PPZZ(CMPNE, cmpne)
36
@@ -XXX,XX +XXX,XX @@ DO_PPZZ(CMPHS, cmphs)
37
#undef DO_PPZZ
38
39
#define DO_PPZW(NAME, name) \
40
-static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a) \
41
-{ \
42
- static gen_helper_gvec_flags_4 * const fns[4] = { \
43
- gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \
44
- gen_helper_sve_##name##_ppzw_s, NULL \
45
- }; \
46
- return do_ppzz_flags(s, a, fns[a->esz]); \
47
-}
48
+ static gen_helper_gvec_flags_4 * const name##_ppzw_fns[4] = { \
49
+ gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \
50
+ gen_helper_sve_##name##_ppzw_s, NULL \
51
+ }; \
52
+ TRANS_FEAT(NAME##_ppzw, aa64_sve, do_ppzz_flags, \
53
+ a, name##_ppzw_fns[a->esz])
54
55
DO_PPZW(CMPEQ, cmpeq)
56
DO_PPZW(CMPNE, cmpne)
57
--
76
--
58
2.25.1
77
2.34.1
diff view generated by jsdifflib
[PULL 068/117] target/arm: Use TRANS_FEAT for SPLICE
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
This pattern appears to have been copied from target/riscv, where it
4
Message-id: 20220527181907.189259-66-richard.henderson@linaro.org
7
is used because the functions there do not have ready access to the
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
7
---
21
---
8
target/arm/translate-sve.c | 17 ++++-------------
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
9
1 file changed, 4 insertions(+), 13 deletions(-)
23
1 file changed, 2 insertions(+), 4 deletions(-)
10
24
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
27
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
16
TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
30
} else if (float32_is_zero_or_denormal(f)) {
17
a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
31
return sign ? 1 << 4 : 1 << 8;
18
32
} else if (float32_is_any_nan(f)) {
19
-static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
33
- float_status s = { }; /* for snan_bit_is_one */
20
-{
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
21
- return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
22
- a->rd, a->rn, a->rm, a->pg, a->esz);
36
} else {
23
-}
37
return sign ? 1 << 3 : 1 << 7;
24
+TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz,
38
}
25
+ gen_helper_sve_splice, a, a->esz)
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
26
40
} else if (float64_is_zero_or_denormal(f)) {
27
-static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
41
return sign ? 1 << 4 : 1 << 8;
28
-{
42
} else if (float64_is_any_nan(f)) {
29
- if (!dc_isar_feature(aa64_sve2, s)) {
43
- float_status s = { }; /* for snan_bit_is_one */
30
- return false;
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
31
- }
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
32
- return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
46
} else {
33
- a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
47
return sign ? 1 << 3 : 1 << 7;
34
-}
48
}
35
+TRANS_FEAT(SPLICE_sve2, aa64_sve2, gen_gvec_ool_zzzp, gen_helper_sve_splice,
36
+ a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz)
37
38
/*
39
*** SVE Integer Compare - Vectors Group
40
--
49
--
41
2.25.1
50
2.34.1
diff view generated by jsdifflib
[PULL 066/117] target/arm: Use TRANS_FEAT for do_last_fp
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
2
9
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-64-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
7
---
13
---
8
target/arm/translate-sve.c | 11 ++---------
14
target/m68k/fpu_helper.c | 6 ++----
9
1 file changed, 2 insertions(+), 9 deletions(-)
15
1 file changed, 2 insertions(+), 4 deletions(-)
10
16
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
19
--- a/target/m68k/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
20
+++ b/target/m68k/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before)
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
16
return true;
22
17
}
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
18
24
if (!floatx80_is_any_nan(fp_rem)) {
19
-static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a)
25
- float_status fp_status = { };
20
-{
26
+ /* Use local temporary fp_status to set different rounding mode */
21
- return do_last_fp(s, a, false);
27
+ float_status fp_status = env->fp_status;
22
-}
28
uint32_t quotient;
23
-
29
int sign;
24
-static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a)
30
25
-{
31
/* Calculate quotient directly using round to nearest mode */
26
- return do_last_fp(s, a, true);
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
27
-}
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
28
+TRANS_FEAT(LASTA_v, aa64_sve, do_last_fp, a, false)
34
- set_floatx80_rounding_precision(
29
+TRANS_FEAT(LASTB_v, aa64_sve, do_last_fp, a, true)
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
30
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
31
/* Compute LAST for a Xreg. */
37
32
static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before)
38
sign = extractFloatx80Sign(fp_quot.d);
33
--
39
--
34
2.25.1
40
2.34.1
diff view generated by jsdifflib
[PULL 065/117] target/arm: Use TRANS_FEAT for do_clast_general
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
2
9
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-63-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
7
---
13
---
8
target/arm/translate-sve.c | 11 ++---------
14
target/m68k/helper.c | 6 ++++--
9
1 file changed, 2 insertions(+), 9 deletions(-)
15
1 file changed, 4 insertions(+), 2 deletions(-)
10
16
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
19
--- a/target/m68k/helper.c
14
+++ b/target/arm/translate-sve.c
20
+++ b/target/m68k/helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before)
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
16
return true;
22
CPUM68KState *env = &cpu->env;
17
}
23
18
24
if (n < 8) {
19
-static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a)
25
- float_status s = {};
20
-{
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
21
- return do_clast_general(s, a, false);
27
+ float_status s = env->fp_status;
22
-}
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
23
-
29
}
24
-static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a)
30
switch (n) {
25
-{
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
26
- return do_clast_general(s, a, true);
32
CPUM68KState *env = &cpu->env;
27
-}
33
28
+TRANS_FEAT(CLASTA_r, aa64_sve, do_clast_general, a, false)
34
if (n < 8) {
29
+TRANS_FEAT(CLASTB_r, aa64_sve, do_clast_general, a, true)
35
- float_status s = {};
30
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
31
/* Compute LAST for a scalar. */
37
+ float_status s = env->fp_status;
32
static TCGv_i64 do_last_scalar(DisasContext *s, int esz,
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
40
}
33
--
41
--
34
2.25.1
42
2.34.1
diff view generated by jsdifflib
[PULL 040/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
Convert SVE translation functions using do_sve2_zzzz_fn
8
To do this we need to pass the CPU env pointer in to the helper.
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzzz.
5
9
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-38-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
10
---
13
---
11
target/arm/translate-sve.c | 38 ++++++--------------------------------
14
target/sparc/helper.h | 4 ++--
12
1 file changed, 6 insertions(+), 32 deletions(-)
15
target/sparc/fop_helper.c | 8 ++++----
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
13
18
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
21
--- a/target/sparc/helper.h
17
+++ b/target/arm/translate-sve.c
22
+++ b/target/sparc/helper.h
18
@@ -XXX,XX +XXX,XX @@ static bool trans_XAR(DisasContext *s, arg_rrri_esz *a)
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
19
return true;
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
32
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/sparc/fop_helper.c
37
+++ b/target/sparc/fop_helper.c
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
39
return finish_fcmp(env, r, GETPC());
20
}
40
}
21
41
22
-static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn)
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
23
-{
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
24
- if (!dc_isar_feature(aa64_sve2, s)) {
25
- return false;
26
- }
27
- return gen_gvec_fn_arg_zzzz(s, fn, a);
28
-}
29
-
30
static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
31
{
44
{
32
tcg_gen_xor_i64(d, n, m);
45
/*
33
@@ -XXX,XX +XXX,XX @@ static void gen_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
46
* FLCMP never raises an exception nor modifies any FSR fields.
34
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
47
* Perform the comparison with a dummy fp environment.
48
*/
49
- float_status discard = { };
50
+ float_status discard = env->fp_status;
51
FloatRelation r;
52
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
55
g_assert_not_reached();
35
}
56
}
36
57
37
-static bool trans_EOR3(DisasContext *s, arg_rrrr_esz *a)
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
38
-{
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
39
- return do_sve2_zzzz_fn(s, a, gen_eor3);
40
-}
41
+TRANS_FEAT(EOR3, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_eor3, a)
42
43
static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
44
{
60
{
45
@@ -XXX,XX +XXX,XX @@ static void gen_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
61
- float_status discard = { };
46
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
62
+ float_status discard = env->fp_status;
63
FloatRelation r;
64
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/sparc/translate.c
69
+++ b/target/sparc/translate.c
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
71
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
47
}
77
}
48
78
49
-static bool trans_BCAX(DisasContext *s, arg_rrrr_esz *a)
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
50
-{
80
51
- return do_sve2_zzzz_fn(s, a, gen_bcax);
81
src1 = gen_load_fpr_D(dc, a->rs1);
52
-}
82
src2 = gen_load_fpr_D(dc, a->rs2);
53
+TRANS_FEAT(BCAX, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bcax, a)
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
54
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
55
static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
85
return advance_pc(dc);
56
uint32_t a, uint32_t oprsz, uint32_t maxsz)
57
@@ -XXX,XX +XXX,XX @@ static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
58
tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz);
59
}
86
}
60
87
61
-static bool trans_BSL(DisasContext *s, arg_rrrr_esz *a)
62
-{
63
- return do_sve2_zzzz_fn(s, a, gen_bsl);
64
-}
65
+TRANS_FEAT(BSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a)
66
67
static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
68
{
69
@@ -XXX,XX +XXX,XX @@ static void gen_bsl1n(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
70
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
71
}
72
73
-static bool trans_BSL1N(DisasContext *s, arg_rrrr_esz *a)
74
-{
75
- return do_sve2_zzzz_fn(s, a, gen_bsl1n);
76
-}
77
+TRANS_FEAT(BSL1N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a)
78
79
static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
80
{
81
@@ -XXX,XX +XXX,XX @@ static void gen_bsl2n(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
82
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
83
}
84
85
-static bool trans_BSL2N(DisasContext *s, arg_rrrr_esz *a)
86
-{
87
- return do_sve2_zzzz_fn(s, a, gen_bsl2n);
88
-}
89
+TRANS_FEAT(BSL2N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a)
90
91
static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
92
{
93
@@ -XXX,XX +XXX,XX @@ static void gen_nbsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
94
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
95
}
96
97
-static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
98
-{
99
- return do_sve2_zzzz_fn(s, a, gen_nbsl);
100
-}
101
+TRANS_FEAT(NBSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a)
102
103
/*
104
*** SVE Integer Arithmetic - Unpredicated Group
105
--
88
--
106
2.25.1
89
2.34.1
diff view generated by jsdifflib
[PULL 064/117] target/arm: Use TRANS_FEAT for do_clast_fp
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
2
8
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Use env->fp_status instead of the dummy fp_status.
4
Message-id: 20220527181907.189259-62-richard.henderson@linaro.org
10
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
7
---
14
---
8
target/arm/translate-sve.c | 11 ++---------
15
target/ppc/fpu_helper.c | 3 +--
9
1 file changed, 2 insertions(+), 9 deletions(-)
16
1 file changed, 1 insertion(+), 2 deletions(-)
10
17
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
20
--- a/target/ppc/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
21
+++ b/target/ppc/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before)
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
16
return true;
23
} else if (tp##_is_infinity(arg)) { \
17
}
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
18
25
} else { \
19
-static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a)
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
20
-{
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
21
- return do_clast_fp(s, a, false);
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
22
-}
29
fprf = 0x00 << FPSCR_FPRF; \
23
-
30
} else { \
24
-static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a)
31
fprf = 0x11 << FPSCR_FPRF; \
25
-{
26
- return do_clast_fp(s, a, true);
27
-}
28
+TRANS_FEAT(CLASTA_v, aa64_sve, do_clast_fp, a, false)
29
+TRANS_FEAT(CLASTB_v, aa64_sve, do_clast_fp, a, true)
30
31
/* Compute CLAST for a Xreg. */
32
static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before)
33
--
32
--
34
2.25.1
33
2.34.1
diff view generated by jsdifflib
[PULL 050/117] target/arm: Use TRANS_FEAT for do_zpzzz_ool
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remove the DO_ZPZZZ macro, as it had just the two uses.
3
Now that float_status has a bunch of fp parameters,
4
it is easier to copy an existing structure than create
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
4
8
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-48-richard.henderson@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
14
---
10
target/arm/translate-sve.c | 23 ++++++++++-------------
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
11
1 file changed, 10 insertions(+), 13 deletions(-)
16
1 file changed, 7 insertions(+), 13 deletions(-)
12
17
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
20
--- a/target/arm/tcg/vec_helper.c
16
+++ b/target/arm/translate-sve.c
21
+++ b/target/arm/tcg/vec_helper.c
17
@@ -XXX,XX +XXX,XX @@ static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a,
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
18
return true;
23
* no effect on AArch32 instructions.
24
*/
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
26
- *statusp = (float_status){
27
- .tininess_before_rounding = float_tininess_before_rounding,
28
- .float_rounding_mode = float_round_to_odd_inf,
29
- .flush_to_zero = true,
30
- .flush_inputs_to_zero = true,
31
- .default_nan_mode = true,
32
- };
33
+
34
+ *statusp = env->vfp.fp_status;
35
+ set_default_nan_mode(true, statusp);
36
37
if (ebf) {
38
- float_status *fpst = &env->vfp.fp_status;
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
42
-
43
/* EBF=1 needs to do a step with round-to-odd semantics */
44
*oddstatusp = *statusp;
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
46
+ } else {
47
+ set_flush_to_zero(true, statusp);
48
+ set_flush_inputs_to_zero(true, statusp);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
50
}
51
-
52
return ebf;
19
}
53
}
20
54
21
-#define DO_ZPZZZ(NAME, name) \
22
-static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
23
-{ \
24
- static gen_helper_gvec_5 * const fns[4] = { \
25
- gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
26
- gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
27
- }; \
28
- return do_zpzzz_ool(s, a, fns[a->esz]); \
29
-}
30
+static gen_helper_gvec_5 * const mla_fns[4] = {
31
+ gen_helper_sve_mla_b, gen_helper_sve_mla_h,
32
+ gen_helper_sve_mla_s, gen_helper_sve_mla_d,
33
+};
34
+TRANS_FEAT(MLA, aa64_sve, do_zpzzz_ool, a, mla_fns[a->esz])
35
36
-DO_ZPZZZ(MLA, mla)
37
-DO_ZPZZZ(MLS, mls)
38
-
39
-#undef DO_ZPZZZ
40
+static gen_helper_gvec_5 * const mls_fns[4] = {
41
+ gen_helper_sve_mls_b, gen_helper_sve_mls_h,
42
+ gen_helper_sve_mls_s, gen_helper_sve_mls_d,
43
+};
44
+TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz])
45
46
/*
47
*** SVE Index Generation Group
48
--
55
--
49
2.25.1
56
2.34.1
57
58
diff view generated by jsdifflib
[PULL 029/117] target/arm: Introduce gen_gvec_ool_arg_zpzz
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
2
6
3
Use gen_gvec_ool_arg_zpzz instead of gen_gvec_ool_zzzp
7
Add a field to float_status to specify the default NaN value; fall
4
when the arguments come from arg_rprr_esz.
8
back to the old ifdef behaviour if these are not set.
5
Replaces do_zpzz_ool.
6
9
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
The default NaN value is specified by setting a uint8_t to a
8
Message-id: 20220527181907.189259-27-richard.henderson@linaro.org
11
pattern corresponding to the sign and upper fraction parts of
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
the pattern.
14
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
11
---
18
---
12
target/arm/translate-sve.c | 21 +++++++++++----------
19
include/fpu/softfloat-helpers.h | 11 +++++++
13
1 file changed, 11 insertions(+), 10 deletions(-)
20
include/fpu/softfloat-types.h | 10 ++++++
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
14
23
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
16
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
26
--- a/include/fpu/softfloat-helpers.h
18
+++ b/target/arm/translate-sve.c
27
+++ b/include/fpu/softfloat-helpers.h
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
20
return true;
29
status->float_infzeronan_rule = rule;
21
}
30
}
22
31
23
+static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
24
+ arg_rprr_esz *a, int data)
33
+ float_status *status)
25
+{
34
+{
26
+ return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
35
+ status->default_nan_pattern = dnan_pattern;
27
+}
36
+}
28
+
37
+
29
/* Invoke a vector expander on two Zregs. */
38
static inline void set_flush_to_zero(bool val, float_status *status)
30
static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
39
{
31
int esz, int rd, int rn)
40
status->flush_to_zero = val;
32
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
33
*** SVE Integer Arithmetic - Binary Predicated Group
42
return status->float_infzeronan_rule;
34
*/
35
36
-static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
37
-{
38
- return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
39
-}
40
-
41
/* Select active elememnts from Zn and inactive elements from Zm,
42
* storing the result in Zd.
43
*/
44
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a) \
45
gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \
46
gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \
47
}; \
48
- return do_zpzz_ool(s, a, fns[a->esz]); \
49
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
50
}
43
}
51
44
52
DO_ZPZZ(AND, and)
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
53
@@ -XXX,XX +XXX,XX @@ static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
46
+{
54
static gen_helper_gvec_4 * const fns[4] = {
47
+ return status->default_nan_pattern;
55
NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
48
+}
56
};
49
+
57
- return do_zpzz_ool(s, a, fns[a->esz]);
50
static inline bool get_flush_to_zero(float_status *status)
58
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
51
{
59
}
52
return status->flush_to_zero;
60
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
61
static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
54
index XXXXXXX..XXXXXXX 100644
62
@@ -XXX,XX +XXX,XX @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
55
--- a/include/fpu/softfloat-types.h
63
static gen_helper_gvec_4 * const fns[4] = {
56
+++ b/include/fpu/softfloat-types.h
64
NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
65
};
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
66
- return do_zpzz_ool(s, a, fns[a->esz]);
59
bool flush_inputs_to_zero;
67
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
60
bool default_nan_mode;
68
}
61
+ /*
69
62
+ * The pattern to use for the default NaN. Here the high bit specifies
70
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
71
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a) \
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
72
if (a->esz < 0 || a->esz >= 3) { \
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
73
return false; \
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
74
} \
67
+ * this to the correct non-zero value, or we will assert when trying to
75
- return do_zpzz_ool(s, a, fns[a->esz]); \
68
+ * create a default NaN.
76
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
69
+ */
77
}
70
+ uint8_t default_nan_pattern;
78
71
/*
79
DO_ZPZW(ASR, asr)
72
* The flags below are not used on all specializations and may
80
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zpzz_ool(DisasContext *s, arg_rprr_esz *a,
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
81
if (!dc_isar_feature(aa64_sve2, s)) {
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
82
return false;
75
index XXXXXXX..XXXXXXX 100644
83
}
76
--- a/fpu/softfloat-specialize.c.inc
84
- return do_zpzz_ool(s, a, fn);
77
+++ b/fpu/softfloat-specialize.c.inc
85
+ return gen_gvec_ool_arg_zpzz(s, fn, a, 0);
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
86
}
79
{
87
80
bool sign = 0;
88
static bool trans_SADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
136
+
137
+ sign = dnan_pattern >> 7;
138
+ /*
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
140
+ * and replecate bit [0] down into [55:0]
141
+ */
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
144
145
*p = (FloatParts64) {
146
.cls = float_class_qnan,
89
--
147
--
90
2.25.1
148
2.34.1
diff view generated by jsdifflib
[PULL 063/117] target/arm: Use TRANS_FEAT for do_clast_vector
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for the tests/fp code.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-61-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 11 ++---------
7
tests/fp/fp-bench.c | 1 +
9
1 file changed, 2 insertions(+), 9 deletions(-)
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/tests/fp/fp-bench.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/tests/fp/fp-bench.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before)
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
16
return true;
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
17
}
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
18
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
19
-static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a)
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
20
-{
21
21
- return do_clast_vector(s, a, false);
22
f = bench_funcs[operation][precision];
22
-}
23
g_assert(f);
23
-
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
24
-static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a)
25
index XXXXXXX..XXXXXXX 100644
25
-{
26
--- a/tests/fp/fp-test-log2.c
26
- return do_clast_vector(s, a, true);
27
+++ b/tests/fp/fp-test-log2.c
27
-}
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
28
+TRANS_FEAT(CLASTA_z, aa64_sve, do_clast_vector, a, false)
29
int i;
29
+TRANS_FEAT(CLASTB_z, aa64_sve, do_clast_vector, a, true)
30
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
31
/* Compute CLAST for a scalar. */
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
32
static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
33
--
48
--
34
2.25.1
49
2.34.1
diff view generated by jsdifflib
[PULL 062/117] target/arm: Use TRANS_FEAT for do_zip, do_zip_q
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
2
3
3
Convert SVE translation functions using do_zip*
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
5
11
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
7
Message-id: 20220527181907.189259-60-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 54 +++++++++-----------------------------
12
1 file changed, 13 insertions(+), 41 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
14
--- a/target/microblaze/cpu.c
17
+++ b/target/arm/translate-sve.c
15
+++ b/target/microblaze/cpu.c
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p)
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
19
*** SVE Permute - Interleaving Group
17
* this architecture.
20
*/
18
*/
21
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
22
-static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
20
+ /* Default NaN: sign bit set, most significant frac bit set */
23
-{
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
24
- static gen_helper_gvec_3 * const fns[4] = {
22
25
- gen_helper_sve_zip_b, gen_helper_sve_zip_h,
23
#if defined(CONFIG_USER_ONLY)
26
- gen_helper_sve_zip_s, gen_helper_sve_zip_d,
24
/* start in user mode with interrupts enabled. */
27
- };
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
- unsigned vsz = vec_full_reg_size(s);
26
index XXXXXXX..XXXXXXX 100644
29
- unsigned high_ofs = high ? vsz / 2 : 0;
27
--- a/fpu/softfloat-specialize.c.inc
30
+static gen_helper_gvec_3 * const zip_fns[4] = {
28
+++ b/fpu/softfloat-specialize.c.inc
31
+ gen_helper_sve_zip_b, gen_helper_sve_zip_h,
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
+ gen_helper_sve_zip_s, gen_helper_sve_zip_d,
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+};
31
/* Sign bit clear, all frac bits set */
34
+TRANS_FEAT(ZIP1_z, aa64_sve, gen_gvec_ool_arg_zzz,
32
dnan_pattern = 0b01111111;
35
+ zip_fns[a->esz], a, 0)
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
36
+TRANS_FEAT(ZIP2_z, aa64_sve, gen_gvec_ool_arg_zzz,
34
- || defined(TARGET_MICROBLAZE)
37
+ zip_fns[a->esz], a, vec_full_reg_size(s) / 2)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
38
36
/* Sign bit set, most significant frac bit set */
39
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, high_ofs);
37
dnan_pattern = 0b11000000;
40
-}
38
#elif defined(TARGET_HPPA)
41
-
42
-static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
43
-{
44
- return do_zip(s, a, false);
45
-}
46
-
47
-static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a)
48
-{
49
- return do_zip(s, a, true);
50
-}
51
-
52
-static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
53
-{
54
- unsigned vsz = vec_full_reg_size(s);
55
- unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
56
-
57
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
58
- return false;
59
- }
60
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_zip_q, a, high_ofs);
61
-}
62
-
63
-static bool trans_ZIP1_q(DisasContext *s, arg_rrr_esz *a)
64
-{
65
- return do_zip_q(s, a, false);
66
-}
67
-
68
-static bool trans_ZIP2_q(DisasContext *s, arg_rrr_esz *a)
69
-{
70
- return do_zip_q(s, a, true);
71
-}
72
+TRANS_FEAT(ZIP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
73
+ gen_helper_sve2_zip_q, a, 0)
74
+TRANS_FEAT(ZIP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
75
+ gen_helper_sve2_zip_q, a,
76
+ QEMU_ALIGN_DOWN(vec_full_reg_size(s), 32) / 2)
77
78
static gen_helper_gvec_3 * const uzp_fns[4] = {
79
gen_helper_sve_uzp_b, gen_helper_sve_uzp_h,
80
--
39
--
81
2.25.1
40
2.34.1
diff view generated by jsdifflib
[PULL 061/117] target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-59-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 25 +++++++------------------
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
1 file changed, 7 insertions(+), 18 deletions(-)
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
gen_helper_sve_zip_b, gen_helper_sve_zip_h,
17
*/
17
gen_helper_sve_zip_s, gen_helper_sve_zip_d,
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
18
};
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
19
+ unsigned vsz = vec_full_reg_size(s);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
20
+ unsigned high_ofs = high ? vsz / 2 : 0;
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
21
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
22
- if (sve_access_check(s)) {
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
23
- unsigned vsz = vec_full_reg_size(s);
24
- unsigned high_ofs = high ? vsz / 2 : 0;
25
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
26
- vec_full_reg_offset(s, a->rn),
27
- vec_full_reg_offset(s, a->rm),
28
- vsz, vsz, high_ofs, fns[a->esz]);
29
- }
30
- return true;
31
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, high_ofs);
32
}
24
}
33
25
34
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
26
static inline uint8_t save_exception_flags(CPUX86State *env)
35
@@ -XXX,XX +XXX,XX @@ static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
28
index XXXXXXX..XXXXXXX 100644
37
static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
29
--- a/fpu/softfloat-specialize.c.inc
38
{
30
+++ b/fpu/softfloat-specialize.c.inc
39
+ unsigned vsz = vec_full_reg_size(s);
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
40
+ unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
41
+
33
/* Sign bit clear, all frac bits set */
42
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
34
dnan_pattern = 0b01111111;
43
return false;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
44
}
36
- /* Sign bit set, most significant frac bit set */
45
- if (sve_access_check(s)) {
37
- dnan_pattern = 0b11000000;
46
- unsigned vsz = vec_full_reg_size(s);
38
#elif defined(TARGET_HPPA)
47
- unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
39
/* Sign bit clear, msb-1 frac bit set */
48
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
40
dnan_pattern = 0b00100000;
49
- vec_full_reg_offset(s, a->rn),
50
- vec_full_reg_offset(s, a->rm),
51
- vsz, vsz, high_ofs, gen_helper_sve2_zip_q);
52
- }
53
- return true;
54
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_zip_q, a, high_ofs);
55
}
56
57
static bool trans_ZIP1_q(DisasContext *s, arg_rrr_esz *a)
58
--
41
--
59
2.25.1
42
2.34.1
diff view generated by jsdifflib
[PULL 058/117] target/arm: Use TRANS_FEAT for do_perm_pred3
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-56-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 35 ++++++-----------------------------
8
target/hppa/fpu_helper.c | 2 ++
9
1 file changed, 6 insertions(+), 29 deletions(-)
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/hppa/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/hppa/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
16
return true;
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
17
}
22
}
18
23
19
-static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a)
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
20
-{
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
21
- return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p);
26
index XXXXXXX..XXXXXXX 100644
22
-}
27
--- a/fpu/softfloat-specialize.c.inc
23
-
28
+++ b/fpu/softfloat-specialize.c.inc
24
-static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a)
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
25
-{
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
26
- return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p);
31
/* Sign bit clear, all frac bits set */
27
-}
32
dnan_pattern = 0b01111111;
28
-
33
-#elif defined(TARGET_HPPA)
29
-static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a)
34
- /* Sign bit clear, msb-1 frac bit set */
30
-{
35
- dnan_pattern = 0b00100000;
31
- return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p);
36
#elif defined(TARGET_HEXAGON)
32
-}
37
/* Sign bit set, all frac bits set. */
33
-
38
dnan_pattern = 0b11111111;
34
-static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a)
35
-{
36
- return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p);
37
-}
38
-
39
-static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a)
40
-{
41
- return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p);
42
-}
43
-
44
-static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a)
45
-{
46
- return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p);
47
-}
48
+TRANS_FEAT(ZIP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_zip_p)
49
+TRANS_FEAT(ZIP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_zip_p)
50
+TRANS_FEAT(UZP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_uzp_p)
51
+TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p)
52
+TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p)
53
+TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p)
54
55
static bool trans_REV_p(DisasContext *s, arg_rr_esz *a)
56
{
57
--
39
--
58
2.25.1
40
2.34.1
diff view generated by jsdifflib
[PULL 060/117] target/arm: Move sve zip high_ofs into simd_data
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for the alpha target.
2
2
3
This is in line with how we treat uzp, and will
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
eliminate the special case code during translation.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
7
Message-id: 20220527181907.189259-58-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/sve_helper.c | 6 ++++--
12
target/arm/translate-sve.c | 12 ++++++------
13
2 files changed, 10 insertions(+), 8 deletions(-)
14
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve_helper.c
12
--- a/target/alpha/cpu.c
18
+++ b/target/arm/sve_helper.c
13
+++ b/target/alpha/cpu.c
19
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc)
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
20
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
15
* operand in Fa. That is float_2nan_prop_ba.
21
{ \
16
*/
22
intptr_t oprsz = simd_oprsz(desc); \
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
23
+ intptr_t odd_ofs = simd_data(desc); \
18
+ /* Default NaN: sign bit clear, msb frac bit set */
24
intptr_t i, oprsz_2 = oprsz / 2; \
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
25
ARMVectorReg tmp_n, tmp_m; \
20
#if defined(CONFIG_USER_ONLY)
26
/* We produce output faster than we consume input. \
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
27
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
28
vm = memcpy(&tmp_m, vm, oprsz_2); \
29
} \
30
for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
31
- *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + H(i)); \
32
- *(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = *(TYPE *)(vm + H(i)); \
33
+ *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + odd_ofs + H(i)); \
34
+ *(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = \
35
+ *(TYPE *)(vm + odd_ofs + H(i)); \
36
} \
37
if (sizeof(TYPE) == 16 && unlikely(oprsz & 16)) { \
38
memset(vd + oprsz - 16, 0, 16); \
39
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate-sve.c
42
+++ b/target/arm/translate-sve.c
43
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
44
unsigned vsz = vec_full_reg_size(s);
45
unsigned high_ofs = high ? vsz / 2 : 0;
46
tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
47
- vec_full_reg_offset(s, a->rn) + high_ofs,
48
- vec_full_reg_offset(s, a->rm) + high_ofs,
49
- vsz, vsz, 0, fns[a->esz]);
50
+ vec_full_reg_offset(s, a->rn),
51
+ vec_full_reg_offset(s, a->rm),
52
+ vsz, vsz, high_ofs, fns[a->esz]);
53
}
54
return true;
55
}
56
@@ -XXX,XX +XXX,XX @@ static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
57
unsigned vsz = vec_full_reg_size(s);
58
unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
59
tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
60
- vec_full_reg_offset(s, a->rn) + high_ofs,
61
- vec_full_reg_offset(s, a->rm) + high_ofs,
62
- vsz, vsz, 0, gen_helper_sve2_zip_q);
63
+ vec_full_reg_offset(s, a->rn),
64
+ vec_full_reg_offset(s, a->rm),
65
+ vsz, vsz, high_ofs, gen_helper_sve2_zip_q);
66
}
67
return true;
68
}
69
--
23
--
70
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 048/117] target/arm: Introduce do_shift_zpzi
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
Share code between the various shifts using arg_rpri_esz.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
9
---
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
4
13
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
6
Message-id: 20220527181907.189259-46-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 68 +++++++++++++++++---------------------
11
1 file changed, 30 insertions(+), 38 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
--- a/linux-user/arm/nwfpe/fpa11.c
16
+++ b/target/arm/translate-sve.c
17
+++ b/linux-user/arm/nwfpe/fpa11.c
17
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
18
return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
19
* this late date.
20
*/
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
22
+ /*
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
25
+ */
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
19
}
27
}
20
28
21
+static bool do_shift_zpzi(DisasContext *s, arg_rpri_esz *a, bool asr,
29
void SetRoundingMode(const unsigned int opcode)
22
+ gen_helper_gvec_3 * const fns[4])
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
23
+{
31
index XXXXXXX..XXXXXXX 100644
24
+ int max;
32
--- a/target/arm/cpu.c
25
+
33
+++ b/target/arm/cpu.c
26
+ if (a->esz < 0) {
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
27
+ /* Invalid tsz encoding -- see tszimm_esz. */
35
* the pseudocode function the arguments are in the order c, a, b.
28
+ return false;
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
29
+ }
37
* and the input NaN if it is signalling
30
+
38
+ * * Default NaN has sign bit clear, msb frac bit set
31
+ /*
39
*/
32
+ * Shift by element size is architecturally valid.
40
static void arm_set_default_fp_behaviours(float_status *s)
33
+ * For arithmetic right-shift, it's the same as by one less.
34
+ * For logical shifts and ASRD, it is a zeroing operation.
35
+ */
36
+ max = 8 << a->esz;
37
+ if (a->imm >= max) {
38
+ if (asr) {
39
+ a->imm = max - 1;
40
+ } else {
41
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
42
+ }
43
+ }
44
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
45
+}
46
+
47
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
48
{
41
{
49
static gen_helper_gvec_3 * const fns[4] = {
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
50
gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
51
gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
52
};
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
53
- if (a->esz < 0) {
46
+ set_float_default_nan_pattern(0b01000000, s);
54
- /* Invalid tsz encoding -- see tszimm_esz. */
55
- return false;
56
- }
57
- /* Shift by element size is architecturally valid. For
58
- arithmetic right-shift, it's the same as by one less. */
59
- a->imm = MIN(a->imm, (8 << a->esz) - 1);
60
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
61
+ return do_shift_zpzi(s, a, true, fns);
62
}
47
}
63
48
64
static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
65
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
66
gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
67
gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
68
};
69
- if (a->esz < 0) {
70
- return false;
71
- }
72
- /* Shift by element size is architecturally valid.
73
- For logical shifts, it is a zeroing operation. */
74
- if (a->imm >= (8 << a->esz)) {
75
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
76
- } else {
77
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
78
- }
79
+ return do_shift_zpzi(s, a, false, fns);
80
}
81
82
static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
83
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
84
gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
85
gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
86
};
87
- if (a->esz < 0) {
88
- return false;
89
- }
90
- /* Shift by element size is architecturally valid.
91
- For logical shifts, it is a zeroing operation. */
92
- if (a->imm >= (8 << a->esz)) {
93
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
94
- } else {
95
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
96
- }
97
+ return do_shift_zpzi(s, a, false, fns);
98
}
99
100
static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
101
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
102
gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
103
gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
104
};
105
- if (a->esz < 0) {
106
- return false;
107
- }
108
- /* Shift by element size is architecturally valid. For arithmetic
109
- right shift for division, it is a zeroing operation. */
110
- if (a->imm >= (8 << a->esz)) {
111
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
112
- } else {
113
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
114
- }
115
+ return do_shift_zpzi(s, a, false, fns);
116
}
117
118
static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
119
--
50
--
120
2.25.1
51
2.34.1
diff view generated by jsdifflib
[PULL 057/117] target/arm: Use TRANS_FEAT for do_EXT
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for loongarch.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-55-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 14 ++------------
7
target/loongarch/tcg/fpu_helper.c | 2 ++
9
1 file changed, 2 insertions(+), 12 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
12
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm)
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
return true;
15
*/
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
17
}
20
}
18
21
19
-static bool trans_EXT(DisasContext *s, arg_EXT *a)
22
int ieee_ex_to_loongarch(int xcpt)
20
-{
21
- return do_EXT(s, a->rd, a->rn, a->rm, a->imm);
22
-}
23
-
24
-static bool trans_EXT_sve2(DisasContext *s, arg_rri *a)
25
-{
26
- if (!dc_isar_feature(aa64_sve2, s)) {
27
- return false;
28
- }
29
- return do_EXT(s, a->rd, a->rn, (a->rn + 1) % 32, a->imm);
30
-}
31
+TRANS_FEAT(EXT, aa64_sve, do_EXT, a->rd, a->rn, a->rm, a->imm)
32
+TRANS_FEAT(EXT_sve2, aa64_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) % 32, a->imm)
33
34
/*
35
*** SVE Permute - Unpredicated Group
36
--
23
--
37
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 059/117] target/arm: Use TRANS_FEAT for do_perm_pred2
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for m68k.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-57-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 17 +++--------------
7
target/m68k/cpu.c | 2 ++
9
1 file changed, 3 insertions(+), 14 deletions(-)
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
13
--- a/target/m68k/cpu.c
14
+++ b/target/arm/translate-sve.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p)
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p)
16
* preceding paragraph for nonsignaling NaNs.
17
TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p)
17
*/
18
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
-static bool trans_REV_p(DisasContext *s, arg_rr_esz *a)
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
-{
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
- return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p);
21
22
-}
22
nan = floatx80_default_nan(&env->fp_status);
23
-
23
for (i = 0; i < 8; i++) {
24
-static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
-{
25
index XXXXXXX..XXXXXXX 100644
26
- return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p);
26
--- a/fpu/softfloat-specialize.c.inc
27
-}
27
+++ b/fpu/softfloat-specialize.c.inc
28
-
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
-static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
-{
30
31
- return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p);
31
if (dnan_pattern == 0) {
32
-}
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+TRANS_FEAT(REV_p, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_rev_p)
33
+#if defined(TARGET_SPARC)
34
+TRANS_FEAT(PUNPKLO, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_punpk_p)
34
/* Sign bit clear, all frac bits set */
35
+TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p)
35
dnan_pattern = 0b01111111;
36
36
#elif defined(TARGET_HEXAGON)
37
/*
38
*** SVE Permute - Interleaving Group
39
--
37
--
40
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 032/117] target/arm: Merge gen_gvec_fn_zz into do_mov_z
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
2
5
3
There is only one caller for gen_gvec_fn_zz; inline it.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
---
10
target/mips/fpu_helper.h | 7 +++++++
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
4
13
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
6
Message-id: 20220527181907.189259-30-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 13 +++----------
11
1 file changed, 3 insertions(+), 10 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
--- a/target/mips/fpu_helper.h
16
+++ b/target/arm/translate-sve.c
17
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
18
return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
22
+ /*
23
+ * With nan2008, the default NaN value has the sign bit clear and the
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
25
+ * frac bits except the msb are set.
26
+ */
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
28
+ &env->active_fpu.fp_status);
29
19
}
30
}
20
31
21
-/* Invoke a vector expander on two Zregs. */
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
22
-static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
33
index XXXXXXX..XXXXXXX 100644
23
- int esz, int rd, int rn)
34
--- a/target/mips/msa.c
24
-{
35
+++ b/target/mips/msa.c
25
- unsigned vsz = vec_full_reg_size(s);
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
26
- gvec_fn(esz, vec_full_reg_offset(s, rd),
37
/* Inf * 0 + NaN returns the input NaN */
27
- vec_full_reg_offset(s, rn), vsz, vsz);
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
28
-}
39
&env->active_tc.msa_fp_status);
29
-
40
+ /* Default NaN: sign bit clear, frac msb set */
30
/* Invoke a vector expander on three Zregs. */
41
+ set_float_default_nan_pattern(0b01000000,
31
static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
42
+ &env->active_tc.msa_fp_status);
32
int esz, int rd, int rn, int rm)
33
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
34
static bool do_mov_z(DisasContext *s, int rd, int rn)
35
{
36
if (sve_access_check(s)) {
37
- gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
38
+ unsigned vsz = vec_full_reg_size(s);
39
+ tcg_gen_gvec_mov(MO_8, vec_full_reg_offset(s, rd),
40
+ vec_full_reg_offset(s, rn), vsz, vsz);
41
}
42
return true;
43
}
43
}
44
--
44
--
45
2.25.1
45
2.34.1
diff view generated by jsdifflib
[PULL 056/117] target/arm: Use TRANS_FEAT for do_pfirst_pnext
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for openrisc.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-54-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 11 ++---------
7
target/openrisc/cpu.c | 2 ++
9
1 file changed, 2 insertions(+), 9 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
12
--- a/target/openrisc/cpu.c
14
+++ b/target/arm/translate-sve.c
13
+++ b/target/openrisc/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
16
return true;
15
*/
17
}
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
18
17
19
-static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a)
18
+ /* Default NaN: sign bit clear, frac msb set */
20
-{
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
21
- return do_pfirst_pnext(s, a, gen_helper_sve_pfirst);
20
22
-}
21
#ifndef CONFIG_USER_ONLY
23
-
22
cpu->env.picmr = 0x00000000;
24
-static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
25
-{
26
- return do_pfirst_pnext(s, a, gen_helper_sve_pnext);
27
-}
28
+TRANS_FEAT(PFIRST, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pfirst)
29
+TRANS_FEAT(PNEXT, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pnext)
30
31
/*
32
*** SVE Element Count Group
33
--
23
--
34
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 018/117] target/arm: Use TRANS_FEAT for do_sve2_zzz_data
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for ppc.
2
2
3
Convert SVE translation functions using do_sve2_zzz_data
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
to use TRANS_FEAT and gen_gvec_ool_zzz.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
6
---
7
target/ppc/cpu_init.c | 4 ++++
8
1 file changed, 4 insertions(+)
5
9
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
7
Message-id: 20220527181907.189259-16-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 69 ++++++++++++++------------------------
12
1 file changed, 25 insertions(+), 44 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
12
--- a/target/ppc/cpu_init.c
17
+++ b/target/arm/translate-sve.c
13
+++ b/target/ppc/cpu_init.c
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SUDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
19
TRANS_FEAT(USDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
gen_helper_gvec_usdot_idx_b, a)
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
21
17
22
-static bool do_sve2_zzz_data(DisasContext *s, int rd, int rn, int rm, int data,
18
+ /* Default NaN: sign bit clear, set frac msb */
23
- gen_helper_gvec_3 *fn)
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
24
-{
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
21
+
26
- return false;
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
27
- }
23
ppc_spr_t *spr = &env->spr_cb[i];
28
- if (sve_access_check(s)) {
29
- unsigned vsz = vec_full_reg_size(s);
30
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
31
- vec_full_reg_offset(s, rn),
32
- vec_full_reg_offset(s, rm),
33
- vsz, vsz, data, fn);
34
- }
35
- return true;
36
-}
37
-
38
#define DO_SVE2_RRX(NAME, FUNC) \
39
- static bool NAME(DisasContext *s, arg_rrx_esz *a) \
40
- { return do_sve2_zzz_data(s, a->rd, a->rn, a->rm, a->index, FUNC); }
41
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \
42
+ a->rd, a->rn, a->rm, a->index)
43
44
-DO_SVE2_RRX(trans_MUL_zzx_h, gen_helper_gvec_mul_idx_h)
45
-DO_SVE2_RRX(trans_MUL_zzx_s, gen_helper_gvec_mul_idx_s)
46
-DO_SVE2_RRX(trans_MUL_zzx_d, gen_helper_gvec_mul_idx_d)
47
+DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h)
48
+DO_SVE2_RRX(MUL_zzx_s, gen_helper_gvec_mul_idx_s)
49
+DO_SVE2_RRX(MUL_zzx_d, gen_helper_gvec_mul_idx_d)
50
51
-DO_SVE2_RRX(trans_SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h)
52
-DO_SVE2_RRX(trans_SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s)
53
-DO_SVE2_RRX(trans_SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d)
54
+DO_SVE2_RRX(SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h)
55
+DO_SVE2_RRX(SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s)
56
+DO_SVE2_RRX(SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d)
57
58
-DO_SVE2_RRX(trans_SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h)
59
-DO_SVE2_RRX(trans_SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s)
60
-DO_SVE2_RRX(trans_SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d)
61
+DO_SVE2_RRX(SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h)
62
+DO_SVE2_RRX(SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s)
63
+DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d)
64
65
#undef DO_SVE2_RRX
66
67
#define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \
68
- static bool NAME(DisasContext *s, arg_rrx_esz *a) \
69
- { \
70
- return do_sve2_zzz_data(s, a->rd, a->rn, a->rm, \
71
- (a->index << 1) | TOP, FUNC); \
72
- }
73
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \
74
+ a->rd, a->rn, a->rm, (a->index << 1) | TOP)
75
76
-DO_SVE2_RRX_TB(trans_SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false)
77
-DO_SVE2_RRX_TB(trans_SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false)
78
-DO_SVE2_RRX_TB(trans_SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true)
79
-DO_SVE2_RRX_TB(trans_SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true)
80
+DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false)
81
+DO_SVE2_RRX_TB(SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false)
82
+DO_SVE2_RRX_TB(SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true)
83
+DO_SVE2_RRX_TB(SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true)
84
85
-DO_SVE2_RRX_TB(trans_SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false)
86
-DO_SVE2_RRX_TB(trans_SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false)
87
-DO_SVE2_RRX_TB(trans_SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true)
88
-DO_SVE2_RRX_TB(trans_SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true)
89
+DO_SVE2_RRX_TB(SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false)
90
+DO_SVE2_RRX_TB(SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false)
91
+DO_SVE2_RRX_TB(SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true)
92
+DO_SVE2_RRX_TB(SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true)
93
94
-DO_SVE2_RRX_TB(trans_UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false)
95
-DO_SVE2_RRX_TB(trans_UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false)
96
-DO_SVE2_RRX_TB(trans_UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true)
97
-DO_SVE2_RRX_TB(trans_UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
98
+DO_SVE2_RRX_TB(UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false)
99
+DO_SVE2_RRX_TB(UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false)
100
+DO_SVE2_RRX_TB(UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true)
101
+DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
102
103
#undef DO_SVE2_RRX_TB
104
24
105
--
25
--
106
2.25.1
26
2.34.1
diff view generated by jsdifflib
[PULL 055/117] target/arm: Use TRANS_FEAT for RDFFR, WRFFR
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
2
4
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-53-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
7
---
8
---
8
target/arm/translate-sve.c | 11 ++---------
9
target/sh4/cpu.c | 2 ++
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
1 file changed, 2 insertions(+)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/sh4/cpu.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/sh4/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
16
return trans_AND_pppp(s, &alt_a);
17
set_flush_to_zero(1, &env->fp_status);
18
#endif
19
set_default_nan_mode(1, &env->fp_status);
20
+ /* sign bit clear, set all frac bits other than msb */
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
17
}
22
}
18
23
19
-static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a)
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
20
-{
21
- return do_mov_p(s, a->rd, FFR_PRED_NUM);
22
-}
23
-
24
-static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a)
25
-{
26
- return do_mov_p(s, FFR_PRED_NUM, a->rn);
27
-}
28
+TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM)
29
+TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn)
30
31
static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
32
void (*gen_fn)(TCGv_i32, TCGv_ptr,
33
--
25
--
34
2.25.1
26
2.34.1
diff view generated by jsdifflib
[PULL 054/117] target/arm: Use TRANS_FEAT for do_predset
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for rx.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-52-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 19 +++++--------------
7
target/rx/cpu.c | 2 ++
9
1 file changed, 5 insertions(+), 14 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
12
--- a/target/rx/cpu.c
14
+++ b/target/arm/translate-sve.c
13
+++ b/target/rx/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
16
return true;
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
17
}
20
}
18
21
19
-static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a)
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
20
-{
21
- return do_predset(s, a->esz, a->rd, a->pat, a->s);
22
-}
23
+TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s)
24
25
-static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a)
26
-{
27
- /* Note pat == 31 is #all, to set all elements. */
28
- return do_predset(s, 0, FFR_PRED_NUM, 31, false);
29
-}
30
+/* Note pat == 31 is #all, to set all elements. */
31
+TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false)
32
33
-static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a)
34
-{
35
- /* Note pat == 32 is #unimp, to set no elements. */
36
- return do_predset(s, 0, a->rd, 32, false);
37
-}
38
+/* Note pat == 32 is #unimp, to set no elements. */
39
+TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false)
40
41
static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
42
{
43
--
23
--
44
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 053/117] target/arm: Use TRANS_FEAT for do_adr
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for s390x.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-51-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 23 ++++-------------------
7
target/s390x/cpu.c | 2 ++
9
1 file changed, 4 insertions(+), 19 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
12
--- a/target/s390x/cpu.c
14
+++ b/target/arm/translate-sve.c
13
+++ b/target/s390x/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
16
return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
17
}
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
18
17
&env->fpu_status);
19
-static bool trans_ADR_p32(DisasContext *s, arg_rrri *a)
18
+ /* Default NaN value: sign bit clear, frac msb set */
20
-{
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
21
- return do_adr(s, a, gen_helper_sve_adr_p32);
20
/* fall through */
22
-}
21
case RESET_TYPE_S390_CPU_NORMAL:
23
-
22
env->psw.mask &= ~PSW_MASK_RI;
24
-static bool trans_ADR_p64(DisasContext *s, arg_rrri *a)
25
-{
26
- return do_adr(s, a, gen_helper_sve_adr_p64);
27
-}
28
-
29
-static bool trans_ADR_s32(DisasContext *s, arg_rrri *a)
30
-{
31
- return do_adr(s, a, gen_helper_sve_adr_s32);
32
-}
33
-
34
-static bool trans_ADR_u32(DisasContext *s, arg_rrri *a)
35
-{
36
- return do_adr(s, a, gen_helper_sve_adr_u32);
37
-}
38
+TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
39
+TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
40
+TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
41
+TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
42
43
/*
44
*** SVE Integer Misc - Unpredicated Group
45
--
23
--
46
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 052/117] target/arm: Use TRANS_FEAT for do_index
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-50-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 35 ++++++++---------------------------
8
target/sparc/cpu.c | 2 ++
9
1 file changed, 8 insertions(+), 27 deletions(-)
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/sparc/cpu.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/sparc/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_index(DisasContext *s, int esz, int rd,
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
16
return true;
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
17
}
18
/* For inf * 0 + NaN, return the input NaN */
18
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
19
-static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
20
+ /* Default NaN value: sign bit clear, all frac bits set */
20
-{
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
- TCGv_i64 start = tcg_constant_i64(a->imm1);
22
22
- TCGv_i64 incr = tcg_constant_i64(a->imm2);
23
cpu_exec_realizefn(cs, &local_err);
23
- return do_index(s, a->esz, a->rd, start, incr);
24
if (local_err != NULL) {
24
-}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
-
26
index XXXXXXX..XXXXXXX 100644
26
-static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
27
--- a/fpu/softfloat-specialize.c.inc
27
-{
28
+++ b/fpu/softfloat-specialize.c.inc
28
- TCGv_i64 start = tcg_constant_i64(a->imm);
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
- TCGv_i64 incr = cpu_reg(s, a->rm);
30
uint8_t dnan_pattern = status->default_nan_pattern;
30
- return do_index(s, a->esz, a->rd, start, incr);
31
31
-}
32
if (dnan_pattern == 0) {
32
-
33
-#if defined(TARGET_SPARC)
33
-static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
34
- /* Sign bit clear, all frac bits set */
34
-{
35
- dnan_pattern = 0b01111111;
35
- TCGv_i64 start = cpu_reg(s, a->rn);
36
-#elif defined(TARGET_HEXAGON)
36
- TCGv_i64 incr = tcg_constant_i64(a->imm);
37
+#if defined(TARGET_HEXAGON)
37
- return do_index(s, a->esz, a->rd, start, incr);
38
/* Sign bit set, all frac bits set. */
38
-}
39
dnan_pattern = 0b11111111;
39
-
40
#else
40
-static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
41
-{
42
- TCGv_i64 start = cpu_reg(s, a->rn);
43
- TCGv_i64 incr = cpu_reg(s, a->rm);
44
- return do_index(s, a->esz, a->rd, start, incr);
45
-}
46
+TRANS_FEAT(INDEX_ii, aa64_sve, do_index, a->esz, a->rd,
47
+ tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2))
48
+TRANS_FEAT(INDEX_ir, aa64_sve, do_index, a->esz, a->rd,
49
+ tcg_constant_i64(a->imm), cpu_reg(s, a->rm))
50
+TRANS_FEAT(INDEX_ri, aa64_sve, do_index, a->esz, a->rd,
51
+ cpu_reg(s, a->rn), tcg_constant_i64(a->imm))
52
+TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->rd,
53
+ cpu_reg(s, a->rn), cpu_reg(s, a->rm))
54
55
/*
56
*** SVE Stack Allocation Group
57
--
41
--
58
2.25.1
42
2.34.1
diff view generated by jsdifflib
[PULL 083/117] target/arm: Implement NOT (prediates) alias
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for xtensa.
2
2
3
This alias is defined on EOR (prediates). While the
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
same operation could be performed with NAND or NOR,
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
only bother with the official alias.
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
6
---
7
target/xtensa/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
6
9
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
8
Message-id: 20220527181907.189259-81-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 5 +++++
13
1 file changed, 5 insertions(+)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
12
--- a/target/xtensa/cpu.c
18
+++ b/target/arm/translate-sve.c
13
+++ b/target/xtensa/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
20
.fno = gen_helper_sve_eor_pppp,
15
/* For inf * 0 + NaN, return the input NaN */
21
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
};
17
set_no_signaling_nans(!dfpu, &env->fp_status);
23
+
18
+ /* Default NaN value: sign bit clear, set frac msb */
24
+ /* Alias NOT (predicate) is EOR Pd.B, Pg/Z, Pn.B, Pg.B */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
25
+ if (!a->s && a->pg == a->rm) {
20
xtensa_use_first_nan(env, !dfpu);
26
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->pg, a->rn);
27
+ }
28
return do_pppp_flags(s, a, &op);
29
}
21
}
30
22
31
--
23
--
32
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 046/117] target/arm: Use TRANS_FEAT for do_vpz_ool
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
2
4
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-44-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
7
---
8
---
8
target/arm/translate-sve.c | 20 +++++++-------------
9
target/hexagon/cpu.c | 2 ++
9
1 file changed, 7 insertions(+), 13 deletions(-)
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
10
12
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
15
--- a/target/hexagon/cpu.c
14
+++ b/target/arm/translate-sve.c
16
+++ b/target/hexagon/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
18
19
set_default_nan_mode(1, &env->fp_status);
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
21
+ /* Default NaN value: sign bit set, all frac bits set */
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
16
}
23
}
17
24
18
#define DO_VPZ(NAME, name) \
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
19
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
20
-{ \
27
index XXXXXXX..XXXXXXX 100644
21
- static gen_helper_gvec_reduc * const fns[4] = { \
28
--- a/fpu/softfloat-specialize.c.inc
22
+ static gen_helper_gvec_reduc * const name##_fns[4] = { \
29
+++ b/fpu/softfloat-specialize.c.inc
23
gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
24
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
31
uint8_t dnan_pattern = status->default_nan_pattern;
25
}; \
32
26
- return do_vpz_ool(s, a, fns[a->esz]); \
33
if (dnan_pattern == 0) {
27
-}
34
-#if defined(TARGET_HEXAGON)
28
+ TRANS_FEAT(NAME, aa64_sve, do_vpz_ool, a, name##_fns[a->esz])
35
- /* Sign bit set, all frac bits set. */
29
36
- dnan_pattern = 0b11111111;
30
DO_VPZ(ORV, orv)
37
-#else
31
DO_VPZ(ANDV, andv)
38
/*
32
@@ -XXX,XX +XXX,XX @@ DO_VPZ(UMAXV, umaxv)
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
33
DO_VPZ(SMINV, sminv)
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
34
DO_VPZ(UMINV, uminv)
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
35
42
/* sign bit clear, set frac msb */
36
-static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a)
43
dnan_pattern = 0b01000000;
37
-{
44
}
38
- static gen_helper_gvec_reduc * const fns[4] = {
45
-#endif
39
- gen_helper_sve_saddv_b, gen_helper_sve_saddv_h,
46
}
40
- gen_helper_sve_saddv_s, NULL
47
assert(dnan_pattern != 0);
41
- };
42
- return do_vpz_ool(s, a, fns[a->esz]);
43
-}
44
+static gen_helper_gvec_reduc * const saddv_fns[4] = {
45
+ gen_helper_sve_saddv_b, gen_helper_sve_saddv_h,
46
+ gen_helper_sve_saddv_s, NULL
47
+};
48
+TRANS_FEAT(SADDV, aa64_sve, do_vpz_ool, a, saddv_fns[a->esz])
49
50
#undef DO_VPZ
51
48
52
--
49
--
53
2.25.1
50
2.34.1
diff view generated by jsdifflib
[PULL 051/117] target/arm: Move sve check into do_index
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for riscv.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-49-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 53 ++++++++++++++++++--------------------
7
target/riscv/cpu.c | 2 ++
9
1 file changed, 25 insertions(+), 28 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
12
--- a/target/riscv/cpu.c
14
+++ b/target/arm/translate-sve.c
13
+++ b/target/riscv/cpu.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz])
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
16
*** SVE Index Generation Group
15
cs->exception_index = RISCV_EXCP_NONE;
17
*/
16
env->load_res = -1;
18
17
set_default_nan_mode(1, &env->fp_status);
19
-static void do_index(DisasContext *s, int esz, int rd,
18
+ /* Default NaN value: sign bit clear, frac msb set */
20
+static bool do_index(DisasContext *s, int esz, int rd,
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
TCGv_i64 start, TCGv_i64 incr)
20
env->vill = true;
22
{
21
23
- unsigned vsz = vec_full_reg_size(s);
22
#ifndef CONFIG_USER_ONLY
24
- TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
25
- TCGv_ptr t_zd = tcg_temp_new_ptr();
26
+ unsigned vsz;
27
+ TCGv_i32 desc;
28
+ TCGv_ptr t_zd;
29
+
30
+ if (!sve_access_check(s)) {
31
+ return true;
32
+ }
33
+
34
+ vsz = vec_full_reg_size(s);
35
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
36
+ t_zd = tcg_temp_new_ptr();
37
38
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
39
if (esz == 3) {
40
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
41
tcg_temp_free_i32(i32);
42
}
43
tcg_temp_free_ptr(t_zd);
44
+ return true;
45
}
46
47
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
48
{
49
- if (sve_access_check(s)) {
50
- TCGv_i64 start = tcg_constant_i64(a->imm1);
51
- TCGv_i64 incr = tcg_constant_i64(a->imm2);
52
- do_index(s, a->esz, a->rd, start, incr);
53
- }
54
- return true;
55
+ TCGv_i64 start = tcg_constant_i64(a->imm1);
56
+ TCGv_i64 incr = tcg_constant_i64(a->imm2);
57
+ return do_index(s, a->esz, a->rd, start, incr);
58
}
59
60
static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
61
{
62
- if (sve_access_check(s)) {
63
- TCGv_i64 start = tcg_constant_i64(a->imm);
64
- TCGv_i64 incr = cpu_reg(s, a->rm);
65
- do_index(s, a->esz, a->rd, start, incr);
66
- }
67
- return true;
68
+ TCGv_i64 start = tcg_constant_i64(a->imm);
69
+ TCGv_i64 incr = cpu_reg(s, a->rm);
70
+ return do_index(s, a->esz, a->rd, start, incr);
71
}
72
73
static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
74
{
75
- if (sve_access_check(s)) {
76
- TCGv_i64 start = cpu_reg(s, a->rn);
77
- TCGv_i64 incr = tcg_constant_i64(a->imm);
78
- do_index(s, a->esz, a->rd, start, incr);
79
- }
80
- return true;
81
+ TCGv_i64 start = cpu_reg(s, a->rn);
82
+ TCGv_i64 incr = tcg_constant_i64(a->imm);
83
+ return do_index(s, a->esz, a->rd, start, incr);
84
}
85
86
static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
87
{
88
- if (sve_access_check(s)) {
89
- TCGv_i64 start = cpu_reg(s, a->rn);
90
- TCGv_i64 incr = cpu_reg(s, a->rm);
91
- do_index(s, a->esz, a->rd, start, incr);
92
- }
93
- return true;
94
+ TCGv_i64 start = cpu_reg(s, a->rn);
95
+ TCGv_i64 incr = cpu_reg(s, a->rm);
96
+ return do_index(s, a->esz, a->rd, start, incr);
97
}
98
99
/*
100
--
23
--
101
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 049/117] target/arm: Use TRANS_FEAT for do_shift_zpzi
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for tricore.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-47-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 52 +++++++++++++++-----------------------
7
target/tricore/helper.c | 2 ++
9
1 file changed, 20 insertions(+), 32 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
12
--- a/target/tricore/helper.c
14
+++ b/target/arm/translate-sve.c
13
+++ b/target/tricore/helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_shift_zpzi(DisasContext *s, arg_rpri_esz *a, bool asr,
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
16
return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
15
set_flush_to_zero(1, &env->fp_status);
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
17
set_default_nan_mode(1, &env->fp_status);
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
17
}
20
}
18
21
19
-static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
22
uint32_t psw_read(CPUTriCoreState *env)
20
-{
21
- static gen_helper_gvec_3 * const fns[4] = {
22
- gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
23
- gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
24
- };
25
- return do_shift_zpzi(s, a, true, fns);
26
-}
27
+static gen_helper_gvec_3 * const asr_zpzi_fns[4] = {
28
+ gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
29
+ gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
30
+};
31
+TRANS_FEAT(ASR_zpzi, aa64_sve, do_shift_zpzi, a, true, asr_zpzi_fns)
32
33
-static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
34
-{
35
- static gen_helper_gvec_3 * const fns[4] = {
36
- gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
37
- gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
38
- };
39
- return do_shift_zpzi(s, a, false, fns);
40
-}
41
+static gen_helper_gvec_3 * const lsr_zpzi_fns[4] = {
42
+ gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
43
+ gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
44
+};
45
+TRANS_FEAT(LSR_zpzi, aa64_sve, do_shift_zpzi, a, false, lsr_zpzi_fns)
46
47
-static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
48
-{
49
- static gen_helper_gvec_3 * const fns[4] = {
50
- gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
51
- gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
52
- };
53
- return do_shift_zpzi(s, a, false, fns);
54
-}
55
+static gen_helper_gvec_3 * const lsl_zpzi_fns[4] = {
56
+ gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
57
+ gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
58
+};
59
+TRANS_FEAT(LSL_zpzi, aa64_sve, do_shift_zpzi, a, false, lsl_zpzi_fns)
60
61
-static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
62
-{
63
- static gen_helper_gvec_3 * const fns[4] = {
64
- gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
65
- gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
66
- };
67
- return do_shift_zpzi(s, a, false, fns);
68
-}
69
+static gen_helper_gvec_3 * const asrd_fns[4] = {
70
+ gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
71
+ gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
72
+};
73
+TRANS_FEAT(ASRD, aa64_sve, do_shift_zpzi, a, false, asrd_fns)
74
75
static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
76
gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
77
--
23
--
78
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 001/117] docs/system/arm: Add FEAT_HCX to list of emulated features
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
In commit 5814d587fe861fe9 we added support for emulating
1
Now that all our targets have bene converted to explicitly specify
2
FEAT_HCX (Support for the HCRX_EL2 register). However we
2
their pattern for the default NaN value we can remove the remaining
3
forgot to add it to the list in emulated.rst. Correct the
3
fallback code in parts64_default_nan().
4
omission.
5
4
6
Fixes: 5814d587fe861fe9 ("target/arm: Enable FEAT_HCX for -cpu max")
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220520084320.424166-1-peter.maydell@linaro.org
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
10
---
8
---
11
docs/system/arm/emulation.rst | 1 +
9
fpu/softfloat-specialize.c.inc | 14 --------------
12
1 file changed, 1 insertion(+)
10
1 file changed, 14 deletions(-)
13
11
14
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/emulation.rst
14
--- a/fpu/softfloat-specialize.c.inc
17
+++ b/docs/system/arm/emulation.rst
15
+++ b/fpu/softfloat-specialize.c.inc
18
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
19
- FEAT_FRINTTS (Floating-point to integer instructions)
17
uint64_t frac;
20
- FEAT_FlagM (Flag manipulation instructions v2)
18
uint8_t dnan_pattern = status->default_nan_pattern;
21
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
19
22
+- FEAT_HCX (Support for the HCRX_EL2 register)
20
- if (dnan_pattern == 0) {
23
- FEAT_HPDS (Hierarchical permission disables)
21
- /*
24
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
25
- FEAT_IDST (ID space trap handling)
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
24
- * do not have floating-point.
25
- */
26
- if (snan_bit_is_one(status)) {
27
- /* sign bit clear, set all frac bits other than msb */
28
- dnan_pattern = 0b00111111;
29
- } else {
30
- /* sign bit clear, set frac msb */
31
- dnan_pattern = 0b01000000;
32
- }
33
- }
34
assert(dnan_pattern != 0);
35
36
sign = dnan_pattern >> 7;
26
--
37
--
27
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 037/117] target/arm: Use TRANS_FEAT for do_sve2_fn_zzz
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Convert SVE translation functions using do_sve2_fn_zzz
3
Inline pickNaNMulAdd into its only caller. This makes
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzz.
4
one assert redundant with the immediately preceding IF.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-35-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-sve.c | 19 ++-----------------
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
12
1 file changed, 2 insertions(+), 17 deletions(-)
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
14
2 files changed, 40 insertions(+), 55 deletions(-)
13
15
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
18
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-sve.c
19
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SLI(DisasContext *s, arg_rri_esz *a)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
return do_sve2_fn2i(s, a, gen_gvec_sli);
21
}
22
23
if (s->default_nan_mode) {
24
+ /*
25
+ * We guarantee not to require the target to tell us how to
26
+ * pick a NaN if we're always returning the default NaN.
27
+ * But if we're not in default-NaN mode then the target must
28
+ * specify.
29
+ */
30
which = 3;
31
+ } else if (infzero) {
32
+ /*
33
+ * Inf * 0 + NaN -- some implementations return the
34
+ * default NaN here, and some return the input NaN.
35
+ */
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
53
+
54
+ assert(rule != float_3nan_prop_none);
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
56
+ /* We have at least one SNaN input and should prefer it */
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
61
+ } else {
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
66
+ }
67
}
68
69
if (which == 3) {
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
71
index XXXXXXX..XXXXXXX 100644
72
--- a/fpu/softfloat-specialize.c.inc
73
+++ b/fpu/softfloat-specialize.c.inc
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
75
}
20
}
76
}
21
77
22
-static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
78
-/*----------------------------------------------------------------------------
79
-| Select which NaN to propagate for a three-input operation.
80
-| For the moment we assume that no CPU needs the 'larger significand'
81
-| information.
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
83
-*----------------------------------------------------------------------------*/
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
85
- bool infzero, bool have_snan, float_status *status)
23
-{
86
-{
24
- if (!dc_isar_feature(aa64_sve2, s)) {
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
25
- return false;
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
89
- int which;
90
-
91
- /*
92
- * We guarantee not to require the target to tell us how to
93
- * pick a NaN if we're always returning the default NaN.
94
- * But if we're not in default-NaN mode then the target must
95
- * specify.
96
- */
97
- assert(!status->default_nan_mode);
98
-
99
- if (infzero) {
100
- /*
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
106
- return 2;
107
- case float_infzeronan_dnan_always:
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
26
- }
114
- }
27
- return gen_gvec_fn_arg_zzz(s, fn, a);
115
-
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
123
- } else {
124
- do {
125
- which = rule & R_3NAN_1ST_MASK;
126
- rule >>= R_3NAN_1ST_LENGTH;
127
- } while (!is_nan(cls[which]));
128
- }
129
- return which;
28
-}
130
-}
29
-
131
-
30
-static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
132
/*----------------------------------------------------------------------------
31
-{
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
32
- return do_sve2_fn_zzz(s, a, gen_gvec_saba);
134
| NaN; otherwise returns 0.
33
-}
34
-
35
-static bool trans_UABA(DisasContext *s, arg_rrr_esz *a)
36
-{
37
- return do_sve2_fn_zzz(s, a, gen_gvec_uaba);
38
-}
39
+TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a)
40
+TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a)
41
42
static bool do_sve2_narrow_extract(DisasContext *s, arg_rri_esz *a,
43
const GVecGen2 ops[3])
44
--
135
--
45
2.25.1
136
2.34.1
137
138
diff view generated by jsdifflib
[PULL 034/117] target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Rename the function to match gen_gvec_fn_zzz,
3
Remove "3" as a special case for which and simply
4
and move to be adjacent.
4
branch to return the desired value.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-32-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate-sve.c | 31 ++++++++++++++++---------------
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
12
1 file changed, 16 insertions(+), 15 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
13
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-sve.c
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
return true;
19
* But if we're not in default-NaN mode then the target must
20
* specify.
21
*/
22
- which = 3;
23
+ goto default_nan;
24
} else if (infzero) {
25
/*
26
* Inf * 0 + NaN -- some implementations return the
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
28
*/
29
switch (s->float_infzeronan_rule) {
30
case float_infzeronan_dnan_never:
31
- which = 2;
32
break;
33
case float_infzeronan_dnan_always:
34
- which = 3;
35
- break;
36
+ goto default_nan;
37
case float_infzeronan_dnan_if_qnan:
38
- which = is_qnan(c->cls) ? 3 : 2;
39
+ if (is_qnan(c->cls)) {
40
+ goto default_nan;
41
+ }
42
break;
43
default:
44
g_assert_not_reached();
45
}
46
+ which = 2;
47
} else {
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
51
}
52
}
53
54
- if (which == 3) {
55
- parts_default_nan(a, s);
56
- return a;
57
- }
58
-
59
switch (which) {
60
case 0:
61
break;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
63
parts_silence_nan(a, s);
64
}
65
return a;
66
+
67
+ default_nan:
68
+ parts_default_nan(a, s);
69
+ return a;
20
}
70
}
21
22
+static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn,
23
+ arg_rrr_esz *a)
24
+{
25
+ return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
26
+}
27
+
28
/* Invoke a vector expander on four Zregs. */
29
static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
30
int esz, int rd, int rn, int rm, int ra)
31
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
32
*** SVE Logical - Unpredicated Group
33
*/
34
35
-static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
36
-{
37
- return gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
38
-}
39
-
40
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
41
{
42
- return do_zzz_fn(s, a, tcg_gen_gvec_and);
43
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_and, a);
44
}
45
46
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
47
{
48
- return do_zzz_fn(s, a, tcg_gen_gvec_or);
49
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_or, a);
50
}
51
52
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
53
{
54
- return do_zzz_fn(s, a, tcg_gen_gvec_xor);
55
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_xor, a);
56
}
57
58
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
59
{
60
- return do_zzz_fn(s, a, tcg_gen_gvec_andc);
61
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_andc, a);
62
}
63
64
static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh)
65
@@ -XXX,XX +XXX,XX @@ static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
66
67
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
68
{
69
- return do_zzz_fn(s, a, tcg_gen_gvec_add);
70
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_add, a);
71
}
72
73
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
74
{
75
- return do_zzz_fn(s, a, tcg_gen_gvec_sub);
76
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sub, a);
77
}
78
79
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
80
{
81
- return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
82
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ssadd, a);
83
}
84
85
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
86
{
87
- return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
88
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sssub, a);
89
}
90
91
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
92
{
93
- return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
94
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_usadd, a);
95
}
96
97
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
98
{
99
- return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
100
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ussub, a);
101
}
102
71
103
/*
72
/*
104
--
73
--
105
2.25.1
74
2.34.1
75
76
diff view generated by jsdifflib
[PULL 082/117] target/arm: Move sve check into gen_gvec_fn_ppp
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Combined with the check already present in gen_mov_p,
3
Assign the pointer return value to 'a' directly,
4
we can simplify some special cases in trans_AND_pppp
4
rather than going through an intermediary index.
5
and trans_BIC_pppp.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-80-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-sve.c | 30 ++++++++++++------------------
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
13
1 file changed, 12 insertions(+), 18 deletions(-)
12
1 file changed, 10 insertions(+), 22 deletions(-)
14
13
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
16
--- a/fpu/softfloat-parts.c.inc
18
+++ b/target/arm/translate-sve.c
17
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
20
}
19
FloatPartsN *c, float_status *s,
21
20
int ab_mask, int abc_mask)
22
/* Invoke a vector expander on three Pregs. */
23
-static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
24
+static bool gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
25
int rd, int rn, int rm)
26
{
21
{
27
- unsigned psz = pred_gvec_reg_size(s);
22
- int which;
28
- gvec_fn(MO_64, pred_full_reg_offset(s, rd),
23
bool infzero = (ab_mask == float_cmask_infzero);
29
- pred_full_reg_offset(s, rn),
24
bool have_snan = (abc_mask & float_cmask_snan);
30
- pred_full_reg_offset(s, rm), psz, psz);
25
+ FloatPartsN *ret;
31
+ if (sve_access_check(s)) {
26
32
+ unsigned psz = pred_gvec_reg_size(s);
27
if (unlikely(have_snan)) {
33
+ gvec_fn(MO_64, pred_full_reg_offset(s, rd),
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
34
+ pred_full_reg_offset(s, rn),
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
35
+ pred_full_reg_offset(s, rm), psz, psz);
30
default:
36
+ }
31
g_assert_not_reached();
37
+ return true;
32
}
38
}
33
- which = 2;
39
34
+ ret = c;
40
/* Invoke a vector move on two Pregs. */
35
} else {
41
@@ -XXX,XX +XXX,XX @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
42
};
37
+ FloatPartsN *val[3] = { a, b, c };
43
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
44
if (!a->s) {
39
45
- if (!sve_access_check(s)) {
40
assert(rule != float_3nan_prop_none);
46
- return true;
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
47
- }
42
/* We have at least one SNaN input and should prefer it */
48
if (a->rn == a->rm) {
43
do {
49
if (a->pg == a->rn) {
44
- which = rule & R_3NAN_1ST_MASK;
50
- do_mov_p(s, a->rd, a->rn);
45
+ ret = val[rule & R_3NAN_1ST_MASK];
51
- } else {
46
rule >>= R_3NAN_1ST_LENGTH;
52
- gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
47
- } while (!is_snan(cls[which]));
53
+ return do_mov_p(s, a->rd, a->rn);
48
+ } while (!is_snan(ret->cls));
54
}
49
} else {
55
- return true;
50
do {
56
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
51
- which = rule & R_3NAN_1ST_MASK;
57
} else if (a->pg == a->rn || a->pg == a->rm) {
52
+ ret = val[rule & R_3NAN_1ST_MASK];
58
- gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
53
rule >>= R_3NAN_1ST_LENGTH;
59
- return true;
54
- } while (!is_nan(cls[which]));
60
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
55
+ } while (!is_nan(ret->cls));
61
}
56
}
62
}
57
}
63
return do_pppp_flags(s, a, &op);
58
64
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
59
- switch (which) {
65
};
60
- case 0:
66
61
- break;
67
if (!a->s && a->pg == a->rn) {
62
- case 1:
68
- if (sve_access_check(s)) {
63
- a = b;
69
- gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
64
- break;
70
- }
65
- case 2:
71
- return true;
66
- a = c;
72
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
67
- break;
68
- default:
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
73
}
72
}
74
return do_pppp_flags(s, a, &op);
73
- if (is_snan(a->cls)) {
75
}
74
- parts_silence_nan(a, s);
75
- }
76
- return a;
77
+ return ret;
78
79
default_nan:
80
parts_default_nan(a, s);
76
--
81
--
77
2.25.1
82
2.34.1
83
84
diff view generated by jsdifflib
[PULL 045/117] target/arm: Use TRANS_FEAT for do_sve2_fn2i
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Convert SVE translation functions using do_sve2_fn2i
3
While all indices into val[] should be in [0-2], the mask
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzi.
4
applied is two bits. To help static analysis see there is
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
5
7
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-43-richard.henderson@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/translate-sve.c | 43 ++++++--------------------------------
13
fpu/softfloat-parts.c.inc | 2 +-
12
1 file changed, 6 insertions(+), 37 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
13
15
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
18
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-sve.c
19
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false)
21
}
20
TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
22
ret = c;
21
23
} else {
22
-static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
24
- FloatPartsN *val[3] = { a, b, c };
23
-{
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
24
- if (!dc_isar_feature(aa64_sve2, s)) {
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
25
- return false;
27
26
- }
28
assert(rule != float_3nan_prop_none);
27
- return gen_gvec_fn_arg_zzi(s, fn, a);
28
-}
29
-
30
-static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
31
-{
32
- return do_sve2_fn2i(s, a, gen_gvec_ssra);
33
-}
34
-
35
-static bool trans_USRA(DisasContext *s, arg_rri_esz *a)
36
-{
37
- return do_sve2_fn2i(s, a, gen_gvec_usra);
38
-}
39
-
40
-static bool trans_SRSRA(DisasContext *s, arg_rri_esz *a)
41
-{
42
- return do_sve2_fn2i(s, a, gen_gvec_srsra);
43
-}
44
-
45
-static bool trans_URSRA(DisasContext *s, arg_rri_esz *a)
46
-{
47
- return do_sve2_fn2i(s, a, gen_gvec_ursra);
48
-}
49
-
50
-static bool trans_SRI(DisasContext *s, arg_rri_esz *a)
51
-{
52
- return do_sve2_fn2i(s, a, gen_gvec_sri);
53
-}
54
-
55
-static bool trans_SLI(DisasContext *s, arg_rri_esz *a)
56
-{
57
- return do_sve2_fn2i(s, a, gen_gvec_sli);
58
-}
59
+TRANS_FEAT(SSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ssra, a)
60
+TRANS_FEAT(USRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_usra, a)
61
+TRANS_FEAT(SRSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_srsra, a)
62
+TRANS_FEAT(URSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ursra, a)
63
+TRANS_FEAT(SRI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sri, a)
64
+TRANS_FEAT(SLI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sli, a)
65
66
TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a)
67
TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a)
68
--
29
--
69
2.25.1
30
2.34.1
31
32
diff view generated by jsdifflib
[PULL 008/117] target/arm: Introduce gen_gvec_ool_arg_zzz
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use gen_gvec_ool_arg_zzz instead of gen_gvec_ool_zzz
3
This function is part of the public interface and
4
when the arguments come from arg_rrr_esz.
4
is not "specialized" to any target in any way.
5
Replaces do_zzw_ool and do_zzz_data_ool.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-6-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-sve.c | 48 +++++++++++++++++---------------------
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
13
1 file changed, 21 insertions(+), 27 deletions(-)
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
13
2 files changed, 52 insertions(+), 52 deletions(-)
14
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
17
--- a/fpu/softfloat.c
18
+++ b/target/arm/translate-sve.c
18
+++ b/fpu/softfloat.c
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
20
return true;
20
*zExpPtr = 1 - shiftCount;
21
}
21
}
22
22
23
+static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
23
+/*----------------------------------------------------------------------------
24
+ arg_rrr_esz *a, int data)
24
+| Takes two extended double-precision floating-point values `a' and `b', one
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
26
+| `b' is a signaling NaN, the invalid exception is raised.
27
+*----------------------------------------------------------------------------*/
28
+
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
25
+{
30
+{
26
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
31
+ bool aIsLargerSignificand;
32
+ FloatClass a_cls, b_cls;
33
+
34
+ /* This is not complete, but is good enough for pickNaN. */
35
+ a_cls = (!floatx80_is_any_nan(a)
36
+ ? float_class_normal
37
+ : floatx80_is_signaling_nan(a, status)
38
+ ? float_class_snan
39
+ : float_class_qnan);
40
+ b_cls = (!floatx80_is_any_nan(b)
41
+ ? float_class_normal
42
+ : floatx80_is_signaling_nan(b, status)
43
+ ? float_class_snan
44
+ : float_class_qnan);
45
+
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
47
+ float_raise(float_flag_invalid, status);
48
+ }
49
+
50
+ if (status->default_nan_mode) {
51
+ return floatx80_default_nan(status);
52
+ }
53
+
54
+ if (a.low < b.low) {
55
+ aIsLargerSignificand = 0;
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
61
+
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
63
+ if (is_snan(b_cls)) {
64
+ return floatx80_silence_nan(b, status);
65
+ }
66
+ return b;
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
72
+ }
27
+}
73
+}
28
+
74
+
29
/* Invoke an out-of-line helper on 4 Zregs. */
75
/*----------------------------------------------------------------------------
30
static void gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
31
int rd, int rn, int rm, int ra, int data)
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
32
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
33
return do_shift_imm(s, a, false, tcg_gen_gvec_shli);
79
index XXXXXXX..XXXXXXX 100644
80
--- a/fpu/softfloat-specialize.c.inc
81
+++ b/fpu/softfloat-specialize.c.inc
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
83
return a;
34
}
84
}
35
85
36
-static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
86
-/*----------------------------------------------------------------------------
87
-| Takes two extended double-precision floating-point values `a' and `b', one
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
89
-| `b' is a signaling NaN, the invalid exception is raised.
90
-*----------------------------------------------------------------------------*/
91
-
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
37
-{
93
-{
38
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
94
- bool aIsLargerSignificand;
95
- FloatClass a_cls, b_cls;
96
-
97
- /* This is not complete, but is good enough for pickNaN. */
98
- a_cls = (!floatx80_is_any_nan(a)
99
- ? float_class_normal
100
- : floatx80_is_signaling_nan(a, status)
101
- ? float_class_snan
102
- : float_class_qnan);
103
- b_cls = (!floatx80_is_any_nan(b)
104
- ? float_class_normal
105
- : floatx80_is_signaling_nan(b, status)
106
- ? float_class_snan
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
135
- }
39
-}
136
-}
40
-
137
-
41
#define DO_ZZW(NAME, name) \
138
/*----------------------------------------------------------------------------
42
static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
43
{ \
140
| NaN; otherwise returns 0.
44
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
45
gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \
46
gen_helper_sve_##name##_zzw_s, NULL \
47
}; \
48
- return do_zzw_ool(s, a, fns[a->esz]); \
49
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0); \
50
}
51
52
DO_ZZW(ASR, asr)
53
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
54
gen_helper_sve_ftssel_s,
55
gen_helper_sve_ftssel_d,
56
};
57
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
58
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
59
}
60
61
/*
62
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
63
gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
64
gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
65
};
66
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
67
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
68
}
69
70
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
71
@@ -XXX,XX +XXX,XX @@ static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
72
if (!dc_isar_feature(aa64_sve2, s)) {
73
return false;
74
}
75
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
76
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
77
}
78
79
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
80
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
81
return true;
82
}
83
84
-static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
85
- gen_helper_gvec_3 *fn)
86
-{
87
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
88
-}
89
-
90
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
91
{
92
return do_zip(s, a, false);
93
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const uzp_fns[4] = {
94
95
static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a)
96
{
97
- return do_zzz_data_ool(s, a, 0, uzp_fns[a->esz]);
98
+ return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 0);
99
}
100
101
static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a)
102
{
103
- return do_zzz_data_ool(s, a, 1 << a->esz, uzp_fns[a->esz]);
104
+ return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 1 << a->esz);
105
}
106
107
static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
108
@@ -XXX,XX +XXX,XX @@ static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
109
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
110
return false;
111
}
112
- return do_zzz_data_ool(s, a, 0, gen_helper_sve2_uzp_q);
113
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 0);
114
}
115
116
static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
117
@@ -XXX,XX +XXX,XX @@ static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
118
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
119
return false;
120
}
121
- return do_zzz_data_ool(s, a, 16, gen_helper_sve2_uzp_q);
122
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 16);
123
}
124
125
static gen_helper_gvec_3 * const trn_fns[4] = {
126
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const trn_fns[4] = {
127
128
static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a)
129
{
130
- return do_zzz_data_ool(s, a, 0, trn_fns[a->esz]);
131
+ return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 0);
132
}
133
134
static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a)
135
{
136
- return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]);
137
+ return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 1 << a->esz);
138
}
139
140
static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
141
@@ -XXX,XX +XXX,XX @@ static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
142
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
143
return false;
144
}
145
- return do_zzz_data_ool(s, a, 0, gen_helper_sve2_trn_q);
146
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 0);
147
}
148
149
static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
150
@@ -XXX,XX +XXX,XX @@ static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
151
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
152
return false;
153
}
154
- return do_zzz_data_ool(s, a, 16, gen_helper_sve2_trn_q);
155
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 16);
156
}
157
158
/*
159
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
160
if (!dc_isar_feature(aa64_sve2, s)) {
161
return false;
162
}
163
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
164
+ return gen_gvec_ool_arg_zzz(s, fn, a, 0);
165
}
166
167
static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
168
@@ -XXX,XX +XXX,XX @@ static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
169
if (!dc_isar_feature(aa64_sve2_aes, s)) {
170
return false;
171
}
172
- return gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
173
- a->rd, a->rn, a->rm, decrypt);
174
+ return gen_gvec_ool_arg_zzz(s, gen_helper_crypto_aese, a, decrypt);
175
}
176
177
static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
178
@@ -XXX,XX +XXX,XX @@ static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
179
if (!dc_isar_feature(aa64_sve2_sm4, s)) {
180
return false;
181
}
182
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
183
+ return gen_gvec_ool_arg_zzz(s, fn, a, 0);
184
}
185
186
static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
187
--
141
--
188
2.25.1
142
2.34.1
diff view generated by jsdifflib
[PULL 044/117] target/arm: Introduce gen_gvec_fn_arg_zzi
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We have two places that perform this particular operation.
3
Unpacking and repacking the parts may be slightly more work
4
than we did before, but we get to reuse more code. For a
5
code path handling exceptional values, this is an improvement.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-42-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate-sve.c | 21 +++++++++++++--------
12
fpu/softfloat.c | 43 +++++--------------------------------------
11
1 file changed, 13 insertions(+), 8 deletions(-)
13
1 file changed, 5 insertions(+), 38 deletions(-)
12
14
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
17
--- a/fpu/softfloat.c
16
+++ b/target/arm/translate-sve.c
18
+++ b/fpu/softfloat.c
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
18
return true;
20
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
22
{
23
- bool aIsLargerSignificand;
24
- FloatClass a_cls, b_cls;
25
+ FloatParts128 pa, pb, *pr;
26
27
- /* This is not complete, but is good enough for pickNaN. */
28
- a_cls = (!floatx80_is_any_nan(a)
29
- ? float_class_normal
30
- : floatx80_is_signaling_nan(a, status)
31
- ? float_class_snan
32
- : float_class_qnan);
33
- b_cls = (!floatx80_is_any_nan(b)
34
- ? float_class_normal
35
- : floatx80_is_signaling_nan(b, status)
36
- ? float_class_snan
37
- : float_class_qnan);
38
-
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
40
- float_raise(float_flag_invalid, status);
41
- }
42
-
43
- if (status->default_nan_mode) {
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
46
return floatx80_default_nan(status);
47
}
48
49
- if (a.low < b.low) {
50
- aIsLargerSignificand = 0;
51
- } else if (b.low < a.low) {
52
- aIsLargerSignificand = 1;
53
- } else {
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
55
- }
56
-
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
58
- if (is_snan(b_cls)) {
59
- return floatx80_silence_nan(b, status);
60
- }
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
67
- }
68
+ pr = parts_pick_nan(&pa, &pb, status);
69
+ return floatx80_round_pack_canonical(pr, status);
19
}
70
}
20
71
21
+static bool gen_gvec_fn_arg_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
72
/*----------------------------------------------------------------------------
22
+ arg_rri_esz *a)
23
+{
24
+ if (a->esz < 0) {
25
+ /* Invalid tsz encoding -- see tszimm_esz. */
26
+ return false;
27
+ }
28
+ return gen_gvec_fn_zzi(s, gvec_fn, a->esz, a->rd, a->rn, a->imm);
29
+}
30
+
31
/* Invoke a vector expander on three Zregs. */
32
static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
33
int esz, int rd, int rn, int rm)
34
@@ -XXX,XX +XXX,XX @@ static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
35
if (a->esz == 0 && extract32(s->insn, 13, 1)) {
36
return false;
37
}
38
- if (sve_access_check(s)) {
39
- unsigned vsz = vec_full_reg_size(s);
40
- tcg_gen_gvec_addi(a->esz, vec_full_reg_offset(s, a->rd),
41
- vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz);
42
- }
43
- return true;
44
+ return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
45
}
46
47
static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a)
48
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
49
50
static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
51
{
52
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
53
+ if (!dc_isar_feature(aa64_sve2, s)) {
54
return false;
55
}
56
- return gen_gvec_fn_zzi(s, fn, a->esz, a->rd, a->rn, a->imm);
57
+ return gen_gvec_fn_arg_zzi(s, fn, a);
58
}
59
60
static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
61
--
73
--
62
2.25.1
74
2.34.1
diff view generated by jsdifflib
[PULL 027/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi
[PULL 67/72] softfloat: Inline pickNaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Convert some SVE translation functions using
3
Inline pickNaN into its only caller. This makes one assert
4
gen_gvec_ool_arg_zpzi to TRANS_FEAT.
4
redundant with the immediately preceding IF.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-25-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate-sve.c | 85 ++++++++++++++------------------------
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
12
1 file changed, 30 insertions(+), 55 deletions(-)
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
13
13
2 files changed, 73 insertions(+), 105 deletions(-)
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-sve.c
18
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
float_status *s)
22
{
23
+ int cmp, which;
24
+
25
if (is_snan(a->cls) || is_snan(b->cls)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
if (s->default_nan_mode) {
30
parts_default_nan(a, s);
31
- } else {
32
- int cmp = frac_cmp(a, b);
33
- if (cmp == 0) {
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
58
}
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
118
index XXXXXXX..XXXXXXX 100644
119
--- a/fpu/softfloat-specialize.c.inc
120
+++ b/fpu/softfloat-specialize.c.inc
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
19
}
122
}
20
}
123
}
21
124
22
-static bool trans_SQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
125
-/*----------------------------------------------------------------------------
126
-| Select which NaN to propagate for a two-input operation.
127
-| IEEE754 doesn't specify all the details of this, so the
128
-| algorithm is target-specific.
129
-| The routine is passed various bits of information about the
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
131
-| Note that signalling NaNs are always squashed to quiet NaNs
132
-| by the caller, by calling floatXX_silence_nan() before
133
-| returning them.
134
-|
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
136
-| of some kind, and is true if a has the larger significand,
137
-| or if both a and b have the same significand but a is
138
-| positive but b is negative. It is only needed for the x87
139
-| tie-break rule.
140
-*----------------------------------------------------------------------------*/
141
-
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
143
- bool aIsLargerSignificand, float_status *status)
23
-{
144
-{
24
- static gen_helper_gvec_3 * const fns[4] = {
145
- /*
25
- gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
146
- * We guarantee not to require the target to tell us how to
26
- gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d,
147
- * pick a NaN if we're always returning the default NaN.
27
- };
148
- * But if we're not in default-NaN mode then the target must
28
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
149
- * specify via set_float_2nan_prop_rule().
29
- return false;
150
- */
151
- assert(!status->default_nan_mode);
152
-
153
- switch (status->float_2nan_prop_rule) {
154
- case float_2nan_prop_s_ab:
155
- if (is_snan(a_cls)) {
156
- return 0;
157
- } else if (is_snan(b_cls)) {
158
- return 1;
159
- } else if (is_qnan(a_cls)) {
160
- return 0;
161
- } else {
162
- return 1;
163
- }
164
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
30
- }
218
- }
31
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
32
-}
219
-}
33
+static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
220
-
34
+ gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
221
/*----------------------------------------------------------------------------
35
+ gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d,
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
36
+};
223
| NaN; otherwise returns 0.
37
+TRANS_FEAT(SQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi,
38
+ a->esz < 0 ? NULL : sqshl_zpzi_fns[a->esz], a)
39
40
-static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
41
-{
42
- static gen_helper_gvec_3 * const fns[4] = {
43
- gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h,
44
- gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d,
45
- };
46
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
47
- return false;
48
- }
49
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
50
-}
51
+static gen_helper_gvec_3 * const uqshl_zpzi_fns[4] = {
52
+ gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h,
53
+ gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d,
54
+};
55
+TRANS_FEAT(UQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi,
56
+ a->esz < 0 ? NULL : uqshl_zpzi_fns[a->esz], a)
57
58
-static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
59
-{
60
- static gen_helper_gvec_3 * const fns[4] = {
61
- gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h,
62
- gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d,
63
- };
64
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
65
- return false;
66
- }
67
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
68
-}
69
+static gen_helper_gvec_3 * const srshr_fns[4] = {
70
+ gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h,
71
+ gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d,
72
+};
73
+TRANS_FEAT(SRSHR, aa64_sve2, gen_gvec_ool_arg_zpzi,
74
+ a->esz < 0 ? NULL : srshr_fns[a->esz], a)
75
76
-static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
77
-{
78
- static gen_helper_gvec_3 * const fns[4] = {
79
- gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h,
80
- gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d,
81
- };
82
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
83
- return false;
84
- }
85
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
86
-}
87
+static gen_helper_gvec_3 * const urshr_fns[4] = {
88
+ gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h,
89
+ gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d,
90
+};
91
+TRANS_FEAT(URSHR, aa64_sve2, gen_gvec_ool_arg_zpzi,
92
+ a->esz < 0 ? NULL : urshr_fns[a->esz], a)
93
94
-static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
95
-{
96
- static gen_helper_gvec_3 * const fns[4] = {
97
- gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h,
98
- gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d,
99
- };
100
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
101
- return false;
102
- }
103
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
104
-}
105
+static gen_helper_gvec_3 * const sqshlu_fns[4] = {
106
+ gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h,
107
+ gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d,
108
+};
109
+TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi,
110
+ a->esz < 0 ? NULL : sqshlu_fns[a->esz], a)
111
112
/*
113
*** SVE Bitwise Shift - Predicated Group
114
--
224
--
115
2.25.1
225
2.34.1
226
227
diff view generated by jsdifflib
[PULL 043/117] target/arm: Hoist sve access check through do_sel_z
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The check is already done in gen_gvec_ool_zzzp,
3
Remember if there was an SNaN, and use that to simplify
4
which is called by do_sel_z; remove from callers.
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
Then, fall through to the corresponding
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
5
8
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-41-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/translate-sve.c | 14 ++++----------
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
12
1 file changed, 4 insertions(+), 10 deletions(-)
15
1 file changed, 12 insertions(+), 20 deletions(-)
13
16
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
19
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-sve.c
20
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a)
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
19
/* Select active elememnts from Zn and inactive elements from Zm,
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
20
* storing the result in Zd.
23
float_status *s)
21
*/
22
-static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
23
+static bool do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
24
{
24
{
25
static gen_helper_gvec_4 * const fns[4] = {
25
+ bool have_snan = false;
26
gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
26
int cmp, which;
27
gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
27
28
};
28
if (is_snan(a->cls) || is_snan(b->cls)) {
29
- gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
30
+ return gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
30
+ have_snan = true;
31
}
31
}
32
32
33
#define DO_ZPZZ(NAME, FEAT, name) \
33
if (s->default_nan_mode) {
34
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
35
35
36
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
36
switch (s->float_2nan_prop_rule) {
37
{
37
case float_2nan_prop_s_ab:
38
- if (sve_access_check(s)) {
38
- if (is_snan(a->cls)) {
39
- do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
39
- which = 0;
40
- }
40
- } else if (is_snan(b->cls)) {
41
- return true;
41
- which = 1;
42
+ return do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
42
- } else if (is_qnan(a->cls)) {
43
}
43
- which = 0;
44
44
- } else {
45
/*
45
- which = 1;
46
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a)
46
+ if (have_snan) {
47
47
+ which = is_snan(a->cls) ? 0 : 1;
48
static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
48
+ break;
49
{
49
}
50
- if (sve_access_check(s)) {
50
- break;
51
- do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
51
- case float_2nan_prop_s_ba:
52
- }
52
- if (is_snan(b->cls)) {
53
- return true;
53
- which = 1;
54
+ return do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
54
- } else if (is_snan(a->cls)) {
55
}
55
- which = 0;
56
56
- } else if (is_qnan(b->cls)) {
57
static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
57
- which = 1;
58
- } else {
59
- which = 0;
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
69
+ break;
70
+ }
71
+ /* fall through */
72
case float_2nan_prop_ba:
73
which = is_nan(b->cls) ? 1 : 0;
74
break;
58
--
75
--
59
2.25.1
76
2.34.1
diff view generated by jsdifflib
[PULL 081/117] target/arm: Use TRANS_FEAT for FMMLA
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Being able to specify the feature predicate in TRANS_FEAT
3
Move the fractional comparison to the end of the
4
makes it easier to split trans_FMMLA by element size,
4
float_2nan_prop_x87 case. This is not required for
5
which also happens to simplify the decode.
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
6
8
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-79-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/sve.decode | 7 +++----
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
13
target/arm/translate-sve.c | 27 ++++-----------------------
15
1 file changed, 9 insertions(+), 10 deletions(-)
14
2 files changed, 7 insertions(+), 27 deletions(-)
15
16
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve.decode
19
--- a/fpu/softfloat-parts.c.inc
19
+++ b/target/arm/sve.decode
20
+++ b/fpu/softfloat-parts.c.inc
20
@@ -XXX,XX +XXX,XX @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm
22
return a;
22
23
}
23
### SVE2 floating point matrix multiply accumulate
24
24
-{
25
- cmp = frac_cmp(a, b);
25
- BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
26
- if (cmp == 0) {
26
- FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm
27
- cmp = a->sign < b->sign;
27
-}
28
+BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
29
+FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
30
+FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
31
32
### SVE2 Memory Gather Load Group
33
34
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/translate-sve.c
37
+++ b/target/arm/translate-sve.c
38
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZPZZ_FP(FMINP, fminp)
39
* SVE Integer Multiply-Add (unpredicated)
40
*/
41
42
-static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
43
-{
44
- gen_helper_gvec_4_ptr *fn;
45
-
46
- switch (a->esz) {
47
- case MO_32:
48
- if (!dc_isar_feature(aa64_sve_f32mm, s)) {
49
- return false;
50
- }
51
- fn = gen_helper_fmmla_s;
52
- break;
53
- case MO_64:
54
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
55
- return false;
56
- }
57
- fn = gen_helper_fmmla_d;
58
- break;
59
- default:
60
- return false;
61
- }
28
- }
62
-
29
-
63
- return gen_gvec_fpst_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR);
30
switch (s->float_2nan_prop_rule) {
64
-}
31
case float_2nan_prop_s_ab:
65
+TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s,
32
if (have_snan) {
66
+ a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
67
+TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d,
34
* return the NaN with the positive sign bit (if any).
68
+ a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
35
*/
69
36
if (is_snan(a->cls)) {
70
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
37
- if (is_snan(b->cls)) {
71
NULL, gen_helper_sve2_sqdmlal_zzzw_h,
38
- which = cmp > 0 ? 0 : 1;
39
- } else {
40
+ if (!is_snan(b->cls)) {
41
which = is_qnan(b->cls) ? 1 : 0;
42
+ break;
43
}
44
} else if (is_qnan(a->cls)) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
46
which = 0;
47
- } else {
48
- which = cmp > 0 ? 0 : 1;
49
+ break;
50
}
51
} else {
52
which = 1;
53
+ break;
54
}
55
+ cmp = frac_cmp(a, b);
56
+ if (cmp == 0) {
57
+ cmp = a->sign < b->sign;
58
+ }
59
+ which = cmp > 0 ? 0 : 1;
60
break;
61
default:
62
g_assert_not_reached();
72
--
63
--
73
2.25.1
64
2.34.1
diff view generated by jsdifflib
[PULL 041/117] target/arm: Introduce gen_gvec_fn_zzi
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We have two places that perform this particular operation.
3
Replace the "index" selecting between A and B with a result variable
4
of the proper type. This improves clarity within the function.
4
5
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-39-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/translate-sve.c | 30 +++++++++++++++++-------------
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
11
1 file changed, 17 insertions(+), 13 deletions(-)
12
1 file changed, 13 insertions(+), 15 deletions(-)
12
13
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
--- a/fpu/softfloat-parts.c.inc
16
+++ b/target/arm/translate-sve.c
17
+++ b/fpu/softfloat-parts.c.inc
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
18
return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
19
float_status *s)
20
{
21
bool have_snan = false;
22
- int cmp, which;
23
+ FloatPartsN *ret;
24
+ int cmp;
25
26
if (is_snan(a->cls) || is_snan(b->cls)) {
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
29
switch (s->float_2nan_prop_rule) {
30
case float_2nan_prop_s_ab:
31
if (have_snan) {
32
- which = is_snan(a->cls) ? 0 : 1;
33
+ ret = is_snan(a->cls) ? a : b;
34
break;
35
}
36
/* fall through */
37
case float_2nan_prop_ab:
38
- which = is_nan(a->cls) ? 0 : 1;
39
+ ret = is_nan(a->cls) ? a : b;
40
break;
41
case float_2nan_prop_s_ba:
42
if (have_snan) {
43
- which = is_snan(b->cls) ? 1 : 0;
44
+ ret = is_snan(b->cls) ? b : a;
45
break;
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
51
break;
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
81
g_assert_not_reached();
82
}
83
84
- if (which) {
85
- a = b;
86
+ if (is_snan(ret->cls)) {
87
+ parts_silence_nan(ret, s);
88
}
89
- if (is_snan(a->cls)) {
90
- parts_silence_nan(a, s);
91
- }
92
- return a;
93
+ return ret;
19
}
94
}
20
95
21
+/* Invoke a vector expander on two Zregs and an immediate. */
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
22
+static bool gen_gvec_fn_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
23
+ int esz, int rd, int rn, uint64_t imm)
24
+{
25
+ if (gvec_fn == NULL) {
26
+ return false;
27
+ }
28
+ if (sve_access_check(s)) {
29
+ unsigned vsz = vec_full_reg_size(s);
30
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
31
+ vec_full_reg_offset(s, rn), imm, vsz, vsz);
32
+ }
33
+ return true;
34
+}
35
+
36
/* Invoke a vector expander on three Zregs. */
37
static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
38
int esz, int rd, int rn, int rm)
39
@@ -XXX,XX +XXX,XX @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
40
extract32(a->dbm, 6, 6))) {
41
return false;
42
}
43
- if (sve_access_check(s)) {
44
- unsigned vsz = vec_full_reg_size(s);
45
- gvec_fn(MO_64, vec_full_reg_offset(s, a->rd),
46
- vec_full_reg_offset(s, a->rn), imm, vsz, vsz);
47
- }
48
- return true;
49
+ return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm);
50
}
51
52
static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a)
53
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
54
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
55
return false;
56
}
57
- if (sve_access_check(s)) {
58
- unsigned vsz = vec_full_reg_size(s);
59
- unsigned rd_ofs = vec_full_reg_offset(s, a->rd);
60
- unsigned rn_ofs = vec_full_reg_offset(s, a->rn);
61
- fn(a->esz, rd_ofs, rn_ofs, a->imm, vsz, vsz);
62
- }
63
- return true;
64
+ return gen_gvec_fn_zzi(s, fn, a->esz, a->rd, a->rn, a->imm);
65
}
66
67
static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
68
--
97
--
69
2.25.1
98
2.34.1
99
100
diff view generated by jsdifflib
[PULL 002/117] target/arm/hvf: Include missing "cpregs.h"
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
Fix when building HVF on macOS Aarch64:
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
update my email address, and update the mailmap to match.
4
5
5
target/arm/hvf/hvf.c:586:15: error: unknown type name 'ARMCPRegInfo'; did you mean 'ARMCPUInfo'?
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
6
const ARMCPRegInfo *ri;
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
7
^~~~~~~~~~~~
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
8
ARMCPUInfo
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
target/arm/cpu-qom.h:38:3: note: 'ARMCPUInfo' declared here
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
} ARMCPUInfo;
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
11
^
12
target/arm/hvf/hvf.c:589:14: error: implicit declaration of function 'get_arm_cp_reginfo' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
13
ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
14
^
15
target/arm/hvf/hvf.c:589:12: warning: incompatible integer to pointer conversion assigning to 'const ARMCPUInfo *' (aka 'const struct ARMCPUInfo *') from 'int' [-Wint-conversion]
16
ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
17
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18
target/arm/hvf/hvf.c:591:26: error: no member named 'type' in 'struct ARMCPUInfo'
19
assert(!(ri->type & ARM_CP_NO_RAW));
20
~~ ^
21
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/usr/include/assert.h:99:25: note: expanded from macro 'assert'
22
(__builtin_expect(!(e), 0) ? __assert_rtn(__func__, __ASSERT_FILE_NAME, __LINE__, #e) : (void)0)
23
^
24
target/arm/hvf/hvf.c:591:33: error: use of undeclared identifier 'ARM_CP_NO_RAW'
25
assert(!(ri->type & ARM_CP_NO_RAW));
26
^
27
1 warning and 4 errors generated.
28
29
Fixes: cf7c6d1004 ("target/arm: Split out cpregs.h")
30
Reported-by: Duncan Bayne <duncan@bayne.id.au>
31
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
32
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
33
Message-id: 20220525161926.34233-1-philmd@fungible.com
34
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1029
35
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
36
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
---
13
---
38
target/arm/hvf/hvf.c | 1 +
14
MAINTAINERS | 2 +-
39
1 file changed, 1 insertion(+)
15
.mailmap | 5 +++--
16
2 files changed, 4 insertions(+), 3 deletions(-)
40
17
41
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
18
diff --git a/MAINTAINERS b/MAINTAINERS
42
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/hvf/hvf.c
20
--- a/MAINTAINERS
44
+++ b/target/arm/hvf/hvf.c
21
+++ b/MAINTAINERS
45
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
46
#include "sysemu/hvf_int.h"
23
SBSA-REF
47
#include "sysemu/hw_accel.h"
24
M: Radoslaw Biernacki <rad@semihalf.com>
48
#include "hvf_arm.h"
25
M: Peter Maydell <peter.maydell@linaro.org>
49
+#include "cpregs.h"
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
50
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
51
#include <mach/mach_time.h>
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
52
29
L: qemu-arm@nongnu.org
30
S: Maintained
31
diff --git a/.mailmap b/.mailmap
32
index XXXXXXX..XXXXXXX 100644
33
--- a/.mailmap
34
+++ b/.mailmap
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
53
--
47
--
54
2.25.1
48
2.34.1
55
49
56
50
diff view generated by jsdifflib
[PULL 003/117] hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
Deleted patch
1
From: Icenowy Zheng <uwu@icenowy.me>
2
1
3
U-Boot queries the FIFO water level to reduce checking status register
4
when doing PIO SD card operation.
5
6
Report a FIFO water level of 1 when data is ready, to prevent the code
7
from trying to read 0 words from the FIFO each time.
8
9
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
10
Message-id: 20220520124200.2112699-1-uwu@icenowy.me
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/sd/allwinner-sdhost.c | 7 +++++++
15
1 file changed, 7 insertions(+)
16
17
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/sd/allwinner-sdhost.c
20
+++ b/hw/sd/allwinner-sdhost.c
21
@@ -XXX,XX +XXX,XX @@ enum {
22
};
23
24
enum {
25
+ SD_STAR_FIFO_EMPTY = (1 << 2),
26
SD_STAR_CARD_PRESENT = (1 << 8),
27
+ SD_STAR_FIFO_LEVEL_1 = (1 << 17),
28
};
29
30
enum {
31
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
32
break;
33
case REG_SD_STAR: /* Status */
34
res = s->status;
35
+ if (sdbus_data_ready(&s->sdbus)) {
36
+ res |= SD_STAR_FIFO_LEVEL_1;
37
+ } else {
38
+ res |= SD_STAR_FIFO_EMPTY;
39
+ }
40
break;
41
case REG_SD_FWLR: /* FIFO Water Level */
42
res = s->fifo_wlevel;
43
--
44
2.25.1
diff view generated by jsdifflib
[PULL 004/117] target/arm: Introduce TRANS, TRANS_FEAT
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Steal the idea for these leaf function expanders from PowerPC.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-2-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.h | 11 +++++++++++
11
1 file changed, 11 insertions(+)
12
13
diff --git a/target/arm/translate.h b/target/arm/translate.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.h
16
+++ b/target/arm/translate.h
17
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
18
*/
19
uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
20
21
+/*
22
+ * Helpers for implementing sets of trans_* functions.
23
+ * Defer the implementation of NAME to FUNC, with optional extra arguments.
24
+ */
25
+#define TRANS(NAME, FUNC, ...) \
26
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
27
+ { return FUNC(s, __VA_ARGS__); }
28
+#define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
29
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
30
+ { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
31
+
32
#endif /* TARGET_ARM_TRANSLATE_H */
33
--
34
2.25.1
diff view generated by jsdifflib
[PULL 005/117] target/arm: Move null function and sve check into gen_gvec_ool_zz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-3-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 36 +++++++++++++++---------------------
9
1 file changed, 15 insertions(+), 21 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
16
}
17
18
/* Invoke an out-of-line helper on 2 Zregs. */
19
-static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
20
+static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
21
int rd, int rn, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vsz, vsz, data, fn);
27
+ if (fn == NULL) {
28
+ return false;
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
33
+ vec_full_reg_offset(s, rn),
34
+ vsz, vsz, data, fn);
35
+ }
36
+ return true;
37
}
38
39
/* Invoke an out-of-line helper on 3 Zregs. */
40
@@ -XXX,XX +XXX,XX @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
41
gen_helper_sve_fexpa_s,
42
gen_helper_sve_fexpa_d,
43
};
44
- if (a->esz == 0) {
45
- return false;
46
- }
47
- if (sve_access_check(s)) {
48
- gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
49
- }
50
- return true;
51
+ return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
52
}
53
54
static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
55
@@ -XXX,XX +XXX,XX @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
56
gen_helper_sve_rev_b, gen_helper_sve_rev_h,
57
gen_helper_sve_rev_s, gen_helper_sve_rev_d
58
};
59
-
60
- if (sve_access_check(s)) {
61
- gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
62
- }
63
- return true;
64
+ return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
65
}
66
67
static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
68
@@ -XXX,XX +XXX,XX @@ static bool trans_AESMC(DisasContext *s, arg_AESMC *a)
69
if (!dc_isar_feature(aa64_sve2_aes, s)) {
70
return false;
71
}
72
- if (sve_access_check(s)) {
73
- gen_gvec_ool_zz(s, gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt);
74
- }
75
- return true;
76
+ return gen_gvec_ool_zz(s, gen_helper_crypto_aesmc,
77
+ a->rd, a->rd, a->decrypt);
78
}
79
80
static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
81
--
82
2.25.1
diff view generated by jsdifflib
[PULL 006/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_zz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions using gen_gvec_ool_zz to TRANS_FEAT.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-4-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 39 +++++++++++++-------------------------
11
1 file changed, 13 insertions(+), 26 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_ADR_u32(DisasContext *s, arg_rrri *a)
18
*** SVE Integer Misc - Unpredicated Group
19
*/
20
21
-static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
22
-{
23
- static gen_helper_gvec_2 * const fns[4] = {
24
- NULL,
25
- gen_helper_sve_fexpa_h,
26
- gen_helper_sve_fexpa_s,
27
- gen_helper_sve_fexpa_d,
28
- };
29
- return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
30
-}
31
+static gen_helper_gvec_2 * const fexpa_fns[4] = {
32
+ NULL, gen_helper_sve_fexpa_h,
33
+ gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
34
+};
35
+TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
36
+ fexpa_fns[a->esz], a->rd, a->rn, 0)
37
38
static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
39
{
40
@@ -XXX,XX +XXX,XX @@ static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a)
41
return true;
42
}
43
44
-static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
45
-{
46
- static gen_helper_gvec_2 * const fns[4] = {
47
- gen_helper_sve_rev_b, gen_helper_sve_rev_h,
48
- gen_helper_sve_rev_s, gen_helper_sve_rev_d
49
- };
50
- return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
51
-}
52
+static gen_helper_gvec_2 * const rev_fns[4] = {
53
+ gen_helper_sve_rev_b, gen_helper_sve_rev_h,
54
+ gen_helper_sve_rev_s, gen_helper_sve_rev_d
55
+};
56
+TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0)
57
58
static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
59
{
60
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
61
return true;
62
}
63
64
-static bool trans_AESMC(DisasContext *s, arg_AESMC *a)
65
-{
66
- if (!dc_isar_feature(aa64_sve2_aes, s)) {
67
- return false;
68
- }
69
- return gen_gvec_ool_zz(s, gen_helper_crypto_aesmc,
70
- a->rd, a->rd, a->decrypt);
71
-}
72
+TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
73
+ gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
74
75
static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
76
{
77
--
78
2.25.1
diff view generated by jsdifflib
[PULL 007/117] target/arm: Move null function and sve check into gen_gvec_ool_zzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-5-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 74 ++++++++++++--------------------------
9
1 file changed, 23 insertions(+), 51 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 3 Zregs. */
19
-static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
20
+static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
21
int rd, int rn, int rm, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- vsz, vsz, data, fn);
28
+ if (fn == NULL) {
29
+ return false;
30
+ }
31
+ if (sve_access_check(s)) {
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
34
+ vec_full_reg_offset(s, rn),
35
+ vec_full_reg_offset(s, rm),
36
+ vsz, vsz, data, fn);
37
+ }
38
+ return true;
39
}
40
41
/* Invoke an out-of-line helper on 4 Zregs. */
42
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
43
44
static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
45
{
46
- if (fn == NULL) {
47
- return false;
48
- }
49
- if (sve_access_check(s)) {
50
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
54
}
55
56
#define DO_ZZW(NAME, name) \
57
@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
58
59
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
60
{
61
- if (sve_access_check(s)) {
62
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
63
- }
64
- return true;
65
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
66
}
67
68
static bool trans_ADR_p32(DisasContext *s, arg_rrri *a)
69
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
70
gen_helper_sve_ftssel_s,
71
gen_helper_sve_ftssel_d,
72
};
73
- if (a->esz == 0) {
74
- return false;
75
- }
76
- if (sve_access_check(s)) {
77
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
78
- }
79
- return true;
80
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
81
}
82
83
/*
84
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
85
gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
86
gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
87
};
88
-
89
- if (sve_access_check(s)) {
90
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
91
- }
92
- return true;
93
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
94
}
95
96
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
97
@@ -XXX,XX +XXX,XX @@ static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
98
if (!dc_isar_feature(aa64_sve2, s)) {
99
return false;
100
}
101
- if (sve_access_check(s)) {
102
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
103
- }
104
- return true;
105
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
106
}
107
108
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
109
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
110
static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
111
gen_helper_gvec_3 *fn)
112
{
113
- if (sve_access_check(s)) {
114
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
115
- }
116
- return true;
117
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
118
}
119
120
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
121
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
122
static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
123
gen_helper_gvec_3 *fn)
124
{
125
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
126
+ if (!dc_isar_feature(aa64_sve2, s)) {
127
return false;
128
}
129
- if (sve_access_check(s)) {
130
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
131
- }
132
- return true;
133
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
134
}
135
136
static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
137
@@ -XXX,XX +XXX,XX @@ static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
138
if (!dc_isar_feature(aa64_sve2_aes, s)) {
139
return false;
140
}
141
- if (sve_access_check(s)) {
142
- gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
143
- a->rd, a->rn, a->rm, decrypt);
144
- }
145
- return true;
146
+ return gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
147
+ a->rd, a->rn, a->rm, decrypt);
148
}
149
150
static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
151
@@ -XXX,XX +XXX,XX @@ static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
152
if (!dc_isar_feature(aa64_sve2_sm4, s)) {
153
return false;
154
}
155
- if (sve_access_check(s)) {
156
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
157
- }
158
- return true;
159
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
160
}
161
162
static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
163
--
164
2.25.1
diff view generated by jsdifflib
[PULL 009/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions using
4
gen_gvec_ool_arg_zzz to TRANS_FEAT.
5
6
Remove trivial wrappers do_aese, do_sm4.
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220527181907.189259-7-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate-sve.c | 165 ++++++++++---------------------------
14
1 file changed, 45 insertions(+), 120 deletions(-)
15
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
21
}
22
23
#define DO_ZZW(NAME, name) \
24
-static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
25
-{ \
26
- static gen_helper_gvec_3 * const fns[4] = { \
27
+ static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \
28
gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \
29
gen_helper_sve_##name##_zzw_s, NULL \
30
}; \
31
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0); \
32
-}
33
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_arg_zzz, \
34
+ name##_zzw_fns[a->esz], a, 0)
35
36
-DO_ZZW(ASR, asr)
37
-DO_ZZW(LSR, lsr)
38
-DO_ZZW(LSL, lsl)
39
+DO_ZZW(ASR_zzw, asr)
40
+DO_ZZW(LSR_zzw, lsr)
41
+DO_ZZW(LSL_zzw, lsl)
42
43
#undef DO_ZZW
44
45
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const fexpa_fns[4] = {
46
TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
47
fexpa_fns[a->esz], a->rd, a->rn, 0)
48
49
-static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
50
-{
51
- static gen_helper_gvec_3 * const fns[4] = {
52
- NULL,
53
- gen_helper_sve_ftssel_h,
54
- gen_helper_sve_ftssel_s,
55
- gen_helper_sve_ftssel_d,
56
- };
57
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
58
-}
59
+static gen_helper_gvec_3 * const ftssel_fns[4] = {
60
+ NULL, gen_helper_sve_ftssel_h,
61
+ gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d,
62
+};
63
+TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0)
64
65
/*
66
*** SVE Predicate Logical Operations Group
67
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const rev_fns[4] = {
68
};
69
TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0)
70
71
-static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
72
-{
73
- static gen_helper_gvec_3 * const fns[4] = {
74
- gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
75
- gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
76
- };
77
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
78
-}
79
+static gen_helper_gvec_3 * const sve_tbl_fns[4] = {
80
+ gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
81
+ gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
82
+};
83
+TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0)
84
85
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
86
{
87
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
88
return true;
89
}
90
91
-static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
92
-{
93
- static gen_helper_gvec_3 * const fns[4] = {
94
- gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
95
- gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d
96
- };
97
-
98
- if (!dc_isar_feature(aa64_sve2, s)) {
99
- return false;
100
- }
101
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
102
-}
103
+static gen_helper_gvec_3 * const tbx_fns[4] = {
104
+ gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
105
+ gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d
106
+};
107
+TRANS_FEAT(TBX, aa64_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a, 0)
108
109
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
110
{
111
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const uzp_fns[4] = {
112
gen_helper_sve_uzp_s, gen_helper_sve_uzp_d,
113
};
114
115
-static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a)
116
-{
117
- return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 0);
118
-}
119
+TRANS_FEAT(UZP1_z, aa64_sve, gen_gvec_ool_arg_zzz,
120
+ uzp_fns[a->esz], a, 0)
121
+TRANS_FEAT(UZP2_z, aa64_sve, gen_gvec_ool_arg_zzz,
122
+ uzp_fns[a->esz], a, 1 << a->esz)
123
124
-static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a)
125
-{
126
- return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 1 << a->esz);
127
-}
128
-
129
-static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
130
-{
131
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
132
- return false;
133
- }
134
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 0);
135
-}
136
-
137
-static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
138
-{
139
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
140
- return false;
141
- }
142
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 16);
143
-}
144
+TRANS_FEAT(UZP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
145
+ gen_helper_sve2_uzp_q, a, 0)
146
+TRANS_FEAT(UZP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
147
+ gen_helper_sve2_uzp_q, a, 16)
148
149
static gen_helper_gvec_3 * const trn_fns[4] = {
150
gen_helper_sve_trn_b, gen_helper_sve_trn_h,
151
gen_helper_sve_trn_s, gen_helper_sve_trn_d,
152
};
153
154
-static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a)
155
-{
156
- return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 0);
157
-}
158
+TRANS_FEAT(TRN1_z, aa64_sve, gen_gvec_ool_arg_zzz,
159
+ trn_fns[a->esz], a, 0)
160
+TRANS_FEAT(TRN2_z, aa64_sve, gen_gvec_ool_arg_zzz,
161
+ trn_fns[a->esz], a, 1 << a->esz)
162
163
-static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a)
164
-{
165
- return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 1 << a->esz);
166
-}
167
-
168
-static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
169
-{
170
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
171
- return false;
172
- }
173
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 0);
174
-}
175
-
176
-static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
177
-{
178
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
179
- return false;
180
- }
181
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 16);
182
-}
183
+TRANS_FEAT(TRN1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
184
+ gen_helper_sve2_trn_q, a, 0)
185
+TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
186
+ gen_helper_sve2_trn_q, a, 16)
187
188
/*
189
*** SVE Permute Vector - Predicated Group
190
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
191
TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
192
gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
193
194
-static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
195
-{
196
- if (!dc_isar_feature(aa64_sve2_aes, s)) {
197
- return false;
198
- }
199
- return gen_gvec_ool_arg_zzz(s, gen_helper_crypto_aese, a, decrypt);
200
-}
201
+TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
202
+ gen_helper_crypto_aese, a, false)
203
+TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
204
+ gen_helper_crypto_aese, a, true)
205
206
-static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
207
-{
208
- return do_aese(s, a, false);
209
-}
210
-
211
-static bool trans_AESD(DisasContext *s, arg_rrr_esz *a)
212
-{
213
- return do_aese(s, a, true);
214
-}
215
-
216
-static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
217
-{
218
- if (!dc_isar_feature(aa64_sve2_sm4, s)) {
219
- return false;
220
- }
221
- return gen_gvec_ool_arg_zzz(s, fn, a, 0);
222
-}
223
-
224
-static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
225
-{
226
- return do_sm4(s, a, gen_helper_crypto_sm4e);
227
-}
228
-
229
-static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
230
-{
231
- return do_sm4(s, a, gen_helper_crypto_sm4ekey);
232
-}
233
+TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
234
+ gen_helper_crypto_sm4e, a, 0)
235
+TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
236
+ gen_helper_crypto_sm4ekey, a, 0)
237
238
static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
239
{
240
--
241
2.25.1
diff view generated by jsdifflib
[PULL 010/117] target/arm: Use TRANS_FEAT for do_sve2_zzz_ool
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions using do_sve2_zzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-8-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 88 ++++++++++++++------------------------
12
1 file changed, 31 insertions(+), 57 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
19
return true;
20
}
21
22
-static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
23
- gen_helper_gvec_3 *fn)
24
-{
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zzz(s, fn, a, 0);
29
-}
30
+static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
31
+ gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
32
+ gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d,
33
+};
34
+TRANS_FEAT(SMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
35
+ smulh_zzz_fns[a->esz], a, 0)
36
37
-static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
38
-{
39
- static gen_helper_gvec_3 * const fns[4] = {
40
- gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
41
- gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d,
42
- };
43
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
44
-}
45
+static gen_helper_gvec_3 * const umulh_zzz_fns[4] = {
46
+ gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h,
47
+ gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d,
48
+};
49
+TRANS_FEAT(UMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
50
+ umulh_zzz_fns[a->esz], a, 0)
51
52
-static bool trans_UMULH_zzz(DisasContext *s, arg_rrr_esz *a)
53
-{
54
- static gen_helper_gvec_3 * const fns[4] = {
55
- gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h,
56
- gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d,
57
- };
58
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
59
-}
60
+TRANS_FEAT(PMUL_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
61
+ gen_helper_gvec_pmul_b, a, 0)
62
63
-static bool trans_PMUL_zzz(DisasContext *s, arg_rrr_esz *a)
64
-{
65
- return do_sve2_zzz_ool(s, a, gen_helper_gvec_pmul_b);
66
-}
67
+static gen_helper_gvec_3 * const sqdmulh_zzz_fns[4] = {
68
+ gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h,
69
+ gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d,
70
+};
71
+TRANS_FEAT(SQDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
72
+ sqdmulh_zzz_fns[a->esz], a, 0)
73
74
-static bool trans_SQDMULH_zzz(DisasContext *s, arg_rrr_esz *a)
75
-{
76
- static gen_helper_gvec_3 * const fns[4] = {
77
- gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h,
78
- gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d,
79
- };
80
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
81
-}
82
-
83
-static bool trans_SQRDMULH_zzz(DisasContext *s, arg_rrr_esz *a)
84
-{
85
- static gen_helper_gvec_3 * const fns[4] = {
86
- gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h,
87
- gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d,
88
- };
89
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
90
-}
91
+static gen_helper_gvec_3 * const sqrdmulh_zzz_fns[4] = {
92
+ gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h,
93
+ gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d,
94
+};
95
+TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
96
+ sqrdmulh_zzz_fns[a->esz], a, 0)
97
98
/*
99
* SVE2 Integer - Predicated
100
@@ -XXX,XX +XXX,XX @@ static bool trans_UQRSHRNT(DisasContext *s, arg_rri_esz *a)
101
}
102
103
#define DO_SVE2_ZZZ_NARROW(NAME, name) \
104
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
105
-{ \
106
- static gen_helper_gvec_3 * const fns[4] = { \
107
+ static gen_helper_gvec_3 * const name##_fns[4] = { \
108
NULL, gen_helper_sve2_##name##_h, \
109
gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
110
}; \
111
- return do_sve2_zzz_ool(s, a, fns[a->esz]); \
112
-}
113
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzz, \
114
+ name##_fns[a->esz], a, 0)
115
116
DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb)
117
DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_HISTCNT(DisasContext *s, arg_rprr_esz *a)
119
return do_sve2_zpzz_ool(s, a, fns[a->esz - 2]);
120
}
121
122
-static bool trans_HISTSEG(DisasContext *s, arg_rrr_esz *a)
123
-{
124
- if (a->esz != 0) {
125
- return false;
126
- }
127
- return do_sve2_zzz_ool(s, a, gen_helper_sve2_histseg);
128
-}
129
+TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
130
+ a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
131
132
static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
133
gen_helper_gvec_4_ptr *fn)
134
--
135
2.25.1
diff view generated by jsdifflib
[PULL 011/117] target/arm: Move null function and sve check into gen_gvec_ool_zzzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-9-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 102 ++++++++++++++-----------------------
9
1 file changed, 38 insertions(+), 64 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 4 Zregs. */
19
-static void gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
20
+static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
21
int rd, int rn, int rm, int ra, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- vec_full_reg_offset(s, ra),
28
- vsz, vsz, data, fn);
29
+ if (fn == NULL) {
30
+ return false;
31
+ }
32
+ if (sve_access_check(s)) {
33
+ unsigned vsz = vec_full_reg_size(s);
34
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
35
+ vec_full_reg_offset(s, rn),
36
+ vec_full_reg_offset(s, rm),
37
+ vec_full_reg_offset(s, ra),
38
+ vsz, vsz, data, fn);
39
+ }
40
+ return true;
41
}
42
43
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
44
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
45
if (!dc_isar_feature(aa64_sve2, s)) {
46
return false;
47
}
48
- if (sve_access_check(s)) {
49
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
50
- (a->rn + 1) % 32, a->rm, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
54
+ (a->rn + 1) % 32, a->rm, 0);
55
}
56
57
static gen_helper_gvec_3 * const tbx_fns[4] = {
58
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
59
{ gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
60
{ gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
61
};
62
-
63
- if (sve_access_check(s)) {
64
- gen_gvec_ool_zzzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0);
65
- }
66
- return true;
67
+ return gen_gvec_ool_zzzz(s, fns[a->u][a->sz],
68
+ a->rd, a->rn, a->rm, a->ra, 0);
69
}
70
71
/*
72
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
73
static bool do_zzxz_ool(DisasContext *s, arg_rrxr_esz *a,
74
gen_helper_gvec_4 *fn)
75
{
76
- if (fn == NULL) {
77
- return false;
78
- }
79
- if (sve_access_check(s)) {
80
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
81
- }
82
- return true;
83
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
84
}
85
86
#define DO_RRXR(NAME, FUNC) \
87
@@ -XXX,XX +XXX,XX @@ static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
88
static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
89
gen_helper_gvec_4 *fn, int data)
90
{
91
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
92
+ if (!dc_isar_feature(aa64_sve2, s)) {
93
return false;
94
}
95
- if (sve_access_check(s)) {
96
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
97
- }
98
- return true;
99
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
100
}
101
102
static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
103
@@ -XXX,XX +XXX,XX @@ static bool trans_CMLA_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
104
if (!dc_isar_feature(aa64_sve2, s)) {
105
return false;
106
}
107
- if (sve_access_check(s)) {
108
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot);
109
- }
110
- return true;
111
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
112
+ a->rm, a->ra, a->rot);
113
}
114
115
static bool trans_CDOT_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
116
{
117
- if (!dc_isar_feature(aa64_sve2, s) || a->esz < MO_32) {
118
+ static gen_helper_gvec_4 * const fns[] = {
119
+ NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
120
+ };
121
+
122
+ if (!dc_isar_feature(aa64_sve2, s)) {
123
return false;
124
}
125
- if (sve_access_check(s)) {
126
- gen_helper_gvec_4 *fn = (a->esz == MO_32
127
- ? gen_helper_sve2_cdot_zzzz_s
128
- : gen_helper_sve2_cdot_zzzz_d);
129
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->rot);
130
- }
131
- return true;
132
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
133
+ a->rm, a->ra, a->rot);
134
}
135
136
static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
137
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
138
if (!dc_isar_feature(aa64_sve2, s)) {
139
return false;
140
}
141
- if (sve_access_check(s)) {
142
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot);
143
- }
144
- return true;
145
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
146
+ a->rm, a->ra, a->rot);
147
}
148
149
static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
150
@@ -XXX,XX +XXX,XX @@ static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
151
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
152
return false;
153
}
154
- if (sve_access_check(s)) {
155
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
156
- }
157
- return true;
158
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
159
}
160
161
static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
162
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
163
if (!dc_isar_feature(aa64_sve_bf16, s)) {
164
return false;
165
}
166
- if (sve_access_check(s)) {
167
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
168
- a->rd, a->rn, a->rm, a->ra, 0);
169
- }
170
- return true;
171
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
172
+ a->rd, a->rn, a->rm, a->ra, 0);
173
}
174
175
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
176
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
177
if (!dc_isar_feature(aa64_sve_bf16, s)) {
178
return false;
179
}
180
- if (sve_access_check(s)) {
181
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
182
- a->rd, a->rn, a->rm, a->ra, a->index);
183
- }
184
- return true;
185
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
186
+ a->rd, a->rn, a->rm, a->ra, a->index);
187
}
188
189
static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
190
@@ -XXX,XX +XXX,XX @@ static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
191
if (!dc_isar_feature(aa64_sve_bf16, s)) {
192
return false;
193
}
194
- if (sve_access_check(s)) {
195
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
196
- a->rd, a->rn, a->rm, a->ra, 0);
197
- }
198
- return true;
199
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
200
+ a->rd, a->rn, a->rm, a->ra, 0);
201
}
202
203
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
204
--
205
2.25.1
diff view generated by jsdifflib
[PULL 012/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions directly using
4
gen_gvec_ool_zzzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-10-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 89 +++++++++++++-------------------------
12
1 file changed, 29 insertions(+), 60 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const sve_tbl_fns[4] = {
19
};
20
TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0)
21
22
-static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
23
-{
24
- static gen_helper_gvec_4 * const fns[4] = {
25
- gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h,
26
- gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d
27
- };
28
-
29
- if (!dc_isar_feature(aa64_sve2, s)) {
30
- return false;
31
- }
32
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
33
- (a->rn + 1) % 32, a->rm, 0);
34
-}
35
+static gen_helper_gvec_4 * const sve2_tbl_fns[4] = {
36
+ gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h,
37
+ gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d
38
+};
39
+TRANS_FEAT(TBL_sve2, aa64_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->esz],
40
+ a->rd, a->rn, (a->rn + 1) % 32, a->rm, 0)
41
42
static gen_helper_gvec_3 * const tbx_fns[4] = {
43
gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
44
@@ -XXX,XX +XXX,XX @@ DO_ZZI(UMIN, umin)
45
46
#undef DO_ZZI
47
48
-static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
49
-{
50
- static gen_helper_gvec_4 * const fns[2][2] = {
51
- { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
52
- { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
53
- };
54
- return gen_gvec_ool_zzzz(s, fns[a->u][a->sz],
55
- a->rd, a->rn, a->rm, a->ra, 0);
56
-}
57
+static gen_helper_gvec_4 * const dot_fns[2][2] = {
58
+ { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
59
+ { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
60
+};
61
+TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
62
+ dot_fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0)
63
64
/*
65
* SVE Multiply - Indexed
66
@@ -XXX,XX +XXX,XX @@ static bool trans_UMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
67
return do_umlsl_zzzw(s, a, true);
68
}
69
70
-static bool trans_CMLA_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
71
-{
72
- static gen_helper_gvec_4 * const fns[] = {
73
- gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
74
- gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d,
75
- };
76
+static gen_helper_gvec_4 * const cmla_fns[] = {
77
+ gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
78
+ gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d,
79
+};
80
+TRANS_FEAT(CMLA_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
81
+ cmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
82
83
- if (!dc_isar_feature(aa64_sve2, s)) {
84
- return false;
85
- }
86
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
87
- a->rm, a->ra, a->rot);
88
-}
89
+static gen_helper_gvec_4 * const cdot_fns[] = {
90
+ NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
91
+};
92
+TRANS_FEAT(CDOT_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
93
+ cdot_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
94
95
-static bool trans_CDOT_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
96
-{
97
- static gen_helper_gvec_4 * const fns[] = {
98
- NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
99
- };
100
-
101
- if (!dc_isar_feature(aa64_sve2, s)) {
102
- return false;
103
- }
104
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
105
- a->rm, a->ra, a->rot);
106
-}
107
-
108
-static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
109
-{
110
- static gen_helper_gvec_4 * const fns[] = {
111
- gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h,
112
- gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d,
113
- };
114
-
115
- if (!dc_isar_feature(aa64_sve2, s)) {
116
- return false;
117
- }
118
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
119
- a->rm, a->ra, a->rot);
120
-}
121
+static gen_helper_gvec_4 * const sqrdcmlah_fns[] = {
122
+ gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h,
123
+ gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d,
124
+};
125
+TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
126
+ sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
127
128
static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
129
{
130
--
131
2.25.1
diff view generated by jsdifflib
[PULL 014/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions using do_sve2_zzzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-12-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 263 +++++++++++--------------------------
12
1 file changed, 79 insertions(+), 184 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
19
return do_cadd(s, a, true, true);
20
}
21
22
-static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
23
- gen_helper_gvec_4 *fn, int data)
24
-{
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zzzz(s, fn, a, data);
29
-}
30
+static gen_helper_gvec_4 * const sabal_fns[4] = {
31
+ NULL, gen_helper_sve2_sabal_h,
32
+ gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d,
33
+};
34
+TRANS_FEAT(SABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 0)
35
+TRANS_FEAT(SABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 1)
36
37
-static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
38
-{
39
- static gen_helper_gvec_4 * const fns[2][4] = {
40
- { NULL, gen_helper_sve2_sabal_h,
41
- gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d },
42
- { NULL, gen_helper_sve2_uabal_h,
43
- gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d },
44
- };
45
- return do_sve2_zzzz_ool(s, a, fns[uns][a->esz], sel);
46
-}
47
-
48
-static bool trans_SABALB(DisasContext *s, arg_rrrr_esz *a)
49
-{
50
- return do_abal(s, a, false, false);
51
-}
52
-
53
-static bool trans_SABALT(DisasContext *s, arg_rrrr_esz *a)
54
-{
55
- return do_abal(s, a, false, true);
56
-}
57
-
58
-static bool trans_UABALB(DisasContext *s, arg_rrrr_esz *a)
59
-{
60
- return do_abal(s, a, true, false);
61
-}
62
-
63
-static bool trans_UABALT(DisasContext *s, arg_rrrr_esz *a)
64
-{
65
- return do_abal(s, a, true, true);
66
-}
67
+static gen_helper_gvec_4 * const uabal_fns[4] = {
68
+ NULL, gen_helper_sve2_uabal_h,
69
+ gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d,
70
+};
71
+TRANS_FEAT(UABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 0)
72
+TRANS_FEAT(UABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 1)
73
74
static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
75
{
76
@@ -XXX,XX +XXX,XX @@ static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
77
* Note that in this case the ESZ field encodes both size and sign.
78
* Split out 'subtract' into bit 1 of the data field for the helper.
79
*/
80
- return do_sve2_zzzz_ool(s, a, fns[a->esz & 1], (a->esz & 2) | sel);
81
+ return gen_gvec_ool_arg_zzzz(s, fns[a->esz & 1], a, (a->esz & 2) | sel);
82
}
83
84
-static bool trans_ADCLB(DisasContext *s, arg_rrrr_esz *a)
85
-{
86
- return do_adcl(s, a, false);
87
-}
88
-
89
-static bool trans_ADCLT(DisasContext *s, arg_rrrr_esz *a)
90
-{
91
- return do_adcl(s, a, true);
92
-}
93
+TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false)
94
+TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
95
96
static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
97
{
98
@@ -XXX,XX +XXX,XX @@ static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
99
return true;
100
}
101
102
-static bool do_sqdmlal_zzzw(DisasContext *s, arg_rrrr_esz *a,
103
- bool sel1, bool sel2)
104
-{
105
- static gen_helper_gvec_4 * const fns[] = {
106
- NULL, gen_helper_sve2_sqdmlal_zzzw_h,
107
- gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d,
108
- };
109
- return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1);
110
-}
111
+static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
112
+ NULL, gen_helper_sve2_sqdmlal_zzzw_h,
113
+ gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d,
114
+};
115
+TRANS_FEAT(SQDMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
116
+ sqdmlal_zzzw_fns[a->esz], a, 0)
117
+TRANS_FEAT(SQDMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
118
+ sqdmlal_zzzw_fns[a->esz], a, 3)
119
+TRANS_FEAT(SQDMLALBT, aa64_sve2, gen_gvec_ool_arg_zzzz,
120
+ sqdmlal_zzzw_fns[a->esz], a, 2)
121
122
-static bool do_sqdmlsl_zzzw(DisasContext *s, arg_rrrr_esz *a,
123
- bool sel1, bool sel2)
124
-{
125
- static gen_helper_gvec_4 * const fns[] = {
126
- NULL, gen_helper_sve2_sqdmlsl_zzzw_h,
127
- gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d,
128
- };
129
- return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1);
130
-}
131
+static gen_helper_gvec_4 * const sqdmlsl_zzzw_fns[] = {
132
+ NULL, gen_helper_sve2_sqdmlsl_zzzw_h,
133
+ gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d,
134
+};
135
+TRANS_FEAT(SQDMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
136
+ sqdmlsl_zzzw_fns[a->esz], a, 0)
137
+TRANS_FEAT(SQDMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
138
+ sqdmlsl_zzzw_fns[a->esz], a, 3)
139
+TRANS_FEAT(SQDMLSLBT, aa64_sve2, gen_gvec_ool_arg_zzzz,
140
+ sqdmlsl_zzzw_fns[a->esz], a, 2)
141
142
-static bool trans_SQDMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
143
-{
144
- return do_sqdmlal_zzzw(s, a, false, false);
145
-}
146
+static gen_helper_gvec_4 * const sqrdmlah_fns[] = {
147
+ gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h,
148
+ gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d,
149
+};
150
+TRANS_FEAT(SQRDMLAH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz,
151
+ sqrdmlah_fns[a->esz], a, 0)
152
153
-static bool trans_SQDMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
154
-{
155
- return do_sqdmlal_zzzw(s, a, true, true);
156
-}
157
+static gen_helper_gvec_4 * const sqrdmlsh_fns[] = {
158
+ gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h,
159
+ gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d,
160
+};
161
+TRANS_FEAT(SQRDMLSH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz,
162
+ sqrdmlsh_fns[a->esz], a, 0)
163
164
-static bool trans_SQDMLALBT(DisasContext *s, arg_rrrr_esz *a)
165
-{
166
- return do_sqdmlal_zzzw(s, a, false, true);
167
-}
168
+static gen_helper_gvec_4 * const smlal_zzzw_fns[] = {
169
+ NULL, gen_helper_sve2_smlal_zzzw_h,
170
+ gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d,
171
+};
172
+TRANS_FEAT(SMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
173
+ smlal_zzzw_fns[a->esz], a, 0)
174
+TRANS_FEAT(SMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
175
+ smlal_zzzw_fns[a->esz], a, 1)
176
177
-static bool trans_SQDMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
178
-{
179
- return do_sqdmlsl_zzzw(s, a, false, false);
180
-}
181
+static gen_helper_gvec_4 * const umlal_zzzw_fns[] = {
182
+ NULL, gen_helper_sve2_umlal_zzzw_h,
183
+ gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d,
184
+};
185
+TRANS_FEAT(UMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
186
+ umlal_zzzw_fns[a->esz], a, 0)
187
+TRANS_FEAT(UMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
188
+ umlal_zzzw_fns[a->esz], a, 1)
189
190
-static bool trans_SQDMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
191
-{
192
- return do_sqdmlsl_zzzw(s, a, true, true);
193
-}
194
+static gen_helper_gvec_4 * const smlsl_zzzw_fns[] = {
195
+ NULL, gen_helper_sve2_smlsl_zzzw_h,
196
+ gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d,
197
+};
198
+TRANS_FEAT(SMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
199
+ smlsl_zzzw_fns[a->esz], a, 0)
200
+TRANS_FEAT(SMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
201
+ smlsl_zzzw_fns[a->esz], a, 1)
202
203
-static bool trans_SQDMLSLBT(DisasContext *s, arg_rrrr_esz *a)
204
-{
205
- return do_sqdmlsl_zzzw(s, a, false, true);
206
-}
207
-
208
-static bool trans_SQRDMLAH_zzzz(DisasContext *s, arg_rrrr_esz *a)
209
-{
210
- static gen_helper_gvec_4 * const fns[] = {
211
- gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h,
212
- gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d,
213
- };
214
- return do_sve2_zzzz_ool(s, a, fns[a->esz], 0);
215
-}
216
-
217
-static bool trans_SQRDMLSH_zzzz(DisasContext *s, arg_rrrr_esz *a)
218
-{
219
- static gen_helper_gvec_4 * const fns[] = {
220
- gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h,
221
- gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d,
222
- };
223
- return do_sve2_zzzz_ool(s, a, fns[a->esz], 0);
224
-}
225
-
226
-static bool do_smlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
227
-{
228
- static gen_helper_gvec_4 * const fns[] = {
229
- NULL, gen_helper_sve2_smlal_zzzw_h,
230
- gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d,
231
- };
232
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
233
-}
234
-
235
-static bool trans_SMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
236
-{
237
- return do_smlal_zzzw(s, a, false);
238
-}
239
-
240
-static bool trans_SMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
241
-{
242
- return do_smlal_zzzw(s, a, true);
243
-}
244
-
245
-static bool do_umlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
246
-{
247
- static gen_helper_gvec_4 * const fns[] = {
248
- NULL, gen_helper_sve2_umlal_zzzw_h,
249
- gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d,
250
- };
251
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
252
-}
253
-
254
-static bool trans_UMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
255
-{
256
- return do_umlal_zzzw(s, a, false);
257
-}
258
-
259
-static bool trans_UMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
260
-{
261
- return do_umlal_zzzw(s, a, true);
262
-}
263
-
264
-static bool do_smlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
265
-{
266
- static gen_helper_gvec_4 * const fns[] = {
267
- NULL, gen_helper_sve2_smlsl_zzzw_h,
268
- gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d,
269
- };
270
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
271
-}
272
-
273
-static bool trans_SMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
274
-{
275
- return do_smlsl_zzzw(s, a, false);
276
-}
277
-
278
-static bool trans_SMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
279
-{
280
- return do_smlsl_zzzw(s, a, true);
281
-}
282
-
283
-static bool do_umlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
284
-{
285
- static gen_helper_gvec_4 * const fns[] = {
286
- NULL, gen_helper_sve2_umlsl_zzzw_h,
287
- gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d,
288
- };
289
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
290
-}
291
-
292
-static bool trans_UMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
293
-{
294
- return do_umlsl_zzzw(s, a, false);
295
-}
296
-
297
-static bool trans_UMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
298
-{
299
- return do_umlsl_zzzw(s, a, true);
300
-}
301
+static gen_helper_gvec_4 * const umlsl_zzzw_fns[] = {
302
+ NULL, gen_helper_sve2_umlsl_zzzw_h,
303
+ gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d,
304
+};
305
+TRANS_FEAT(UMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
306
+ umlsl_zzzw_fns[a->esz], a, 0)
307
+TRANS_FEAT(UMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
308
+ umlsl_zzzw_fns[a->esz], a, 1)
309
310
static gen_helper_gvec_4 * const cmla_fns[] = {
311
gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
312
--
313
2.25.1
diff view generated by jsdifflib
[PULL 015/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zzzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-13-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 47 ++++++++------------------------------
12
1 file changed, 10 insertions(+), 37 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_FMLSLT_zzxw(DisasContext *s, arg_rrxr_esz *a)
19
return do_FMLAL_zzxw(s, a, true, true);
20
}
21
22
-static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
23
- gen_helper_gvec_4 *fn, int data)
24
-{
25
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zzzz(s, fn, a, data);
29
-}
30
+TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
31
+ gen_helper_gvec_smmla_b, a, 0)
32
+TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
33
+ gen_helper_gvec_usmmla_b, a, 0)
34
+TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
35
+ gen_helper_gvec_ummla_b, a, 0)
36
37
-static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
38
-{
39
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_smmla_b, 0);
40
-}
41
-
42
-static bool trans_USMMLA(DisasContext *s, arg_rrrr_esz *a)
43
-{
44
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_usmmla_b, 0);
45
-}
46
-
47
-static bool trans_UMMLA(DisasContext *s, arg_rrrr_esz *a)
48
-{
49
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_ummla_b, 0);
50
-}
51
-
52
-static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
53
-{
54
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
55
- return false;
56
- }
57
- return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfdot, a, 0);
58
-}
59
+TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
60
+ gen_helper_gvec_bfdot, a, 0)
61
62
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
63
{
64
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
65
a->rd, a->rn, a->rm, a->ra, a->index);
66
}
67
68
-static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
69
-{
70
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
71
- return false;
72
- }
73
- return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfmmla, a, 0);
74
-}
75
+TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
76
+ gen_helper_gvec_bfmmla, a, 0)
77
78
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
79
{
80
--
81
2.25.1
diff view generated by jsdifflib
[PULL 017/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zzxz to TRANS_FEAT. Also include
5
BFDOT_zzxz, which was using gen_gvec_ool_zzzz.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-15-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 48 +++++++++++---------------------------
13
1 file changed, 14 insertions(+), 34 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
20
* SVE Multiply - Indexed
21
*/
22
23
-#define DO_RRXR(NAME, FUNC) \
24
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
25
- { return gen_gvec_ool_arg_zzxz(s, FUNC, a); }
26
+TRANS_FEAT(SDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz,
27
+ gen_helper_gvec_sdot_idx_b, a)
28
+TRANS_FEAT(SDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz,
29
+ gen_helper_gvec_sdot_idx_h, a)
30
+TRANS_FEAT(UDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz,
31
+ gen_helper_gvec_udot_idx_b, a)
32
+TRANS_FEAT(UDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz,
33
+ gen_helper_gvec_udot_idx_h, a)
34
35
-DO_RRXR(trans_SDOT_zzxw_s, gen_helper_gvec_sdot_idx_b)
36
-DO_RRXR(trans_SDOT_zzxw_d, gen_helper_gvec_sdot_idx_h)
37
-DO_RRXR(trans_UDOT_zzxw_s, gen_helper_gvec_udot_idx_b)
38
-DO_RRXR(trans_UDOT_zzxw_d, gen_helper_gvec_udot_idx_h)
39
-
40
-static bool trans_SUDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
41
-{
42
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
43
- return false;
44
- }
45
- return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_sudot_idx_b, a);
46
-}
47
-
48
-static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
49
-{
50
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
51
- return false;
52
- }
53
- return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_usdot_idx_b, a);
54
-}
55
-
56
-#undef DO_RRXR
57
+TRANS_FEAT(SUDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
58
+ gen_helper_gvec_sudot_idx_b, a)
59
+TRANS_FEAT(USDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
60
+ gen_helper_gvec_usdot_idx_b, a)
61
62
static bool do_sve2_zzz_data(DisasContext *s, int rd, int rn, int rm, int data,
63
gen_helper_gvec_3 *fn)
64
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
65
66
TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
67
gen_helper_gvec_bfdot, a, 0)
68
-
69
-static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
70
-{
71
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
72
- return false;
73
- }
74
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
75
- a->rd, a->rn, a->rm, a->ra, a->index);
76
-}
77
+TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz,
78
+ gen_helper_gvec_bfdot_idx, a)
79
80
TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
81
gen_helper_gvec_bfmmla, a, 0)
82
--
83
2.25.1
diff view generated by jsdifflib
[PULL 019/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions using do_sve2_zzzz_data
4
to use TRANS_FEAT and gen_gvec_ool_{zzzz,zzxz}.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-17-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 106 ++++++++++++++-----------------------
12
1 file changed, 41 insertions(+), 65 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
19
20
#undef DO_SVE2_RRX_TB
21
22
-static bool do_sve2_zzzz_data(DisasContext *s, int rd, int rn, int rm, int ra,
23
- int data, gen_helper_gvec_4 *fn)
24
-{
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- if (sve_access_check(s)) {
29
- unsigned vsz = vec_full_reg_size(s);
30
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
31
- vec_full_reg_offset(s, rn),
32
- vec_full_reg_offset(s, rm),
33
- vec_full_reg_offset(s, ra),
34
- vsz, vsz, data, fn);
35
- }
36
- return true;
37
-}
38
-
39
#define DO_SVE2_RRXR(NAME, FUNC) \
40
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
41
- { return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, a->index, FUNC); }
42
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a)
43
44
-DO_SVE2_RRXR(trans_MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
45
-DO_SVE2_RRXR(trans_MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
46
-DO_SVE2_RRXR(trans_MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
47
+DO_SVE2_RRXR(MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
48
+DO_SVE2_RRXR(MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
49
+DO_SVE2_RRXR(MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
50
51
-DO_SVE2_RRXR(trans_MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
52
-DO_SVE2_RRXR(trans_MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
53
-DO_SVE2_RRXR(trans_MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
54
+DO_SVE2_RRXR(MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
55
+DO_SVE2_RRXR(MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
56
+DO_SVE2_RRXR(MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
57
58
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
59
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
60
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
61
+DO_SVE2_RRXR(SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
62
+DO_SVE2_RRXR(SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
63
+DO_SVE2_RRXR(SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
64
65
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
66
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
67
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
68
+DO_SVE2_RRXR(SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
69
+DO_SVE2_RRXR(SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
70
+DO_SVE2_RRXR(SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
71
72
#undef DO_SVE2_RRXR
73
74
#define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \
75
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
76
- { \
77
- return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->rd, \
78
- (a->index << 1) | TOP, FUNC); \
79
- }
80
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
81
+ a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP)
82
83
-DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false)
84
-DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false)
85
-DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true)
86
-DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true)
87
+DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false)
88
+DO_SVE2_RRXR_TB(SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false)
89
+DO_SVE2_RRXR_TB(SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true)
90
+DO_SVE2_RRXR_TB(SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true)
91
92
-DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false)
93
-DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false)
94
-DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
95
-DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
96
+DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false)
97
+DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false)
98
+DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
99
+DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
100
101
-DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
102
-DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
103
-DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
104
-DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
105
+DO_SVE2_RRXR_TB(SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
106
+DO_SVE2_RRXR_TB(SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
107
+DO_SVE2_RRXR_TB(SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
108
+DO_SVE2_RRXR_TB(SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
109
110
-DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
111
-DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
112
-DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
113
-DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
114
+DO_SVE2_RRXR_TB(UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
115
+DO_SVE2_RRXR_TB(UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
116
+DO_SVE2_RRXR_TB(UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
117
+DO_SVE2_RRXR_TB(UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
118
119
-DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
120
-DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
121
-DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
122
-DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
123
+DO_SVE2_RRXR_TB(SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
124
+DO_SVE2_RRXR_TB(SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
125
+DO_SVE2_RRXR_TB(SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
126
+DO_SVE2_RRXR_TB(SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
127
128
-DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
129
-DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
130
-DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
131
-DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
132
+DO_SVE2_RRXR_TB(UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
133
+DO_SVE2_RRXR_TB(UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
134
+DO_SVE2_RRXR_TB(UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
135
+DO_SVE2_RRXR_TB(UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
136
137
#undef DO_SVE2_RRXR_TB
138
139
#define DO_SVE2_RRXR_ROT(NAME, FUNC) \
140
- static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
141
- { \
142
- return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, \
143
- (a->index << 2) | a->rot, FUNC); \
144
- }
145
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
146
+ a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot)
147
148
DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h)
149
DO_SVE2_RRXR_ROT(CMLA_zzxz_s, gen_helper_sve2_cmla_idx_s)
150
--
151
2.25.1
diff view generated by jsdifflib
[PULL 020/117] target/arm: Use TRANS_FEAT for do_sve2_zzw_data
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions using do_sve2_zzw_data
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-18-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 297 ++++++++++++++++++-------------------
12
1 file changed, 145 insertions(+), 152 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZPZZ(USQADD, usqadd)
19
* SVE2 Widening Integer Arithmetic
20
*/
21
22
-static bool do_sve2_zzw_ool(DisasContext *s, arg_rrr_esz *a,
23
- gen_helper_gvec_3 *fn, int data)
24
-{
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- if (sve_access_check(s)) {
29
- unsigned vsz = vec_full_reg_size(s);
30
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
31
- vec_full_reg_offset(s, a->rn),
32
- vec_full_reg_offset(s, a->rm),
33
- vsz, vsz, data, fn);
34
- }
35
- return true;
36
-}
37
+static gen_helper_gvec_3 * const saddl_fns[4] = {
38
+ NULL, gen_helper_sve2_saddl_h,
39
+ gen_helper_sve2_saddl_s, gen_helper_sve2_saddl_d,
40
+};
41
+TRANS_FEAT(SADDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
42
+ saddl_fns[a->esz], a, 0)
43
+TRANS_FEAT(SADDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
44
+ saddl_fns[a->esz], a, 3)
45
+TRANS_FEAT(SADDLBT, aa64_sve2, gen_gvec_ool_arg_zzz,
46
+ saddl_fns[a->esz], a, 2)
47
48
-#define DO_SVE2_ZZZ_TB(NAME, name, SEL1, SEL2) \
49
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
50
-{ \
51
- static gen_helper_gvec_3 * const fns[4] = { \
52
- NULL, gen_helper_sve2_##name##_h, \
53
- gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
54
- }; \
55
- return do_sve2_zzw_ool(s, a, fns[a->esz], (SEL2 << 1) | SEL1); \
56
-}
57
+static gen_helper_gvec_3 * const ssubl_fns[4] = {
58
+ NULL, gen_helper_sve2_ssubl_h,
59
+ gen_helper_sve2_ssubl_s, gen_helper_sve2_ssubl_d,
60
+};
61
+TRANS_FEAT(SSUBLB, aa64_sve2, gen_gvec_ool_arg_zzz,
62
+ ssubl_fns[a->esz], a, 0)
63
+TRANS_FEAT(SSUBLT, aa64_sve2, gen_gvec_ool_arg_zzz,
64
+ ssubl_fns[a->esz], a, 3)
65
+TRANS_FEAT(SSUBLBT, aa64_sve2, gen_gvec_ool_arg_zzz,
66
+ ssubl_fns[a->esz], a, 2)
67
+TRANS_FEAT(SSUBLTB, aa64_sve2, gen_gvec_ool_arg_zzz,
68
+ ssubl_fns[a->esz], a, 1)
69
70
-DO_SVE2_ZZZ_TB(SADDLB, saddl, false, false)
71
-DO_SVE2_ZZZ_TB(SSUBLB, ssubl, false, false)
72
-DO_SVE2_ZZZ_TB(SABDLB, sabdl, false, false)
73
+static gen_helper_gvec_3 * const sabdl_fns[4] = {
74
+ NULL, gen_helper_sve2_sabdl_h,
75
+ gen_helper_sve2_sabdl_s, gen_helper_sve2_sabdl_d,
76
+};
77
+TRANS_FEAT(SABDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
78
+ sabdl_fns[a->esz], a, 0)
79
+TRANS_FEAT(SABDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
80
+ sabdl_fns[a->esz], a, 3)
81
82
-DO_SVE2_ZZZ_TB(UADDLB, uaddl, false, false)
83
-DO_SVE2_ZZZ_TB(USUBLB, usubl, false, false)
84
-DO_SVE2_ZZZ_TB(UABDLB, uabdl, false, false)
85
+static gen_helper_gvec_3 * const uaddl_fns[4] = {
86
+ NULL, gen_helper_sve2_uaddl_h,
87
+ gen_helper_sve2_uaddl_s, gen_helper_sve2_uaddl_d,
88
+};
89
+TRANS_FEAT(UADDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
90
+ uaddl_fns[a->esz], a, 0)
91
+TRANS_FEAT(UADDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
92
+ uaddl_fns[a->esz], a, 3)
93
94
-DO_SVE2_ZZZ_TB(SADDLT, saddl, true, true)
95
-DO_SVE2_ZZZ_TB(SSUBLT, ssubl, true, true)
96
-DO_SVE2_ZZZ_TB(SABDLT, sabdl, true, true)
97
+static gen_helper_gvec_3 * const usubl_fns[4] = {
98
+ NULL, gen_helper_sve2_usubl_h,
99
+ gen_helper_sve2_usubl_s, gen_helper_sve2_usubl_d,
100
+};
101
+TRANS_FEAT(USUBLB, aa64_sve2, gen_gvec_ool_arg_zzz,
102
+ usubl_fns[a->esz], a, 0)
103
+TRANS_FEAT(USUBLT, aa64_sve2, gen_gvec_ool_arg_zzz,
104
+ usubl_fns[a->esz], a, 3)
105
106
-DO_SVE2_ZZZ_TB(UADDLT, uaddl, true, true)
107
-DO_SVE2_ZZZ_TB(USUBLT, usubl, true, true)
108
-DO_SVE2_ZZZ_TB(UABDLT, uabdl, true, true)
109
+static gen_helper_gvec_3 * const uabdl_fns[4] = {
110
+ NULL, gen_helper_sve2_uabdl_h,
111
+ gen_helper_sve2_uabdl_s, gen_helper_sve2_uabdl_d,
112
+};
113
+TRANS_FEAT(UABDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
114
+ uabdl_fns[a->esz], a, 0)
115
+TRANS_FEAT(UABDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
116
+ uabdl_fns[a->esz], a, 3)
117
118
-DO_SVE2_ZZZ_TB(SADDLBT, saddl, false, true)
119
-DO_SVE2_ZZZ_TB(SSUBLBT, ssubl, false, true)
120
-DO_SVE2_ZZZ_TB(SSUBLTB, ssubl, true, false)
121
+static gen_helper_gvec_3 * const sqdmull_fns[4] = {
122
+ NULL, gen_helper_sve2_sqdmull_zzz_h,
123
+ gen_helper_sve2_sqdmull_zzz_s, gen_helper_sve2_sqdmull_zzz_d,
124
+};
125
+TRANS_FEAT(SQDMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
126
+ sqdmull_fns[a->esz], a, 0)
127
+TRANS_FEAT(SQDMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
128
+ sqdmull_fns[a->esz], a, 3)
129
130
-DO_SVE2_ZZZ_TB(SQDMULLB_zzz, sqdmull_zzz, false, false)
131
-DO_SVE2_ZZZ_TB(SQDMULLT_zzz, sqdmull_zzz, true, true)
132
+static gen_helper_gvec_3 * const smull_fns[4] = {
133
+ NULL, gen_helper_sve2_smull_zzz_h,
134
+ gen_helper_sve2_smull_zzz_s, gen_helper_sve2_smull_zzz_d,
135
+};
136
+TRANS_FEAT(SMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
137
+ smull_fns[a->esz], a, 0)
138
+TRANS_FEAT(SMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
139
+ smull_fns[a->esz], a, 3)
140
141
-DO_SVE2_ZZZ_TB(SMULLB_zzz, smull_zzz, false, false)
142
-DO_SVE2_ZZZ_TB(SMULLT_zzz, smull_zzz, true, true)
143
+static gen_helper_gvec_3 * const umull_fns[4] = {
144
+ NULL, gen_helper_sve2_umull_zzz_h,
145
+ gen_helper_sve2_umull_zzz_s, gen_helper_sve2_umull_zzz_d,
146
+};
147
+TRANS_FEAT(UMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
148
+ umull_fns[a->esz], a, 0)
149
+TRANS_FEAT(UMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
150
+ umull_fns[a->esz], a, 3)
151
152
-DO_SVE2_ZZZ_TB(UMULLB_zzz, umull_zzz, false, false)
153
-DO_SVE2_ZZZ_TB(UMULLT_zzz, umull_zzz, true, true)
154
-
155
-static bool do_eor_tb(DisasContext *s, arg_rrr_esz *a, bool sel1)
156
-{
157
- static gen_helper_gvec_3 * const fns[4] = {
158
- gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h,
159
- gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d,
160
- };
161
- return do_sve2_zzw_ool(s, a, fns[a->esz], (!sel1 << 1) | sel1);
162
-}
163
-
164
-static bool trans_EORBT(DisasContext *s, arg_rrr_esz *a)
165
-{
166
- return do_eor_tb(s, a, false);
167
-}
168
-
169
-static bool trans_EORTB(DisasContext *s, arg_rrr_esz *a)
170
-{
171
- return do_eor_tb(s, a, true);
172
-}
173
+static gen_helper_gvec_3 * const eoril_fns[4] = {
174
+ gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h,
175
+ gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d,
176
+};
177
+TRANS_FEAT(EORBT, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 2)
178
+TRANS_FEAT(EORTB, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 1)
179
180
static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
181
{
182
@@ -XXX,XX +XXX,XX @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
183
if (a->esz == 0 && !dc_isar_feature(aa64_sve2_pmull128, s)) {
184
return false;
185
}
186
- return do_sve2_zzw_ool(s, a, fns[a->esz], sel);
187
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
188
}
189
190
-static bool trans_PMULLB(DisasContext *s, arg_rrr_esz *a)
191
-{
192
- return do_trans_pmull(s, a, false);
193
-}
194
+TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false)
195
+TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true)
196
197
-static bool trans_PMULLT(DisasContext *s, arg_rrr_esz *a)
198
-{
199
- return do_trans_pmull(s, a, true);
200
-}
201
+static gen_helper_gvec_3 * const saddw_fns[4] = {
202
+ NULL, gen_helper_sve2_saddw_h,
203
+ gen_helper_sve2_saddw_s, gen_helper_sve2_saddw_d,
204
+};
205
+TRANS_FEAT(SADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 0)
206
+TRANS_FEAT(SADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 1)
207
208
-#define DO_SVE2_ZZZ_WTB(NAME, name, SEL2) \
209
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
210
-{ \
211
- static gen_helper_gvec_3 * const fns[4] = { \
212
- NULL, gen_helper_sve2_##name##_h, \
213
- gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
214
- }; \
215
- return do_sve2_zzw_ool(s, a, fns[a->esz], SEL2); \
216
-}
217
+static gen_helper_gvec_3 * const ssubw_fns[4] = {
218
+ NULL, gen_helper_sve2_ssubw_h,
219
+ gen_helper_sve2_ssubw_s, gen_helper_sve2_ssubw_d,
220
+};
221
+TRANS_FEAT(SSUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 0)
222
+TRANS_FEAT(SSUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 1)
223
224
-DO_SVE2_ZZZ_WTB(SADDWB, saddw, false)
225
-DO_SVE2_ZZZ_WTB(SADDWT, saddw, true)
226
-DO_SVE2_ZZZ_WTB(SSUBWB, ssubw, false)
227
-DO_SVE2_ZZZ_WTB(SSUBWT, ssubw, true)
228
+static gen_helper_gvec_3 * const uaddw_fns[4] = {
229
+ NULL, gen_helper_sve2_uaddw_h,
230
+ gen_helper_sve2_uaddw_s, gen_helper_sve2_uaddw_d,
231
+};
232
+TRANS_FEAT(UADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 0)
233
+TRANS_FEAT(UADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 1)
234
235
-DO_SVE2_ZZZ_WTB(UADDWB, uaddw, false)
236
-DO_SVE2_ZZZ_WTB(UADDWT, uaddw, true)
237
-DO_SVE2_ZZZ_WTB(USUBWB, usubw, false)
238
-DO_SVE2_ZZZ_WTB(USUBWT, usubw, true)
239
+static gen_helper_gvec_3 * const usubw_fns[4] = {
240
+ NULL, gen_helper_sve2_usubw_h,
241
+ gen_helper_sve2_usubw_s, gen_helper_sve2_usubw_d,
242
+};
243
+TRANS_FEAT(USUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 0)
244
+TRANS_FEAT(USUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 1)
245
246
static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm)
247
{
248
@@ -XXX,XX +XXX,XX @@ static bool trans_USHLLT(DisasContext *s, arg_rri_esz *a)
249
return do_sve2_shll_tb(s, a, true, true);
250
}
251
252
-static bool trans_BEXT(DisasContext *s, arg_rrr_esz *a)
253
-{
254
- static gen_helper_gvec_3 * const fns[4] = {
255
- gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
256
- gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
257
- };
258
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
259
- return false;
260
- }
261
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
262
-}
263
+static gen_helper_gvec_3 * const bext_fns[4] = {
264
+ gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
265
+ gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
266
+};
267
+TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
268
+ bext_fns[a->esz], a, 0)
269
270
-static bool trans_BDEP(DisasContext *s, arg_rrr_esz *a)
271
-{
272
- static gen_helper_gvec_3 * const fns[4] = {
273
- gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
274
- gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
275
- };
276
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
277
- return false;
278
- }
279
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
280
-}
281
+static gen_helper_gvec_3 * const bdep_fns[4] = {
282
+ gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
283
+ gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
284
+};
285
+TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
286
+ bdep_fns[a->esz], a, 0)
287
288
-static bool trans_BGRP(DisasContext *s, arg_rrr_esz *a)
289
-{
290
- static gen_helper_gvec_3 * const fns[4] = {
291
- gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
292
- gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
293
- };
294
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
295
- return false;
296
- }
297
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
298
-}
299
+static gen_helper_gvec_3 * const bgrp_fns[4] = {
300
+ gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
301
+ gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
302
+};
303
+TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
304
+ bgrp_fns[a->esz], a, 0)
305
306
-static bool do_cadd(DisasContext *s, arg_rrr_esz *a, bool sq, bool rot)
307
-{
308
- static gen_helper_gvec_3 * const fns[2][4] = {
309
- { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
310
- gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d },
311
- { gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
312
- gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d },
313
- };
314
- return do_sve2_zzw_ool(s, a, fns[sq][a->esz], rot);
315
-}
316
+static gen_helper_gvec_3 * const cadd_fns[4] = {
317
+ gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
318
+ gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d,
319
+};
320
+TRANS_FEAT(CADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz,
321
+ cadd_fns[a->esz], a, 0)
322
+TRANS_FEAT(CADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz,
323
+ cadd_fns[a->esz], a, 1)
324
325
-static bool trans_CADD_rot90(DisasContext *s, arg_rrr_esz *a)
326
-{
327
- return do_cadd(s, a, false, false);
328
-}
329
-
330
-static bool trans_CADD_rot270(DisasContext *s, arg_rrr_esz *a)
331
-{
332
- return do_cadd(s, a, false, true);
333
-}
334
-
335
-static bool trans_SQCADD_rot90(DisasContext *s, arg_rrr_esz *a)
336
-{
337
- return do_cadd(s, a, true, false);
338
-}
339
-
340
-static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
341
-{
342
- return do_cadd(s, a, true, true);
343
-}
344
+static gen_helper_gvec_3 * const sqcadd_fns[4] = {
345
+ gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
346
+ gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d,
347
+};
348
+TRANS_FEAT(SQCADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz,
349
+ sqcadd_fns[a->esz], a, 0)
350
+TRANS_FEAT(SQCADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz,
351
+ sqcadd_fns[a->esz], a, 1)
352
353
static gen_helper_gvec_4 * const sabal_fns[4] = {
354
NULL, gen_helper_sve2_sabal_h,
355
--
356
2.25.1
diff view generated by jsdifflib
[PULL 021/117] target/arm: Use TRANS_FEAT for USDOT_zzzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This is the last direct user of tcg_gen_gvec_4_ool.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-19-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 17 ++---------------
11
1 file changed, 2 insertions(+), 15 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_4 * const sqrdcmlah_fns[] = {
18
TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
19
sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
20
21
-static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
22
-{
23
- if (a->esz != 2 || !dc_isar_feature(aa64_sve_i8mm, s)) {
24
- return false;
25
- }
26
- if (sve_access_check(s)) {
27
- unsigned vsz = vec_full_reg_size(s);
28
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
29
- vec_full_reg_offset(s, a->rn),
30
- vec_full_reg_offset(s, a->rm),
31
- vec_full_reg_offset(s, a->ra),
32
- vsz, vsz, 0, gen_helper_gvec_usdot_b);
33
- }
34
- return true;
35
-}
36
+TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
37
+ a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0)
38
39
TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
40
gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
41
--
42
2.25.1
diff view generated by jsdifflib
[PULL 022/117] target/arm: Move null function and sve check into gen_gvec_ool_zzp
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-20-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 37 +++++++++++++++----------------------
9
1 file changed, 15 insertions(+), 22 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
19
-static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
20
+static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
21
int rd, int rn, int pg, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- pred_full_reg_offset(s, pg),
27
- vsz, vsz, data, fn);
28
+ if (fn == NULL) {
29
+ return false;
30
+ }
31
+ if (sve_access_check(s)) {
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
34
+ vec_full_reg_offset(s, rn),
35
+ pred_full_reg_offset(s, pg),
36
+ vsz, vsz, data, fn);
37
+ }
38
+ return true;
39
}
40
41
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
42
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
43
44
static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
45
{
46
- if (fn == NULL) {
47
- return false;
48
- }
49
- if (sve_access_check(s)) {
50
- gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
54
}
55
56
#define DO_ZPZ(NAME, name) \
57
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
58
gen_helper_sve_movz_b, gen_helper_sve_movz_h,
59
gen_helper_sve_movz_s, gen_helper_sve_movz_d,
60
};
61
-
62
- if (sve_access_check(s)) {
63
- gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
64
- }
65
- return true;
66
+ return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
67
}
68
69
static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
70
gen_helper_gvec_3 *fn)
71
{
72
- if (sve_access_check(s)) {
73
- gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
74
- }
75
- return true;
76
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
77
}
78
79
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
80
--
81
2.25.1
diff view generated by jsdifflib
[PULL 023/117] target/arm: Introduce gen_gvec_ool_arg_zpz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Use gen_gvec_ool_arg_zpz instead of gen_gvec_ool_zzp
4
when the arguments come from arg_rpr_esz.
5
Replaces do_zpz_ool.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-21-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 45 +++++++++++++++++++++-----------------
13
1 file changed, 25 insertions(+), 20 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
20
return true;
21
}
22
23
+static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn,
24
+ arg_rpr_esz *a, int data)
25
+{
26
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data);
27
+}
28
+
29
+
30
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
31
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
32
int rd, int rn, int rm, int pg, int data)
33
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
34
*** SVE Integer Arithmetic - Unary Predicated Group
35
*/
36
37
-static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
38
-{
39
- return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
40
-}
41
-
42
#define DO_ZPZ(NAME, name) \
43
static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
44
{ \
45
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
46
gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
47
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
48
}; \
49
- return do_zpz_ool(s, a, fns[a->esz]); \
50
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0); \
51
}
52
53
DO_ZPZ(CLS, cls)
54
@@ -XXX,XX +XXX,XX @@ static bool trans_FABS(DisasContext *s, arg_rpr_esz *a)
55
gen_helper_sve_fabs_s,
56
gen_helper_sve_fabs_d
57
};
58
- return do_zpz_ool(s, a, fns[a->esz]);
59
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
60
}
61
62
static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
63
@@ -XXX,XX +XXX,XX @@ static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
64
gen_helper_sve_fneg_s,
65
gen_helper_sve_fneg_d
66
};
67
- return do_zpz_ool(s, a, fns[a->esz]);
68
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
69
}
70
71
static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
72
@@ -XXX,XX +XXX,XX @@ static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
73
gen_helper_sve_sxtb_s,
74
gen_helper_sve_sxtb_d
75
};
76
- return do_zpz_ool(s, a, fns[a->esz]);
77
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
78
}
79
80
static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
81
@@ -XXX,XX +XXX,XX @@ static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
82
gen_helper_sve_uxtb_s,
83
gen_helper_sve_uxtb_d
84
};
85
- return do_zpz_ool(s, a, fns[a->esz]);
86
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
87
}
88
89
static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
90
@@ -XXX,XX +XXX,XX @@ static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
91
gen_helper_sve_sxth_s,
92
gen_helper_sve_sxth_d
93
};
94
- return do_zpz_ool(s, a, fns[a->esz]);
95
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
96
}
97
98
static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
99
@@ -XXX,XX +XXX,XX @@ static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
100
gen_helper_sve_uxth_s,
101
gen_helper_sve_uxth_d
102
};
103
- return do_zpz_ool(s, a, fns[a->esz]);
104
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
105
}
106
107
static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a)
108
{
109
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_sxtw_d : NULL);
110
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_sxtw_d
111
+ : NULL, a, 0);
112
}
113
114
static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a)
115
{
116
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_uxtw_d : NULL);
117
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_uxtw_d
118
+ : NULL, a, 0);
119
}
120
121
#undef DO_ZPZ
122
@@ -XXX,XX +XXX,XX @@ static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a)
123
static gen_helper_gvec_3 * const fns[4] = {
124
NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
125
};
126
- return do_zpz_ool(s, a, fns[a->esz]);
127
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
128
}
129
130
/* Call the helper that computes the ARM LastActiveElement pseudocode
131
@@ -XXX,XX +XXX,XX @@ static bool trans_REVB(DisasContext *s, arg_rpr_esz *a)
132
gen_helper_sve_revb_s,
133
gen_helper_sve_revb_d,
134
};
135
- return do_zpz_ool(s, a, fns[a->esz]);
136
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
137
}
138
139
static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
140
@@ -XXX,XX +XXX,XX @@ static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
141
gen_helper_sve_revh_s,
142
gen_helper_sve_revh_d,
143
};
144
- return do_zpz_ool(s, a, fns[a->esz]);
145
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
146
}
147
148
static bool trans_REVW(DisasContext *s, arg_rpr_esz *a)
149
{
150
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_revw_d : NULL);
151
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_revw_d
152
+ : NULL, a, 0);
153
}
154
155
static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
156
@@ -XXX,XX +XXX,XX @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
157
gen_helper_sve_rbit_s,
158
gen_helper_sve_rbit_d,
159
};
160
- return do_zpz_ool(s, a, fns[a->esz]);
161
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
162
}
163
164
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
165
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zpz_ool(DisasContext *s, arg_rpr_esz *a,
166
if (!dc_isar_feature(aa64_sve2, s)) {
167
return false;
168
}
169
- return do_zpz_ool(s, a, fn);
170
+ return gen_gvec_ool_arg_zpz(s, fn, a, 0);
171
}
172
173
static bool trans_URECPE(DisasContext *s, arg_rpr_esz *a)
174
--
175
2.25.1
diff view generated by jsdifflib
[PULL 024/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zpz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-22-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 189 ++++++++++++-------------------------
12
1 file changed, 60 insertions(+), 129 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
19
*** SVE Integer Arithmetic - Unary Predicated Group
20
*/
21
22
-#define DO_ZPZ(NAME, name) \
23
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
24
-{ \
25
- static gen_helper_gvec_3 * const fns[4] = { \
26
- gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
27
- gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
28
+#define DO_ZPZ(NAME, FEAT, name) \
29
+ static gen_helper_gvec_3 * const name##_fns[4] = { \
30
+ gen_helper_##name##_b, gen_helper_##name##_h, \
31
+ gen_helper_##name##_s, gen_helper_##name##_d, \
32
}; \
33
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0); \
34
-}
35
+ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0)
36
37
-DO_ZPZ(CLS, cls)
38
-DO_ZPZ(CLZ, clz)
39
-DO_ZPZ(CNT_zpz, cnt_zpz)
40
-DO_ZPZ(CNOT, cnot)
41
-DO_ZPZ(NOT_zpz, not_zpz)
42
-DO_ZPZ(ABS, abs)
43
-DO_ZPZ(NEG, neg)
44
+DO_ZPZ(CLS, aa64_sve, sve_cls)
45
+DO_ZPZ(CLZ, aa64_sve, sve_clz)
46
+DO_ZPZ(CNT_zpz, aa64_sve, sve_cnt_zpz)
47
+DO_ZPZ(CNOT, aa64_sve, sve_cnot)
48
+DO_ZPZ(NOT_zpz, aa64_sve, sve_not_zpz)
49
+DO_ZPZ(ABS, aa64_sve, sve_abs)
50
+DO_ZPZ(NEG, aa64_sve, sve_neg)
51
+DO_ZPZ(RBIT, aa64_sve, sve_rbit)
52
53
-static bool trans_FABS(DisasContext *s, arg_rpr_esz *a)
54
-{
55
- static gen_helper_gvec_3 * const fns[4] = {
56
- NULL,
57
- gen_helper_sve_fabs_h,
58
- gen_helper_sve_fabs_s,
59
- gen_helper_sve_fabs_d
60
- };
61
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
62
-}
63
+static gen_helper_gvec_3 * const fabs_fns[4] = {
64
+ NULL, gen_helper_sve_fabs_h,
65
+ gen_helper_sve_fabs_s, gen_helper_sve_fabs_d,
66
+};
67
+TRANS_FEAT(FABS, aa64_sve, gen_gvec_ool_arg_zpz, fabs_fns[a->esz], a, 0)
68
69
-static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
70
-{
71
- static gen_helper_gvec_3 * const fns[4] = {
72
- NULL,
73
- gen_helper_sve_fneg_h,
74
- gen_helper_sve_fneg_s,
75
- gen_helper_sve_fneg_d
76
- };
77
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
78
-}
79
+static gen_helper_gvec_3 * const fneg_fns[4] = {
80
+ NULL, gen_helper_sve_fneg_h,
81
+ gen_helper_sve_fneg_s, gen_helper_sve_fneg_d,
82
+};
83
+TRANS_FEAT(FNEG, aa64_sve, gen_gvec_ool_arg_zpz, fneg_fns[a->esz], a, 0)
84
85
-static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
86
-{
87
- static gen_helper_gvec_3 * const fns[4] = {
88
- NULL,
89
- gen_helper_sve_sxtb_h,
90
- gen_helper_sve_sxtb_s,
91
- gen_helper_sve_sxtb_d
92
- };
93
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
94
-}
95
+static gen_helper_gvec_3 * const sxtb_fns[4] = {
96
+ NULL, gen_helper_sve_sxtb_h,
97
+ gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d,
98
+};
99
+TRANS_FEAT(SXTB, aa64_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0)
100
101
-static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
102
-{
103
- static gen_helper_gvec_3 * const fns[4] = {
104
- NULL,
105
- gen_helper_sve_uxtb_h,
106
- gen_helper_sve_uxtb_s,
107
- gen_helper_sve_uxtb_d
108
- };
109
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
110
-}
111
+static gen_helper_gvec_3 * const uxtb_fns[4] = {
112
+ NULL, gen_helper_sve_uxtb_h,
113
+ gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d,
114
+};
115
+TRANS_FEAT(UXTB, aa64_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0)
116
117
-static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
118
-{
119
- static gen_helper_gvec_3 * const fns[4] = {
120
- NULL, NULL,
121
- gen_helper_sve_sxth_s,
122
- gen_helper_sve_sxth_d
123
- };
124
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
125
-}
126
+static gen_helper_gvec_3 * const sxth_fns[4] = {
127
+ NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d
128
+};
129
+TRANS_FEAT(SXTH, aa64_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0)
130
131
-static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
132
-{
133
- static gen_helper_gvec_3 * const fns[4] = {
134
- NULL, NULL,
135
- gen_helper_sve_uxth_s,
136
- gen_helper_sve_uxth_d
137
- };
138
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
139
-}
140
+static gen_helper_gvec_3 * const uxth_fns[4] = {
141
+ NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d
142
+};
143
+TRANS_FEAT(UXTH, aa64_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0)
144
145
-static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a)
146
-{
147
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_sxtw_d
148
- : NULL, a, 0);
149
-}
150
-
151
-static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a)
152
-{
153
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_uxtw_d
154
- : NULL, a, 0);
155
-}
156
-
157
-#undef DO_ZPZ
158
+TRANS_FEAT(SXTW, aa64_sve, gen_gvec_ool_arg_zpz,
159
+ a->esz == 3 ? gen_helper_sve_sxtw_d : NULL, a, 0)
160
+TRANS_FEAT(UXTW, aa64_sve, gen_gvec_ool_arg_zpz,
161
+ a->esz == 3 ? gen_helper_sve_uxtw_d : NULL, a, 0)
162
163
/*
164
*** SVE Integer Reduction Group
165
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
166
*** SVE Permute Vector - Predicated Group
167
*/
168
169
-static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a)
170
-{
171
- static gen_helper_gvec_3 * const fns[4] = {
172
- NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
173
- };
174
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
175
-}
176
+static gen_helper_gvec_3 * const compact_fns[4] = {
177
+ NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
178
+};
179
+TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0)
180
181
/* Call the helper that computes the ARM LastActiveElement pseudocode
182
* function, scaled by the element size. This includes the not found
183
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a)
184
return true;
185
}
186
187
-static bool trans_REVB(DisasContext *s, arg_rpr_esz *a)
188
-{
189
- static gen_helper_gvec_3 * const fns[4] = {
190
- NULL,
191
- gen_helper_sve_revb_h,
192
- gen_helper_sve_revb_s,
193
- gen_helper_sve_revb_d,
194
- };
195
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
196
-}
197
+static gen_helper_gvec_3 * const revb_fns[4] = {
198
+ NULL, gen_helper_sve_revb_h,
199
+ gen_helper_sve_revb_s, gen_helper_sve_revb_d,
200
+};
201
+TRANS_FEAT(REVB, aa64_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0)
202
203
-static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
204
-{
205
- static gen_helper_gvec_3 * const fns[4] = {
206
- NULL,
207
- NULL,
208
- gen_helper_sve_revh_s,
209
- gen_helper_sve_revh_d,
210
- };
211
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
212
-}
213
+static gen_helper_gvec_3 * const revh_fns[4] = {
214
+ NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d,
215
+};
216
+TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
217
218
-static bool trans_REVW(DisasContext *s, arg_rpr_esz *a)
219
-{
220
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_revw_d
221
- : NULL, a, 0);
222
-}
223
-
224
-static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
225
-{
226
- static gen_helper_gvec_3 * const fns[4] = {
227
- gen_helper_sve_rbit_b,
228
- gen_helper_sve_rbit_h,
229
- gen_helper_sve_rbit_s,
230
- gen_helper_sve_rbit_d,
231
- };
232
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
233
-}
234
+TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
235
+ a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
236
237
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
238
{
239
--
240
2.25.1
diff view generated by jsdifflib
[PULL 025/117] target/arm: Use TRANS_FEAT for do_sve2_zpz_data
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions using do_sve2_zpz_data
4
to use TRANS_FEAT and gen_gvec_ool_arg_zpz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-23-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 53 ++++++++++----------------------------
12
1 file changed, 14 insertions(+), 39 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_UADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
19
* SVE2 integer unary operations (predicated)
20
*/
21
22
-static bool do_sve2_zpz_ool(DisasContext *s, arg_rpr_esz *a,
23
- gen_helper_gvec_3 *fn)
24
-{
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zpz(s, fn, a, 0);
29
-}
30
+TRANS_FEAT(URECPE, aa64_sve2, gen_gvec_ool_arg_zpz,
31
+ a->esz == 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0)
32
33
-static bool trans_URECPE(DisasContext *s, arg_rpr_esz *a)
34
-{
35
- if (a->esz != 2) {
36
- return false;
37
- }
38
- return do_sve2_zpz_ool(s, a, gen_helper_sve2_urecpe_s);
39
-}
40
+TRANS_FEAT(URSQRTE, aa64_sve2, gen_gvec_ool_arg_zpz,
41
+ a->esz == 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0)
42
43
-static bool trans_URSQRTE(DisasContext *s, arg_rpr_esz *a)
44
-{
45
- if (a->esz != 2) {
46
- return false;
47
- }
48
- return do_sve2_zpz_ool(s, a, gen_helper_sve2_ursqrte_s);
49
-}
50
+static gen_helper_gvec_3 * const sqabs_fns[4] = {
51
+ gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h,
52
+ gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d,
53
+};
54
+TRANS_FEAT(SQABS, aa64_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0)
55
56
-static bool trans_SQABS(DisasContext *s, arg_rpr_esz *a)
57
-{
58
- static gen_helper_gvec_3 * const fns[4] = {
59
- gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h,
60
- gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d,
61
- };
62
- return do_sve2_zpz_ool(s, a, fns[a->esz]);
63
-}
64
-
65
-static bool trans_SQNEG(DisasContext *s, arg_rpr_esz *a)
66
-{
67
- static gen_helper_gvec_3 * const fns[4] = {
68
- gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h,
69
- gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d,
70
- };
71
- return do_sve2_zpz_ool(s, a, fns[a->esz]);
72
-}
73
+static gen_helper_gvec_3 * const sqneg_fns[4] = {
74
+ gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h,
75
+ gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d,
76
+};
77
+TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0)
78
79
#define DO_SVE2_ZPZZ(NAME, name) \
80
static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
81
--
82
2.25.1
diff view generated by jsdifflib
[PULL 028/117] target/arm: Move null function and sve check into gen_gvec_ool_zzzp
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-26-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 42 ++++++++++++++++----------------------
9
1 file changed, 18 insertions(+), 24 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
19
-static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
20
+static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
21
int rd, int rn, int rm, int pg, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- pred_full_reg_offset(s, pg),
28
- vsz, vsz, data, fn);
29
+ if (fn == NULL) {
30
+ return false;
31
+ }
32
+ if (sve_access_check(s)) {
33
+ unsigned vsz = vec_full_reg_size(s);
34
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
35
+ vec_full_reg_offset(s, rn),
36
+ vec_full_reg_offset(s, rm),
37
+ pred_full_reg_offset(s, pg),
38
+ vsz, vsz, data, fn);
39
+ }
40
+ return true;
41
}
42
43
/* Invoke a vector expander on two Zregs. */
44
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
45
46
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
47
{
48
- if (fn == NULL) {
49
- return false;
50
- }
51
- if (sve_access_check(s)) {
52
- gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
53
- }
54
- return true;
55
+ return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
56
}
57
58
/* Select active elememnts from Zn and inactive elements from Zm,
59
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
60
61
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
62
{
63
- if (sve_access_check(s)) {
64
- gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
65
- a->rd, a->rn, a->rm, a->pg, a->esz);
66
- }
67
- return true;
68
+ return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
69
+ a->rd, a->rn, a->rm, a->pg, a->esz);
70
}
71
72
static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
73
@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
74
if (!dc_isar_feature(aa64_sve2, s)) {
75
return false;
76
}
77
- if (sve_access_check(s)) {
78
- gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
79
- a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
80
- }
81
- return true;
82
+ return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
83
+ a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
84
}
85
86
/*
87
--
88
2.25.1
diff view generated by jsdifflib
[PULL 030/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zpzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-28-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 85 ++++++++++++++++----------------------
12
1 file changed, 36 insertions(+), 49 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
19
gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
20
}
21
22
-#define DO_ZPZZ(NAME, name) \
23
-static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a) \
24
-{ \
25
- static gen_helper_gvec_4 * const fns[4] = { \
26
- gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \
27
- gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \
28
+#define DO_ZPZZ(NAME, FEAT, name) \
29
+ static gen_helper_gvec_4 * const name##_zpzz_fns[4] = { \
30
+ gen_helper_##name##_zpzz_b, gen_helper_##name##_zpzz_h, \
31
+ gen_helper_##name##_zpzz_s, gen_helper_##name##_zpzz_d, \
32
}; \
33
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
34
-}
35
+ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpzz, \
36
+ name##_zpzz_fns[a->esz], a, 0)
37
38
-DO_ZPZZ(AND, and)
39
-DO_ZPZZ(EOR, eor)
40
-DO_ZPZZ(ORR, orr)
41
-DO_ZPZZ(BIC, bic)
42
+DO_ZPZZ(AND_zpzz, aa64_sve, sve_and)
43
+DO_ZPZZ(EOR_zpzz, aa64_sve, sve_eor)
44
+DO_ZPZZ(ORR_zpzz, aa64_sve, sve_orr)
45
+DO_ZPZZ(BIC_zpzz, aa64_sve, sve_bic)
46
47
-DO_ZPZZ(ADD, add)
48
-DO_ZPZZ(SUB, sub)
49
+DO_ZPZZ(ADD_zpzz, aa64_sve, sve_add)
50
+DO_ZPZZ(SUB_zpzz, aa64_sve, sve_sub)
51
52
-DO_ZPZZ(SMAX, smax)
53
-DO_ZPZZ(UMAX, umax)
54
-DO_ZPZZ(SMIN, smin)
55
-DO_ZPZZ(UMIN, umin)
56
-DO_ZPZZ(SABD, sabd)
57
-DO_ZPZZ(UABD, uabd)
58
+DO_ZPZZ(SMAX_zpzz, aa64_sve, sve_smax)
59
+DO_ZPZZ(UMAX_zpzz, aa64_sve, sve_umax)
60
+DO_ZPZZ(SMIN_zpzz, aa64_sve, sve_smin)
61
+DO_ZPZZ(UMIN_zpzz, aa64_sve, sve_umin)
62
+DO_ZPZZ(SABD_zpzz, aa64_sve, sve_sabd)
63
+DO_ZPZZ(UABD_zpzz, aa64_sve, sve_uabd)
64
65
-DO_ZPZZ(MUL, mul)
66
-DO_ZPZZ(SMULH, smulh)
67
-DO_ZPZZ(UMULH, umulh)
68
+DO_ZPZZ(MUL_zpzz, aa64_sve, sve_mul)
69
+DO_ZPZZ(SMULH_zpzz, aa64_sve, sve_smulh)
70
+DO_ZPZZ(UMULH_zpzz, aa64_sve, sve_umulh)
71
72
-DO_ZPZZ(ASR, asr)
73
-DO_ZPZZ(LSR, lsr)
74
-DO_ZPZZ(LSL, lsl)
75
+DO_ZPZZ(ASR_zpzz, aa64_sve, sve_asr)
76
+DO_ZPZZ(LSR_zpzz, aa64_sve, sve_lsr)
77
+DO_ZPZZ(LSL_zpzz, aa64_sve, sve_lsl)
78
79
-static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
80
-{
81
- static gen_helper_gvec_4 * const fns[4] = {
82
- NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
83
- };
84
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
85
-}
86
+static gen_helper_gvec_4 * const sdiv_fns[4] = {
87
+ NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
88
+};
89
+TRANS_FEAT(SDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->esz], a, 0)
90
91
-static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
92
-{
93
- static gen_helper_gvec_4 * const fns[4] = {
94
- NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
95
- };
96
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
97
-}
98
+static gen_helper_gvec_4 * const udiv_fns[4] = {
99
+ NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
100
+};
101
+TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
102
103
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
104
{
105
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi,
106
*/
107
108
#define DO_ZPZW(NAME, name) \
109
-static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a) \
110
-{ \
111
- static gen_helper_gvec_4 * const fns[3] = { \
112
+ static gen_helper_gvec_4 * const name##_zpzw_fns[4] = { \
113
gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \
114
- gen_helper_sve_##name##_zpzw_s, \
115
+ gen_helper_sve_##name##_zpzw_s, NULL \
116
}; \
117
- if (a->esz < 0 || a->esz >= 3) { \
118
- return false; \
119
- } \
120
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
121
-}
122
+ TRANS_FEAT(NAME##_zpzw, aa64_sve, gen_gvec_ool_arg_zpzz, \
123
+ a->esz < 0 ? NULL : name##_zpzw_fns[a->esz], a, 0)
124
125
DO_ZPZW(ASR, asr)
126
DO_ZPZW(LSR, lsr)
127
--
128
2.25.1
diff view generated by jsdifflib
[PULL 031/117] target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions using do_sve2_zpzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zpzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-29-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 118 +++++++++++++------------------------
12
1 file changed, 40 insertions(+), 78 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
19
return true;
20
}
21
22
-#undef DO_ZPZZ
23
-
24
/*
25
*** SVE Integer Arithmetic - Unary Predicated Group
26
*/
27
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
28
* SVE2 Integer - Predicated
29
*/
30
31
-static bool do_sve2_zpzz_ool(DisasContext *s, arg_rprr_esz *a,
32
- gen_helper_gvec_4 *fn)
33
-{
34
- if (!dc_isar_feature(aa64_sve2, s)) {
35
- return false;
36
- }
37
- return gen_gvec_ool_arg_zpzz(s, fn, a, 0);
38
-}
39
+static gen_helper_gvec_4 * const sadlp_fns[4] = {
40
+ NULL, gen_helper_sve2_sadalp_zpzz_h,
41
+ gen_helper_sve2_sadalp_zpzz_s, gen_helper_sve2_sadalp_zpzz_d,
42
+};
43
+TRANS_FEAT(SADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz,
44
+ sadlp_fns[a->esz], a, 0)
45
46
-static bool trans_SADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
47
-{
48
- static gen_helper_gvec_4 * const fns[3] = {
49
- gen_helper_sve2_sadalp_zpzz_h,
50
- gen_helper_sve2_sadalp_zpzz_s,
51
- gen_helper_sve2_sadalp_zpzz_d,
52
- };
53
- if (a->esz == 0) {
54
- return false;
55
- }
56
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
57
-}
58
-
59
-static bool trans_UADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
60
-{
61
- static gen_helper_gvec_4 * const fns[3] = {
62
- gen_helper_sve2_uadalp_zpzz_h,
63
- gen_helper_sve2_uadalp_zpzz_s,
64
- gen_helper_sve2_uadalp_zpzz_d,
65
- };
66
- if (a->esz == 0) {
67
- return false;
68
- }
69
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
70
-}
71
+static gen_helper_gvec_4 * const uadlp_fns[4] = {
72
+ NULL, gen_helper_sve2_uadalp_zpzz_h,
73
+ gen_helper_sve2_uadalp_zpzz_s, gen_helper_sve2_uadalp_zpzz_d,
74
+};
75
+TRANS_FEAT(UADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz,
76
+ uadlp_fns[a->esz], a, 0)
77
78
/*
79
* SVE2 integer unary operations (predicated)
80
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const sqneg_fns[4] = {
81
};
82
TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0)
83
84
-#define DO_SVE2_ZPZZ(NAME, name) \
85
-static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
86
-{ \
87
- static gen_helper_gvec_4 * const fns[4] = { \
88
- gen_helper_sve2_##name##_zpzz_b, gen_helper_sve2_##name##_zpzz_h, \
89
- gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d, \
90
- }; \
91
- return do_sve2_zpzz_ool(s, a, fns[a->esz]); \
92
-}
93
+DO_ZPZZ(SQSHL, aa64_sve2, sve2_sqshl)
94
+DO_ZPZZ(SQRSHL, aa64_sve2, sve2_sqrshl)
95
+DO_ZPZZ(SRSHL, aa64_sve2, sve2_srshl)
96
97
-DO_SVE2_ZPZZ(SQSHL, sqshl)
98
-DO_SVE2_ZPZZ(SQRSHL, sqrshl)
99
-DO_SVE2_ZPZZ(SRSHL, srshl)
100
+DO_ZPZZ(UQSHL, aa64_sve2, sve2_uqshl)
101
+DO_ZPZZ(UQRSHL, aa64_sve2, sve2_uqrshl)
102
+DO_ZPZZ(URSHL, aa64_sve2, sve2_urshl)
103
104
-DO_SVE2_ZPZZ(UQSHL, uqshl)
105
-DO_SVE2_ZPZZ(UQRSHL, uqrshl)
106
-DO_SVE2_ZPZZ(URSHL, urshl)
107
+DO_ZPZZ(SHADD, aa64_sve2, sve2_shadd)
108
+DO_ZPZZ(SRHADD, aa64_sve2, sve2_srhadd)
109
+DO_ZPZZ(SHSUB, aa64_sve2, sve2_shsub)
110
111
-DO_SVE2_ZPZZ(SHADD, shadd)
112
-DO_SVE2_ZPZZ(SRHADD, srhadd)
113
-DO_SVE2_ZPZZ(SHSUB, shsub)
114
+DO_ZPZZ(UHADD, aa64_sve2, sve2_uhadd)
115
+DO_ZPZZ(URHADD, aa64_sve2, sve2_urhadd)
116
+DO_ZPZZ(UHSUB, aa64_sve2, sve2_uhsub)
117
118
-DO_SVE2_ZPZZ(UHADD, uhadd)
119
-DO_SVE2_ZPZZ(URHADD, urhadd)
120
-DO_SVE2_ZPZZ(UHSUB, uhsub)
121
+DO_ZPZZ(ADDP, aa64_sve2, sve2_addp)
122
+DO_ZPZZ(SMAXP, aa64_sve2, sve2_smaxp)
123
+DO_ZPZZ(UMAXP, aa64_sve2, sve2_umaxp)
124
+DO_ZPZZ(SMINP, aa64_sve2, sve2_sminp)
125
+DO_ZPZZ(UMINP, aa64_sve2, sve2_uminp)
126
127
-DO_SVE2_ZPZZ(ADDP, addp)
128
-DO_SVE2_ZPZZ(SMAXP, smaxp)
129
-DO_SVE2_ZPZZ(UMAXP, umaxp)
130
-DO_SVE2_ZPZZ(SMINP, sminp)
131
-DO_SVE2_ZPZZ(UMINP, uminp)
132
-
133
-DO_SVE2_ZPZZ(SQADD_zpzz, sqadd)
134
-DO_SVE2_ZPZZ(UQADD_zpzz, uqadd)
135
-DO_SVE2_ZPZZ(SQSUB_zpzz, sqsub)
136
-DO_SVE2_ZPZZ(UQSUB_zpzz, uqsub)
137
-DO_SVE2_ZPZZ(SUQADD, suqadd)
138
-DO_SVE2_ZPZZ(USQADD, usqadd)
139
+DO_ZPZZ(SQADD_zpzz, aa64_sve2, sve2_sqadd)
140
+DO_ZPZZ(UQADD_zpzz, aa64_sve2, sve2_uqadd)
141
+DO_ZPZZ(SQSUB_zpzz, aa64_sve2, sve2_sqsub)
142
+DO_ZPZZ(UQSUB_zpzz, aa64_sve2, sve2_uqsub)
143
+DO_ZPZZ(SUQADD, aa64_sve2, sve2_suqadd)
144
+DO_ZPZZ(USQADD, aa64_sve2, sve2_usqadd)
145
146
/*
147
* SVE2 Widening Integer Arithmetic
148
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
149
DO_SVE2_PPZZ_MATCH(MATCH, match)
150
DO_SVE2_PPZZ_MATCH(NMATCH, nmatch)
151
152
-static bool trans_HISTCNT(DisasContext *s, arg_rprr_esz *a)
153
-{
154
- static gen_helper_gvec_4 * const fns[2] = {
155
- gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
156
- };
157
- if (a->esz < 2) {
158
- return false;
159
- }
160
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 2]);
161
-}
162
+static gen_helper_gvec_4 * const histcnt_fns[4] = {
163
+ NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
164
+};
165
+TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
166
+ histcnt_fns[a->esz], a, 0)
167
168
TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
169
a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
170
--
171
2.25.1
diff view generated by jsdifflib
[PULL 033/117] target/arm: Move null function and sve check into gen_gvec_fn_zzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-31-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 36 +++++++++++++++---------------------
9
1 file changed, 15 insertions(+), 21 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
16
}
17
18
/* Invoke a vector expander on three Zregs. */
19
-static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
20
+static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
21
int esz, int rd, int rn, int rm)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- gvec_fn(esz, vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm), vsz, vsz);
27
+ if (gvec_fn == NULL) {
28
+ return false;
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
33
+ vec_full_reg_offset(s, rn),
34
+ vec_full_reg_offset(s, rm), vsz, vsz);
35
+ }
36
+ return true;
37
}
38
39
/* Invoke a vector expander on four Zregs. */
40
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
41
42
static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
43
{
44
- if (sve_access_check(s)) {
45
- gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
46
- }
47
- return true;
48
+ return gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
49
}
50
51
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
52
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
53
if (!dc_isar_feature(aa64_sve2, s)) {
54
return false;
55
}
56
- if (sve_access_check(s)) {
57
- gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
58
- }
59
- return true;
60
+ return gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
61
}
62
63
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
64
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
65
if (!dc_isar_feature(aa64_sve2, s)) {
66
return false;
67
}
68
- if (sve_access_check(s)) {
69
- gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
70
- }
71
- return true;
72
+ return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
73
}
74
75
static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
76
@@ -XXX,XX +XXX,XX @@ static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
77
if (!dc_isar_feature(aa64_sve2_sha3, s)) {
78
return false;
79
}
80
- if (sve_access_check(s)) {
81
- gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
82
- }
83
- return true;
84
+ return gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
85
}
86
87
static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
88
--
89
2.25.1
diff view generated by jsdifflib
[PULL 036/117] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Convert SVE translation functions directly using
4
gen_gvec_fn_arg_zzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-34-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 66 +++++++-------------------------------
12
1 file changed, 11 insertions(+), 55 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
19
*** SVE Logical - Unpredicated Group
20
*/
21
22
-static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
23
-{
24
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_and, a);
25
-}
26
-
27
-static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
28
-{
29
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_or, a);
30
-}
31
-
32
-static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
33
-{
34
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_xor, a);
35
-}
36
-
37
-static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
38
-{
39
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_andc, a);
40
-}
41
+TRANS_FEAT(AND_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and, a)
42
+TRANS_FEAT(ORR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or, a)
43
+TRANS_FEAT(EOR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor, a)
44
+TRANS_FEAT(BIC_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_andc, a)
45
46
static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh)
47
{
48
@@ -XXX,XX +XXX,XX @@ static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
49
*** SVE Integer Arithmetic - Unpredicated Group
50
*/
51
52
-static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
53
-{
54
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_add, a);
55
-}
56
-
57
-static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
58
-{
59
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sub, a);
60
-}
61
-
62
-static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
63
-{
64
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ssadd, a);
65
-}
66
-
67
-static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
68
-{
69
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sssub, a);
70
-}
71
-
72
-static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
73
-{
74
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_usadd, a);
75
-}
76
-
77
-static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
78
-{
79
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ussub, a);
80
-}
81
+TRANS_FEAT(ADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add, a)
82
+TRANS_FEAT(SUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub, a)
83
+TRANS_FEAT(SQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ssadd, a)
84
+TRANS_FEAT(SQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sssub, a)
85
+TRANS_FEAT(UQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_usadd, a)
86
+TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a)
87
88
/*
89
*** SVE Integer Arithmetic - Binary Predicated Group
90
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
91
* SVE2 Integer Multiply - Unpredicated
92
*/
93
94
-static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
95
-{
96
- if (!dc_isar_feature(aa64_sve2, s)) {
97
- return false;
98
- }
99
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_mul, a);
100
-}
101
+TRANS_FEAT(MUL_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mul, a)
102
103
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
104
gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
105
--
106
2.25.1
diff view generated by jsdifflib
[PULL 038/117] target/arm: Use TRANS_FEAT for RAX1
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The decode for RAX1 sets esz to MO_8, because that's what
4
we use by default for "no esz present". We changed that
5
to MO_64 during translation because it is more logical for
6
the operation. However, the esz argument to gen_gvec_rax1
7
is unused and forces MO_64 within that function, so there
8
is no need to do it here as well.
9
10
Simplify to use gen_gvec_fn_arg_zzz and TRANS_FEAT.
11
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220527181907.189259-36-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/translate-sve.c | 8 +-------
18
1 file changed, 1 insertion(+), 7 deletions(-)
19
20
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/translate-sve.c
23
+++ b/target/arm/translate-sve.c
24
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
25
TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
26
gen_helper_crypto_sm4ekey, a, 0)
27
28
-static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
29
-{
30
- if (!dc_isar_feature(aa64_sve2_sha3, s)) {
31
- return false;
32
- }
33
- return gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
34
-}
35
+TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
36
37
static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
38
{
39
--
40
2.25.1
diff view generated by jsdifflib
[PULL 039/117] target/arm: Introduce gen_gvec_fn_arg_zzzz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Merge gen_gvec_fn_zzzz with the sve access check and the
4
dereference of arg_rrrr_esz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-37-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 25 ++++++++++++++-----------
12
1 file changed, 14 insertions(+), 11 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn,
19
}
20
21
/* Invoke a vector expander on four Zregs. */
22
-static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
23
- int esz, int rd, int rn, int rm, int ra)
24
+static bool gen_gvec_fn_arg_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
25
+ arg_rrrr_esz *a)
26
{
27
- unsigned vsz = vec_full_reg_size(s);
28
- gvec_fn(esz, vec_full_reg_offset(s, rd),
29
- vec_full_reg_offset(s, rn),
30
- vec_full_reg_offset(s, rm),
31
- vec_full_reg_offset(s, ra), vsz, vsz);
32
+ if (gvec_fn == NULL) {
33
+ return false;
34
+ }
35
+ if (sve_access_check(s)) {
36
+ unsigned vsz = vec_full_reg_size(s);
37
+ gvec_fn(a->esz, vec_full_reg_offset(s, a->rd),
38
+ vec_full_reg_offset(s, a->rn),
39
+ vec_full_reg_offset(s, a->rm),
40
+ vec_full_reg_offset(s, a->ra), vsz, vsz);
41
+ }
42
+ return true;
43
}
44
45
/* Invoke a vector move on two Zregs. */
46
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn)
47
if (!dc_isar_feature(aa64_sve2, s)) {
48
return false;
49
}
50
- if (sve_access_check(s)) {
51
- gen_gvec_fn_zzzz(s, fn, a->esz, a->rd, a->rn, a->rm, a->ra);
52
- }
53
- return true;
54
+ return gen_gvec_fn_arg_zzzz(s, fn, a);
55
}
56
57
static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
58
--
59
2.25.1
diff view generated by jsdifflib
[PULL 042/117] target/arm: Use TRANS_FEAT for do_zz_dbm
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-40-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
16
return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm);
17
}
18
19
-static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a)
20
-{
21
- return do_zz_dbm(s, a, tcg_gen_gvec_andi);
22
-}
23
-
24
-static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a)
25
-{
26
- return do_zz_dbm(s, a, tcg_gen_gvec_ori);
27
-}
28
-
29
-static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a)
30
-{
31
- return do_zz_dbm(s, a, tcg_gen_gvec_xori);
32
-}
33
+TRANS_FEAT(AND_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_andi)
34
+TRANS_FEAT(ORR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_ori)
35
+TRANS_FEAT(EOR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_xori)
36
37
static bool trans_DUPM(DisasContext *s, arg_DUPM *a)
38
{
39
--
40
2.25.1
diff view generated by jsdifflib
[PULL 047/117] target/arm: Use TRANS_FEAT for do_shift_imm
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
Message-id: 20220527181907.189259-45-richard.henderson@linaro.org
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/translate-sve.c | 17 +++--------------
11
MAINTAINERS | 2 ++
9
1 file changed, 3 insertions(+), 14 deletions(-)
12
1 file changed, 2 insertions(+)
10
13
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/MAINTAINERS b/MAINTAINERS
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
16
--- a/MAINTAINERS
14
+++ b/target/arm/translate-sve.c
17
+++ b/MAINTAINERS
15
@@ -XXX,XX +XXX,XX @@ static bool do_shift_imm(DisasContext *s, arg_rri_esz *a, bool asr,
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
16
return true;
19
17
}
20
Xilinx CAN
18
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
19
-static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a)
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
20
-{
23
S: Maintained
21
- return do_shift_imm(s, a, true, tcg_gen_gvec_sari);
24
F: hw/net/can/xlnx-*
22
-}
25
F: include/hw/net/xlnx-*
23
-
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
24
-static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a)
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CAN bus subsystem and hardware
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-{
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M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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- return do_shift_imm(s, a, false, tcg_gen_gvec_shri);
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M: Francisco Iglesias <francisco.iglesias@amd.com>
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-}
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+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
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-
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S: Maintained
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-static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
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W: https://canbus.pages.fel.cvut.cz/
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-{
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F: net/can/*
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- return do_shift_imm(s, a, false, tcg_gen_gvec_shli);
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-}
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+TRANS_FEAT(ASR_zzi, aa64_sve, do_shift_imm, a, true, tcg_gen_gvec_sari)
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+TRANS_FEAT(LSR_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shri)
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+TRANS_FEAT(LSL_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shli)
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#define DO_ZZW(NAME, name) \
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static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \
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--
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--
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2.25.1
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2.34.1
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Patchew 2.1-devel-b67e4c2

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