| 1 | The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d: | 1 | The following changes since commit ae35f033b874c627d81d51070187fbf55f0bf1a7: |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700) | 3 | Update version for v9.2.0 release (2024-12-10 16:20:54 +0000) |
| 4 | 4 | ||
| 5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
| 6 | 6 | ||
| 7 | https://github.com/legoater/qemu/ tags/pull-aspeed-20220525 | 7 | https://github.com/legoater/qemu/ tags/pull-aspeed-20241211 |
| 8 | 8 | ||
| 9 | for you to fetch changes up to 52bcd997800fab67d57bea6d93e368f6f7a93b24: | 9 | for you to fetch changes up to 124f4dc0d832c1bf3a4513c05a2b93bac0a5fac0: |
| 10 | 10 | ||
| 11 | hw/arm/aspeed: Add i2c devices for AST2600 EVB (2022-05-25 16:22:37 +0200) | 11 | test/qtest/ast2700-smc-test: Support to test AST2700 (2024-12-11 07:25:53 +0100) |
| 12 | 12 | ||
| 13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
| 14 | aspeed queue: | 14 | aspeed queue: |
| 15 | 15 | ||
| 16 | * Aspeed GPIO model extensions | 16 | * Removed tacoma-bmc machine |
| 17 | * GPIO support for the Aspeed AST1030 SoC | 17 | * Added support for SDHCI on AST2700 SoC |
| 18 | * New fby35 machine (AST2600 based) | 18 | * Improved functional tests |
| 19 | * Extra unit tests for the GPIO and SMC models | 19 | * Extended SMC qtest to all Aspeed SoCs |
| 20 | * Initialization of all UART with serial devices | ||
| 21 | * AST2600 EVB and Documentation update | ||
| 22 | 20 | ||
| 23 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
| 24 | Cédric Le Goater (1): | 22 | Cédric Le Goater (8): |
| 25 | aspeed: Introduce a get_irq AspeedSoCClass method | 23 | arm: Remove tacoma-bmc machine |
| 24 | tests/functional: Introduce a specific test for ast1030 SoC | ||
| 25 | tests/functional: Introduce a specific test for palmetto-bmc machine | ||
| 26 | tests/functional: Introduce a specific test for romulus-bmc machine | ||
| 27 | tests/functional: Introduce a specific test for ast2500 SoC | ||
| 28 | tests/functional: Introduce a specific test for ast2600 SoC | ||
| 29 | tests/functional: Introduce a specific test for rainier-bmc machine | ||
| 30 | tests/functional: Move debian boot test from avocado | ||
| 26 | 31 | ||
| 27 | Howard Chiu (1): | 32 | Jamin Lin (16): |
| 28 | hw/arm/aspeed: Add i2c devices for AST2600 EVB | 33 | hw/sd/aspeed_sdhci: Fix coding style |
| 34 | hw/arm/aspeed: Fix coding style | ||
| 35 | hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers | ||
| 36 | hw/sd/aspeed_sdhci: Add AST2700 Support | ||
| 37 | aspeed/soc: Support SDHCI for AST2700 | ||
| 38 | aspeed/soc: Support eMMC for AST2700 | ||
| 39 | test/qtest/aspeed_smc-test: Move testcases to test_palmetto_bmc function | ||
| 40 | test/qtest/aspeed_smc-test: Introduce a new TestData to test different BMC SOCs | ||
| 41 | test/qtest/aspeed_smc-test: Support to test all CE pins | ||
| 42 | test/qtest/aspeed_smc-test: Introducing a "page_addr" data field | ||
| 43 | test/qtest/aspeed_smc-test: Support to test AST2500 | ||
| 44 | test/qtest/aspeed_smc-test: Support to test AST2600 | ||
| 45 | test/qtest/aspeed_smc-test: Support to test AST1030 | ||
| 46 | test/qtest/aspeed_smc-test: Support write page command with QPI mode | ||
| 47 | test/qtest: Introduce a new aspeed-smc-utils.c to place common testcases | ||
| 48 | test/qtest/ast2700-smc-test: Support to test AST2700 | ||
| 29 | 49 | ||
| 30 | Iris Chen (1): | 50 | docs/about/deprecated.rst | 8 - |
| 31 | hw: m25p80: allow write_enable latch get/set | 51 | docs/about/removed-features.rst | 10 + |
| 52 | docs/system/arm/aspeed.rst | 1 - | ||
| 53 | include/hw/sd/aspeed_sdhci.h | 13 +- | ||
| 54 | tests/qtest/aspeed-smc-utils.h | 95 ++++ | ||
| 55 | hw/arm/aspeed.c | 28 - | ||
| 56 | hw/arm/aspeed_ast2400.c | 3 +- | ||
| 57 | hw/arm/aspeed_ast2600.c | 10 +- | ||
| 58 | hw/arm/aspeed_ast27x0.c | 35 ++ | ||
| 59 | hw/sd/aspeed_sdhci.c | 67 ++- | ||
| 60 | tests/qtest/aspeed-smc-utils.c | 686 ++++++++++++++++++++++++ | ||
| 61 | tests/qtest/aspeed_smc-test.c | 775 ++++++--------------------- | ||
| 62 | tests/qtest/ast2700-smc-test.c | 71 +++ | ||
| 63 | tests/avocado/boot_linux_console.py | 26 - | ||
| 64 | tests/functional/aspeed.py | 56 ++ | ||
| 65 | tests/functional/meson.build | 13 +- | ||
| 66 | tests/functional/test_arm_aspeed.py | 351 ------------ | ||
| 67 | tests/functional/test_arm_aspeed_ast1030.py | 81 +++ | ||
| 68 | tests/functional/test_arm_aspeed_ast2500.py | 59 ++ | ||
| 69 | tests/functional/test_arm_aspeed_ast2600.py | 143 +++++ | ||
| 70 | tests/functional/test_arm_aspeed_palmetto.py | 24 + | ||
| 71 | tests/functional/test_arm_aspeed_rainier.py | 64 +++ | ||
| 72 | tests/functional/test_arm_aspeed_romulus.py | 24 + | ||
| 73 | tests/qtest/meson.build | 5 +- | ||
| 74 | 24 files changed, 1623 insertions(+), 1025 deletions(-) | ||
| 75 | create mode 100644 tests/qtest/aspeed-smc-utils.h | ||
| 76 | create mode 100644 tests/qtest/aspeed-smc-utils.c | ||
| 77 | create mode 100644 tests/qtest/ast2700-smc-test.c | ||
| 78 | create mode 100644 tests/functional/aspeed.py | ||
| 79 | delete mode 100755 tests/functional/test_arm_aspeed.py | ||
| 80 | create mode 100644 tests/functional/test_arm_aspeed_ast1030.py | ||
| 81 | create mode 100644 tests/functional/test_arm_aspeed_ast2500.py | ||
| 82 | create mode 100644 tests/functional/test_arm_aspeed_ast2600.py | ||
| 83 | create mode 100644 tests/functional/test_arm_aspeed_palmetto.py | ||
| 84 | create mode 100644 tests/functional/test_arm_aspeed_rainier.py | ||
| 85 | create mode 100644 tests/functional/test_arm_aspeed_romulus.py | ||
| 32 | 86 | ||
| 33 | Jamin Lin (5): | ||
| 34 | docs: add minibmc section in aspeed document | ||
| 35 | hw/gpio Add GPIO read/write trace event. | ||
| 36 | hw/gpio: Add ASPEED GPIO model for AST1030 | ||
| 37 | hw/gpio support GPIO index mode for write operation. | ||
| 38 | hw/gpio: replace HWADDR_PRIx with PRIx64 | ||
| 39 | 87 | ||
| 40 | Peter Delevoryas (7): | ||
| 41 | hw/arm/aspeed: Add fby35 machine type | ||
| 42 | docs: aspeed: Add fby35 board | ||
| 43 | hw: aspeed: Add missing UART's | ||
| 44 | hw: aspeed: Add uarts_num SoC attribute | ||
| 45 | hw: aspeed: Ensure AST1030 respects uart-default | ||
| 46 | hw: aspeed: Introduce common UART init function | ||
| 47 | hw: aspeed: Init all UART's with serial devices | ||
| 48 | |||
| 49 | docs/system/arm/aspeed.rst | 62 ++++++++++ | ||
| 50 | include/hw/arm/aspeed_soc.h | 13 +++ | ||
| 51 | include/hw/gpio/aspeed_gpio.h | 16 ++- | ||
| 52 | tests/qtest/libqtest.h | 22 ++++ | ||
| 53 | hw/arm/aspeed.c | 74 +++++++++++- | ||
| 54 | hw/arm/aspeed_ast10x0.c | 48 ++++++-- | ||
| 55 | hw/arm/aspeed_ast2600.c | 32 +++-- | ||
| 56 | hw/arm/aspeed_soc.c | 46 ++++++-- | ||
| 57 | hw/block/m25p80.c | 1 + | ||
| 58 | hw/gpio/aspeed_gpio.c | 257 ++++++++++++++++++++++++++++++++++++++--- | ||
| 59 | tests/qtest/aspeed_gpio-test.c | 40 ++----- | ||
| 60 | tests/qtest/aspeed_smc-test.c | 43 +++++++ | ||
| 61 | tests/qtest/libqtest.c | 24 ++++ | ||
| 62 | hw/gpio/trace-events | 4 + | ||
| 63 | 14 files changed, 607 insertions(+), 75 deletions(-) | ||
| 64 | diff view generated by jsdifflib |
| 1 | From: Peter Delevoryas <pdel@fb.com> | 1 | Removal was scheduled for 10.0. Use the rainier-bmc machine or the |
|---|---|---|---|
| 2 | ast2600-evb as a replacement. | ||
| 2 | 3 | ||
| 3 | Add fby35 to the list of Aspeed boards. | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 5 | Link: https://lore.kernel.org/r/20241119071352.515790-1-clg@redhat.com | ||
| 6 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 7 | --- | ||
| 8 | docs/about/deprecated.rst | 8 -------- | ||
| 9 | docs/about/removed-features.rst | 10 ++++++++++ | ||
| 10 | docs/system/arm/aspeed.rst | 1 - | ||
| 11 | hw/arm/aspeed.c | 28 ---------------------------- | ||
| 12 | 4 files changed, 10 insertions(+), 37 deletions(-) | ||
| 4 | 13 | ||
| 5 | Signed-off-by: Peter Delevoryas <pdel@fb.com> | 14 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst |
| 6 | Message-Id: <20220506193354.990532-2-pdel@fb.com> | 15 | index XXXXXXX..XXXXXXX 100644 |
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 16 | --- a/docs/about/deprecated.rst |
| 8 | --- | 17 | +++ b/docs/about/deprecated.rst |
| 9 | docs/system/arm/aspeed.rst | 1 + | 18 | @@ -XXX,XX +XXX,XX @@ images are not available, OpenWRT dropped support in 2019, U-Boot in |
| 10 | 1 file changed, 1 insertion(+) | 19 | 2017, Linux also is dropping support in 2024. It is time to let go of |
| 11 | 20 | this ancient hardware and focus on newer CPUs and platforms. | |
| 21 | |||
| 22 | -Arm ``tacoma-bmc`` machine (since 9.1) | ||
| 23 | -'''''''''''''''''''''''''''''''''''''''' | ||
| 24 | - | ||
| 25 | -The ``tacoma-bmc`` machine was a board including an AST2600 SoC based | ||
| 26 | -BMC and a witherspoon like OpenPOWER system. It was used for bring up | ||
| 27 | -of the AST2600 SoC in labs. It can be easily replaced by the | ||
| 28 | -``rainier-bmc`` machine which is a real product. | ||
| 29 | - | ||
| 30 | Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2) | ||
| 31 | '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' | ||
| 32 | |||
| 33 | diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/docs/about/removed-features.rst | ||
| 36 | +++ b/docs/about/removed-features.rst | ||
| 37 | @@ -XXX,XX +XXX,XX @@ Aspeed ``swift-bmc`` machine (removed in 7.0) | ||
| 38 | This machine was removed because it was unused. Alternative AST2500 based | ||
| 39 | OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``. | ||
| 40 | |||
| 41 | +Aspeed ``tacoma-bmc`` machine (removed in 10.0) | ||
| 42 | +''''''''''''''''''''''''''''''''''''''''''''''' | ||
| 43 | + | ||
| 44 | +The ``tacoma-bmc`` machine was removed because it didn't bring much | ||
| 45 | +compared to the ``rainier-bmc`` machine. Also, the ``tacoma-bmc`` was | ||
| 46 | +a board used for bring up of the AST2600 SoC that never left the | ||
| 47 | +labs. It can be easily replaced by the ``rainier-bmc`` machine, which | ||
| 48 | +was the actual final product, or by the ``ast2600-evb`` with some | ||
| 49 | +tweaks. | ||
| 50 | + | ||
| 51 | ppc ``taihu`` machine (removed in 7.2) | ||
| 52 | ''''''''''''''''''''''''''''''''''''''''''''' | ||
| 53 | |||
| 12 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst | 54 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
| 13 | index XXXXXXX..XXXXXXX 100644 | 55 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/docs/system/arm/aspeed.rst | 56 | --- a/docs/system/arm/aspeed.rst |
| 15 | +++ b/docs/system/arm/aspeed.rst | 57 | +++ b/docs/system/arm/aspeed.rst |
| 16 | @@ -XXX,XX +XXX,XX @@ AST2600 SoC based machines : | 58 | @@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines : |
| 17 | - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC | 59 | AST2600 SoC based machines : |
| 60 | |||
| 61 | - ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) | ||
| 62 | -- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC | ||
| 18 | - ``rainier-bmc`` IBM Rainier POWER10 BMC | 63 | - ``rainier-bmc`` IBM Rainier POWER10 BMC |
| 19 | - ``fuji-bmc`` Facebook Fuji BMC | 64 | - ``fuji-bmc`` Facebook Fuji BMC |
| 20 | +- ``fby35-bmc`` Facebook fby35 BMC | 65 | - ``bletchley-bmc`` Facebook Bletchley BMC |
| 21 | 66 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | |
| 22 | Supported devices | 67 | index XXXXXXX..XXXXXXX 100644 |
| 23 | ----------------- | 68 | --- a/hw/arm/aspeed.c |
| 69 | +++ b/hw/arm/aspeed.c | ||
| 70 | @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState { | ||
| 71 | #define AST2700_EVB_HW_STRAP2 0x00000003 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | -/* Tacoma hardware value */ | ||
| 75 | -#define TACOMA_BMC_HW_STRAP1 0x00000000 | ||
| 76 | -#define TACOMA_BMC_HW_STRAP2 0x00000040 | ||
| 77 | - | ||
| 78 | /* Rainier hardware value: (QEMU prototype) */ | ||
| 79 | #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) | ||
| 80 | #define RAINIER_BMC_HW_STRAP2 0x80000848 | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) | ||
| 82 | aspeed_machine_ast2600_class_emmc_init(oc); | ||
| 83 | }; | ||
| 84 | |||
| 85 | -static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) | ||
| 86 | -{ | ||
| 87 | - MachineClass *mc = MACHINE_CLASS(oc); | ||
| 88 | - AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | ||
| 89 | - | ||
| 90 | - mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; | ||
| 91 | - amc->soc_name = "ast2600-a3"; | ||
| 92 | - amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; | ||
| 93 | - amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; | ||
| 94 | - amc->fmc_model = "mx66l1g45g"; | ||
| 95 | - amc->spi_model = "mx66l1g45g"; | ||
| 96 | - amc->num_cs = 2; | ||
| 97 | - amc->macs_mask = ASPEED_MAC2_ON; | ||
| 98 | - amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ | ||
| 99 | - mc->default_ram_size = 1 * GiB; | ||
| 100 | - aspeed_machine_class_init_cpus_defaults(mc); | ||
| 101 | - | ||
| 102 | - mc->deprecation_reason = "Please use the similar 'rainier-bmc' machine"; | ||
| 103 | -}; | ||
| 104 | - | ||
| 105 | static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) | ||
| 106 | { | ||
| 107 | MachineClass *mc = MACHINE_CLASS(oc); | ||
| 108 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { | ||
| 109 | .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), | ||
| 110 | .parent = TYPE_ASPEED_MACHINE, | ||
| 111 | .class_init = aspeed_machine_yosemitev2_class_init, | ||
| 112 | - }, { | ||
| 113 | - .name = MACHINE_TYPE_NAME("tacoma-bmc"), | ||
| 114 | - .parent = TYPE_ASPEED_MACHINE, | ||
| 115 | - .class_init = aspeed_machine_tacoma_class_init, | ||
| 116 | }, { | ||
| 117 | .name = MACHINE_TYPE_NAME("tiogapass-bmc"), | ||
| 118 | .parent = TYPE_ASPEED_MACHINE, | ||
| 24 | -- | 119 | -- |
| 25 | 2.35.3 | 120 | 2.47.1 |
| 26 | 121 | ||
| 27 | 122 | diff view generated by jsdifflib |
| 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | 1. replace HWADDR_PRIx with PRIx64 | 3 | Fix coding style issues from checkpatch.pl. |
| 4 | 2. fix indent issue | ||
| 5 | 4 | ||
| 6 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> | 5 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 6 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 8 | Message-Id: <20220525053444.27228-5-jamin_lin@aspeedtech.com> | 7 | Link: https://lore.kernel.org/r/20241204084453.610660-2-jamin_lin@aspeedtech.com |
| 9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 8 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 10 | --- | 9 | --- |
| 11 | include/hw/gpio/aspeed_gpio.h | 2 +- | 10 | hw/sd/aspeed_sdhci.c | 6 ++++-- |
| 12 | hw/gpio/aspeed_gpio.c | 8 ++++---- | 11 | 1 file changed, 4 insertions(+), 2 deletions(-) |
| 13 | 2 files changed, 5 insertions(+), 5 deletions(-) | ||
| 14 | 12 | ||
| 15 | diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h | 13 | diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/include/hw/gpio/aspeed_gpio.h | 15 | --- a/hw/sd/aspeed_sdhci.c |
| 18 | +++ b/include/hw/gpio/aspeed_gpio.h | 16 | +++ b/hw/sd/aspeed_sdhci.c |
| 19 | @@ -XXX,XX +XXX,XX @@ enum GPIORegIndexType { | 17 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val, |
| 20 | typedef struct AspeedGPIOReg { | 18 | sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET; |
| 21 | uint16_t set_idx; | ||
| 22 | enum GPIORegType type; | ||
| 23 | - } AspeedGPIOReg; | ||
| 24 | +} AspeedGPIOReg; | ||
| 25 | |||
| 26 | struct AspeedGPIOClass { | ||
| 27 | SysBusDevice parent_obj; | ||
| 28 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/gpio/aspeed_gpio.c | ||
| 31 | +++ b/hw/gpio/aspeed_gpio.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) | ||
| 33 | reg = &agc->reg_table[idx]; | ||
| 34 | if (reg->set_idx >= agc->nr_gpio_sets) { | ||
| 35 | qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" | ||
| 36 | - HWADDR_PRIx"\n", __func__, offset); | ||
| 37 | + PRIx64"\n", __func__, offset); | ||
| 38 | return 0; | ||
| 39 | } | ||
| 40 | |||
| 41 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) | ||
| 42 | break; | 19 | break; |
| 43 | default: | 20 | case ASPEED_SDHCI_SDIO_140: |
| 44 | qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" | 21 | - sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 0, 32, val); |
| 45 | - HWADDR_PRIx"\n", __func__, offset); | 22 | + sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, |
| 46 | + PRIx64"\n", __func__, offset); | 23 | + 0, 32, val); |
| 47 | return 0; | ||
| 48 | } | ||
| 49 | |||
| 50 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 51 | reg = &agc->reg_table[idx]; | ||
| 52 | if (reg->set_idx >= agc->nr_gpio_sets) { | ||
| 53 | qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" | ||
| 54 | - HWADDR_PRIx"\n", __func__, offset); | ||
| 55 | + PRIx64"\n", __func__, offset); | ||
| 56 | return; | ||
| 57 | } | ||
| 58 | |||
| 59 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 60 | break; | 24 | break; |
| 61 | default: | 25 | case ASPEED_SDHCI_SDIO_144: |
| 62 | qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" | 26 | - sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 32, 32, val); |
| 63 | - HWADDR_PRIx"\n", __func__, offset); | 27 | + sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, |
| 64 | + PRIx64"\n", __func__, offset); | 28 | + 32, 32, val); |
| 65 | return; | 29 | break; |
| 66 | } | 30 | case ASPEED_SDHCI_SDIO_148: |
| 67 | aspeed_gpio_update(s, set, set->data_value); | 31 | sdhci->slots[0].maxcurr = deposit64(sdhci->slots[0].maxcurr, |
| 68 | -- | 32 | -- |
| 69 | 2.35.3 | 33 | 2.47.1 |
| 70 | 34 | ||
| 71 | 35 | diff view generated by jsdifflib |
| 1 | From: Peter Delevoryas <pdel@fb.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13. | 3 | Fix coding style issues from checkpatch.pl. |
| 4 | 4 | ||
| 5 | Signed-off-by: Peter Delevoryas <pdel@fb.com> | 5 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 6 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 7 | Message-Id: <20220516062328.298336-3-pdel@fb.com> | 7 | Link: https://lore.kernel.org/r/20241204084453.610660-3-jamin_lin@aspeedtech.com |
| 8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 8 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 9 | --- | 9 | --- |
| 10 | include/hw/arm/aspeed_soc.h | 1 + | 10 | hw/arm/aspeed_ast2600.c | 3 ++- |
| 11 | hw/arm/aspeed_ast10x0.c | 1 + | 11 | 1 file changed, 2 insertions(+), 1 deletion(-) |
| 12 | hw/arm/aspeed_ast2600.c | 1 + | ||
| 13 | hw/arm/aspeed_soc.c | 2 ++ | ||
| 14 | 4 files changed, 5 insertions(+) | ||
| 15 | 12 | ||
| 16 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/include/hw/arm/aspeed_soc.h | ||
| 19 | +++ b/include/hw/arm/aspeed_soc.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass { | ||
| 21 | int ehcis_num; | ||
| 22 | int wdts_num; | ||
| 23 | int macs_num; | ||
| 24 | + int uarts_num; | ||
| 25 | const int *irqmap; | ||
| 26 | const hwaddr *memmap; | ||
| 27 | uint32_t num_cpus; | ||
| 28 | diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/arm/aspeed_ast10x0.c | ||
| 31 | +++ b/hw/arm/aspeed_ast10x0.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) | ||
| 33 | sc->ehcis_num = 0; | ||
| 34 | sc->wdts_num = 4; | ||
| 35 | sc->macs_num = 1; | ||
| 36 | + sc->uarts_num = 13; | ||
| 37 | sc->irqmap = aspeed_soc_ast1030_irqmap; | ||
| 38 | sc->memmap = aspeed_soc_ast1030_memmap; | ||
| 39 | sc->num_cpus = 1; | ||
| 40 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | 13 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c |
| 41 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 42 | --- a/hw/arm/aspeed_ast2600.c | 15 | --- a/hw/arm/aspeed_ast2600.c |
| 43 | +++ b/hw/arm/aspeed_ast2600.c | 16 | +++ b/hw/arm/aspeed_ast2600.c |
| 44 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | 17 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) |
| 45 | sc->ehcis_num = 2; | 18 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
| 46 | sc->wdts_num = 4; | 19 | return; |
| 47 | sc->macs_num = 4; | 20 | } |
| 48 | + sc->uarts_num = 13; | 21 | - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
| 49 | sc->irqmap = aspeed_soc_ast2600_irqmap; | 22 | + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, |
| 50 | sc->memmap = aspeed_soc_ast2600_memmap; | 23 | + sc->memmap[ASPEED_DEV_GPIO]); |
| 51 | sc->num_cpus = 2; | 24 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
| 52 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | 25 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
| 53 | index XXXXXXX..XXXXXXX 100644 | 26 | |
| 54 | --- a/hw/arm/aspeed_soc.c | ||
| 55 | +++ b/hw/arm/aspeed_soc.c | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
| 57 | sc->ehcis_num = 1; | ||
| 58 | sc->wdts_num = 2; | ||
| 59 | sc->macs_num = 2; | ||
| 60 | + sc->uarts_num = 5; | ||
| 61 | sc->irqmap = aspeed_soc_ast2400_irqmap; | ||
| 62 | sc->memmap = aspeed_soc_ast2400_memmap; | ||
| 63 | sc->num_cpus = 1; | ||
| 64 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
| 65 | sc->ehcis_num = 2; | ||
| 66 | sc->wdts_num = 3; | ||
| 67 | sc->macs_num = 2; | ||
| 68 | + sc->uarts_num = 5; | ||
| 69 | sc->irqmap = aspeed_soc_ast2500_irqmap; | ||
| 70 | sc->memmap = aspeed_soc_ast2500_memmap; | ||
| 71 | sc->num_cpus = 1; | ||
| 72 | -- | 27 | -- |
| 73 | 2.35.3 | 28 | 2.47.1 |
| 74 | 29 | ||
| 75 | 30 | diff view generated by jsdifflib |
| 1 | From: Peter Delevoryas <pdel@fb.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Signed-off-by: Peter Delevoryas <pdel@fb.com> | 3 | Currently, it set the hardcode value of capability registers to all ASPEED SOCs |
| 4 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 4 | However, the value of capability registers should be different for all ASPEED |
| 5 | Message-Id: <20220516062328.298336-5-pdel@fb.com> | 5 | SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for |
| 6 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | 64-bits System Bus support for AST2700. |
| 7 | |||
| 8 | Introduce a new "capareg" class member whose data type is uint_64 to set the | ||
| 9 | different Capability Registers to all ASPEED SOCs. | ||
| 10 | |||
| 11 | The value of Capability Register is "0x0000000001e80080" for AST2400 and | ||
| 12 | AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600. | ||
| 13 | |||
| 14 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> | ||
| 15 | Reviewed-by: Cédric Le Goater <clg@redhat.com> | ||
| 16 | Link: https://lore.kernel.org/r/20241204084453.610660-4-jamin_lin@aspeedtech.com | ||
| 17 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 7 | --- | 18 | --- |
| 8 | include/hw/arm/aspeed_soc.h | 1 + | 19 | include/hw/sd/aspeed_sdhci.h | 12 +++++++-- |
| 9 | hw/arm/aspeed_ast10x0.c | 7 ++----- | 20 | hw/arm/aspeed_ast2400.c | 3 ++- |
| 10 | hw/arm/aspeed_ast2600.c | 7 ++----- | 21 | hw/arm/aspeed_ast2600.c | 7 +++--- |
| 11 | hw/arm/aspeed_soc.c | 16 ++++++++++++---- | 22 | hw/sd/aspeed_sdhci.c | 47 +++++++++++++++++++++++++++++++++++- |
| 12 | 4 files changed, 17 insertions(+), 14 deletions(-) | 23 | 4 files changed, 61 insertions(+), 8 deletions(-) |
| 13 | 24 | ||
| 14 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | 25 | diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h |
| 15 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/include/hw/arm/aspeed_soc.h | 27 | --- a/include/hw/sd/aspeed_sdhci.h |
| 17 | +++ b/include/hw/arm/aspeed_soc.h | 28 | +++ b/include/hw/sd/aspeed_sdhci.h |
| 18 | @@ -XXX,XX +XXX,XX @@ enum { | 29 | @@ -XXX,XX +XXX,XX @@ |
| 30 | #include "qom/object.h" | ||
| 31 | |||
| 32 | #define TYPE_ASPEED_SDHCI "aspeed.sdhci" | ||
| 33 | -OBJECT_DECLARE_SIMPLE_TYPE(AspeedSDHCIState, ASPEED_SDHCI) | ||
| 34 | +#define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400" | ||
| 35 | +#define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500" | ||
| 36 | +#define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600" | ||
| 37 | +OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI) | ||
| 38 | |||
| 39 | -#define ASPEED_SDHCI_CAPABILITIES 0x01E80080 | ||
| 40 | #define ASPEED_SDHCI_NUM_SLOTS 2 | ||
| 41 | #define ASPEED_SDHCI_NUM_REGS (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t)) | ||
| 42 | #define ASPEED_SDHCI_REG_SIZE 0x100 | ||
| 43 | @@ -XXX,XX +XXX,XX @@ struct AspeedSDHCIState { | ||
| 44 | uint32_t regs[ASPEED_SDHCI_NUM_REGS]; | ||
| 19 | }; | 45 | }; |
| 20 | 46 | ||
| 21 | qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); | 47 | +struct AspeedSDHCIClass { |
| 22 | +void aspeed_soc_uart_init(AspeedSoCState *s); | 48 | + SysBusDeviceClass parent_class; |
| 23 | 49 | + | |
| 24 | #endif /* ASPEED_SOC_H */ | 50 | + uint64_t capareg; |
| 25 | diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c | 51 | +}; |
| 52 | + | ||
| 53 | #endif /* ASPEED_SDHCI_H */ | ||
| 54 | diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | 55 | index XXXXXXX..XXXXXXX 100644 |
| 27 | --- a/hw/arm/aspeed_ast10x0.c | 56 | --- a/hw/arm/aspeed_ast2400.c |
| 28 | +++ b/hw/arm/aspeed_ast10x0.c | 57 | +++ b/hw/arm/aspeed_ast2400.c |
| 29 | @@ -XXX,XX +XXX,XX @@ | 58 | @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj) |
| 30 | #include "sysemu/sysemu.h" | 59 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
| 31 | #include "hw/qdev-clock.h" | 60 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
| 32 | #include "hw/misc/unimp.h" | 61 | |
| 33 | -#include "hw/char/serial.h" | 62 | - object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); |
| 34 | #include "hw/arm/aspeed_soc.h" | 63 | + snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); |
| 35 | 64 | + object_initialize_child(obj, "sdc", &s->sdhci, typename); | |
| 36 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | 65 | |
| 37 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | 66 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
| 38 | qdev_get_gpio_in(DEVICE(&s->armv7m), | 67 | |
| 39 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | ||
| 40 | |||
| 41 | - /* UART - attach an 8250 to the IO space as our UART */ | ||
| 42 | - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | ||
| 43 | - aspeed_soc_get_irq(s, s->uart_default), | ||
| 44 | - 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); | ||
| 45 | + /* UART */ | ||
| 46 | + aspeed_soc_uart_init(s); | ||
| 47 | |||
| 48 | /* Timer */ | ||
| 49 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), | ||
| 50 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | 68 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c |
| 51 | index XXXXXXX..XXXXXXX 100644 | 69 | index XXXXXXX..XXXXXXX 100644 |
| 52 | --- a/hw/arm/aspeed_ast2600.c | 70 | --- a/hw/arm/aspeed_ast2600.c |
| 53 | +++ b/hw/arm/aspeed_ast2600.c | 71 | +++ b/hw/arm/aspeed_ast2600.c |
| 54 | @@ -XXX,XX +XXX,XX @@ | 72 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) |
| 55 | #include "qapi/error.h" | 73 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); |
| 56 | #include "hw/misc/unimp.h" | 74 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
| 57 | #include "hw/arm/aspeed_soc.h" | 75 | |
| 58 | -#include "hw/char/serial.h" | 76 | - object_initialize_child(obj, "sd-controller", &s->sdhci, |
| 59 | #include "qemu/module.h" | 77 | - TYPE_ASPEED_SDHCI); |
| 60 | #include "qemu/error-report.h" | 78 | + snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); |
| 61 | #include "hw/i2c/aspeed_i2c.h" | 79 | + object_initialize_child(obj, "sd-controller", &s->sdhci, typename); |
| 62 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | 80 | |
| 63 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | 81 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
| 64 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | 82 | |
| 65 | 83 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | |
| 66 | - /* UART - attach an 8250 to the IO space as our UART */ | 84 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); |
| 67 | - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | 85 | } |
| 68 | - aspeed_soc_get_irq(s, s->uart_default), 38400, | 86 | |
| 69 | - serial_hd(0), DEVICE_LITTLE_ENDIAN); | 87 | - object_initialize_child(obj, "emmc-controller", &s->emmc, |
| 70 | + /* UART */ | 88 | - TYPE_ASPEED_SDHCI); |
| 71 | + aspeed_soc_uart_init(s); | 89 | + object_initialize_child(obj, "emmc-controller", &s->emmc, typename); |
| 72 | 90 | ||
| 73 | /* I2C */ | 91 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
| 74 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), | 92 | |
| 75 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | 93 | diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c |
| 76 | index XXXXXXX..XXXXXXX 100644 | 94 | index XXXXXXX..XXXXXXX 100644 |
| 77 | --- a/hw/arm/aspeed_soc.c | 95 | --- a/hw/sd/aspeed_sdhci.c |
| 78 | +++ b/hw/arm/aspeed_soc.c | 96 | +++ b/hw/sd/aspeed_sdhci.c |
| 79 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | 97 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) |
| 80 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | ||
| 81 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | ||
| 82 | |||
| 83 | - /* UART - attach an 8250 to the IO space as our UART */ | ||
| 84 | - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | ||
| 85 | - aspeed_soc_get_irq(s, s->uart_default), 38400, | ||
| 86 | - serial_hd(0), DEVICE_LITTLE_ENDIAN); | ||
| 87 | + /* UART */ | ||
| 88 | + aspeed_soc_uart_init(s); | ||
| 89 | |||
| 90 | /* I2C */ | ||
| 91 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), | ||
| 92 | @@ -XXX,XX +XXX,XX @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) | ||
| 93 | { | 98 | { |
| 94 | return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); | 99 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 100 | AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev); | ||
| 101 | + AspeedSDHCIClass *asc = ASPEED_SDHCI_GET_CLASS(sdhci); | ||
| 102 | |||
| 103 | /* Create input irqs for the slots */ | ||
| 104 | qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, | ||
| 105 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) | ||
| 106 | } | ||
| 107 | |||
| 108 | if (!object_property_set_uint(sdhci_slot, "capareg", | ||
| 109 | - ASPEED_SDHCI_CAPABILITIES, errp)) { | ||
| 110 | + asc->capareg, errp)) { | ||
| 111 | return; | ||
| 112 | } | ||
| 113 | |||
| 114 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) | ||
| 115 | device_class_set_props(dc, aspeed_sdhci_properties); | ||
| 95 | } | 116 | } |
| 117 | |||
| 118 | +static void aspeed_2400_sdhci_class_init(ObjectClass *klass, void *data) | ||
| 119 | +{ | ||
| 120 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 121 | + AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass); | ||
| 96 | + | 122 | + |
| 97 | +void aspeed_soc_uart_init(AspeedSoCState *s) | 123 | + dc->desc = "ASPEED 2400 SDHCI Controller"; |
| 124 | + asc->capareg = 0x0000000001e80080; | ||
| 125 | +} | ||
| 126 | + | ||
| 127 | +static void aspeed_2500_sdhci_class_init(ObjectClass *klass, void *data) | ||
| 98 | +{ | 128 | +{ |
| 99 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | 129 | + DeviceClass *dc = DEVICE_CLASS(klass); |
| 130 | + AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass); | ||
| 100 | + | 131 | + |
| 101 | + /* Attach an 8250 to the IO space as our UART */ | 132 | + dc->desc = "ASPEED 2500 SDHCI Controller"; |
| 102 | + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | 133 | + asc->capareg = 0x0000000001e80080; |
| 103 | + aspeed_soc_get_irq(s, s->uart_default), 38400, | ||
| 104 | + serial_hd(0), DEVICE_LITTLE_ENDIAN); | ||
| 105 | +} | 134 | +} |
| 135 | + | ||
| 136 | +static void aspeed_2600_sdhci_class_init(ObjectClass *klass, void *data) | ||
| 137 | +{ | ||
| 138 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 139 | + AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass); | ||
| 140 | + | ||
| 141 | + dc->desc = "ASPEED 2600 SDHCI Controller"; | ||
| 142 | + asc->capareg = 0x0000000701f80080; | ||
| 143 | +} | ||
| 144 | + | ||
| 145 | static const TypeInfo aspeed_sdhci_types[] = { | ||
| 146 | { | ||
| 147 | .name = TYPE_ASPEED_SDHCI, | ||
| 148 | .parent = TYPE_SYS_BUS_DEVICE, | ||
| 149 | .instance_size = sizeof(AspeedSDHCIState), | ||
| 150 | .class_init = aspeed_sdhci_class_init, | ||
| 151 | + .class_size = sizeof(AspeedSDHCIClass), | ||
| 152 | + .abstract = true, | ||
| 153 | + }, | ||
| 154 | + { | ||
| 155 | + .name = TYPE_ASPEED_2400_SDHCI, | ||
| 156 | + .parent = TYPE_ASPEED_SDHCI, | ||
| 157 | + .class_init = aspeed_2400_sdhci_class_init, | ||
| 158 | + }, | ||
| 159 | + { | ||
| 160 | + .name = TYPE_ASPEED_2500_SDHCI, | ||
| 161 | + .parent = TYPE_ASPEED_SDHCI, | ||
| 162 | + .class_init = aspeed_2500_sdhci_class_init, | ||
| 163 | + }, | ||
| 164 | + { | ||
| 165 | + .name = TYPE_ASPEED_2600_SDHCI, | ||
| 166 | + .parent = TYPE_ASPEED_SDHCI, | ||
| 167 | + .class_init = aspeed_2600_sdhci_class_init, | ||
| 168 | }, | ||
| 169 | }; | ||
| 170 | |||
| 106 | -- | 171 | -- |
| 107 | 2.35.3 | 172 | 2.47.1 |
| 108 | 173 | ||
| 109 | 174 | diff view generated by jsdifflib |
| 1 | From: Peter Delevoryas <pdel@fb.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, | 3 | Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class |
| 4 | AST2600, and AST1030. | 4 | init function and set the value of capability register to "0x0000000719f80080". |
| 5 | 5 | ||
| 6 | This also includes the new UART interfaces added in the AST2600 and AST1030 | 6 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 7 | from UART6 to UART13. The addresses and interrupt numbers for these two | 7 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 8 | later chips are identical. | 8 | Link: https://lore.kernel.org/r/20241204084453.610660-5-jamin_lin@aspeedtech.com |
| 9 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 10 | --- | ||
| 11 | include/hw/sd/aspeed_sdhci.h | 1 + | ||
| 12 | hw/sd/aspeed_sdhci.c | 14 ++++++++++++++ | ||
| 13 | 2 files changed, 15 insertions(+) | ||
| 9 | 14 | ||
| 10 | Signed-off-by: Peter Delevoryas <pdel@fb.com> | 15 | diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h |
| 11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
| 12 | Message-Id: <20220516062328.298336-2-pdel@fb.com> | ||
| 13 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 14 | --- | ||
| 15 | include/hw/arm/aspeed_soc.h | 8 ++++++++ | ||
| 16 | hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++++++++++ | ||
| 17 | hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++ | ||
| 18 | hw/arm/aspeed_soc.c | 6 ++++++ | ||
| 19 | 4 files changed, 57 insertions(+) | ||
| 20 | |||
| 21 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 23 | --- a/include/hw/arm/aspeed_soc.h | 17 | --- a/include/hw/sd/aspeed_sdhci.h |
| 24 | +++ b/include/hw/arm/aspeed_soc.h | 18 | +++ b/include/hw/sd/aspeed_sdhci.h |
| 25 | @@ -XXX,XX +XXX,XX @@ enum { | 19 | @@ -XXX,XX +XXX,XX @@ |
| 26 | ASPEED_DEV_UART3, | 20 | #define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400" |
| 27 | ASPEED_DEV_UART4, | 21 | #define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500" |
| 28 | ASPEED_DEV_UART5, | 22 | #define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600" |
| 29 | + ASPEED_DEV_UART6, | 23 | +#define TYPE_ASPEED_2700_SDHCI TYPE_ASPEED_SDHCI "-ast2700" |
| 30 | + ASPEED_DEV_UART7, | 24 | OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI) |
| 31 | + ASPEED_DEV_UART8, | 25 | |
| 32 | + ASPEED_DEV_UART9, | 26 | #define ASPEED_SDHCI_NUM_SLOTS 2 |
| 33 | + ASPEED_DEV_UART10, | 27 | diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c |
| 34 | + ASPEED_DEV_UART11, | ||
| 35 | + ASPEED_DEV_UART12, | ||
| 36 | + ASPEED_DEV_UART13, | ||
| 37 | ASPEED_DEV_VUART, | ||
| 38 | ASPEED_DEV_FMC, | ||
| 39 | ASPEED_DEV_SPI1, | ||
| 40 | diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
| 42 | --- a/hw/arm/aspeed_ast10x0.c | 29 | --- a/hw/sd/aspeed_sdhci.c |
| 43 | +++ b/hw/arm/aspeed_ast10x0.c | 30 | +++ b/hw/sd/aspeed_sdhci.c |
| 44 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = { | 31 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2600_sdhci_class_init(ObjectClass *klass, void *data) |
| 45 | [ASPEED_DEV_SBC] = 0x7E6F2000, | 32 | asc->capareg = 0x0000000701f80080; |
| 46 | [ASPEED_DEV_GPIO] = 0x7E780000, | 33 | } |
| 47 | [ASPEED_DEV_TIMER1] = 0x7E782000, | 34 | |
| 48 | + [ASPEED_DEV_UART1] = 0x7E783000, | 35 | +static void aspeed_2700_sdhci_class_init(ObjectClass *klass, void *data) |
| 49 | + [ASPEED_DEV_UART2] = 0x7E78D000, | 36 | +{ |
| 50 | + [ASPEED_DEV_UART3] = 0x7E78E000, | 37 | + DeviceClass *dc = DEVICE_CLASS(klass); |
| 51 | + [ASPEED_DEV_UART4] = 0x7E78F000, | 38 | + AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass); |
| 52 | [ASPEED_DEV_UART5] = 0x7E784000, | 39 | + |
| 53 | + [ASPEED_DEV_UART6] = 0x7E790000, | 40 | + dc->desc = "ASPEED 2700 SDHCI Controller"; |
| 54 | + [ASPEED_DEV_UART7] = 0x7E790100, | 41 | + asc->capareg = 0x0000000719f80080; |
| 55 | + [ASPEED_DEV_UART8] = 0x7E790200, | 42 | +} |
| 56 | + [ASPEED_DEV_UART9] = 0x7E790300, | 43 | + |
| 57 | + [ASPEED_DEV_UART10] = 0x7E790400, | 44 | static const TypeInfo aspeed_sdhci_types[] = { |
| 58 | + [ASPEED_DEV_UART11] = 0x7E790500, | 45 | { |
| 59 | + [ASPEED_DEV_UART12] = 0x7E790600, | 46 | .name = TYPE_ASPEED_SDHCI, |
| 60 | + [ASPEED_DEV_UART13] = 0x7E790700, | 47 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_sdhci_types[] = { |
| 61 | [ASPEED_DEV_WDT] = 0x7E785000, | 48 | .parent = TYPE_ASPEED_SDHCI, |
| 62 | [ASPEED_DEV_LPC] = 0x7E789000, | 49 | .class_init = aspeed_2600_sdhci_class_init, |
| 63 | [ASPEED_DEV_I2C] = 0x7E7B0000, | 50 | }, |
| 51 | + { | ||
| 52 | + .name = TYPE_ASPEED_2700_SDHCI, | ||
| 53 | + .parent = TYPE_ASPEED_SDHCI, | ||
| 54 | + .class_init = aspeed_2700_sdhci_class_init, | ||
| 55 | + }, | ||
| 64 | }; | 56 | }; |
| 65 | 57 | ||
| 66 | static const int aspeed_soc_ast1030_irqmap[] = { | 58 | DEFINE_TYPES(aspeed_sdhci_types) |
| 67 | + [ASPEED_DEV_UART1] = 47, | ||
| 68 | + [ASPEED_DEV_UART2] = 48, | ||
| 69 | + [ASPEED_DEV_UART3] = 49, | ||
| 70 | + [ASPEED_DEV_UART4] = 50, | ||
| 71 | [ASPEED_DEV_UART5] = 8, | ||
| 72 | + [ASPEED_DEV_UART6] = 57, | ||
| 73 | + [ASPEED_DEV_UART7] = 58, | ||
| 74 | + [ASPEED_DEV_UART8] = 59, | ||
| 75 | + [ASPEED_DEV_UART9] = 60, | ||
| 76 | + [ASPEED_DEV_UART10] = 61, | ||
| 77 | + [ASPEED_DEV_UART11] = 62, | ||
| 78 | + [ASPEED_DEV_UART12] = 63, | ||
| 79 | + [ASPEED_DEV_UART13] = 64, | ||
| 80 | [ASPEED_DEV_GPIO] = 11, | ||
| 81 | [ASPEED_DEV_TIMER1] = 16, | ||
| 82 | [ASPEED_DEV_TIMER2] = 17, | ||
| 83 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
| 84 | index XXXXXXX..XXXXXXX 100644 | ||
| 85 | --- a/hw/arm/aspeed_ast2600.c | ||
| 86 | +++ b/hw/arm/aspeed_ast2600.c | ||
| 87 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | ||
| 88 | [ASPEED_DEV_IBT] = 0x1E789140, | ||
| 89 | [ASPEED_DEV_I2C] = 0x1E78A000, | ||
| 90 | [ASPEED_DEV_UART1] = 0x1E783000, | ||
| 91 | + [ASPEED_DEV_UART2] = 0x1E78D000, | ||
| 92 | + [ASPEED_DEV_UART3] = 0x1E78E000, | ||
| 93 | + [ASPEED_DEV_UART4] = 0x1E78F000, | ||
| 94 | [ASPEED_DEV_UART5] = 0x1E784000, | ||
| 95 | + [ASPEED_DEV_UART6] = 0x1E790000, | ||
| 96 | + [ASPEED_DEV_UART7] = 0x1E790100, | ||
| 97 | + [ASPEED_DEV_UART8] = 0x1E790200, | ||
| 98 | + [ASPEED_DEV_UART9] = 0x1E790300, | ||
| 99 | + [ASPEED_DEV_UART10] = 0x1E790400, | ||
| 100 | + [ASPEED_DEV_UART11] = 0x1E790500, | ||
| 101 | + [ASPEED_DEV_UART12] = 0x1E790600, | ||
| 102 | + [ASPEED_DEV_UART13] = 0x1E790700, | ||
| 103 | [ASPEED_DEV_VUART] = 0x1E787000, | ||
| 104 | [ASPEED_DEV_I3C] = 0x1E7A0000, | ||
| 105 | [ASPEED_DEV_SDRAM] = 0x80000000, | ||
| 106 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = { | ||
| 107 | [ASPEED_DEV_UART3] = 49, | ||
| 108 | [ASPEED_DEV_UART4] = 50, | ||
| 109 | [ASPEED_DEV_UART5] = 8, | ||
| 110 | + [ASPEED_DEV_UART6] = 57, | ||
| 111 | + [ASPEED_DEV_UART7] = 58, | ||
| 112 | + [ASPEED_DEV_UART8] = 59, | ||
| 113 | + [ASPEED_DEV_UART9] = 60, | ||
| 114 | + [ASPEED_DEV_UART10] = 61, | ||
| 115 | + [ASPEED_DEV_UART11] = 62, | ||
| 116 | + [ASPEED_DEV_UART12] = 63, | ||
| 117 | + [ASPEED_DEV_UART13] = 64, | ||
| 118 | [ASPEED_DEV_VUART] = 8, | ||
| 119 | [ASPEED_DEV_FMC] = 39, | ||
| 120 | [ASPEED_DEV_SDMC] = 0, | ||
| 121 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 122 | index XXXXXXX..XXXXXXX 100644 | ||
| 123 | --- a/hw/arm/aspeed_soc.c | ||
| 124 | +++ b/hw/arm/aspeed_soc.c | ||
| 125 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { | ||
| 126 | [ASPEED_DEV_ETH1] = 0x1E660000, | ||
| 127 | [ASPEED_DEV_ETH2] = 0x1E680000, | ||
| 128 | [ASPEED_DEV_UART1] = 0x1E783000, | ||
| 129 | + [ASPEED_DEV_UART2] = 0x1E78D000, | ||
| 130 | + [ASPEED_DEV_UART3] = 0x1E78E000, | ||
| 131 | + [ASPEED_DEV_UART4] = 0x1E78F000, | ||
| 132 | [ASPEED_DEV_UART5] = 0x1E784000, | ||
| 133 | [ASPEED_DEV_VUART] = 0x1E787000, | ||
| 134 | [ASPEED_DEV_SDRAM] = 0x40000000, | ||
| 135 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { | ||
| 136 | [ASPEED_DEV_ETH1] = 0x1E660000, | ||
| 137 | [ASPEED_DEV_ETH2] = 0x1E680000, | ||
| 138 | [ASPEED_DEV_UART1] = 0x1E783000, | ||
| 139 | + [ASPEED_DEV_UART2] = 0x1E78D000, | ||
| 140 | + [ASPEED_DEV_UART3] = 0x1E78E000, | ||
| 141 | + [ASPEED_DEV_UART4] = 0x1E78F000, | ||
| 142 | [ASPEED_DEV_UART5] = 0x1E784000, | ||
| 143 | [ASPEED_DEV_VUART] = 0x1E787000, | ||
| 144 | [ASPEED_DEV_SDRAM] = 0x80000000, | ||
| 145 | -- | 59 | -- |
| 146 | 2.35.3 | 60 | 2.47.1 |
| 147 | 61 | ||
| 148 | 62 | diff view generated by jsdifflib |
| 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | It did not support GPIO index mode for read operation. | 3 | Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1 |
| 4 | slot and registers base address is start at 0x1408_0000 and its interrupt is | ||
| 5 | connected to GICINT133_INTC at bit 1. | ||
| 4 | 6 | ||
| 5 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> | 7 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 8 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 7 | Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com> | 9 | Link: https://lore.kernel.org/r/20241204084453.610660-6-jamin_lin@aspeedtech.com |
| 8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 10 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 9 | --- | 11 | --- |
| 10 | include/hw/gpio/aspeed_gpio.h | 14 +++ | 12 | hw/arm/aspeed_ast27x0.c | 20 ++++++++++++++++++++ |
| 11 | hw/gpio/aspeed_gpio.c | 168 ++++++++++++++++++++++++++++++++++ | 13 | 1 file changed, 20 insertions(+) |
| 12 | 2 files changed, 182 insertions(+) | ||
| 13 | 14 | ||
| 14 | diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h | 15 | diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/include/hw/gpio/aspeed_gpio.h | 17 | --- a/hw/arm/aspeed_ast27x0.c |
| 17 | +++ b/include/hw/gpio/aspeed_gpio.h | 18 | +++ b/hw/arm/aspeed_ast27x0.c |
| 18 | @@ -XXX,XX +XXX,XX @@ enum GPIORegType { | 19 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2700_memmap[] = { |
| 19 | gpio_reg_input_mask, | 20 | [ASPEED_DEV_I2C] = 0x14C0F000, |
| 21 | [ASPEED_DEV_GPIO] = 0x14C0B000, | ||
| 22 | [ASPEED_DEV_RTC] = 0x12C0F000, | ||
| 23 | + [ASPEED_DEV_SDHCI] = 0x14080000, | ||
| 20 | }; | 24 | }; |
| 21 | 25 | ||
| 22 | +/* GPIO index mode */ | 26 | #define AST2700_MAX_IRQ 256 |
| 23 | +enum GPIORegIndexType { | 27 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2700_irqmap[] = { |
| 24 | + gpio_reg_idx_data = 0, | 28 | [ASPEED_DEV_KCS] = 128, |
| 25 | + gpio_reg_idx_direction, | 29 | [ASPEED_DEV_DP] = 28, |
| 26 | + gpio_reg_idx_interrupt, | 30 | [ASPEED_DEV_I3C] = 131, |
| 27 | + gpio_reg_idx_debounce, | 31 | + [ASPEED_DEV_SDHCI] = 133, |
| 28 | + gpio_reg_idx_tolerance, | 32 | }; |
| 29 | + gpio_reg_idx_cmd_src, | 33 | |
| 30 | + gpio_reg_idx_input_mask, | 34 | /* GICINT 128 */ |
| 31 | + gpio_reg_idx_reserved, | 35 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2700_gic132_intcmap[] = { |
| 32 | + gpio_reg_idx_new_w_cmd_src, | 36 | |
| 33 | + gpio_reg_idx_new_r_cmd_src, | 37 | /* GICINT 133 */ |
| 34 | +}; | 38 | static const int aspeed_soc_ast2700_gic133_intcmap[] = { |
| 39 | + [ASPEED_DEV_SDHCI] = 1, | ||
| 40 | [ASPEED_DEV_PECI] = 4, | ||
| 41 | }; | ||
| 42 | |||
| 43 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj) | ||
| 44 | object_initialize_child(obj, "gpio", &s->gpio, typename); | ||
| 45 | |||
| 46 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); | ||
| 35 | + | 47 | + |
| 36 | typedef struct AspeedGPIOReg { | 48 | + snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); |
| 37 | uint16_t set_idx; | 49 | + object_initialize_child(obj, "sd-controller", &s->sdhci, typename); |
| 38 | enum GPIORegType type; | 50 | + object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); |
| 39 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/hw/gpio/aspeed_gpio.c | ||
| 42 | +++ b/hw/gpio/aspeed_gpio.c | ||
| 43 | @@ -XXX,XX +XXX,XX @@ | ||
| 44 | #include "hw/irq.h" | ||
| 45 | #include "migration/vmstate.h" | ||
| 46 | #include "trace.h" | ||
| 47 | +#include "hw/registerfields.h" | ||
| 48 | |||
| 49 | #define GPIOS_PER_GROUP 8 | ||
| 50 | |||
| 51 | @@ -XXX,XX +XXX,XX @@ | ||
| 52 | #define GPIO_1_8V_MEM_SIZE 0x1D8 | ||
| 53 | #define GPIO_1_8V_REG_ARRAY_SIZE (GPIO_1_8V_MEM_SIZE >> 2) | ||
| 54 | |||
| 55 | +/* | ||
| 56 | + * GPIO index mode support | ||
| 57 | + * It only supports write operation | ||
| 58 | + */ | ||
| 59 | +REG32(GPIO_INDEX_REG, 0x2AC) | ||
| 60 | + FIELD(GPIO_INDEX_REG, NUMBER, 0, 8) | ||
| 61 | + FIELD(GPIO_INDEX_REG, COMMAND, 12, 1) | ||
| 62 | + FIELD(GPIO_INDEX_REG, TYPE, 16, 4) | ||
| 63 | + FIELD(GPIO_INDEX_REG, DATA_VALUE, 20, 1) | ||
| 64 | + FIELD(GPIO_INDEX_REG, DIRECTION, 20, 1) | ||
| 65 | + FIELD(GPIO_INDEX_REG, INT_ENABLE, 20, 1) | ||
| 66 | + FIELD(GPIO_INDEX_REG, INT_SENS_0, 21, 1) | ||
| 67 | + FIELD(GPIO_INDEX_REG, INT_SENS_1, 22, 1) | ||
| 68 | + FIELD(GPIO_INDEX_REG, INT_SENS_2, 23, 1) | ||
| 69 | + FIELD(GPIO_INDEX_REG, INT_STATUS, 24, 1) | ||
| 70 | + FIELD(GPIO_INDEX_REG, DEBOUNCE_1, 20, 1) | ||
| 71 | + FIELD(GPIO_INDEX_REG, DEBOUNCE_2, 21, 1) | ||
| 72 | + FIELD(GPIO_INDEX_REG, RESET_TOLERANT, 20, 1) | ||
| 73 | + FIELD(GPIO_INDEX_REG, COMMAND_SRC_0, 20, 1) | ||
| 74 | + FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1) | ||
| 75 | + FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1) | ||
| 76 | + | 51 | + |
| 77 | static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) | 52 | + /* Init sd card slot class here so that they're under the correct parent */ |
| 78 | { | 53 | + object_initialize_child(obj, "sd-controller.sdhci", |
| 79 | uint32_t falling_edge = 0, rising_edge = 0; | 54 | + &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); |
| 80 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) | ||
| 81 | return value; | ||
| 82 | } | 55 | } |
| 83 | 56 | ||
| 84 | +static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset, | 57 | /* |
| 85 | + uint64_t data, uint32_t size) | 58 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) |
| 86 | +{ | 59 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
| 87 | + | 60 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
| 88 | + AspeedGPIOState *s = ASPEED_GPIO(opaque); | 61 | |
| 89 | + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); | 62 | + /* SDHCI */ |
| 90 | + const GPIOSetProperties *props; | 63 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
| 91 | + GPIOSets *set; | ||
| 92 | + uint32_t reg_idx_number = FIELD_EX32(data, GPIO_INDEX_REG, NUMBER); | ||
| 93 | + uint32_t reg_idx_type = FIELD_EX32(data, GPIO_INDEX_REG, TYPE); | ||
| 94 | + uint32_t reg_idx_command = FIELD_EX32(data, GPIO_INDEX_REG, COMMAND); | ||
| 95 | + uint32_t set_idx = reg_idx_number / ASPEED_GPIOS_PER_SET; | ||
| 96 | + uint32_t pin_idx = reg_idx_number % ASPEED_GPIOS_PER_SET; | ||
| 97 | + uint32_t group_idx = pin_idx / GPIOS_PER_GROUP; | ||
| 98 | + uint32_t reg_value = 0; | ||
| 99 | + uint32_t cleared; | ||
| 100 | + | ||
| 101 | + set = &s->sets[set_idx]; | ||
| 102 | + props = &agc->props[set_idx]; | ||
| 103 | + | ||
| 104 | + if (reg_idx_command) | ||
| 105 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" | ||
| 106 | + PRIx64 "index mode wrong command 0x%x\n", | ||
| 107 | + __func__, offset, data, reg_idx_command); | ||
| 108 | + | ||
| 109 | + switch (reg_idx_type) { | ||
| 110 | + case gpio_reg_idx_data: | ||
| 111 | + reg_value = set->data_read; | ||
| 112 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 113 | + FIELD_EX32(data, GPIO_INDEX_REG, DATA_VALUE)); | ||
| 114 | + reg_value &= props->output; | ||
| 115 | + reg_value = update_value_control_source(set, set->data_value, | ||
| 116 | + reg_value); | ||
| 117 | + set->data_read = reg_value; | ||
| 118 | + aspeed_gpio_update(s, set, reg_value); | ||
| 119 | + return; | ||
| 120 | + case gpio_reg_idx_direction: | ||
| 121 | + reg_value = set->direction; | ||
| 122 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 123 | + FIELD_EX32(data, GPIO_INDEX_REG, DIRECTION)); | ||
| 124 | + /* | ||
| 125 | + * where data is the value attempted to be written to the pin: | ||
| 126 | + * pin type | input mask | output mask | expected value | ||
| 127 | + * ------------------------------------------------------------ | ||
| 128 | + * bidirectional | 1 | 1 | data | ||
| 129 | + * input only | 1 | 0 | 0 | ||
| 130 | + * output only | 0 | 1 | 1 | ||
| 131 | + * no pin | 0 | 0 | 0 | ||
| 132 | + * | ||
| 133 | + * which is captured by: | ||
| 134 | + * data = ( data | ~input) & output; | ||
| 135 | + */ | ||
| 136 | + reg_value = (reg_value | ~props->input) & props->output; | ||
| 137 | + set->direction = update_value_control_source(set, set->direction, | ||
| 138 | + reg_value); | ||
| 139 | + break; | ||
| 140 | + case gpio_reg_idx_interrupt: | ||
| 141 | + reg_value = set->int_enable; | ||
| 142 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 143 | + FIELD_EX32(data, GPIO_INDEX_REG, INT_ENABLE)); | ||
| 144 | + set->int_enable = update_value_control_source(set, set->int_enable, | ||
| 145 | + reg_value); | ||
| 146 | + reg_value = set->int_sens_0; | ||
| 147 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 148 | + FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_0)); | ||
| 149 | + set->int_sens_0 = update_value_control_source(set, set->int_sens_0, | ||
| 150 | + reg_value); | ||
| 151 | + reg_value = set->int_sens_1; | ||
| 152 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 153 | + FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_1)); | ||
| 154 | + set->int_sens_1 = update_value_control_source(set, set->int_sens_1, | ||
| 155 | + reg_value); | ||
| 156 | + reg_value = set->int_sens_2; | ||
| 157 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 158 | + FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_2)); | ||
| 159 | + set->int_sens_2 = update_value_control_source(set, set->int_sens_2, | ||
| 160 | + reg_value); | ||
| 161 | + /* set interrupt status */ | ||
| 162 | + reg_value = set->int_status; | ||
| 163 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 164 | + FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)); | ||
| 165 | + cleared = ctpop32(reg_value & set->int_status); | ||
| 166 | + if (s->pending && cleared) { | ||
| 167 | + assert(s->pending >= cleared); | ||
| 168 | + s->pending -= cleared; | ||
| 169 | + } | ||
| 170 | + set->int_status &= ~reg_value; | ||
| 171 | + break; | ||
| 172 | + case gpio_reg_idx_debounce: | ||
| 173 | + reg_value = set->debounce_1; | ||
| 174 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 175 | + FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_1)); | ||
| 176 | + set->debounce_1 = update_value_control_source(set, set->debounce_1, | ||
| 177 | + reg_value); | ||
| 178 | + reg_value = set->debounce_2; | ||
| 179 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 180 | + FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_2)); | ||
| 181 | + set->debounce_2 = update_value_control_source(set, set->debounce_2, | ||
| 182 | + reg_value); | ||
| 183 | + return; | ||
| 184 | + case gpio_reg_idx_tolerance: | ||
| 185 | + reg_value = set->reset_tol; | ||
| 186 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 187 | + FIELD_EX32(data, GPIO_INDEX_REG, RESET_TOLERANT)); | ||
| 188 | + set->reset_tol = update_value_control_source(set, set->reset_tol, | ||
| 189 | + reg_value); | ||
| 190 | + return; | ||
| 191 | + case gpio_reg_idx_cmd_src: | ||
| 192 | + reg_value = set->cmd_source_0; | ||
| 193 | + reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1, | ||
| 194 | + FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC_0)); | ||
| 195 | + set->cmd_source_0 = reg_value & ASPEED_CMD_SRC_MASK; | ||
| 196 | + reg_value = set->cmd_source_1; | ||
| 197 | + reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1, | ||
| 198 | + FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC_1)); | ||
| 199 | + set->cmd_source_1 = reg_value & ASPEED_CMD_SRC_MASK; | ||
| 200 | + return; | ||
| 201 | + case gpio_reg_idx_input_mask: | ||
| 202 | + reg_value = set->input_mask; | ||
| 203 | + reg_value = deposit32(reg_value, pin_idx, 1, | ||
| 204 | + FIELD_EX32(data, GPIO_INDEX_REG, INPUT_MASK)); | ||
| 205 | + /* | ||
| 206 | + * feeds into interrupt generation | ||
| 207 | + * 0: read from data value reg will be updated | ||
| 208 | + * 1: read from data value reg will not be updated | ||
| 209 | + */ | ||
| 210 | + set->input_mask = reg_value & props->input; | ||
| 211 | + break; | ||
| 212 | + default: | ||
| 213 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" | ||
| 214 | + PRIx64 "index mode wrong type 0x%x\n", | ||
| 215 | + __func__, offset, data, reg_idx_type); | ||
| 216 | + return; | 64 | + return; |
| 217 | + } | 65 | + } |
| 218 | + aspeed_gpio_update(s, set, set->data_value); | 66 | + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, |
| 219 | + return; | 67 | + sc->memmap[ASPEED_DEV_SDHCI]); |
| 220 | +} | 68 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
| 69 | + aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); | ||
| 221 | + | 70 | + |
| 222 | static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, | 71 | create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); |
| 223 | uint32_t size) | 72 | create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); |
| 224 | { | 73 | create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); |
| 225 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 226 | trace_aspeed_gpio_write(offset, data); | ||
| 227 | |||
| 228 | idx = offset >> 2; | ||
| 229 | + | ||
| 230 | + /* check gpio index mode */ | ||
| 231 | + if (idx == R_GPIO_INDEX_REG) { | ||
| 232 | + aspeed_gpio_write_index_mode(opaque, offset, data, size); | ||
| 233 | + return; | ||
| 234 | + } | ||
| 235 | + | ||
| 236 | if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { | ||
| 237 | idx -= GPIO_DEBOUNCE_TIME_1; | ||
| 238 | s->debounce_regs[idx] = (uint32_t) data; | ||
| 239 | -- | 74 | -- |
| 240 | 2.35.3 | 75 | 2.47.1 |
| 241 | 76 | ||
| 242 | 77 | diff view generated by jsdifflib |
| 1 | From: Howard Chiu <howard_chiu@aspeedtech.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add EEPROM and LM75 temperature sensor according to hardware schematic | 3 | Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1 |
| 4 | slot and registers base address is start at 0x1209_0000 and its interrupt is | ||
| 5 | connected to GICINT 15. | ||
| 4 | 6 | ||
| 5 | Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com> | 7 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 8 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 9 | Link: https://lore.kernel.org/r/20241204084453.610660-7-jamin_lin@aspeedtech.com |
| 10 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 8 | --- | 11 | --- |
| 9 | hw/arm/aspeed.c | 11 +++++++++-- | 12 | hw/arm/aspeed_ast27x0.c | 15 +++++++++++++++ |
| 10 | 1 file changed, 9 insertions(+), 2 deletions(-) | 13 | 1 file changed, 15 insertions(+) |
| 11 | 14 | ||
| 12 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 15 | diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c |
| 13 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/hw/arm/aspeed.c | 17 | --- a/hw/arm/aspeed_ast27x0.c |
| 15 | +++ b/hw/arm/aspeed.c | 18 | +++ b/hw/arm/aspeed_ast27x0.c |
| 16 | @@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc) | 19 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj) |
| 17 | 20 | /* Init sd card slot class here so that they're under the correct parent */ | |
| 18 | static void ast2600_evb_i2c_init(AspeedMachineState *bmc) | 21 | object_initialize_child(obj, "sd-controller.sdhci", |
| 19 | { | 22 | &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); |
| 20 | - /* Start with some devices on our I2C busses */ | ||
| 21 | - ast2500_evb_i2c_init(bmc); | ||
| 22 | + AspeedSoCState *soc = &bmc->soc; | ||
| 23 | + uint8_t *eeprom_buf = g_malloc0(8 * 1024); | ||
| 24 | + | 23 | + |
| 25 | + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, | 24 | + object_initialize_child(obj, "emmc-controller", &s->emmc, typename); |
| 26 | + eeprom_buf); | 25 | + object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
| 27 | + | 26 | + |
| 28 | + /* LM75 is compatible with TMP105 driver */ | 27 | + object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
| 29 | + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), | 28 | + TYPE_SYSBUS_SDHCI); |
| 30 | + TYPE_TMP105, 0x4d); | ||
| 31 | } | 29 | } |
| 32 | 30 | ||
| 33 | static void romulus_bmc_i2c_init(AspeedMachineState *bmc) | 31 | /* |
| 32 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) | ||
| 33 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
| 34 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); | ||
| 35 | |||
| 36 | + /* eMMC */ | ||
| 37 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { | ||
| 38 | + return; | ||
| 39 | + } | ||
| 40 | + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, | ||
| 41 | + sc->memmap[ASPEED_DEV_EMMC]); | ||
| 42 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, | ||
| 43 | + aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); | ||
| 44 | + | ||
| 45 | create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); | ||
| 46 | create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); | ||
| 47 | create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); | ||
| 34 | -- | 48 | -- |
| 35 | 2.35.3 | 49 | 2.47.1 |
| 36 | 50 | ||
| 37 | 51 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | This simply moves the ast1030 tests to a new test file. No changes. | ||
| 1 | 2 | ||
| 3 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 4 | Link: https://lore.kernel.org/r/20241206131132.520911-2-clg@redhat.com | ||
| 5 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 6 | --- | ||
| 7 | tests/functional/meson.build | 1 + | ||
| 8 | tests/functional/test_arm_aspeed.py | 64 ---------------- | ||
| 9 | tests/functional/test_arm_aspeed_ast1030.py | 81 +++++++++++++++++++++ | ||
| 10 | 3 files changed, 82 insertions(+), 64 deletions(-) | ||
| 11 | create mode 100644 tests/functional/test_arm_aspeed_ast1030.py | ||
| 12 | |||
| 13 | diff --git a/tests/functional/meson.build b/tests/functional/meson.build | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/tests/functional/meson.build | ||
| 16 | +++ b/tests/functional/meson.build | ||
| 17 | @@ -XXX,XX +XXX,XX @@ tests_alpha_system_thorough = [ | ||
| 18 | |||
| 19 | tests_arm_system_thorough = [ | ||
| 20 | 'arm_aspeed', | ||
| 21 | + 'arm_aspeed_ast1030', | ||
| 22 | 'arm_bpim2u', | ||
| 23 | 'arm_canona1100', | ||
| 24 | 'arm_collie', | ||
| 25 | diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py | ||
| 26 | index XXXXXXX..XXXXXXX 100755 | ||
| 27 | --- a/tests/functional/test_arm_aspeed.py | ||
| 28 | +++ b/tests/functional/test_arm_aspeed.py | ||
| 29 | @@ -XXX,XX +XXX,XX @@ | ||
| 30 | from zipfile import ZipFile | ||
| 31 | from unittest import skipUnless | ||
| 32 | |||
| 33 | -class AST1030Machine(LinuxKernelTest): | ||
| 34 | - | ||
| 35 | - ASSET_ZEPHYR_1_04 = Asset( | ||
| 36 | - ('https://github.com/AspeedTech-BMC' | ||
| 37 | - '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip'), | ||
| 38 | - '4ac6210adcbc61294927918707c6762483fd844dde5e07f3ba834ad1f91434d3') | ||
| 39 | - | ||
| 40 | - def test_ast1030_zephyros_1_04(self): | ||
| 41 | - self.set_machine('ast1030-evb') | ||
| 42 | - | ||
| 43 | - zip_file = self.ASSET_ZEPHYR_1_04.fetch() | ||
| 44 | - | ||
| 45 | - kernel_name = "ast1030-evb-demo/zephyr.elf" | ||
| 46 | - with ZipFile(zip_file, 'r') as zf: | ||
| 47 | - zf.extract(kernel_name, path=self.workdir) | ||
| 48 | - kernel_file = os.path.join(self.workdir, kernel_name) | ||
| 49 | - | ||
| 50 | - self.vm.set_console() | ||
| 51 | - self.vm.add_args('-kernel', kernel_file, '-nographic') | ||
| 52 | - self.vm.launch() | ||
| 53 | - self.wait_for_console_pattern("Booting Zephyr OS") | ||
| 54 | - exec_command_and_wait_for_pattern(self, "help", | ||
| 55 | - "Available commands") | ||
| 56 | - | ||
| 57 | - ASSET_ZEPHYR_1_07 = Asset( | ||
| 58 | - ('https://github.com/AspeedTech-BMC' | ||
| 59 | - '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip'), | ||
| 60 | - 'ad52e27959746988afaed8429bf4e12ab988c05c4d07c9d90e13ec6f7be4574c') | ||
| 61 | - | ||
| 62 | - def test_ast1030_zephyros_1_07(self): | ||
| 63 | - self.set_machine('ast1030-evb') | ||
| 64 | - | ||
| 65 | - zip_file = self.ASSET_ZEPHYR_1_07.fetch() | ||
| 66 | - | ||
| 67 | - kernel_name = "ast1030-evb-demo/zephyr.bin" | ||
| 68 | - with ZipFile(zip_file, 'r') as zf: | ||
| 69 | - zf.extract(kernel_name, path=self.workdir) | ||
| 70 | - kernel_file = os.path.join(self.workdir, kernel_name) | ||
| 71 | - | ||
| 72 | - self.vm.set_console() | ||
| 73 | - self.vm.add_args('-kernel', kernel_file, '-nographic') | ||
| 74 | - self.vm.launch() | ||
| 75 | - self.wait_for_console_pattern("Booting Zephyr OS") | ||
| 76 | - for shell_cmd in [ | ||
| 77 | - 'kernel stacks', | ||
| 78 | - 'otp info conf', | ||
| 79 | - 'otp info scu', | ||
| 80 | - 'hwinfo devid', | ||
| 81 | - 'crypto aes256_cbc_vault', | ||
| 82 | - 'random get', | ||
| 83 | - 'jtag JTAG1 sw_xfer high TMS', | ||
| 84 | - 'adc ADC0 resolution 12', | ||
| 85 | - 'adc ADC0 read 42', | ||
| 86 | - 'adc ADC1 read 69', | ||
| 87 | - 'i2c scan I2C_0', | ||
| 88 | - 'i3c attach I3C_0', | ||
| 89 | - 'hash test', | ||
| 90 | - 'kernel uptime', | ||
| 91 | - 'kernel reboot warm', | ||
| 92 | - 'kernel uptime', | ||
| 93 | - 'kernel reboot cold', | ||
| 94 | - 'kernel uptime', | ||
| 95 | - ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$") | ||
| 96 | - | ||
| 97 | class AST2x00Machine(LinuxKernelTest): | ||
| 98 | |||
| 99 | def do_test_arm_aspeed(self, machine, image): | ||
| 100 | diff --git a/tests/functional/test_arm_aspeed_ast1030.py b/tests/functional/test_arm_aspeed_ast1030.py | ||
| 101 | new file mode 100644 | ||
| 102 | index XXXXXXX..XXXXXXX | ||
| 103 | --- /dev/null | ||
| 104 | +++ b/tests/functional/test_arm_aspeed_ast1030.py | ||
| 105 | @@ -XXX,XX +XXX,XX @@ | ||
| 106 | +#!/usr/bin/env python3 | ||
| 107 | +# | ||
| 108 | +# Functional test that boots the ASPEED SoCs with firmware | ||
| 109 | +# | ||
| 110 | +# Copyright (C) 2022 ASPEED Technology Inc | ||
| 111 | +# | ||
| 112 | +# SPDX-License-Identifier: GPL-2.0-or-later | ||
| 113 | + | ||
| 114 | +import os | ||
| 115 | + | ||
| 116 | +from qemu_test import LinuxKernelTest, Asset | ||
| 117 | +from qemu_test import exec_command_and_wait_for_pattern | ||
| 118 | +from zipfile import ZipFile | ||
| 119 | + | ||
| 120 | +class AST1030Machine(LinuxKernelTest): | ||
| 121 | + | ||
| 122 | + ASSET_ZEPHYR_1_04 = Asset( | ||
| 123 | + ('https://github.com/AspeedTech-BMC' | ||
| 124 | + '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip'), | ||
| 125 | + '4ac6210adcbc61294927918707c6762483fd844dde5e07f3ba834ad1f91434d3') | ||
| 126 | + | ||
| 127 | + def test_ast1030_zephyros_1_04(self): | ||
| 128 | + self.set_machine('ast1030-evb') | ||
| 129 | + | ||
| 130 | + zip_file = self.ASSET_ZEPHYR_1_04.fetch() | ||
| 131 | + | ||
| 132 | + kernel_name = "ast1030-evb-demo/zephyr.elf" | ||
| 133 | + with ZipFile(zip_file, 'r') as zf: | ||
| 134 | + zf.extract(kernel_name, path=self.workdir) | ||
| 135 | + kernel_file = os.path.join(self.workdir, kernel_name) | ||
| 136 | + | ||
| 137 | + self.vm.set_console() | ||
| 138 | + self.vm.add_args('-kernel', kernel_file, '-nographic') | ||
| 139 | + self.vm.launch() | ||
| 140 | + self.wait_for_console_pattern("Booting Zephyr OS") | ||
| 141 | + exec_command_and_wait_for_pattern(self, "help", | ||
| 142 | + "Available commands") | ||
| 143 | + | ||
| 144 | + ASSET_ZEPHYR_1_07 = Asset( | ||
| 145 | + ('https://github.com/AspeedTech-BMC' | ||
| 146 | + '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip'), | ||
| 147 | + 'ad52e27959746988afaed8429bf4e12ab988c05c4d07c9d90e13ec6f7be4574c') | ||
| 148 | + | ||
| 149 | + def test_ast1030_zephyros_1_07(self): | ||
| 150 | + self.set_machine('ast1030-evb') | ||
| 151 | + | ||
| 152 | + zip_file = self.ASSET_ZEPHYR_1_07.fetch() | ||
| 153 | + | ||
| 154 | + kernel_name = "ast1030-evb-demo/zephyr.bin" | ||
| 155 | + with ZipFile(zip_file, 'r') as zf: | ||
| 156 | + zf.extract(kernel_name, path=self.workdir) | ||
| 157 | + kernel_file = os.path.join(self.workdir, kernel_name) | ||
| 158 | + | ||
| 159 | + self.vm.set_console() | ||
| 160 | + self.vm.add_args('-kernel', kernel_file, '-nographic') | ||
| 161 | + self.vm.launch() | ||
| 162 | + self.wait_for_console_pattern("Booting Zephyr OS") | ||
| 163 | + for shell_cmd in [ | ||
| 164 | + 'kernel stacks', | ||
| 165 | + 'otp info conf', | ||
| 166 | + 'otp info scu', | ||
| 167 | + 'hwinfo devid', | ||
| 168 | + 'crypto aes256_cbc_vault', | ||
| 169 | + 'random get', | ||
| 170 | + 'jtag JTAG1 sw_xfer high TMS', | ||
| 171 | + 'adc ADC0 resolution 12', | ||
| 172 | + 'adc ADC0 read 42', | ||
| 173 | + 'adc ADC1 read 69', | ||
| 174 | + 'i2c scan I2C_0', | ||
| 175 | + 'i3c attach I3C_0', | ||
| 176 | + 'hash test', | ||
| 177 | + 'kernel uptime', | ||
| 178 | + 'kernel reboot warm', | ||
| 179 | + 'kernel uptime', | ||
| 180 | + 'kernel reboot cold', | ||
| 181 | + 'kernel uptime', | ||
| 182 | + ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$") | ||
| 183 | + | ||
| 184 | + | ||
| 185 | +if __name__ == '__main__': | ||
| 186 | + LinuxKernelTest.main() | ||
| 187 | -- | ||
| 188 | 2.47.1 | ||
| 189 | |||
| 190 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | This introduces a new aspeed module for sharing code between tests and | ||
| 2 | moves the palmetto test to a new test file. No changes in the test. | ||
| 1 | 3 | ||
| 4 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 5 | Link: https://lore.kernel.org/r/20241206131132.520911-3-clg@redhat.com | ||
| 6 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 7 | --- | ||
| 8 | tests/functional/aspeed.py | 23 +++++++++++++++++++ | ||
| 9 | tests/functional/meson.build | 2 ++ | ||
| 10 | tests/functional/test_arm_aspeed.py | 10 -------- | ||
| 11 | tests/functional/test_arm_aspeed_palmetto.py | 24 ++++++++++++++++++++ | ||
| 12 | 4 files changed, 49 insertions(+), 10 deletions(-) | ||
| 13 | create mode 100644 tests/functional/aspeed.py | ||
| 14 | create mode 100644 tests/functional/test_arm_aspeed_palmetto.py | ||
| 15 | |||
| 16 | diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py | ||
| 17 | new file mode 100644 | ||
| 18 | index XXXXXXX..XXXXXXX | ||
| 19 | --- /dev/null | ||
| 20 | +++ b/tests/functional/aspeed.py | ||
| 21 | @@ -XXX,XX +XXX,XX @@ | ||
| 22 | +# Test class to boot aspeed machines | ||
| 23 | +# | ||
| 24 | +# SPDX-License-Identifier: GPL-2.0-or-later | ||
| 25 | + | ||
| 26 | +from qemu_test import LinuxKernelTest | ||
| 27 | + | ||
| 28 | +class AspeedTest(LinuxKernelTest): | ||
| 29 | + | ||
| 30 | + def do_test_arm_aspeed(self, machine, image): | ||
| 31 | + self.set_machine(machine) | ||
| 32 | + self.vm.set_console() | ||
| 33 | + self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw', | ||
| 34 | + '-net', 'nic', '-snapshot') | ||
| 35 | + self.vm.launch() | ||
| 36 | + | ||
| 37 | + self.wait_for_console_pattern("U-Boot 2016.07") | ||
| 38 | + self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000") | ||
| 39 | + self.wait_for_console_pattern("Starting kernel ...") | ||
| 40 | + self.wait_for_console_pattern("Booting Linux on physical CPU 0x0") | ||
| 41 | + self.wait_for_console_pattern( | ||
| 42 | + "aspeed-smc 1e620000.spi: read control register: 203b0641") | ||
| 43 | + self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ") | ||
| 44 | + self.wait_for_console_pattern("systemd[1]: Set hostname to") | ||
| 45 | diff --git a/tests/functional/meson.build b/tests/functional/meson.build | ||
| 46 | index XXXXXXX..XXXXXXX 100644 | ||
| 47 | --- a/tests/functional/meson.build | ||
| 48 | +++ b/tests/functional/meson.build | ||
| 49 | @@ -XXX,XX +XXX,XX @@ test_timeouts = { | ||
| 50 | 'aarch64_tuxrun' : 240, | ||
| 51 | 'aarch64_virt' : 720, | ||
| 52 | 'acpi_bits' : 420, | ||
| 53 | + 'arm_aspeed_palmetto' : 120, | ||
| 54 | 'arm_aspeed' : 600, | ||
| 55 | 'arm_bpim2u' : 500, | ||
| 56 | 'arm_collie' : 180, | ||
| 57 | @@ -XXX,XX +XXX,XX @@ tests_alpha_system_thorough = [ | ||
| 58 | tests_arm_system_thorough = [ | ||
| 59 | 'arm_aspeed', | ||
| 60 | 'arm_aspeed_ast1030', | ||
| 61 | + 'arm_aspeed_palmetto', | ||
| 62 | 'arm_bpim2u', | ||
| 63 | 'arm_canona1100', | ||
| 64 | 'arm_collie', | ||
| 65 | diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py | ||
| 66 | index XXXXXXX..XXXXXXX 100755 | ||
| 67 | --- a/tests/functional/test_arm_aspeed.py | ||
| 68 | +++ b/tests/functional/test_arm_aspeed.py | ||
| 69 | @@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed(self, machine, image): | ||
| 70 | self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ") | ||
| 71 | self.wait_for_console_pattern("systemd[1]: Set hostname to") | ||
| 72 | |||
| 73 | - ASSET_PALMETTO_FLASH = Asset( | ||
| 74 | - ('https://github.com/openbmc/openbmc/releases/download/2.9.0/' | ||
| 75 | - 'obmc-phosphor-image-palmetto.static.mtd'), | ||
| 76 | - '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d'); | ||
| 77 | - | ||
| 78 | - def test_arm_ast2400_palmetto_openbmc_v2_9_0(self): | ||
| 79 | - image_path = self.ASSET_PALMETTO_FLASH.fetch() | ||
| 80 | - | ||
| 81 | - self.do_test_arm_aspeed('palmetto-bmc', image_path) | ||
| 82 | - | ||
| 83 | ASSET_ROMULUS_FLASH = Asset( | ||
| 84 | ('https://github.com/openbmc/openbmc/releases/download/2.9.0/' | ||
| 85 | 'obmc-phosphor-image-romulus.static.mtd'), | ||
| 86 | diff --git a/tests/functional/test_arm_aspeed_palmetto.py b/tests/functional/test_arm_aspeed_palmetto.py | ||
| 87 | new file mode 100644 | ||
| 88 | index XXXXXXX..XXXXXXX | ||
| 89 | --- /dev/null | ||
| 90 | +++ b/tests/functional/test_arm_aspeed_palmetto.py | ||
| 91 | @@ -XXX,XX +XXX,XX @@ | ||
| 92 | +#!/usr/bin/env python3 | ||
| 93 | +# | ||
| 94 | +# Functional test that boots the ASPEED machines | ||
| 95 | +# | ||
| 96 | +# SPDX-License-Identifier: GPL-2.0-or-later | ||
| 97 | + | ||
| 98 | +from qemu_test import Asset | ||
| 99 | +from aspeed import AspeedTest | ||
| 100 | + | ||
| 101 | +class PalmettoMachine(AspeedTest): | ||
| 102 | + | ||
| 103 | + ASSET_PALMETTO_FLASH = Asset( | ||
| 104 | + ('https://github.com/openbmc/openbmc/releases/download/2.9.0/' | ||
| 105 | + 'obmc-phosphor-image-palmetto.static.mtd'), | ||
| 106 | + '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d'); | ||
| 107 | + | ||
| 108 | + def test_arm_ast2400_palmetto_openbmc_v2_9_0(self): | ||
| 109 | + image_path = self.ASSET_PALMETTO_FLASH.fetch() | ||
| 110 | + | ||
| 111 | + self.do_test_arm_aspeed('palmetto-bmc', image_path) | ||
| 112 | + | ||
| 113 | + | ||
| 114 | +if __name__ == '__main__': | ||
| 115 | + AspeedTest.main() | ||
| 116 | -- | ||
| 117 | 2.47.1 | ||
| 118 | |||
| 119 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | This simply moves the romulus-bmc test to a new test file. No changes | ||
| 2 | in the test. The do_test_arm_aspeed routine is removed from the | ||
| 3 | test_arm_aspeed.py file because it is now unused. | ||
| 1 | 4 | ||
| 5 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 6 | Link: https://lore.kernel.org/r/20241206131132.520911-4-clg@redhat.com | ||
| 7 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 8 | --- | ||
| 9 | tests/functional/meson.build | 2 ++ | ||
| 10 | tests/functional/test_arm_aspeed.py | 26 --------------------- | ||
| 11 | tests/functional/test_arm_aspeed_romulus.py | 24 +++++++++++++++++++ | ||
| 12 | 3 files changed, 26 insertions(+), 26 deletions(-) | ||
| 13 | create mode 100644 tests/functional/test_arm_aspeed_romulus.py | ||
| 14 | |||
| 15 | diff --git a/tests/functional/meson.build b/tests/functional/meson.build | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/tests/functional/meson.build | ||
| 18 | +++ b/tests/functional/meson.build | ||
| 19 | @@ -XXX,XX +XXX,XX @@ test_timeouts = { | ||
| 20 | 'aarch64_virt' : 720, | ||
| 21 | 'acpi_bits' : 420, | ||
| 22 | 'arm_aspeed_palmetto' : 120, | ||
| 23 | + 'arm_aspeed_romulus' : 120, | ||
| 24 | 'arm_aspeed' : 600, | ||
| 25 | 'arm_bpim2u' : 500, | ||
| 26 | 'arm_collie' : 180, | ||
| 27 | @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ | ||
| 28 | 'arm_aspeed', | ||
| 29 | 'arm_aspeed_ast1030', | ||
| 30 | 'arm_aspeed_palmetto', | ||
| 31 | + 'arm_aspeed_romulus', | ||
| 32 | 'arm_bpim2u', | ||
| 33 | 'arm_canona1100', | ||
| 34 | 'arm_collie', | ||
| 35 | diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py | ||
| 36 | index XXXXXXX..XXXXXXX 100755 | ||
| 37 | --- a/tests/functional/test_arm_aspeed.py | ||
| 38 | +++ b/tests/functional/test_arm_aspeed.py | ||
| 39 | @@ -XXX,XX +XXX,XX @@ | ||
| 40 | |||
| 41 | class AST2x00Machine(LinuxKernelTest): | ||
| 42 | |||
| 43 | - def do_test_arm_aspeed(self, machine, image): | ||
| 44 | - self.set_machine(machine) | ||
| 45 | - self.vm.set_console() | ||
| 46 | - self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw', | ||
| 47 | - '-net', 'nic', '-snapshot') | ||
| 48 | - self.vm.launch() | ||
| 49 | - | ||
| 50 | - self.wait_for_console_pattern("U-Boot 2016.07") | ||
| 51 | - self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000") | ||
| 52 | - self.wait_for_console_pattern("Starting kernel ...") | ||
| 53 | - self.wait_for_console_pattern("Booting Linux on physical CPU 0x0") | ||
| 54 | - self.wait_for_console_pattern( | ||
| 55 | - "aspeed-smc 1e620000.spi: read control register: 203b0641") | ||
| 56 | - self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ") | ||
| 57 | - self.wait_for_console_pattern("systemd[1]: Set hostname to") | ||
| 58 | - | ||
| 59 | - ASSET_ROMULUS_FLASH = Asset( | ||
| 60 | - ('https://github.com/openbmc/openbmc/releases/download/2.9.0/' | ||
| 61 | - 'obmc-phosphor-image-romulus.static.mtd'), | ||
| 62 | - '820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25') | ||
| 63 | - | ||
| 64 | - def test_arm_ast2500_romulus_openbmc_v2_9_0(self): | ||
| 65 | - image_path = self.ASSET_ROMULUS_FLASH.fetch() | ||
| 66 | - | ||
| 67 | - self.do_test_arm_aspeed('romulus-bmc', image_path) | ||
| 68 | - | ||
| 69 | def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'): | ||
| 70 | self.require_netdev('user') | ||
| 71 | self.vm.set_console() | ||
| 72 | diff --git a/tests/functional/test_arm_aspeed_romulus.py b/tests/functional/test_arm_aspeed_romulus.py | ||
| 73 | new file mode 100644 | ||
| 74 | index XXXXXXX..XXXXXXX | ||
| 75 | --- /dev/null | ||
| 76 | +++ b/tests/functional/test_arm_aspeed_romulus.py | ||
| 77 | @@ -XXX,XX +XXX,XX @@ | ||
| 78 | +#!/usr/bin/env python3 | ||
| 79 | +# | ||
| 80 | +# Functional test that boots the ASPEED machines | ||
| 81 | +# | ||
| 82 | +# SPDX-License-Identifier: GPL-2.0-or-later | ||
| 83 | + | ||
| 84 | +from qemu_test import Asset | ||
| 85 | +from aspeed import AspeedTest | ||
| 86 | + | ||
| 87 | +class RomulusMachine(AspeedTest): | ||
| 88 | + | ||
| 89 | + ASSET_ROMULUS_FLASH = Asset( | ||
| 90 | + ('https://github.com/openbmc/openbmc/releases/download/2.9.0/' | ||
| 91 | + 'obmc-phosphor-image-romulus.static.mtd'), | ||
| 92 | + '820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25') | ||
| 93 | + | ||
| 94 | + def test_arm_ast2500_romulus_openbmc_v2_9_0(self): | ||
| 95 | + image_path = self.ASSET_ROMULUS_FLASH.fetch() | ||
| 96 | + | ||
| 97 | + self.do_test_arm_aspeed('romulus-bmc', image_path) | ||
| 98 | + | ||
| 99 | + | ||
| 100 | +if __name__ == '__main__': | ||
| 101 | + AspeedTest.main() | ||
| 102 | -- | ||
| 103 | 2.47.1 | ||
| 104 | |||
| 105 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | This moves the ast2500-evb tests to a new test file and extends the | |
| 2 | aspeed module with routines used to run the buildroot and sdk | ||
| 3 | tests. No changes in the test. | ||
| 4 | |||
| 5 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 6 | Link: https://lore.kernel.org/r/20241206131132.520911-5-clg@redhat.com | ||
| 7 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 8 | --- | ||
| 9 | tests/functional/aspeed.py | 33 ++++++++++++ | ||
| 10 | tests/functional/meson.build | 2 + | ||
| 11 | tests/functional/test_arm_aspeed.py | 44 --------------- | ||
| 12 | tests/functional/test_arm_aspeed_ast2500.py | 59 +++++++++++++++++++++ | ||
| 13 | 4 files changed, 94 insertions(+), 44 deletions(-) | ||
| 14 | create mode 100644 tests/functional/test_arm_aspeed_ast2500.py | ||
| 15 | |||
| 16 | diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/tests/functional/aspeed.py | ||
| 19 | +++ b/tests/functional/aspeed.py | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | # | ||
| 22 | # SPDX-License-Identifier: GPL-2.0-or-later | ||
| 23 | |||
| 24 | +from qemu_test import exec_command_and_wait_for_pattern | ||
| 25 | from qemu_test import LinuxKernelTest | ||
| 26 | |||
| 27 | class AspeedTest(LinuxKernelTest): | ||
| 28 | @@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed(self, machine, image): | ||
| 29 | "aspeed-smc 1e620000.spi: read control register: 203b0641") | ||
| 30 | self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ") | ||
| 31 | self.wait_for_console_pattern("systemd[1]: Set hostname to") | ||
| 32 | + | ||
| 33 | + def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'): | ||
| 34 | + self.require_netdev('user') | ||
| 35 | + self.vm.set_console() | ||
| 36 | + self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw,read-only=true', | ||
| 37 | + '-net', 'nic', '-net', 'user') | ||
| 38 | + self.vm.launch() | ||
| 39 | + | ||
| 40 | + self.wait_for_console_pattern('U-Boot 2019.04') | ||
| 41 | + self.wait_for_console_pattern('## Loading kernel from FIT Image') | ||
| 42 | + self.wait_for_console_pattern('Starting kernel ...') | ||
| 43 | + self.wait_for_console_pattern('Booting Linux on physical CPU ' + cpu_id) | ||
| 44 | + self.wait_for_console_pattern('lease of 10.0.2.15') | ||
| 45 | + # the line before login: | ||
| 46 | + self.wait_for_console_pattern(pattern) | ||
| 47 | + exec_command_and_wait_for_pattern(self, 'root', 'Password:') | ||
| 48 | + exec_command_and_wait_for_pattern(self, 'passw0rd', '#') | ||
| 49 | + | ||
| 50 | + def do_test_arm_aspeed_buildroot_poweroff(self): | ||
| 51 | + exec_command_and_wait_for_pattern(self, 'poweroff', | ||
| 52 | + 'reboot: System halted'); | ||
| 53 | + | ||
| 54 | + def do_test_arm_aspeed_sdk_start(self, image): | ||
| 55 | + self.require_netdev('user') | ||
| 56 | + self.vm.set_console() | ||
| 57 | + self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw', | ||
| 58 | + '-net', 'nic', '-net', 'user', '-snapshot') | ||
| 59 | + self.vm.launch() | ||
| 60 | + | ||
| 61 | + self.wait_for_console_pattern('U-Boot 2019.04') | ||
| 62 | + self.wait_for_console_pattern('## Loading kernel from FIT Image') | ||
| 63 | + self.wait_for_console_pattern('Starting kernel ...') | ||
| 64 | diff --git a/tests/functional/meson.build b/tests/functional/meson.build | ||
| 65 | index XXXXXXX..XXXXXXX 100644 | ||
| 66 | --- a/tests/functional/meson.build | ||
| 67 | +++ b/tests/functional/meson.build | ||
| 68 | @@ -XXX,XX +XXX,XX @@ test_timeouts = { | ||
| 69 | 'acpi_bits' : 420, | ||
| 70 | 'arm_aspeed_palmetto' : 120, | ||
| 71 | 'arm_aspeed_romulus' : 120, | ||
| 72 | + 'arm_aspeed_ast2500' : 480, | ||
| 73 | 'arm_aspeed' : 600, | ||
| 74 | 'arm_bpim2u' : 500, | ||
| 75 | 'arm_collie' : 180, | ||
| 76 | @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ | ||
| 77 | 'arm_aspeed_ast1030', | ||
| 78 | 'arm_aspeed_palmetto', | ||
| 79 | 'arm_aspeed_romulus', | ||
| 80 | + 'arm_aspeed_ast2500', | ||
| 81 | 'arm_bpim2u', | ||
| 82 | 'arm_canona1100', | ||
| 83 | 'arm_collie', | ||
| 84 | diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py | ||
| 85 | index XXXXXXX..XXXXXXX 100755 | ||
| 86 | --- a/tests/functional/test_arm_aspeed.py | ||
| 87 | +++ b/tests/functional/test_arm_aspeed.py | ||
| 88 | @@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB' | ||
| 89 | def do_test_arm_aspeed_buildroot_poweroff(self): | ||
| 90 | exec_command_and_wait_for_pattern(self, 'poweroff', | ||
| 91 | 'reboot: System halted'); | ||
| 92 | - | ||
| 93 | - ASSET_BR2_202311_AST2500_FLASH = Asset( | ||
| 94 | - ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' | ||
| 95 | - 'images/ast2500-evb/buildroot-2023.11/flash.img'), | ||
| 96 | - 'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f') | ||
| 97 | - | ||
| 98 | - def test_arm_ast2500_evb_buildroot(self): | ||
| 99 | - self.set_machine('ast2500-evb') | ||
| 100 | - | ||
| 101 | - image_path = self.ASSET_BR2_202311_AST2500_FLASH.fetch() | ||
| 102 | - | ||
| 103 | - self.vm.add_args('-device', | ||
| 104 | - 'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test'); | ||
| 105 | - self.do_test_arm_aspeed_buildroot_start(image_path, '0x0', | ||
| 106 | - 'ast2500-evb login:') | ||
| 107 | - | ||
| 108 | - exec_command_and_wait_for_pattern(self, | ||
| 109 | - 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device', | ||
| 110 | - 'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d'); | ||
| 111 | - exec_command_and_wait_for_pattern(self, | ||
| 112 | - 'cat /sys/class/hwmon/hwmon1/temp1_input', '0') | ||
| 113 | - self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test', | ||
| 114 | - property='temperature', value=18000); | ||
| 115 | - exec_command_and_wait_for_pattern(self, | ||
| 116 | - 'cat /sys/class/hwmon/hwmon1/temp1_input', '18000') | ||
| 117 | - | ||
| 118 | - self.do_test_arm_aspeed_buildroot_poweroff() | ||
| 119 | - | ||
| 120 | ASSET_BR2_202311_AST2600_FLASH = Asset( | ||
| 121 | ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' | ||
| 122 | 'images/ast2600-evb/buildroot-2023.11/flash.img'), | ||
| 123 | @@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_sdk_start(self, image): | ||
| 124 | self.wait_for_console_pattern('## Loading kernel from FIT Image') | ||
| 125 | self.wait_for_console_pattern('Starting kernel ...') | ||
| 126 | |||
| 127 | - ASSET_SDK_V806_AST2500 = Asset( | ||
| 128 | - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2500-default-obmc.tar.gz', | ||
| 129 | - 'e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca') | ||
| 130 | - | ||
| 131 | - def test_arm_ast2500_evb_sdk(self): | ||
| 132 | - self.set_machine('ast2500-evb') | ||
| 133 | - | ||
| 134 | - image_path = self.ASSET_SDK_V806_AST2500.fetch() | ||
| 135 | - | ||
| 136 | - archive_extract(image_path, self.workdir) | ||
| 137 | - | ||
| 138 | - self.do_test_arm_aspeed_sdk_start( | ||
| 139 | - self.workdir + '/ast2500-default/image-bmc') | ||
| 140 | - | ||
| 141 | - self.wait_for_console_pattern('ast2500-default login:') | ||
| 142 | - | ||
| 143 | ASSET_SDK_V806_AST2600_A2 = Asset( | ||
| 144 | 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz', | ||
| 145 | '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4') | ||
| 146 | diff --git a/tests/functional/test_arm_aspeed_ast2500.py b/tests/functional/test_arm_aspeed_ast2500.py | ||
| 147 | new file mode 100644 | ||
| 148 | index XXXXXXX..XXXXXXX | ||
| 149 | --- /dev/null | ||
| 150 | +++ b/tests/functional/test_arm_aspeed_ast2500.py | ||
| 151 | @@ -XXX,XX +XXX,XX @@ | ||
| 152 | +#!/usr/bin/env python3 | ||
| 153 | +# | ||
| 154 | +# Functional test that boots the ASPEED machines | ||
| 155 | +# | ||
| 156 | +# SPDX-License-Identifier: GPL-2.0-or-later | ||
| 157 | + | ||
| 158 | +from qemu_test import Asset | ||
| 159 | +from aspeed import AspeedTest | ||
| 160 | +from qemu_test import exec_command_and_wait_for_pattern | ||
| 161 | +from qemu_test.utils import archive_extract | ||
| 162 | + | ||
| 163 | +class AST2500Machine(AspeedTest): | ||
| 164 | + | ||
| 165 | + ASSET_BR2_202311_AST2500_FLASH = Asset( | ||
| 166 | + ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' | ||
| 167 | + 'images/ast2500-evb/buildroot-2023.11/flash.img'), | ||
| 168 | + 'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f') | ||
| 169 | + | ||
| 170 | + def test_arm_ast2500_evb_buildroot(self): | ||
| 171 | + self.set_machine('ast2500-evb') | ||
| 172 | + | ||
| 173 | + image_path = self.ASSET_BR2_202311_AST2500_FLASH.fetch() | ||
| 174 | + | ||
| 175 | + self.vm.add_args('-device', | ||
| 176 | + 'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test'); | ||
| 177 | + self.do_test_arm_aspeed_buildroot_start(image_path, '0x0', | ||
| 178 | + 'ast2500-evb login:') | ||
| 179 | + | ||
| 180 | + exec_command_and_wait_for_pattern(self, | ||
| 181 | + 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device', | ||
| 182 | + 'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d'); | ||
| 183 | + exec_command_and_wait_for_pattern(self, | ||
| 184 | + 'cat /sys/class/hwmon/hwmon1/temp1_input', '0') | ||
| 185 | + self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test', | ||
| 186 | + property='temperature', value=18000); | ||
| 187 | + exec_command_and_wait_for_pattern(self, | ||
| 188 | + 'cat /sys/class/hwmon/hwmon1/temp1_input', '18000') | ||
| 189 | + | ||
| 190 | + self.do_test_arm_aspeed_buildroot_poweroff() | ||
| 191 | + | ||
| 192 | + ASSET_SDK_V806_AST2500 = Asset( | ||
| 193 | + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2500-default-obmc.tar.gz', | ||
| 194 | + 'e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca') | ||
| 195 | + | ||
| 196 | + def test_arm_ast2500_evb_sdk(self): | ||
| 197 | + self.set_machine('ast2500-evb') | ||
| 198 | + | ||
| 199 | + image_path = self.ASSET_SDK_V806_AST2500.fetch() | ||
| 200 | + | ||
| 201 | + archive_extract(image_path, self.workdir) | ||
| 202 | + | ||
| 203 | + self.do_test_arm_aspeed_sdk_start( | ||
| 204 | + self.workdir + '/ast2500-default/image-bmc') | ||
| 205 | + | ||
| 206 | + self.wait_for_console_pattern('ast2500-default login:') | ||
| 207 | + | ||
| 208 | + | ||
| 209 | +if __name__ == '__main__': | ||
| 210 | + AspeedTest.main() | ||
| 211 | -- | ||
| 212 | 2.47.1 | ||
| 213 | |||
| 214 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | This moves the ast2600-evb tests to a new test file. No changes in the | ||
| 2 | test. The routines used to run the buildroot and sdk tests are removed | ||
| 3 | from the test_arm_aspeed.py file because now unused. | ||
| 1 | 4 | ||
| 5 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 6 | Link: https://lore.kernel.org/r/20241206131132.520911-6-clg@redhat.com | ||
| 7 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 8 | --- | ||
| 9 | tests/functional/meson.build | 2 + | ||
| 10 | tests/functional/test_arm_aspeed.py | 155 -------------------- | ||
| 11 | tests/functional/test_arm_aspeed_ast2600.py | 143 ++++++++++++++++++ | ||
| 12 | 3 files changed, 145 insertions(+), 155 deletions(-) | ||
| 13 | create mode 100644 tests/functional/test_arm_aspeed_ast2600.py | ||
| 14 | |||
| 15 | diff --git a/tests/functional/meson.build b/tests/functional/meson.build | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/tests/functional/meson.build | ||
| 18 | +++ b/tests/functional/meson.build | ||
| 19 | @@ -XXX,XX +XXX,XX @@ test_timeouts = { | ||
| 20 | 'arm_aspeed_palmetto' : 120, | ||
| 21 | 'arm_aspeed_romulus' : 120, | ||
| 22 | 'arm_aspeed_ast2500' : 480, | ||
| 23 | + 'arm_aspeed_ast2600' : 720, | ||
| 24 | 'arm_aspeed' : 600, | ||
| 25 | 'arm_bpim2u' : 500, | ||
| 26 | 'arm_collie' : 180, | ||
| 27 | @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ | ||
| 28 | 'arm_aspeed_palmetto', | ||
| 29 | 'arm_aspeed_romulus', | ||
| 30 | 'arm_aspeed_ast2500', | ||
| 31 | + 'arm_aspeed_ast2600', | ||
| 32 | 'arm_bpim2u', | ||
| 33 | 'arm_canona1100', | ||
| 34 | 'arm_collie', | ||
| 35 | diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py | ||
| 36 | index XXXXXXX..XXXXXXX 100755 | ||
| 37 | --- a/tests/functional/test_arm_aspeed.py | ||
| 38 | +++ b/tests/functional/test_arm_aspeed.py | ||
| 39 | @@ -XXX,XX +XXX,XX @@ | ||
| 40 | from zipfile import ZipFile | ||
| 41 | from unittest import skipUnless | ||
| 42 | |||
| 43 | -class AST2x00Machine(LinuxKernelTest): | ||
| 44 | - | ||
| 45 | - def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'): | ||
| 46 | - self.require_netdev('user') | ||
| 47 | - self.vm.set_console() | ||
| 48 | - self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw,read-only=true', | ||
| 49 | - '-net', 'nic', '-net', 'user') | ||
| 50 | - self.vm.launch() | ||
| 51 | - | ||
| 52 | - self.wait_for_console_pattern('U-Boot 2019.04') | ||
| 53 | - self.wait_for_console_pattern('## Loading kernel from FIT Image') | ||
| 54 | - self.wait_for_console_pattern('Starting kernel ...') | ||
| 55 | - self.wait_for_console_pattern('Booting Linux on physical CPU ' + cpu_id) | ||
| 56 | - self.wait_for_console_pattern('lease of 10.0.2.15') | ||
| 57 | - # the line before login: | ||
| 58 | - self.wait_for_console_pattern(pattern) | ||
| 59 | - exec_command_and_wait_for_pattern(self, 'root', 'Password:') | ||
| 60 | - exec_command_and_wait_for_pattern(self, 'passw0rd', '#') | ||
| 61 | - | ||
| 62 | - def do_test_arm_aspeed_buildroot_poweroff(self): | ||
| 63 | - exec_command_and_wait_for_pattern(self, 'poweroff', | ||
| 64 | - 'reboot: System halted'); | ||
| 65 | - ASSET_BR2_202311_AST2600_FLASH = Asset( | ||
| 66 | - ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' | ||
| 67 | - 'images/ast2600-evb/buildroot-2023.11/flash.img'), | ||
| 68 | - 'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68') | ||
| 69 | - | ||
| 70 | - def test_arm_ast2600_evb_buildroot(self): | ||
| 71 | - self.set_machine('ast2600-evb') | ||
| 72 | - | ||
| 73 | - image_path = self.ASSET_BR2_202311_AST2600_FLASH.fetch() | ||
| 74 | - | ||
| 75 | - self.vm.add_args('-device', | ||
| 76 | - 'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test'); | ||
| 77 | - self.vm.add_args('-device', | ||
| 78 | - 'ds1338,bus=aspeed.i2c.bus.3,address=0x32'); | ||
| 79 | - self.vm.add_args('-device', | ||
| 80 | - 'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42'); | ||
| 81 | - self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', | ||
| 82 | - 'ast2600-evb login:') | ||
| 83 | - | ||
| 84 | - exec_command_and_wait_for_pattern(self, | ||
| 85 | - 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device', | ||
| 86 | - 'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d'); | ||
| 87 | - exec_command_and_wait_for_pattern(self, | ||
| 88 | - 'cat /sys/class/hwmon/hwmon1/temp1_input', '0') | ||
| 89 | - self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test', | ||
| 90 | - property='temperature', value=18000); | ||
| 91 | - exec_command_and_wait_for_pattern(self, | ||
| 92 | - 'cat /sys/class/hwmon/hwmon1/temp1_input', '18000') | ||
| 93 | - | ||
| 94 | - exec_command_and_wait_for_pattern(self, | ||
| 95 | - 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device', | ||
| 96 | - 'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32'); | ||
| 97 | - year = time.strftime("%Y") | ||
| 98 | - exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year); | ||
| 99 | - | ||
| 100 | - exec_command_and_wait_for_pattern(self, | ||
| 101 | - 'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_device', | ||
| 102 | - 'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x64'); | ||
| 103 | - exec_command_and_wait_for_pattern(self, | ||
| 104 | - 'i2cset -y 3 0x42 0x64 0x00 0xaa i', '#'); | ||
| 105 | - exec_command_and_wait_for_pattern(self, | ||
| 106 | - 'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom', | ||
| 107 | - '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff'); | ||
| 108 | - self.do_test_arm_aspeed_buildroot_poweroff() | ||
| 109 | - | ||
| 110 | - ASSET_BR2_202302_AST2600_TPM_FLASH = Asset( | ||
| 111 | - ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' | ||
| 112 | - 'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'), | ||
| 113 | - 'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997') | ||
| 114 | - | ||
| 115 | - @skipUnless(*has_cmd('swtpm')) | ||
| 116 | - def test_arm_ast2600_evb_buildroot_tpm(self): | ||
| 117 | - self.set_machine('ast2600-evb') | ||
| 118 | - | ||
| 119 | - image_path = self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch() | ||
| 120 | - | ||
| 121 | - tpmstate_dir = tempfile.TemporaryDirectory(prefix="qemu_") | ||
| 122 | - socket = os.path.join(tpmstate_dir.name, 'swtpm-socket') | ||
| 123 | - | ||
| 124 | - # We must put the TPM state dir in /tmp/, not the build dir, | ||
| 125 | - # because some distros use AppArmor to lock down swtpm and | ||
| 126 | - # restrict the set of locations it can access files in. | ||
| 127 | - subprocess.run(['swtpm', 'socket', '-d', '--tpm2', | ||
| 128 | - '--tpmstate', f'dir={tpmstate_dir.name}', | ||
| 129 | - '--ctrl', f'type=unixio,path={socket}']) | ||
| 130 | - | ||
| 131 | - self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}') | ||
| 132 | - self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm') | ||
| 133 | - self.vm.add_args('-device', | ||
| 134 | - 'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e') | ||
| 135 | - self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB') | ||
| 136 | - | ||
| 137 | - exec_command_and_wait_for_pattern(self, | ||
| 138 | - 'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device', | ||
| 139 | - 'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)'); | ||
| 140 | - exec_command_and_wait_for_pattern(self, | ||
| 141 | - 'cat /sys/class/tpm/tpm0/pcr-sha256/0', | ||
| 142 | - 'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0'); | ||
| 143 | - | ||
| 144 | - self.do_test_arm_aspeed_buildroot_poweroff() | ||
| 145 | - | ||
| 146 | - def do_test_arm_aspeed_sdk_start(self, image): | ||
| 147 | - self.require_netdev('user') | ||
| 148 | - self.vm.set_console() | ||
| 149 | - self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw', | ||
| 150 | - '-net', 'nic', '-net', 'user', '-snapshot') | ||
| 151 | - self.vm.launch() | ||
| 152 | - | ||
| 153 | - self.wait_for_console_pattern('U-Boot 2019.04') | ||
| 154 | - self.wait_for_console_pattern('## Loading kernel from FIT Image') | ||
| 155 | - self.wait_for_console_pattern('Starting kernel ...') | ||
| 156 | - | ||
| 157 | - ASSET_SDK_V806_AST2600_A2 = Asset( | ||
| 158 | - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz', | ||
| 159 | - '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4') | ||
| 160 | - | ||
| 161 | - def test_arm_ast2600_evb_sdk(self): | ||
| 162 | - self.set_machine('ast2600-evb') | ||
| 163 | - | ||
| 164 | - image_path = self.ASSET_SDK_V806_AST2600_A2.fetch() | ||
| 165 | - | ||
| 166 | - archive_extract(image_path, self.workdir) | ||
| 167 | - | ||
| 168 | - self.vm.add_args('-device', | ||
| 169 | - 'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test'); | ||
| 170 | - self.vm.add_args('-device', | ||
| 171 | - 'ds1338,bus=aspeed.i2c.bus.5,address=0x32'); | ||
| 172 | - self.do_test_arm_aspeed_sdk_start( | ||
| 173 | - self.workdir + '/ast2600-a2/image-bmc') | ||
| 174 | - | ||
| 175 | - self.wait_for_console_pattern('ast2600-a2 login:') | ||
| 176 | - | ||
| 177 | - exec_command_and_wait_for_pattern(self, 'root', 'Password:') | ||
| 178 | - exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-a2:~#') | ||
| 179 | - | ||
| 180 | - exec_command_and_wait_for_pattern(self, | ||
| 181 | - 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device', | ||
| 182 | - 'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d'); | ||
| 183 | - exec_command_and_wait_for_pattern(self, | ||
| 184 | - 'cat /sys/class/hwmon/hwmon19/temp1_input', '0') | ||
| 185 | - self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test', | ||
| 186 | - property='temperature', value=18000); | ||
| 187 | - exec_command_and_wait_for_pattern(self, | ||
| 188 | - 'cat /sys/class/hwmon/hwmon19/temp1_input', '18000') | ||
| 189 | - | ||
| 190 | - exec_command_and_wait_for_pattern(self, | ||
| 191 | - 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_device', | ||
| 192 | - 'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32'); | ||
| 193 | - year = time.strftime("%Y") | ||
| 194 | - exec_command_and_wait_for_pattern(self, | ||
| 195 | - '/sbin/hwclock -f /dev/rtc1', year); | ||
| 196 | - | ||
| 197 | - | ||
| 198 | class AST2x00MachineMMC(LinuxKernelTest): | ||
| 199 | |||
| 200 | ASSET_RAINIER_EMMC = Asset( | ||
| 201 | diff --git a/tests/functional/test_arm_aspeed_ast2600.py b/tests/functional/test_arm_aspeed_ast2600.py | ||
| 202 | new file mode 100644 | ||
| 203 | index XXXXXXX..XXXXXXX | ||
| 204 | --- /dev/null | ||
| 205 | +++ b/tests/functional/test_arm_aspeed_ast2600.py | ||
| 206 | @@ -XXX,XX +XXX,XX @@ | ||
| 207 | +#!/usr/bin/env python3 | ||
| 208 | +# | ||
| 209 | +# Functional test that boots the ASPEED machines | ||
| 210 | +# | ||
| 211 | +# SPDX-License-Identifier: GPL-2.0-or-later | ||
| 212 | + | ||
| 213 | +import os | ||
| 214 | +import time | ||
| 215 | +import tempfile | ||
| 216 | +import subprocess | ||
| 217 | + | ||
| 218 | +from qemu_test import Asset | ||
| 219 | +from aspeed import AspeedTest | ||
| 220 | +from qemu_test import exec_command_and_wait_for_pattern | ||
| 221 | +from qemu_test import has_cmd | ||
| 222 | +from qemu_test.utils import archive_extract | ||
| 223 | +from unittest import skipUnless | ||
| 224 | + | ||
| 225 | +class AST2600Machine(AspeedTest): | ||
| 226 | + | ||
| 227 | + ASSET_BR2_202311_AST2600_FLASH = Asset( | ||
| 228 | + ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' | ||
| 229 | + 'images/ast2600-evb/buildroot-2023.11/flash.img'), | ||
| 230 | + 'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68') | ||
| 231 | + | ||
| 232 | + def test_arm_ast2600_evb_buildroot(self): | ||
| 233 | + self.set_machine('ast2600-evb') | ||
| 234 | + | ||
| 235 | + image_path = self.ASSET_BR2_202311_AST2600_FLASH.fetch() | ||
| 236 | + | ||
| 237 | + self.vm.add_args('-device', | ||
| 238 | + 'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test'); | ||
| 239 | + self.vm.add_args('-device', | ||
| 240 | + 'ds1338,bus=aspeed.i2c.bus.3,address=0x32'); | ||
| 241 | + self.vm.add_args('-device', | ||
| 242 | + 'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42'); | ||
| 243 | + self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', | ||
| 244 | + 'ast2600-evb login:') | ||
| 245 | + | ||
| 246 | + exec_command_and_wait_for_pattern(self, | ||
| 247 | + 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device', | ||
| 248 | + 'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d'); | ||
| 249 | + exec_command_and_wait_for_pattern(self, | ||
| 250 | + 'cat /sys/class/hwmon/hwmon1/temp1_input', '0') | ||
| 251 | + self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test', | ||
| 252 | + property='temperature', value=18000); | ||
| 253 | + exec_command_and_wait_for_pattern(self, | ||
| 254 | + 'cat /sys/class/hwmon/hwmon1/temp1_input', '18000') | ||
| 255 | + | ||
| 256 | + exec_command_and_wait_for_pattern(self, | ||
| 257 | + 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device', | ||
| 258 | + 'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32'); | ||
| 259 | + year = time.strftime("%Y") | ||
| 260 | + exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year); | ||
| 261 | + | ||
| 262 | + exec_command_and_wait_for_pattern(self, | ||
| 263 | + 'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_device', | ||
| 264 | + 'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x64'); | ||
| 265 | + exec_command_and_wait_for_pattern(self, | ||
| 266 | + 'i2cset -y 3 0x42 0x64 0x00 0xaa i', '#'); | ||
| 267 | + exec_command_and_wait_for_pattern(self, | ||
| 268 | + 'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom', | ||
| 269 | + '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff'); | ||
| 270 | + self.do_test_arm_aspeed_buildroot_poweroff() | ||
| 271 | + | ||
| 272 | + ASSET_BR2_202302_AST2600_TPM_FLASH = Asset( | ||
| 273 | + ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' | ||
| 274 | + 'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'), | ||
| 275 | + 'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997') | ||
| 276 | + | ||
| 277 | + @skipUnless(*has_cmd('swtpm')) | ||
| 278 | + def test_arm_ast2600_evb_buildroot_tpm(self): | ||
| 279 | + self.set_machine('ast2600-evb') | ||
| 280 | + | ||
| 281 | + image_path = self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch() | ||
| 282 | + | ||
| 283 | + tpmstate_dir = tempfile.TemporaryDirectory(prefix="qemu_") | ||
| 284 | + socket = os.path.join(tpmstate_dir.name, 'swtpm-socket') | ||
| 285 | + | ||
| 286 | + # We must put the TPM state dir in /tmp/, not the build dir, | ||
| 287 | + # because some distros use AppArmor to lock down swtpm and | ||
| 288 | + # restrict the set of locations it can access files in. | ||
| 289 | + subprocess.run(['swtpm', 'socket', '-d', '--tpm2', | ||
| 290 | + '--tpmstate', f'dir={tpmstate_dir.name}', | ||
| 291 | + '--ctrl', f'type=unixio,path={socket}']) | ||
| 292 | + | ||
| 293 | + self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}') | ||
| 294 | + self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm') | ||
| 295 | + self.vm.add_args('-device', | ||
| 296 | + 'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e') | ||
| 297 | + self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB') | ||
| 298 | + | ||
| 299 | + exec_command_and_wait_for_pattern(self, | ||
| 300 | + 'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device', | ||
| 301 | + 'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)'); | ||
| 302 | + exec_command_and_wait_for_pattern(self, | ||
| 303 | + 'cat /sys/class/tpm/tpm0/pcr-sha256/0', | ||
| 304 | + 'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0'); | ||
| 305 | + | ||
| 306 | + self.do_test_arm_aspeed_buildroot_poweroff() | ||
| 307 | + | ||
| 308 | + ASSET_SDK_V806_AST2600_A2 = Asset( | ||
| 309 | + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz', | ||
| 310 | + '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4') | ||
| 311 | + | ||
| 312 | + def test_arm_ast2600_evb_sdk(self): | ||
| 313 | + self.set_machine('ast2600-evb') | ||
| 314 | + | ||
| 315 | + image_path = self.ASSET_SDK_V806_AST2600_A2.fetch() | ||
| 316 | + | ||
| 317 | + archive_extract(image_path, self.workdir) | ||
| 318 | + | ||
| 319 | + self.vm.add_args('-device', | ||
| 320 | + 'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test'); | ||
| 321 | + self.vm.add_args('-device', | ||
| 322 | + 'ds1338,bus=aspeed.i2c.bus.5,address=0x32'); | ||
| 323 | + self.do_test_arm_aspeed_sdk_start( | ||
| 324 | + self.workdir + '/ast2600-a2/image-bmc') | ||
| 325 | + | ||
| 326 | + self.wait_for_console_pattern('ast2600-a2 login:') | ||
| 327 | + | ||
| 328 | + exec_command_and_wait_for_pattern(self, 'root', 'Password:') | ||
| 329 | + exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-a2:~#') | ||
| 330 | + | ||
| 331 | + exec_command_and_wait_for_pattern(self, | ||
| 332 | + 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device', | ||
| 333 | + 'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d'); | ||
| 334 | + exec_command_and_wait_for_pattern(self, | ||
| 335 | + 'cat /sys/class/hwmon/hwmon19/temp1_input', '0') | ||
| 336 | + self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test', | ||
| 337 | + property='temperature', value=18000); | ||
| 338 | + exec_command_and_wait_for_pattern(self, | ||
| 339 | + 'cat /sys/class/hwmon/hwmon19/temp1_input', '18000') | ||
| 340 | + | ||
| 341 | + exec_command_and_wait_for_pattern(self, | ||
| 342 | + 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_device', | ||
| 343 | + 'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32'); | ||
| 344 | + year = time.strftime("%Y") | ||
| 345 | + exec_command_and_wait_for_pattern(self, | ||
| 346 | + '/sbin/hwclock -f /dev/rtc1', year); | ||
| 347 | + | ||
| 348 | +if __name__ == '__main__': | ||
| 349 | + AspeedTest.main() | ||
| 350 | -- | ||
| 351 | 2.47.1 | ||
| 352 | |||
| 353 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | This simply moves the rainier-bmc test to a new test file. No changes | ||
| 2 | in the test. The test_arm_aspeed.py is deleted. | ||
| 1 | 3 | ||
| 4 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 5 | Link: https://lore.kernel.org/r/20241206131132.520911-7-clg@redhat.com | ||
| 6 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 7 | --- | ||
| 8 | tests/functional/meson.build | 4 ++-- | ||
| 9 | ...m_aspeed.py => test_arm_aspeed_rainier.py} | 22 +++++-------------- | ||
| 10 | 2 files changed, 7 insertions(+), 19 deletions(-) | ||
| 11 | rename tests/functional/{test_arm_aspeed.py => test_arm_aspeed_rainier.py} (71%) | ||
| 12 | mode change 100755 => 100644 | ||
| 13 | |||
| 14 | diff --git a/tests/functional/meson.build b/tests/functional/meson.build | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/tests/functional/meson.build | ||
| 17 | +++ b/tests/functional/meson.build | ||
| 18 | @@ -XXX,XX +XXX,XX @@ test_timeouts = { | ||
| 19 | 'arm_aspeed_romulus' : 120, | ||
| 20 | 'arm_aspeed_ast2500' : 480, | ||
| 21 | 'arm_aspeed_ast2600' : 720, | ||
| 22 | - 'arm_aspeed' : 600, | ||
| 23 | + 'arm_aspeed_rainier' : 240, | ||
| 24 | 'arm_bpim2u' : 500, | ||
| 25 | 'arm_collie' : 180, | ||
| 26 | 'arm_orangepi' : 540, | ||
| 27 | @@ -XXX,XX +XXX,XX @@ tests_alpha_system_thorough = [ | ||
| 28 | ] | ||
| 29 | |||
| 30 | tests_arm_system_thorough = [ | ||
| 31 | - 'arm_aspeed', | ||
| 32 | 'arm_aspeed_ast1030', | ||
| 33 | 'arm_aspeed_palmetto', | ||
| 34 | 'arm_aspeed_romulus', | ||
| 35 | 'arm_aspeed_ast2500', | ||
| 36 | 'arm_aspeed_ast2600', | ||
| 37 | + 'arm_aspeed_rainier', | ||
| 38 | 'arm_bpim2u', | ||
| 39 | 'arm_canona1100', | ||
| 40 | 'arm_collie', | ||
| 41 | diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed_rainier.py | ||
| 42 | old mode 100755 | ||
| 43 | new mode 100644 | ||
| 44 | similarity index 71% | ||
| 45 | rename from tests/functional/test_arm_aspeed.py | ||
| 46 | rename to tests/functional/test_arm_aspeed_rainier.py | ||
| 47 | index XXXXXXX..XXXXXXX | ||
| 48 | --- a/tests/functional/test_arm_aspeed.py | ||
| 49 | +++ b/tests/functional/test_arm_aspeed_rainier.py | ||
| 50 | @@ -XXX,XX +XXX,XX @@ | ||
| 51 | #!/usr/bin/env python3 | ||
| 52 | # | ||
| 53 | -# Functional test that boots the ASPEED SoCs with firmware | ||
| 54 | -# | ||
| 55 | -# Copyright (C) 2022 ASPEED Technology Inc | ||
| 56 | +# Functional test that boots the ASPEED machines | ||
| 57 | # | ||
| 58 | # SPDX-License-Identifier: GPL-2.0-or-later | ||
| 59 | |||
| 60 | -import os | ||
| 61 | -import time | ||
| 62 | -import subprocess | ||
| 63 | -import tempfile | ||
| 64 | - | ||
| 65 | -from qemu_test import LinuxKernelTest, Asset | ||
| 66 | -from qemu_test import exec_command_and_wait_for_pattern | ||
| 67 | -from qemu_test import interrupt_interactive_console_until_pattern | ||
| 68 | -from qemu_test import has_cmd | ||
| 69 | -from qemu_test.utils import archive_extract | ||
| 70 | -from zipfile import ZipFile | ||
| 71 | -from unittest import skipUnless | ||
| 72 | +from qemu_test import Asset | ||
| 73 | +from aspeed import AspeedTest | ||
| 74 | |||
| 75 | -class AST2x00MachineMMC(LinuxKernelTest): | ||
| 76 | +class RainierMachine(AspeedTest): | ||
| 77 | |||
| 78 | ASSET_RAINIER_EMMC = Asset( | ||
| 79 | ('https://fileserver.linaro.org/s/B6pJTwWEkzSDi36/download/' | ||
| 80 | @@ -XXX,XX +XXX,XX @@ def test_arm_aspeed_emmc_boot(self): | ||
| 81 | self.wait_for_console_pattern('IBM eBMC (OpenBMC for IBM Enterprise') | ||
| 82 | |||
| 83 | if __name__ == '__main__': | ||
| 84 | - LinuxKernelTest.main() | ||
| 85 | + AspeedTest.main() | ||
| 86 | -- | ||
| 87 | 2.47.1 | ||
| 88 | |||
| 89 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | This simply moves the debian boot test from the avocado testsuite to | ||
| 2 | the new functional testsuite. No changes in the test. | ||
| 1 | 3 | ||
| 4 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 5 | Link: https://lore.kernel.org/r/20241206131132.520911-8-clg@redhat.com | ||
| 6 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 7 | --- | ||
| 8 | tests/avocado/boot_linux_console.py | 26 --------------------- | ||
| 9 | tests/functional/test_arm_aspeed_rainier.py | 24 +++++++++++++++++++ | ||
| 10 | 2 files changed, 24 insertions(+), 26 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/tests/avocado/boot_linux_console.py | ||
| 15 | +++ b/tests/avocado/boot_linux_console.py | ||
| 16 | @@ -XXX,XX +XXX,XX @@ def test_arm_quanta_gsj_initrd(self): | ||
| 17 | self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0') | ||
| 18 | self.wait_for_console_pattern( | ||
| 19 | 'Give root password for system maintenance') | ||
| 20 | - | ||
| 21 | - def test_arm_ast2600_debian(self): | ||
| 22 | - """ | ||
| 23 | - :avocado: tags=arch:arm | ||
| 24 | - :avocado: tags=machine:rainier-bmc | ||
| 25 | - """ | ||
| 26 | - deb_url = ('http://snapshot.debian.org/archive/debian/' | ||
| 27 | - '20220606T211338Z/' | ||
| 28 | - 'pool/main/l/linux/' | ||
| 29 | - 'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb') | ||
| 30 | - deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e' | ||
| 31 | - deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash, | ||
| 32 | - algorithm='sha256') | ||
| 33 | - kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp') | ||
| 34 | - dtb_path = self.extract_from_deb(deb_path, | ||
| 35 | - '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb') | ||
| 36 | - | ||
| 37 | - self.vm.set_console() | ||
| 38 | - self.vm.add_args('-kernel', kernel_path, | ||
| 39 | - '-dtb', dtb_path, | ||
| 40 | - '-net', 'nic') | ||
| 41 | - self.vm.launch() | ||
| 42 | - self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00") | ||
| 43 | - self.wait_for_console_pattern("SMP: Total of 2 processors activated") | ||
| 44 | - self.wait_for_console_pattern("No filesystem could mount root") | ||
| 45 | - | ||
| 46 | diff --git a/tests/functional/test_arm_aspeed_rainier.py b/tests/functional/test_arm_aspeed_rainier.py | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | ||
| 48 | --- a/tests/functional/test_arm_aspeed_rainier.py | ||
| 49 | +++ b/tests/functional/test_arm_aspeed_rainier.py | ||
| 50 | @@ -XXX,XX +XXX,XX @@ def test_arm_aspeed_emmc_boot(self): | ||
| 51 | self.wait_for_console_pattern('mmcblk0: p1 p2 p3 p4 p5 p6 p7') | ||
| 52 | self.wait_for_console_pattern('IBM eBMC (OpenBMC for IBM Enterprise') | ||
| 53 | |||
| 54 | + ASSET_DEBIAN_LINUX_ARMHF_DEB = Asset( | ||
| 55 | + ('http://snapshot.debian.org/archive/debian/20220606T211338Z/pool/main/l/linux/linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb'), | ||
| 56 | + '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e') | ||
| 57 | + | ||
| 58 | + def test_arm_debian_kernel_boot(self): | ||
| 59 | + self.set_machine('rainier-bmc') | ||
| 60 | + | ||
| 61 | + deb_path = self.ASSET_DEBIAN_LINUX_ARMHF_DEB.fetch() | ||
| 62 | + | ||
| 63 | + kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp') | ||
| 64 | + dtb_path = self.extract_from_deb(deb_path, | ||
| 65 | + '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb') | ||
| 66 | + | ||
| 67 | + self.vm.set_console() | ||
| 68 | + self.vm.add_args('-kernel', kernel_path, | ||
| 69 | + '-dtb', dtb_path, | ||
| 70 | + '-net', 'nic') | ||
| 71 | + self.vm.launch() | ||
| 72 | + | ||
| 73 | + self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00") | ||
| 74 | + self.wait_for_console_pattern("SMP: Total of 2 processors activated") | ||
| 75 | + self.wait_for_console_pattern("No filesystem could mount root") | ||
| 76 | + | ||
| 77 | + | ||
| 78 | if __name__ == '__main__': | ||
| 79 | AspeedTest.main() | ||
| 80 | -- | ||
| 81 | 2.47.1 | ||
| 82 | |||
| 83 | diff view generated by jsdifflib |
| 1 | From: Iris Chen <irischenlj@fb.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The write_enable latch property is not currently exposed. | 3 | So far, the test cases are used for testing SMC model with AST2400 BMC. |
| 4 | This commit makes it a modifiable property. | 4 | However, AST2400 is end off live and ASPEED is no longer support this SOC. |
| 5 | To test SMC model for AST2500, AST2600 and AST1030, move the test cases | ||
| 6 | from main to test_palmetto_bmc function. | ||
| 5 | 7 | ||
| 6 | Signed-off-by: Iris Chen <irischenlj@fb.com> | 8 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 7 | Acked-by: Thomas Huth <thuth@redhat.com> | 9 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 10 | Link: https://lore.kernel.org/r/20241127091543.1243114-2-jamin_lin@aspeedtech.com |
| 9 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | 11 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 10 | Message-Id: <20220513055022.951759-1-irischenlj@fb.com> | ||
| 11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 12 | --- | 12 | --- |
| 13 | tests/qtest/libqtest.h | 22 +++++++++++++++++ | 13 | tests/qtest/aspeed_smc-test.c | 16 ++++++++++++---- |
| 14 | hw/block/m25p80.c | 1 + | 14 | 1 file changed, 12 insertions(+), 4 deletions(-) |
| 15 | tests/qtest/aspeed_gpio-test.c | 40 +++++++------------------------ | ||
| 16 | tests/qtest/aspeed_smc-test.c | 43 ++++++++++++++++++++++++++++++++++ | ||
| 17 | tests/qtest/libqtest.c | 24 +++++++++++++++++++ | ||
| 18 | 5 files changed, 98 insertions(+), 32 deletions(-) | ||
| 19 | 15 | ||
| 20 | diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/tests/qtest/libqtest.h | ||
| 23 | +++ b/tests/qtest/libqtest.h | ||
| 24 | @@ -XXX,XX +XXX,XX @@ QTestState *qtest_inproc_init(QTestState **s, bool log, const char* arch, | ||
| 25 | void (*send)(void*, const char*)); | ||
| 26 | |||
| 27 | void qtest_client_inproc_recv(void *opaque, const char *str); | ||
| 28 | + | ||
| 29 | +/** | ||
| 30 | + * qtest_qom_set_bool: | ||
| 31 | + * @s: QTestState instance to operate on. | ||
| 32 | + * @path: Path to the property being set. | ||
| 33 | + * @property: Property being set. | ||
| 34 | + * @value: Value to set the property. | ||
| 35 | + * | ||
| 36 | + * Set the property with passed in value. | ||
| 37 | + */ | ||
| 38 | +void qtest_qom_set_bool(QTestState *s, const char *path, const char *property, | ||
| 39 | + bool value); | ||
| 40 | + | ||
| 41 | +/** | ||
| 42 | + * qtest_qom_get_bool: | ||
| 43 | + * @s: QTestState instance to operate on. | ||
| 44 | + * @path: Path to the property being retrieved. | ||
| 45 | + * @property: Property from where the value is being retrieved. | ||
| 46 | + * | ||
| 47 | + * Returns: Value retrieved from property. | ||
| 48 | + */ | ||
| 49 | +bool qtest_qom_get_bool(QTestState *s, const char *path, const char *property); | ||
| 50 | #endif | ||
| 51 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | ||
| 52 | index XXXXXXX..XXXXXXX 100644 | ||
| 53 | --- a/hw/block/m25p80.c | ||
| 54 | +++ b/hw/block/m25p80.c | ||
| 55 | @@ -XXX,XX +XXX,XX @@ static int m25p80_pre_save(void *opaque) | ||
| 56 | |||
| 57 | static Property m25p80_properties[] = { | ||
| 58 | /* This is default value for Micron flash */ | ||
| 59 | + DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), | ||
| 60 | DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), | ||
| 61 | DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), | ||
| 62 | DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), | ||
| 63 | diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c | ||
| 64 | index XXXXXXX..XXXXXXX 100644 | ||
| 65 | --- a/tests/qtest/aspeed_gpio-test.c | ||
| 66 | +++ b/tests/qtest/aspeed_gpio-test.c | ||
| 67 | @@ -XXX,XX +XXX,XX @@ | ||
| 68 | #include "qapi/qmp/qdict.h" | ||
| 69 | #include "libqtest-single.h" | ||
| 70 | |||
| 71 | -static bool qom_get_bool(QTestState *s, const char *path, const char *property) | ||
| 72 | -{ | ||
| 73 | - QDict *r; | ||
| 74 | - bool b; | ||
| 75 | - | ||
| 76 | - r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': " | ||
| 77 | - "{ 'path': %s, 'property': %s } }", path, property); | ||
| 78 | - b = qdict_get_bool(r, "return"); | ||
| 79 | - qobject_unref(r); | ||
| 80 | - | ||
| 81 | - return b; | ||
| 82 | -} | ||
| 83 | - | ||
| 84 | -static void qom_set_bool(QTestState *s, const char *path, const char *property, | ||
| 85 | - bool value) | ||
| 86 | -{ | ||
| 87 | - QDict *r; | ||
| 88 | - | ||
| 89 | - r = qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': " | ||
| 90 | - "{ 'path': %s, 'property': %s, 'value': %i } }", | ||
| 91 | - path, property, value); | ||
| 92 | - qobject_unref(r); | ||
| 93 | -} | ||
| 94 | - | ||
| 95 | static void test_set_colocated_pins(const void *data) | ||
| 96 | { | ||
| 97 | QTestState *s = (QTestState *)data; | ||
| 98 | @@ -XXX,XX +XXX,XX @@ static void test_set_colocated_pins(const void *data) | ||
| 99 | * gpioV4-7 occupy bits within a single 32-bit value, so we want to make | ||
| 100 | * sure that modifying one doesn't affect the other. | ||
| 101 | */ | ||
| 102 | - qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true); | ||
| 103 | - qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false); | ||
| 104 | - qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true); | ||
| 105 | - qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false); | ||
| 106 | - g_assert(qom_get_bool(s, "/machine/soc/gpio", "gpioV4")); | ||
| 107 | - g_assert(!qom_get_bool(s, "/machine/soc/gpio", "gpioV5")); | ||
| 108 | - g_assert(qom_get_bool(s, "/machine/soc/gpio", "gpioV6")); | ||
| 109 | - g_assert(!qom_get_bool(s, "/machine/soc/gpio", "gpioV7")); | ||
| 110 | + qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true); | ||
| 111 | + qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false); | ||
| 112 | + qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true); | ||
| 113 | + qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false); | ||
| 114 | + g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV4")); | ||
| 115 | + g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV5")); | ||
| 116 | + g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV6")); | ||
| 117 | + g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV7")); | ||
| 118 | } | ||
| 119 | |||
| 120 | int main(int argc, char **argv) | ||
| 121 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c | 16 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c |
| 122 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 123 | --- a/tests/qtest/aspeed_smc-test.c | 18 | --- a/tests/qtest/aspeed_smc-test.c |
| 124 | +++ b/tests/qtest/aspeed_smc-test.c | 19 | +++ b/tests/qtest/aspeed_smc-test.c |
| 125 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void) |
| 126 | #include "qemu/osdep.h" | ||
| 127 | #include "qemu/bswap.h" | ||
| 128 | #include "libqtest-single.h" | ||
| 129 | +#include "qemu/bitops.h" | ||
| 130 | |||
| 131 | /* | ||
| 132 | * ASPEED SPI Controller registers | ||
| 133 | @@ -XXX,XX +XXX,XX @@ | ||
| 134 | #define CTRL_FREADMODE 0x1 | ||
| 135 | #define CTRL_WRITEMODE 0x2 | ||
| 136 | #define CTRL_USERMODE 0x3 | ||
| 137 | +#define SR_WEL BIT(1) | ||
| 138 | |||
| 139 | #define ASPEED_FMC_BASE 0x1E620000 | ||
| 140 | #define ASPEED_FLASH_BASE 0x20000000 | ||
| 141 | @@ -XXX,XX +XXX,XX @@ | ||
| 142 | */ | ||
| 143 | enum { | ||
| 144 | JEDEC_READ = 0x9f, | ||
| 145 | + RDSR = 0x5, | ||
| 146 | + WRDI = 0x4, | ||
| 147 | BULK_ERASE = 0xc7, | ||
| 148 | READ = 0x03, | ||
| 149 | PP = 0x02, | ||
| 150 | @@ -XXX,XX +XXX,XX @@ static void test_write_page_mem(void) | ||
| 151 | flash_reset(); | 21 | flash_reset(); |
| 152 | } | 22 | } |
| 153 | 23 | ||
| 154 | +static void test_read_status_reg(void) | 24 | -int main(int argc, char **argv) |
| 155 | +{ | 25 | +static int test_palmetto_bmc(void) |
| 156 | + uint8_t r; | 26 | { |
| 27 | g_autofree char *tmp_path = NULL; | ||
| 28 | int ret; | ||
| 29 | int fd; | ||
| 30 | |||
| 31 | - g_test_init(&argc, &argv, NULL); | ||
| 32 | - | ||
| 33 | fd = g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL); | ||
| 34 | g_assert(fd >= 0); | ||
| 35 | ret = ftruncate(fd, FLASH_SIZE); | ||
| 36 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | ||
| 37 | |||
| 38 | flash_reset(); | ||
| 39 | ret = g_test_run(); | ||
| 40 | - | ||
| 41 | qtest_quit(global_qtest); | ||
| 42 | unlink(tmp_path); | ||
| 157 | + | 43 | + |
| 158 | + spi_conf(CONF_ENABLE_W0); | 44 | + return ret; |
| 159 | + | ||
| 160 | + spi_ctrl_start_user(); | ||
| 161 | + writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 162 | + r = readb(ASPEED_FLASH_BASE); | ||
| 163 | + spi_ctrl_stop_user(); | ||
| 164 | + | ||
| 165 | + g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 166 | + g_assert(!qtest_qom_get_bool | ||
| 167 | + (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 168 | + | ||
| 169 | + spi_ctrl_start_user(); | ||
| 170 | + writeb(ASPEED_FLASH_BASE, WREN); | ||
| 171 | + writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 172 | + r = readb(ASPEED_FLASH_BASE); | ||
| 173 | + spi_ctrl_stop_user(); | ||
| 174 | + | ||
| 175 | + g_assert_cmphex(r & SR_WEL, ==, SR_WEL); | ||
| 176 | + g_assert(qtest_qom_get_bool | ||
| 177 | + (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 178 | + | ||
| 179 | + spi_ctrl_start_user(); | ||
| 180 | + writeb(ASPEED_FLASH_BASE, WRDI); | ||
| 181 | + writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 182 | + r = readb(ASPEED_FLASH_BASE); | ||
| 183 | + spi_ctrl_stop_user(); | ||
| 184 | + | ||
| 185 | + g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 186 | + g_assert(!qtest_qom_get_bool | ||
| 187 | + (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 188 | + | ||
| 189 | + flash_reset(); | ||
| 190 | +} | 45 | +} |
| 191 | + | 46 | + |
| 192 | static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX"; | 47 | +int main(int argc, char **argv) |
| 193 | 48 | +{ | |
| 194 | int main(int argc, char **argv) | 49 | + int ret; |
| 195 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | 50 | + |
| 196 | qtest_add_func("/ast2400/smc/write_page", test_write_page); | 51 | + g_test_init(&argc, &argv, NULL); |
| 197 | qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem); | 52 | + ret = test_palmetto_bmc(); |
| 198 | qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem); | 53 | + |
| 199 | + qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg); | 54 | return ret; |
| 200 | |||
| 201 | ret = g_test_run(); | ||
| 202 | |||
| 203 | diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c | ||
| 204 | index XXXXXXX..XXXXXXX 100644 | ||
| 205 | --- a/tests/qtest/libqtest.c | ||
| 206 | +++ b/tests/qtest/libqtest.c | ||
| 207 | @@ -XXX,XX +XXX,XX @@ void qtest_client_inproc_recv(void *opaque, const char *str) | ||
| 208 | g_string_append(qts->rx, str); | ||
| 209 | return; | ||
| 210 | } | 55 | } |
| 211 | + | ||
| 212 | +void qtest_qom_set_bool(QTestState *s, const char *path, const char *property, | ||
| 213 | + bool value) | ||
| 214 | +{ | ||
| 215 | + QDict *r; | ||
| 216 | + | ||
| 217 | + r = qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': " | ||
| 218 | + "{ 'path': %s, 'property': %s, 'value': %i } }", | ||
| 219 | + path, property, value); | ||
| 220 | + qobject_unref(r); | ||
| 221 | +} | ||
| 222 | + | ||
| 223 | +bool qtest_qom_get_bool(QTestState *s, const char *path, const char *property) | ||
| 224 | +{ | ||
| 225 | + QDict *r; | ||
| 226 | + bool b; | ||
| 227 | + | ||
| 228 | + r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': " | ||
| 229 | + "{ 'path': %s, 'property': %s } }", path, property); | ||
| 230 | + b = qdict_get_bool(r, "return"); | ||
| 231 | + qobject_unref(r); | ||
| 232 | + | ||
| 233 | + return b; | ||
| 234 | +} | ||
| 235 | -- | 56 | -- |
| 236 | 2.35.3 | 57 | 2.47.1 |
| 237 | 58 | ||
| 238 | 59 | diff view generated by jsdifflib |
| 1 | From: Peter Delevoryas <pdel@fb.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace | 3 | Currently, these test cases are only used for testing fmc_cs0 for AST2400. |
| 4 | i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB. | 4 | To test others BMC SOCs, introduces a new TestData structure. |
| 5 | Users can set the spi base address, flash base address, jedesc id and so on | ||
| 6 | for different BMC SOCs and flash model testing. | ||
| 5 | 7 | ||
| 6 | Reference images can be found in Facebook OpenBMC Github Release assets | 8 | Introduce new helper functions to make the test case more readable. |
| 7 | as "fby35.mtd". [3] | ||
| 8 | 9 | ||
| 9 | You can boot the reference images as follows (fby35 uses dual-flash): | 10 | Set spi base address 0x1E620000, flash_base address 0x20000000 |
| 11 | and jedec id 0x20ba19 for fmc_cs0 with n25q256a flash for AST2400 | ||
| 12 | SMC model testing. | ||
| 10 | 13 | ||
| 11 | qemu-system-arm -machine fby35-bmc \ | 14 | To pass the TestData into the test case, replace qtest_add_func with |
| 12 | -drive file=fby35.mtd,format=raw,if=mtd \ | 15 | qtest_add_data_func. |
| 13 | -drive file=fby35.mtd,format=raw,if=mtd \ | ||
| 14 | -nographic | ||
| 15 | 16 | ||
| 16 | [1] https://github.com/facebook/openbmc-linux/blob/412d5053258007117e94b1e36015aefc1301474b/arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts | 17 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 17 | [2] https://github.com/facebook/openbmc/blob/e2294ff5d31dd65c248fe396a385286d6d5c463d/meta-facebook/meta-fby35/recipes-fby35/plat-utils/files/setup-dev.sh | 18 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 18 | [3] https://github.com/facebook/openbmc/releases | 19 | Link: https://lore.kernel.org/r/20241127091543.1243114-3-jamin_lin@aspeedtech.com |
| 20 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 21 | --- | ||
| 22 | tests/qtest/aspeed_smc-test.c | 546 +++++++++++++++++++--------------- | ||
| 23 | 1 file changed, 299 insertions(+), 247 deletions(-) | ||
| 19 | 24 | ||
| 20 | Signed-off-by: Peter Delevoryas <pdel@fb.com> | 25 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c |
| 21 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
| 22 | Message-Id: <20220503225925.1798324-2-pdel@fb.com> | ||
| 23 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 24 | --- | ||
| 25 | hw/arm/aspeed.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++ | ||
| 26 | 1 file changed, 63 insertions(+) | ||
| 27 | |||
| 28 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
| 30 | --- a/hw/arm/aspeed.c | 27 | --- a/tests/qtest/aspeed_smc-test.c |
| 31 | +++ b/hw/arm/aspeed.c | 28 | +++ b/tests/qtest/aspeed_smc-test.c |
| 32 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ |
| 33 | #include "hw/misc/led.h" | 30 | #define CTRL_USERMODE 0x3 |
| 34 | #include "hw/qdev-properties.h" | 31 | #define SR_WEL BIT(1) |
| 35 | #include "sysemu/block-backend.h" | 32 | |
| 36 | +#include "sysemu/reset.h" | 33 | -#define ASPEED_FMC_BASE 0x1E620000 |
| 37 | #include "hw/loader.h" | 34 | -#define ASPEED_FLASH_BASE 0x20000000 |
| 38 | #include "qemu/error-report.h" | 35 | - |
| 39 | #include "qemu/units.h" | 36 | /* |
| 40 | @@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) | 37 | * Flash commands |
| 41 | i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); | 38 | */ |
| 42 | } | 39 | @@ -XXX,XX +XXX,XX @@ enum { |
| 43 | 40 | ERASE_SECTOR = 0xd8, | |
| 44 | +static void fby35_i2c_init(AspeedMachineState *bmc) | 41 | }; |
| 42 | |||
| 43 | -#define FLASH_JEDEC 0x20ba19 /* n25q256a */ | ||
| 44 | -#define FLASH_SIZE (32 * 1024 * 1024) | ||
| 45 | - | ||
| 46 | #define FLASH_PAGE_SIZE 256 | ||
| 47 | |||
| 48 | +typedef struct TestData { | ||
| 49 | + QTestState *s; | ||
| 50 | + uint64_t spi_base; | ||
| 51 | + uint64_t flash_base; | ||
| 52 | + uint32_t jedec_id; | ||
| 53 | + char *tmp_path; | ||
| 54 | +} TestData; | ||
| 55 | + | ||
| 56 | /* | ||
| 57 | * Use an explicit bswap for the values read/wrote to the flash region | ||
| 58 | * as they are BE and the Aspeed CPU is LE. | ||
| 59 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t make_be32(uint32_t data) | ||
| 60 | return bswap32(data); | ||
| 61 | } | ||
| 62 | |||
| 63 | -static void spi_conf(uint32_t value) | ||
| 64 | +static inline void spi_writel(const TestData *data, uint64_t offset, | ||
| 65 | + uint32_t value) | ||
| 45 | +{ | 66 | +{ |
| 46 | + AspeedSoCState *soc = &bmc->soc; | 67 | + qtest_writel(data->s, data->spi_base + offset, value); |
| 47 | + I2CBus *i2c[16]; | ||
| 48 | + | ||
| 49 | + for (int i = 0; i < 16; i++) { | ||
| 50 | + i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); | ||
| 51 | + } | ||
| 52 | + | ||
| 53 | + i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); | ||
| 54 | + i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); | ||
| 55 | + /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ | ||
| 56 | + i2c_slave_create_simple(i2c[11], "adm1272", 0x44); | ||
| 57 | + i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); | ||
| 58 | + i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); | ||
| 59 | + | ||
| 60 | + aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB); | ||
| 61 | + aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB); | ||
| 62 | + aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB); | ||
| 63 | + aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB); | ||
| 64 | + aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB); | ||
| 65 | + | ||
| 66 | + /* | ||
| 67 | + * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on | ||
| 68 | + * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on | ||
| 69 | + * each. | ||
| 70 | + */ | ||
| 71 | +} | 68 | +} |
| 72 | + | 69 | + |
| 73 | static bool aspeed_get_mmio_exec(Object *obj, Error **errp) | 70 | +static inline uint32_t spi_readl(const TestData *data, uint64_t offset) |
| 74 | { | ||
| 75 | return ASPEED_MACHINE(obj)->mmio_exec; | ||
| 76 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) | ||
| 77 | aspeed_soc_num_cpus(amc->soc_name); | ||
| 78 | } | ||
| 79 | |||
| 80 | +static void fby35_reset(MachineState *state) | ||
| 81 | +{ | 71 | +{ |
| 82 | + AspeedMachineState *bmc = ASPEED_MACHINE(state); | 72 | + return qtest_readl(data->s, data->spi_base + offset); |
| 83 | + AspeedGPIOState *gpio = &bmc->soc.gpio; | ||
| 84 | + | ||
| 85 | + qemu_devices_reset(); | ||
| 86 | + | ||
| 87 | + /* Board ID */ | ||
| 88 | + object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); | ||
| 89 | + object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); | ||
| 90 | + object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); | ||
| 91 | + object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); | ||
| 92 | +} | 73 | +} |
| 93 | + | 74 | + |
| 94 | +static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) | 75 | +static inline void flash_writeb(const TestData *data, uint64_t offset, |
| 76 | + uint8_t value) | ||
| 95 | +{ | 77 | +{ |
| 96 | + MachineClass *mc = MACHINE_CLASS(oc); | 78 | + qtest_writeb(data->s, data->flash_base + offset, value); |
| 97 | + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | ||
| 98 | + | ||
| 99 | + mc->desc = "Facebook fby35 BMC (Cortex-A7)"; | ||
| 100 | + mc->reset = fby35_reset; | ||
| 101 | + amc->fmc_model = "mx66l1g45g"; | ||
| 102 | + amc->num_cs = 2; | ||
| 103 | + amc->macs_mask = ASPEED_MAC3_ON; | ||
| 104 | + amc->i2c_init = fby35_i2c_init; | ||
| 105 | + /* FIXME: Replace this macro with something more general */ | ||
| 106 | + mc->default_ram_size = FUJI_BMC_RAM_SIZE; | ||
| 107 | +} | 79 | +} |
| 108 | + | 80 | + |
| 109 | #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) | 81 | +static inline void flash_writel(const TestData *data, uint64_t offset, |
| 110 | /* Main SYSCLK frequency in Hz (200MHz) */ | 82 | + uint32_t value) |
| 111 | #define SYSCLK_FRQ 200000000ULL | 83 | +{ |
| 112 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { | 84 | + qtest_writel(data->s, data->flash_base + offset, value); |
| 113 | .name = MACHINE_TYPE_NAME("bletchley-bmc"), | 85 | +} |
| 114 | .parent = TYPE_ASPEED_MACHINE, | 86 | + |
| 115 | .class_init = aspeed_machine_bletchley_class_init, | 87 | +static inline uint8_t flash_readb(const TestData *data, uint64_t offset) |
| 116 | + }, { | 88 | { |
| 117 | + .name = MACHINE_TYPE_NAME("fby35-bmc"), | 89 | - uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF); |
| 118 | + .parent = MACHINE_TYPE_NAME("ast2600-evb"), | 90 | + return qtest_readb(data->s, data->flash_base + offset); |
| 119 | + .class_init = aspeed_machine_fby35_class_init, | 91 | +} |
| 120 | }, { | 92 | + |
| 121 | .name = MACHINE_TYPE_NAME("ast1030-evb"), | 93 | +static inline uint32_t flash_readl(const TestData *data, uint64_t offset) |
| 122 | .parent = TYPE_ASPEED_MACHINE, | 94 | +{ |
| 95 | + return qtest_readl(data->s, data->flash_base + offset); | ||
| 96 | +} | ||
| 97 | + | ||
| 98 | +static void spi_conf(const TestData *data, uint32_t value) | ||
| 99 | +{ | ||
| 100 | + uint32_t conf = spi_readl(data, R_CONF); | ||
| 101 | |||
| 102 | conf |= value; | ||
| 103 | - writel(ASPEED_FMC_BASE + R_CONF, conf); | ||
| 104 | + spi_writel(data, R_CONF, conf); | ||
| 105 | } | ||
| 106 | |||
| 107 | -static void spi_conf_remove(uint32_t value) | ||
| 108 | +static void spi_conf_remove(const TestData *data, uint32_t value) | ||
| 109 | { | ||
| 110 | - uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF); | ||
| 111 | + uint32_t conf = spi_readl(data, R_CONF); | ||
| 112 | |||
| 113 | conf &= ~value; | ||
| 114 | - writel(ASPEED_FMC_BASE + R_CONF, conf); | ||
| 115 | + spi_writel(data, R_CONF, conf); | ||
| 116 | } | ||
| 117 | |||
| 118 | -static void spi_ce_ctrl(uint32_t value) | ||
| 119 | +static void spi_ce_ctrl(const TestData *data, uint32_t value) | ||
| 120 | { | ||
| 121 | - uint32_t conf = readl(ASPEED_FMC_BASE + R_CE_CTRL); | ||
| 122 | + uint32_t conf = spi_readl(data, R_CE_CTRL); | ||
| 123 | |||
| 124 | conf |= value; | ||
| 125 | - writel(ASPEED_FMC_BASE + R_CE_CTRL, conf); | ||
| 126 | + spi_writel(data, R_CE_CTRL, conf); | ||
| 127 | } | ||
| 128 | |||
| 129 | -static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd) | ||
| 130 | +static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd) | ||
| 131 | { | ||
| 132 | - uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); | ||
| 133 | + uint32_t ctrl = spi_readl(data, R_CTRL0); | ||
| 134 | ctrl &= ~(CTRL_USERMODE | 0xff << 16); | ||
| 135 | ctrl |= mode | (cmd << 16); | ||
| 136 | - writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); | ||
| 137 | + spi_writel(data, R_CTRL0, ctrl); | ||
| 138 | } | ||
| 139 | |||
| 140 | -static void spi_ctrl_start_user(void) | ||
| 141 | +static void spi_ctrl_start_user(const TestData *data) | ||
| 142 | { | ||
| 143 | - uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); | ||
| 144 | + uint32_t ctrl = spi_readl(data, R_CTRL0); | ||
| 145 | |||
| 146 | ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; | ||
| 147 | - writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); | ||
| 148 | + spi_writel(data, R_CTRL0, ctrl); | ||
| 149 | |||
| 150 | ctrl &= ~CTRL_CE_STOP_ACTIVE; | ||
| 151 | - writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); | ||
| 152 | + spi_writel(data, R_CTRL0, ctrl); | ||
| 153 | } | ||
| 154 | |||
| 155 | -static void spi_ctrl_stop_user(void) | ||
| 156 | +static void spi_ctrl_stop_user(const TestData *data) | ||
| 157 | { | ||
| 158 | - uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); | ||
| 159 | + uint32_t ctrl = spi_readl(data, R_CTRL0); | ||
| 160 | |||
| 161 | ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; | ||
| 162 | - writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); | ||
| 163 | + spi_writel(data, R_CTRL0, ctrl); | ||
| 164 | } | ||
| 165 | |||
| 166 | -static void flash_reset(void) | ||
| 167 | +static void flash_reset(const TestData *data) | ||
| 168 | { | ||
| 169 | - spi_conf(CONF_ENABLE_W0); | ||
| 170 | + spi_conf(data, CONF_ENABLE_W0); | ||
| 171 | |||
| 172 | - spi_ctrl_start_user(); | ||
| 173 | - writeb(ASPEED_FLASH_BASE, RESET_ENABLE); | ||
| 174 | - writeb(ASPEED_FLASH_BASE, RESET_MEMORY); | ||
| 175 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 176 | - writeb(ASPEED_FLASH_BASE, BULK_ERASE); | ||
| 177 | - writeb(ASPEED_FLASH_BASE, WRDI); | ||
| 178 | - spi_ctrl_stop_user(); | ||
| 179 | + spi_ctrl_start_user(data); | ||
| 180 | + flash_writeb(data, 0, RESET_ENABLE); | ||
| 181 | + flash_writeb(data, 0, RESET_MEMORY); | ||
| 182 | + flash_writeb(data, 0, WREN); | ||
| 183 | + flash_writeb(data, 0, BULK_ERASE); | ||
| 184 | + flash_writeb(data, 0, WRDI); | ||
| 185 | + spi_ctrl_stop_user(data); | ||
| 186 | |||
| 187 | - spi_conf_remove(CONF_ENABLE_W0); | ||
| 188 | + spi_conf_remove(data, CONF_ENABLE_W0); | ||
| 189 | } | ||
| 190 | |||
| 191 | -static void test_read_jedec(void) | ||
| 192 | +static void test_read_jedec(const void *data) | ||
| 193 | { | ||
| 194 | + const TestData *test_data = (const TestData *)data; | ||
| 195 | uint32_t jedec = 0x0; | ||
| 196 | |||
| 197 | - spi_conf(CONF_ENABLE_W0); | ||
| 198 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 199 | |||
| 200 | - spi_ctrl_start_user(); | ||
| 201 | - writeb(ASPEED_FLASH_BASE, JEDEC_READ); | ||
| 202 | - jedec |= readb(ASPEED_FLASH_BASE) << 16; | ||
| 203 | - jedec |= readb(ASPEED_FLASH_BASE) << 8; | ||
| 204 | - jedec |= readb(ASPEED_FLASH_BASE); | ||
| 205 | - spi_ctrl_stop_user(); | ||
| 206 | + spi_ctrl_start_user(test_data); | ||
| 207 | + flash_writeb(test_data, 0, JEDEC_READ); | ||
| 208 | + jedec |= flash_readb(test_data, 0) << 16; | ||
| 209 | + jedec |= flash_readb(test_data, 0) << 8; | ||
| 210 | + jedec |= flash_readb(test_data, 0); | ||
| 211 | + spi_ctrl_stop_user(test_data); | ||
| 212 | |||
| 213 | - flash_reset(); | ||
| 214 | + flash_reset(test_data); | ||
| 215 | |||
| 216 | - g_assert_cmphex(jedec, ==, FLASH_JEDEC); | ||
| 217 | + g_assert_cmphex(jedec, ==, test_data->jedec_id); | ||
| 218 | } | ||
| 219 | |||
| 220 | -static void read_page(uint32_t addr, uint32_t *page) | ||
| 221 | +static void read_page(const TestData *data, uint32_t addr, uint32_t *page) | ||
| 222 | { | ||
| 223 | int i; | ||
| 224 | |||
| 225 | - spi_ctrl_start_user(); | ||
| 226 | + spi_ctrl_start_user(data); | ||
| 227 | |||
| 228 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 229 | - writeb(ASPEED_FLASH_BASE, READ); | ||
| 230 | - writel(ASPEED_FLASH_BASE, make_be32(addr)); | ||
| 231 | + flash_writeb(data, 0, EN_4BYTE_ADDR); | ||
| 232 | + flash_writeb(data, 0, READ); | ||
| 233 | + flash_writel(data, 0, make_be32(addr)); | ||
| 234 | |||
| 235 | /* Continuous read are supported */ | ||
| 236 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 237 | - page[i] = make_be32(readl(ASPEED_FLASH_BASE)); | ||
| 238 | + page[i] = make_be32(flash_readl(data, 0)); | ||
| 239 | } | ||
| 240 | - spi_ctrl_stop_user(); | ||
| 241 | + spi_ctrl_stop_user(data); | ||
| 242 | } | ||
| 243 | |||
| 244 | -static void read_page_mem(uint32_t addr, uint32_t *page) | ||
| 245 | +static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *page) | ||
| 246 | { | ||
| 247 | int i; | ||
| 248 | |||
| 249 | /* move out USER mode to use direct reads from the AHB bus */ | ||
| 250 | - spi_ctrl_setmode(CTRL_READMODE, READ); | ||
| 251 | + spi_ctrl_setmode(data, CTRL_READMODE, READ); | ||
| 252 | |||
| 253 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 254 | - page[i] = make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4)); | ||
| 255 | + page[i] = make_be32(flash_readl(data, addr + i * 4)); | ||
| 256 | } | ||
| 257 | } | ||
| 258 | |||
| 259 | -static void write_page_mem(uint32_t addr, uint32_t write_value) | ||
| 260 | +static void write_page_mem(const TestData *data, uint32_t addr, | ||
| 261 | + uint32_t write_value) | ||
| 262 | { | ||
| 263 | - spi_ctrl_setmode(CTRL_WRITEMODE, PP); | ||
| 264 | + spi_ctrl_setmode(data, CTRL_WRITEMODE, PP); | ||
| 265 | |||
| 266 | for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 267 | - writel(ASPEED_FLASH_BASE + addr + i * 4, write_value); | ||
| 268 | + flash_writel(data, addr + i * 4, write_value); | ||
| 269 | } | ||
| 270 | } | ||
| 271 | |||
| 272 | -static void assert_page_mem(uint32_t addr, uint32_t expected_value) | ||
| 273 | +static void assert_page_mem(const TestData *data, uint32_t addr, | ||
| 274 | + uint32_t expected_value) | ||
| 275 | { | ||
| 276 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 277 | - read_page_mem(addr, page); | ||
| 278 | + read_page_mem(data, addr, page); | ||
| 279 | for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 280 | g_assert_cmphex(page[i], ==, expected_value); | ||
| 281 | } | ||
| 282 | } | ||
| 283 | |||
| 284 | -static void test_erase_sector(void) | ||
| 285 | +static void test_erase_sector(const void *data) | ||
| 286 | { | ||
| 287 | + const TestData *test_data = (const TestData *)data; | ||
| 288 | uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE; | ||
| 289 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 290 | int i; | ||
| 291 | |||
| 292 | - spi_conf(CONF_ENABLE_W0); | ||
| 293 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 294 | |||
| 295 | /* | ||
| 296 | * Previous page should be full of 0xffs after backend is | ||
| 297 | * initialized | ||
| 298 | */ | ||
| 299 | - read_page(some_page_addr - FLASH_PAGE_SIZE, page); | ||
| 300 | + read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); | ||
| 301 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 302 | g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 303 | } | ||
| 304 | |||
| 305 | - spi_ctrl_start_user(); | ||
| 306 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 307 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 308 | - writeb(ASPEED_FLASH_BASE, PP); | ||
| 309 | - writel(ASPEED_FLASH_BASE, make_be32(some_page_addr)); | ||
| 310 | + spi_ctrl_start_user(test_data); | ||
| 311 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 312 | + flash_writeb(test_data, 0, WREN); | ||
| 313 | + flash_writeb(test_data, 0, PP); | ||
| 314 | + flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 315 | |||
| 316 | /* Fill the page with its own addresses */ | ||
| 317 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 318 | - writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4)); | ||
| 319 | + flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); | ||
| 320 | } | ||
| 321 | - spi_ctrl_stop_user(); | ||
| 322 | + spi_ctrl_stop_user(test_data); | ||
| 323 | |||
| 324 | /* Check the page is correctly written */ | ||
| 325 | - read_page(some_page_addr, page); | ||
| 326 | + read_page(test_data, some_page_addr, page); | ||
| 327 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 328 | g_assert_cmphex(page[i], ==, some_page_addr + i * 4); | ||
| 329 | } | ||
| 330 | |||
| 331 | - spi_ctrl_start_user(); | ||
| 332 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 333 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 334 | - writeb(ASPEED_FLASH_BASE, ERASE_SECTOR); | ||
| 335 | - writel(ASPEED_FLASH_BASE, make_be32(some_page_addr)); | ||
| 336 | - spi_ctrl_stop_user(); | ||
| 337 | + spi_ctrl_start_user(test_data); | ||
| 338 | + flash_writeb(test_data, 0, WREN); | ||
| 339 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 340 | + flash_writeb(test_data, 0, ERASE_SECTOR); | ||
| 341 | + flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 342 | + spi_ctrl_stop_user(test_data); | ||
| 343 | |||
| 344 | /* Check the page is erased */ | ||
| 345 | - read_page(some_page_addr, page); | ||
| 346 | + read_page(test_data, some_page_addr, page); | ||
| 347 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 348 | g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 349 | } | ||
| 350 | |||
| 351 | - flash_reset(); | ||
| 352 | + flash_reset(test_data); | ||
| 353 | } | ||
| 354 | |||
| 355 | -static void test_erase_all(void) | ||
| 356 | +static void test_erase_all(const void *data) | ||
| 357 | { | ||
| 358 | + const TestData *test_data = (const TestData *)data; | ||
| 359 | uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; | ||
| 360 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 361 | int i; | ||
| 362 | |||
| 363 | - spi_conf(CONF_ENABLE_W0); | ||
| 364 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 365 | |||
| 366 | /* | ||
| 367 | * Previous page should be full of 0xffs after backend is | ||
| 368 | * initialized | ||
| 369 | */ | ||
| 370 | - read_page(some_page_addr - FLASH_PAGE_SIZE, page); | ||
| 371 | + read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); | ||
| 372 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 373 | g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 374 | } | ||
| 375 | |||
| 376 | - spi_ctrl_start_user(); | ||
| 377 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 378 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 379 | - writeb(ASPEED_FLASH_BASE, PP); | ||
| 380 | - writel(ASPEED_FLASH_BASE, make_be32(some_page_addr)); | ||
| 381 | + spi_ctrl_start_user(test_data); | ||
| 382 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 383 | + flash_writeb(test_data, 0, WREN); | ||
| 384 | + flash_writeb(test_data, 0, PP); | ||
| 385 | + flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 386 | |||
| 387 | /* Fill the page with its own addresses */ | ||
| 388 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 389 | - writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4)); | ||
| 390 | + flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); | ||
| 391 | } | ||
| 392 | - spi_ctrl_stop_user(); | ||
| 393 | + spi_ctrl_stop_user(test_data); | ||
| 394 | |||
| 395 | /* Check the page is correctly written */ | ||
| 396 | - read_page(some_page_addr, page); | ||
| 397 | + read_page(test_data, some_page_addr, page); | ||
| 398 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 399 | g_assert_cmphex(page[i], ==, some_page_addr + i * 4); | ||
| 400 | } | ||
| 401 | |||
| 402 | - spi_ctrl_start_user(); | ||
| 403 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 404 | - writeb(ASPEED_FLASH_BASE, BULK_ERASE); | ||
| 405 | - spi_ctrl_stop_user(); | ||
| 406 | + spi_ctrl_start_user(test_data); | ||
| 407 | + flash_writeb(test_data, 0, WREN); | ||
| 408 | + flash_writeb(test_data, 0, BULK_ERASE); | ||
| 409 | + spi_ctrl_stop_user(test_data); | ||
| 410 | |||
| 411 | /* Check the page is erased */ | ||
| 412 | - read_page(some_page_addr, page); | ||
| 413 | + read_page(test_data, some_page_addr, page); | ||
| 414 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 415 | g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 416 | } | ||
| 417 | |||
| 418 | - flash_reset(); | ||
| 419 | + flash_reset(test_data); | ||
| 420 | } | ||
| 421 | |||
| 422 | -static void test_write_page(void) | ||
| 423 | +static void test_write_page(const void *data) | ||
| 424 | { | ||
| 425 | + const TestData *test_data = (const TestData *)data; | ||
| 426 | uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */ | ||
| 427 | uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; | ||
| 428 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 429 | int i; | ||
| 430 | |||
| 431 | - spi_conf(CONF_ENABLE_W0); | ||
| 432 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 433 | |||
| 434 | - spi_ctrl_start_user(); | ||
| 435 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 436 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 437 | - writeb(ASPEED_FLASH_BASE, PP); | ||
| 438 | - writel(ASPEED_FLASH_BASE, make_be32(my_page_addr)); | ||
| 439 | + spi_ctrl_start_user(test_data); | ||
| 440 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 441 | + flash_writeb(test_data, 0, WREN); | ||
| 442 | + flash_writeb(test_data, 0, PP); | ||
| 443 | + flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 444 | |||
| 445 | /* Fill the page with its own addresses */ | ||
| 446 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 447 | - writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4)); | ||
| 448 | + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 449 | } | ||
| 450 | - spi_ctrl_stop_user(); | ||
| 451 | + spi_ctrl_stop_user(test_data); | ||
| 452 | |||
| 453 | /* Check what was written */ | ||
| 454 | - read_page(my_page_addr, page); | ||
| 455 | + read_page(test_data, my_page_addr, page); | ||
| 456 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 457 | g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 458 | } | ||
| 459 | |||
| 460 | /* Check some other page. It should be full of 0xff */ | ||
| 461 | - read_page(some_page_addr, page); | ||
| 462 | + read_page(test_data, some_page_addr, page); | ||
| 463 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 464 | g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 465 | } | ||
| 466 | |||
| 467 | - flash_reset(); | ||
| 468 | + flash_reset(test_data); | ||
| 469 | } | ||
| 470 | |||
| 471 | -static void test_read_page_mem(void) | ||
| 472 | +static void test_read_page_mem(const void *data) | ||
| 473 | { | ||
| 474 | + const TestData *test_data = (const TestData *)data; | ||
| 475 | uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */ | ||
| 476 | uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; | ||
| 477 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 478 | @@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(void) | ||
| 479 | * Enable 4BYTE mode for controller. This is should be strapped by | ||
| 480 | * HW for CE0 anyhow. | ||
| 481 | */ | ||
| 482 | - spi_ce_ctrl(1 << CRTL_EXTENDED0); | ||
| 483 | + spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0); | ||
| 484 | |||
| 485 | /* Enable 4BYTE mode for flash. */ | ||
| 486 | - spi_conf(CONF_ENABLE_W0); | ||
| 487 | - spi_ctrl_start_user(); | ||
| 488 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 489 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 490 | - writeb(ASPEED_FLASH_BASE, PP); | ||
| 491 | - writel(ASPEED_FLASH_BASE, make_be32(my_page_addr)); | ||
| 492 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 493 | + spi_ctrl_start_user(test_data); | ||
| 494 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 495 | + flash_writeb(test_data, 0, WREN); | ||
| 496 | + flash_writeb(test_data, 0, PP); | ||
| 497 | + flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 498 | |||
| 499 | /* Fill the page with its own addresses */ | ||
| 500 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 501 | - writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4)); | ||
| 502 | + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 503 | } | ||
| 504 | - spi_ctrl_stop_user(); | ||
| 505 | - spi_conf_remove(CONF_ENABLE_W0); | ||
| 506 | + spi_ctrl_stop_user(test_data); | ||
| 507 | + spi_conf_remove(test_data, CONF_ENABLE_W0); | ||
| 508 | |||
| 509 | /* Check what was written */ | ||
| 510 | - read_page_mem(my_page_addr, page); | ||
| 511 | + read_page_mem(test_data, my_page_addr, page); | ||
| 512 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 513 | g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 514 | } | ||
| 515 | |||
| 516 | /* Check some other page. It should be full of 0xff */ | ||
| 517 | - read_page_mem(some_page_addr, page); | ||
| 518 | + read_page_mem(test_data, some_page_addr, page); | ||
| 519 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 520 | g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 521 | } | ||
| 522 | |||
| 523 | - flash_reset(); | ||
| 524 | + flash_reset(test_data); | ||
| 525 | } | ||
| 526 | |||
| 527 | -static void test_write_page_mem(void) | ||
| 528 | +static void test_write_page_mem(const void *data) | ||
| 529 | { | ||
| 530 | + const TestData *test_data = (const TestData *)data; | ||
| 531 | uint32_t my_page_addr = 0x15000 * FLASH_PAGE_SIZE; | ||
| 532 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 533 | int i; | ||
| 534 | @@ -XXX,XX +XXX,XX @@ static void test_write_page_mem(void) | ||
| 535 | * Enable 4BYTE mode for controller. This is should be strapped by | ||
| 536 | * HW for CE0 anyhow. | ||
| 537 | */ | ||
| 538 | - spi_ce_ctrl(1 << CRTL_EXTENDED0); | ||
| 539 | + spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0); | ||
| 540 | |||
| 541 | /* Enable 4BYTE mode for flash. */ | ||
| 542 | - spi_conf(CONF_ENABLE_W0); | ||
| 543 | - spi_ctrl_start_user(); | ||
| 544 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 545 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 546 | - spi_ctrl_stop_user(); | ||
| 547 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 548 | + spi_ctrl_start_user(test_data); | ||
| 549 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 550 | + flash_writeb(test_data, 0, WREN); | ||
| 551 | + spi_ctrl_stop_user(test_data); | ||
| 552 | |||
| 553 | /* move out USER mode to use direct writes to the AHB bus */ | ||
| 554 | - spi_ctrl_setmode(CTRL_WRITEMODE, PP); | ||
| 555 | + spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP); | ||
| 556 | |||
| 557 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 558 | - writel(ASPEED_FLASH_BASE + my_page_addr + i * 4, | ||
| 559 | + flash_writel(test_data, my_page_addr + i * 4, | ||
| 560 | make_be32(my_page_addr + i * 4)); | ||
| 561 | } | ||
| 562 | |||
| 563 | /* Check what was written */ | ||
| 564 | - read_page_mem(my_page_addr, page); | ||
| 565 | + read_page_mem(test_data, my_page_addr, page); | ||
| 566 | for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 567 | g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 568 | } | ||
| 569 | |||
| 570 | - flash_reset(); | ||
| 571 | + flash_reset(test_data); | ||
| 572 | } | ||
| 573 | |||
| 574 | -static void test_read_status_reg(void) | ||
| 575 | +static void test_read_status_reg(const void *data) | ||
| 576 | { | ||
| 577 | + const TestData *test_data = (const TestData *)data; | ||
| 578 | uint8_t r; | ||
| 579 | |||
| 580 | - spi_conf(CONF_ENABLE_W0); | ||
| 581 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 582 | |||
| 583 | - spi_ctrl_start_user(); | ||
| 584 | - writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 585 | - r = readb(ASPEED_FLASH_BASE); | ||
| 586 | - spi_ctrl_stop_user(); | ||
| 587 | + spi_ctrl_start_user(test_data); | ||
| 588 | + flash_writeb(test_data, 0, RDSR); | ||
| 589 | + r = flash_readb(test_data, 0); | ||
| 590 | + spi_ctrl_stop_user(test_data); | ||
| 591 | |||
| 592 | g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 593 | g_assert(!qtest_qom_get_bool | ||
| 594 | - (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 595 | + (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 596 | |||
| 597 | - spi_ctrl_start_user(); | ||
| 598 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 599 | - writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 600 | - r = readb(ASPEED_FLASH_BASE); | ||
| 601 | - spi_ctrl_stop_user(); | ||
| 602 | + spi_ctrl_start_user(test_data); | ||
| 603 | + flash_writeb(test_data, 0, WREN); | ||
| 604 | + flash_writeb(test_data, 0, RDSR); | ||
| 605 | + r = flash_readb(test_data, 0); | ||
| 606 | + spi_ctrl_stop_user(test_data); | ||
| 607 | |||
| 608 | g_assert_cmphex(r & SR_WEL, ==, SR_WEL); | ||
| 609 | g_assert(qtest_qom_get_bool | ||
| 610 | - (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 611 | + (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 612 | |||
| 613 | - spi_ctrl_start_user(); | ||
| 614 | - writeb(ASPEED_FLASH_BASE, WRDI); | ||
| 615 | - writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 616 | - r = readb(ASPEED_FLASH_BASE); | ||
| 617 | - spi_ctrl_stop_user(); | ||
| 618 | + spi_ctrl_start_user(test_data); | ||
| 619 | + flash_writeb(test_data, 0, WRDI); | ||
| 620 | + flash_writeb(test_data, 0, RDSR); | ||
| 621 | + r = flash_readb(test_data, 0); | ||
| 622 | + spi_ctrl_stop_user(test_data); | ||
| 623 | |||
| 624 | g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 625 | g_assert(!qtest_qom_get_bool | ||
| 626 | - (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 627 | + (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 628 | |||
| 629 | - flash_reset(); | ||
| 630 | + flash_reset(test_data); | ||
| 631 | } | ||
| 632 | |||
| 633 | -static void test_status_reg_write_protection(void) | ||
| 634 | +static void test_status_reg_write_protection(const void *data) | ||
| 635 | { | ||
| 636 | + const TestData *test_data = (const TestData *)data; | ||
| 637 | uint8_t r; | ||
| 638 | |||
| 639 | - spi_conf(CONF_ENABLE_W0); | ||
| 640 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 641 | |||
| 642 | /* default case: WP# is high and SRWD is low -> status register writable */ | ||
| 643 | - spi_ctrl_start_user(); | ||
| 644 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 645 | + spi_ctrl_start_user(test_data); | ||
| 646 | + flash_writeb(test_data, 0, WREN); | ||
| 647 | /* test ability to write SRWD */ | ||
| 648 | - writeb(ASPEED_FLASH_BASE, WRSR); | ||
| 649 | - writeb(ASPEED_FLASH_BASE, SRWD); | ||
| 650 | - writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 651 | - r = readb(ASPEED_FLASH_BASE); | ||
| 652 | - spi_ctrl_stop_user(); | ||
| 653 | + flash_writeb(test_data, 0, WRSR); | ||
| 654 | + flash_writeb(test_data, 0, SRWD); | ||
| 655 | + flash_writeb(test_data, 0, RDSR); | ||
| 656 | + r = flash_readb(test_data, 0); | ||
| 657 | + spi_ctrl_stop_user(test_data); | ||
| 658 | g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 659 | |||
| 660 | /* WP# high and SRWD high -> status register writable */ | ||
| 661 | - spi_ctrl_start_user(); | ||
| 662 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 663 | + spi_ctrl_start_user(test_data); | ||
| 664 | + flash_writeb(test_data, 0, WREN); | ||
| 665 | /* test ability to write SRWD */ | ||
| 666 | - writeb(ASPEED_FLASH_BASE, WRSR); | ||
| 667 | - writeb(ASPEED_FLASH_BASE, 0); | ||
| 668 | - writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 669 | - r = readb(ASPEED_FLASH_BASE); | ||
| 670 | - spi_ctrl_stop_user(); | ||
| 671 | + flash_writeb(test_data, 0, WRSR); | ||
| 672 | + flash_writeb(test_data, 0, 0); | ||
| 673 | + flash_writeb(test_data, 0, RDSR); | ||
| 674 | + r = flash_readb(test_data, 0); | ||
| 675 | + spi_ctrl_stop_user(test_data); | ||
| 676 | g_assert_cmphex(r & SRWD, ==, 0); | ||
| 677 | |||
| 678 | /* WP# low and SRWD low -> status register writable */ | ||
| 679 | - qtest_set_irq_in(global_qtest, | ||
| 680 | + qtest_set_irq_in(test_data->s, | ||
| 681 | "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0); | ||
| 682 | - spi_ctrl_start_user(); | ||
| 683 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 684 | + spi_ctrl_start_user(test_data); | ||
| 685 | + flash_writeb(test_data, 0, WREN); | ||
| 686 | /* test ability to write SRWD */ | ||
| 687 | - writeb(ASPEED_FLASH_BASE, WRSR); | ||
| 688 | - writeb(ASPEED_FLASH_BASE, SRWD); | ||
| 689 | - writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 690 | - r = readb(ASPEED_FLASH_BASE); | ||
| 691 | - spi_ctrl_stop_user(); | ||
| 692 | + flash_writeb(test_data, 0, WRSR); | ||
| 693 | + flash_writeb(test_data, 0, SRWD); | ||
| 694 | + flash_writeb(test_data, 0, RDSR); | ||
| 695 | + r = flash_readb(test_data, 0); | ||
| 696 | + spi_ctrl_stop_user(test_data); | ||
| 697 | g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 698 | |||
| 699 | /* WP# low and SRWD high -> status register NOT writable */ | ||
| 700 | - spi_ctrl_start_user(); | ||
| 701 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 702 | + spi_ctrl_start_user(test_data); | ||
| 703 | + flash_writeb(test_data, 0 , WREN); | ||
| 704 | /* test ability to write SRWD */ | ||
| 705 | - writeb(ASPEED_FLASH_BASE, WRSR); | ||
| 706 | - writeb(ASPEED_FLASH_BASE, 0); | ||
| 707 | - writeb(ASPEED_FLASH_BASE, RDSR); | ||
| 708 | - r = readb(ASPEED_FLASH_BASE); | ||
| 709 | - spi_ctrl_stop_user(); | ||
| 710 | + flash_writeb(test_data, 0, WRSR); | ||
| 711 | + flash_writeb(test_data, 0, 0); | ||
| 712 | + flash_writeb(test_data, 0, RDSR); | ||
| 713 | + r = flash_readb(test_data, 0); | ||
| 714 | + spi_ctrl_stop_user(test_data); | ||
| 715 | /* write is not successful */ | ||
| 716 | g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 717 | |||
| 718 | - qtest_set_irq_in(global_qtest, | ||
| 719 | + qtest_set_irq_in(test_data->s, | ||
| 720 | "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1); | ||
| 721 | - flash_reset(); | ||
| 722 | + flash_reset(test_data); | ||
| 723 | } | ||
| 724 | |||
| 725 | -static void test_write_block_protect(void) | ||
| 726 | +static void test_write_block_protect(const void *data) | ||
| 727 | { | ||
| 728 | + const TestData *test_data = (const TestData *)data; | ||
| 729 | uint32_t sector_size = 65536; | ||
| 730 | uint32_t n_sectors = 512; | ||
| 731 | |||
| 732 | - spi_ce_ctrl(1 << CRTL_EXTENDED0); | ||
| 733 | - spi_conf(CONF_ENABLE_W0); | ||
| 734 | + spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0); | ||
| 735 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 736 | |||
| 737 | uint32_t bp_bits = 0b0; | ||
| 738 | |||
| 739 | for (int i = 0; i < 16; i++) { | ||
| 740 | bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2); | ||
| 741 | |||
| 742 | - spi_ctrl_start_user(); | ||
| 743 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 744 | - writeb(ASPEED_FLASH_BASE, BULK_ERASE); | ||
| 745 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 746 | - writeb(ASPEED_FLASH_BASE, WRSR); | ||
| 747 | - writeb(ASPEED_FLASH_BASE, bp_bits); | ||
| 748 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 749 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 750 | - spi_ctrl_stop_user(); | ||
| 751 | + spi_ctrl_start_user(test_data); | ||
| 752 | + flash_writeb(test_data, 0, WREN); | ||
| 753 | + flash_writeb(test_data, 0, BULK_ERASE); | ||
| 754 | + flash_writeb(test_data, 0, WREN); | ||
| 755 | + flash_writeb(test_data, 0, WRSR); | ||
| 756 | + flash_writeb(test_data, 0, bp_bits); | ||
| 757 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 758 | + flash_writeb(test_data, 0, WREN); | ||
| 759 | + spi_ctrl_stop_user(test_data); | ||
| 760 | |||
| 761 | uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0; | ||
| 762 | uint32_t protection_start = n_sectors - num_protected_sectors; | ||
| 763 | @@ -XXX,XX +XXX,XX @@ static void test_write_block_protect(void) | ||
| 764 | for (int sector = 0; sector < n_sectors; sector++) { | ||
| 765 | uint32_t addr = sector * sector_size; | ||
| 766 | |||
| 767 | - assert_page_mem(addr, 0xffffffff); | ||
| 768 | - write_page_mem(addr, make_be32(0xabcdef12)); | ||
| 769 | + assert_page_mem(test_data, addr, 0xffffffff); | ||
| 770 | + write_page_mem(test_data, addr, make_be32(0xabcdef12)); | ||
| 771 | |||
| 772 | uint32_t expected_value = protection_start <= sector | ||
| 773 | && sector < protection_end | ||
| 774 | ? 0xffffffff : 0xabcdef12; | ||
| 775 | |||
| 776 | - assert_page_mem(addr, expected_value); | ||
| 777 | + assert_page_mem(test_data, addr, expected_value); | ||
| 778 | } | ||
| 779 | } | ||
| 780 | |||
| 781 | - flash_reset(); | ||
| 782 | + flash_reset(test_data); | ||
| 783 | } | ||
| 784 | |||
| 785 | -static void test_write_block_protect_bottom_bit(void) | ||
| 786 | +static void test_write_block_protect_bottom_bit(const void *data) | ||
| 787 | { | ||
| 788 | + const TestData *test_data = (const TestData *)data; | ||
| 789 | uint32_t sector_size = 65536; | ||
| 790 | uint32_t n_sectors = 512; | ||
| 791 | |||
| 792 | - spi_ce_ctrl(1 << CRTL_EXTENDED0); | ||
| 793 | - spi_conf(CONF_ENABLE_W0); | ||
| 794 | + spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0); | ||
| 795 | + spi_conf(test_data, CONF_ENABLE_W0); | ||
| 796 | |||
| 797 | /* top bottom bit is enabled */ | ||
| 798 | uint32_t bp_bits = 0b00100 << 3; | ||
| 799 | @@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void) | ||
| 800 | for (int i = 0; i < 16; i++) { | ||
| 801 | bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2); | ||
| 802 | |||
| 803 | - spi_ctrl_start_user(); | ||
| 804 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 805 | - writeb(ASPEED_FLASH_BASE, BULK_ERASE); | ||
| 806 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 807 | - writeb(ASPEED_FLASH_BASE, WRSR); | ||
| 808 | - writeb(ASPEED_FLASH_BASE, bp_bits); | ||
| 809 | - writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); | ||
| 810 | - writeb(ASPEED_FLASH_BASE, WREN); | ||
| 811 | - spi_ctrl_stop_user(); | ||
| 812 | + spi_ctrl_start_user(test_data); | ||
| 813 | + flash_writeb(test_data, 0, WREN); | ||
| 814 | + flash_writeb(test_data, 0, BULK_ERASE); | ||
| 815 | + flash_writeb(test_data, 0, WREN); | ||
| 816 | + flash_writeb(test_data, 0, WRSR); | ||
| 817 | + flash_writeb(test_data, 0, bp_bits); | ||
| 818 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 819 | + flash_writeb(test_data, 0, WREN); | ||
| 820 | + spi_ctrl_stop_user(test_data); | ||
| 821 | |||
| 822 | uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0; | ||
| 823 | uint32_t protection_start = 0; | ||
| 824 | @@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void) | ||
| 825 | for (int sector = 0; sector < n_sectors; sector++) { | ||
| 826 | uint32_t addr = sector * sector_size; | ||
| 827 | |||
| 828 | - assert_page_mem(addr, 0xffffffff); | ||
| 829 | - write_page_mem(addr, make_be32(0xabcdef12)); | ||
| 830 | + assert_page_mem(test_data, addr, 0xffffffff); | ||
| 831 | + write_page_mem(test_data, addr, make_be32(0xabcdef12)); | ||
| 832 | |||
| 833 | uint32_t expected_value = protection_start <= sector | ||
| 834 | && sector < protection_end | ||
| 835 | ? 0xffffffff : 0xabcdef12; | ||
| 836 | |||
| 837 | - assert_page_mem(addr, expected_value); | ||
| 838 | + assert_page_mem(test_data, addr, expected_value); | ||
| 839 | } | ||
| 840 | } | ||
| 841 | |||
| 842 | - flash_reset(); | ||
| 843 | + flash_reset(test_data); | ||
| 844 | } | ||
| 845 | |||
| 846 | -static int test_palmetto_bmc(void) | ||
| 847 | +static void test_palmetto_bmc(TestData *data) | ||
| 848 | { | ||
| 849 | - g_autofree char *tmp_path = NULL; | ||
| 850 | int ret; | ||
| 851 | int fd; | ||
| 852 | |||
| 853 | - fd = g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL); | ||
| 854 | + fd = g_file_open_tmp("qtest.m25p80.n25q256a.XXXXXX", &data->tmp_path, NULL); | ||
| 855 | g_assert(fd >= 0); | ||
| 856 | - ret = ftruncate(fd, FLASH_SIZE); | ||
| 857 | + ret = ftruncate(fd, 32 * 1024 * 1024); | ||
| 858 | g_assert(ret == 0); | ||
| 859 | close(fd); | ||
| 860 | |||
| 861 | - global_qtest = qtest_initf("-m 256 -machine palmetto-bmc " | ||
| 862 | - "-drive file=%s,format=raw,if=mtd", | ||
| 863 | - tmp_path); | ||
| 864 | - | ||
| 865 | - qtest_add_func("/ast2400/smc/read_jedec", test_read_jedec); | ||
| 866 | - qtest_add_func("/ast2400/smc/erase_sector", test_erase_sector); | ||
| 867 | - qtest_add_func("/ast2400/smc/erase_all", test_erase_all); | ||
| 868 | - qtest_add_func("/ast2400/smc/write_page", test_write_page); | ||
| 869 | - qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem); | ||
| 870 | - qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem); | ||
| 871 | - qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg); | ||
| 872 | - qtest_add_func("/ast2400/smc/status_reg_write_protection", | ||
| 873 | - test_status_reg_write_protection); | ||
| 874 | - qtest_add_func("/ast2400/smc/write_block_protect", | ||
| 875 | - test_write_block_protect); | ||
| 876 | - qtest_add_func("/ast2400/smc/write_block_protect_bottom_bit", | ||
| 877 | - test_write_block_protect_bottom_bit); | ||
| 878 | - | ||
| 879 | - flash_reset(); | ||
| 880 | - ret = g_test_run(); | ||
| 881 | - qtest_quit(global_qtest); | ||
| 882 | - unlink(tmp_path); | ||
| 883 | - | ||
| 884 | - return ret; | ||
| 885 | + data->s = qtest_initf("-m 256 -machine palmetto-bmc " | ||
| 886 | + "-drive file=%s,format=raw,if=mtd", | ||
| 887 | + data->tmp_path); | ||
| 888 | + | ||
| 889 | + /* fmc cs0 with n25q256a flash */ | ||
| 890 | + data->flash_base = 0x20000000; | ||
| 891 | + data->spi_base = 0x1E620000; | ||
| 892 | + data->jedec_id = 0x20ba19; | ||
| 893 | + | ||
| 894 | + qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec); | ||
| 895 | + qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector); | ||
| 896 | + qtest_add_data_func("/ast2400/smc/erase_all", data, test_erase_all); | ||
| 897 | + qtest_add_data_func("/ast2400/smc/write_page", data, test_write_page); | ||
| 898 | + qtest_add_data_func("/ast2400/smc/read_page_mem", | ||
| 899 | + data, test_read_page_mem); | ||
| 900 | + qtest_add_data_func("/ast2400/smc/write_page_mem", | ||
| 901 | + data, test_write_page_mem); | ||
| 902 | + qtest_add_data_func("/ast2400/smc/read_status_reg", | ||
| 903 | + data, test_read_status_reg); | ||
| 904 | + qtest_add_data_func("/ast2400/smc/status_reg_write_protection", | ||
| 905 | + data, test_status_reg_write_protection); | ||
| 906 | + qtest_add_data_func("/ast2400/smc/write_block_protect", | ||
| 907 | + data, test_write_block_protect); | ||
| 908 | + qtest_add_data_func("/ast2400/smc/write_block_protect_bottom_bit", | ||
| 909 | + data, test_write_block_protect_bottom_bit); | ||
| 910 | } | ||
| 911 | |||
| 912 | int main(int argc, char **argv) | ||
| 913 | { | ||
| 914 | + TestData palmetto_data; | ||
| 915 | int ret; | ||
| 916 | |||
| 917 | g_test_init(&argc, &argv, NULL); | ||
| 918 | - ret = test_palmetto_bmc(); | ||
| 919 | |||
| 920 | + test_palmetto_bmc(&palmetto_data); | ||
| 921 | + ret = g_test_run(); | ||
| 922 | + | ||
| 923 | + qtest_quit(palmetto_data.s); | ||
| 924 | + unlink(palmetto_data.tmp_path); | ||
| 925 | return ret; | ||
| 926 | } | ||
| 123 | -- | 927 | -- |
| 124 | 2.35.3 | 928 | 2.47.1 |
| 125 | 929 | ||
| 126 | 930 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> | |
| 2 | |||
| 3 | Currently, these test cases only support to test CE0. To test all CE pins, | ||
| 4 | introduces new ce and node members in TestData structure. The ce member is used | ||
| 5 | for saving the ce index and node member is used for saving the node path, | ||
| 6 | respectively. | ||
| 7 | |||
| 8 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> | ||
| 9 | Reviewed-by: Cédric Le Goater <clg@redhat.com> | ||
| 10 | Link: https://lore.kernel.org/r/20241127091543.1243114-4-jamin_lin@aspeedtech.com | ||
| 11 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 12 | --- | ||
| 13 | tests/qtest/aspeed_smc-test.c | 77 ++++++++++++++++++----------------- | ||
| 14 | 1 file changed, 40 insertions(+), 37 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/tests/qtest/aspeed_smc-test.c | ||
| 19 | +++ b/tests/qtest/aspeed_smc-test.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | * ASPEED SPI Controller registers | ||
| 22 | */ | ||
| 23 | #define R_CONF 0x00 | ||
| 24 | -#define CONF_ENABLE_W0 (1 << 16) | ||
| 25 | +#define CONF_ENABLE_W0 16 | ||
| 26 | #define R_CE_CTRL 0x04 | ||
| 27 | #define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ | ||
| 28 | #define R_CTRL0 0x10 | ||
| 29 | -#define CTRL_CE_STOP_ACTIVE (1 << 2) | ||
| 30 | +#define CTRL_CE_STOP_ACTIVE BIT(2) | ||
| 31 | #define CTRL_READMODE 0x0 | ||
| 32 | #define CTRL_FREADMODE 0x1 | ||
| 33 | #define CTRL_WRITEMODE 0x2 | ||
| 34 | @@ -XXX,XX +XXX,XX @@ typedef struct TestData { | ||
| 35 | uint64_t flash_base; | ||
| 36 | uint32_t jedec_id; | ||
| 37 | char *tmp_path; | ||
| 38 | + uint8_t cs; | ||
| 39 | + const char *node; | ||
| 40 | } TestData; | ||
| 41 | |||
| 42 | /* | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static void spi_ce_ctrl(const TestData *data, uint32_t value) | ||
| 44 | |||
| 45 | static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd) | ||
| 46 | { | ||
| 47 | - uint32_t ctrl = spi_readl(data, R_CTRL0); | ||
| 48 | + uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 49 | + uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 50 | ctrl &= ~(CTRL_USERMODE | 0xff << 16); | ||
| 51 | ctrl |= mode | (cmd << 16); | ||
| 52 | - spi_writel(data, R_CTRL0, ctrl); | ||
| 53 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 54 | } | ||
| 55 | |||
| 56 | static void spi_ctrl_start_user(const TestData *data) | ||
| 57 | { | ||
| 58 | - uint32_t ctrl = spi_readl(data, R_CTRL0); | ||
| 59 | + uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 60 | + uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 61 | |||
| 62 | ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; | ||
| 63 | - spi_writel(data, R_CTRL0, ctrl); | ||
| 64 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 65 | |||
| 66 | ctrl &= ~CTRL_CE_STOP_ACTIVE; | ||
| 67 | - spi_writel(data, R_CTRL0, ctrl); | ||
| 68 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 69 | } | ||
| 70 | |||
| 71 | static void spi_ctrl_stop_user(const TestData *data) | ||
| 72 | { | ||
| 73 | - uint32_t ctrl = spi_readl(data, R_CTRL0); | ||
| 74 | + uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 75 | + uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 76 | |||
| 77 | ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; | ||
| 78 | - spi_writel(data, R_CTRL0, ctrl); | ||
| 79 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 80 | } | ||
| 81 | |||
| 82 | static void flash_reset(const TestData *data) | ||
| 83 | { | ||
| 84 | - spi_conf(data, CONF_ENABLE_W0); | ||
| 85 | + spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs)); | ||
| 86 | |||
| 87 | spi_ctrl_start_user(data); | ||
| 88 | flash_writeb(data, 0, RESET_ENABLE); | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static void flash_reset(const TestData *data) | ||
| 90 | flash_writeb(data, 0, WRDI); | ||
| 91 | spi_ctrl_stop_user(data); | ||
| 92 | |||
| 93 | - spi_conf_remove(data, CONF_ENABLE_W0); | ||
| 94 | + spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs)); | ||
| 95 | } | ||
| 96 | |||
| 97 | static void test_read_jedec(const void *data) | ||
| 98 | @@ -XXX,XX +XXX,XX @@ static void test_read_jedec(const void *data) | ||
| 99 | const TestData *test_data = (const TestData *)data; | ||
| 100 | uint32_t jedec = 0x0; | ||
| 101 | |||
| 102 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 103 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 104 | |||
| 105 | spi_ctrl_start_user(test_data); | ||
| 106 | flash_writeb(test_data, 0, JEDEC_READ); | ||
| 107 | @@ -XXX,XX +XXX,XX @@ static void test_erase_sector(const void *data) | ||
| 108 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 109 | int i; | ||
| 110 | |||
| 111 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 112 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Previous page should be full of 0xffs after backend is | ||
| 116 | @@ -XXX,XX +XXX,XX @@ static void test_erase_all(const void *data) | ||
| 117 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 118 | int i; | ||
| 119 | |||
| 120 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 121 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 122 | |||
| 123 | /* | ||
| 124 | * Previous page should be full of 0xffs after backend is | ||
| 125 | @@ -XXX,XX +XXX,XX @@ static void test_write_page(const void *data) | ||
| 126 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 127 | int i; | ||
| 128 | |||
| 129 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 130 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 131 | |||
| 132 | spi_ctrl_start_user(test_data); | ||
| 133 | flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 134 | @@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data) | ||
| 135 | int i; | ||
| 136 | |||
| 137 | /* | ||
| 138 | - * Enable 4BYTE mode for controller. This is should be strapped by | ||
| 139 | - * HW for CE0 anyhow. | ||
| 140 | + * Enable 4BYTE mode for controller. | ||
| 141 | */ | ||
| 142 | - spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0); | ||
| 143 | + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 144 | |||
| 145 | /* Enable 4BYTE mode for flash. */ | ||
| 146 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 147 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 148 | spi_ctrl_start_user(test_data); | ||
| 149 | flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 150 | flash_writeb(test_data, 0, WREN); | ||
| 151 | @@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data) | ||
| 152 | flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 153 | } | ||
| 154 | spi_ctrl_stop_user(test_data); | ||
| 155 | - spi_conf_remove(test_data, CONF_ENABLE_W0); | ||
| 156 | + spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 157 | |||
| 158 | /* Check what was written */ | ||
| 159 | read_page_mem(test_data, my_page_addr, page); | ||
| 160 | @@ -XXX,XX +XXX,XX @@ static void test_write_page_mem(const void *data) | ||
| 161 | int i; | ||
| 162 | |||
| 163 | /* | ||
| 164 | - * Enable 4BYTE mode for controller. This is should be strapped by | ||
| 165 | - * HW for CE0 anyhow. | ||
| 166 | + * Enable 4BYTE mode for controller. | ||
| 167 | */ | ||
| 168 | - spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0); | ||
| 169 | + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 170 | |||
| 171 | /* Enable 4BYTE mode for flash. */ | ||
| 172 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 173 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 174 | spi_ctrl_start_user(test_data); | ||
| 175 | flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 176 | flash_writeb(test_data, 0, WREN); | ||
| 177 | @@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data) | ||
| 178 | const TestData *test_data = (const TestData *)data; | ||
| 179 | uint8_t r; | ||
| 180 | |||
| 181 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 182 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 183 | |||
| 184 | spi_ctrl_start_user(test_data); | ||
| 185 | flash_writeb(test_data, 0, RDSR); | ||
| 186 | @@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data) | ||
| 187 | |||
| 188 | g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 189 | g_assert(!qtest_qom_get_bool | ||
| 190 | - (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 191 | + (test_data->s, test_data->node, "write-enable")); | ||
| 192 | |||
| 193 | spi_ctrl_start_user(test_data); | ||
| 194 | flash_writeb(test_data, 0, WREN); | ||
| 195 | @@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data) | ||
| 196 | |||
| 197 | g_assert_cmphex(r & SR_WEL, ==, SR_WEL); | ||
| 198 | g_assert(qtest_qom_get_bool | ||
| 199 | - (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 200 | + (test_data->s, test_data->node, "write-enable")); | ||
| 201 | |||
| 202 | spi_ctrl_start_user(test_data); | ||
| 203 | flash_writeb(test_data, 0, WRDI); | ||
| 204 | @@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data) | ||
| 205 | |||
| 206 | g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 207 | g_assert(!qtest_qom_get_bool | ||
| 208 | - (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); | ||
| 209 | + (test_data->s, test_data->node, "write-enable")); | ||
| 210 | |||
| 211 | flash_reset(test_data); | ||
| 212 | } | ||
| 213 | @@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data) | ||
| 214 | const TestData *test_data = (const TestData *)data; | ||
| 215 | uint8_t r; | ||
| 216 | |||
| 217 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 218 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 219 | |||
| 220 | /* default case: WP# is high and SRWD is low -> status register writable */ | ||
| 221 | spi_ctrl_start_user(test_data); | ||
| 222 | @@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data) | ||
| 223 | g_assert_cmphex(r & SRWD, ==, 0); | ||
| 224 | |||
| 225 | /* WP# low and SRWD low -> status register writable */ | ||
| 226 | - qtest_set_irq_in(test_data->s, | ||
| 227 | - "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0); | ||
| 228 | + qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0); | ||
| 229 | spi_ctrl_start_user(test_data); | ||
| 230 | flash_writeb(test_data, 0, WREN); | ||
| 231 | /* test ability to write SRWD */ | ||
| 232 | @@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data) | ||
| 233 | /* write is not successful */ | ||
| 234 | g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 235 | |||
| 236 | - qtest_set_irq_in(test_data->s, | ||
| 237 | - "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1); | ||
| 238 | + qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1); | ||
| 239 | flash_reset(test_data); | ||
| 240 | } | ||
| 241 | |||
| 242 | @@ -XXX,XX +XXX,XX @@ static void test_write_block_protect(const void *data) | ||
| 243 | uint32_t sector_size = 65536; | ||
| 244 | uint32_t n_sectors = 512; | ||
| 245 | |||
| 246 | - spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0); | ||
| 247 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 248 | + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 249 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 250 | |||
| 251 | uint32_t bp_bits = 0b0; | ||
| 252 | |||
| 253 | @@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(const void *data) | ||
| 254 | uint32_t sector_size = 65536; | ||
| 255 | uint32_t n_sectors = 512; | ||
| 256 | |||
| 257 | - spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0); | ||
| 258 | - spi_conf(test_data, CONF_ENABLE_W0); | ||
| 259 | + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 260 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 261 | |||
| 262 | /* top bottom bit is enabled */ | ||
| 263 | uint32_t bp_bits = 0b00100 << 3; | ||
| 264 | @@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data) | ||
| 265 | data->flash_base = 0x20000000; | ||
| 266 | data->spi_base = 0x1E620000; | ||
| 267 | data->jedec_id = 0x20ba19; | ||
| 268 | + data->cs = 0; | ||
| 269 | + data->node = "/machine/soc/fmc/ssi.0/child[0]"; | ||
| 270 | |||
| 271 | qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec); | ||
| 272 | qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector); | ||
| 273 | -- | ||
| 274 | 2.47.1 | ||
| 275 | |||
| 276 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> | ||
| 1 | 2 | ||
| 3 | Currently, these test cases used the hardcode offset 0x1400000 (0x14000 * 256) | ||
| 4 | which was beyond the 16MB flash size for flash page read/write command testing. | ||
| 5 | However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose size | ||
| 6 | is 1MB. To test SoC flash models, introduces a new page_addr member in TestData | ||
| 7 | structure, so users can set the offset for flash page read/write command | ||
| 8 | testing. | ||
| 9 | |||
| 10 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> | ||
| 11 | Reviewed-by: Cédric Le Goater <clg@redhat.com> | ||
| 12 | Link: https://lore.kernel.org/r/20241127091543.1243114-5-jamin_lin@aspeedtech.com | ||
| 13 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 14 | --- | ||
| 15 | tests/qtest/aspeed_smc-test.c | 17 ++++++++++------- | ||
| 16 | 1 file changed, 10 insertions(+), 7 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/tests/qtest/aspeed_smc-test.c | ||
| 21 | +++ b/tests/qtest/aspeed_smc-test.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ typedef struct TestData { | ||
| 23 | char *tmp_path; | ||
| 24 | uint8_t cs; | ||
| 25 | const char *node; | ||
| 26 | + uint32_t page_addr; | ||
| 27 | } TestData; | ||
| 28 | |||
| 29 | /* | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static void assert_page_mem(const TestData *data, uint32_t addr, | ||
| 31 | static void test_erase_sector(const void *data) | ||
| 32 | { | ||
| 33 | const TestData *test_data = (const TestData *)data; | ||
| 34 | - uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE; | ||
| 35 | + uint32_t some_page_addr = test_data->page_addr; | ||
| 36 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 37 | int i; | ||
| 38 | |||
| 39 | @@ -XXX,XX +XXX,XX @@ static void test_erase_sector(const void *data) | ||
| 40 | static void test_erase_all(const void *data) | ||
| 41 | { | ||
| 42 | const TestData *test_data = (const TestData *)data; | ||
| 43 | - uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; | ||
| 44 | + uint32_t some_page_addr = test_data->page_addr; | ||
| 45 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 46 | int i; | ||
| 47 | |||
| 48 | @@ -XXX,XX +XXX,XX @@ static void test_erase_all(const void *data) | ||
| 49 | static void test_write_page(const void *data) | ||
| 50 | { | ||
| 51 | const TestData *test_data = (const TestData *)data; | ||
| 52 | - uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */ | ||
| 53 | - uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; | ||
| 54 | + uint32_t my_page_addr = test_data->page_addr; | ||
| 55 | + uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; | ||
| 56 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 57 | int i; | ||
| 58 | |||
| 59 | @@ -XXX,XX +XXX,XX @@ static void test_write_page(const void *data) | ||
| 60 | static void test_read_page_mem(const void *data) | ||
| 61 | { | ||
| 62 | const TestData *test_data = (const TestData *)data; | ||
| 63 | - uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */ | ||
| 64 | - uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; | ||
| 65 | + uint32_t my_page_addr = test_data->page_addr; | ||
| 66 | + uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; | ||
| 67 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 68 | int i; | ||
| 69 | |||
| 70 | @@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data) | ||
| 71 | static void test_write_page_mem(const void *data) | ||
| 72 | { | ||
| 73 | const TestData *test_data = (const TestData *)data; | ||
| 74 | - uint32_t my_page_addr = 0x15000 * FLASH_PAGE_SIZE; | ||
| 75 | + uint32_t my_page_addr = test_data->page_addr; | ||
| 76 | uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 77 | int i; | ||
| 78 | |||
| 79 | @@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data) | ||
| 80 | data->jedec_id = 0x20ba19; | ||
| 81 | data->cs = 0; | ||
| 82 | data->node = "/machine/soc/fmc/ssi.0/child[0]"; | ||
| 83 | + /* beyond 16MB */ | ||
| 84 | + data->page_addr = 0x14000 * FLASH_PAGE_SIZE; | ||
| 85 | |||
| 86 | qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec); | ||
| 87 | qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector); | ||
| 88 | -- | ||
| 89 | 2.47.1 | ||
| 90 | |||
| 91 | diff view generated by jsdifflib |
| 1 | From: Peter Delevoryas <pdel@fb.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The AST1030 machine initialization was not respecting the Aspeed SoC | 3 | Add test_ast2500_evb function and reused testcases for AST2500 testing. |
| 4 | property "uart-default", which specifies which UART should be connected to | 4 | The spi base address, flash base address and ce index of fmc_cs0 are |
| 5 | the first serial device, it was just always connecting UART5. This doesn't | 5 | 0x1E620000, 0x20000000 and 0, respectively. |
| 6 | change any behavior, because the default value for "uart-default" is UART5, | 6 | The default flash model of fmc_cs0 is "mx25l25635e" whose size is 32MB, |
| 7 | but it makes it possible to override this in new machine definitions using | 7 | so set jedec_id 0xc22019. |
| 8 | the AST1030. | ||
| 9 | 8 | ||
| 10 | Signed-off-by: Peter Delevoryas <pdel@fb.com> | 9 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 10 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 12 | Message-Id: <20220516062328.298336-4-pdel@fb.com> | 11 | Link: https://lore.kernel.org/r/20241127091543.1243114-6-jamin_lin@aspeedtech.com |
| 13 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 12 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 14 | --- | 13 | --- |
| 15 | hw/arm/aspeed_ast10x0.c | 6 +++--- | 14 | tests/qtest/aspeed_smc-test.c | 40 +++++++++++++++++++++++++++++++++++ |
| 16 | 1 file changed, 3 insertions(+), 3 deletions(-) | 15 | 1 file changed, 40 insertions(+) |
| 17 | 16 | ||
| 18 | diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c | 17 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c |
| 19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/hw/arm/aspeed_ast10x0.c | 19 | --- a/tests/qtest/aspeed_smc-test.c |
| 21 | +++ b/hw/arm/aspeed_ast10x0.c | 20 | +++ b/tests/qtest/aspeed_smc-test.c |
| 22 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | 21 | @@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data) |
| 23 | qdev_get_gpio_in(DEVICE(&s->armv7m), | 22 | data, test_write_block_protect_bottom_bit); |
| 24 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | 23 | } |
| 25 | 24 | ||
| 26 | - /* UART5 - attach an 8250 to the IO space as our UART */ | 25 | +static void test_ast2500_evb(TestData *data) |
| 27 | - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, | 26 | +{ |
| 28 | - aspeed_soc_get_irq(s, ASPEED_DEV_UART5), | 27 | + int ret; |
| 29 | + /* UART - attach an 8250 to the IO space as our UART */ | 28 | + int fd; |
| 30 | + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | 29 | + |
| 31 | + aspeed_soc_get_irq(s, s->uart_default), | 30 | + fd = g_file_open_tmp("qtest.m25p80.mx25l25635e.XXXXXX", |
| 32 | 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); | 31 | + &data->tmp_path, NULL); |
| 33 | 32 | + g_assert(fd >= 0); | |
| 34 | /* Timer */ | 33 | + ret = ftruncate(fd, 32 * 1024 * 1024); |
| 34 | + g_assert(ret == 0); | ||
| 35 | + close(fd); | ||
| 36 | + | ||
| 37 | + data->s = qtest_initf("-machine ast2500-evb " | ||
| 38 | + "-drive file=%s,format=raw,if=mtd", | ||
| 39 | + data->tmp_path); | ||
| 40 | + | ||
| 41 | + /* fmc cs0 with mx25l25635e flash */ | ||
| 42 | + data->flash_base = 0x20000000; | ||
| 43 | + data->spi_base = 0x1E620000; | ||
| 44 | + data->jedec_id = 0xc22019; | ||
| 45 | + data->cs = 0; | ||
| 46 | + data->node = "/machine/soc/fmc/ssi.0/child[0]"; | ||
| 47 | + /* beyond 16MB */ | ||
| 48 | + data->page_addr = 0x14000 * FLASH_PAGE_SIZE; | ||
| 49 | + | ||
| 50 | + qtest_add_data_func("/ast2500/smc/read_jedec", data, test_read_jedec); | ||
| 51 | + qtest_add_data_func("/ast2500/smc/erase_sector", data, test_erase_sector); | ||
| 52 | + qtest_add_data_func("/ast2500/smc/erase_all", data, test_erase_all); | ||
| 53 | + qtest_add_data_func("/ast2500/smc/write_page", data, test_write_page); | ||
| 54 | + qtest_add_data_func("/ast2500/smc/read_page_mem", | ||
| 55 | + data, test_read_page_mem); | ||
| 56 | + qtest_add_data_func("/ast2500/smc/write_page_mem", | ||
| 57 | + data, test_write_page_mem); | ||
| 58 | + qtest_add_data_func("/ast2500/smc/read_status_reg", | ||
| 59 | + data, test_read_status_reg); | ||
| 60 | +} | ||
| 61 | int main(int argc, char **argv) | ||
| 62 | { | ||
| 63 | TestData palmetto_data; | ||
| 64 | + TestData ast2500_evb_data; | ||
| 65 | int ret; | ||
| 66 | |||
| 67 | g_test_init(&argc, &argv, NULL); | ||
| 68 | |||
| 69 | test_palmetto_bmc(&palmetto_data); | ||
| 70 | + test_ast2500_evb(&ast2500_evb_data); | ||
| 71 | ret = g_test_run(); | ||
| 72 | |||
| 73 | qtest_quit(palmetto_data.s); | ||
| 74 | + qtest_quit(ast2500_evb_data.s); | ||
| 75 | unlink(palmetto_data.tmp_path); | ||
| 76 | + unlink(ast2500_evb_data.tmp_path); | ||
| 77 | return ret; | ||
| 78 | } | ||
| 35 | -- | 79 | -- |
| 36 | 2.35.3 | 80 | 2.47.1 |
| 37 | 81 | ||
| 38 | 82 | diff view generated by jsdifflib |
| 1 | From: Peter Delevoryas <pdel@fb.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Background: | 3 | Add test_ast2600_evb function and reused testcases for AST2600 testing. |
| 4 | The spi base address, flash base address and ce index of fmc_cs0 are | ||
| 5 | 0x1E620000, 0x20000000 and 0, respectively. | ||
| 6 | The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB, | ||
| 7 | so set jedec_id 0xc2253a. | ||
| 4 | 8 | ||
| 5 | AspeedMachineClass.uart_default specifies the serial console UART, which | 9 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 6 | usually corresponds to the "stdout-path" in the device tree. | 10 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 11 | Link: https://lore.kernel.org/r/20241127091543.1243114-7-jamin_lin@aspeedtech.com | ||
| 12 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 13 | --- | ||
| 14 | tests/qtest/aspeed_smc-test.c | 41 +++++++++++++++++++++++++++++++++++ | ||
| 15 | 1 file changed, 41 insertions(+) | ||
| 7 | 16 | ||
| 8 | The default value is UART5, since most boards use UART5 for this: | 17 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c |
| 9 | |||
| 10 | amc->uart_default = ASPEED_DEV_UART5; | ||
| 11 | |||
| 12 | Users can override AspeedMachineClass.uart_default in their board's machine | ||
| 13 | class init to specify something besides UART5. For example, for fuji-bmc: | ||
| 14 | |||
| 15 | amc->uart_default = ASPEED_DEV_UART1; | ||
| 16 | |||
| 17 | We only connect this one UART, of the 5 UART's on the AST2400 and AST2500 | ||
| 18 | and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU | ||
| 19 | users can use. None of the other UART's are initialized, and the only way | ||
| 20 | to override this attribute is by creating a specialized board definition, | ||
| 21 | requiring QEMU source code changes and rebuilding. | ||
| 22 | |||
| 23 | The result of this is that if you want to get serial console output on a | ||
| 24 | board that uses UART3, you need to add a board definition. This was | ||
| 25 | encountered by Zev in OpenBMC. [1] | ||
| 26 | |||
| 27 | Changes: | ||
| 28 | |||
| 29 | This commit initializes all of the UART's present on each Aspeed chip with | ||
| 30 | serial devices and allows the QEMU user to connect as many or few as they | ||
| 31 | like to serial devices. For example, you can still run QEMU and just connect | ||
| 32 | stdout to the machine's default UART, without specifying any additional | ||
| 33 | serial devices: | ||
| 34 | |||
| 35 | qemu-system-arm -machine fuji-bmc \ | ||
| 36 | -drive file=fuji.mtd,format=raw,if=mtd \ | ||
| 37 | -nographic | ||
| 38 | |||
| 39 | However, if you don't want to add a special machine definition, you can now | ||
| 40 | manually configure UART1 to connect to stdout and get serial console output, | ||
| 41 | even if the machine's default is UART5: | ||
| 42 | |||
| 43 | qemu-system-arm -machine ast2600-evb \ | ||
| 44 | -drive file=fuji.mtd,format=raw,if=mtd \ | ||
| 45 | -serial null -serial mon:stdio -display none | ||
| 46 | |||
| 47 | In the example above, the first "-serial null" argument is connected to | ||
| 48 | UART5, and "-serial mon:stdio" is connected to UART1. | ||
| 49 | |||
| 50 | Another example: you can get serial console output from Wedge100, which uses | ||
| 51 | UART3, by reusing the palmetto AST2400 machine and rewiring the serial | ||
| 52 | device arguments: | ||
| 53 | |||
| 54 | qemu-system-arm -machine palmetto-bmc \ | ||
| 55 | -drive file=wedge100.mtd,format=raw,if=mtd \ | ||
| 56 | -serial null -serial null -serial null \ | ||
| 57 | -serial mon:stdio -display none | ||
| 58 | |||
| 59 | There is a slight change in behavior introduced with this change: now, each | ||
| 60 | UART's memory-mapped IO region will have a serial device model connected to | ||
| 61 | it. Previously, all reads and writes to those regions would be ineffective | ||
| 62 | and return zero values, but now some values will be nonzero, even when the | ||
| 63 | user doesn't connect a serial device backend (like a socket, file, etc). For | ||
| 64 | example, the line status register might indicate that the transmit buffer is | ||
| 65 | empty now, whereas previously it might have always indicated it was full. | ||
| 66 | |||
| 67 | [1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/ | ||
| 68 | [2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd | ||
| 69 | [3] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd | ||
| 70 | |||
| 71 | Signed-off-by: Peter Delevoryas <pdel@fb.com> | ||
| 72 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
| 73 | Message-Id: <20220516062328.298336-6-pdel@fb.com> | ||
| 74 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 75 | --- | ||
| 76 | hw/arm/aspeed_soc.c | 9 +++++++++ | ||
| 77 | 1 file changed, 9 insertions(+) | ||
| 78 | |||
| 79 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 80 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 81 | --- a/hw/arm/aspeed_soc.c | 19 | --- a/tests/qtest/aspeed_smc-test.c |
| 82 | +++ b/hw/arm/aspeed_soc.c | 20 | +++ b/tests/qtest/aspeed_smc-test.c |
| 83 | @@ -XXX,XX +XXX,XX @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) | 21 | @@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data) |
| 84 | void aspeed_soc_uart_init(AspeedSoCState *s) | 22 | qtest_add_data_func("/ast2500/smc/read_status_reg", |
| 23 | data, test_read_status_reg); | ||
| 24 | } | ||
| 25 | + | ||
| 26 | +static void test_ast2600_evb(TestData *data) | ||
| 27 | +{ | ||
| 28 | + int ret; | ||
| 29 | + int fd; | ||
| 30 | + | ||
| 31 | + fd = g_file_open_tmp("qtest.m25p80.mx66u51235f.XXXXXX", | ||
| 32 | + &data->tmp_path, NULL); | ||
| 33 | + g_assert(fd >= 0); | ||
| 34 | + ret = ftruncate(fd, 64 * 1024 * 1024); | ||
| 35 | + g_assert(ret == 0); | ||
| 36 | + close(fd); | ||
| 37 | + | ||
| 38 | + data->s = qtest_initf("-machine ast2600-evb " | ||
| 39 | + "-drive file=%s,format=raw,if=mtd", | ||
| 40 | + data->tmp_path); | ||
| 41 | + | ||
| 42 | + /* fmc cs0 with mx66u51235f flash */ | ||
| 43 | + data->flash_base = 0x20000000; | ||
| 44 | + data->spi_base = 0x1E620000; | ||
| 45 | + data->jedec_id = 0xc2253a; | ||
| 46 | + data->cs = 0; | ||
| 47 | + data->node = "/machine/soc/fmc/ssi.0/child[0]"; | ||
| 48 | + /* beyond 16MB */ | ||
| 49 | + data->page_addr = 0x14000 * FLASH_PAGE_SIZE; | ||
| 50 | + | ||
| 51 | + qtest_add_data_func("/ast2600/smc/read_jedec", data, test_read_jedec); | ||
| 52 | + qtest_add_data_func("/ast2600/smc/erase_sector", data, test_erase_sector); | ||
| 53 | + qtest_add_data_func("/ast2600/smc/erase_all", data, test_erase_all); | ||
| 54 | + qtest_add_data_func("/ast2600/smc/write_page", data, test_write_page); | ||
| 55 | + qtest_add_data_func("/ast2600/smc/read_page_mem", | ||
| 56 | + data, test_read_page_mem); | ||
| 57 | + qtest_add_data_func("/ast2600/smc/write_page_mem", | ||
| 58 | + data, test_write_page_mem); | ||
| 59 | + qtest_add_data_func("/ast2600/smc/read_status_reg", | ||
| 60 | + data, test_read_status_reg); | ||
| 61 | +} | ||
| 62 | int main(int argc, char **argv) | ||
| 85 | { | 63 | { |
| 86 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | 64 | TestData palmetto_data; |
| 87 | + int i, uart; | 65 | TestData ast2500_evb_data; |
| 88 | 66 | + TestData ast2600_evb_data; | |
| 89 | /* Attach an 8250 to the IO space as our UART */ | 67 | int ret; |
| 90 | serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | 68 | |
| 91 | aspeed_soc_get_irq(s, s->uart_default), 38400, | 69 | g_test_init(&argc, &argv, NULL); |
| 92 | serial_hd(0), DEVICE_LITTLE_ENDIAN); | 70 | |
| 93 | + for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { | 71 | test_palmetto_bmc(&palmetto_data); |
| 94 | + if (uart == s->uart_default) { | 72 | test_ast2500_evb(&ast2500_evb_data); |
| 95 | + uart++; | 73 | + test_ast2600_evb(&ast2600_evb_data); |
| 96 | + } | 74 | ret = g_test_run(); |
| 97 | + serial_mm_init(get_system_memory(), sc->memmap[uart], 2, | 75 | |
| 98 | + aspeed_soc_get_irq(s, uart), 38400, | 76 | qtest_quit(palmetto_data.s); |
| 99 | + serial_hd(i), DEVICE_LITTLE_ENDIAN); | 77 | qtest_quit(ast2500_evb_data.s); |
| 100 | + } | 78 | + qtest_quit(ast2600_evb_data.s); |
| 79 | unlink(palmetto_data.tmp_path); | ||
| 80 | unlink(ast2500_evb_data.tmp_path); | ||
| 81 | + unlink(ast2600_evb_data.tmp_path); | ||
| 82 | return ret; | ||
| 101 | } | 83 | } |
| 102 | -- | 84 | -- |
| 103 | 2.35.3 | 85 | 2.47.1 |
| 104 | 86 | ||
| 105 | 87 | diff view generated by jsdifflib |
| 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add test_ast1030_evb function and reused testcases for AST1030 testing. | ||
| 4 | The base address, flash base address and ce index of fmc_cs0 are | ||
| 5 | 0x7E620000, 0x80000000 and 0, respectively. | ||
| 6 | The default flash model of fmc_cs0 is "w25q80bl" whose size is 1MB, | ||
| 7 | so set jedec_id 0xef4014. | ||
| 8 | |||
| 3 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> | 9 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 4 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 10 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 5 | Message-Id: <20220506031521.13254-2-jamin_lin@aspeedtech.com> | 11 | Link: https://lore.kernel.org/r/20241127091543.1243114-8-jamin_lin@aspeedtech.com |
| 6 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 12 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 7 | --- | 13 | --- |
| 8 | docs/system/arm/aspeed.rst | 61 ++++++++++++++++++++++++++++++++++++++ | 14 | tests/qtest/aspeed_smc-test.c | 42 +++++++++++++++++++++++++++++++++++ |
| 9 | 1 file changed, 61 insertions(+) | 15 | 1 file changed, 42 insertions(+) |
| 10 | 16 | ||
| 11 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst | 17 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/docs/system/arm/aspeed.rst | 19 | --- a/tests/qtest/aspeed_smc-test.c |
| 14 | +++ b/docs/system/arm/aspeed.rst | 20 | +++ b/tests/qtest/aspeed_smc-test.c |
| 15 | @@ -XXX,XX +XXX,XX @@ FMC chip and a bigger (64M) SPI chip, use : | 21 | @@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data) |
| 16 | .. code-block:: bash | 22 | qtest_add_data_func("/ast2600/smc/read_status_reg", |
| 17 | 23 | data, test_read_status_reg); | |
| 18 | -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f | 24 | } |
| 19 | + | 25 | + |
| 26 | +static void test_ast1030_evb(TestData *data) | ||
| 27 | +{ | ||
| 28 | + int ret; | ||
| 29 | + int fd; | ||
| 20 | + | 30 | + |
| 21 | +Aspeed minibmc family boards (``ast1030-evb``) | 31 | + fd = g_file_open_tmp("qtest.m25p80.w25q80bl.XXXXXX", |
| 22 | +================================================================== | 32 | + &data->tmp_path, NULL); |
| 33 | + g_assert(fd >= 0); | ||
| 34 | + ret = ftruncate(fd, 1 * 1024 * 1024); | ||
| 35 | + g_assert(ret == 0); | ||
| 36 | + close(fd); | ||
| 23 | + | 37 | + |
| 24 | +The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation | 38 | + data->s = qtest_initf("-machine ast1030-evb " |
| 25 | +boards. They are based on different releases of the | 39 | + "-drive file=%s,format=raw,if=mtd", |
| 26 | +Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). | 40 | + data->tmp_path); |
| 27 | + | 41 | + |
| 28 | +The SoC comes with SRAM, SPI, I2C, etc. | 42 | + /* fmc cs0 with w25q80bl flash */ |
| 43 | + data->flash_base = 0x80000000; | ||
| 44 | + data->spi_base = 0x7E620000; | ||
| 45 | + data->jedec_id = 0xef4014; | ||
| 46 | + data->cs = 0; | ||
| 47 | + data->node = "/machine/soc/fmc/ssi.0/child[0]"; | ||
| 48 | + /* beyond 512KB */ | ||
| 49 | + data->page_addr = 0x800 * FLASH_PAGE_SIZE; | ||
| 29 | + | 50 | + |
| 30 | +AST1030 SoC based machines : | 51 | + qtest_add_data_func("/ast1030/smc/read_jedec", data, test_read_jedec); |
| 52 | + qtest_add_data_func("/ast1030/smc/erase_sector", data, test_erase_sector); | ||
| 53 | + qtest_add_data_func("/ast1030/smc/erase_all", data, test_erase_all); | ||
| 54 | + qtest_add_data_func("/ast1030/smc/write_page", data, test_write_page); | ||
| 55 | + qtest_add_data_func("/ast1030/smc/read_page_mem", | ||
| 56 | + data, test_read_page_mem); | ||
| 57 | + qtest_add_data_func("/ast1030/smc/write_page_mem", | ||
| 58 | + data, test_write_page_mem); | ||
| 59 | + qtest_add_data_func("/ast1030/smc/read_status_reg", | ||
| 60 | + data, test_read_status_reg); | ||
| 61 | +} | ||
| 31 | + | 62 | + |
| 32 | +- ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F) | 63 | int main(int argc, char **argv) |
| 33 | + | 64 | { |
| 34 | +Supported devices | 65 | TestData palmetto_data; |
| 35 | +----------------- | 66 | TestData ast2500_evb_data; |
| 36 | + | 67 | TestData ast2600_evb_data; |
| 37 | + * SMP (for the AST1030 Cortex-M4F) | 68 | + TestData ast1030_evb_data; |
| 38 | + * Interrupt Controller (VIC) | 69 | int ret; |
| 39 | + * Timer Controller | 70 | |
| 40 | + * I2C Controller | 71 | g_test_init(&argc, &argv, NULL); |
| 41 | + * System Control Unit (SCU) | 72 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) |
| 42 | + * SRAM mapping | 73 | test_palmetto_bmc(&palmetto_data); |
| 43 | + * Static Memory Controller (SMC or FMC) - Only SPI Flash support | 74 | test_ast2500_evb(&ast2500_evb_data); |
| 44 | + * SPI Memory Controller | 75 | test_ast2600_evb(&ast2600_evb_data); |
| 45 | + * USB 2.0 Controller | 76 | + test_ast1030_evb(&ast1030_evb_data); |
| 46 | + * Watchdog Controller | 77 | ret = g_test_run(); |
| 47 | + * GPIO Controller (Master only) | 78 | |
| 48 | + * UART | 79 | qtest_quit(palmetto_data.s); |
| 49 | + * LPC Peripheral Controller (a subset of subdevices are supported) | 80 | qtest_quit(ast2500_evb_data.s); |
| 50 | + * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA | 81 | qtest_quit(ast2600_evb_data.s); |
| 51 | + * ADC | 82 | + qtest_quit(ast1030_evb_data.s); |
| 52 | + | 83 | unlink(palmetto_data.tmp_path); |
| 53 | + | 84 | unlink(ast2500_evb_data.tmp_path); |
| 54 | +Missing devices | 85 | unlink(ast2600_evb_data.tmp_path); |
| 55 | +--------------- | 86 | + unlink(ast1030_evb_data.tmp_path); |
| 56 | + | 87 | return ret; |
| 57 | + * PWM and Fan Controller | 88 | } |
| 58 | + * Slave GPIO Controller | ||
| 59 | + * PECI Controller | ||
| 60 | + * Mailbox Controller | ||
| 61 | + * Virtual UART | ||
| 62 | + * eSPI Controller | ||
| 63 | + * I3C Controller | ||
| 64 | + | ||
| 65 | +Boot options | ||
| 66 | +------------ | ||
| 67 | + | ||
| 68 | +The Aspeed machines can be started using the ``-kernel`` to load a | ||
| 69 | +Zephyr OS or from a firmware. Images can be downloaded from the | ||
| 70 | +ASPEED GitHub release repository : | ||
| 71 | + | ||
| 72 | + https://github.com/AspeedTech-BMC/zephyr/releases | ||
| 73 | + | ||
| 74 | +To boot a kernel directly from a Zephyr build tree: | ||
| 75 | + | ||
| 76 | +.. code-block:: bash | ||
| 77 | + | ||
| 78 | + $ qemu-system-arm -M ast1030-evb -nographic \ | ||
| 79 | + -kernel zephyr.elf | ||
| 80 | -- | 89 | -- |
| 81 | 2.35.3 | 90 | 2.47.1 |
| 82 | 91 | ||
| 83 | 92 | diff view generated by jsdifflib |
| 1 | and make routine aspeed_soc_get_irq() common to all SoCs. This will be | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | useful to share code. | ||
| 3 | 2 | ||
| 4 | Cc: Jamin Lin <jamin_lin@aspeedtech.com> | 3 | Add a new testcase for write page command with QPI mode testing. |
| 5 | Cc: Peter Delevoryas <pdel@fb.com> | 4 | Currently, only run this testcase for AST2500, AST2600 and AST1030. |
| 6 | Reviewed-by: Peter Delevoryas <pdel@fb.com> | 5 | |
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 8 | Message-Id: <20220516055620.2380197-1-clg@kaod.org> | 7 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 8 | Link: https://lore.kernel.org/r/20241127091543.1243114-9-jamin_lin@aspeedtech.com |
| 9 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 10 | --- | 10 | --- |
| 11 | include/hw/arm/aspeed_soc.h | 3 +++ | 11 | tests/qtest/aspeed_smc-test.c | 74 +++++++++++++++++++++++++++++++++++ |
| 12 | hw/arm/aspeed_ast10x0.c | 5 +++-- | 12 | 1 file changed, 74 insertions(+) |
| 13 | hw/arm/aspeed_ast2600.c | 5 +++-- | ||
| 14 | hw/arm/aspeed_soc.c | 13 ++++++++++--- | ||
| 15 | 4 files changed, 19 insertions(+), 7 deletions(-) | ||
| 16 | 13 | ||
| 17 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | 14 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c |
| 18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/include/hw/arm/aspeed_soc.h | 16 | --- a/tests/qtest/aspeed_smc-test.c |
| 20 | +++ b/include/hw/arm/aspeed_soc.h | 17 | +++ b/tests/qtest/aspeed_smc-test.c |
| 21 | @@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass { | 18 | @@ -XXX,XX +XXX,XX @@ |
| 22 | const int *irqmap; | 19 | #define R_CE_CTRL 0x04 |
| 23 | const hwaddr *memmap; | 20 | #define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ |
| 24 | uint32_t num_cpus; | 21 | #define R_CTRL0 0x10 |
| 25 | + qemu_irq (*get_irq)(AspeedSoCState *s, int dev); | 22 | +#define CTRL_IO_QUAD_IO BIT(31) |
| 23 | #define CTRL_CE_STOP_ACTIVE BIT(2) | ||
| 24 | #define CTRL_READMODE 0x0 | ||
| 25 | #define CTRL_FREADMODE 0x1 | ||
| 26 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 27 | ERASE_SECTOR = 0xd8, | ||
| 26 | }; | 28 | }; |
| 27 | 29 | ||
| 28 | 30 | +#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28)) | |
| 29 | @@ -XXX,XX +XXX,XX @@ enum { | 31 | #define FLASH_PAGE_SIZE 256 |
| 30 | ASPEED_DEV_I3C, | 32 | |
| 31 | }; | 33 | typedef struct TestData { |
| 32 | 34 | @@ -XXX,XX +XXX,XX @@ static void spi_ctrl_stop_user(const TestData *data) | |
| 33 | +qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); | 35 | spi_writel(data, ctrl_reg, ctrl); |
| 36 | } | ||
| 37 | |||
| 38 | +static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value) | ||
| 39 | +{ | ||
| 40 | + uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 41 | + uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 42 | + uint32_t mode; | ||
| 34 | + | 43 | + |
| 35 | #endif /* ASPEED_SOC_H */ | 44 | + mode = value & CTRL_IO_MODE_MASK; |
| 36 | diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c | 45 | + ctrl &= ~CTRL_IO_MODE_MASK; |
| 37 | index XXXXXXX..XXXXXXX 100644 | 46 | + ctrl |= mode; |
| 38 | --- a/hw/arm/aspeed_ast10x0.c | 47 | + spi_writel(data, ctrl_reg, ctrl); |
| 39 | +++ b/hw/arm/aspeed_ast10x0.c | 48 | +} |
| 40 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = { | 49 | + |
| 41 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ | 50 | static void flash_reset(const TestData *data) |
| 42 | }; | ||
| 43 | |||
| 44 | -static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | ||
| 45 | +static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) | ||
| 46 | { | 51 | { |
| 47 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | 52 | spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs)); |
| 48 | 53 | @@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(const void *data) | |
| 49 | - return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ctrl]); | 54 | flash_reset(test_data); |
| 50 | + return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]); | ||
| 51 | } | 55 | } |
| 52 | 56 | ||
| 53 | static void aspeed_soc_ast1030_init(Object *obj) | 57 | +static void test_write_page_qpi(const void *data) |
| 54 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) | 58 | +{ |
| 55 | sc->irqmap = aspeed_soc_ast1030_irqmap; | 59 | + const TestData *test_data = (const TestData *)data; |
| 56 | sc->memmap = aspeed_soc_ast1030_memmap; | 60 | + uint32_t my_page_addr = test_data->page_addr; |
| 57 | sc->num_cpus = 1; | 61 | + uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; |
| 58 | + sc->get_irq = aspeed_soc_ast1030_get_irq; | 62 | + uint32_t page[FLASH_PAGE_SIZE / 4]; |
| 63 | + uint32_t page_pattern[] = { | ||
| 64 | + 0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf | ||
| 65 | + }; | ||
| 66 | + int i; | ||
| 67 | + | ||
| 68 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 69 | + | ||
| 70 | + spi_ctrl_start_user(test_data); | ||
| 71 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 72 | + flash_writeb(test_data, 0, WREN); | ||
| 73 | + flash_writeb(test_data, 0, PP); | ||
| 74 | + flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 75 | + | ||
| 76 | + /* Set QPI mode */ | ||
| 77 | + spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO); | ||
| 78 | + | ||
| 79 | + /* Fill the page pattern */ | ||
| 80 | + for (i = 0; i < ARRAY_SIZE(page_pattern); i++) { | ||
| 81 | + flash_writel(test_data, 0, make_be32(page_pattern[i])); | ||
| 82 | + } | ||
| 83 | + | ||
| 84 | + /* Fill the page with its own addresses */ | ||
| 85 | + for (; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 86 | + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 87 | + } | ||
| 88 | + | ||
| 89 | + /* Restore io mode */ | ||
| 90 | + spi_ctrl_set_io_mode(test_data, 0); | ||
| 91 | + spi_ctrl_stop_user(test_data); | ||
| 92 | + | ||
| 93 | + /* Check what was written */ | ||
| 94 | + read_page(test_data, my_page_addr, page); | ||
| 95 | + for (i = 0; i < ARRAY_SIZE(page_pattern); i++) { | ||
| 96 | + g_assert_cmphex(page[i], ==, page_pattern[i]); | ||
| 97 | + } | ||
| 98 | + for (; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 99 | + g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 100 | + } | ||
| 101 | + | ||
| 102 | + /* Check some other page. It should be full of 0xff */ | ||
| 103 | + read_page(test_data, some_page_addr, page); | ||
| 104 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 105 | + g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 106 | + } | ||
| 107 | + | ||
| 108 | + flash_reset(test_data); | ||
| 109 | +} | ||
| 110 | + | ||
| 111 | static void test_palmetto_bmc(TestData *data) | ||
| 112 | { | ||
| 113 | int ret; | ||
| 114 | @@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data) | ||
| 115 | data, test_write_page_mem); | ||
| 116 | qtest_add_data_func("/ast2500/smc/read_status_reg", | ||
| 117 | data, test_read_status_reg); | ||
| 118 | + qtest_add_data_func("/ast2500/smc/write_page_qpi", | ||
| 119 | + data, test_write_page_qpi); | ||
| 59 | } | 120 | } |
| 60 | 121 | ||
| 61 | static const TypeInfo aspeed_soc_ast1030_type_info = { | 122 | static void test_ast2600_evb(TestData *data) |
| 62 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | 123 | @@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data) |
| 63 | index XXXXXXX..XXXXXXX 100644 | 124 | data, test_write_page_mem); |
| 64 | --- a/hw/arm/aspeed_ast2600.c | 125 | qtest_add_data_func("/ast2600/smc/read_status_reg", |
| 65 | +++ b/hw/arm/aspeed_ast2600.c | 126 | data, test_read_status_reg); |
| 66 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = { | 127 | + qtest_add_data_func("/ast2600/smc/write_page_qpi", |
| 67 | [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ | 128 | + data, test_write_page_qpi); |
| 68 | }; | ||
| 69 | |||
| 70 | -static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | ||
| 71 | +static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) | ||
| 72 | { | ||
| 73 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
| 74 | |||
| 75 | - return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); | ||
| 76 | + return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]); | ||
| 77 | } | 129 | } |
| 78 | 130 | ||
| 79 | static void aspeed_soc_ast2600_init(Object *obj) | 131 | static void test_ast1030_evb(TestData *data) |
| 80 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | 132 | @@ -XXX,XX +XXX,XX @@ static void test_ast1030_evb(TestData *data) |
| 81 | sc->irqmap = aspeed_soc_ast2600_irqmap; | 133 | data, test_write_page_mem); |
| 82 | sc->memmap = aspeed_soc_ast2600_memmap; | 134 | qtest_add_data_func("/ast1030/smc/read_status_reg", |
| 83 | sc->num_cpus = 2; | 135 | data, test_read_status_reg); |
| 84 | + sc->get_irq = aspeed_soc_ast2600_get_irq; | 136 | + qtest_add_data_func("/ast1030/smc/write_page_qpi", |
| 137 | + data, test_write_page_qpi); | ||
| 85 | } | 138 | } |
| 86 | 139 | ||
| 87 | static const TypeInfo aspeed_soc_ast2600_type_info = { | 140 | int main(int argc, char **argv) |
| 88 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 89 | index XXXXXXX..XXXXXXX 100644 | ||
| 90 | --- a/hw/arm/aspeed_soc.c | ||
| 91 | +++ b/hw/arm/aspeed_soc.c | ||
| 92 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = { | ||
| 93 | |||
| 94 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap | ||
| 95 | |||
| 96 | -static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | ||
| 97 | +static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) | ||
| 98 | { | ||
| 99 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
| 100 | |||
| 101 | - return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]); | ||
| 102 | + return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]); | ||
| 103 | } | ||
| 104 | |||
| 105 | static void aspeed_soc_init(Object *obj) | ||
| 106 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
| 107 | sc->irqmap = aspeed_soc_ast2400_irqmap; | ||
| 108 | sc->memmap = aspeed_soc_ast2400_memmap; | ||
| 109 | sc->num_cpus = 1; | ||
| 110 | + sc->get_irq = aspeed_soc_ast2400_get_irq; | ||
| 111 | } | ||
| 112 | |||
| 113 | static const TypeInfo aspeed_soc_ast2400_type_info = { | ||
| 114 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
| 115 | sc->irqmap = aspeed_soc_ast2500_irqmap; | ||
| 116 | sc->memmap = aspeed_soc_ast2500_memmap; | ||
| 117 | sc->num_cpus = 1; | ||
| 118 | + sc->get_irq = aspeed_soc_ast2400_get_irq; | ||
| 119 | } | ||
| 120 | |||
| 121 | static const TypeInfo aspeed_soc_ast2500_type_info = { | ||
| 122 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void) | ||
| 123 | type_register_static(&aspeed_soc_ast2500_type_info); | ||
| 124 | }; | ||
| 125 | |||
| 126 | -type_init(aspeed_soc_register_types) | ||
| 127 | +type_init(aspeed_soc_register_types); | ||
| 128 | + | ||
| 129 | +qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) | ||
| 130 | +{ | ||
| 131 | + return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); | ||
| 132 | +} | ||
| 133 | -- | 141 | -- |
| 134 | 2.35.3 | 142 | 2.47.1 |
| 135 | 143 | ||
| 136 | 144 | diff view generated by jsdifflib |
| 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | AST1030 integrates one set of Parallel GPIO Controller | 3 | The testcases for ASPEED SMC model were placed in aspeed_smc-test.c. |
| 4 | with maximum 151 control pins, which are 21 groups | 4 | However, this test file only supports for ARM32. To support all ASPEED SOCs |
| 5 | (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4 | 5 | such as AST2700 whose CPU architecture is aarch64, introduces a new |
| 6 | S5 S6 S7 ) and the group T and U are input only. | 6 | aspeed-smc-utils source file and move all common APIs and testcases |
| 7 | from aspeed_smc-test.c to aspeed-smc-utils.c. | ||
| 8 | |||
| 9 | Finally, users are able to re-used these testcase for AST2700 and future | ||
| 10 | ASPEED SOCs testing. | ||
| 7 | 11 | ||
| 8 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> | 12 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 9 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 13 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 10 | Message-Id: <20220525053444.27228-3-jamin_lin@aspeedtech.com> | 14 | Link: https://lore.kernel.org/r/20241127091543.1243114-10-jamin_lin@aspeedtech.com |
| 11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 15 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 12 | --- | 16 | --- |
| 13 | hw/arm/aspeed_ast10x0.c | 11 +++++++++++ | 17 | tests/qtest/aspeed-smc-utils.h | 95 ++++ |
| 14 | hw/gpio/aspeed_gpio.c | 27 +++++++++++++++++++++++++++ | 18 | tests/qtest/aspeed-smc-utils.c | 686 ++++++++++++++++++++++++++++ |
| 15 | 2 files changed, 38 insertions(+) | 19 | tests/qtest/aspeed_smc-test.c | 800 +++------------------------------ |
| 20 | tests/qtest/meson.build | 1 + | ||
| 21 | 4 files changed, 841 insertions(+), 741 deletions(-) | ||
| 22 | create mode 100644 tests/qtest/aspeed-smc-utils.h | ||
| 23 | create mode 100644 tests/qtest/aspeed-smc-utils.c | ||
| 16 | 24 | ||
| 17 | diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c | 25 | diff --git a/tests/qtest/aspeed-smc-utils.h b/tests/qtest/aspeed-smc-utils.h |
| 26 | new file mode 100644 | ||
| 27 | index XXXXXXX..XXXXXXX | ||
| 28 | --- /dev/null | ||
| 29 | +++ b/tests/qtest/aspeed-smc-utils.h | ||
| 30 | @@ -XXX,XX +XXX,XX @@ | ||
| 31 | +/* | ||
| 32 | + * QTest testcase for the M25P80 Flash (Using the Aspeed SPI | ||
| 33 | + * Controller) | ||
| 34 | + * | ||
| 35 | + * Copyright (C) 2016 IBM Corp. | ||
| 36 | + * | ||
| 37 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
| 38 | + * of this software and associated documentation files (the "Software"), to deal | ||
| 39 | + * in the Software without restriction, including without limitation the rights | ||
| 40 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
| 41 | + * copies of the Software, and to permit persons to whom the Software is | ||
| 42 | + * furnished to do so, subject to the following conditions: | ||
| 43 | + * | ||
| 44 | + * The above copyright notice and this permission notice shall be included in | ||
| 45 | + * all copies or substantial portions of the Software. | ||
| 46 | + * | ||
| 47 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 48 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 49 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 50 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 51 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
| 52 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
| 53 | + * THE SOFTWARE. | ||
| 54 | + */ | ||
| 55 | + | ||
| 56 | +#ifndef TESTS_ASPEED_SMC_UTILS_H | ||
| 57 | +#define TESTS_ASPEED_SMC_UTILS_H | ||
| 58 | + | ||
| 59 | +#include "qemu/osdep.h" | ||
| 60 | +#include "qemu/bswap.h" | ||
| 61 | +#include "libqtest-single.h" | ||
| 62 | +#include "qemu/bitops.h" | ||
| 63 | + | ||
| 64 | +/* | ||
| 65 | + * ASPEED SPI Controller registers | ||
| 66 | + */ | ||
| 67 | +#define R_CONF 0x00 | ||
| 68 | +#define CONF_ENABLE_W0 16 | ||
| 69 | +#define R_CE_CTRL 0x04 | ||
| 70 | +#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ | ||
| 71 | +#define R_CTRL0 0x10 | ||
| 72 | +#define CTRL_IO_QUAD_IO BIT(31) | ||
| 73 | +#define CTRL_CE_STOP_ACTIVE BIT(2) | ||
| 74 | +#define CTRL_READMODE 0x0 | ||
| 75 | +#define CTRL_FREADMODE 0x1 | ||
| 76 | +#define CTRL_WRITEMODE 0x2 | ||
| 77 | +#define CTRL_USERMODE 0x3 | ||
| 78 | +#define SR_WEL BIT(1) | ||
| 79 | + | ||
| 80 | +/* | ||
| 81 | + * Flash commands | ||
| 82 | + */ | ||
| 83 | +enum { | ||
| 84 | + JEDEC_READ = 0x9f, | ||
| 85 | + RDSR = 0x5, | ||
| 86 | + WRDI = 0x4, | ||
| 87 | + BULK_ERASE = 0xc7, | ||
| 88 | + READ = 0x03, | ||
| 89 | + PP = 0x02, | ||
| 90 | + WRSR = 0x1, | ||
| 91 | + WREN = 0x6, | ||
| 92 | + SRWD = 0x80, | ||
| 93 | + RESET_ENABLE = 0x66, | ||
| 94 | + RESET_MEMORY = 0x99, | ||
| 95 | + EN_4BYTE_ADDR = 0xB7, | ||
| 96 | + ERASE_SECTOR = 0xd8, | ||
| 97 | +}; | ||
| 98 | + | ||
| 99 | +#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28)) | ||
| 100 | +#define FLASH_PAGE_SIZE 256 | ||
| 101 | + | ||
| 102 | +typedef struct AspeedSMCTestData { | ||
| 103 | + QTestState *s; | ||
| 104 | + uint64_t spi_base; | ||
| 105 | + uint64_t flash_base; | ||
| 106 | + uint32_t jedec_id; | ||
| 107 | + char *tmp_path; | ||
| 108 | + uint8_t cs; | ||
| 109 | + const char *node; | ||
| 110 | + uint32_t page_addr; | ||
| 111 | +} AspeedSMCTestData; | ||
| 112 | + | ||
| 113 | +void aspeed_smc_test_read_jedec(const void *data); | ||
| 114 | +void aspeed_smc_test_erase_sector(const void *data); | ||
| 115 | +void aspeed_smc_test_erase_all(const void *data); | ||
| 116 | +void aspeed_smc_test_write_page(const void *data); | ||
| 117 | +void aspeed_smc_test_read_page_mem(const void *data); | ||
| 118 | +void aspeed_smc_test_write_page_mem(const void *data); | ||
| 119 | +void aspeed_smc_test_read_status_reg(const void *data); | ||
| 120 | +void aspeed_smc_test_status_reg_write_protection(const void *data); | ||
| 121 | +void aspeed_smc_test_write_block_protect(const void *data); | ||
| 122 | +void aspeed_smc_test_write_block_protect_bottom_bit(const void *data); | ||
| 123 | +void aspeed_smc_test_write_page_qpi(const void *data); | ||
| 124 | + | ||
| 125 | +#endif /* TESTS_ASPEED_SMC_UTILS_H */ | ||
| 126 | diff --git a/tests/qtest/aspeed-smc-utils.c b/tests/qtest/aspeed-smc-utils.c | ||
| 127 | new file mode 100644 | ||
| 128 | index XXXXXXX..XXXXXXX | ||
| 129 | --- /dev/null | ||
| 130 | +++ b/tests/qtest/aspeed-smc-utils.c | ||
| 131 | @@ -XXX,XX +XXX,XX @@ | ||
| 132 | +/* | ||
| 133 | + * QTest testcase for the M25P80 Flash (Using the Aspeed SPI | ||
| 134 | + * Controller) | ||
| 135 | + * | ||
| 136 | + * Copyright (C) 2016 IBM Corp. | ||
| 137 | + * | ||
| 138 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
| 139 | + * of this software and associated documentation files (the "Software"), to deal | ||
| 140 | + * in the Software without restriction, including without limitation the rights | ||
| 141 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
| 142 | + * copies of the Software, and to permit persons to whom the Software is | ||
| 143 | + * furnished to do so, subject to the following conditions: | ||
| 144 | + * | ||
| 145 | + * The above copyright notice and this permission notice shall be included in | ||
| 146 | + * all copies or substantial portions of the Software. | ||
| 147 | + * | ||
| 148 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 149 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 150 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 151 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 152 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
| 153 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
| 154 | + * THE SOFTWARE. | ||
| 155 | + */ | ||
| 156 | + | ||
| 157 | +#include "qemu/osdep.h" | ||
| 158 | +#include "qemu/bswap.h" | ||
| 159 | +#include "libqtest-single.h" | ||
| 160 | +#include "qemu/bitops.h" | ||
| 161 | +#include "aspeed-smc-utils.h" | ||
| 162 | + | ||
| 163 | +/* | ||
| 164 | + * Use an explicit bswap for the values read/wrote to the flash region | ||
| 165 | + * as they are BE and the Aspeed CPU is LE. | ||
| 166 | + */ | ||
| 167 | +static inline uint32_t make_be32(uint32_t data) | ||
| 168 | +{ | ||
| 169 | + return bswap32(data); | ||
| 170 | +} | ||
| 171 | + | ||
| 172 | +static inline void spi_writel(const AspeedSMCTestData *data, uint64_t offset, | ||
| 173 | + uint32_t value) | ||
| 174 | +{ | ||
| 175 | + qtest_writel(data->s, data->spi_base + offset, value); | ||
| 176 | +} | ||
| 177 | + | ||
| 178 | +static inline uint32_t spi_readl(const AspeedSMCTestData *data, uint64_t offset) | ||
| 179 | +{ | ||
| 180 | + return qtest_readl(data->s, data->spi_base + offset); | ||
| 181 | +} | ||
| 182 | + | ||
| 183 | +static inline void flash_writeb(const AspeedSMCTestData *data, uint64_t offset, | ||
| 184 | + uint8_t value) | ||
| 185 | +{ | ||
| 186 | + qtest_writeb(data->s, data->flash_base + offset, value); | ||
| 187 | +} | ||
| 188 | + | ||
| 189 | +static inline void flash_writel(const AspeedSMCTestData *data, uint64_t offset, | ||
| 190 | + uint32_t value) | ||
| 191 | +{ | ||
| 192 | + qtest_writel(data->s, data->flash_base + offset, value); | ||
| 193 | +} | ||
| 194 | + | ||
| 195 | +static inline uint8_t flash_readb(const AspeedSMCTestData *data, | ||
| 196 | + uint64_t offset) | ||
| 197 | +{ | ||
| 198 | + return qtest_readb(data->s, data->flash_base + offset); | ||
| 199 | +} | ||
| 200 | + | ||
| 201 | +static inline uint32_t flash_readl(const AspeedSMCTestData *data, | ||
| 202 | + uint64_t offset) | ||
| 203 | +{ | ||
| 204 | + return qtest_readl(data->s, data->flash_base + offset); | ||
| 205 | +} | ||
| 206 | + | ||
| 207 | +static void spi_conf(const AspeedSMCTestData *data, uint32_t value) | ||
| 208 | +{ | ||
| 209 | + uint32_t conf = spi_readl(data, R_CONF); | ||
| 210 | + | ||
| 211 | + conf |= value; | ||
| 212 | + spi_writel(data, R_CONF, conf); | ||
| 213 | +} | ||
| 214 | + | ||
| 215 | +static void spi_conf_remove(const AspeedSMCTestData *data, uint32_t value) | ||
| 216 | +{ | ||
| 217 | + uint32_t conf = spi_readl(data, R_CONF); | ||
| 218 | + | ||
| 219 | + conf &= ~value; | ||
| 220 | + spi_writel(data, R_CONF, conf); | ||
| 221 | +} | ||
| 222 | + | ||
| 223 | +static void spi_ce_ctrl(const AspeedSMCTestData *data, uint32_t value) | ||
| 224 | +{ | ||
| 225 | + uint32_t conf = spi_readl(data, R_CE_CTRL); | ||
| 226 | + | ||
| 227 | + conf |= value; | ||
| 228 | + spi_writel(data, R_CE_CTRL, conf); | ||
| 229 | +} | ||
| 230 | + | ||
| 231 | +static void spi_ctrl_setmode(const AspeedSMCTestData *data, uint8_t mode, | ||
| 232 | + uint8_t cmd) | ||
| 233 | +{ | ||
| 234 | + uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 235 | + uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 236 | + ctrl &= ~(CTRL_USERMODE | 0xff << 16); | ||
| 237 | + ctrl |= mode | (cmd << 16); | ||
| 238 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 239 | +} | ||
| 240 | + | ||
| 241 | +static void spi_ctrl_start_user(const AspeedSMCTestData *data) | ||
| 242 | +{ | ||
| 243 | + uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 244 | + uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 245 | + | ||
| 246 | + ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; | ||
| 247 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 248 | + | ||
| 249 | + ctrl &= ~CTRL_CE_STOP_ACTIVE; | ||
| 250 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 251 | +} | ||
| 252 | + | ||
| 253 | +static void spi_ctrl_stop_user(const AspeedSMCTestData *data) | ||
| 254 | +{ | ||
| 255 | + uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 256 | + uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 257 | + | ||
| 258 | + ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; | ||
| 259 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 260 | +} | ||
| 261 | + | ||
| 262 | +static void spi_ctrl_set_io_mode(const AspeedSMCTestData *data, uint32_t value) | ||
| 263 | +{ | ||
| 264 | + uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 265 | + uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 266 | + uint32_t mode; | ||
| 267 | + | ||
| 268 | + mode = value & CTRL_IO_MODE_MASK; | ||
| 269 | + ctrl &= ~CTRL_IO_MODE_MASK; | ||
| 270 | + ctrl |= mode; | ||
| 271 | + spi_writel(data, ctrl_reg, ctrl); | ||
| 272 | +} | ||
| 273 | + | ||
| 274 | +static void flash_reset(const AspeedSMCTestData *data) | ||
| 275 | +{ | ||
| 276 | + spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs)); | ||
| 277 | + | ||
| 278 | + spi_ctrl_start_user(data); | ||
| 279 | + flash_writeb(data, 0, RESET_ENABLE); | ||
| 280 | + flash_writeb(data, 0, RESET_MEMORY); | ||
| 281 | + flash_writeb(data, 0, WREN); | ||
| 282 | + flash_writeb(data, 0, BULK_ERASE); | ||
| 283 | + flash_writeb(data, 0, WRDI); | ||
| 284 | + spi_ctrl_stop_user(data); | ||
| 285 | + | ||
| 286 | + spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs)); | ||
| 287 | +} | ||
| 288 | + | ||
| 289 | +static void read_page(const AspeedSMCTestData *data, uint32_t addr, | ||
| 290 | + uint32_t *page) | ||
| 291 | +{ | ||
| 292 | + int i; | ||
| 293 | + | ||
| 294 | + spi_ctrl_start_user(data); | ||
| 295 | + | ||
| 296 | + flash_writeb(data, 0, EN_4BYTE_ADDR); | ||
| 297 | + flash_writeb(data, 0, READ); | ||
| 298 | + flash_writel(data, 0, make_be32(addr)); | ||
| 299 | + | ||
| 300 | + /* Continuous read are supported */ | ||
| 301 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 302 | + page[i] = make_be32(flash_readl(data, 0)); | ||
| 303 | + } | ||
| 304 | + spi_ctrl_stop_user(data); | ||
| 305 | +} | ||
| 306 | + | ||
| 307 | +static void read_page_mem(const AspeedSMCTestData *data, uint32_t addr, | ||
| 308 | + uint32_t *page) | ||
| 309 | +{ | ||
| 310 | + int i; | ||
| 311 | + | ||
| 312 | + /* move out USER mode to use direct reads from the AHB bus */ | ||
| 313 | + spi_ctrl_setmode(data, CTRL_READMODE, READ); | ||
| 314 | + | ||
| 315 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 316 | + page[i] = make_be32(flash_readl(data, addr + i * 4)); | ||
| 317 | + } | ||
| 318 | +} | ||
| 319 | + | ||
| 320 | +static void write_page_mem(const AspeedSMCTestData *data, uint32_t addr, | ||
| 321 | + uint32_t write_value) | ||
| 322 | +{ | ||
| 323 | + spi_ctrl_setmode(data, CTRL_WRITEMODE, PP); | ||
| 324 | + | ||
| 325 | + for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 326 | + flash_writel(data, addr + i * 4, write_value); | ||
| 327 | + } | ||
| 328 | +} | ||
| 329 | + | ||
| 330 | +static void assert_page_mem(const AspeedSMCTestData *data, uint32_t addr, | ||
| 331 | + uint32_t expected_value) | ||
| 332 | +{ | ||
| 333 | + uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 334 | + read_page_mem(data, addr, page); | ||
| 335 | + for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 336 | + g_assert_cmphex(page[i], ==, expected_value); | ||
| 337 | + } | ||
| 338 | +} | ||
| 339 | + | ||
| 340 | +void aspeed_smc_test_read_jedec(const void *data) | ||
| 341 | +{ | ||
| 342 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 343 | + uint32_t jedec = 0x0; | ||
| 344 | + | ||
| 345 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 346 | + | ||
| 347 | + spi_ctrl_start_user(test_data); | ||
| 348 | + flash_writeb(test_data, 0, JEDEC_READ); | ||
| 349 | + jedec |= flash_readb(test_data, 0) << 16; | ||
| 350 | + jedec |= flash_readb(test_data, 0) << 8; | ||
| 351 | + jedec |= flash_readb(test_data, 0); | ||
| 352 | + spi_ctrl_stop_user(test_data); | ||
| 353 | + | ||
| 354 | + flash_reset(test_data); | ||
| 355 | + | ||
| 356 | + g_assert_cmphex(jedec, ==, test_data->jedec_id); | ||
| 357 | +} | ||
| 358 | + | ||
| 359 | +void aspeed_smc_test_erase_sector(const void *data) | ||
| 360 | +{ | ||
| 361 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 362 | + uint32_t some_page_addr = test_data->page_addr; | ||
| 363 | + uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 364 | + int i; | ||
| 365 | + | ||
| 366 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 367 | + | ||
| 368 | + /* | ||
| 369 | + * Previous page should be full of 0xffs after backend is | ||
| 370 | + * initialized | ||
| 371 | + */ | ||
| 372 | + read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); | ||
| 373 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 374 | + g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 375 | + } | ||
| 376 | + | ||
| 377 | + spi_ctrl_start_user(test_data); | ||
| 378 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 379 | + flash_writeb(test_data, 0, WREN); | ||
| 380 | + flash_writeb(test_data, 0, PP); | ||
| 381 | + flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 382 | + | ||
| 383 | + /* Fill the page with its own addresses */ | ||
| 384 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 385 | + flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); | ||
| 386 | + } | ||
| 387 | + spi_ctrl_stop_user(test_data); | ||
| 388 | + | ||
| 389 | + /* Check the page is correctly written */ | ||
| 390 | + read_page(test_data, some_page_addr, page); | ||
| 391 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 392 | + g_assert_cmphex(page[i], ==, some_page_addr + i * 4); | ||
| 393 | + } | ||
| 394 | + | ||
| 395 | + spi_ctrl_start_user(test_data); | ||
| 396 | + flash_writeb(test_data, 0, WREN); | ||
| 397 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 398 | + flash_writeb(test_data, 0, ERASE_SECTOR); | ||
| 399 | + flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 400 | + spi_ctrl_stop_user(test_data); | ||
| 401 | + | ||
| 402 | + /* Check the page is erased */ | ||
| 403 | + read_page(test_data, some_page_addr, page); | ||
| 404 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 405 | + g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 406 | + } | ||
| 407 | + | ||
| 408 | + flash_reset(test_data); | ||
| 409 | +} | ||
| 410 | + | ||
| 411 | +void aspeed_smc_test_erase_all(const void *data) | ||
| 412 | +{ | ||
| 413 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 414 | + uint32_t some_page_addr = test_data->page_addr; | ||
| 415 | + uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 416 | + int i; | ||
| 417 | + | ||
| 418 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 419 | + | ||
| 420 | + /* | ||
| 421 | + * Previous page should be full of 0xffs after backend is | ||
| 422 | + * initialized | ||
| 423 | + */ | ||
| 424 | + read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); | ||
| 425 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 426 | + g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 427 | + } | ||
| 428 | + | ||
| 429 | + spi_ctrl_start_user(test_data); | ||
| 430 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 431 | + flash_writeb(test_data, 0, WREN); | ||
| 432 | + flash_writeb(test_data, 0, PP); | ||
| 433 | + flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 434 | + | ||
| 435 | + /* Fill the page with its own addresses */ | ||
| 436 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 437 | + flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); | ||
| 438 | + } | ||
| 439 | + spi_ctrl_stop_user(test_data); | ||
| 440 | + | ||
| 441 | + /* Check the page is correctly written */ | ||
| 442 | + read_page(test_data, some_page_addr, page); | ||
| 443 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 444 | + g_assert_cmphex(page[i], ==, some_page_addr + i * 4); | ||
| 445 | + } | ||
| 446 | + | ||
| 447 | + spi_ctrl_start_user(test_data); | ||
| 448 | + flash_writeb(test_data, 0, WREN); | ||
| 449 | + flash_writeb(test_data, 0, BULK_ERASE); | ||
| 450 | + spi_ctrl_stop_user(test_data); | ||
| 451 | + | ||
| 452 | + /* Check the page is erased */ | ||
| 453 | + read_page(test_data, some_page_addr, page); | ||
| 454 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 455 | + g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 456 | + } | ||
| 457 | + | ||
| 458 | + flash_reset(test_data); | ||
| 459 | +} | ||
| 460 | + | ||
| 461 | +void aspeed_smc_test_write_page(const void *data) | ||
| 462 | +{ | ||
| 463 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 464 | + uint32_t my_page_addr = test_data->page_addr; | ||
| 465 | + uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; | ||
| 466 | + uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 467 | + int i; | ||
| 468 | + | ||
| 469 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 470 | + | ||
| 471 | + spi_ctrl_start_user(test_data); | ||
| 472 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 473 | + flash_writeb(test_data, 0, WREN); | ||
| 474 | + flash_writeb(test_data, 0, PP); | ||
| 475 | + flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 476 | + | ||
| 477 | + /* Fill the page with its own addresses */ | ||
| 478 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 479 | + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 480 | + } | ||
| 481 | + spi_ctrl_stop_user(test_data); | ||
| 482 | + | ||
| 483 | + /* Check what was written */ | ||
| 484 | + read_page(test_data, my_page_addr, page); | ||
| 485 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 486 | + g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 487 | + } | ||
| 488 | + | ||
| 489 | + /* Check some other page. It should be full of 0xff */ | ||
| 490 | + read_page(test_data, some_page_addr, page); | ||
| 491 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 492 | + g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 493 | + } | ||
| 494 | + | ||
| 495 | + flash_reset(test_data); | ||
| 496 | +} | ||
| 497 | + | ||
| 498 | +void aspeed_smc_test_read_page_mem(const void *data) | ||
| 499 | +{ | ||
| 500 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 501 | + uint32_t my_page_addr = test_data->page_addr; | ||
| 502 | + uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; | ||
| 503 | + uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 504 | + int i; | ||
| 505 | + | ||
| 506 | + /* | ||
| 507 | + * Enable 4BYTE mode for controller. | ||
| 508 | + */ | ||
| 509 | + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 510 | + | ||
| 511 | + /* Enable 4BYTE mode for flash. */ | ||
| 512 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 513 | + spi_ctrl_start_user(test_data); | ||
| 514 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 515 | + flash_writeb(test_data, 0, WREN); | ||
| 516 | + flash_writeb(test_data, 0, PP); | ||
| 517 | + flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 518 | + | ||
| 519 | + /* Fill the page with its own addresses */ | ||
| 520 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 521 | + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 522 | + } | ||
| 523 | + spi_ctrl_stop_user(test_data); | ||
| 524 | + spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 525 | + | ||
| 526 | + /* Check what was written */ | ||
| 527 | + read_page_mem(test_data, my_page_addr, page); | ||
| 528 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 529 | + g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 530 | + } | ||
| 531 | + | ||
| 532 | + /* Check some other page. It should be full of 0xff */ | ||
| 533 | + read_page_mem(test_data, some_page_addr, page); | ||
| 534 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 535 | + g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 536 | + } | ||
| 537 | + | ||
| 538 | + flash_reset(test_data); | ||
| 539 | +} | ||
| 540 | + | ||
| 541 | +void aspeed_smc_test_write_page_mem(const void *data) | ||
| 542 | +{ | ||
| 543 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 544 | + uint32_t my_page_addr = test_data->page_addr; | ||
| 545 | + uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 546 | + int i; | ||
| 547 | + | ||
| 548 | + /* | ||
| 549 | + * Enable 4BYTE mode for controller. | ||
| 550 | + */ | ||
| 551 | + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 552 | + | ||
| 553 | + /* Enable 4BYTE mode for flash. */ | ||
| 554 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 555 | + spi_ctrl_start_user(test_data); | ||
| 556 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 557 | + flash_writeb(test_data, 0, WREN); | ||
| 558 | + spi_ctrl_stop_user(test_data); | ||
| 559 | + | ||
| 560 | + /* move out USER mode to use direct writes to the AHB bus */ | ||
| 561 | + spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP); | ||
| 562 | + | ||
| 563 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 564 | + flash_writel(test_data, my_page_addr + i * 4, | ||
| 565 | + make_be32(my_page_addr + i * 4)); | ||
| 566 | + } | ||
| 567 | + | ||
| 568 | + /* Check what was written */ | ||
| 569 | + read_page_mem(test_data, my_page_addr, page); | ||
| 570 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 571 | + g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 572 | + } | ||
| 573 | + | ||
| 574 | + flash_reset(test_data); | ||
| 575 | +} | ||
| 576 | + | ||
| 577 | +void aspeed_smc_test_read_status_reg(const void *data) | ||
| 578 | +{ | ||
| 579 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 580 | + uint8_t r; | ||
| 581 | + | ||
| 582 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 583 | + | ||
| 584 | + spi_ctrl_start_user(test_data); | ||
| 585 | + flash_writeb(test_data, 0, RDSR); | ||
| 586 | + r = flash_readb(test_data, 0); | ||
| 587 | + spi_ctrl_stop_user(test_data); | ||
| 588 | + | ||
| 589 | + g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 590 | + g_assert(!qtest_qom_get_bool | ||
| 591 | + (test_data->s, test_data->node, "write-enable")); | ||
| 592 | + | ||
| 593 | + spi_ctrl_start_user(test_data); | ||
| 594 | + flash_writeb(test_data, 0, WREN); | ||
| 595 | + flash_writeb(test_data, 0, RDSR); | ||
| 596 | + r = flash_readb(test_data, 0); | ||
| 597 | + spi_ctrl_stop_user(test_data); | ||
| 598 | + | ||
| 599 | + g_assert_cmphex(r & SR_WEL, ==, SR_WEL); | ||
| 600 | + g_assert(qtest_qom_get_bool | ||
| 601 | + (test_data->s, test_data->node, "write-enable")); | ||
| 602 | + | ||
| 603 | + spi_ctrl_start_user(test_data); | ||
| 604 | + flash_writeb(test_data, 0, WRDI); | ||
| 605 | + flash_writeb(test_data, 0, RDSR); | ||
| 606 | + r = flash_readb(test_data, 0); | ||
| 607 | + spi_ctrl_stop_user(test_data); | ||
| 608 | + | ||
| 609 | + g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 610 | + g_assert(!qtest_qom_get_bool | ||
| 611 | + (test_data->s, test_data->node, "write-enable")); | ||
| 612 | + | ||
| 613 | + flash_reset(test_data); | ||
| 614 | +} | ||
| 615 | + | ||
| 616 | +void aspeed_smc_test_status_reg_write_protection(const void *data) | ||
| 617 | +{ | ||
| 618 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 619 | + uint8_t r; | ||
| 620 | + | ||
| 621 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 622 | + | ||
| 623 | + /* default case: WP# is high and SRWD is low -> status register writable */ | ||
| 624 | + spi_ctrl_start_user(test_data); | ||
| 625 | + flash_writeb(test_data, 0, WREN); | ||
| 626 | + /* test ability to write SRWD */ | ||
| 627 | + flash_writeb(test_data, 0, WRSR); | ||
| 628 | + flash_writeb(test_data, 0, SRWD); | ||
| 629 | + flash_writeb(test_data, 0, RDSR); | ||
| 630 | + r = flash_readb(test_data, 0); | ||
| 631 | + spi_ctrl_stop_user(test_data); | ||
| 632 | + g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 633 | + | ||
| 634 | + /* WP# high and SRWD high -> status register writable */ | ||
| 635 | + spi_ctrl_start_user(test_data); | ||
| 636 | + flash_writeb(test_data, 0, WREN); | ||
| 637 | + /* test ability to write SRWD */ | ||
| 638 | + flash_writeb(test_data, 0, WRSR); | ||
| 639 | + flash_writeb(test_data, 0, 0); | ||
| 640 | + flash_writeb(test_data, 0, RDSR); | ||
| 641 | + r = flash_readb(test_data, 0); | ||
| 642 | + spi_ctrl_stop_user(test_data); | ||
| 643 | + g_assert_cmphex(r & SRWD, ==, 0); | ||
| 644 | + | ||
| 645 | + /* WP# low and SRWD low -> status register writable */ | ||
| 646 | + qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0); | ||
| 647 | + spi_ctrl_start_user(test_data); | ||
| 648 | + flash_writeb(test_data, 0, WREN); | ||
| 649 | + /* test ability to write SRWD */ | ||
| 650 | + flash_writeb(test_data, 0, WRSR); | ||
| 651 | + flash_writeb(test_data, 0, SRWD); | ||
| 652 | + flash_writeb(test_data, 0, RDSR); | ||
| 653 | + r = flash_readb(test_data, 0); | ||
| 654 | + spi_ctrl_stop_user(test_data); | ||
| 655 | + g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 656 | + | ||
| 657 | + /* WP# low and SRWD high -> status register NOT writable */ | ||
| 658 | + spi_ctrl_start_user(test_data); | ||
| 659 | + flash_writeb(test_data, 0 , WREN); | ||
| 660 | + /* test ability to write SRWD */ | ||
| 661 | + flash_writeb(test_data, 0, WRSR); | ||
| 662 | + flash_writeb(test_data, 0, 0); | ||
| 663 | + flash_writeb(test_data, 0, RDSR); | ||
| 664 | + r = flash_readb(test_data, 0); | ||
| 665 | + spi_ctrl_stop_user(test_data); | ||
| 666 | + /* write is not successful */ | ||
| 667 | + g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 668 | + | ||
| 669 | + qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1); | ||
| 670 | + flash_reset(test_data); | ||
| 671 | +} | ||
| 672 | + | ||
| 673 | +void aspeed_smc_test_write_block_protect(const void *data) | ||
| 674 | +{ | ||
| 675 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 676 | + uint32_t sector_size = 65536; | ||
| 677 | + uint32_t n_sectors = 512; | ||
| 678 | + | ||
| 679 | + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 680 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 681 | + | ||
| 682 | + uint32_t bp_bits = 0b0; | ||
| 683 | + | ||
| 684 | + for (int i = 0; i < 16; i++) { | ||
| 685 | + bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2); | ||
| 686 | + | ||
| 687 | + spi_ctrl_start_user(test_data); | ||
| 688 | + flash_writeb(test_data, 0, WREN); | ||
| 689 | + flash_writeb(test_data, 0, BULK_ERASE); | ||
| 690 | + flash_writeb(test_data, 0, WREN); | ||
| 691 | + flash_writeb(test_data, 0, WRSR); | ||
| 692 | + flash_writeb(test_data, 0, bp_bits); | ||
| 693 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 694 | + flash_writeb(test_data, 0, WREN); | ||
| 695 | + spi_ctrl_stop_user(test_data); | ||
| 696 | + | ||
| 697 | + uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0; | ||
| 698 | + uint32_t protection_start = n_sectors - num_protected_sectors; | ||
| 699 | + uint32_t protection_end = n_sectors; | ||
| 700 | + | ||
| 701 | + for (int sector = 0; sector < n_sectors; sector++) { | ||
| 702 | + uint32_t addr = sector * sector_size; | ||
| 703 | + | ||
| 704 | + assert_page_mem(test_data, addr, 0xffffffff); | ||
| 705 | + write_page_mem(test_data, addr, make_be32(0xabcdef12)); | ||
| 706 | + | ||
| 707 | + uint32_t expected_value = protection_start <= sector | ||
| 708 | + && sector < protection_end | ||
| 709 | + ? 0xffffffff : 0xabcdef12; | ||
| 710 | + | ||
| 711 | + assert_page_mem(test_data, addr, expected_value); | ||
| 712 | + } | ||
| 713 | + } | ||
| 714 | + | ||
| 715 | + flash_reset(test_data); | ||
| 716 | +} | ||
| 717 | + | ||
| 718 | +void aspeed_smc_test_write_block_protect_bottom_bit(const void *data) | ||
| 719 | +{ | ||
| 720 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 721 | + uint32_t sector_size = 65536; | ||
| 722 | + uint32_t n_sectors = 512; | ||
| 723 | + | ||
| 724 | + spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 725 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 726 | + | ||
| 727 | + /* top bottom bit is enabled */ | ||
| 728 | + uint32_t bp_bits = 0b00100 << 3; | ||
| 729 | + | ||
| 730 | + for (int i = 0; i < 16; i++) { | ||
| 731 | + bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2); | ||
| 732 | + | ||
| 733 | + spi_ctrl_start_user(test_data); | ||
| 734 | + flash_writeb(test_data, 0, WREN); | ||
| 735 | + flash_writeb(test_data, 0, BULK_ERASE); | ||
| 736 | + flash_writeb(test_data, 0, WREN); | ||
| 737 | + flash_writeb(test_data, 0, WRSR); | ||
| 738 | + flash_writeb(test_data, 0, bp_bits); | ||
| 739 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 740 | + flash_writeb(test_data, 0, WREN); | ||
| 741 | + spi_ctrl_stop_user(test_data); | ||
| 742 | + | ||
| 743 | + uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0; | ||
| 744 | + uint32_t protection_start = 0; | ||
| 745 | + uint32_t protection_end = num_protected_sectors; | ||
| 746 | + | ||
| 747 | + for (int sector = 0; sector < n_sectors; sector++) { | ||
| 748 | + uint32_t addr = sector * sector_size; | ||
| 749 | + | ||
| 750 | + assert_page_mem(test_data, addr, 0xffffffff); | ||
| 751 | + write_page_mem(test_data, addr, make_be32(0xabcdef12)); | ||
| 752 | + | ||
| 753 | + uint32_t expected_value = protection_start <= sector | ||
| 754 | + && sector < protection_end | ||
| 755 | + ? 0xffffffff : 0xabcdef12; | ||
| 756 | + | ||
| 757 | + assert_page_mem(test_data, addr, expected_value); | ||
| 758 | + } | ||
| 759 | + } | ||
| 760 | + | ||
| 761 | + flash_reset(test_data); | ||
| 762 | +} | ||
| 763 | + | ||
| 764 | +void aspeed_smc_test_write_page_qpi(const void *data) | ||
| 765 | +{ | ||
| 766 | + const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data; | ||
| 767 | + uint32_t my_page_addr = test_data->page_addr; | ||
| 768 | + uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; | ||
| 769 | + uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 770 | + uint32_t page_pattern[] = { | ||
| 771 | + 0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf | ||
| 772 | + }; | ||
| 773 | + int i; | ||
| 774 | + | ||
| 775 | + spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 776 | + | ||
| 777 | + spi_ctrl_start_user(test_data); | ||
| 778 | + flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 779 | + flash_writeb(test_data, 0, WREN); | ||
| 780 | + flash_writeb(test_data, 0, PP); | ||
| 781 | + flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 782 | + | ||
| 783 | + /* Set QPI mode */ | ||
| 784 | + spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO); | ||
| 785 | + | ||
| 786 | + /* Fill the page pattern */ | ||
| 787 | + for (i = 0; i < ARRAY_SIZE(page_pattern); i++) { | ||
| 788 | + flash_writel(test_data, 0, make_be32(page_pattern[i])); | ||
| 789 | + } | ||
| 790 | + | ||
| 791 | + /* Fill the page with its own addresses */ | ||
| 792 | + for (; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 793 | + flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 794 | + } | ||
| 795 | + | ||
| 796 | + /* Restore io mode */ | ||
| 797 | + spi_ctrl_set_io_mode(test_data, 0); | ||
| 798 | + spi_ctrl_stop_user(test_data); | ||
| 799 | + | ||
| 800 | + /* Check what was written */ | ||
| 801 | + read_page(test_data, my_page_addr, page); | ||
| 802 | + for (i = 0; i < ARRAY_SIZE(page_pattern); i++) { | ||
| 803 | + g_assert_cmphex(page[i], ==, page_pattern[i]); | ||
| 804 | + } | ||
| 805 | + for (; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 806 | + g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 807 | + } | ||
| 808 | + | ||
| 809 | + /* Check some other page. It should be full of 0xff */ | ||
| 810 | + read_page(test_data, some_page_addr, page); | ||
| 811 | + for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 812 | + g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 813 | + } | ||
| 814 | + | ||
| 815 | + flash_reset(test_data); | ||
| 816 | +} | ||
| 817 | + | ||
| 818 | diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | 819 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/arm/aspeed_ast10x0.c | 820 | --- a/tests/qtest/aspeed_smc-test.c |
| 20 | +++ b/hw/arm/aspeed_ast10x0.c | 821 | +++ b/tests/qtest/aspeed_smc-test.c |
| 21 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj) | 822 | @@ -XXX,XX +XXX,XX @@ |
| 22 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | 823 | #include "qemu/bswap.h" |
| 23 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); | 824 | #include "libqtest-single.h" |
| 24 | } | 825 | #include "qemu/bitops.h" |
| 25 | + | 826 | +#include "aspeed-smc-utils.h" |
| 26 | + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | 827 | |
| 27 | + object_initialize_child(obj, "gpio", &s->gpio, typename); | 828 | -/* |
| 829 | - * ASPEED SPI Controller registers | ||
| 830 | - */ | ||
| 831 | -#define R_CONF 0x00 | ||
| 832 | -#define CONF_ENABLE_W0 16 | ||
| 833 | -#define R_CE_CTRL 0x04 | ||
| 834 | -#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ | ||
| 835 | -#define R_CTRL0 0x10 | ||
| 836 | -#define CTRL_IO_QUAD_IO BIT(31) | ||
| 837 | -#define CTRL_CE_STOP_ACTIVE BIT(2) | ||
| 838 | -#define CTRL_READMODE 0x0 | ||
| 839 | -#define CTRL_FREADMODE 0x1 | ||
| 840 | -#define CTRL_WRITEMODE 0x2 | ||
| 841 | -#define CTRL_USERMODE 0x3 | ||
| 842 | -#define SR_WEL BIT(1) | ||
| 843 | - | ||
| 844 | -/* | ||
| 845 | - * Flash commands | ||
| 846 | - */ | ||
| 847 | -enum { | ||
| 848 | - JEDEC_READ = 0x9f, | ||
| 849 | - RDSR = 0x5, | ||
| 850 | - WRDI = 0x4, | ||
| 851 | - BULK_ERASE = 0xc7, | ||
| 852 | - READ = 0x03, | ||
| 853 | - PP = 0x02, | ||
| 854 | - WRSR = 0x1, | ||
| 855 | - WREN = 0x6, | ||
| 856 | - SRWD = 0x80, | ||
| 857 | - RESET_ENABLE = 0x66, | ||
| 858 | - RESET_MEMORY = 0x99, | ||
| 859 | - EN_4BYTE_ADDR = 0xB7, | ||
| 860 | - ERASE_SECTOR = 0xd8, | ||
| 861 | -}; | ||
| 862 | - | ||
| 863 | -#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28)) | ||
| 864 | -#define FLASH_PAGE_SIZE 256 | ||
| 865 | - | ||
| 866 | -typedef struct TestData { | ||
| 867 | - QTestState *s; | ||
| 868 | - uint64_t spi_base; | ||
| 869 | - uint64_t flash_base; | ||
| 870 | - uint32_t jedec_id; | ||
| 871 | - char *tmp_path; | ||
| 872 | - uint8_t cs; | ||
| 873 | - const char *node; | ||
| 874 | - uint32_t page_addr; | ||
| 875 | -} TestData; | ||
| 876 | - | ||
| 877 | -/* | ||
| 878 | - * Use an explicit bswap for the values read/wrote to the flash region | ||
| 879 | - * as they are BE and the Aspeed CPU is LE. | ||
| 880 | - */ | ||
| 881 | -static inline uint32_t make_be32(uint32_t data) | ||
| 882 | -{ | ||
| 883 | - return bswap32(data); | ||
| 884 | -} | ||
| 885 | - | ||
| 886 | -static inline void spi_writel(const TestData *data, uint64_t offset, | ||
| 887 | - uint32_t value) | ||
| 888 | -{ | ||
| 889 | - qtest_writel(data->s, data->spi_base + offset, value); | ||
| 890 | -} | ||
| 891 | - | ||
| 892 | -static inline uint32_t spi_readl(const TestData *data, uint64_t offset) | ||
| 893 | -{ | ||
| 894 | - return qtest_readl(data->s, data->spi_base + offset); | ||
| 895 | -} | ||
| 896 | - | ||
| 897 | -static inline void flash_writeb(const TestData *data, uint64_t offset, | ||
| 898 | - uint8_t value) | ||
| 899 | -{ | ||
| 900 | - qtest_writeb(data->s, data->flash_base + offset, value); | ||
| 901 | -} | ||
| 902 | - | ||
| 903 | -static inline void flash_writel(const TestData *data, uint64_t offset, | ||
| 904 | - uint32_t value) | ||
| 905 | -{ | ||
| 906 | - qtest_writel(data->s, data->flash_base + offset, value); | ||
| 907 | -} | ||
| 908 | - | ||
| 909 | -static inline uint8_t flash_readb(const TestData *data, uint64_t offset) | ||
| 910 | -{ | ||
| 911 | - return qtest_readb(data->s, data->flash_base + offset); | ||
| 912 | -} | ||
| 913 | - | ||
| 914 | -static inline uint32_t flash_readl(const TestData *data, uint64_t offset) | ||
| 915 | -{ | ||
| 916 | - return qtest_readl(data->s, data->flash_base + offset); | ||
| 917 | -} | ||
| 918 | - | ||
| 919 | -static void spi_conf(const TestData *data, uint32_t value) | ||
| 920 | -{ | ||
| 921 | - uint32_t conf = spi_readl(data, R_CONF); | ||
| 922 | - | ||
| 923 | - conf |= value; | ||
| 924 | - spi_writel(data, R_CONF, conf); | ||
| 925 | -} | ||
| 926 | - | ||
| 927 | -static void spi_conf_remove(const TestData *data, uint32_t value) | ||
| 928 | -{ | ||
| 929 | - uint32_t conf = spi_readl(data, R_CONF); | ||
| 930 | - | ||
| 931 | - conf &= ~value; | ||
| 932 | - spi_writel(data, R_CONF, conf); | ||
| 933 | -} | ||
| 934 | - | ||
| 935 | -static void spi_ce_ctrl(const TestData *data, uint32_t value) | ||
| 936 | -{ | ||
| 937 | - uint32_t conf = spi_readl(data, R_CE_CTRL); | ||
| 938 | - | ||
| 939 | - conf |= value; | ||
| 940 | - spi_writel(data, R_CE_CTRL, conf); | ||
| 941 | -} | ||
| 942 | - | ||
| 943 | -static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd) | ||
| 944 | -{ | ||
| 945 | - uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 946 | - uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 947 | - ctrl &= ~(CTRL_USERMODE | 0xff << 16); | ||
| 948 | - ctrl |= mode | (cmd << 16); | ||
| 949 | - spi_writel(data, ctrl_reg, ctrl); | ||
| 950 | -} | ||
| 951 | - | ||
| 952 | -static void spi_ctrl_start_user(const TestData *data) | ||
| 953 | -{ | ||
| 954 | - uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 955 | - uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 956 | - | ||
| 957 | - ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; | ||
| 958 | - spi_writel(data, ctrl_reg, ctrl); | ||
| 959 | - | ||
| 960 | - ctrl &= ~CTRL_CE_STOP_ACTIVE; | ||
| 961 | - spi_writel(data, ctrl_reg, ctrl); | ||
| 962 | -} | ||
| 963 | - | ||
| 964 | -static void spi_ctrl_stop_user(const TestData *data) | ||
| 965 | -{ | ||
| 966 | - uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 967 | - uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 968 | - | ||
| 969 | - ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; | ||
| 970 | - spi_writel(data, ctrl_reg, ctrl); | ||
| 971 | -} | ||
| 972 | - | ||
| 973 | -static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value) | ||
| 974 | -{ | ||
| 975 | - uint32_t ctrl_reg = R_CTRL0 + data->cs * 4; | ||
| 976 | - uint32_t ctrl = spi_readl(data, ctrl_reg); | ||
| 977 | - uint32_t mode; | ||
| 978 | - | ||
| 979 | - mode = value & CTRL_IO_MODE_MASK; | ||
| 980 | - ctrl &= ~CTRL_IO_MODE_MASK; | ||
| 981 | - ctrl |= mode; | ||
| 982 | - spi_writel(data, ctrl_reg, ctrl); | ||
| 983 | -} | ||
| 984 | - | ||
| 985 | -static void flash_reset(const TestData *data) | ||
| 986 | -{ | ||
| 987 | - spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs)); | ||
| 988 | - | ||
| 989 | - spi_ctrl_start_user(data); | ||
| 990 | - flash_writeb(data, 0, RESET_ENABLE); | ||
| 991 | - flash_writeb(data, 0, RESET_MEMORY); | ||
| 992 | - flash_writeb(data, 0, WREN); | ||
| 993 | - flash_writeb(data, 0, BULK_ERASE); | ||
| 994 | - flash_writeb(data, 0, WRDI); | ||
| 995 | - spi_ctrl_stop_user(data); | ||
| 996 | - | ||
| 997 | - spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs)); | ||
| 998 | -} | ||
| 999 | - | ||
| 1000 | -static void test_read_jedec(const void *data) | ||
| 1001 | -{ | ||
| 1002 | - const TestData *test_data = (const TestData *)data; | ||
| 1003 | - uint32_t jedec = 0x0; | ||
| 1004 | - | ||
| 1005 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1006 | - | ||
| 1007 | - spi_ctrl_start_user(test_data); | ||
| 1008 | - flash_writeb(test_data, 0, JEDEC_READ); | ||
| 1009 | - jedec |= flash_readb(test_data, 0) << 16; | ||
| 1010 | - jedec |= flash_readb(test_data, 0) << 8; | ||
| 1011 | - jedec |= flash_readb(test_data, 0); | ||
| 1012 | - spi_ctrl_stop_user(test_data); | ||
| 1013 | - | ||
| 1014 | - flash_reset(test_data); | ||
| 1015 | - | ||
| 1016 | - g_assert_cmphex(jedec, ==, test_data->jedec_id); | ||
| 1017 | -} | ||
| 1018 | - | ||
| 1019 | -static void read_page(const TestData *data, uint32_t addr, uint32_t *page) | ||
| 1020 | -{ | ||
| 1021 | - int i; | ||
| 1022 | - | ||
| 1023 | - spi_ctrl_start_user(data); | ||
| 1024 | - | ||
| 1025 | - flash_writeb(data, 0, EN_4BYTE_ADDR); | ||
| 1026 | - flash_writeb(data, 0, READ); | ||
| 1027 | - flash_writel(data, 0, make_be32(addr)); | ||
| 1028 | - | ||
| 1029 | - /* Continuous read are supported */ | ||
| 1030 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1031 | - page[i] = make_be32(flash_readl(data, 0)); | ||
| 1032 | - } | ||
| 1033 | - spi_ctrl_stop_user(data); | ||
| 1034 | -} | ||
| 1035 | - | ||
| 1036 | -static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *page) | ||
| 1037 | -{ | ||
| 1038 | - int i; | ||
| 1039 | - | ||
| 1040 | - /* move out USER mode to use direct reads from the AHB bus */ | ||
| 1041 | - spi_ctrl_setmode(data, CTRL_READMODE, READ); | ||
| 1042 | - | ||
| 1043 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1044 | - page[i] = make_be32(flash_readl(data, addr + i * 4)); | ||
| 1045 | - } | ||
| 1046 | -} | ||
| 1047 | - | ||
| 1048 | -static void write_page_mem(const TestData *data, uint32_t addr, | ||
| 1049 | - uint32_t write_value) | ||
| 1050 | -{ | ||
| 1051 | - spi_ctrl_setmode(data, CTRL_WRITEMODE, PP); | ||
| 1052 | - | ||
| 1053 | - for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1054 | - flash_writel(data, addr + i * 4, write_value); | ||
| 1055 | - } | ||
| 1056 | -} | ||
| 1057 | - | ||
| 1058 | -static void assert_page_mem(const TestData *data, uint32_t addr, | ||
| 1059 | - uint32_t expected_value) | ||
| 1060 | -{ | ||
| 1061 | - uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 1062 | - read_page_mem(data, addr, page); | ||
| 1063 | - for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1064 | - g_assert_cmphex(page[i], ==, expected_value); | ||
| 1065 | - } | ||
| 1066 | -} | ||
| 1067 | - | ||
| 1068 | -static void test_erase_sector(const void *data) | ||
| 1069 | -{ | ||
| 1070 | - const TestData *test_data = (const TestData *)data; | ||
| 1071 | - uint32_t some_page_addr = test_data->page_addr; | ||
| 1072 | - uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 1073 | - int i; | ||
| 1074 | - | ||
| 1075 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1076 | - | ||
| 1077 | - /* | ||
| 1078 | - * Previous page should be full of 0xffs after backend is | ||
| 1079 | - * initialized | ||
| 1080 | - */ | ||
| 1081 | - read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); | ||
| 1082 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1083 | - g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 1084 | - } | ||
| 1085 | - | ||
| 1086 | - spi_ctrl_start_user(test_data); | ||
| 1087 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1088 | - flash_writeb(test_data, 0, WREN); | ||
| 1089 | - flash_writeb(test_data, 0, PP); | ||
| 1090 | - flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 1091 | - | ||
| 1092 | - /* Fill the page with its own addresses */ | ||
| 1093 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1094 | - flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); | ||
| 1095 | - } | ||
| 1096 | - spi_ctrl_stop_user(test_data); | ||
| 1097 | - | ||
| 1098 | - /* Check the page is correctly written */ | ||
| 1099 | - read_page(test_data, some_page_addr, page); | ||
| 1100 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1101 | - g_assert_cmphex(page[i], ==, some_page_addr + i * 4); | ||
| 1102 | - } | ||
| 1103 | - | ||
| 1104 | - spi_ctrl_start_user(test_data); | ||
| 1105 | - flash_writeb(test_data, 0, WREN); | ||
| 1106 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1107 | - flash_writeb(test_data, 0, ERASE_SECTOR); | ||
| 1108 | - flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 1109 | - spi_ctrl_stop_user(test_data); | ||
| 1110 | - | ||
| 1111 | - /* Check the page is erased */ | ||
| 1112 | - read_page(test_data, some_page_addr, page); | ||
| 1113 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1114 | - g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 1115 | - } | ||
| 1116 | - | ||
| 1117 | - flash_reset(test_data); | ||
| 1118 | -} | ||
| 1119 | - | ||
| 1120 | -static void test_erase_all(const void *data) | ||
| 1121 | -{ | ||
| 1122 | - const TestData *test_data = (const TestData *)data; | ||
| 1123 | - uint32_t some_page_addr = test_data->page_addr; | ||
| 1124 | - uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 1125 | - int i; | ||
| 1126 | - | ||
| 1127 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1128 | - | ||
| 1129 | - /* | ||
| 1130 | - * Previous page should be full of 0xffs after backend is | ||
| 1131 | - * initialized | ||
| 1132 | - */ | ||
| 1133 | - read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page); | ||
| 1134 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1135 | - g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 1136 | - } | ||
| 1137 | - | ||
| 1138 | - spi_ctrl_start_user(test_data); | ||
| 1139 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1140 | - flash_writeb(test_data, 0, WREN); | ||
| 1141 | - flash_writeb(test_data, 0, PP); | ||
| 1142 | - flash_writel(test_data, 0, make_be32(some_page_addr)); | ||
| 1143 | - | ||
| 1144 | - /* Fill the page with its own addresses */ | ||
| 1145 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1146 | - flash_writel(test_data, 0, make_be32(some_page_addr + i * 4)); | ||
| 1147 | - } | ||
| 1148 | - spi_ctrl_stop_user(test_data); | ||
| 1149 | - | ||
| 1150 | - /* Check the page is correctly written */ | ||
| 1151 | - read_page(test_data, some_page_addr, page); | ||
| 1152 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1153 | - g_assert_cmphex(page[i], ==, some_page_addr + i * 4); | ||
| 1154 | - } | ||
| 1155 | - | ||
| 1156 | - spi_ctrl_start_user(test_data); | ||
| 1157 | - flash_writeb(test_data, 0, WREN); | ||
| 1158 | - flash_writeb(test_data, 0, BULK_ERASE); | ||
| 1159 | - spi_ctrl_stop_user(test_data); | ||
| 1160 | - | ||
| 1161 | - /* Check the page is erased */ | ||
| 1162 | - read_page(test_data, some_page_addr, page); | ||
| 1163 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1164 | - g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 1165 | - } | ||
| 1166 | - | ||
| 1167 | - flash_reset(test_data); | ||
| 1168 | -} | ||
| 1169 | - | ||
| 1170 | -static void test_write_page(const void *data) | ||
| 1171 | -{ | ||
| 1172 | - const TestData *test_data = (const TestData *)data; | ||
| 1173 | - uint32_t my_page_addr = test_data->page_addr; | ||
| 1174 | - uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; | ||
| 1175 | - uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 1176 | - int i; | ||
| 1177 | - | ||
| 1178 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1179 | - | ||
| 1180 | - spi_ctrl_start_user(test_data); | ||
| 1181 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1182 | - flash_writeb(test_data, 0, WREN); | ||
| 1183 | - flash_writeb(test_data, 0, PP); | ||
| 1184 | - flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 1185 | - | ||
| 1186 | - /* Fill the page with its own addresses */ | ||
| 1187 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1188 | - flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 1189 | - } | ||
| 1190 | - spi_ctrl_stop_user(test_data); | ||
| 1191 | - | ||
| 1192 | - /* Check what was written */ | ||
| 1193 | - read_page(test_data, my_page_addr, page); | ||
| 1194 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1195 | - g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 1196 | - } | ||
| 1197 | - | ||
| 1198 | - /* Check some other page. It should be full of 0xff */ | ||
| 1199 | - read_page(test_data, some_page_addr, page); | ||
| 1200 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1201 | - g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 1202 | - } | ||
| 1203 | - | ||
| 1204 | - flash_reset(test_data); | ||
| 1205 | -} | ||
| 1206 | - | ||
| 1207 | -static void test_read_page_mem(const void *data) | ||
| 1208 | -{ | ||
| 1209 | - const TestData *test_data = (const TestData *)data; | ||
| 1210 | - uint32_t my_page_addr = test_data->page_addr; | ||
| 1211 | - uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; | ||
| 1212 | - uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 1213 | - int i; | ||
| 1214 | - | ||
| 1215 | - /* | ||
| 1216 | - * Enable 4BYTE mode for controller. | ||
| 1217 | - */ | ||
| 1218 | - spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 1219 | - | ||
| 1220 | - /* Enable 4BYTE mode for flash. */ | ||
| 1221 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1222 | - spi_ctrl_start_user(test_data); | ||
| 1223 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1224 | - flash_writeb(test_data, 0, WREN); | ||
| 1225 | - flash_writeb(test_data, 0, PP); | ||
| 1226 | - flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 1227 | - | ||
| 1228 | - /* Fill the page with its own addresses */ | ||
| 1229 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1230 | - flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 1231 | - } | ||
| 1232 | - spi_ctrl_stop_user(test_data); | ||
| 1233 | - spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1234 | - | ||
| 1235 | - /* Check what was written */ | ||
| 1236 | - read_page_mem(test_data, my_page_addr, page); | ||
| 1237 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1238 | - g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 1239 | - } | ||
| 1240 | - | ||
| 1241 | - /* Check some other page. It should be full of 0xff */ | ||
| 1242 | - read_page_mem(test_data, some_page_addr, page); | ||
| 1243 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1244 | - g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 1245 | - } | ||
| 1246 | - | ||
| 1247 | - flash_reset(test_data); | ||
| 1248 | -} | ||
| 1249 | - | ||
| 1250 | -static void test_write_page_mem(const void *data) | ||
| 1251 | -{ | ||
| 1252 | - const TestData *test_data = (const TestData *)data; | ||
| 1253 | - uint32_t my_page_addr = test_data->page_addr; | ||
| 1254 | - uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 1255 | - int i; | ||
| 1256 | - | ||
| 1257 | - /* | ||
| 1258 | - * Enable 4BYTE mode for controller. | ||
| 1259 | - */ | ||
| 1260 | - spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 1261 | - | ||
| 1262 | - /* Enable 4BYTE mode for flash. */ | ||
| 1263 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1264 | - spi_ctrl_start_user(test_data); | ||
| 1265 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1266 | - flash_writeb(test_data, 0, WREN); | ||
| 1267 | - spi_ctrl_stop_user(test_data); | ||
| 1268 | - | ||
| 1269 | - /* move out USER mode to use direct writes to the AHB bus */ | ||
| 1270 | - spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP); | ||
| 1271 | - | ||
| 1272 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1273 | - flash_writel(test_data, my_page_addr + i * 4, | ||
| 1274 | - make_be32(my_page_addr + i * 4)); | ||
| 1275 | - } | ||
| 1276 | - | ||
| 1277 | - /* Check what was written */ | ||
| 1278 | - read_page_mem(test_data, my_page_addr, page); | ||
| 1279 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1280 | - g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 1281 | - } | ||
| 1282 | - | ||
| 1283 | - flash_reset(test_data); | ||
| 1284 | -} | ||
| 1285 | - | ||
| 1286 | -static void test_read_status_reg(const void *data) | ||
| 1287 | -{ | ||
| 1288 | - const TestData *test_data = (const TestData *)data; | ||
| 1289 | - uint8_t r; | ||
| 1290 | - | ||
| 1291 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1292 | - | ||
| 1293 | - spi_ctrl_start_user(test_data); | ||
| 1294 | - flash_writeb(test_data, 0, RDSR); | ||
| 1295 | - r = flash_readb(test_data, 0); | ||
| 1296 | - spi_ctrl_stop_user(test_data); | ||
| 1297 | - | ||
| 1298 | - g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 1299 | - g_assert(!qtest_qom_get_bool | ||
| 1300 | - (test_data->s, test_data->node, "write-enable")); | ||
| 1301 | - | ||
| 1302 | - spi_ctrl_start_user(test_data); | ||
| 1303 | - flash_writeb(test_data, 0, WREN); | ||
| 1304 | - flash_writeb(test_data, 0, RDSR); | ||
| 1305 | - r = flash_readb(test_data, 0); | ||
| 1306 | - spi_ctrl_stop_user(test_data); | ||
| 1307 | - | ||
| 1308 | - g_assert_cmphex(r & SR_WEL, ==, SR_WEL); | ||
| 1309 | - g_assert(qtest_qom_get_bool | ||
| 1310 | - (test_data->s, test_data->node, "write-enable")); | ||
| 1311 | - | ||
| 1312 | - spi_ctrl_start_user(test_data); | ||
| 1313 | - flash_writeb(test_data, 0, WRDI); | ||
| 1314 | - flash_writeb(test_data, 0, RDSR); | ||
| 1315 | - r = flash_readb(test_data, 0); | ||
| 1316 | - spi_ctrl_stop_user(test_data); | ||
| 1317 | - | ||
| 1318 | - g_assert_cmphex(r & SR_WEL, ==, 0); | ||
| 1319 | - g_assert(!qtest_qom_get_bool | ||
| 1320 | - (test_data->s, test_data->node, "write-enable")); | ||
| 1321 | - | ||
| 1322 | - flash_reset(test_data); | ||
| 1323 | -} | ||
| 1324 | - | ||
| 1325 | -static void test_status_reg_write_protection(const void *data) | ||
| 1326 | -{ | ||
| 1327 | - const TestData *test_data = (const TestData *)data; | ||
| 1328 | - uint8_t r; | ||
| 1329 | - | ||
| 1330 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1331 | - | ||
| 1332 | - /* default case: WP# is high and SRWD is low -> status register writable */ | ||
| 1333 | - spi_ctrl_start_user(test_data); | ||
| 1334 | - flash_writeb(test_data, 0, WREN); | ||
| 1335 | - /* test ability to write SRWD */ | ||
| 1336 | - flash_writeb(test_data, 0, WRSR); | ||
| 1337 | - flash_writeb(test_data, 0, SRWD); | ||
| 1338 | - flash_writeb(test_data, 0, RDSR); | ||
| 1339 | - r = flash_readb(test_data, 0); | ||
| 1340 | - spi_ctrl_stop_user(test_data); | ||
| 1341 | - g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 1342 | - | ||
| 1343 | - /* WP# high and SRWD high -> status register writable */ | ||
| 1344 | - spi_ctrl_start_user(test_data); | ||
| 1345 | - flash_writeb(test_data, 0, WREN); | ||
| 1346 | - /* test ability to write SRWD */ | ||
| 1347 | - flash_writeb(test_data, 0, WRSR); | ||
| 1348 | - flash_writeb(test_data, 0, 0); | ||
| 1349 | - flash_writeb(test_data, 0, RDSR); | ||
| 1350 | - r = flash_readb(test_data, 0); | ||
| 1351 | - spi_ctrl_stop_user(test_data); | ||
| 1352 | - g_assert_cmphex(r & SRWD, ==, 0); | ||
| 1353 | - | ||
| 1354 | - /* WP# low and SRWD low -> status register writable */ | ||
| 1355 | - qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0); | ||
| 1356 | - spi_ctrl_start_user(test_data); | ||
| 1357 | - flash_writeb(test_data, 0, WREN); | ||
| 1358 | - /* test ability to write SRWD */ | ||
| 1359 | - flash_writeb(test_data, 0, WRSR); | ||
| 1360 | - flash_writeb(test_data, 0, SRWD); | ||
| 1361 | - flash_writeb(test_data, 0, RDSR); | ||
| 1362 | - r = flash_readb(test_data, 0); | ||
| 1363 | - spi_ctrl_stop_user(test_data); | ||
| 1364 | - g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 1365 | - | ||
| 1366 | - /* WP# low and SRWD high -> status register NOT writable */ | ||
| 1367 | - spi_ctrl_start_user(test_data); | ||
| 1368 | - flash_writeb(test_data, 0 , WREN); | ||
| 1369 | - /* test ability to write SRWD */ | ||
| 1370 | - flash_writeb(test_data, 0, WRSR); | ||
| 1371 | - flash_writeb(test_data, 0, 0); | ||
| 1372 | - flash_writeb(test_data, 0, RDSR); | ||
| 1373 | - r = flash_readb(test_data, 0); | ||
| 1374 | - spi_ctrl_stop_user(test_data); | ||
| 1375 | - /* write is not successful */ | ||
| 1376 | - g_assert_cmphex(r & SRWD, ==, SRWD); | ||
| 1377 | - | ||
| 1378 | - qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1); | ||
| 1379 | - flash_reset(test_data); | ||
| 1380 | -} | ||
| 1381 | - | ||
| 1382 | -static void test_write_block_protect(const void *data) | ||
| 1383 | -{ | ||
| 1384 | - const TestData *test_data = (const TestData *)data; | ||
| 1385 | - uint32_t sector_size = 65536; | ||
| 1386 | - uint32_t n_sectors = 512; | ||
| 1387 | - | ||
| 1388 | - spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 1389 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1390 | - | ||
| 1391 | - uint32_t bp_bits = 0b0; | ||
| 1392 | - | ||
| 1393 | - for (int i = 0; i < 16; i++) { | ||
| 1394 | - bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2); | ||
| 1395 | - | ||
| 1396 | - spi_ctrl_start_user(test_data); | ||
| 1397 | - flash_writeb(test_data, 0, WREN); | ||
| 1398 | - flash_writeb(test_data, 0, BULK_ERASE); | ||
| 1399 | - flash_writeb(test_data, 0, WREN); | ||
| 1400 | - flash_writeb(test_data, 0, WRSR); | ||
| 1401 | - flash_writeb(test_data, 0, bp_bits); | ||
| 1402 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1403 | - flash_writeb(test_data, 0, WREN); | ||
| 1404 | - spi_ctrl_stop_user(test_data); | ||
| 1405 | - | ||
| 1406 | - uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0; | ||
| 1407 | - uint32_t protection_start = n_sectors - num_protected_sectors; | ||
| 1408 | - uint32_t protection_end = n_sectors; | ||
| 1409 | - | ||
| 1410 | - for (int sector = 0; sector < n_sectors; sector++) { | ||
| 1411 | - uint32_t addr = sector * sector_size; | ||
| 1412 | - | ||
| 1413 | - assert_page_mem(test_data, addr, 0xffffffff); | ||
| 1414 | - write_page_mem(test_data, addr, make_be32(0xabcdef12)); | ||
| 1415 | - | ||
| 1416 | - uint32_t expected_value = protection_start <= sector | ||
| 1417 | - && sector < protection_end | ||
| 1418 | - ? 0xffffffff : 0xabcdef12; | ||
| 1419 | - | ||
| 1420 | - assert_page_mem(test_data, addr, expected_value); | ||
| 1421 | - } | ||
| 1422 | - } | ||
| 1423 | - | ||
| 1424 | - flash_reset(test_data); | ||
| 1425 | -} | ||
| 1426 | - | ||
| 1427 | -static void test_write_block_protect_bottom_bit(const void *data) | ||
| 1428 | -{ | ||
| 1429 | - const TestData *test_data = (const TestData *)data; | ||
| 1430 | - uint32_t sector_size = 65536; | ||
| 1431 | - uint32_t n_sectors = 512; | ||
| 1432 | - | ||
| 1433 | - spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs)); | ||
| 1434 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1435 | - | ||
| 1436 | - /* top bottom bit is enabled */ | ||
| 1437 | - uint32_t bp_bits = 0b00100 << 3; | ||
| 1438 | - | ||
| 1439 | - for (int i = 0; i < 16; i++) { | ||
| 1440 | - bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2); | ||
| 1441 | - | ||
| 1442 | - spi_ctrl_start_user(test_data); | ||
| 1443 | - flash_writeb(test_data, 0, WREN); | ||
| 1444 | - flash_writeb(test_data, 0, BULK_ERASE); | ||
| 1445 | - flash_writeb(test_data, 0, WREN); | ||
| 1446 | - flash_writeb(test_data, 0, WRSR); | ||
| 1447 | - flash_writeb(test_data, 0, bp_bits); | ||
| 1448 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1449 | - flash_writeb(test_data, 0, WREN); | ||
| 1450 | - spi_ctrl_stop_user(test_data); | ||
| 1451 | - | ||
| 1452 | - uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0; | ||
| 1453 | - uint32_t protection_start = 0; | ||
| 1454 | - uint32_t protection_end = num_protected_sectors; | ||
| 1455 | - | ||
| 1456 | - for (int sector = 0; sector < n_sectors; sector++) { | ||
| 1457 | - uint32_t addr = sector * sector_size; | ||
| 1458 | - | ||
| 1459 | - assert_page_mem(test_data, addr, 0xffffffff); | ||
| 1460 | - write_page_mem(test_data, addr, make_be32(0xabcdef12)); | ||
| 1461 | - | ||
| 1462 | - uint32_t expected_value = protection_start <= sector | ||
| 1463 | - && sector < protection_end | ||
| 1464 | - ? 0xffffffff : 0xabcdef12; | ||
| 1465 | - | ||
| 1466 | - assert_page_mem(test_data, addr, expected_value); | ||
| 1467 | - } | ||
| 1468 | - } | ||
| 1469 | - | ||
| 1470 | - flash_reset(test_data); | ||
| 1471 | -} | ||
| 1472 | - | ||
| 1473 | -static void test_write_page_qpi(const void *data) | ||
| 1474 | -{ | ||
| 1475 | - const TestData *test_data = (const TestData *)data; | ||
| 1476 | - uint32_t my_page_addr = test_data->page_addr; | ||
| 1477 | - uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE; | ||
| 1478 | - uint32_t page[FLASH_PAGE_SIZE / 4]; | ||
| 1479 | - uint32_t page_pattern[] = { | ||
| 1480 | - 0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf | ||
| 1481 | - }; | ||
| 1482 | - int i; | ||
| 1483 | - | ||
| 1484 | - spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs)); | ||
| 1485 | - | ||
| 1486 | - spi_ctrl_start_user(test_data); | ||
| 1487 | - flash_writeb(test_data, 0, EN_4BYTE_ADDR); | ||
| 1488 | - flash_writeb(test_data, 0, WREN); | ||
| 1489 | - flash_writeb(test_data, 0, PP); | ||
| 1490 | - flash_writel(test_data, 0, make_be32(my_page_addr)); | ||
| 1491 | - | ||
| 1492 | - /* Set QPI mode */ | ||
| 1493 | - spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO); | ||
| 1494 | - | ||
| 1495 | - /* Fill the page pattern */ | ||
| 1496 | - for (i = 0; i < ARRAY_SIZE(page_pattern); i++) { | ||
| 1497 | - flash_writel(test_data, 0, make_be32(page_pattern[i])); | ||
| 1498 | - } | ||
| 1499 | - | ||
| 1500 | - /* Fill the page with its own addresses */ | ||
| 1501 | - for (; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1502 | - flash_writel(test_data, 0, make_be32(my_page_addr + i * 4)); | ||
| 1503 | - } | ||
| 1504 | - | ||
| 1505 | - /* Restore io mode */ | ||
| 1506 | - spi_ctrl_set_io_mode(test_data, 0); | ||
| 1507 | - spi_ctrl_stop_user(test_data); | ||
| 1508 | - | ||
| 1509 | - /* Check what was written */ | ||
| 1510 | - read_page(test_data, my_page_addr, page); | ||
| 1511 | - for (i = 0; i < ARRAY_SIZE(page_pattern); i++) { | ||
| 1512 | - g_assert_cmphex(page[i], ==, page_pattern[i]); | ||
| 1513 | - } | ||
| 1514 | - for (; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1515 | - g_assert_cmphex(page[i], ==, my_page_addr + i * 4); | ||
| 1516 | - } | ||
| 1517 | - | ||
| 1518 | - /* Check some other page. It should be full of 0xff */ | ||
| 1519 | - read_page(test_data, some_page_addr, page); | ||
| 1520 | - for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { | ||
| 1521 | - g_assert_cmphex(page[i], ==, 0xffffffff); | ||
| 1522 | - } | ||
| 1523 | - | ||
| 1524 | - flash_reset(test_data); | ||
| 1525 | -} | ||
| 1526 | - | ||
| 1527 | -static void test_palmetto_bmc(TestData *data) | ||
| 1528 | +static void test_palmetto_bmc(AspeedSMCTestData *data) | ||
| 1529 | { | ||
| 1530 | int ret; | ||
| 1531 | int fd; | ||
| 1532 | @@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data) | ||
| 1533 | /* beyond 16MB */ | ||
| 1534 | data->page_addr = 0x14000 * FLASH_PAGE_SIZE; | ||
| 1535 | |||
| 1536 | - qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec); | ||
| 1537 | - qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector); | ||
| 1538 | - qtest_add_data_func("/ast2400/smc/erase_all", data, test_erase_all); | ||
| 1539 | - qtest_add_data_func("/ast2400/smc/write_page", data, test_write_page); | ||
| 1540 | + qtest_add_data_func("/ast2400/smc/read_jedec", | ||
| 1541 | + data, aspeed_smc_test_read_jedec); | ||
| 1542 | + qtest_add_data_func("/ast2400/smc/erase_sector", | ||
| 1543 | + data, aspeed_smc_test_erase_sector); | ||
| 1544 | + qtest_add_data_func("/ast2400/smc/erase_all", | ||
| 1545 | + data, aspeed_smc_test_erase_all); | ||
| 1546 | + qtest_add_data_func("/ast2400/smc/write_page", | ||
| 1547 | + data, aspeed_smc_test_write_page); | ||
| 1548 | qtest_add_data_func("/ast2400/smc/read_page_mem", | ||
| 1549 | - data, test_read_page_mem); | ||
| 1550 | + data, aspeed_smc_test_read_page_mem); | ||
| 1551 | qtest_add_data_func("/ast2400/smc/write_page_mem", | ||
| 1552 | - data, test_write_page_mem); | ||
| 1553 | + data, aspeed_smc_test_write_page_mem); | ||
| 1554 | qtest_add_data_func("/ast2400/smc/read_status_reg", | ||
| 1555 | - data, test_read_status_reg); | ||
| 1556 | + data, aspeed_smc_test_read_status_reg); | ||
| 1557 | qtest_add_data_func("/ast2400/smc/status_reg_write_protection", | ||
| 1558 | - data, test_status_reg_write_protection); | ||
| 1559 | + data, aspeed_smc_test_status_reg_write_protection); | ||
| 1560 | qtest_add_data_func("/ast2400/smc/write_block_protect", | ||
| 1561 | - data, test_write_block_protect); | ||
| 1562 | + data, aspeed_smc_test_write_block_protect); | ||
| 1563 | qtest_add_data_func("/ast2400/smc/write_block_protect_bottom_bit", | ||
| 1564 | - data, test_write_block_protect_bottom_bit); | ||
| 1565 | + data, aspeed_smc_test_write_block_protect_bottom_bit); | ||
| 28 | } | 1566 | } |
| 29 | 1567 | ||
| 30 | static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | 1568 | -static void test_ast2500_evb(TestData *data) |
| 31 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | 1569 | +static void test_ast2500_evb(AspeedSMCTestData *data) |
| 32 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | 1570 | { |
| 33 | sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); | 1571 | int ret; |
| 34 | } | 1572 | int fd; |
| 35 | + | 1573 | @@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data) |
| 36 | + /* GPIO */ | 1574 | /* beyond 16MB */ |
| 37 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { | 1575 | data->page_addr = 0x14000 * FLASH_PAGE_SIZE; |
| 38 | + return; | 1576 | |
| 39 | + } | 1577 | - qtest_add_data_func("/ast2500/smc/read_jedec", data, test_read_jedec); |
| 40 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); | 1578 | - qtest_add_data_func("/ast2500/smc/erase_sector", data, test_erase_sector); |
| 41 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | 1579 | - qtest_add_data_func("/ast2500/smc/erase_all", data, test_erase_all); |
| 42 | + aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); | 1580 | - qtest_add_data_func("/ast2500/smc/write_page", data, test_write_page); |
| 1581 | + qtest_add_data_func("/ast2500/smc/read_jedec", | ||
| 1582 | + data, aspeed_smc_test_read_jedec); | ||
| 1583 | + qtest_add_data_func("/ast2500/smc/erase_sector", | ||
| 1584 | + data, aspeed_smc_test_erase_sector); | ||
| 1585 | + qtest_add_data_func("/ast2500/smc/erase_all", | ||
| 1586 | + data, aspeed_smc_test_erase_all); | ||
| 1587 | + qtest_add_data_func("/ast2500/smc/write_page", | ||
| 1588 | + data, aspeed_smc_test_write_page); | ||
| 1589 | qtest_add_data_func("/ast2500/smc/read_page_mem", | ||
| 1590 | - data, test_read_page_mem); | ||
| 1591 | + data, aspeed_smc_test_read_page_mem); | ||
| 1592 | qtest_add_data_func("/ast2500/smc/write_page_mem", | ||
| 1593 | - data, test_write_page_mem); | ||
| 1594 | + data, aspeed_smc_test_write_page_mem); | ||
| 1595 | qtest_add_data_func("/ast2500/smc/read_status_reg", | ||
| 1596 | - data, test_read_status_reg); | ||
| 1597 | + data, aspeed_smc_test_read_status_reg); | ||
| 1598 | qtest_add_data_func("/ast2500/smc/write_page_qpi", | ||
| 1599 | - data, test_write_page_qpi); | ||
| 1600 | + data, aspeed_smc_test_write_page_qpi); | ||
| 43 | } | 1601 | } |
| 44 | 1602 | ||
| 45 | static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) | 1603 | -static void test_ast2600_evb(TestData *data) |
| 46 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c | 1604 | +static void test_ast2600_evb(AspeedSMCTestData *data) |
| 1605 | { | ||
| 1606 | int ret; | ||
| 1607 | int fd; | ||
| 1608 | @@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data) | ||
| 1609 | /* beyond 16MB */ | ||
| 1610 | data->page_addr = 0x14000 * FLASH_PAGE_SIZE; | ||
| 1611 | |||
| 1612 | - qtest_add_data_func("/ast2600/smc/read_jedec", data, test_read_jedec); | ||
| 1613 | - qtest_add_data_func("/ast2600/smc/erase_sector", data, test_erase_sector); | ||
| 1614 | - qtest_add_data_func("/ast2600/smc/erase_all", data, test_erase_all); | ||
| 1615 | - qtest_add_data_func("/ast2600/smc/write_page", data, test_write_page); | ||
| 1616 | + qtest_add_data_func("/ast2600/smc/read_jedec", | ||
| 1617 | + data, aspeed_smc_test_read_jedec); | ||
| 1618 | + qtest_add_data_func("/ast2600/smc/erase_sector", | ||
| 1619 | + data, aspeed_smc_test_erase_sector); | ||
| 1620 | + qtest_add_data_func("/ast2600/smc/erase_all", | ||
| 1621 | + data, aspeed_smc_test_erase_all); | ||
| 1622 | + qtest_add_data_func("/ast2600/smc/write_page", | ||
| 1623 | + data, aspeed_smc_test_write_page); | ||
| 1624 | qtest_add_data_func("/ast2600/smc/read_page_mem", | ||
| 1625 | - data, test_read_page_mem); | ||
| 1626 | + data, aspeed_smc_test_read_page_mem); | ||
| 1627 | qtest_add_data_func("/ast2600/smc/write_page_mem", | ||
| 1628 | - data, test_write_page_mem); | ||
| 1629 | + data, aspeed_smc_test_write_page_mem); | ||
| 1630 | qtest_add_data_func("/ast2600/smc/read_status_reg", | ||
| 1631 | - data, test_read_status_reg); | ||
| 1632 | + data, aspeed_smc_test_read_status_reg); | ||
| 1633 | qtest_add_data_func("/ast2600/smc/write_page_qpi", | ||
| 1634 | - data, test_write_page_qpi); | ||
| 1635 | + data, aspeed_smc_test_write_page_qpi); | ||
| 1636 | } | ||
| 1637 | |||
| 1638 | -static void test_ast1030_evb(TestData *data) | ||
| 1639 | +static void test_ast1030_evb(AspeedSMCTestData *data) | ||
| 1640 | { | ||
| 1641 | int ret; | ||
| 1642 | int fd; | ||
| 1643 | @@ -XXX,XX +XXX,XX @@ static void test_ast1030_evb(TestData *data) | ||
| 1644 | /* beyond 512KB */ | ||
| 1645 | data->page_addr = 0x800 * FLASH_PAGE_SIZE; | ||
| 1646 | |||
| 1647 | - qtest_add_data_func("/ast1030/smc/read_jedec", data, test_read_jedec); | ||
| 1648 | - qtest_add_data_func("/ast1030/smc/erase_sector", data, test_erase_sector); | ||
| 1649 | - qtest_add_data_func("/ast1030/smc/erase_all", data, test_erase_all); | ||
| 1650 | - qtest_add_data_func("/ast1030/smc/write_page", data, test_write_page); | ||
| 1651 | + qtest_add_data_func("/ast1030/smc/read_jedec", | ||
| 1652 | + data, aspeed_smc_test_read_jedec); | ||
| 1653 | + qtest_add_data_func("/ast1030/smc/erase_sector", | ||
| 1654 | + data, aspeed_smc_test_erase_sector); | ||
| 1655 | + qtest_add_data_func("/ast1030/smc/erase_all", | ||
| 1656 | + data, aspeed_smc_test_erase_all); | ||
| 1657 | + qtest_add_data_func("/ast1030/smc/write_page", | ||
| 1658 | + data, aspeed_smc_test_write_page); | ||
| 1659 | qtest_add_data_func("/ast1030/smc/read_page_mem", | ||
| 1660 | - data, test_read_page_mem); | ||
| 1661 | + data, aspeed_smc_test_read_page_mem); | ||
| 1662 | qtest_add_data_func("/ast1030/smc/write_page_mem", | ||
| 1663 | - data, test_write_page_mem); | ||
| 1664 | + data, aspeed_smc_test_write_page_mem); | ||
| 1665 | qtest_add_data_func("/ast1030/smc/read_status_reg", | ||
| 1666 | - data, test_read_status_reg); | ||
| 1667 | + data, aspeed_smc_test_read_status_reg); | ||
| 1668 | qtest_add_data_func("/ast1030/smc/write_page_qpi", | ||
| 1669 | - data, test_write_page_qpi); | ||
| 1670 | + data, aspeed_smc_test_write_page_qpi); | ||
| 1671 | } | ||
| 1672 | |||
| 1673 | int main(int argc, char **argv) | ||
| 1674 | { | ||
| 1675 | - TestData palmetto_data; | ||
| 1676 | - TestData ast2500_evb_data; | ||
| 1677 | - TestData ast2600_evb_data; | ||
| 1678 | - TestData ast1030_evb_data; | ||
| 1679 | + AspeedSMCTestData palmetto_data; | ||
| 1680 | + AspeedSMCTestData ast2500_evb_data; | ||
| 1681 | + AspeedSMCTestData ast2600_evb_data; | ||
| 1682 | + AspeedSMCTestData ast1030_evb_data; | ||
| 1683 | int ret; | ||
| 1684 | |||
| 1685 | g_test_init(&argc, &argv, NULL); | ||
| 1686 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | 1687 | index XXXXXXX..XXXXXXX 100644 |
| 48 | --- a/hw/gpio/aspeed_gpio.c | 1688 | --- a/tests/qtest/meson.build |
| 49 | +++ b/hw/gpio/aspeed_gpio.c | 1689 | +++ b/tests/qtest/meson.build |
| 50 | @@ -XXX,XX +XXX,XX @@ static GPIOSetProperties ast2600_1_8v_set_props[ASPEED_GPIO_MAX_NR_SETS] = { | 1690 | @@ -XXX,XX +XXX,XX @@ qtests = { |
| 51 | [1] = {0x0000000f, 0x0000000f, {"18E"} }, | 1691 | 'virtio-net-failover': files('migration-helpers.c'), |
| 52 | }; | 1692 | 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'), |
| 53 | 1693 | 'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'), | |
| 54 | +static GPIOSetProperties ast1030_set_props[ASPEED_GPIO_MAX_NR_SETS] = { | 1694 | + 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), |
| 55 | + [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, | ||
| 56 | + [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, | ||
| 57 | + [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, | ||
| 58 | + [3] = {0xffffff3f, 0xffffff3f, {"M", "N", "O", "P"} }, | ||
| 59 | + [4] = {0xff060c1f, 0x00060c1f, {"Q", "R", "S", "T"} }, | ||
| 60 | + [5] = {0x000000ff, 0x00000000, {"U"} }, | ||
| 61 | +}; | ||
| 62 | + | ||
| 63 | static const MemoryRegionOps aspeed_gpio_ops = { | ||
| 64 | .read = aspeed_gpio_read, | ||
| 65 | .write = aspeed_gpio_write, | ||
| 66 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) | ||
| 67 | agc->reg_table = aspeed_1_8v_gpios; | ||
| 68 | } | 1695 | } |
| 69 | 1696 | ||
| 70 | +static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) | 1697 | if vnc.found() |
| 71 | +{ | ||
| 72 | + AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); | ||
| 73 | + | ||
| 74 | + agc->props = ast1030_set_props; | ||
| 75 | + agc->nr_gpio_pins = 151; | ||
| 76 | + agc->nr_gpio_sets = 6; | ||
| 77 | + agc->reg_table = aspeed_3_3v_gpios; | ||
| 78 | +} | ||
| 79 | + | ||
| 80 | static const TypeInfo aspeed_gpio_info = { | ||
| 81 | .name = TYPE_ASPEED_GPIO, | ||
| 82 | .parent = TYPE_SYS_BUS_DEVICE, | ||
| 83 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_gpio_ast2600_1_8v_info = { | ||
| 84 | .instance_init = aspeed_gpio_init, | ||
| 85 | }; | ||
| 86 | |||
| 87 | +static const TypeInfo aspeed_gpio_ast1030_info = { | ||
| 88 | + .name = TYPE_ASPEED_GPIO "-ast1030", | ||
| 89 | + .parent = TYPE_ASPEED_GPIO, | ||
| 90 | + .class_init = aspeed_gpio_1030_class_init, | ||
| 91 | + .instance_init = aspeed_gpio_init, | ||
| 92 | +}; | ||
| 93 | + | ||
| 94 | static void aspeed_gpio_register_types(void) | ||
| 95 | { | ||
| 96 | type_register_static(&aspeed_gpio_info); | ||
| 97 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_register_types(void) | ||
| 98 | type_register_static(&aspeed_gpio_ast2500_info); | ||
| 99 | type_register_static(&aspeed_gpio_ast2600_3_3v_info); | ||
| 100 | type_register_static(&aspeed_gpio_ast2600_1_8v_info); | ||
| 101 | + type_register_static(&aspeed_gpio_ast1030_info); | ||
| 102 | } | ||
| 103 | |||
| 104 | type_init(aspeed_gpio_register_types); | ||
| 105 | -- | 1698 | -- |
| 106 | 2.35.3 | 1699 | 2.47.1 |
| 107 | 1700 | ||
| 108 | 1701 | diff view generated by jsdifflib |
| 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> | 1 | From: Jamin Lin <jamin_lin@aspeedtech.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add GPIO read/write trace event for aspeed model. | 3 | Add test_ast2700_evb function and reused testcases which are from |
| 4 | aspeed_smc-test.c for AST2700 testing. The base address, flash base address | ||
| 5 | and ce index of fmc_cs0 are 0x14000000, 0x100000000 and 0, respectively. | ||
| 6 | The default flash model of fmc_cs0 is "w25q01jvq" whose size is 128MB, | ||
| 7 | so set jedec_id 0xef4021. | ||
| 4 | 8 | ||
| 5 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> | 9 | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
| 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 10 | Reviewed-by: Cédric Le Goater <clg@redhat.com> |
| 7 | Message-Id: <20220525053444.27228-2-jamin_lin@aspeedtech.com> | 11 | Link: https://lore.kernel.org/r/20241127091543.1243114-11-jamin_lin@aspeedtech.com |
| 8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 12 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 9 | --- | 13 | --- |
| 10 | hw/gpio/aspeed_gpio.c | 54 +++++++++++++++++++++++++++++++------------ | 14 | tests/qtest/ast2700-smc-test.c | 71 ++++++++++++++++++++++++++++++++++ |
| 11 | hw/gpio/trace-events | 4 ++++ | 15 | tests/qtest/meson.build | 4 +- |
| 12 | 2 files changed, 43 insertions(+), 15 deletions(-) | 16 | 2 files changed, 74 insertions(+), 1 deletion(-) |
| 17 | create mode 100644 tests/qtest/ast2700-smc-test.c | ||
| 13 | 18 | ||
| 14 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c | 19 | diff --git a/tests/qtest/ast2700-smc-test.c b/tests/qtest/ast2700-smc-test.c |
| 20 | new file mode 100644 | ||
| 21 | index XXXXXXX..XXXXXXX | ||
| 22 | --- /dev/null | ||
| 23 | +++ b/tests/qtest/ast2700-smc-test.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ | ||
| 25 | +/* | ||
| 26 | + * QTest testcase for the M25P80 Flash using the ASPEED SPI Controller since | ||
| 27 | + * AST2700. | ||
| 28 | + * | ||
| 29 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
| 30 | + * Copyright (C) 2024 ASPEED Technology Inc. | ||
| 31 | + */ | ||
| 32 | + | ||
| 33 | +#include "qemu/osdep.h" | ||
| 34 | +#include "qemu/bswap.h" | ||
| 35 | +#include "libqtest-single.h" | ||
| 36 | +#include "qemu/bitops.h" | ||
| 37 | +#include "aspeed-smc-utils.h" | ||
| 38 | + | ||
| 39 | +static void test_ast2700_evb(AspeedSMCTestData *data) | ||
| 40 | +{ | ||
| 41 | + int ret; | ||
| 42 | + int fd; | ||
| 43 | + | ||
| 44 | + fd = g_file_open_tmp("qtest.m25p80.w25q01jvq.XXXXXX", | ||
| 45 | + &data->tmp_path, NULL); | ||
| 46 | + g_assert(fd >= 0); | ||
| 47 | + ret = ftruncate(fd, 128 * 1024 * 1024); | ||
| 48 | + g_assert(ret == 0); | ||
| 49 | + close(fd); | ||
| 50 | + | ||
| 51 | + data->s = qtest_initf("-machine ast2700-evb " | ||
| 52 | + "-drive file=%s,format=raw,if=mtd", | ||
| 53 | + data->tmp_path); | ||
| 54 | + | ||
| 55 | + /* fmc cs0 with w25q01jvq flash */ | ||
| 56 | + data->flash_base = 0x100000000; | ||
| 57 | + data->spi_base = 0x14000000; | ||
| 58 | + data->jedec_id = 0xef4021; | ||
| 59 | + data->cs = 0; | ||
| 60 | + data->node = "/machine/soc/fmc/ssi.0/child[0]"; | ||
| 61 | + /* beyond 64MB */ | ||
| 62 | + data->page_addr = 0x40000 * FLASH_PAGE_SIZE; | ||
| 63 | + | ||
| 64 | + qtest_add_data_func("/ast2700/smc/read_jedec", | ||
| 65 | + data, aspeed_smc_test_read_jedec); | ||
| 66 | + qtest_add_data_func("/ast2700/smc/erase_sector", | ||
| 67 | + data, aspeed_smc_test_erase_sector); | ||
| 68 | + qtest_add_data_func("/ast2700/smc/erase_all", | ||
| 69 | + data, aspeed_smc_test_erase_all); | ||
| 70 | + qtest_add_data_func("/ast2700/smc/write_page", | ||
| 71 | + data, aspeed_smc_test_write_page); | ||
| 72 | + qtest_add_data_func("/ast2700/smc/read_page_mem", | ||
| 73 | + data, aspeed_smc_test_read_page_mem); | ||
| 74 | + qtest_add_data_func("/ast2700/smc/write_page_mem", | ||
| 75 | + data, aspeed_smc_test_write_page_mem); | ||
| 76 | + qtest_add_data_func("/ast2700/smc/read_status_reg", | ||
| 77 | + data, aspeed_smc_test_read_status_reg); | ||
| 78 | + qtest_add_data_func("/ast2700/smc/write_page_qpi", | ||
| 79 | + data, aspeed_smc_test_write_page_qpi); | ||
| 80 | +} | ||
| 81 | + | ||
| 82 | +int main(int argc, char **argv) | ||
| 83 | +{ | ||
| 84 | + AspeedSMCTestData ast2700_evb_data; | ||
| 85 | + int ret; | ||
| 86 | + | ||
| 87 | + g_test_init(&argc, &argv, NULL); | ||
| 88 | + | ||
| 89 | + test_ast2700_evb(&ast2700_evb_data); | ||
| 90 | + ret = g_test_run(); | ||
| 91 | + | ||
| 92 | + qtest_quit(ast2700_evb_data.s); | ||
| 93 | + unlink(ast2700_evb_data.tmp_path); | ||
| 94 | + return ret; | ||
| 95 | +} | ||
| 96 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | 97 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/gpio/aspeed_gpio.c | 98 | --- a/tests/qtest/meson.build |
| 17 | +++ b/hw/gpio/aspeed_gpio.c | 99 | +++ b/tests/qtest/meson.build |
| 18 | @@ -XXX,XX +XXX,XX @@ | 100 | @@ -XXX,XX +XXX,XX @@ qtests_aspeed = \ |
| 19 | #include "qapi/visitor.h" | 101 | 'aspeed_smc-test', |
| 20 | #include "hw/irq.h" | 102 | 'aspeed_gpio-test'] |
| 21 | #include "migration/vmstate.h" | 103 | qtests_aspeed64 = \ |
| 22 | +#include "trace.h" | 104 | - ['ast2700-gpio-test'] |
| 23 | 105 | + ['ast2700-gpio-test', | |
| 24 | #define GPIOS_PER_GROUP 8 | 106 | + 'ast2700-smc-test'] |
| 25 | 107 | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) | 108 | qtests_stm32l4x5 = \ |
| 27 | uint64_t idx = -1; | 109 | ['stm32l4x5_exti-test', |
| 28 | const AspeedGPIOReg *reg; | 110 | @@ -XXX,XX +XXX,XX @@ qtests = { |
| 29 | GPIOSets *set; | 111 | 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'), |
| 30 | + uint32_t value = 0; | 112 | 'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'), |
| 31 | + uint64_t debounce_value; | 113 | 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), |
| 32 | 114 | + 'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'), | |
| 33 | idx = offset >> 2; | ||
| 34 | if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { | ||
| 35 | idx -= GPIO_DEBOUNCE_TIME_1; | ||
| 36 | - return (uint64_t) s->debounce_regs[idx]; | ||
| 37 | + debounce_value = (uint64_t) s->debounce_regs[idx]; | ||
| 38 | + trace_aspeed_gpio_read(offset, debounce_value); | ||
| 39 | + return debounce_value; | ||
| 40 | } | ||
| 41 | |||
| 42 | reg = &agc->reg_table[idx]; | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) | ||
| 44 | set = &s->sets[reg->set_idx]; | ||
| 45 | switch (reg->type) { | ||
| 46 | case gpio_reg_data_value: | ||
| 47 | - return set->data_value; | ||
| 48 | + value = set->data_value; | ||
| 49 | + break; | ||
| 50 | case gpio_reg_direction: | ||
| 51 | - return set->direction; | ||
| 52 | + value = set->direction; | ||
| 53 | + break; | ||
| 54 | case gpio_reg_int_enable: | ||
| 55 | - return set->int_enable; | ||
| 56 | + value = set->int_enable; | ||
| 57 | + break; | ||
| 58 | case gpio_reg_int_sens_0: | ||
| 59 | - return set->int_sens_0; | ||
| 60 | + value = set->int_sens_0; | ||
| 61 | + break; | ||
| 62 | case gpio_reg_int_sens_1: | ||
| 63 | - return set->int_sens_1; | ||
| 64 | + value = set->int_sens_1; | ||
| 65 | + break; | ||
| 66 | case gpio_reg_int_sens_2: | ||
| 67 | - return set->int_sens_2; | ||
| 68 | + value = set->int_sens_2; | ||
| 69 | + break; | ||
| 70 | case gpio_reg_int_status: | ||
| 71 | - return set->int_status; | ||
| 72 | + value = set->int_status; | ||
| 73 | + break; | ||
| 74 | case gpio_reg_reset_tolerant: | ||
| 75 | - return set->reset_tol; | ||
| 76 | + value = set->reset_tol; | ||
| 77 | + break; | ||
| 78 | case gpio_reg_debounce_1: | ||
| 79 | - return set->debounce_1; | ||
| 80 | + value = set->debounce_1; | ||
| 81 | + break; | ||
| 82 | case gpio_reg_debounce_2: | ||
| 83 | - return set->debounce_2; | ||
| 84 | + value = set->debounce_2; | ||
| 85 | + break; | ||
| 86 | case gpio_reg_cmd_source_0: | ||
| 87 | - return set->cmd_source_0; | ||
| 88 | + value = set->cmd_source_0; | ||
| 89 | + break; | ||
| 90 | case gpio_reg_cmd_source_1: | ||
| 91 | - return set->cmd_source_1; | ||
| 92 | + value = set->cmd_source_1; | ||
| 93 | + break; | ||
| 94 | case gpio_reg_data_read: | ||
| 95 | - return set->data_read; | ||
| 96 | + value = set->data_read; | ||
| 97 | + break; | ||
| 98 | case gpio_reg_input_mask: | ||
| 99 | - return set->input_mask; | ||
| 100 | + value = set->input_mask; | ||
| 101 | + break; | ||
| 102 | default: | ||
| 103 | qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" | ||
| 104 | HWADDR_PRIx"\n", __func__, offset); | ||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | + | ||
| 108 | + trace_aspeed_gpio_read(offset, value); | ||
| 109 | + return value; | ||
| 110 | } | 115 | } |
| 111 | 116 | ||
| 112 | static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, | 117 | if vnc.found() |
| 113 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 114 | GPIOSets *set; | ||
| 115 | uint32_t cleared; | ||
| 116 | |||
| 117 | + trace_aspeed_gpio_write(offset, data); | ||
| 118 | + | ||
| 119 | idx = offset >> 2; | ||
| 120 | if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { | ||
| 121 | idx -= GPIO_DEBOUNCE_TIME_1; | ||
| 122 | diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events | ||
| 123 | index XXXXXXX..XXXXXXX 100644 | ||
| 124 | --- a/hw/gpio/trace-events | ||
| 125 | +++ b/hw/gpio/trace-events | ||
| 126 | @@ -XXX,XX +XXX,XX @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" P | ||
| 127 | sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 | ||
| 128 | sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 | ||
| 129 | sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 | ||
| 130 | + | ||
| 131 | +# aspeed_gpio.c | ||
| 132 | +aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64 | ||
| 133 | +aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64 | ||
| 134 | -- | 118 | -- |
| 135 | 2.35.3 | 119 | 2.47.1 |
| 136 | 120 | ||
| 137 | 121 | diff view generated by jsdifflib |