The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:

Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700)

https://github.com/legoater/qemu/ tags/pull-aspeed-20220525

for you to fetch changes up to 52bcd997800fab67d57bea6d93e368f6f7a93b24:

hw/arm/aspeed: Add i2c devices for AST2600 EVB (2022-05-25 16:22:37 +0200)

* Aspeed GPIO model extensions

* GPIO support for the Aspeed AST1030 SoC

* New fby35 machine (AST2600 based)

* Extra unit tests for the GPIO and SMC models

* Initialization of all UART with serial devices

* AST2600 EVB and Documentation update

Cédric Le Goater (1):

aspeed: Introduce a get_irq AspeedSoCClass method

Howard Chiu (1):

hw/arm/aspeed: Add i2c devices for AST2600 EVB

Iris Chen (1):

hw: m25p80: allow write_enable latch get/set

From: Jamin Lin <jamin_lin@aspeedtech.com>

It did not support GPIO index mode for read operation.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com>

include/hw/gpio/aspeed_gpio.h | 14 +++

hw/gpio/aspeed_gpio.c | 168 ++++++++++++++++++++++++++++++++++

2 files changed, 182 insertions(+)

diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h

--- a/include/hw/gpio/aspeed_gpio.h

+++ b/include/hw/gpio/aspeed_gpio.h

@@ -XXX,XX +XXX,XX @@ enum GPIORegType {

gpio_reg_input_mask,

};

+/* GPIO index mode */

+enum GPIORegIndexType {

+ gpio_reg_idx_data = 0,

+ gpio_reg_idx_direction,

+ gpio_reg_idx_interrupt,

+ gpio_reg_idx_debounce,

+ gpio_reg_idx_tolerance,

+ gpio_reg_idx_cmd_src,

+ gpio_reg_idx_input_mask,

+ gpio_reg_idx_reserved,

+ gpio_reg_idx_new_w_cmd_src,

+ gpio_reg_idx_new_r_cmd_src,

+};

+

typedef struct AspeedGPIOReg {

uint16_t set_idx;

enum GPIORegType type;

diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/aspeed_gpio.c

+++ b/hw/gpio/aspeed_gpio.c

@@ -XXX,XX +XXX,XX @@

#include "hw/irq.h"

#include "migration/vmstate.h"

#include "trace.h"

+#include "hw/registerfields.h"

#define GPIOS_PER_GROUP 8

@@ -XXX,XX +XXX,XX @@

#define GPIO_1_8V_MEM_SIZE 0x1D8

#define GPIO_1_8V_REG_ARRAY_SIZE (GPIO_1_8V_MEM_SIZE >> 2)

+/*

+ * GPIO index mode support

+ * It only supports write operation

+ */

+REG32(GPIO_INDEX_REG, 0x2AC)

+ FIELD(GPIO_INDEX_REG, NUMBER, 0, 8)

+ FIELD(GPIO_INDEX_REG, COMMAND, 12, 1)

+ FIELD(GPIO_INDEX_REG, TYPE, 16, 4)

+ FIELD(GPIO_INDEX_REG, DATA_VALUE, 20, 1)

+ FIELD(GPIO_INDEX_REG, DIRECTION, 20, 1)

+ FIELD(GPIO_INDEX_REG, INT_ENABLE, 20, 1)

+ FIELD(GPIO_INDEX_REG, INT_SENS_0, 21, 1)

+ FIELD(GPIO_INDEX_REG, INT_SENS_1, 22, 1)

+ FIELD(GPIO_INDEX_REG, INT_SENS_2, 23, 1)

+ FIELD(GPIO_INDEX_REG, INT_STATUS, 24, 1)

+ FIELD(GPIO_INDEX_REG, DEBOUNCE_1, 20, 1)

+ FIELD(GPIO_INDEX_REG, DEBOUNCE_2, 21, 1)

+ FIELD(GPIO_INDEX_REG, RESET_TOLERANT, 20, 1)

+ FIELD(GPIO_INDEX_REG, COMMAND_SRC_0, 20, 1)

+ FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1)

+ FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1)

+

static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)

{

uint32_t falling_edge = 0, rising_edge = 0;

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)

return value;

}

+static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset,

+ uint64_t data, uint32_t size)

+{

+

+ AspeedGPIOState *s = ASPEED_GPIO(opaque);

+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);

+ const GPIOSetProperties *props;

+ GPIOSets *set;

+ uint32_t reg_idx_number = FIELD_EX32(data, GPIO_INDEX_REG, NUMBER);

+ uint32_t reg_idx_type = FIELD_EX32(data, GPIO_INDEX_REG, TYPE);

+ uint32_t reg_idx_command = FIELD_EX32(data, GPIO_INDEX_REG, COMMAND);

+ uint32_t set_idx = reg_idx_number / ASPEED_GPIOS_PER_SET;

+ uint32_t pin_idx = reg_idx_number % ASPEED_GPIOS_PER_SET;

+ uint32_t group_idx = pin_idx / GPIOS_PER_GROUP;

+ uint32_t reg_value = 0;

+ uint32_t cleared;

+

+ set = &s->sets[set_idx];

+ props = &agc->props[set_idx];

+

+ if (reg_idx_command)

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%"

+ PRIx64 "index mode wrong command 0x%x\n",

+ __func__, offset, data, reg_idx_command);

+

+ switch (reg_idx_type) {

+ case gpio_reg_idx_data:

+ reg_value = set->data_read;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, DATA_VALUE));

+ reg_value &= props->output;

+ reg_value = update_value_control_source(set, set->data_value,

+ reg_value);

+ set->data_read = reg_value;

+ aspeed_gpio_update(s, set, reg_value);

+ return;

+ case gpio_reg_idx_direction:

+ reg_value = set->direction;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, DIRECTION));

+ /*

+ * where data is the value attempted to be written to the pin:

+ * pin type | input mask | output mask | expected value

+ * ------------------------------------------------------------

+ * bidirectional | 1 | 1 | data

+ * input only | 1 | 0 | 0

+ * output only | 0 | 1 | 1

+ * no pin | 0 | 0 | 0

+ *

+ * which is captured by:

+ * data = ( data | ~input) & output;

+ */

+ reg_value = (reg_value | ~props->input) & props->output;

+ set->direction = update_value_control_source(set, set->direction,

+ reg_value);

+ break;

+ case gpio_reg_idx_interrupt:

+ reg_value = set->int_enable;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, INT_ENABLE));

+ set->int_enable = update_value_control_source(set, set->int_enable,

+ reg_value);

+ reg_value = set->int_sens_0;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_0));

+ set->int_sens_0 = update_value_control_source(set, set->int_sens_0,

+ reg_value);

+ reg_value = set->int_sens_1;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_1));

+ set->int_sens_1 = update_value_control_source(set, set->int_sens_1,

+ reg_value);

+ reg_value = set->int_sens_2;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_2));

+ set->int_sens_2 = update_value_control_source(set, set->int_sens_2,

+ reg_value);

+ /* set interrupt status */

+ reg_value = set->int_status;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS));

+ cleared = ctpop32(reg_value & set->int_status);

+ if (s->pending && cleared) {

+ assert(s->pending >= cleared);

+ s->pending -= cleared;

+ }

+ set->int_status &= ~reg_value;

+ break;

+ case gpio_reg_idx_debounce:

+ reg_value = set->debounce_1;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_1));

+ set->debounce_1 = update_value_control_source(set, set->debounce_1,

+ reg_value);

+ reg_value = set->debounce_2;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_2));

+ set->debounce_2 = update_value_control_source(set, set->debounce_2,

+ reg_value);

+ return;

+ case gpio_reg_idx_tolerance:

+ reg_value = set->reset_tol;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, RESET_TOLERANT));

+ set->reset_tol = update_value_control_source(set, set->reset_tol,

+ reg_value);

+ return;

+ case gpio_reg_idx_cmd_src:

+ reg_value = set->cmd_source_0;

+ reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC_0));

+ set->cmd_source_0 = reg_value & ASPEED_CMD_SRC_MASK;

+ reg_value = set->cmd_source_1;

+ reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC_1));

+ set->cmd_source_1 = reg_value & ASPEED_CMD_SRC_MASK;

+ return;

+ case gpio_reg_idx_input_mask:

+ reg_value = set->input_mask;

+ reg_value = deposit32(reg_value, pin_idx, 1,

+ FIELD_EX32(data, GPIO_INDEX_REG, INPUT_MASK));

+ /*

+ * feeds into interrupt generation

+ * 0: read from data value reg will be updated

+ * 1: read from data value reg will not be updated

+ */

+ set->input_mask = reg_value & props->input;

+ break;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%"

+ PRIx64 "index mode wrong type 0x%x\n",

+ __func__, offset, data, reg_idx_type);

+ return;

+ }

+ aspeed_gpio_update(s, set, set->data_value);

+ return;

+}

+

static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,

uint32_t size)

{

@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,

trace_aspeed_gpio_write(offset, data);

idx = offset >> 2;

+

+ /* check gpio index mode */

+ if (idx == R_GPIO_INDEX_REG) {

+ aspeed_gpio_write_index_mode(opaque, offset, data, size);

+ return;

+ }

+

if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {

idx -= GPIO_DEBOUNCE_TIME_1;

s->debounce_regs[idx] = (uint32_t) data;

2.35.3

From: Peter Delevoryas <pdel@fb.com>

Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace

i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB.

Reference images can be found in Facebook OpenBMC Github Release assets

as "fby35.mtd". [3]

You can boot the reference images as follows (fby35 uses dual-flash):

qemu-system-arm -machine fby35-bmc \

-drive file=fby35.mtd,format=raw,if=mtd \

-drive file=fby35.mtd,format=raw,if=mtd \

-nographic

[1] https://github.com/facebook/openbmc-linux/blob/412d5053258007117e94b1e36015aefc1301474b/arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts

[2] https://github.com/facebook/openbmc/blob/e2294ff5d31dd65c248fe396a385286d6d5c463d/meta-facebook/meta-fby35/recipes-fby35/plat-utils/files/setup-dev.sh

[3] https://github.com/facebook/openbmc/releases

Signed-off-by: Peter Delevoryas <pdel@fb.com>

hw/arm/aspeed.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++

1 file changed, 63 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c

--- a/hw/arm/aspeed.c

+++ b/hw/arm/aspeed.c

#include "hw/misc/led.h"

#include "hw/qdev-properties.h"

#include "sysemu/block-backend.h"

+#include "sysemu/reset.h"

#include "hw/loader.h"

#include "qemu/error-report.h"

#include "qemu/units.h"

@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)

i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);

}

+static void fby35_i2c_init(AspeedMachineState *bmc)

+{

+ AspeedSoCState *soc = &bmc->soc;

+ I2CBus *i2c[16];

+

+ for (int i = 0; i < 16; i++) {

+ i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);

+ i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);

+ i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);

+ /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */

+ i2c_slave_create_simple(i2c[11], "adm1272", 0x44);

+ i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);

+ i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);

+

+ aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);

+ aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);

+ aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);

+ aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);

+ aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);

+ * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on

+ * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on

+ * each.

+}

+

static bool aspeed_get_mmio_exec(Object *obj, Error **errp)

{

return ASPEED_MACHINE(obj)->mmio_exec;

@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)

aspeed_soc_num_cpus(amc->soc_name);

}

+static void fby35_reset(MachineState *state)

+{

+ AspeedMachineState *bmc = ASPEED_MACHINE(state);

+ AspeedGPIOState *gpio = &bmc->soc.gpio;

+

+ qemu_devices_reset();

+

+ /* Board ID */

+ object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);

+ object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);

+ object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);

+ object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);

+}

+

+static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)

+{

+ MachineClass *mc = MACHINE_CLASS(oc);

+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);

+

+ mc->desc = "Facebook fby35 BMC (Cortex-A7)";

+ mc->reset = fby35_reset;

+ amc->fmc_model = "mx66l1g45g";

+ amc->num_cs = 2;

+ amc->macs_mask = ASPEED_MAC3_ON;

+ amc->i2c_init = fby35_i2c_init;

+ /* FIXME: Replace this macro with something more general */

+ mc->default_ram_size = FUJI_BMC_RAM_SIZE;

+}

+

#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)

/* Main SYSCLK frequency in Hz (200MHz) */

#define SYSCLK_FRQ 200000000ULL

@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {

.name = MACHINE_TYPE_NAME("bletchley-bmc"),

.parent = TYPE_ASPEED_MACHINE,

.class_init = aspeed_machine_bletchley_class_init,

+ }, {

+ .name = MACHINE_TYPE_NAME("fby35-bmc"),

+ .parent = MACHINE_TYPE_NAME("ast2600-evb"),

+ .class_init = aspeed_machine_fby35_class_init,

}, {

.name = MACHINE_TYPE_NAME("ast1030-evb"),

.parent = TYPE_ASPEED_MACHINE,

2.35.3

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add GPIO read/write trace event for aspeed model.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

hw/gpio/aspeed_gpio.c | 54 +++++++++++++++++++++++++++++++------------

hw/gpio/trace-events | 4 ++++

2 files changed, 43 insertions(+), 15 deletions(-)

diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c

--- a/hw/gpio/aspeed_gpio.c

+++ b/hw/gpio/aspeed_gpio.c

@@ -XXX,XX +XXX,XX @@

#include "qapi/visitor.h"

#include "hw/irq.h"

#include "migration/vmstate.h"

+#include "trace.h"

#define GPIOS_PER_GROUP 8

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)

uint64_t idx = -1;

const AspeedGPIOReg *reg;

GPIOSets *set;

+ uint32_t value = 0;

+ uint64_t debounce_value;

idx = offset >> 2;

if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {

idx -= GPIO_DEBOUNCE_TIME_1;

- return (uint64_t) s->debounce_regs[idx];

+ debounce_value = (uint64_t) s->debounce_regs[idx];

+ trace_aspeed_gpio_read(offset, debounce_value);

+ return debounce_value;

}

reg = &agc->reg_table[idx];

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)

set = &s->sets[reg->set_idx];

switch (reg->type) {

case gpio_reg_data_value:

- return set->data_value;

+ value = set->data_value;

+ break;

case gpio_reg_direction:

- return set->direction;

+ value = set->direction;

+ break;

case gpio_reg_int_enable:

- return set->int_enable;

+ value = set->int_enable;

+ break;

case gpio_reg_int_sens_0:

- return set->int_sens_0;

+ value = set->int_sens_0;

+ break;

case gpio_reg_int_sens_1:

- return set->int_sens_1;

+ value = set->int_sens_1;

+ break;

case gpio_reg_int_sens_2:

- return set->int_sens_2;

+ value = set->int_sens_2;

+ break;

case gpio_reg_int_status:

- return set->int_status;

+ value = set->int_status;

+ break;

case gpio_reg_reset_tolerant:

- return set->reset_tol;

+ value = set->reset_tol;

+ break;

case gpio_reg_debounce_1:

- return set->debounce_1;

+ value = set->debounce_1;

+ break;

case gpio_reg_debounce_2:

- return set->debounce_2;

+ value = set->debounce_2;

+ break;

case gpio_reg_cmd_source_0:

- return set->cmd_source_0;

+ value = set->cmd_source_0;

+ break;

case gpio_reg_cmd_source_1:

- return set->cmd_source_1;

+ value = set->cmd_source_1;

+ break;

case gpio_reg_data_read:

- return set->data_read;

+ value = set->data_read;

+ break;

case gpio_reg_input_mask:

- return set->input_mask;

+ value = set->input_mask;

+ break;

default:

qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"

HWADDR_PRIx"\n", __func__, offset);

return 0;

}

+

+ trace_aspeed_gpio_read(offset, value);

+ return value;

static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,

@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,

GPIOSets *set;

uint32_t cleared;

+ trace_aspeed_gpio_write(offset, data);

+

idx = offset >> 2;

if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {

idx -= GPIO_DEBOUNCE_TIME_1;

diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/trace-events

+++ b/hw/gpio/trace-events

@@ -XXX,XX +XXX,XX @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" P

sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64

sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

+

+# aspeed_gpio.c

+aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64

+aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64

2.35.3

From: Peter Delevoryas <pdel@fb.com>

Background:

AspeedMachineClass.uart_default specifies the serial console UART, which

usually corresponds to the "stdout-path" in the device tree.

The default value is UART5, since most boards use UART5 for this:

amc->uart_default = ASPEED_DEV_UART5;

Users can override AspeedMachineClass.uart_default in their board's machine

class init to specify something besides UART5. For example, for fuji-bmc:

amc->uart_default = ASPEED_DEV_UART1;

We only connect this one UART, of the 5 UART's on the AST2400 and AST2500

and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU

users can use. None of the other UART's are initialized, and the only way

to override this attribute is by creating a specialized board definition,

requiring QEMU source code changes and rebuilding.

The result of this is that if you want to get serial console output on a

board that uses UART3, you need to add a board definition. This was

encountered by Zev in OpenBMC. [1]

Changes:

This commit initializes all of the UART's present on each Aspeed chip with

serial devices and allows the QEMU user to connect as many or few as they

like to serial devices. For example, you can still run QEMU and just connect

stdout to the machine's default UART, without specifying any additional

serial devices:

qemu-system-arm -machine fuji-bmc \

-drive file=fuji.mtd,format=raw,if=mtd \

-nographic

However, if you don't want to add a special machine definition, you can now

manually configure UART1 to connect to stdout and get serial console output,

even if the machine's default is UART5:

qemu-system-arm -machine ast2600-evb \

-drive file=fuji.mtd,format=raw,if=mtd \

-serial null -serial mon:stdio -display none

In the example above, the first "-serial null" argument is connected to

UART5, and "-serial mon:stdio" is connected to UART1.

Another example: you can get serial console output from Wedge100, which uses

UART3, by reusing the palmetto AST2400 machine and rewiring the serial

device arguments:

qemu-system-arm -machine palmetto-bmc \

-drive file=wedge100.mtd,format=raw,if=mtd \

-serial null -serial null -serial null \

-serial mon:stdio -display none

There is a slight change in behavior introduced with this change: now, each

UART's memory-mapped IO region will have a serial device model connected to

it. Previously, all reads and writes to those regions would be ineffective

and return zero values, but now some values will be nonzero, even when the

user doesn't connect a serial device backend (like a socket, file, etc). For

example, the line status register might indicate that the transmit buffer is

empty now, whereas previously it might have always indicated it was full.

[1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/

[2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd

[3] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd

Signed-off-by: Peter Delevoryas <pdel@fb.com>

hw/arm/aspeed_soc.c | 9 +++++++++

1 file changed, 9 insertions(+)

@@ -XXX,XX +XXX,XX @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)

void aspeed_soc_uart_init(AspeedSoCState *s)

AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

+ int i, uart;

/* Attach an 8250 to the IO space as our UART */

serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,

aspeed_soc_get_irq(s, s->uart_default), 38400,

serial_hd(0), DEVICE_LITTLE_ENDIAN);

+ for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {

+ if (uart == s->uart_default) {

+ uart++;

+ }

+ serial_mm_init(get_system_memory(), sc->memmap[uart], 2,

+ aspeed_soc_get_irq(s, uart), 38400,

+ serial_hd(i), DEVICE_LITTLE_ENDIAN);

+ }

2.35.3

From: Howard Chiu <howard_chiu@aspeedtech.com>

Add EEPROM and LM75 temperature sensor according to hardware schematic

Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com>

hw/arm/aspeed.c | 11 +++++++++--

1 file changed, 9 insertions(+), 2 deletions(-)