[v2] hw/gpio Add ASPEED GPIO model for AST1030

[PATCH v2 0/4] hw/gpio Add ASPEED GPIO model for AST1030

Jamin Lin posted 4 patches 1 year, 11 months ago

Diff against v1
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220525053444.27228-1-jamin._5Flin@aspeedtech.com

Maintainers: "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Andrew Jeffery <andrew@aj.id.au>, Joel Stanley <joel@jms.id.au>

hw/arm/aspeed_ast10x0.c       |  11 ++
hw/gpio/aspeed_gpio.c         | 257 +++++++++++++++++++++++++++++++---
hw/gpio/trace-events          |   5 +
include/hw/gpio/aspeed_gpio.h |  16 ++-
4 files changed, 269 insertions(+), 20 deletions(-)

Expand all Fold all

[PATCH v2 0/4] hw/gpio Add ASPEED GPIO model for AST1030

Posted by Jamin Lin 1 year, 11 months ago

-v2 changes

Create separate patches to support the following features

1. Add GPIO read/write trace event.
2. Support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.
3. AST1030 integrates one set of Parallel GPIO Controller
with maximum 151 control pins, which are 21 groups
(A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4
S5 S6 S7 ) and the group T and U are input only.
4. replace HWADDR_PRIx with PRIx64

Jamin Lin (4):
  hw/gpio Add GPIO read/write trace event.
  hw/gpio: Add ASPEED GPIO model for AST1030
  hw/gpio support GPIO index mode for write operation.
  hw/gpio: replace HWADDR_PRIx with PRIx64

 hw/arm/aspeed_ast10x0.c       |  11 ++
 hw/gpio/aspeed_gpio.c         | 257 +++++++++++++++++++++++++++++++---
 hw/gpio/trace-events          |   5 +
 include/hw/gpio/aspeed_gpio.h |  16 ++-
 4 files changed, 269 insertions(+), 20 deletions(-)

-- 
2.17.1