target/riscv/cpu.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-)
- setting ext_g will implicitly set ext_i
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6d01569cad..e373c61ba2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -584,18 +584,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
uint32_t ext = 0;
/* Do some ISA extension error checking */
- if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
- error_setg(errp,
- "I and E extensions are incompatible");
- return;
- }
-
- if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
- error_setg(errp,
- "Either I or E extension must be set");
- return;
- }
-
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
cpu->cfg.ext_a && cpu->cfg.ext_f &&
cpu->cfg.ext_d &&
@@ -610,6 +598,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_ifencei = true;
}
+ if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+ error_setg(errp,
+ "I and E extensions are incompatible");
+ return;
+ }
+
+ if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+ error_setg(errp,
+ "Either I or E extension must be set");
+ return;
+ }
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
--
2.17.1
On Wed, May 18, 2022 at 11:27 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - setting ext_g will implicitly set ext_i > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 24 ++++++++++++------------ > 1 file changed, 12 insertions(+), 12 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6d01569cad..e373c61ba2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -584,18 +584,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > uint32_t ext = 0; > > /* Do some ISA extension error checking */ > - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > - error_setg(errp, > - "I and E extensions are incompatible"); > - return; > - } > - > - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { > - error_setg(errp, > - "Either I or E extension must be set"); > - return; > - } > - > if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && > cpu->cfg.ext_a && cpu->cfg.ext_f && > cpu->cfg.ext_d && > @@ -610,6 +598,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > cpu->cfg.ext_ifencei = true; > } > > + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > + error_setg(errp, > + "I and E extensions are incompatible"); > + return; > + } > + > + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { > + error_setg(errp, > + "Either I or E extension must be set"); > + return; > + } > + > if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { > error_setg(errp, "F extension requires Zicsr"); > return; > -- > 2.17.1 > >
© 2016 - 2024 Red Hat, Inc.