From: Marcin Nowakowski <marcin.nowakowski@fungible.com>
bit 31 (M) of WatchHiN register is a read-only register indicating
whether the next WatchHi register is present. It must not be reset
during user writes to the register.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: David Daney <david.daney@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com>
---
target/mips/cpu.c | 2 +-
target/mips/cpu.h | 1 +
target/mips/tcg/sysemu/cp0_helper.c | 3 ++-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ad74fbe636..c15c955367 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -305,7 +305,7 @@ static void mips_cpu_reset(DeviceState *dev)
for (i = 0; i < 7; i++) {
env->CP0_WatchLo[i] = 0;
- env->CP0_WatchHi[i] = 0x80000000;
+ env->CP0_WatchHi[i] = 1 << CP0WH_M;
}
env->CP0_WatchLo[7] = 0;
env->CP0_WatchHi[7] = 0;
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5335ac10a3..6b6b8776d1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1005,6 +1005,7 @@ typedef struct CPUArchState {
*/
uint64_t CP0_WatchHi[8];
#define CP0WH_ASID 16
+#define CP0WH_M 31
/*
* CP0 Register 20
*/
diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c
index aae2af6ecc..5da1124589 100644
--- a/target/mips/tcg/sysemu/cp0_helper.c
+++ b/target/mips/tcg/sysemu/cp0_helper.c
@@ -1396,10 +1396,11 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
+ uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */
if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
mask |= 0xFFFFFFFF00000000ULL; /* MMID */
}
- env->CP0_WatchHi[sel] = arg1 & mask;
+ env->CP0_WatchHi[sel] = m_bit | (arg1 & mask);
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
}
--
2.35.1