Hello everyone,

The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
One could think this means that, if an instruction is said to modify
the FPSCR register, the bit FI should be cleared. This is what QEMU
does today.

This is not, however, what the real hardware appears to do. It looks
like QEMU's interpretation of Power ISA was not correct for the
implementation of this bit.

This patch set fixes inconsistencies found in QEMU's handling of the
FPSCR.FI bit.

I found this while investigating how to enable Hardfpu for Power
guests. This change in the understanding on how the Power arch
handles the inexact bit makes it trivial to enable hardfpu for
affected instructions (mostly vsx-vector), but actually seems to
create even more complexity for the changes that will be required
to enable hardfpu for all float instructions. I'll instigate this
discussion more in the next few weeks.

Thanks!

Víctor Colombo (2):
  target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't
  target/ppc: Fix FPSCR.FI changing in float_overflow_excp()

 target/ppc/fpu_helper.c | 213 +++++++++++++++++++++-------------------
 1 file changed, 111 insertions(+), 102 deletions(-)

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2.25.1