Series comparison

-[PULL 00/32] target-arm queue
+[PULL 00/21] target-arm queue
-target-arm queue: the big stuff here is the final part of
+Hi; here's a target-arm pullreq to go in before softfreeze.
-rth's patches for Cortex-A76 and Neoverse-N1 support;
+This is actually pretty much entirely bugfixes (since the
-also present are Gavin's NUMA series and a few other things.
+SEL2 timers we implement here are a missing part of a feature
 we claim to already implement).
 thanks
 -- PMM
-The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
+The following changes since commit 98c7362b1efe651327385a25874a73e008c6549e:
-  Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
+  Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging (2025-03-07 07:39:49 +0800)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250307
-for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
+for you to fetch changes up to 0ce0739d46983e5e88fa9c149cb305689c9d8c6f:
-  hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
+  target/rx: Remove TCG_CALL_NO_WG from helpers which write env (2025-03-07 15:03:20 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * MAINTAINERS/.mailmap: update email for Leif Lindholm
+ * hw/arm/smmu-common: Remove the repeated ttb field
- * hw/arm: add version information to sbsa-ref machine DT
+ * hw/gpio: npcm7xx: fixup out-of-bounds access
- * Enable new features for -cpu max:
+ * tests/functional/test_arm_sx1: Check whether the serial console is working
-   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
+ * target/arm: Fix minor bugs in generic timer register handling
-   FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
+ * target/arm: Implement SEL2 physical and virtual timers
- * Emulate Cortex-A76
+ * target/arm: Correct STRD, LDRD atomicity and fault behaviour
- * Emulate Neoverse-N1
+ * target/arm: Make dummy debug registers RAZ, not NOP
- * Fix the virt board default NUMA topology
+ * util/qemu-timer.c: Don't warp timer from timerlist_rearm()
  * include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
  * hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
  * target/rx: Set exception vector base to 0xffffff80
  * target/rx: Remove TCG_CALL_NO_WG from helpers which write env
 ----------------------------------------------------------------
-Gavin Shan (6):
+Alex Bennée (4):
-      qapi/machine.json: Add cluster-id
+      target/arm: Implement SEL2 physical and virtual timers
-      qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
+      target/arm: Document the architectural names of our GTIMERs
-      hw/arm/virt: Consider SMP configuration in CPU topology
+      hw/arm: enable secure EL2 timers for virt machine
-      qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
+      hw/arm: enable secure EL2 timers for sbsa machine
       hw/arm/virt: Fix CPU's default NUMA node ID
       hw/acpi/aml-build: Use existing CPU topology to build PPTT table
-Leif Lindholm (2):
+JianChunfu (2):
-      MAINTAINERS/.mailmap: update email for Leif Lindholm
+      hw/arm/smmu-common: Remove the repeated ttb field
-      hw/arm: add versioning to sbsa-ref machine DT
+      hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
-Richard Henderson (24):
+Keith Packard (2):
-      target/arm: Handle cpreg registration for missing EL
+      target/rx: Set exception vector base to 0xffffff80
-      target/arm: Drop EL3 no EL2 fallbacks
+      target/rx: Remove TCG_CALL_NO_WG from helpers which write env
       target/arm: Merge zcr reginfo
       target/arm: Adjust definition of CONTEXTIDR_EL2
       target/arm: Move cortex impdef sysregs to cpu_tcg.c
       target/arm: Update qemu-system-arm -cpu max to cortex-a57
       target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
       target/arm: Split out aa32_max_features
       target/arm: Annotate arm_max_initfn with FEAT identifiers
       target/arm: Use field names for manipulating EL2 and EL3 modes
       target/arm: Enable FEAT_Debugv8p2 for -cpu max
       target/arm: Enable FEAT_Debugv8p4 for -cpu max
       target/arm: Add minimal RAS registers
       target/arm: Enable SCR and HCR bits for RAS
       target/arm: Implement virtual SError exceptions
       target/arm: Implement ESB instruction
       target/arm: Enable FEAT_RAS for -cpu max
       target/arm: Enable FEAT_IESB for -cpu max
       target/arm: Enable FEAT_CSV2 for -cpu max
       target/arm: Enable FEAT_CSV2_2 for -cpu max
       target/arm: Enable FEAT_CSV3 for -cpu max
       target/arm: Enable FEAT_DGH for -cpu max
       target/arm: Define cortex-a76
       target/arm: Define neoverse-n1
- docs/system/arm/emulation.rst |  10 +
+Patrick Venture (1):
- docs/system/arm/virt.rst      |   2 +
+      hw/gpio: npcm7xx: fixup out-of-bounds access
- qapi/machine.json             |   6 +-
- target/arm/cpregs.h           |  11 +
+Peter Maydell (11):
- target/arm/cpu.h              |  23 ++
+      target/arm: Apply correct timer offset when calculating deadlines
- target/arm/helper.h           |   1 +
+      target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
- target/arm/internals.h        |  16 ++
+      target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
- target/arm/syndrome.h         |   5 +
+      target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
- target/arm/a32.decode         |  16 +-
+      target/arm: Refactor handling of timer offset for direct register accesses
- target/arm/t32.decode         |  18 +-
+      target/arm: Correct LDRD atomicity and fault behaviour
- hw/acpi/aml-build.c           | 111 ++++----
+      target/arm: Correct STRD atomicity
- hw/arm/sbsa-ref.c             |  16 ++
+      target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
- hw/arm/virt.c                 |  21 +-
+      target/arm: Make dummy debug registers RAZ, not NOP
- hw/core/machine-hmp-cmds.c    |   4 +
+      util/qemu-timer.c: Don't warp timer from timerlist_rearm()
- hw/core/machine.c             |  16 ++
+      include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
- target/arm/cpu.c              |  66 ++++-
- target/arm/cpu64.c            | 353 ++++++++++++++-----------
+Thomas Huth (1):
- target/arm/cpu_tcg.c          | 227 +++++++++++-----
+      tests/functional/test_arm_sx1: Check whether the serial console is working
- target/arm/helper.c           | 600 +++++++++++++++++++++++++-----------------
- target/arm/op_helper.c        |  43 +++
+ MAINTAINERS                      |   1 +
- target/arm/translate-a64.c    |  18 ++
+ hw/arm/smmu-internal.h           |   5 -
- target/arm/translate.c        |  23 ++
+ include/exec/memop.h             |   8 +-
- tests/qtest/numa-test.c       |  19 +-
+ include/hw/arm/bsa.h             |   2 +
- .mailmap                      |   3 +-
+ include/hw/arm/smmu-common.h     |   7 +-
- MAINTAINERS                   |   2 +-
+ target/arm/cpu.h                 |   2 +
-files changed, 1068 insertions(+), 562 deletions(-)
+ target/arm/gtimer.h              |  14 +-
  target/arm/internals.h           |   5 +-
  target/rx/helper.h               |  34 ++--
  hw/arm/sbsa-ref.c                |   2 +
  hw/arm/smmu-common.c             |  21 +++
  hw/arm/smmuv3.c                  |  19 +--
  hw/arm/virt.c                    |   2 +
  hw/gpio/npcm7xx_gpio.c           |   3 +-
  target/arm/cpu.c                 |   4 +
  target/arm/debug_helper.c        |   7 +-
  target/arm/helper.c              | 324 ++++++++++++++++++++++++++++++++-------
  target/arm/tcg/op_helper.c       |   8 +-
  target/arm/tcg/translate.c       | 147 +++++++++++-------
  target/rx/helper.c               |   2 +-
  util/qemu-timer.c                |   4 -
  hw/arm/trace-events              |   3 +-
  tests/functional/test_arm_sx1.py |   7 +-
 files changed, 455 insertions(+), 176 deletions(-)

-[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
+[PULL 01/21] hw/arm/smmu-common: Remove the repeated ttb field
-From: Gavin Shan <gshan@redhat.com>
+From: JianChunfu <jansef.jian@hj-micro.com>
-When the PPTT table is built, the CPU topology is re-calculated, but
+SMMUTransCfg->ttb is never used in QEMU, TT base address
-it's unecessary because the CPU topology has been populated in
+can be accessed by SMMUTransCfg->tt[i]->ttb.
 virt_possible_cpu_arch_ids() on arm/virt machine.
-This reworks build_pptt() to avoid by reusing the existing IDs in
+Signed-off-by: JianChunfu <jansef.jian@hj-micro.com>
-ms->possible_cpus. Currently, the only user of build_pptt() is
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-arm/virt machine.
+Message-id: 20250221031034.69822-1-jansef.jian@hj-micro.com
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Tested-by: Yanan Wang <wangyanan55@huawei.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Acked-by: Igor Mammedov <imammedo@redhat.com>
 Acked-by: Michael S. Tsirkin <mst@redhat.com>
 Message-id: 20220503140304.855514-7-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
+ include/hw/arm/smmu-common.h | 1 -
-file changed, 48 insertions(+), 63 deletions(-)
+file changed, 1 deletion(-)
-diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/acpi/aml-build.c
+--- a/include/hw/arm/smmu-common.h
-+++ b/hw/acpi/aml-build.c
++++ b/include/hw/arm/smmu-common.h
-@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
+@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
-                 const char *oem_id, const char *oem_table_id)
+     /* Used by stage-1 only. */
- {
+     bool aa64;                 /* arch64 or aarch32 translation table */
-     MachineClass *mc = MACHINE_GET_CLASS(ms);
+     bool record_faults;        /* record fault events */
--    GQueue *list = g_queue_new();
+-    uint64_t ttb;              /* TT base address */
--    guint pptt_start = table_data->len;
+     uint8_t oas;               /* output address width */
--    guint parent_offset;
+     uint8_t tbi;               /* Top Byte Ignore */
--    guint length, i;
+     int asid;
 -    int uid = 0;
 -    int socket;
 +    CPUArchIdList *cpus = ms->possible_cpus;
 +    int64_t socket_id = -1, cluster_id = -1, core_id = -1;
 +    uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
 +    uint32_t pptt_start = table_data->len;
 +    int n;
      AcpiTable table = { .sig = "PPTT", .rev = 2,
                          .oem_id = oem_id, .oem_table_id = oem_table_id };
      acpi_table_begin(&table, table_data);
 -    for (socket = 0; socket < ms->smp.sockets; socket++) {
 -        g_queue_push_tail(list,
 -            GUINT_TO_POINTER(table_data->len - pptt_start));
 -        build_processor_hierarchy_node(
 -            table_data,
 -            /*
 -             * Physical package - represents the boundary
 -             * of a physical package
 -             */
 -            (1 << 0),
 -            0, socket, NULL, 0);
 -    }
 -
 -    if (mc->smp_props.clusters_supported) {
 -        length = g_queue_get_length(list);
 -        for (i = 0; i < length; i++) {
 -            int cluster;
 -
 -            parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -            for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
 -                g_queue_push_tail(list,
 -                    GUINT_TO_POINTER(table_data->len - pptt_start));
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (0 << 0), /* not a physical package */
 -                    parent_offset, cluster, NULL, 0);
 -            }
 +    /*
 +     * This works with the assumption that cpus[n].props.*_id has been
 +     * sorted from top to down levels in mc->possible_cpu_arch_ids().
 +     * Otherwise, the unexpected and duplicated containers will be
 +     * created.
 +     */
 +    for (n = 0; n < cpus->len; n++) {
 +        if (cpus->cpus[n].props.socket_id != socket_id) {
 +            assert(cpus->cpus[n].props.socket_id > socket_id);
 +            socket_id = cpus->cpus[n].props.socket_id;
 +            cluster_id = -1;
 +            core_id = -1;
 +            socket_offset = table_data->len - pptt_start;
 +            build_processor_hierarchy_node(table_data,
 +                (1 << 0), /* Physical package */
 +                0, socket_id, NULL, 0);
          }
 -    }
 -    length = g_queue_get_length(list);
 -    for (i = 0; i < length; i++) {
 -        int core;
 -
 -        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -        for (core = 0; core < ms->smp.cores; core++) {
 -            if (ms->smp.threads > 1) {
 -                g_queue_push_tail(list,
 -                    GUINT_TO_POINTER(table_data->len - pptt_start));
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (0 << 0), /* not a physical package */
 -                    parent_offset, core, NULL, 0);
 -            } else {
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (1 << 1) | /* ACPI Processor ID valid */
 -                    (1 << 3),  /* Node is a Leaf */
 -                    parent_offset, uid++, NULL, 0);
 +        if (mc->smp_props.clusters_supported) {
 +            if (cpus->cpus[n].props.cluster_id != cluster_id) {
 +                assert(cpus->cpus[n].props.cluster_id > cluster_id);
 +                cluster_id = cpus->cpus[n].props.cluster_id;
 +                core_id = -1;
 +                cluster_offset = table_data->len - pptt_start;
 +                build_processor_hierarchy_node(table_data,
 +                    (0 << 0), /* Not a physical package */
 +                    socket_offset, cluster_id, NULL, 0);
              }
 +        } else {
 +            cluster_offset = socket_offset;
          }
 -    }
 -    length = g_queue_get_length(list);
 -    for (i = 0; i < length; i++) {
 -        int thread;
 +        if (ms->smp.threads == 1) {
 +            build_processor_hierarchy_node(table_data,
 +                (1 << 1) | /* ACPI Processor ID valid */
 +                (1 << 3),  /* Node is a Leaf */
 +                cluster_offset, n, NULL, 0);
 +        } else {
 +            if (cpus->cpus[n].props.core_id != core_id) {
 +                assert(cpus->cpus[n].props.core_id > core_id);
 +                core_id = cpus->cpus[n].props.core_id;
 +                core_offset = table_data->len - pptt_start;
 +                build_processor_hierarchy_node(table_data,
 +                    (0 << 0), /* Not a physical package */
 +                    cluster_offset, core_id, NULL, 0);
 +            }
 -        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -        for (thread = 0; thread < ms->smp.threads; thread++) {
 -            build_processor_hierarchy_node(
 -                table_data,
 +            build_processor_hierarchy_node(table_data,
                  (1 << 1) | /* ACPI Processor ID valid */
                  (1 << 2) | /* Processor is a Thread */
                  (1 << 3),  /* Node is a Leaf */
 -                parent_offset, uid++, NULL, 0);
 +                core_offset, n, NULL, 0);
          }
      }
 -    g_queue_free(list);
      acpi_table_end(linker, &table);
  }
 --
-.25.1
+.43.0

-[PULL 02/32] target/arm: Handle cpreg registration for missing EL
+[PULL 02/21] hw/gpio: npcm7xx: fixup out-of-bounds access
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Patrick Venture <venture@google.com>
-More gracefully handle cpregs when EL2 and/or EL3 are missing.
+The reg isn't validated to be a possible register before
-If the reg is entirely inaccessible, do not register it at all.
+it's dereferenced for one case.  The mmio space registered
-If the reg is for EL2, and EL3 is present but EL2 is not,
+for the gpio device is 4KiB but there aren't that many
-either discard, squash to res0, const, or keep unchanged.
+registers in the struct.
-Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
+Cc: qemu-stable@nongnu.org
-with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
+Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nuvoton NPCM7xx")
-translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
+Signed-off-by: Patrick Venture <venture@google.com>
-Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20250226024603.493148-1-venture@google.com
 This will simplify cpreg registration for conditional arm features.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h |  11 +++
+ hw/gpio/npcm7xx_gpio.c | 3 +--
- target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
+file changed, 1 insertion(+), 2 deletions(-)
 files changed, 133 insertions(+), 56 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/hw/gpio/npcm7xx_gpio.c
-+++ b/target/arm/cpregs.h
++++ b/hw/gpio/npcm7xx_gpio.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
-     ARM_CP_SVE                   = 1 << 14,
+         return;
      /* Flag: Do not expose in gdb sysreg xml. */
      ARM_CP_NO_GDB                = 1 << 15,
 +    /*
 +     * Flags: If EL3 but not EL2...
 +     *   - UNDEF: discard the cpreg,
 +     *   -  KEEP: retain the cpreg as is,
 +     *   -  C_NZ: set const on the cpreg, but retain resetvalue,
 +     *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
 +     * See rule RJFFP in section D1.1.3 of DDI0487H.a.
 +     */
 +    ARM_CP_EL3_NO_EL2_UNDEF      = 1 << 16,
 +    ARM_CP_EL3_NO_EL2_KEEP       = 1 << 17,
 +    ARM_CP_EL3_NO_EL2_C_NZ       = 1 << 18,
  };
  /*
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
      { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
 +      .access = PL2_RW,
 +      .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
        .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
      { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
 -      .access = PL2_RW, .resetvalue = 0,
 +      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
        .writefn = dacr_write, .raw_writefn = raw_write,
        .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
      { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
 -      .access = PL2_RW, .resetvalue = 0,
 +      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
        .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
      { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
        .type = ARM_CP_ALIAS,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
        .writefn = tlbimva_hyp_is_write },
      { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_alle2_write },
      { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2_write },
      { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2_write },
      { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_alle2is_write },
      { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
      { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
  #ifndef CONFIG_USER_ONLY
      /* Unlike the other EL2-related AT operations, these must
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
      { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
        .access = PL2_W, .accessfn = at_s1e2_access,
 -      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
 +      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
 +      .writefn = ats_write64 },
      { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
        .access = PL2_W, .accessfn = at_s1e2_access,
 -      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
 +      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
 +      .writefn = ats_write64 },
      /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
       * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
       * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
        .access = PL2_RW, .accessfn = access_tda,
 -      .type = ARM_CP_NOP },
 +      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
      /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
       * Channel but Linux may try to access this register. The 32-bit
       * alias is DBGDCCINT.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .access = PL2_W, .type = ARM_CP_NOP },
      { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
      { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
      { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2_write },
     { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2_write },
     { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_alle2is_write },
      { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .writefn = tlbi_aa64_alle1is_write },
      { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
      { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
                .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -              .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
 +              .resetvalue = cpu->midr,
 +              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
              { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
                .access = PL2_RW, .resetvalue = cpu->midr,
 +              .type = ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
              { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
                .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -              .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
 +              .resetvalue = vmpidr_def,
 +              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
              { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
 -              .access = PL2_RW,
 -              .resetvalue = vmpidr_def,
 +              .access = PL2_RW, .resetvalue = vmpidr_def,
 +              .type = ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
          };
          define_arm_cp_regs(cpu, vpidr_regs);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                     int crm, int opc1, int opc2,
                                     const char *name)
  {
 +    CPUARMState *env = &cpu->env;
      uint32_t key;
      ARMCPRegInfo *r2;
      bool is64 = r->type & ARM_CP_64BIT;
      bool ns = secstate & ARM_CP_SECSTATE_NS;
      int cp = r->cp;
 -    bool isbanked;
      size_t name_len;
 +    bool make_const;
      switch (state) {
      case ARM_CP_STATE_AA32:
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          }
      }
-+    /*
+-    diff = s->regs[reg] ^ value;
-+     * Eliminate registers that are not present because the EL is missing.
+-
-+     * Doing this here makes it easier to put all registers for a given
+     switch (reg) {
-+     * feature into the same ARMCPRegInfo array and define them all at once.
+     case NPCM7XX_GPIO_TLOCK1:
-+     */
+     case NPCM7XX_GPIO_TLOCK2:
-+    make_const = false;
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
-+    if (arm_feature(env, ARM_FEATURE_EL3)) {
+     case NPCM7XX_GPIO_PU:
-+        /*
+     case NPCM7XX_GPIO_PD:
-+         * An EL2 register without EL2 but with EL3 is (usually) RES0.
+     case NPCM7XX_GPIO_IEM:
-+         * See rule RJFFP in section D1.1.3 of DDI0487H.a.
++        diff = s->regs[reg] ^ value;
-+         */
+         s->regs[reg] = value;
-+        int min_el = ctz32(r->access) / 2;
+         npcm7xx_gpio_update_pins(s, diff);
-+        if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
+         break;
 +            if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
 +                return;
 +            }
 +            make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
 +        }
 +    } else {
 +        CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
 +                                 ? PL2_RW : PL1_RW);
 +        if ((r->access & max_el) == 0) {
 +            return;
 +        }
 +    }
 +
      /* Combine cpreg and name into one allocation. */
      name_len = strlen(name) + 1;
      r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          r2->opaque = opaque;
      }
 -    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 -    if (isbanked) {
 +    if (make_const) {
 +        /* This should not have been a very special register to begin. */
 +        int old_special = r2->type & ARM_CP_SPECIAL_MASK;
 +        assert(old_special == 0 || old_special == ARM_CP_NOP);
          /*
 -         * Register is banked (using both entries in array).
 -         * Overwriting fieldoffset as the array is only used to define
 -         * banked registers but later only fieldoffset is used.
 +         * Set the special function to CONST, retaining the other flags.
 +         * This is important for e.g. ARM_CP_SVE so that we still
 +         * take the SVE trap if CPTR_EL3.EZ == 0.
           */
 -        r2->fieldoffset = r->bank_fieldoffsets[ns];
 -    }
 +        r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
 +        /*
 +         * Usually, these registers become RES0, but there are a few
 +         * special cases like VPIDR_EL2 which have a constant non-zero
 +         * value with writes ignored.
 +         */
 +        if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
 +            r2->resetvalue = 0;
 +        }
 +        /*
 +         * ARM_CP_CONST has precedence, so removing the callbacks and
 +         * offsets are not strictly necessary, but it is potentially
 +         * less confusing to debug later.
 +         */
 +        r2->readfn = NULL;
 +        r2->writefn = NULL;
 +        r2->raw_readfn = NULL;
 +        r2->raw_writefn = NULL;
 +        r2->resetfn = NULL;
 +        r2->fieldoffset = 0;
 +        r2->bank_fieldoffsets[0] = 0;
 +        r2->bank_fieldoffsets[1] = 0;
 +    } else {
 +        bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 -    if (state == ARM_CP_STATE_AA32) {
          if (isbanked) {
              /*
 -             * If the register is banked then we don't need to migrate or
 -             * reset the 32-bit instance in certain cases:
 -             *
 -             * 1) If the register has both 32-bit and 64-bit instances then we
 -             *    can count on the 64-bit instance taking care of the
 -             *    non-secure bank.
 -             * 2) If ARMv8 is enabled then we can count on a 64-bit version
 -             *    taking care of the secure bank.  This requires that separate
 -             *    32 and 64-bit definitions are provided.
 +             * Register is banked (using both entries in array).
 +             * Overwriting fieldoffset as the array is only used to define
 +             * banked registers but later only fieldoffset is used.
               */
 -            if ((r->state == ARM_CP_STATE_BOTH && ns) ||
 -                (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
 +            r2->fieldoffset = r->bank_fieldoffsets[ns];
 +        }
 +        if (state == ARM_CP_STATE_AA32) {
 +            if (isbanked) {
 +                /*
 +                 * If the register is banked then we don't need to migrate or
 +                 * reset the 32-bit instance in certain cases:
 +                 *
 +                 * 1) If the register has both 32-bit and 64-bit instances
 +                 *    then we can count on the 64-bit instance taking care
 +                 *    of the non-secure bank.
 +                 * 2) If ARMv8 is enabled then we can count on a 64-bit
 +                 *    version taking care of the secure bank.  This requires
 +                 *    that separate 32 and 64-bit definitions are provided.
 +                 */
 +                if ((r->state == ARM_CP_STATE_BOTH && ns) ||
 +                    (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
 +                    r2->type |= ARM_CP_ALIAS;
 +                }
 +            } else if ((secstate != r->secure) && !ns) {
 +                /*
 +                 * The register is not banked so we only want to allow
 +                 * migration of the non-secure instance.
 +                 */
                  r2->type |= ARM_CP_ALIAS;
              }
 -        } else if ((secstate != r->secure) && !ns) {
 -            /*
 -             * The register is not banked so we only want to allow migration
 -             * of the non-secure instance.
 -             */
 -            r2->type |= ARM_CP_ALIAS;
 -        }
 -        if (HOST_BIG_ENDIAN &&
 -            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
 -            r2->fieldoffset += sizeof(uint32_t);
 +            if (HOST_BIG_ENDIAN &&
 +                r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
 +                r2->fieldoffset += sizeof(uint32_t);
 +            }
          }
      }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
       * multiple times. Special registers (ie NOP/WFI) are
       * never migratable and not even raw-accessible.
       */
 -    if (r->type & ARM_CP_SPECIAL_MASK) {
 +    if (r2->type & ARM_CP_SPECIAL_MASK) {
          r2->type |= ARM_CP_NO_RAW;
      }
      if (((r->crm == CP_ANY) && crm != 0) ||
 --
-.25.1
+.43.0

-[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
+[PULL 03/21] tests/functional/test_arm_sx1: Check whether the serial console is working
-From: Leif Lindholm <quic_llindhol@quicinc.com>
+From: Thomas Huth <thuth@redhat.com>
-NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
+The kernel that is used in the sx1 test prints the usual Linux log
-separate infrastructure for a transitional period. We've now switched
+onto the serial console, but this test currently ignores it. To
-over to contributing as Qualcomm Innovation Center (quicinc), so update
+make sure that the serial device is working properly, let's check
-my email address to reflect this.
+for some strings in the output here.
-Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
+While we're at it, also add the test to the corresponding section
-Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
+in the MAINTAINERS file.
-Cc: Leif Lindholm <leif@nuviainc.com>
-Cc: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Thomas Huth <thuth@redhat.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-[Fixed commit message typo]
+Message-id: 20250226104833.1176253-1-thuth@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- .mailmap    | 3 ++-
+ MAINTAINERS                      | 1 +
- MAINTAINERS | 2 +-
+ tests/functional/test_arm_sx1.py | 7 ++++---
-files changed, 3 insertions(+), 2 deletions(-)
+files changed, 5 insertions(+), 3 deletions(-)
-diff --git a/.mailmap b/.mailmap
-index XXXXXXX..XXXXXXX 100644
---- a/.mailmap
-+++ b/.mailmap
-@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
- Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
- Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
- James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
--Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
-+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
-+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
- Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
- Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
- Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
+@@ -XXX,XX +XXX,XX @@ S: Maintained
- SBSA-REF
+ F: hw/*/omap*
- M: Radoslaw Biernacki <rad@semihalf.com>
+ F: include/hw/arm/omap.h
- M: Peter Maydell <peter.maydell@linaro.org>
+ F: docs/system/arm/sx1.rst
--R: Leif Lindholm <leif@nuviainc.com>
++F: tests/functional/test_arm_sx1.py
-+R: Leif Lindholm <quic_llindhol@quicinc.com>
- L: qemu-arm@nongnu.org
+ IPack
- S: Maintained
+ M: Alberto Garcia <berto@igalia.com>
- F: hw/arm/sbsa-ref.c
+diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/test_arm_sx1.py
 index XXXXXXX..XXXXXXX 100755
 --- a/tests/functional/test_arm_sx1.py
 +++ b/tests/functional/test_arm_sx1.py
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_initrd(self):
          self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}')
          self.vm.add_args('-no-reboot')
          self.launch_kernel(zimage_path,
 -                           initrd=initrd_path)
 +                           initrd=initrd_path,
 +                           wait_for='Boot successful')
          self.vm.wait(timeout=120)
      def test_arm_sx1_sd(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_sd(self):
          self.vm.add_args('-no-reboot')
          self.vm.add_args('-snapshot')
          self.vm.add_args('-drive', f'format=raw,if=sd,file={sd_fs_path}')
 -        self.launch_kernel(zimage_path)
 +        self.launch_kernel(zimage_path, wait_for='Boot successful')
          self.vm.wait(timeout=120)
      def test_arm_sx1_flash(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_flash(self):
          self.vm.add_args('-no-reboot')
          self.vm.add_args('-snapshot')
          self.vm.add_args('-drive', f'format=raw,if=pflash,file={flash_path}')
 -        self.launch_kernel(zimage_path)
 +        self.launch_kernel(zimage_path, wait_for='Boot successful')
          self.vm.wait(timeout=120)
  if __name__ == '__main__':
 --
-.25.1
+.43.0

-[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
-vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
-while registering for v8.
-This is a behavior change for v7 cpus with Security Extensions and
-without Virtualization Extensions, in that the virtualization cpregs
-are now correctly not present.  This would be a migration compatibility
-break, except that we have an existing bug in which migration of 32-bit
-cpus with Security Extensions enabled does not work.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.c | 158 ++++----------------------------------------
-file changed, 13 insertions(+), 145 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
- };
--/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
--static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
--    { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
--      .access = PL2_RW,
--      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
--    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
--      .access = PL2_RW,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
--      .access = PL2_RW,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
--      .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
--      .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
--      .access = PL2_RW, .accessfn = access_el3_aa32ns,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
--      .cp = 15, .opc1 = 6, .crm = 2,
--      .access = PL2_RW, .accessfn = access_el3_aa32ns,
--      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
--    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
--      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
--      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
--      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
--      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
--      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
--      .access = PL2_RW, .accessfn = access_tda,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
--      .access = PL2_RW, .accessfn = access_el3_aa32ns,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
--      .type = ARM_CP_CONST,
--      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
--      .access = PL2_RW, .resetvalue = 0 },
--};
--
--/* Ditto, but for registers which exist in ARMv8 but not v7 */
--static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
--    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
--      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
--      .access = PL2_RW,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--};
--
- static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
- {
-     ARMCPU *cpu = env_archcpu(env);
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-         define_arm_cp_regs(cpu, v8_idregs);
-         define_arm_cp_regs(cpu, v8_cp_reginfo);
-     }
--    if (arm_feature(env, ARM_FEATURE_EL2)) {
-+
-+    /*
-+     * Register the base EL2 cpregs.
-+     * Pre v8, these registers are implemented only as part of the
-+     * Virtualization Extensions (EL2 present).  Beginning with v8,
-+     * if EL2 is missing but EL3 is enabled, mostly these become
-+     * RES0 from EL3, with some specific exceptions.
-+     */
-+    if (arm_feature(env, ARM_FEATURE_EL2)
-+        || (arm_feature(env, ARM_FEATURE_EL3)
-+            && arm_feature(env, ARM_FEATURE_V8))) {
-         uint64_t vmpidr_def = mpidr_read_val(env);
-         ARMCPRegInfo vpidr_regs[] = {
-             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-             };
-             define_one_arm_cp_reg(cpu, &rvbar);
-         }
--    } else {
--        /* If EL2 is missing but higher ELs are enabled, we need to
--         * register the no_el2 reginfos.
--         */
--        if (arm_feature(env, ARM_FEATURE_EL3)) {
--            /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
--             * of MIDR_EL1 and MPIDR_EL1.
--             */
--            ARMCPRegInfo vpidr_regs[] = {
--                { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
--                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
--                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
--                  .type = ARM_CP_CONST, .resetvalue = cpu->midr,
--                  .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
--                { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
--                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
--                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
--                  .type = ARM_CP_NO_RAW,
--                  .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
--            };
--            define_arm_cp_regs(cpu, vpidr_regs);
--            define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
--            if (arm_feature(env, ARM_FEATURE_V8)) {
--                define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
--            }
--        }
-     }
-+
-+    /* Register the base EL3 cpregs. */
-     if (arm_feature(env, ARM_FEATURE_EL3)) {
-         define_arm_cp_regs(cpu, el3_cp_reginfo);
-         ARMCPRegInfo el3_regs[] = {
---
-.25.1

-[PULL 04/32] target/arm: Merge zcr reginfo
+[PULL 04/21] target/arm: Apply correct timer offset when calculating deadlines
-From: Richard Henderson <richard.henderson@linaro.org>
+When we are calculating timer deadlines, the correct definition of
 whether or not to apply an offset to the physical count is described
 in the Arm ARM DDI4087 rev L.a section D12.2.4.1.  This is different
 from when the offset should be applied for a direct read of the
 counter sysreg.
-Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
+We got this right for the EL1 physical timer and for the EL1 virtual
-now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
+timer, but got all the rest wrong: they should be using a zero offset
-while registering.
+always.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Factor the offset calculation out into a function that has a comment
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+documenting exactly which offset it is calculating and which gets the
-Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
+HYP, SEC, and HYPVIRT cases right.
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20250204125009.2281315-2-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 55 ++++++++++++++-------------------------------
+ target/arm/helper.c | 29 +++++++++++++++++++++++++++--
-file changed, 17 insertions(+), 38 deletions(-)
+file changed, 27 insertions(+), 2 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_cnt_offset(CPUARMState *env)
-     }
+     return gt_phys_raw_cnt_offset(env);
  }
--static const ARMCPRegInfo zcr_el1_reginfo = {
++static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
--    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
++{
--    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
++    /*
--    .access = PL1_RW, .type = ARM_CP_SVE,
++     * Return the timer offset to use for indirect accesses to the timer.
--    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
++     * This is the Offset value as defined in D12.2.4.1 "Operation of the
--    .writefn = zcr_write, .raw_writefn = raw_write
++     * CompareValue views of the timers".
--};
++     *
--
++     * The condition here is not always the same as the condition for
--static const ARMCPRegInfo zcr_el2_reginfo = {
++     * whether to apply an offset register when doing a direct read of
--    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
++     * the counter sysreg; those conditions are described in the
--    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
++     * access pseudocode for each counter register.
--    .access = PL2_RW, .type = ARM_CP_SVE,
++     */
--    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
++    switch (timeridx) {
--    .writefn = zcr_write, .raw_writefn = raw_write
++    case GTIMER_PHYS:
--};
++        return gt_phys_raw_cnt_offset(env);
--
++    case GTIMER_VIRT:
--static const ARMCPRegInfo zcr_no_el2_reginfo = {
++        return env->cp15.cntvoff_el2;
--    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
++    case GTIMER_HYP:
--    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
++    case GTIMER_SEC:
--    .access = PL2_RW, .type = ARM_CP_SVE,
++    case GTIMER_HYPVIRT:
--    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
++        return 0;
--};
++    default:
--
++        g_assert_not_reached();
--static const ARMCPRegInfo zcr_el3_reginfo = {
++    }
--    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
++}
--    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
++
--    .access = PL3_RW, .type = ARM_CP_SVE,
+ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
--    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
+ {
--    .writefn = zcr_write, .raw_writefn = raw_write
+     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
-+static const ARMCPRegInfo zcr_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
-+    { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
+          * Timer enabled: calculate and set current ISTATUS, irq, and
-+      .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
+          * reset timer to when ISTATUS next has to change
-+      .access = PL1_RW, .type = ARM_CP_SVE,
+          */
-+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
+-        uint64_t offset = timeridx == GTIMER_VIRT ?
-+      .writefn = zcr_write, .raw_writefn = raw_write },
+-            cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
-+    { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
++        uint64_t offset = gt_indirect_access_timer_offset(&cpu->env, timeridx);
-+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
+         uint64_t count = gt_get_countervalue(&cpu->env);
-+      .access = PL2_RW, .type = ARM_CP_SVE,
+         /* Note that this must be unsigned 64 bit arithmetic: */
-+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
+         int istatus = count - offset >= gt->cval;
 +      .writefn = zcr_write, .raw_writefn = raw_write },
 +    { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
 +      .access = PL3_RW, .type = ARM_CP_SVE,
 +      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
 +      .writefn = zcr_write, .raw_writefn = raw_write },
  };
  void hw_watchpoint_update(ARMCPU *cpu, int n)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      }
      if (cpu_isar_feature(aa64_sve, cpu)) {
 -        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
 -        if (arm_feature(env, ARM_FEATURE_EL2)) {
 -            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
 -        } else {
 -            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
 -        }
 -        if (arm_feature(env, ARM_FEATURE_EL3)) {
 -            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
 -        }
 +        define_arm_cp_regs(cpu, zcr_reginfo);
      }
  #ifdef TARGET_AARCH64
 --
-.25.1
+.43.0

-[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
+[PULL 05/21] target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
-From: Richard Henderson <richard.henderson@linaro.org>
+The CNTVOFF_EL2 offset register should only be applied for accessses
 to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*).  We were
 incorrectly applying it for the EL2 virtual timer (CNTHV_*).
-This register is present for either VHE or Debugv8p2.
+Cc: qemu-stable@nongnu.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20250204125009.2281315-3-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 15 +++++++++++----
+ target/arm/helper.c | 2 --
-file changed, 11 insertions(+), 4 deletions(-)
+file changed, 2 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
+@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
-       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- };
+     switch (timeridx) {
+     case GTIMER_VIRT:
-+static const ARMCPRegInfo contextidr_el2 = {
+-    case GTIMER_HYPVIRT:
-+    .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+         offset = gt_virt_cnt_offset(env);
-+    .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+         break;
-+    .access = PL2_RW,
+     case GTIMER_PHYS:
-+    .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
-+};
-+
+     switch (timeridx) {
- static const ARMCPRegInfo vhe_reginfo[] = {
+     case GTIMER_VIRT:
--    { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+-    case GTIMER_HYPVIRT:
--      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+         offset = gt_virt_cnt_offset(env);
--      .access = PL2_RW,
+         break;
--      .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
+     case GTIMER_PHYS:
      { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
        .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          define_one_arm_cp_reg(cpu, &ssbs_reginfo);
      }
 +    if (cpu_isar_feature(aa64_vh, cpu) ||
 +        cpu_isar_feature(aa64_debugv8p2, cpu)) {
 +        define_one_arm_cp_reg(cpu, &contextidr_el2);
 +    }
      if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
          define_arm_cp_regs(cpu, vhe_reginfo);
      }
 --
-.25.1
+.43.0

-[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
+[PULL 06/21] target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
-From: Richard Henderson <richard.henderson@linaro.org>
+When we added Secure EL2 support, we missed that this needs an update
 to the access code for the EL3 physical timer registers.  These are
 supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
-Enable writes to the TERR and TEA bits when RAS is enabled.
+(Note for stable backporting: for backports to branches where
-These bits are otherwise RES0.
+CP_ACCESS_UNDEFINED is not defined, the old name to use instead
 is CP_ACCESS_TRAP_UNCATEGORIZED.)
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20250204125009.2281315-4-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 9 +++++++++
+ target/arm/helper.c | 3 +++
-file changed, 9 insertions(+)
+file changed, 3 insertions(+)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
          if (!arm_is_secure(env)) {
              return CP_ACCESS_UNDEFINED;
          }
-         valid_mask &= ~SCR_NET;
++        if (arm_is_el2_enabled(env)) {
++            return CP_ACCESS_UNDEFINED;
 +        if (cpu_isar_feature(aa64_ras, cpu)) {
 +            valid_mask |= SCR_TERR;
 +        }
-         if (cpu_isar_feature(aa64_lor, cpu)) {
+         if (!(env->cp15.scr_el3 & SCR_ST)) {
-             valid_mask |= SCR_TLOR;
+             return CP_ACCESS_TRAP_EL3;
          }
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          }
      } else {
          valid_mask &= ~(SCR_RW | SCR_ST);
 +        if (cpu_isar_feature(aa32_ras, cpu)) {
 +            valid_mask |= SCR_TERR;
 +        }
      }
      if (!arm_feature(env, ARM_FEATURE_EL2)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
          if (cpu_isar_feature(aa64_vh, cpu)) {
              valid_mask |= HCR_E2H;
          }
 +        if (cpu_isar_feature(aa64_ras, cpu)) {
 +            valid_mask |= HCR_TERR | HCR_TEA;
 +        }
          if (cpu_isar_feature(aa64_lor, cpu)) {
              valid_mask |= HCR_TLOR;
          }
 --
-.25.1
+.43.0

-[PULL 14/32] target/arm: Add minimal RAS registers
+[PULL 07/21] target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
-From: Richard Henderson <richard.henderson@linaro.org>
+Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the
 EL1 virt timer.  This is almost correct, but the underlying
 CNTV_TVAL_EL0 register behaves slightly differently.  CNTV_TVAL_EL02
 always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if
 we're at EL2 and HCR_EL2.E2H is 1.
-Add only the system registers required to implement zero error
+We were getting this wrong, because we ended up in
-records.  This means that all values for ERRSELR are out of range,
+gt_virt_cnt_offset() and did the E2H check.
 which means that it and all of the indexed error record registers
 need not be implemented.
-Add the EL2 registers required for injecting virtual SError.
+Factor out the tval read/write calculation from the selection of the
 offset, so that we can special case gt_virt_tval_read() and
 gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20250204125009.2281315-5-peter.maydell@linaro.org
 ---
- target/arm/cpu.h    |  5 +++
+ target/arm/helper.c | 36 +++++++++++++++++++++++++++---------
- target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
+file changed, 27 insertions(+), 9 deletions(-)
 files changed, 89 insertions(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
-         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
-         uint64_t gcr_el1;
-         uint64_t rgsr_el1;
-+
-+        /* Minimal RAS registers */
-+        uint64_t disr_el1;
-+        uint64_t vdisr_el2;
-+        uint64_t vsesr_el2;
-     } cp15;
-     struct {
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
-       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
+     gt_recalc_timer(env_archcpu(env), timeridx);
- };
+ }
-+/*
++static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset)
 + * Check for traps to RAS registers, which are controlled
 + * by HCR_EL2.TERR and SCR_EL3.TERR.
 + */
 +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                  bool isread)
 +{
-+    int el = arm_current_el(env);
++    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
-+
++                      (gt_get_countervalue(env) - offset));
 +    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
 +        return CP_ACCESS_TRAP_EL2;
 +    }
 +    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
 +        return CP_ACCESS_TRAP_EL3;
 +    }
 +    return CP_ACCESS_OK;
 +}
 +
-+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
-+{
+                              int timeridx)
-+    int el = arm_current_el(env);
+ {
-+
+@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
-+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+         break;
-+        return env->cp15.vdisr_el2;
+     }
-+    }
-+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+-    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
-+        return 0; /* RAZ/WI */
+-                      (gt_get_countervalue(env) - offset));
-+    }
++    return do_tval_read(env, timeridx, offset);
 +    return env->cp15.disr_el1;
 +}
 +
-+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
++static void do_tval_write(CPUARMState *env, int timeridx, uint64_t value,
 +                          uint64_t offset)
 +{
-+    int el = arm_current_el(env);
++    trace_arm_gt_tval_write(timeridx, value);
-+
++    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
-+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
++                                         sextract64(value, 0, 32);
-+        env->cp15.vdisr_el2 = val;
++    gt_recalc_timer(env_archcpu(env), timeridx);
-+        return;
+ }
-+    }
-+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
-+        return; /* RAZ/WI */
+@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
-+    }
+         offset = gt_phys_cnt_offset(env);
-+    env->cp15.disr_el1 = val;
+         break;
 +}
 +
 +/*
 + * Minimal RAS implementation with no Error Records.
 + * Which means that all of the Error Record registers:
 + *   ERXADDR_EL1
 + *   ERXCTLR_EL1
 + *   ERXFR_EL1
 + *   ERXMISC0_EL1
 + *   ERXMISC1_EL1
 + *   ERXMISC2_EL1
 + *   ERXMISC3_EL1
 + *   ERXPFGCDN_EL1  (RASv1p1)
 + *   ERXPFGCTL_EL1  (RASv1p1)
 + *   ERXPFGF_EL1    (RASv1p1)
 + *   ERXSTATUS_EL1
 + * and
 + *   ERRSELR_EL1
 + * may generate UNDEFINED, which is the effect we get by not
 + * listing them at all.
 + */
 +static const ARMCPRegInfo minimal_ras_reginfo[] = {
 +    { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
 +      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
 +      .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
 +    { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
 +      .access = PL1_R, .accessfn = access_terr,
 +      .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
 +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
 +    { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
 +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
 +};
 +
  /* Return the exception level to which exceptions should be taken
   * via SVEAccessTrap.  If an exception should be routed through
   * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      if (cpu_isar_feature(aa64_ssbs, cpu)) {
          define_one_arm_cp_reg(cpu, &ssbs_reginfo);
      }
-+    if (cpu_isar_feature(any_ras, cpu)) {
+-
-+        define_arm_cp_regs(cpu, minimal_ras_reginfo);
+-    trace_arm_gt_tval_write(timeridx, value);
-+    }
+-    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
+-                                         sextract64(value, 0, 32);
-     if (cpu_isar_feature(aa64_vh, cpu) ||
+-    gt_recalc_timer(env_archcpu(env), timeridx);
-         cpu_isar_feature(aa64_debugv8p2, cpu)) {
++    do_tval_write(env, timeridx, value, offset);
  }
  static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
  static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
 -    return gt_tval_read(env, ri, GTIMER_VIRT);
 +    /*
 +     * This is CNTV_TVAL_EL02; unlike the underlying CNTV_TVAL_EL0
 +     * we always apply CNTVOFF_EL2. Special case that here rather
 +     * than going into the generic gt_tval_read() and then having
 +     * to re-detect that it's this register.
 +     * Note that the accessfn/perms mean we know we're at EL2 or EL3 here.
 +     */
 +    return do_tval_read(env, GTIMER_VIRT, env->cp15.cntvoff_el2);
  }
  static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                 uint64_t value)
  {
 -    gt_tval_write(env, ri, GTIMER_VIRT, value);
 +    /* Similarly for writes to CNTV_TVAL_EL02 */
 +    do_tval_write(env, GTIMER_VIRT, value, env->cp15.cntvoff_el2);
  }
  static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
 --
-.25.1
+.43.0

-[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
+[PULL 08/21] target/arm: Refactor handling of timer offset for direct register accesses
-From: Richard Henderson <richard.henderson@linaro.org>
+When reading or writing the timer registers, sometimes we need to
+apply one of the timer offsets.  Specifically, this happens for
-Previously we were defining some of these in user-only mode,
+direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and
-but none of them are accessible from user-only, therefore
+their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0).  It
-define them only in system mode.
+also applies for direct reads and writes of the CNT*_TVAL_EL*
+registers that provide the 32-bit downcounting view of each timer.
-This will shortly be used from cpu_tcg.c also.
+We currently do this with duplicated code in gt_tval_read() and
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+gt_tval_write() and a special-case in gt_virt_cnt_read() and
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+gt_cnt_read().  Refactor this so that we handle it all in a single
-Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
+function gt_direct_access_timer_offset(), to parallel how we handle
 the offset for indirect accesses.
 The call in the WFIT helper previously to gt_virt_cnt_offset() is
 now to gt_direct_access_timer_offset(); this is the correct
 behaviour, but it's not immediately obvious that it shouldn't be
 considered an indirect access, so we add an explanatory comment.
 This commit should make no behavioural changes.
 (Cc to stable because the following bugfix commit will
 depend on this one.)
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20250204125009.2281315-6-peter.maydell@linaro.org
 ---
- target/arm/internals.h |  6 ++++
+ target/arm/internals.h     |   5 +-
- target/arm/cpu64.c     | 64 +++---------------------------------------
+ target/arm/helper.c        | 103 +++++++++++++++++++------------------
- target/arm/cpu_tcg.c   | 59 ++++++++++++++++++++++++++++++++++++++
+ target/arm/tcg/op_helper.c |   8 ++-
-files changed, 69 insertions(+), 60 deletions(-)
+files changed, 62 insertions(+), 54 deletions(-)
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
+@@ -XXX,XX +XXX,XX @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type);
- int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
+ uint64_t gt_get_countervalue(CPUARMState *env);
- #endif
+ /*
+  * Return the currently applicable offset between the system counter
-+#ifdef CONFIG_USER_ONLY
+- * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2).
-+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
++ * and the counter for the specified timer, as used for direct register
-+#else
++ * accesses.
-+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+  */
-+#endif
+-uint64_t gt_virt_cnt_offset(CPUARMState *env);
 +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx);
  /*
   * Return mask of ARMMMUIdxBit values corresponding to an "invalidate
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
      return 0;
  }
 -static uint64_t gt_phys_cnt_offset(CPUARMState *env)
 -{
 -    if (arm_current_el(env) >= 2) {
 -        return 0;
 -    }
 -    return gt_phys_raw_cnt_offset(env);
 -}
 -
  static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
  {
      /*
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
      }
  }
 +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx)
 +{
 +    /*
 +     * Return the timer offset to use for direct accesses to the
 +     * counter registers CNTPCT and CNTVCT, and for direct accesses
 +     * to the CNT*_TVAL registers.
 +     *
 +     * This isn't exactly the same as the indirect-access offset,
 +     * because here we also care about what EL the register access
 +     * is being made from.
 +     *
 +     * This corresponds to the access pseudocode for the registers.
 +     */
 +    uint64_t hcr;
 +
- #endif
++    switch (timeridx) {
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
++    case GTIMER_PHYS:
-index XXXXXXX..XXXXXXX 100644
++        if (arm_current_el(env) >= 2) {
---- a/target/arm/cpu64.c
++            return 0;
-+++ b/target/arm/cpu64.c
++        }
-@@ -XXX,XX +XXX,XX @@
++        return gt_phys_raw_cnt_offset(env);
- #include "hvf_arm.h"
++    case GTIMER_VIRT:
- #include "qapi/visitor.h"
++        switch (arm_current_el(env)) {
- #include "hw/qdev-properties.h"
++        case 2:
--#include "cpregs.h"
++            hcr = arm_hcr_el2_eff(env);
-+#include "internals.h"
++            if (hcr & HCR_E2H) {
++                return 0;
++            }
--#ifndef CONFIG_USER_ONLY
++            break;
--static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
++        case 0:
--{
++            hcr = arm_hcr_el2_eff(env);
--    ARMCPU *cpu = env_archcpu(env);
++            if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
--
++                return 0;
--    /* Number of cores is in [25:24]; otherwise we RAZ */
++            }
--    return (cpu->core_count - 1) << 24;
++            break;
--}
++        }
--#endif
++        return env->cp15.cntvoff_el2;
--
++    case GTIMER_HYP:
--static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
++    case GTIMER_SEC:
--#ifndef CONFIG_USER_ONLY
++    case GTIMER_HYPVIRT:
--    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
++        return 0;
--      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
++    default:
--      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
++        g_assert_not_reached();
--      .writefn = arm_cp_write_ignore },
++    }
 -    { .name = "L2CTLR",
 -      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
 -      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
 -      .writefn = arm_cp_write_ignore },
 -#endif
 -    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2ECTLR",
 -      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUACTLR",
 -      .cp = 15, .opc1 = 0, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUECTLR",
 -      .cp = 15, .opc1 = 1, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUMERRSR",
 -      .cp = 15, .opc1 = 2, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2MERRSR",
 -      .cp = 15, .opc1 = 3, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -};
 -
  static void aarch64_a57_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
      cpu->gic_num_lrs = 4;
      cpu->gic_vpribits = 5;
      cpu->gic_vprebits = 5;
 -    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
  static void aarch64_a53_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
      cpu->gic_num_lrs = 4;
      cpu->gic_vpribits = 5;
      cpu->gic_vprebits = 5;
 -    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
  static void aarch64_a72_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      cpu->gic_num_lrs = 4;
      cpu->gic_vpribits = 5;
      cpu->gic_vprebits = 5;
 -    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #endif
  #include "cpregs.h"
 +#ifndef CONFIG_USER_ONLY
 +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +
 +    /* Number of cores is in [25:24]; otherwise we RAZ */
 +    return (cpu->core_count - 1) << 24;
 +}
 +
-+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
-+    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+ {
-+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
-+      .access = PL1_RW, .readfn = l2ctlr_read,
+@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
-+      .writefn = arm_cp_write_ignore },
-+    { .name = "L2CTLR",
+ static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
-+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+ {
-+      .access = PL1_RW, .readfn = l2ctlr_read,
+-    return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
-+      .writefn = arm_cp_write_ignore },
+-}
-+    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+-
-+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+-uint64_t gt_virt_cnt_offset(CPUARMState *env)
-+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+-{
-+    { .name = "L2ECTLR",
+-    uint64_t hcr;
-+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+-
-+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+-    switch (arm_current_el(env)) {
-+    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+-    case 2:
-+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+-        hcr = arm_hcr_el2_eff(env);
-+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+-        if (hcr & HCR_E2H) {
-+    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+-            return 0;
-+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+-        }
-+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+-        break;
-+    { .name = "CPUACTLR",
+-    case 0:
-+      .cp = 15, .opc1 = 0, .crm = 15,
+-        hcr = arm_hcr_el2_eff(env);
-+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+-        if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
-+    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+-            return 0;
-+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+-        }
-+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+-        break;
-+    { .name = "CPUECTLR",
+-    }
-+      .cp = 15, .opc1 = 1, .crm = 15,
+-
-+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+-    return env->cp15.cntvoff_el2;
-+    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
++    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_PHYS);
-+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
++    return gt_get_countervalue(env) - offset;
-+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ }
-+    { .name = "CPUMERRSR",
-+      .cp = 15, .opc1 = 2, .crm = 15,
+ static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
-+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ {
-+    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+-    return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
-+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
++    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);
-+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++    return gt_get_countervalue(env) - offset;
-+    { .name = "L2MERRSR",
+ }
-+      .cp = 15, .opc1 = 3, .crm = 15,
-+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
-+};
+@@ -XXX,XX +XXX,XX @@ static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset)
-+
+ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
-+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+                              int timeridx)
-+{
+ {
-+    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+-    uint64_t offset = 0;
-+}
+-
-+#endif /* !CONFIG_USER_ONLY */
+-    switch (timeridx) {
-+
+-    case GTIMER_VIRT:
- /* CPU models. These are not needed for the AArch64 linux-user build. */
+-        offset = gt_virt_cnt_offset(env);
- #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+-        break;
 -    case GTIMER_PHYS:
 -        offset = gt_phys_cnt_offset(env);
 -        break;
 -    }
 +    uint64_t offset = gt_direct_access_timer_offset(env, timeridx);
      return do_tval_read(env, timeridx, offset);
  }
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                            int timeridx,
                            uint64_t value)
  {
 -    uint64_t offset = 0;
 +    uint64_t offset = gt_direct_access_timer_offset(env, timeridx);
 -    switch (timeridx) {
 -    case GTIMER_VIRT:
 -        offset = gt_virt_cnt_offset(env);
 -        break;
 -    case GTIMER_PHYS:
 -        offset = gt_phys_cnt_offset(env);
 -        break;
 -    }
      do_tval_write(env, timeridx, value, offset);
  }
 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/op_helper.c
 +++ b/target/arm/tcg/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout)
      int target_el = check_wfx_trap(env, false, &excp);
      /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */
      uint64_t cntval = gt_get_countervalue(env);
 -    uint64_t offset = gt_virt_cnt_offset(env);
 +    /*
 +     * We want the value that we would get if we read CNTVCT_EL0 from
 +     * the current exception level, so the direct_access offset, not
 +     * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(),
 +     * which calls VirtualCounterTimer().
 +     */
 +    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);
      uint64_t cntvct = cntval - offset;
      uint64_t nexttick;
 --
-.25.1
+.43.0

-[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Instead of starting with cortex-a15 and adding v8 features to
-a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
-This fixes the long-standing to-do where we only enabled v8
-features for user-only.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
-file changed, 92 insertions(+), 59 deletions(-)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
- static void arm_max_initfn(Object *obj)
- {
-     ARMCPU *cpu = ARM_CPU(obj);
-+    uint32_t t;
--    cortex_a15_initfn(obj);
-+    /* aarch64_a57_initfn, advertising none of the aarch64 features */
-+    cpu->dtb_compatible = "arm,cortex-a57";
-+    set_feature(&cpu->env, ARM_FEATURE_V8);
-+    set_feature(&cpu->env, ARM_FEATURE_NEON);
-+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-+    set_feature(&cpu->env, ARM_FEATURE_EL2);
-+    set_feature(&cpu->env, ARM_FEATURE_EL3);
-+    set_feature(&cpu->env, ARM_FEATURE_PMU);
-+    cpu->midr = 0x411fd070;
-+    cpu->revidr = 0x00000000;
-+    cpu->reset_fpsid = 0x41034070;
-+    cpu->isar.mvfr0 = 0x10110222;
-+    cpu->isar.mvfr1 = 0x12111111;
-+    cpu->isar.mvfr2 = 0x00000043;
-+    cpu->ctr = 0x8444c004;
-+    cpu->reset_sctlr = 0x00c50838;
-+    cpu->isar.id_pfr0 = 0x00000131;
-+    cpu->isar.id_pfr1 = 0x00011011;
-+    cpu->isar.id_dfr0 = 0x03010066;
-+    cpu->id_afr0 = 0x00000000;
-+    cpu->isar.id_mmfr0 = 0x10101105;
-+    cpu->isar.id_mmfr1 = 0x40000000;
-+    cpu->isar.id_mmfr2 = 0x01260000;
-+    cpu->isar.id_mmfr3 = 0x02102211;
-+    cpu->isar.id_isar0 = 0x02101110;
-+    cpu->isar.id_isar1 = 0x13112111;
-+    cpu->isar.id_isar2 = 0x21232042;
-+    cpu->isar.id_isar3 = 0x01112131;
-+    cpu->isar.id_isar4 = 0x00011142;
-+    cpu->isar.id_isar5 = 0x00011121;
-+    cpu->isar.id_isar6 = 0;
-+    cpu->isar.dbgdidr = 0x3516d000;
-+    cpu->clidr = 0x0a200023;
-+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
-+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
-+    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
-+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
--    /* old-style VFP short-vector support */
--    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
-+    /* Add additional features supported by QEMU */
-+    t = cpu->isar.id_isar5;
-+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-+    cpu->isar.id_isar5 = t;
-+
-+    t = cpu->isar.id_isar6;
-+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-+    cpu->isar.id_isar6 = t;
-+
-+    t = cpu->isar.mvfr1;
-+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-+    cpu->isar.mvfr1 = t;
-+
-+    t = cpu->isar.mvfr2;
-+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-+    cpu->isar.mvfr2 = t;
-+
-+    t = cpu->isar.id_mmfr3;
-+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-+    cpu->isar.id_mmfr3 = t;
-+
-+    t = cpu->isar.id_mmfr4;
-+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-+    cpu->isar.id_mmfr4 = t;
-+
-+    t = cpu->isar.id_pfr0;
-+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-+    cpu->isar.id_pfr0 = t;
-+
-+    t = cpu->isar.id_pfr2;
-+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-+    cpu->isar.id_pfr2 = t;
- #ifdef CONFIG_USER_ONLY
-     /*
--     * We don't set these in system emulation mode for the moment,
--     * since we don't correctly set (all of) the ID registers to
--     * advertise them.
-+     * Break with true ARMv8 and add back old-style VFP short-vector support.
-+     * Only do this for user-mode, where -cpu max is the default, so that
-+     * older v6 and v7 programs are more likely to work without adjustment.
-      */
--    set_feature(&cpu->env, ARM_FEATURE_V8);
--    {
--        uint32_t t;
--
--        t = cpu->isar.id_isar5;
--        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
--        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
--        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
--        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
--        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
--        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
--        cpu->isar.id_isar5 = t;
--
--        t = cpu->isar.id_isar6;
--        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
--        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
--        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
--        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
--        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
--        t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
--        t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
--        cpu->isar.id_isar6 = t;
--
--        t = cpu->isar.mvfr1;
--        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
--        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
--        cpu->isar.mvfr1 = t;
--
--        t = cpu->isar.mvfr2;
--        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
--        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
--        cpu->isar.mvfr2 = t;
--
--        t = cpu->isar.id_mmfr3;
--        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
--        cpu->isar.id_mmfr3 = t;
--
--        t = cpu->isar.id_mmfr4;
--        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
--        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
--        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
--        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
--        cpu->isar.id_mmfr4 = t;
--
--        t = cpu->isar.id_pfr0;
--        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
--        cpu->isar.id_pfr0 = t;
--
--        t = cpu->isar.id_pfr2;
--        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
--        cpu->isar.id_pfr2 = t;
--    }
--#endif /* CONFIG_USER_ONLY */
-+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
-+#endif
- }
- #endif /* !TARGET_AARCH64 */
---
-.25.1

-[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-We set this for qemu-system-aarch64, but failed to do so
-for the strictly 32-bit emulation.
-Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu_tcg.c | 4 ++++
-file changed, 4 insertions(+)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
-     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-     cpu->isar.id_pfr2 = t;
-+    t = cpu->isar.id_dfr0;
-+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-+    cpu->isar.id_dfr0 = t;
-+
- #ifdef CONFIG_USER_ONLY
-     /*
-      * Break with true ARMv8 and add back old-style VFP short-vector support.
---
-.25.1

-[PULL 09/32] target/arm: Split out aa32_max_features
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Share the code to set AArch32 max features so that we no
-longer have code drift between qemu{-system,}-{arm,aarch64}.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/internals.h |   2 +
- target/arm/cpu64.c     |  50 +-----------------
- target/arm/cpu_tcg.c   | 114 ++++++++++++++++++++++-------------------
-files changed, 65 insertions(+), 101 deletions(-)
-diff --git a/target/arm/internals.h b/target/arm/internals.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
-+++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
- void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
- #endif
-+void aa32_max_features(ARMCPU *cpu);
-+
- #endif
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
- {
-     ARMCPU *cpu = ARM_CPU(obj);
-     uint64_t t;
--    uint32_t u;
-     if (kvm_enabled() || hvf_enabled()) {
-         /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
-     cpu->isar.id_aa64zfr0 = t;
--    /* Replicate the same data to the 32-bit id registers.  */
--    u = cpu->isar.id_isar5;
--    u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
--    u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
--    u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
--    u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
--    u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
--    u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
--    cpu->isar.id_isar5 = u;
--
--    u = cpu->isar.id_isar6;
--    u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
--    u = FIELD_DP32(u, ID_ISAR6, DP, 1);
--    u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
--    u = FIELD_DP32(u, ID_ISAR6, SB, 1);
--    u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
--    u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
--    u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
--    cpu->isar.id_isar6 = u;
--
--    u = cpu->isar.id_pfr0;
--    u = FIELD_DP32(u, ID_PFR0, DIT, 1);
--    cpu->isar.id_pfr0 = u;
--
--    u = cpu->isar.id_pfr2;
--    u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
--    cpu->isar.id_pfr2 = u;
--
--    u = cpu->isar.id_mmfr3;
--    u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
--    cpu->isar.id_mmfr3 = u;
--
--    u = cpu->isar.id_mmfr4;
--    u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
--    u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
--    u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
--    u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
--    cpu->isar.id_mmfr4 = u;
--
-     t = cpu->isar.id_aa64dfr0;
-     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
-     cpu->isar.id_aa64dfr0 = t;
--    u = cpu->isar.id_dfr0;
--    u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
--    cpu->isar.id_dfr0 = u;
--
--    u = cpu->isar.mvfr1;
--    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
--    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
--    cpu->isar.mvfr1 = u;
-+    /* Replicate the same data to the 32-bit id registers.  */
-+    aa32_max_features(cpu);
- #ifdef CONFIG_USER_ONLY
-     /*
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@
- #endif
- #include "cpregs.h"
-+
-+/* Share AArch32 -cpu max features with AArch64. */
-+void aa32_max_features(ARMCPU *cpu)
-+{
-+    uint32_t t;
-+
-+    /* Add additional features supported by QEMU */
-+    t = cpu->isar.id_isar5;
-+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-+    cpu->isar.id_isar5 = t;
-+
-+    t = cpu->isar.id_isar6;
-+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-+    cpu->isar.id_isar6 = t;
-+
-+    t = cpu->isar.mvfr1;
-+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-+    cpu->isar.mvfr1 = t;
-+
-+    t = cpu->isar.mvfr2;
-+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-+    cpu->isar.mvfr2 = t;
-+
-+    t = cpu->isar.id_mmfr3;
-+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-+    cpu->isar.id_mmfr3 = t;
-+
-+    t = cpu->isar.id_mmfr4;
-+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-+    cpu->isar.id_mmfr4 = t;
-+
-+    t = cpu->isar.id_pfr0;
-+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-+    cpu->isar.id_pfr0 = t;
-+
-+    t = cpu->isar.id_pfr2;
-+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-+    cpu->isar.id_pfr2 = t;
-+
-+    t = cpu->isar.id_dfr0;
-+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-+    cpu->isar.id_dfr0 = t;
-+}
-+
- #ifndef CONFIG_USER_ONLY
- static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
- {
-@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
- static void arm_max_initfn(Object *obj)
- {
-     ARMCPU *cpu = ARM_CPU(obj);
--    uint32_t t;
-     /* aarch64_a57_initfn, advertising none of the aarch64 features */
-     cpu->dtb_compatible = "arm,cortex-a57";
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
-     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
-     define_cortex_a72_a57_a53_cp_reginfo(cpu);
--    /* Add additional features supported by QEMU */
--    t = cpu->isar.id_isar5;
--    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
--    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
--    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
--    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
--    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
--    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
--    cpu->isar.id_isar5 = t;
--
--    t = cpu->isar.id_isar6;
--    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
--    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
--    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
--    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
--    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
--    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
--    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
--    cpu->isar.id_isar6 = t;
--
--    t = cpu->isar.mvfr1;
--    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
--    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
--    cpu->isar.mvfr1 = t;
--
--    t = cpu->isar.mvfr2;
--    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
--    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
--    cpu->isar.mvfr2 = t;
--
--    t = cpu->isar.id_mmfr3;
--    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
--    cpu->isar.id_mmfr3 = t;
--
--    t = cpu->isar.id_mmfr4;
--    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
--    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
--    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
--    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
--    cpu->isar.id_mmfr4 = t;
--
--    t = cpu->isar.id_pfr0;
--    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
--    cpu->isar.id_pfr0 = t;
--
--    t = cpu->isar.id_pfr2;
--    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
--    cpu->isar.id_pfr2 = t;
--
--    t = cpu->isar.id_dfr0;
--    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
--    cpu->isar.id_dfr0 = t;
-+    aa32_max_features(cpu);
- #ifdef CONFIG_USER_ONLY
-     /*
---
-.25.1

-[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
+[PULL 09/21] target/arm: Implement SEL2 physical and virtual timers
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Alex Bennée <alex.bennee@linaro.org>
-There is no branch prediction in TCG, therefore there is no
+When FEAT_SEL2 was implemented the SEL2 timers were missed. This
-need to actually include the context number into the predictor.
+shows up when building the latest Hafnium with SPMC_AT_EL=2. The
-Therefore all we need to do is add the state for SCXTNUM_ELx.
+actual implementation utilises the same logic as the rest of the
+timers so all we need to do is:
   - define the timers and their access functions
   - conditionally add the correct system registers
   - create a new accessfn as the rules are subtly different to the
     existing secure timer
 Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers)
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20250204125009.2281315-7-peter.maydell@linaro.org
-Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
+Cc: qemu-stable@nongnu.org
 Cc: Andrei Homescu <ahomescu@google.com>
 Cc: Arve Hjønnevåg <arve@google.com>
 Cc: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
 [PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED;
  offset logic now in gt_{indirect,direct}_access_timer_offset() ]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/emulation.rst |  3 ++
+ include/hw/arm/bsa.h |   2 +
- target/arm/cpu.h              | 16 +++++++++
+ target/arm/cpu.h     |   2 +
- target/arm/cpu.c              |  5 +++
+ target/arm/gtimer.h  |   4 +-
- target/arm/cpu64.c            |  3 +-
+ target/arm/cpu.c     |   4 ++
- target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
+ target/arm/helper.c  | 163 +++++++++++++++++++++++++++++++++++++++++++
-files changed, 86 insertions(+), 2 deletions(-)
+files changed, 174 insertions(+), 1 deletion(-)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/include/hw/arm/bsa.h
-+++ b/docs/system/arm/emulation.rst
++++ b/include/hw/arm/bsa.h
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@
- - FEAT_BF16 (AArch64 BFloat16 instructions)
+ #define QEMU_ARM_BSA_H
- - FEAT_BTI (Branch Target Identification)
- - FEAT_CSV2 (Cache speculation variant 2)
+ /* These are architectural INTID values */
-+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
++#define ARCH_TIMER_S_EL2_VIRT_IRQ  19
-+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
++#define ARCH_TIMER_S_EL2_IRQ       20
-+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
+ #define VIRTUAL_PMU_IRQ            23
- - FEAT_DIT (Data Independent Timing instructions)
+ #define ARCH_GIC_MAINT_IRQ         25
- - FEAT_DPB (DC CVAP instruction)
+ #define ARCH_TIMER_NS_EL2_IRQ      26
  - FEAT_Debugv8p2 (Debug changes for v8.2)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+@@ -XXX,XX +XXX,XX @@ void arm_gt_vtimer_cb(void *opaque);
-         ARMPACKey apdb;
+ void arm_gt_htimer_cb(void *opaque);
-         ARMPACKey apga;
+ void arm_gt_stimer_cb(void *opaque);
-     } keys;
+ void arm_gt_hvtimer_cb(void *opaque);
-+
++void arm_gt_sel2timer_cb(void *opaque);
-+    uint64_t scxtnum_el[4];
++void arm_gt_sel2vtimer_cb(void *opaque);
  unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
  void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
 diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gtimer.h
 +++ b/target/arm/gtimer.h
@@ -XXX,XX +XXX,XX @@ enum {
      GTIMER_HYP      = 2,
      GTIMER_SEC      = 3,
      GTIMER_HYPVIRT  = 4,
 -#define NUM_GTIMERS   5
 +    GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */
 +    GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */
 +#define NUM_GTIMERS   7
  };
  #endif
- #if defined(CONFIG_USER_ONLY)
-@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
- #define SCTLR_WXN     (1U << 19)
- #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
- #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
-+#define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
- #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
- #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
- #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
- }
-+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
-+{
-+    int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
-+    if (key >= 2) {
-+        return true;      /* FEAT_CSV2_2 */
-+    }
-+    if (key == 1) {
-+        key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
-+        return key >= 2;  /* FEAT_CSV2_1p2 */
-+    }
-+    return false;
-+}
-+
- static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
- {
-     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-              */
+                                               arm_gt_stimer_cb, cpu);
-             env->cp15.gcr_el1 = 0x1ffff;
+         cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
-         }
+                                                   arm_gt_hvtimer_cb, cpu);
-+        /*
++        cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
-+         * Disable access to SCXTNUM_EL0 from CSV2_1p2.
++                                                     arm_gt_sel2timer_cb, cpu);
-+         * This is not yet exposed from the Linux kernel in any way.
++        cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
-+         */
++                                                     arm_gt_sel2vtimer_cb, cpu);
-+        env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
+     }
- #else
+ #endif
-         /* Reset into the highest available EL */
          if (arm_feature(env, ARM_FEATURE_EL3)) {
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
      t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
      t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
 -    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
      cpu->isar.id_aa64pfr0 = t;
      t = cpu->isar.id_aa64pfr1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
       * we do for EL2 with the virtualization=on property.
       */
      t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
 +    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
      cpu->isar.id_aa64pfr1 = t;
      t = cpu->isar.id_aa64mmfr0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
-         if (cpu_isar_feature(aa64_mte, cpu)) {
+     }
-             valid_mask |= SCR_ATA;
+ }
-         }
-+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
++static CPAccessResult gt_sel2timer_access(CPUARMState *env,
-+            valid_mask |= SCR_ENSCXT;
++                                          const ARMCPRegInfo *ri,
 +                                          bool isread)
 +{
 +    /*
 +     * The AArch64 register view of the secure EL2 timers are mostly
 +     * accessible from EL3 and EL2 although can also be trapped to EL2
 +     * from EL1 depending on nested virt config.
 +     */
 +    switch (arm_current_el(env)) {
 +    case 0: /* UNDEFINED */
 +        return CP_ACCESS_UNDEFINED;
 +    case 1:
 +        if (!arm_is_secure(env)) {
 +            /* UNDEFINED */
 +            return CP_ACCESS_UNDEFINED;
 +        } else if (arm_hcr_el2_eff(env) & HCR_NV) {
 +            /* Aarch64.SystemAccessTrap(EL2, 0x18) */
 +            return CP_ACCESS_TRAP_EL2;
 +        }
-     } else {
++        /* UNDEFINED */
-         valid_mask &= ~(SCR_RW | SCR_ST);
++        return CP_ACCESS_UNDEFINED;
-         if (cpu_isar_feature(aa32_ras, cpu)) {
++    case 2:
-@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
++        if (!arm_is_secure(env)) {
-         if (cpu_isar_feature(aa64_mte, cpu)) {
++            /* UNDEFINED */
-             valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
++            return CP_ACCESS_UNDEFINED;
          }
 +        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
 +            valid_mask |= HCR_ENSCXT;
 +        }
-     }
++        return CP_ACCESS_OK;
++    case 3:
-     /* Clear RES0 bits.  */
++        if (env->cp15.scr_el3 & SCR_EEL2) {
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
++            return CP_ACCESS_OK;
-         { K(3, 0,  5, 6, 0), K(3, 4,  5, 6, 0), K(3, 5, 5, 6, 0),
++        } else {
-           "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
++            return CP_ACCESS_UNDEFINED;
++        }
-+        { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
++    default:
-+          "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
++        g_assert_not_reached();
-+          isar_feature_aa64_scxtnum },
++    }
-+
++}
-         /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
++
-         /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
+ uint64_t gt_get_countervalue(CPUARMState *env)
-     };
+ {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
+     ARMCPU *cpu = env_archcpu(env);
-     },
+@@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
      case GTIMER_HYP:
      case GTIMER_SEC:
      case GTIMER_HYPVIRT:
 +    case GTIMER_S_EL2_PHYS:
 +    case GTIMER_S_EL2_VIRT:
          return 0;
      default:
          g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx)
      case GTIMER_HYP:
      case GTIMER_SEC:
      case GTIMER_HYPVIRT:
 +    case GTIMER_S_EL2_PHYS:
 +    case GTIMER_S_EL2_VIRT:
          return 0;
      default:
          g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
      gt_ctl_write(env, ri, GTIMER_SEC, value);
  }
 +static void gt_sec_pel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    gt_timer_reset(env, ri, GTIMER_S_EL2_PHYS);
 +}
 +
 +static void gt_sec_pel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                   uint64_t value)
 +{
 +    gt_cval_write(env, ri, GTIMER_S_EL2_PHYS, value);
 +}
 +
 +static uint64_t gt_sec_pel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    return gt_tval_read(env, ri, GTIMER_S_EL2_PHYS);
 +}
 +
 +static void gt_sec_pel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                              uint64_t value)
 +{
 +    gt_tval_write(env, ri, GTIMER_S_EL2_PHYS, value);
 +}
 +
 +static void gt_sec_pel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                              uint64_t value)
 +{
 +    gt_ctl_write(env, ri, GTIMER_S_EL2_PHYS, value);
 +}
 +
 +static void gt_sec_vel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    gt_timer_reset(env, ri, GTIMER_S_EL2_VIRT);
 +}
 +
 +static void gt_sec_vel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                              uint64_t value)
 +{
 +    gt_cval_write(env, ri, GTIMER_S_EL2_VIRT, value);
 +}
 +
 +static uint64_t gt_sec_vel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    return gt_tval_read(env, ri, GTIMER_S_EL2_VIRT);
 +}
 +
 +static void gt_sec_vel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                   uint64_t value)
 +{
 +    gt_tval_write(env, ri, GTIMER_S_EL2_VIRT, value);
 +}
 +
 +static void gt_sec_vel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                              uint64_t value)
 +{
 +    gt_ctl_write(env, ri, GTIMER_S_EL2_VIRT, value);
 +}
 +
  static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
  {
      gt_timer_reset(env, ri, GTIMER_HYPVIRT);
@@ -XXX,XX +XXX,XX @@ void arm_gt_stimer_cb(void *opaque)
      gt_recalc_timer(cpu, GTIMER_SEC);
  }
 +void arm_gt_sel2timer_cb(void *opaque)
 +{
 +    ARMCPU *cpu = opaque;
 +
 +    gt_recalc_timer(cpu, GTIMER_S_EL2_PHYS);
 +}
 +
 +void arm_gt_sel2vtimer_cb(void *opaque)
 +{
 +    ARMCPU *cpu = opaque;
 +
 +    gt_recalc_timer(cpu, GTIMER_S_EL2_VIRT);
 +}
 +
  void arm_gt_hvtimer_cb(void *opaque)
  {
      ARMCPU *cpu = opaque;
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
        .access = PL2_RW, .accessfn = sel2_access,
        .nv2_redirect_offset = 0x48,
        .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
 +#ifndef CONFIG_USER_ONLY
 +    /* Secure EL2 Physical Timer */
 +    { .name = "CNTHPS_TVAL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0,
 +      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .readfn = gt_sec_pel2_tval_read,
 +      .writefn = gt_sec_pel2_tval_write,
 +      .resetfn = gt_sec_pel2_timer_reset,
 +    },
 +    { .name = "CNTHPS_CTL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 1,
 +      .type = ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].ctl),
 +      .resetvalue = 0,
 +      .writefn = gt_sec_pel2_ctl_write, .raw_writefn = raw_write,
 +    },
 +    { .name = "CNTHPS_CVAL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 2,
 +      .type = ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].cval),
 +      .writefn = gt_sec_pel2_cval_write, .raw_writefn = raw_write,
 +    },
 +    /* Secure EL2 Virtual Timer */
 +    { .name = "CNTHVS_TVAL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0,
 +      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .readfn = gt_sec_vel2_tval_read,
 +      .writefn = gt_sec_vel2_tval_write,
 +      .resetfn = gt_sec_vel2_timer_reset,
 +    },
 +    { .name = "CNTHVS_CTL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 1,
 +      .type = ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].ctl),
 +      .resetvalue = 0,
 +      .writefn = gt_sec_vel2_ctl_write, .raw_writefn = raw_write,
 +    },
 +    { .name = "CNTHVS_CVAL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 2,
 +      .type = ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].cval),
 +      .writefn = gt_sec_vel2_cval_write, .raw_writefn = raw_write,
 +    },
 +#endif
  };
--#endif
+ static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                     bool isread)
 +{
 +    uint64_t hcr = arm_hcr_el2_eff(env);
 +    int el = arm_current_el(env);
 +
 +    if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
 +        if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
 +            if (hcr & HCR_TGE) {
 +                return CP_ACCESS_TRAP_EL2;
 +            }
 +            return CP_ACCESS_TRAP;
 +        }
 +    } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
 +        return CP_ACCESS_TRAP_EL2;
 +    }
 +    if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
 +        return CP_ACCESS_TRAP_EL2;
 +    }
 +    if (el < 3
 +        && arm_feature(env, ARM_FEATURE_EL3)
 +        && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
 +        return CP_ACCESS_TRAP_EL3;
 +    }
 +    return CP_ACCESS_OK;
 +}
 +
 +static const ARMCPRegInfo scxtnum_reginfo[] = {
 +    { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL0_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
 +    { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL1_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
 +    { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL2_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
 +    { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL3_RW,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
 +};
 +#endif /* TARGET_AARCH64 */
  static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
                                       bool isread)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
          define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
      }
 +
 +    if (cpu_isar_feature(aa64_scxtnum, cpu)) {
 +        define_arm_cp_regs(cpu, scxtnum_reginfo);
 +    }
  #endif
      if (cpu_isar_feature(any_predinv, cpu)) {
 --
-.25.1
+.43.0

-[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
+[PULL 10/21] target/arm: Document the architectural names of our GTIMERs
-From: Gavin Shan <gshan@redhat.com>
+From: Alex Bennée <alex.bennee@linaro.org>
-When CPU-to-NUMA association isn't explicitly provided by users,
+As we are about to add more physical and virtual timers let's make it
-the default one is given by mc->get_default_cpu_node_id(). However,
+clear what each timer does.
 the CPU topology isn't fully considered in the default association
 and this causes CPU topology broken warnings on booting Linux guest.
-For example, the following warning messages are observed when the
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Linux guest is booted with the following command lines.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-  /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
+Message-id: 20250204125009.2281315-8-peter.maydell@linaro.org
-  -accel kvm -machine virt,gic-version=host               \
+[PMM: Add timer register name prefix to each comment]
-  -cpu host                                               \
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
   -smp 6,sockets=2,cores=3,threads=1                      \
   -m 1024M,slots=16,maxmem=64G                            \
   -object memory-backend-ram,id=mem0,size=128M            \
   -object memory-backend-ram,id=mem1,size=128M            \
   -object memory-backend-ram,id=mem2,size=128M            \
   -object memory-backend-ram,id=mem3,size=128M            \
   -object memory-backend-ram,id=mem4,size=128M            \
   -object memory-backend-ram,id=mem4,size=384M            \
   -numa node,nodeid=0,memdev=mem0                         \
   -numa node,nodeid=1,memdev=mem1                         \
   -numa node,nodeid=2,memdev=mem2                         \
   -numa node,nodeid=3,memdev=mem3                         \
   -numa node,nodeid=4,memdev=mem4                         \
   -numa node,nodeid=5,memdev=mem5
          :
   alternatives: patching kernel code
   BUG: arch topology borken
   the CLS domain not a subset of the MC domain
   <the above error log repeats>
   BUG: arch topology borken
   the DIE domain not a subset of the NODE domain
 With current implementation of mc->get_default_cpu_node_id(),
 CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
 That's incorrect because CPU#0/1/2 should be associated with same
 NUMA node because they're seated in same socket.
 This fixes the issue by considering the socket ID when the default
 CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
 With this applied, no more CPU topology broken warnings are seen
 from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
 there are no CPUs associated with NODE#2/3/4/5.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Message-id: 20220503140304.855514-6-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 4 +++-
+ target/arm/gtimer.h | 10 +++++-----
-file changed, 3 insertions(+), 1 deletion(-)
+file changed, 5 insertions(+), 5 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/target/arm/gtimer.h
-+++ b/hw/arm/virt.c
++++ b/target/arm/gtimer.h
-@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
+@@ -XXX,XX +XXX,XX @@
+ #define TARGET_ARM_GTIMER_H
- static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
- {
+ enum {
--    return idx % ms->numa_state->num_nodes;
+-    GTIMER_PHYS     = 0,
-+    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
+-    GTIMER_VIRT     = 1,
-+
+-    GTIMER_HYP      = 2,
-+    return socket_id % ms->numa_state->num_nodes;
+-    GTIMER_SEC      = 3,
- }
+-    GTIMER_HYPVIRT  = 4,
++    GTIMER_PHYS     = 0, /* CNTP_* ; EL1 physical timer */
- static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
++    GTIMER_VIRT     = 1, /* CNTV_* ; EL1 virtual timer */
 +    GTIMER_HYP      = 2, /* CNTHP_* ; EL2 physical timer */
 +    GTIMER_SEC      = 3, /* CNTPS_* ; EL3 physical timer */
 +    GTIMER_HYPVIRT  = 4, /* CNTHV_* ; EL2 virtual timer ; only if FEAT_VHE */
      GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */
      GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */
  #define NUM_GTIMERS   7
 --
-.25.1
+.43.0

-[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
+[PULL 11/21] hw/arm: enable secure EL2 timers for virt machine
-From: Gavin Shan <gshan@redhat.com>
+From: Alex Bennée <alex.bennee@linaro.org>
-Currently, the SMP configuration isn't considered when the CPU
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-topology is populated. In this case, it's impossible to provide
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-the default CPU-to-NUMA mapping or association based on the socket
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-ID of the given CPU.
+Message-id: 20250204125009.2281315-9-peter.maydell@linaro.org
+Cc: qemu-stable@nongnu.org
-This takes account of SMP configuration when the CPU topology
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 is populated. The die ID for the given CPU isn't assigned since
 it's not supported on arm/virt machine. Besides, the used SMP
 configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
 to avoid testing failure
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Acked-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20220503140304.855514-4-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 15 ++++++++++++++-
+ hw/arm/virt.c | 2 ++
-file changed, 14 insertions(+), 1 deletion(-)
+file changed, 2 insertions(+)
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
+@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
-     int n;
+             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
-     unsigned int max_cpus = ms->smp.max_cpus;
+             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
-     VirtMachineState *vms = VIRT_MACHINE(ms);
+             [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
-+    MachineClass *mc = MACHINE_GET_CLASS(vms);
++            [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
++            [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
-     if (ms->possible_cpus) {
+         };
-         assert(ms->possible_cpus->len == max_cpus);
-@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
+         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
          ms->possible_cpus->cpus[n].type = ms->cpu_type;
          ms->possible_cpus->cpus[n].arch_id =
              virt_cpu_mp_affinity(vms, n);
 +
 +        assert(!mc->smp_props.dies_supported);
 +        ms->possible_cpus->cpus[n].props.has_socket_id = true;
 +        ms->possible_cpus->cpus[n].props.socket_id =
 +            n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
 +        ms->possible_cpus->cpus[n].props.has_cluster_id = true;
 +        ms->possible_cpus->cpus[n].props.cluster_id =
 +            (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
 +        ms->possible_cpus->cpus[n].props.has_core_id = true;
 +        ms->possible_cpus->cpus[n].props.core_id =
 +            (n / ms->smp.threads) % ms->smp.cores;
          ms->possible_cpus->cpus[n].props.has_thread_id = true;
 -        ms->possible_cpus->cpus[n].props.thread_id = n;
 +        ms->possible_cpus->cpus[n].props.thread_id =
 +            n % ms->smp.threads;
      }
      return ms->possible_cpus;
  }
 --
-.25.1
+.43.0

-[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
+[PULL 12/21] hw/arm: enable secure EL2 timers for sbsa machine
-From: Leif Lindholm <quic_llindhol@quicinc.com>
+From: Alex Bennée <alex.bennee@linaro.org>
-The sbsa-ref machine is continuously evolving. Some of the changes we
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 want to make in the near future, to align with real components (e.g.
 the GIC-700), will break compatibility for existing firmware.
 Introduce two new properties to the DT generated on machine generation:
 - machine-version-major
   To be incremented when a platform change makes the machine
   incompatible with existing firmware.
 - machine-version-minor
   To be incremented when functionality is added to the machine
   without causing incompatibility with existing firmware.
   to be reset to 0 when machine-version-major is incremented.
 This versioning scheme is *neither*:
 - A QEMU versioned machine type; a given version of QEMU will emulate
   a given version of the platform.
 - A reflection of level of SBSA (now SystemReady SR) support provided.
 The version will increment on guest-visible functional changes only,
 akin to a revision ID register found on a physical platform.
 These properties are both introduced with the value 0.
 (Hence, a machine where the DT is lacking these nodes is equivalent
 to version 0.0.)
 Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
 Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Cc: Radoslaw Biernacki <rad@semihalf.com>
 Cc: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20250204125009.2281315-10-peter.maydell@linaro.org
+Cc: qemu-stable@nongnu.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/sbsa-ref.c | 14 ++++++++++++++
+ hw/arm/sbsa-ref.c | 2 ++
-file changed, 14 insertions(+)
+file changed, 2 insertions(+)
 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/sbsa-ref.c
 +++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
+@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
-     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
+             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
-     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
+             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
+             [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
-+    /*
++            [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
-+     * This versioning scheme is for informing platform fw only. It is neither:
++            [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
-+     * - A QEMU versioned machine type; a given version of QEMU will emulate
+         };
-+     *   a given version of the platform.
-+     * - A reflection of level of SBSA (now SystemReady SR) support provided.
+         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 +     *
 +     * machine-version-major: updated when changes breaking fw compatibility
 +     *                        are introduced.
 +     * machine-version-minor: updated when features are added that don't break
 +     *                        fw compatibility.
 +     */
 +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
 +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
 +
      if (ms->numa_state->have_numa_distance) {
          int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
          uint32_t *matrix = g_malloc0(size);
 --
-.25.1
+.43.0

-[PULL 25/32] target/arm: Define neoverse-n1
+[PULL 13/21] target/arm: Correct LDRD atomicity and fault behaviour
-From: Richard Henderson <richard.henderson@linaro.org>
+Our LDRD implementation is wrong in two respects:
-Enable the n1 for virt and sbsa board use.
+ * if the address is 4-aligned and the load crosses a page boundary
    and the second load faults and the first load was to the
    base register (as in cases like "ldrd r2, r3, [r2]", then we
    must not update the base register before taking the fault
  * if the address is 8-aligned the access must be a 64-bit
    single-copy atomic access, not two 32-bit accesses
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Rewrite the handling of the loads in LDRD to use a single
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+tcg_gen_qemu_ld_i64() and split the result into the destination
-Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
+registers. This allows us to get the atomicity requirements
 right, and also implicitly means that we won't update the
 base register too early for the page-crossing case.
 Note that because we no longer increment 'addr' by 4 in the course of
 performing the LDRD we must change the adjustment value we pass to
 op_addr_ri_post() and op_addr_rr_post(): it no longer needs to
 subtract 4 to get the correct value to use if doing base register
 writeback.
 STRD has the same problem with not getting the atomicity right;
 we will deal with that in the following commit.
 Cc: qemu-stable@nongnu.org
 Reported-by: Stu Grossman <stu.grossman@gmail.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20250227142746.1698904-2-peter.maydell@linaro.org
 ---
- docs/system/arm/virt.rst |  1 +
+ target/arm/tcg/translate.c | 70 +++++++++++++++++++++++++-------------
- hw/arm/sbsa-ref.c        |  1 +
+file changed, 46 insertions(+), 24 deletions(-)
  hw/arm/virt.c            |  1 +
  target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 files changed, 69 insertions(+)
-diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
+diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/virt.rst
+--- a/target/arm/tcg/translate.c
-+++ b/docs/system/arm/virt.rst
++++ b/target/arm/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
+@@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
- - ``cortex-a76`` (64-bit)
+     return true;
  - ``a64fx`` (64-bit)
  - ``host`` (with KVM only)
 +- ``neoverse-n1`` (64-bit)
  - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
  Note that the default is ``cortex-a15``, so for an AArch64 guest you must
 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/sbsa-ref.c
 +++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
      ARM_CPU_TYPE_NAME("cortex-a57"),
      ARM_CPU_TYPE_NAME("cortex-a72"),
      ARM_CPU_TYPE_NAME("cortex-a76"),
 +    ARM_CPU_TYPE_NAME("neoverse-n1"),
      ARM_CPU_TYPE_NAME("max"),
  };
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
      ARM_CPU_TYPE_NAME("cortex-a72"),
      ARM_CPU_TYPE_NAME("cortex-a76"),
      ARM_CPU_TYPE_NAME("a64fx"),
 +    ARM_CPU_TYPE_NAME("neoverse-n1"),
      ARM_CPU_TYPE_NAME("host"),
      ARM_CPU_TYPE_NAME("max"),
  };
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
      cpu->isar.mvfr2 = 0x00000043;
  }
-+static void aarch64_neoverse_n1_initfn(Object *obj)
++static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
 +{
-+    ARMCPU *cpu = ARM_CPU(obj);
++    /*
 +     * LDRD is required to be an atomic 64-bit access if the
 +     * address is 8-aligned, two atomic 32-bit accesses if
 +     * it's only 4-aligned, and to give an alignment fault
 +     * if it's not 4-aligned. This is MO_ALIGN_4 | MO_ATOM_SUBALIGN.
 +     * Rt is always the word from the lower address, and Rt2 the
 +     * data from the higher address, regardless of endianness.
 +     * So (like gen_load_exclusive) we avoid gen_aa32_ld_i64()
 +     * so we don't get its SCTLR_B check, and instead do a 64-bit access
 +     * using MO_BE if appropriate and then split the two halves.
 +     *
 +     * For M-profile, and for A-profile before LPAE, the 64-bit
 +     * atomicity is not required. We could model that using
 +     * the looser MO_ATOM_IFALIGN_PAIR, but providing a higher
 +     * level of atomicity than required is harmless (we would not
 +     * currently generate better code for IFALIGN_PAIR here).
 +     *
 +     * This also gives us the correct behaviour of not updating
 +     * rt if the load of rt2 faults; this is required for cases
 +     * like "ldrd r2, r3, [r2]" where rt is also the base register.
 +     */
 +    int mem_idx = get_mem_index(s);
 +    MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
 +    TCGv taddr = gen_aa32_addr(s, addr, opc);
 +    TCGv_i64 t64 = tcg_temp_new_i64();
 +    TCGv_i32 tmp = tcg_temp_new_i32();
 +    TCGv_i32 tmp2 = tcg_temp_new_i32();
 +
-+    cpu->dtb_compatible = "arm,neoverse-n1";
++    tcg_gen_qemu_ld_i64(t64, taddr, mem_idx, opc);
-+    set_feature(&cpu->env, ARM_FEATURE_V8);
++    if (s->be_data == MO_BE) {
-+    set_feature(&cpu->env, ARM_FEATURE_NEON);
++        tcg_gen_extr_i64_i32(tmp2, tmp, t64);
-+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
++    } else {
-+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
++        tcg_gen_extr_i64_i32(tmp, tmp2, t64);
-+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
++    }
-+    set_feature(&cpu->env, ARM_FEATURE_EL2);
++    store_reg(s, rt, tmp);
-+    set_feature(&cpu->env, ARM_FEATURE_EL3);
++    store_reg(s, rt2, tmp2);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444c004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0c1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.23 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
 +
 +    /* From B2.98 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +}
 +
- void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
  {
-     /*
+-    int mem_idx = get_mem_index(s);
-@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
+-    TCGv_i32 addr, tmp;
-     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
++    TCGv_i32 addr;
-     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
-     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+     if (!ENABLE_ARCH_5TE) {
-+    { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
+         return false;
-     { .name = "max",                .initfn = aarch64_max_initfn },
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
- #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
+     }
-     { .name = "host",               .initfn = aarch64_host_initfn },
+     addr = op_addr_rr_pre(s, a);
 -    tmp = tcg_temp_new_i32();
 -    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
 -    store_reg(s, a->rt, tmp);
 -
 -    tcg_gen_addi_i32(addr, addr, 4);
 -
 -    tmp = tcg_temp_new_i32();
 -    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
 -    store_reg(s, a->rt + 1, tmp);
 +    do_ldrd_load(s, addr, a->rt, a->rt + 1);
      /* LDRD w/ base writeback is undefined if the registers overlap.  */
 -    op_addr_rr_post(s, a, addr, -4);
 +    op_addr_rr_post(s, a, addr, 0);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
  static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
  {
 -    int mem_idx = get_mem_index(s);
 -    TCGv_i32 addr, tmp;
 +    TCGv_i32 addr;
      addr = op_addr_ri_pre(s, a);
 -    tmp = tcg_temp_new_i32();
 -    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
 -    store_reg(s, a->rt, tmp);
 -
 -    tcg_gen_addi_i32(addr, addr, 4);
 -
 -    tmp = tcg_temp_new_i32();
 -    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
 -    store_reg(s, rt2, tmp);
 +    do_ldrd_load(s, addr, a->rt, rt2);
      /* LDRD w/ base writeback is undefined if the registers overlap.  */
 -    op_addr_ri_post(s, a, addr, -4);
 +    op_addr_ri_post(s, a, addr, 0);
      return true;
  }
 --
-.25.1
+.43.0

-[PULL 17/32] target/arm: Implement ESB instruction
+[PULL 14/21] target/arm: Correct STRD atomicity
-From: Richard Henderson <richard.henderson@linaro.org>
+Our STRD implementation doesn't correctly implement the requirement:
  * if the address is 8-aligned the access must be a 64-bit
    single-copy atomic access, not two 32-bit accesses
-Check for and defer any pending virtual SError.
+Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64()
 of a value produced by concatenating the two 32 bit source registers.
 This allows us to get the atomicity right.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+As with the LDRD change, now that we don't update 'addr' in the
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+course of performing the store we need to adjust the offset
-Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
+we pass to op_addr_ri_post() and op_addr_rr_post().
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20250227142746.1698904-3-peter.maydell@linaro.org
 ---
- target/arm/helper.h        |  1 +
+ target/arm/tcg/translate.c | 59 +++++++++++++++++++++++++-------------
- target/arm/a32.decode      | 16 ++++++++------
+file changed, 39 insertions(+), 20 deletions(-)
  target/arm/t32.decode      | 18 ++++++++--------
  target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-a64.c | 17 +++++++++++++++
  target/arm/translate.c     | 23 ++++++++++++++++++++
 files changed, 103 insertions(+), 15 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/target/arm/tcg/translate.c
-+++ b/target/arm/helper.h
++++ b/target/arm/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
- DEF_HELPER_1(yield, void, env)
+     return true;
  DEF_HELPER_1(pre_hvc, void, env)
  DEF_HELPER_2(pre_smc, void, env, i32)
 +DEF_HELPER_1(vesb, void, env)
  DEF_HELPER_3(cpsr_write, void, env, i32, i32)
  DEF_HELPER_2(cpsr_write_eret, void, env, i32)
 diff --git a/target/arm/a32.decode b/target/arm/a32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/a32.decode
 +++ b/target/arm/a32.decode
@@ -XXX,XX +XXX,XX @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
  {
    {
 -    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
 -    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
 -    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
 +    [
 +      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
 +      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
 +      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 -    # TODO: Implement SEV, SEVL; may help SMP performance.
 -    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
 -    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
 +      # TODO: Implement SEV, SEVL; may help SMP performance.
 +      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
 +      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
 +
 +      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
 +    ]
      # The canonical nop ends in 00000000, but the whole of the
      # rest of the space executes as nop if otherwise unsupported.
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
    [
      # Hints, and CPS
      {
 -      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
 -      WFE        1111 0011 1010 1111 1000 0000 0000 0010
 -      WFI        1111 0011 1010 1111 1000 0000 0000 0011
 +      [
 +        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
 +        WFE      1111 0011 1010 1111 1000 0000 0000 0010
 +        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 -      # TODO: Implement SEV, SEVL; may help SMP performance.
 -      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
 -      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
 +        # TODO: Implement SEV, SEVL; may help SMP performance.
 +        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
 +        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 -      # For M-profile minimal-RAS ESB can be a NOP, which is the
 -      # default behaviour since it is in the hint space.
 -      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +        ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +      ]
        # The canonical nop ends in 0000 0000, but the whole rest
        # of the space is "reserved hint, behaves as nop".
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/op_helper.c
 +++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                       access_type, mmu_idx, ra);
      }
  }
-+
-+/*
++static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
 + * This function corresponds to AArch64.vESBOperation().
 + * Note that the AArch32 version is not functionally different.
 + */
 +void HELPER(vesb)(CPUARMState *env)
 +{
 +    /*
-+     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
++     * STRD is required to be an atomic 64-bit access if the
-+     * and will return HCR_EL2.VSE == 0, so nothing happens.
++     * address is 8-aligned, two atomic 32-bit accesses if
 +     * it's only 4-aligned, and to give an alignment fault
 +     * if it's not 4-aligned.
 +     * Rt is always the word from the lower address, and Rt2 the
 +     * data from the higher address, regardless of endianness.
 +     * So (like gen_store_exclusive) we avoid gen_aa32_ld_i64()
 +     * so we don't get its SCTLR_B check, and instead do a 64-bit access
 +     * using MO_BE if appropriate, using a value constructed
 +     * by putting the two halves together in the right order.
 +     *
 +     * As with LDRD, the 64-bit atomicity is not required for
 +     * M-profile, or for A-profile before LPAE, and we provide
 +     * the higher guarantee always for simplicity.
 +     */
-+    uint64_t hcr = arm_hcr_el2_eff(env);
++    int mem_idx = get_mem_index(s);
-+    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
++    MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
-+    bool pending = enabled && (hcr & HCR_VSE);
++    TCGv taddr = gen_aa32_addr(s, addr, opc);
-+    bool masked  = (env->daif & PSTATE_A);
++    TCGv_i32 t1 = load_reg(s, rt);
 +    TCGv_i32 t2 = load_reg(s, rt2);
 +    TCGv_i64 t64 = tcg_temp_new_i64();
 +
-+    /* If VSE pending and masked, defer the exception.  */
++    if (s->be_data == MO_BE) {
-+    if (pending && masked) {
++        tcg_gen_concat_i32_i64(t64, t2, t1);
-+        uint32_t syndrome;
++    } else {
 +        tcg_gen_concat_i32_i64(t64, t1, t2);
 +    }
 +    tcg_gen_qemu_st_i64(t64, taddr, mem_idx, opc);
 +}
 +
-+        if (arm_el_is_aa64(env, 1)) {
+ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
-+            /* Copy across IDS and ISS from VSESR. */
+ {
-+            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
+-    int mem_idx = get_mem_index(s);
-+        } else {
+-    TCGv_i32 addr, tmp;
-+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
++    TCGv_i32 addr;
-+
-+            if (extended_addresses_enabled(env)) {
+     if (!ENABLE_ARCH_5TE) {
-+                syndrome = arm_fi_to_lfsc(&fi);
+         return false;
-+            } else {
+@@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
-+                syndrome = arm_fi_to_sfsc(&fi);
+     }
-+            }
+     addr = op_addr_rr_pre(s, a);
-+            /* Copy across AET and ExT from VSESR. */
-+            syndrome |= env->cp15.vsesr_el2 & 0xd000;
+-    tmp = load_reg(s, a->rt);
-+        }
+-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-+
++    do_strd_store(s, addr, a->rt, a->rt + 1);
-+        /* Set VDISR_EL2.A along with the syndrome. */
-+        env->cp15.vdisr_el2 = syndrome | (1u << 31);
+-    tcg_gen_addi_i32(addr, addr, 4);
-+
+-
-+        /* Clear pending virtual SError */
+-    tmp = load_reg(s, a->rt + 1);
-+        env->cp15.hcr_el2 &= ~HCR_VSE;
+-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-+        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
+-
-+    }
+-    op_addr_rr_post(s, a, addr, -4);
-+}
++    op_addr_rr_post(s, a, addr, 0);
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
              gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
          }
          break;
 +    case 0b10000: /* ESB */
 +        /* Without RAS, we must implement this as NOP. */
 +        if (dc_isar_feature(aa64_ras, s)) {
 +            /*
 +             * QEMU does not have a source of physical SErrors,
 +             * so we are only concerned with virtual SErrors.
 +             * The pseudocode in the ARM for this case is
 +             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
 +             *      AArch64.vESBOperation();
 +             * Most of the condition can be evaluated at translation time.
 +             * Test for EL2 present, and defer test for SEL2 to runtime.
 +             */
 +            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
 +                gen_helper_vesb(cpu_env);
 +            }
 +        }
 +        break;
      case 0b11000: /* PACIAZ */
          if (s->pauth_active) {
              gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
      return true;
  }
-+static bool trans_ESB(DisasContext *s, arg_ESB *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a)
-+{
-+    /*
+ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
 +     * For M-profile, minimal-RAS ESB can be a NOP.
 +     * Without RAS, we must implement this as NOP.
 +     */
 +    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
 +        /*
 +         * QEMU does not have a source of physical SErrors,
 +         * so we are only concerned with virtual SErrors.
 +         * The pseudocode in the ARM for this case is
 +         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
 +         *      AArch32.vESBOperation();
 +         * Most of the condition can be evaluated at translation time.
 +         * Test for EL2 present, and defer test for SEL2 to runtime.
 +         */
 +        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
 +            gen_helper_vesb(cpu_env);
 +        }
 +    }
 +    return true;
 +}
 +
  static bool trans_NOP(DisasContext *s, arg_NOP *a)
  {
+-    int mem_idx = get_mem_index(s);
+-    TCGv_i32 addr, tmp;
++    TCGv_i32 addr;
+     addr = op_addr_ri_pre(s, a);
+-    tmp = load_reg(s, a->rt);
+-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
++    do_strd_store(s, addr, a->rt, rt2);
+-    tcg_gen_addi_i32(addr, addr, 4);
+-
+-    tmp = load_reg(s, rt2);
+-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+-
+-    op_addr_ri_post(s, a, addr, -4);
++    op_addr_ri_post(s, a, addr, 0);
      return true;
+ }
 --
-.25.1
+.43.0

-[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
+[PULL 15/21] target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
-From: Gavin Shan <gshan@redhat.com>
+All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in
 zero for the address_offset, so we can remove that argument.
-The CPU topology isn't enabled on arm/virt machine yet, but we're
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-going to do it in next patch. After the CPU topology is enabled by
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-next patch, "thread-id=1" becomes invalid because the CPU core is
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-preferred on arm/virt machine. It means these two CPUs have 0/1
+Message-id: 20250227142746.1698904-4-peter.maydell@linaro.org
-as their core IDs, but their thread IDs are all 0. It will trigger
+---
-test failure as the following message indicates:
+ target/arm/tcg/translate.c | 26 +++++++++++++-------------
 file changed, 13 insertions(+), 13 deletions(-)
-  [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test  ERROR
+diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
 .48s   killed by signal 6 SIGABRT
   >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
       QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon         \
       QTEST_QEMU_BINARY=./qemu-system-aarch64                                       \
       QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83                                  \
       /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
   ――――――――――――――――――――――――――――――――――――――――――――――
   stderr:
   qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
 This fixes the issue by providing comprehensive SMP configurations
 in aarch64_numa_cpu(). The SMP configurations aren't used before
 the CPU topology is enabled in next patch.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Message-id: 20220503140304.855514-3-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/qtest/numa-test.c | 3 ++-
 file changed, 2 insertions(+), 1 deletion(-)
 diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/numa-test.c
+--- a/target/arm/tcg/translate.c
-+++ b/tests/qtest/numa-test.c
++++ b/target/arm/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
+@@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a)
-     QTestState *qts;
+ }
-     g_autofree char *cli = NULL;
+ static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
--    cli = make_cli(data, "-machine smp.cpus=2 "
+-                            TCGv_i32 addr, int address_offset)
-+    cli = make_cli(data, "-machine "
++                            TCGv_i32 addr)
-+        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+ {
-         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
+     if (!a->p) {
-         "-numa cpu,node-id=1,thread-id=0 "
+         TCGv_i32 ofs = load_reg(s, a->rm);
-         "-numa cpu,node-id=0,thread-id=1");
+@@ -XXX,XX +XXX,XX @@ static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
      } else if (!a->w) {
          return;
      }
 -    tcg_gen_addi_i32(addr, addr, address_offset);
      store_reg(s, a->rn, addr);
  }
@@ -XXX,XX +XXX,XX @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a,
       * Perform base writeback before the loaded value to
       * ensure correct behavior with overlapping index registers.
       */
 -    op_addr_rr_post(s, a, addr, 0);
 +    op_addr_rr_post(s, a, addr);
      store_reg_from_load(s, a->rt, tmp);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
      gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
      disas_set_da_iss(s, mop, issinfo);
 -    op_addr_rr_post(s, a, addr, 0);
 +    op_addr_rr_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
      do_ldrd_load(s, addr, a->rt, a->rt + 1);
      /* LDRD w/ base writeback is undefined if the registers overlap.  */
 -    op_addr_rr_post(s, a, addr, 0);
 +    op_addr_rr_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
      do_strd_store(s, addr, a->rt, a->rt + 1);
 -    op_addr_rr_post(s, a, addr, 0);
 +    op_addr_rr_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a)
  }
  static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a,
 -                            TCGv_i32 addr, int address_offset)
 +                            TCGv_i32 addr)
  {
 +    int address_offset = 0;
      if (!a->p) {
          if (a->u) {
 -            address_offset += a->imm;
 +            address_offset = a->imm;
          } else {
 -            address_offset -= a->imm;
 +            address_offset = -a->imm;
          }
      } else if (!a->w) {
          return;
@@ -XXX,XX +XXX,XX @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a,
       * Perform base writeback before the loaded value to
       * ensure correct behavior with overlapping index registers.
       */
 -    op_addr_ri_post(s, a, addr, 0);
 +    op_addr_ri_post(s, a, addr);
      store_reg_from_load(s, a->rt, tmp);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
      gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
      disas_set_da_iss(s, mop, issinfo);
 -    op_addr_ri_post(s, a, addr, 0);
 +    op_addr_ri_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
      do_ldrd_load(s, addr, a->rt, rt2);
      /* LDRD w/ base writeback is undefined if the registers overlap.  */
 -    op_addr_ri_post(s, a, addr, 0);
 +    op_addr_ri_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
      do_strd_store(s, addr, a->rt, rt2);
 -    op_addr_ri_post(s, a, addr, 0);
 +    op_addr_ri_post(s, a, addr);
      return true;
  }
 --
-.25.1
+.43.0

-[PULL 24/32] target/arm: Define cortex-a76
+[PULL 16/21] target/arm: Make dummy debug registers RAZ, not NOP
-From: Richard Henderson <richard.henderson@linaro.org>
+In debug_helper.c we provide a few dummy versions of
 debug registers:
  * DBGVCR (AArch32 only): enable bits for vector-catch
    debug events
  * MDCCINT_EL1: interrupt enable bits for the DCC
    debug communications channel
  * DBGVCR32_EL2: the AArch64 accessor for the state in
    DBGVCR
-Enable the a76 for virt and sbsa board use.
+We implemented these only to stop Linux crashing on startup,
 but we chose to implement them as ARM_CP_NOP. This worked
 for Linux where it only cares about trying to write to these
 registers, but is very confusing behaviour for anything that
 wants to read the registers (perhaps for context state switches),
 because the destination register will be left with whatever
 random value it happened to have before the read.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Model these registers instead as RAZ.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
+Fixes: 5e8b12ffbb8c68 ("target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0")
 Fixes: 5dbdc4342f479d ("target-arm: Implement dummy MDCCINT_EL1")
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2708
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20250228162424.1917269-1-peter.maydell@linaro.org
 ---
- docs/system/arm/virt.rst |  1 +
+ target/arm/debug_helper.c | 7 ++++---
- hw/arm/sbsa-ref.c        |  1 +
+file changed, 4 insertions(+), 3 deletions(-)
  hw/arm/virt.c            |  1 +
  target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 files changed, 69 insertions(+)
-diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/virt.rst
+--- a/target/arm/debug_helper.c
-+++ b/docs/system/arm/virt.rst
++++ b/target/arm/debug_helper.c
-@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
- - ``cortex-a53`` (64-bit)
+     { .name = "DBGVCR",
- - ``cortex-a57`` (64-bit)
+       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
- - ``cortex-a72`` (64-bit)
+       .access = PL1_RW, .accessfn = access_tda,
-+- ``cortex-a76`` (64-bit)
+-      .type = ARM_CP_NOP },
- - ``a64fx`` (64-bit)
++      .type = ARM_CP_CONST, .resetvalue = 0 },
- - ``host`` (with KVM only)
+     /*
- - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
+      * Dummy MDCCINT_EL1, since we don't implement the Debug Communications
-diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
+      * Channel but Linux may try to access this register. The 32-bit
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
---- a/hw/arm/sbsa-ref.c
+     { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
-+++ b/hw/arm/sbsa-ref.c
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
-@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
+       .access = PL1_RW, .accessfn = access_tdcc,
- static const char * const valid_cpus[] = {
+-      .type = ARM_CP_NOP },
-     ARM_CPU_TYPE_NAME("cortex-a57"),
++      .type = ARM_CP_CONST, .resetvalue = 0 },
-     ARM_CPU_TYPE_NAME("cortex-a72"),
+     /*
-+    ARM_CPU_TYPE_NAME("cortex-a76"),
+      * Dummy DBGCLAIM registers.
-     ARM_CPU_TYPE_NAME("max"),
+      * "The architecture does not define any functionality for the CLAIM tag bits.",
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_aa32_el1_reginfo[] = {
      { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
        .access = PL2_RW, .accessfn = access_dbgvcr32,
 -      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
 +      .type = ARM_CP_CONST | ARM_CP_EL3_NO_EL2_KEEP,
 +      .resetvalue = 0 },
  };
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
      ARM_CPU_TYPE_NAME("cortex-a53"),
      ARM_CPU_TYPE_NAME("cortex-a57"),
      ARM_CPU_TYPE_NAME("cortex-a72"),
 +    ARM_CPU_TYPE_NAME("cortex-a76"),
      ARM_CPU_TYPE_NAME("a64fx"),
      ARM_CPU_TYPE_NAME("host"),
      ARM_CPU_TYPE_NAME("max"),
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
 +static void aarch64_a76_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,cortex-a76";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444C004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0b1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.18 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
 +
 +    /* From B2.93 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +}
 +
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
  {
      /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
      { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
      { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
      { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
 +    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
      { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
      { .name = "max",                .initfn = aarch64_max_initfn },
  #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
 --
-.25.1
+.43.0

-[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
+[PULL 17/21] util/qemu-timer.c: Don't warp timer from timerlist_rearm()
-From: Richard Henderson <richard.henderson@linaro.org>
+Currently we call icount_start_warp_timer() from timerlist_rearm().
 This produces incorrect behaviour, because timerlist_rearm() is
 called, for instance, when a timer callback modifies its timer.  We
 cannot decide here to warp the timer forwards to the next timer
 deadline merely because all_cpu_threads_idle() is true, because the
 timer callback we were called from (or some other callback later in
 the list of callbacks being invoked) may be about to raise a CPU
 interrupt and move a CPU from idle to ready.
-Update the legacy feature names to the current names.
+The only valid place to choose to warp the timer forward is from the
-Provide feature names for id changes that were not marked.
+main loop, when we know we have no outstanding IO or timer callbacks
-Sort the field updates into increasing bitfield order.
+that might be about to wake up a CPU.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+For Arm guests, this bug was mostly latent until the refactoring
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+commit f6fc36deef6abc ("target/arm/helper: Implement
-Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
+CNTHCTL_EL2.CNT[VP]MASK"), which exposed it because it refactored a
 timer callback so that it happened to call timer_mod() first and
 raise the interrupt second, when it had previously raised the
 interrupt first and called timer_mod() afterwards.
 This call seems to have originally derived from the
 pre-record-and-replay icount code, which (as of e.g.  commit
 db1a49726c3c in 2010) in this location did a call to
 qemu_notify_event(), necessary to get the icount code in the vCPU
 round-robin thread to stop and recalculate the icount deadline when a
 timer was reprogrammed from the IO thread.  In current QEMU,
 everything is done on the vCPU thread when we are in icount mode, so
 there's no need to try to notify another thread here.
 I suspect that the other reason why this call was doing icount timer
 warping is that it pre-dates commit efab87cf79077a from 2015, which
 added a call to icount_start_warp_timer() to main_loop_wait().  Once
 the call in timerlist_rearm() has been removed, if the timer
 callbacks don't cause any CPU to be woken up then we will end up
 calling icount_start_warp_timer() from main_loop_wait() when the rr
 main loop code calls rr_wait_io_event().
 Remove the incorrect call from timerlist_rearm().
 Cc: qemu-stable@nongnu.org
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2703
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20250210135804.3526943-1-peter.maydell@linaro.org
 ---
- target/arm/cpu64.c   | 100 +++++++++++++++++++++----------------------
+ util/qemu-timer.c | 4 ----
- target/arm/cpu_tcg.c |  48 ++++++++++-----------
+file changed, 4 deletions(-)
 files changed, 74 insertions(+), 74 deletions(-)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+diff --git a/util/qemu-timer.c b/util/qemu-timer.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/util/qemu-timer.c
-+++ b/target/arm/cpu64.c
++++ b/util/qemu-timer.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static bool timer_mod_ns_locked(QEMUTimerList *timer_list,
-     cpu->midr = t;
+ static void timerlist_rearm(QEMUTimerList *timer_list)
-     t = cpu->isar.id_aa64isar0;
+ {
--    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
+-    /* Interrupt execution to force deadline recalculation.  */
--    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
+-    if (icount_enabled() && timer_list->clock->type == QEMU_CLOCK_VIRTUAL) {
--    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
+-        icount_start_warp_timer();
-+    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
+-    }
-+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
+     timerlist_notify(timer_list);
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
      t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
 -    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
 -    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
 +    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
      cpu->isar.id_aa64isar0 = t;
      t = cpu->isar.id_aa64isar1;
 -    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
 -    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
 +    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
      cpu->isar.id_aa64isar1 = t;
      t = cpu->isar.id_aa64pfr0;
 +    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
 +    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
      cpu->isar.id_aa64pfr0 = t;
      t = cpu->isar.id_aa64pfr1;
 -    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
 +    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
 +    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
      /*
       * Begin with full support for MTE. This will be downgraded to MTE=0
       * during realize if the board provides no tag memory, much like
       * we do for EL2 with the virtualization=on property.
       */
 -    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
 +    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
      cpu->isar.id_aa64pfr1 = t;
      t = cpu->isar.id_aa64mmfr0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      cpu->isar.id_aa64mmfr0 = t;
      t = cpu->isar.id_aa64mmfr1;
 -    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
      cpu->isar.id_aa64mmfr1 = t;
      t = cpu->isar.id_aa64mmfr2;
 -    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
      cpu->isar.id_aa64mmfr2 = t;
      t = cpu->isar.id_aa64zfr0;
      t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
 -    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
 +    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
      cpu->isar.id_aa64zfr0 = t;
      t = cpu->isar.id_aa64dfr0;
 -    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
 +    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
      cpu->isar.id_aa64dfr0 = t;
      /* Replicate the same data to the 32-bit id registers.  */
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
      /* Add additional features supported by QEMU */
      t = cpu->isar.id_isar5;
 -    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 -    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
 +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
 +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
      t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
 +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
      cpu->isar.id_isar5 = t;
      t = cpu->isar.id_isar6;
 -    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
 +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
 +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
 +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
 +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
 +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
 +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
      cpu->isar.id_isar6 = t;
      t = cpu->isar.mvfr1;
 -    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 -    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 +    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
 +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
      cpu->isar.mvfr1 = t;
      t = cpu->isar.mvfr2;
 -    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 -    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
 +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
      cpu->isar.mvfr2 = t;
      t = cpu->isar.id_mmfr3;
 -    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
      cpu->isar.id_mmfr3 = t;
      t = cpu->isar.id_mmfr4;
 -    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 -    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
 +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
 +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
      cpu->isar.id_mmfr4 = t;
      t = cpu->isar.id_pfr0;
 -    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
      cpu->isar.id_pfr0 = t;
      t = cpu->isar.id_pfr2;
 -    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
      cpu->isar.id_pfr2 = t;
      t = cpu->isar.id_dfr0;
 -    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
 +    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
      cpu->isar.id_dfr0 = t;
  }
 --
-.25.1
+.43.0

-[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
-during arm_cpu_realizefn.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.c | 22 +++++++++++++---------
-file changed, 13 insertions(+), 9 deletions(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-          */
-         unset_feature(env, ARM_FEATURE_EL3);
--        /* Disable the security extension feature bits in the processor feature
--         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
-+        /*
-+         * Disable the security extension feature bits in the processor
-+         * feature registers as well.
-          */
--        cpu->isar.id_pfr1 &= ~0xf0;
--        cpu->isar.id_aa64pfr0 &= ~0xf000;
-+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
-+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-+                                           ID_AA64PFR0, EL3, 0);
-     }
-     if (!cpu->has_el2) {
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-     }
-     if (!arm_feature(env, ARM_FEATURE_EL2)) {
--        /* Disable the hypervisor feature bits in the processor feature
--         * registers if we don't have EL2. These are id_pfr1[15:12] and
--         * id_aa64pfr0_el1[11:8].
-+        /*
-+         * Disable the hypervisor feature bits in the processor feature
-+         * registers if we don't have EL2.
-          */
--        cpu->isar.id_aa64pfr0 &= ~0xf00;
--        cpu->isar.id_pfr1 &= ~0xf000;
-+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-+                                           ID_AA64PFR0, EL2, 0);
-+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
-+                                       ID_PFR1, VIRTUALIZATION, 0);
-     }
- #ifndef CONFIG_USER_ONLY
---
-.25.1

-[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The only portion of FEAT_Debugv8p2 that is relevant to QEMU
-is CONTEXTIDR_EL2, which is also conditionally implemented
-with FEAT_VHE.  The rest of the debug extension concerns the
-External debug interface, which is outside the scope of QEMU.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu.c              | 1 +
- target/arm/cpu64.c            | 1 +
- target/arm/cpu_tcg.c          | 2 ++
-files changed, 5 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_BTI (Branch Target Identification)
- - FEAT_DIT (Data Independent Timing instructions)
- - FEAT_DPB (DC CVAP instruction)
-+- FEAT_Debugv8p2 (Debug changes for v8.2)
- - FEAT_DotProd (Advanced SIMD dot product instructions)
- - FEAT_FCMA (Floating-point complex number instructions)
- - FEAT_FHM (Floating-point half-precision multiplication instructions)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-          * feature registers as well.
-          */
-         cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
-+        cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
-         cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-                                            ID_AA64PFR0, EL3, 0);
-     }
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     cpu->isar.id_aa64zfr0 = t;
-     t = cpu->isar.id_aa64dfr0;
-+    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8);  /* FEAT_Debugv8p2 */
-     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
-     cpu->isar.id_aa64dfr0 = t;
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     cpu->isar.id_pfr2 = t;
-     t = cpu->isar.id_dfr0;
-+    t = FIELD_DP32(t, ID_DFR0, COPDBG, 8);        /* FEAT_Debugv8p2 */
-+    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8);       /* FEAT_Debugv8p2 */
-     t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
-     cpu->isar.id_dfr0 = t;
- }
---
-.25.1

-[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This extension concerns changes to the External Debug interface,
-with Secure and Non-secure access to the debug registers, and all
-of it is outside the scope of QEMU.  Indicating support for this
-is mandatory with FEAT_SEL2, which we do implement.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 2 +-
- target/arm/cpu_tcg.c          | 4 ++--
-files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_DIT (Data Independent Timing instructions)
- - FEAT_DPB (DC CVAP instruction)
- - FEAT_Debugv8p2 (Debug changes for v8.2)
-+- FEAT_Debugv8p4 (Debug changes for v8.4)
- - FEAT_DotProd (Advanced SIMD dot product instructions)
- - FEAT_FCMA (Floating-point complex number instructions)
- - FEAT_FHM (Floating-point half-precision multiplication instructions)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     cpu->isar.id_aa64zfr0 = t;
-     t = cpu->isar.id_aa64dfr0;
--    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8);  /* FEAT_Debugv8p2 */
-+    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9);  /* FEAT_Debugv8p4 */
-     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
-     cpu->isar.id_aa64dfr0 = t;
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     cpu->isar.id_pfr2 = t;
-     t = cpu->isar.id_dfr0;
--    t = FIELD_DP32(t, ID_DFR0, COPDBG, 8);        /* FEAT_Debugv8p2 */
--    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8);       /* FEAT_Debugv8p2 */
-+    t = FIELD_DP32(t, ID_DFR0, COPDBG, 9);        /* FEAT_Debugv8p4 */
-+    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9);       /* FEAT_Debugv8p4 */
-     t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
-     cpu->isar.id_dfr0 = t;
- }
---
-.25.1

-[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
+[PULL 18/21] include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
-From: Gavin Shan <gshan@redhat.com>
+Expand the example in the comment documenting MO_ATOM_SUBALIGN,
 to be clearer about the atomicity guarantees it represents.
-In aarch64_numa_cpu(), the CPU and NUMA association is something
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-like below. Two threads in the same core/cluster/socket are
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-associated with two individual NUMA nodes, which is unreal as
+Message-id: 20250228103222.1838913-1-peter.maydell@linaro.org
-Igor Mammedov mentioned. We don't expect the association to break
+---
-NUMA-to-socket boundary, which matches with the real world.
+ include/exec/memop.h | 8 ++++++--
 file changed, 6 insertions(+), 2 deletions(-)
-    NUMA-node  socket  cluster   core   thread
+diff --git a/include/exec/memop.h b/include/exec/memop.h
     ------------------------------------------
 0        0        0      0
 0        0        0      1
 This corrects the topology for CPUs and their association with
 NUMA nodes. After this patch is applied, the CPU and NUMA
 association becomes something like below, which looks real.
 Besides, socket/cluster/core/thread IDs are all checked when
 the NUMA node IDs are verified. It helps to check if the CPU
 topology is properly populated or not.
     NUMA-node  socket  cluster   core   thread
     ------------------------------------------
 1        0        0       0
 0        0        0       0
 Suggested-by: Igor Mammedov <imammedo@redhat.com>
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Acked-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20220503140304.855514-5-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/qtest/numa-test.c | 18 ++++++++++++------
 file changed, 12 insertions(+), 6 deletions(-)
 diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/numa-test.c
+--- a/include/exec/memop.h
-+++ b/tests/qtest/numa-test.c
++++ b/include/exec/memop.h
-@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
+@@ -XXX,XX +XXX,XX @@ typedef enum MemOp {
-     g_autofree char *cli = NULL;
+      *    Depending on alignment, one or both will be single-copy atomic.
+      *    This is the atomicity e.g. of Arm FEAT_LSE2 LDP.
-     cli = make_cli(data, "-machine "
+      * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts
--        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+-     *    by the alignment.  E.g. if the address is 0 mod 4, then each
-+        "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
+-     *    4-byte subobject is single-copy atomic.
-         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
++     *    by the alignment.  E.g. if an 8-byte value is accessed at an
--        "-numa cpu,node-id=1,thread-id=0 "
++     *    address which is 0 mod 8, then the whole 8-byte access is
--        "-numa cpu,node-id=0,thread-id=1");
++     *    single-copy atomic; otherwise, if it is accessed at 0 mod 4
-+        "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
++     *    then each 4-byte subobject is single-copy atomic; otherwise
-+        "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
++     *    if it is accessed at 0 mod 2 then the four 2-byte subobjects
-     qts = qtest_init(cli);
++     *    are single-copy atomic.
-     cpus = get_cpus(qts, &resp);
+      *    This is the atomicity e.g. of IBM Power.
-     g_assert(cpus);
+      * MO_ATOM_NONE: the operation has no atomicity requirements.
+      *
      while ((e = qlist_pop(cpus))) {
          QDict *cpu, *props;
 -        int64_t thread, node;
 +        int64_t socket, cluster, core, thread, node;
          cpu = qobject_to(QDict, e);
          g_assert(qdict_haskey(cpu, "props"));
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
          g_assert(qdict_haskey(props, "node-id"));
          node = qdict_get_int(props, "node-id");
 +        g_assert(qdict_haskey(props, "socket-id"));
 +        socket = qdict_get_int(props, "socket-id");
 +        g_assert(qdict_haskey(props, "cluster-id"));
 +        cluster = qdict_get_int(props, "cluster-id");
 +        g_assert(qdict_haskey(props, "core-id"));
 +        core = qdict_get_int(props, "core-id");
          g_assert(qdict_haskey(props, "thread-id"));
          thread = qdict_get_int(props, "thread-id");
 -        if (thread == 0) {
 +        if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
              g_assert_cmpint(node, ==, 1);
 -        } else if (thread == 1) {
 +        } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
              g_assert_cmpint(node, ==, 0);
          } else {
              g_assert(false);
 --
-.25.1
+.43.0

-[PULL 16/32] target/arm: Implement virtual SError exceptions
+[PULL 19/21] hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
-From: Richard Henderson <richard.henderson@linaro.org>
+From: JianChunfu <jansef.jian@hj-micro.com>
-Virtual SError exceptions are raised by setting HCR_EL2.VSE,
+Use a similar terminology smmu_hash_remove_by_sid_range() as the one
-and are routed to EL1 just like other virtual exceptions.
+being used for other hash table matching functions since
 smmuv3_invalidate_ste() name is not self explanatory, and introduce a
 helper that invokes the g_hash_table_foreach_remove.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+No functional change intended.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
+Signed-off-by: JianChunfu <jansef.jian@hj-micro.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20250228031438.3916-1-jansef.jian@hj-micro.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h       |  2 ++
+ hw/arm/smmu-internal.h       |  5 -----
- target/arm/internals.h |  8 ++++++++
+ include/hw/arm/smmu-common.h |  6 ++++++
- target/arm/syndrome.h  |  5 +++++
+ hw/arm/smmu-common.c         | 21 +++++++++++++++++++++
- target/arm/cpu.c       | 38 +++++++++++++++++++++++++++++++++++++-
+ hw/arm/smmuv3.c              | 19 ++-----------------
- target/arm/helper.c    | 40 +++++++++++++++++++++++++++++++++++++++-
+ hw/arm/trace-events          |  3 ++-
-files changed, 91 insertions(+), 2 deletions(-)
+files changed, 31 insertions(+), 23 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/arm/smmu-internal.h
-+++ b/target/arm/cpu.h
++++ b/hw/arm/smmu-internal.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBPageInvInfo {
- #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
+     uint64_t mask;
- #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
+ } SMMUIOTLBPageInvInfo;
- #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
-+#define EXCP_VSERR          24
+-typedef struct SMMUSIDRange {
- /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
+-    uint32_t start;
+-    uint32_t end;
- #define ARMV7M_EXCP_RESET   1
+-} SMMUSIDRange;
-@@ -XXX,XX +XXX,XX @@ enum {
+-
- #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
+ #endif
- #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
  #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
  /* The usual mapping for an AArch64 system register to its AArch32
   * counterpart is for the 32 bit world to have access to the lower
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/include/hw/arm/smmu-common.h
-+++ b/target/arm/internals.h
++++ b/include/hw/arm/smmu-common.h
-@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
+@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBKey {
-  */
+     uint8_t level;
- void arm_cpu_update_vfiq(ARMCPU *cpu);
+ } SMMUIOTLBKey;
-+/**
++typedef struct SMMUSIDRange {
-+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
++    uint32_t start;
-+ *
++    uint32_t end;
-+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
++} SMMUSIDRange;
 + * following a change to the HCR_EL2.VSE bit.
 + */
 +void arm_cpu_update_vserr(ARMCPU *cpu);
 +
- /**
+ struct SMMUState {
-  * arm_mmu_idx_el:
+     /* <private> */
-  * @env: The cpu environment
+     SysBusDevice  dev;
-diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
+@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
                           uint8_t tg, uint64_t num_pages, uint8_t ttl);
  void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg,
                          uint64_t num_pages, uint8_t ttl);
 +void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range);
  /* Unmap the range of all the notifiers registered to any IOMMU mr */
  void smmu_inv_notifiers_all(SMMUState *s);
 diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/syndrome.h
+--- a/hw/arm/smmu-common.c
-+++ b/target/arm/syndrome.h
++++ b/hw/arm/smmu-common.c
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
+@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_vmid_ipa(gpointer key, gpointer value,
-     return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
+            ((entry->iova & ~info->mask) == info->iova);
  }
-+static inline uint32_t syn_serror(uint32_t extra)
++static gboolean
 +smmu_hash_remove_by_sid_range(gpointer key, gpointer value, gpointer user_data)
 +{
-+    return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
++    SMMUDevice *sdev = (SMMUDevice *)key;
 +    uint32_t sid = smmu_get_sid(sdev);
 +    SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
 +
 +    if (sid < sid_range->start || sid > sid_range->end) {
 +        return false;
 +    }
 +    trace_smmu_config_cache_inv(sid);
 +    return true;
 +}
 +
- #endif /* TARGET_ARM_SYNDROME_H */
++void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
++{
 +    trace_smmu_configs_inv_sid_range(sid_range.start, sid_range.end);
 +    g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_range,
 +                                &sid_range);
 +}
 +
  void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
                           uint8_t tg, uint64_t num_pages, uint8_t ttl)
  {
 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/hw/arm/smmuv3.c
-+++ b/target/arm/cpu.c
++++ b/hw/arm/smmuv3.c
-@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_flush_config(SMMUDevice *sdev)
-     return (cpu->power_state != PSCI_OFF)
+     SMMUv3State *s = sdev->smmu;
-         && cs->interrupt_request &
+     SMMUState *bc = &s->smmu_state;
-         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
--         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
+-    trace_smmuv3_config_cache_inv(smmu_get_sid(sdev));
-+         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
++    trace_smmu_config_cache_inv(smmu_get_sid(sdev));
-          | CPU_INTERRUPT_EXITTB);
+     g_hash_table_remove(bc->configs, sdev);
  }
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage)
              return false;
          }
          return !(env->daif & PSTATE_I);
 +    case EXCP_VSERR:
 +        if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
 +            /* VIRQs are only taken when hypervized.  */
 +            return false;
 +        }
 +        return !(env->daif & PSTATE_A);
      default:
          g_assert_not_reached();
      }
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
              goto found;
          }
      }
 +    if (interrupt_request & CPU_INTERRUPT_VSERR) {
 +        excp_idx = EXCP_VSERR;
 +        target_el = 1;
 +        if (arm_excp_unmasked(cs, excp_idx, target_el,
 +                              cur_el, secure, hcr_el2)) {
 +            /* Taking a virtual abort clears HCR_EL2.VSE */
 +            env->cp15.hcr_el2 &= ~HCR_VSE;
 +            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
 +            goto found;
 +        }
 +    }
      return false;
   found:
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
      }
  }
-+void arm_cpu_update_vserr(ARMCPU *cpu)
+-static gboolean
-+{
+-smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
-+    /*
+-{
-+     * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
+-    SMMUDevice *sdev = (SMMUDevice *)key;
-+     */
+-    uint32_t sid = smmu_get_sid(sdev);
-+    CPUARMState *env = &cpu->env;
+-    SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
-+    CPUState *cs = CPU(cpu);
+-
-+
+-    if (sid < sid_range->start || sid > sid_range->end) {
-+    bool new_state = env->cp15.hcr_el2 & HCR_VSE;
+-        return false;
-+
+-    }
-+    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
+-    trace_smmuv3_config_cache_inv(sid);
-+        if (new_state) {
+-    return true;
-+            cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
+-}
-+        } else {
+-
-+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+ static int smmuv3_cmdq_consume(SMMUv3State *s)
 +        }
 +    }
 +}
 +
  #ifndef CONFIG_USER_ONLY
  static void arm_cpu_set_irq(void *opaque, int irq, int level)
  {
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+     SMMUState *bs = ARM_SMMU(s);
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
              sid_range.end = sid_range.start + mask;
              trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
 -            g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
 -                                        &sid_range);
 +            smmu_configs_inv_sid_range(bs, sid_range);
              break;
          }
          case SMMU_CMD_CFGI_CD:
 diff --git a/hw/arm/trace-events b/hw/arm/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/trace-events
-+++ b/target/arm/helper.c
++++ b/hw/arm/trace-events
-@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=%d vmid=%d"
-         }
+ smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=%d"
-     }
+ smmu_iotlb_inv_vmid_s1(int vmid) "IOTLB invalidate vmid=%d"
+ smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
--    /* External aborts are not possible in QEMU so A bit is always clear */
++smmu_configs_inv_sid_range(uint32_t start, uint32_t end) "Config cache INV SID range from 0x%x to 0x%x"
-+    if (hcr_el2 & HCR_AMO) {
++smmu_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
-+        if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
+ smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
-+            ret |= CPSR_A;
+ smmu_iotlb_lookup_hit(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
-+        }
+ smmu_iotlb_lookup_miss(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
-+    }
+@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_tlbi_nh(int vmid) "vmid=%d"
-+
+ smmuv3_cmdq_tlbi_nsnh(void) ""
-     return ret;
+ smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d"
- }
+ smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d"
+-smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
-@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
+ smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
-     g_assert(qemu_mutex_iothread_locked());
+ smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
-     arm_cpu_update_virq(cpu);
+ smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d"
      arm_cpu_update_vfiq(cpu);
 +    arm_cpu_update_vserr(cpu);
  }
  static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
              [EXCP_LSERR] = "v8M LSERR UsageFault",
              [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
              [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
 +            [EXCP_VSERR] = "Virtual SERR",
          };
          if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
          mask = CPSR_A | CPSR_I | CPSR_F;
          offset = 4;
          break;
 +    case EXCP_VSERR:
 +        {
 +            /*
 +             * Note that this is reported as a data abort, but the DFAR
 +             * has an UNKNOWN value.  Construct the SError syndrome from
 +             * AET and ExT fields.
 +             */
 +            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
 +
 +            if (extended_addresses_enabled(env)) {
 +                env->exception.fsr = arm_fi_to_lfsc(&fi);
 +            } else {
 +                env->exception.fsr = arm_fi_to_sfsc(&fi);
 +            }
 +            env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
 +            A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
 +            qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
 +                          env->exception.fsr);
 +
 +            new_mode = ARM_CPU_MODE_ABT;
 +            addr = 0x10;
 +            mask = CPSR_A | CPSR_I;
 +            offset = 8;
 +        }
 +        break;
      case EXCP_SMC:
          new_mode = ARM_CPU_MODE_MON;
          addr = 0x08;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
      case EXCP_VFIQ:
          addr += 0x100;
          break;
 +    case EXCP_VSERR:
 +        addr += 0x180;
 +        /* Construct the SError syndrome from IDS and ISS fields. */
 +        env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
 +        env->cp15.esr_el[new_el] = env->exception.syndrome;
 +        break;
      default:
          cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
      }
 --
-.25.1
+.43.0

-[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 1 +
- target/arm/cpu_tcg.c          | 1 +
-files changed, 3 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_PMULL (PMULL, PMULL2 instructions)
- - FEAT_PMUv3p1 (PMU Extensions v3.1)
- - FEAT_PMUv3p4 (PMU Extensions v3.4)
-+- FEAT_RAS (Reliability, availability, and serviceability)
- - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
- - FEAT_RNG (Random number generator)
- - FEAT_SB (Speculation Barrier)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     t = cpu->isar.id_aa64pfr0;
-     t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
-     t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
-+    t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1);       /* FEAT_RAS */
-     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
-     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     t = cpu->isar.id_pfr0;
-     t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
-+    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
-     cpu->isar.id_pfr0 = t;
-     t = cpu->isar.id_pfr2;
---
-.25.1

-[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This feature is AArch64 only, and applies to physical SErrors,
-which QEMU does not implement, thus the feature is a nop.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 1 +
-files changed, 2 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
- - FEAT_HPDS (Hierarchical permission disables)
- - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
-+- FEAT_IESB (Implicit error synchronization event)
- - FEAT_JSCVT (JavaScript conversion instructions)
- - FEAT_LOR (Limited ordering regions)
- - FEAT_LPA (Large Physical Address space)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     t = cpu->isar.id_aa64mmfr2;
-     t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
-     t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
-+    t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1);     /* FEAT_IESB */
-     t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
-     t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
-     t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
---
-.25.1

-[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This extension concerns branch speculation, which TCG does
-not implement.  Thus we can trivially enable this feature.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 1 +
- target/arm/cpu_tcg.c          | 1 +
-files changed, 3 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_BBM at level 2 (Translation table break-before-make levels)
- - FEAT_BF16 (AArch64 BFloat16 instructions)
- - FEAT_BTI (Branch Target Identification)
-+- FEAT_CSV2 (Cache speculation variant 2)
- - FEAT_DIT (Data Independent Timing instructions)
- - FEAT_DPB (DC CVAP instruction)
- - FEAT_Debugv8p2 (Debug changes for v8.2)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
-     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
-     cpu->isar.id_aa64pfr0 = t;
-     t = cpu->isar.id_aa64pfr1;
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     cpu->isar.id_mmfr4 = t;
-     t = cpu->isar.id_pfr0;
-+    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CVS2 */
-     t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
-     t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
-     cpu->isar.id_pfr0 = t;
---
-.25.1

-[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This extension concerns cache speculation, which TCG does
-not implement.  Thus we can trivially enable this feature.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 1 +
- target/arm/cpu_tcg.c          | 1 +
-files changed, 3 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
- - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
- - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
-+- FEAT_CSV3 (Cache speculation variant 3)
- - FEAT_DIT (Data Independent Timing instructions)
- - FEAT_DPB (DC CVAP instruction)
- - FEAT_Debugv8p2 (Debug changes for v8.2)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
-     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-     t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
-+    t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1);      /* FEAT_CSV3 */
-     cpu->isar.id_aa64pfr0 = t;
-     t = cpu->isar.id_aa64pfr1;
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     cpu->isar.id_pfr0 = t;
-     t = cpu->isar.id_pfr2;
-+    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
-     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
-     cpu->isar.id_pfr2 = t;
---
-.25.1

-[PULL 27/32] qapi/machine.json: Add cluster-id
+[PULL 20/21] target/rx: Set exception vector base to 0xffffff80
-From: Gavin Shan <gshan@redhat.com>
+From: Keith Packard <keithp@keithp.com>
-This adds cluster-id in CPU instance properties, which will be used
+The documentation says the vector is at 0xffffff80, instead of the
-by arm/virt machine. Besides, the cluster-id is also verified or
+previous value of 0xffffffc0. That value must have been a bug because
-dumped in various spots:
+the standard vector values (20, 21, 23, 25, 30) were all
 past the end of the array.
-  * hw/core/machine.c::machine_set_cpu_numa_node() to associate
+Signed-off-by: Keith Packard <keithp@keithp.com>
-    CPU with its NUMA node.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
   * hw/core/machine.c::machine_numa_finish_cpu_init() to record
     CPU slots with no NUMA mapping set.
   * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
     cluster-id.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Acked-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20220503140304.855514-2-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- qapi/machine.json          |  6 ++++--
+ target/rx/helper.c | 2 +-
- hw/core/machine-hmp-cmds.c |  4 ++++
+file changed, 1 insertion(+), 1 deletion(-)
  hw/core/machine.c          | 16 ++++++++++++++++
 files changed, 24 insertions(+), 2 deletions(-)
-diff --git a/qapi/machine.json b/qapi/machine.json
+diff --git a/target/rx/helper.c b/target/rx/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/qapi/machine.json
+--- a/target/rx/helper.c
-+++ b/qapi/machine.json
++++ b/target/rx/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void rx_cpu_do_interrupt(CPUState *cs)
- # @node-id: NUMA node ID the CPU belongs to
+         cpu_stl_data(env, env->isp, env->pc);
- # @socket-id: socket number within node/board the CPU belongs to
- # @die-id: die number within socket the CPU belongs to (since 4.1)
+         if (vec < 0x100) {
--# @core-id: core number within die the CPU belongs to
+-            env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4);
-+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
++            env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4);
-+# @core-id: core number within cluster the CPU belongs to
+         } else {
- # @thread-id: thread number within core the CPU belongs to
+             env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4);
  #
 -# Note: currently there are 5 properties that could be present
 +# Note: currently there are 6 properties that could be present
  #       but management should be prepared to pass through other
  #       properties with device_add command to allow for future
  #       interface extension. This also requires the filed names to be kept in
@@ -XXX,XX +XXX,XX @@
    'data': { '*node-id': 'int',
              '*socket-id': 'int',
              '*die-id': 'int',
 +            '*cluster-id': 'int',
              '*core-id': 'int',
              '*thread-id': 'int'
    }
 diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/machine-hmp-cmds.c
 +++ b/hw/core/machine-hmp-cmds.c
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
          if (c->has_die_id) {
              monitor_printf(mon, "    die-id: \"%" PRIu64 "\"\n", c->die_id);
          }
-+        if (c->has_cluster_id) {
-+            monitor_printf(mon, "    cluster-id: \"%" PRIu64 "\"\n",
-+                           c->cluster_id);
-+        }
-         if (c->has_core_id) {
-             monitor_printf(mon, "    core-id: \"%" PRIu64 "\"\n", c->core_id);
-         }
-diff --git a/hw/core/machine.c b/hw/core/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/core/machine.c
-+++ b/hw/core/machine.c
-@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
-             return;
-         }
-+        if (props->has_cluster_id && !slot->props.has_cluster_id) {
-+            error_setg(errp, "cluster-id is not supported");
-+            return;
-+        }
-+
-         if (props->has_socket_id && !slot->props.has_socket_id) {
-             error_setg(errp, "socket-id is not supported");
-             return;
-@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
-                 continue;
-         }
-+        if (props->has_cluster_id &&
-+            props->cluster_id != slot->props.cluster_id) {
-+                continue;
-+        }
-+
-         if (props->has_die_id && props->die_id != slot->props.die_id) {
-                 continue;
-         }
-@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
-         }
-         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
-     }
-+    if (cpu->props.has_cluster_id) {
-+        if (s->len) {
-+            g_string_append_printf(s, ", ");
-+        }
-+        g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
-+    }
-     if (cpu->props.has_core_id) {
-         if (s->len) {
-             g_string_append_printf(s, ", ");
 --
-.25.1
+.43.0

-[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
+[PULL 21/21] target/rx: Remove TCG_CALL_NO_WG from helpers which write env
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Keith Packard <keithp@keithp.com>
-This extension concerns not merging memory access, which TCG does
+Functions which modify TCG globals must not be marked TCG_CALL_NO_WG,
-not implement.  Thus we can trivially enable this feature.
+as that tells the optimizer that TCG global values already loaded in
-Add a comment to handle_hint for the DGH instruction, but no code.
+machine registers are still valid, and so any changes which these
 helpers make to the CPU state may be ignored.
+The target/rx code chooses to put (among other things) all the PSW
+bits and also ACC into globals, so the NO_WG flag on various
+functions that touch the PSW or ACC is incorrect and must be removed.
+This includes all the floating point helper functions, because
+update_fpsw() will update PSW Z and S.
+Signed-off-by: Keith Packard <keithp@keithp.com>
+[PMM: Clarified commit message]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/emulation.rst | 1 +
+ target/rx/helper.h | 34 +++++++++++++++++-----------------
- target/arm/cpu64.c            | 1 +
+file changed, 17 insertions(+), 17 deletions(-)
  target/arm/translate-a64.c    | 1 +
 files changed, 3 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/target/rx/helper.h b/target/rx/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/target/rx/helper.h
-+++ b/docs/system/arm/emulation.rst
++++ b/target/rx/helper.h
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_privilege_violation, noreturn, env)
- - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+ DEF_HELPER_1(wait, noreturn, env)
- - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
+ DEF_HELPER_2(rxint, noreturn, env, i32)
- - FEAT_CSV3 (Cache speculation variant 3)
+ DEF_HELPER_1(rxbrk, noreturn, env)
-+- FEAT_DGH (Data gathering hint)
+-DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
- - FEAT_DIT (Data Independent Timing instructions)
+-DEF_HELPER_FLAGS_3(fsub, TCG_CALL_NO_WG, f32, env, f32, f32)
- - FEAT_DPB (DC CVAP instruction)
+-DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, f32, env, f32, f32)
- - FEAT_Debugv8p2 (Debug changes for v8.2)
+-DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+-DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_WG, void, env, f32, f32)
-index XXXXXXX..XXXXXXX 100644
+-DEF_HELPER_FLAGS_2(ftoi, TCG_CALL_NO_WG, i32, env, f32)
---- a/target/arm/cpu64.c
+-DEF_HELPER_FLAGS_2(round, TCG_CALL_NO_WG, i32, env, f32)
-+++ b/target/arm/cpu64.c
+-DEF_HELPER_FLAGS_2(itof, TCG_CALL_NO_WG, f32, env, i32)
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
++DEF_HELPER_3(fadd, f32, env, f32, f32)
-     t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
++DEF_HELPER_3(fsub, f32, env, f32, f32)
-     t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
++DEF_HELPER_3(fmul, f32, env, f32, f32)
-     t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
++DEF_HELPER_3(fdiv, f32, env, f32, f32)
-+    t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1);      /* FEAT_DGH */
++DEF_HELPER_3(fcmp, void, env, f32, f32)
-     t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
++DEF_HELPER_2(ftoi, i32, env, f32)
-     cpu->isar.id_aa64isar1 = t;
++DEF_HELPER_2(round, i32, env, f32)
++DEF_HELPER_2(itof, f32, env, i32)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+ DEF_HELPER_2(set_fpsw, void, env, i32)
-index XXXXXXX..XXXXXXX 100644
+-DEF_HELPER_FLAGS_2(racw, TCG_CALL_NO_WG, void, env, i32)
---- a/target/arm/translate-a64.c
+-DEF_HELPER_FLAGS_2(set_psw_rte, TCG_CALL_NO_WG, void, env, i32)
-+++ b/target/arm/translate-a64.c
+-DEF_HELPER_FLAGS_2(set_psw, TCG_CALL_NO_WG, void, env, i32)
-@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
++DEF_HELPER_2(racw, void, env, i32)
-         break;
++DEF_HELPER_2(set_psw_rte, void, env, i32)
-     case 0b00100: /* SEV */
++DEF_HELPER_2(set_psw, void, env, i32)
-     case 0b00101: /* SEVL */
+ DEF_HELPER_1(pack_psw, i32, env)
-+    case 0b00110: /* DGH */
+-DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32)
-         /* we treat all as NOP at least for now */
+-DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
-         break;
+-DEF_HELPER_FLAGS_1(scmpu, TCG_CALL_NO_WG, void, env)
-     case 0b00111: /* XPACLRI */
++DEF_HELPER_3(div, i32, env, i32, i32)
 +DEF_HELPER_3(divu, i32, env, i32, i32)
 +DEF_HELPER_1(scmpu, void, env)
  DEF_HELPER_1(smovu, void, env)
  DEF_HELPER_1(smovf, void, env)
  DEF_HELPER_1(smovb, void, env)
  DEF_HELPER_2(sstr, void, env, i32)
 -DEF_HELPER_FLAGS_2(swhile, TCG_CALL_NO_WG, void, env, i32)
 -DEF_HELPER_FLAGS_2(suntil, TCG_CALL_NO_WG, void, env, i32)
 -DEF_HELPER_FLAGS_2(rmpa, TCG_CALL_NO_WG, void, env, i32)
 +DEF_HELPER_2(swhile, void, env, i32)
 +DEF_HELPER_2(suntil, void, env, i32)
 +DEF_HELPER_2(rmpa, void, env, i32)
  DEF_HELPER_1(satr, void, env)
 --
-.25.1
+.43.0

target-arm queue: the big stuff here is the final part of
rth's patches for Cortex-A76 and Neoverse-N1 support;
also present are Gavin's NUMA series and a few other things.

thanks
-- PMM

The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:

Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509

for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:

hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)

----------------------------------------------------------------
target-arm queue:
 * MAINTAINERS/.mailmap: update email for Leif Lindholm
 * hw/arm: add version information to sbsa-ref machine DT
 * Enable new features for -cpu max:
   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
   FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
 * Emulate Cortex-A76
 * Emulate Neoverse-N1
 * Fix the virt board default NUMA topology

----------------------------------------------------------------
Gavin Shan (6):
      qapi/machine.json: Add cluster-id
      qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
      hw/arm/virt: Consider SMP configuration in CPU topology
      qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
      hw/arm/virt: Fix CPU's default NUMA node ID
      hw/acpi/aml-build: Use existing CPU topology to build PPTT table

Leif Lindholm (2):
      MAINTAINERS/.mailmap: update email for Leif Lindholm
      hw/arm: add versioning to sbsa-ref machine DT

Richard Henderson (24):
      target/arm: Handle cpreg registration for missing EL
      target/arm: Drop EL3 no EL2 fallbacks
      target/arm: Merge zcr reginfo
      target/arm: Adjust definition of CONTEXTIDR_EL2
      target/arm: Move cortex impdef sysregs to cpu_tcg.c
      target/arm: Update qemu-system-arm -cpu max to cortex-a57
      target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
      target/arm: Split out aa32_max_features
      target/arm: Annotate arm_max_initfn with FEAT identifiers
      target/arm: Use field names for manipulating EL2 and EL3 modes
      target/arm: Enable FEAT_Debugv8p2 for -cpu max
      target/arm: Enable FEAT_Debugv8p4 for -cpu max
      target/arm: Add minimal RAS registers
      target/arm: Enable SCR and HCR bits for RAS
      target/arm: Implement virtual SError exceptions
      target/arm: Implement ESB instruction
      target/arm: Enable FEAT_RAS for -cpu max
      target/arm: Enable FEAT_IESB for -cpu max
      target/arm: Enable FEAT_CSV2 for -cpu max
      target/arm: Enable FEAT_CSV2_2 for -cpu max
      target/arm: Enable FEAT_CSV3 for -cpu max
      target/arm: Enable FEAT_DGH for -cpu max
      target/arm: Define cortex-a76
      target/arm: Define neoverse-n1

From: Leif Lindholm <quic_llindhol@quicinc.com>

NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innovation Center (quicinc), so update
my email address to reflect this.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[Fixed commit message typo]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 .mailmap    | 3 ++-
 MAINTAINERS | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.mailmap b/.mailmap
index XXXXXXX..XXXXXXX 100644
--- a/.mailmap
+++ b/.mailmap
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
 James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
 Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
 Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
 Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
 SBSA-REF
 M: Radoslaw Biernacki <rad@semihalf.com>
 M: Peter Maydell <peter.maydell@linaro.org>
-R: Leif Lindholm <leif@nuviainc.com>
+R: Leif Lindholm <quic_llindhol@quicinc.com>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/sbsa-ref.c
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.

Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.

This will simplify cpreg registration for conditional arm features.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h |  11 +++
 target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
 2 files changed, 133 insertions(+), 56 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SVE                   = 1 << 14,
     /* Flag: Do not expose in gdb sysreg xml. */
     ARM_CP_NO_GDB                = 1 << 15,
+    /*
+     * Flags: If EL3 but not EL2...
+     *   - UNDEF: discard the cpreg,
+     *   -  KEEP: retain the cpreg as is,
+     *   -  C_NZ: set const on the cpreg, but retain resetvalue,
+     *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
+     * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+     */
+    ARM_CP_EL3_NO_EL2_UNDEF      = 1 << 16,
+    ARM_CP_EL3_NO_EL2_KEEP       = 1 << 17,
+    ARM_CP_EL3_NO_EL2_C_NZ       = 1 << 18,
 };
 
 /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
+      .access = PL2_RW,
+      .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
       .writefn = dacr_write, .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
       .type = ARM_CP_ALIAS,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .writefn = tlbimva_hyp_is_write },
     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2_write },
     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2_write },
     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2_write },
     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2is_write },
     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
 #ifndef CONFIG_USER_ONLY
     /* Unlike the other EL2-related AT operations, these must
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
       .access = PL2_W, .accessfn = at_s1e2_access,
-      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn = ats_write64 },
     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
       .access = PL2_W, .accessfn = at_s1e2_access,
-      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn = ats_write64 },
     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .accessfn = access_tda,
-      .type = ARM_CP_NOP },
+      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
     /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
      * Channel but Linux may try to access this register. The 32-bit
      * alias is DBGDCCINT.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
    { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NOP },
    { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
    { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2_write },
    { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2_write },
    { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2is_write },
     { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
    { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .writefn = tlbi_aa64_alle1is_write },
     { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL2_RW, .accessfn = access_el3_aa32ns,
-              .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
+              .resetvalue = cpu->midr,
+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL2_RW, .resetvalue = cpu->midr,
+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
               .access = PL2_RW, .accessfn = access_el3_aa32ns,
-              .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
+              .resetvalue = vmpidr_def,
+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-              .access = PL2_RW,
-              .resetvalue = vmpidr_def,
+              .access = PL2_RW, .resetvalue = vmpidr_def,
+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
         };
         define_arm_cp_regs(cpu, vpidr_regs);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
+    CPUARMState *env = &cpu->env;
     uint32_t key;
     ARMCPRegInfo *r2;
     bool is64 = r->type & ARM_CP_64BIT;
     bool ns = secstate & ARM_CP_SECSTATE_NS;
     int cp = r->cp;
-    bool isbanked;
     size_t name_len;
+    bool make_const;
 
     switch (state) {
     case ARM_CP_STATE_AA32:
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
     }
 
+    /*
+     * Eliminate registers that are not present because the EL is missing.
+     * Doing this here makes it easier to put all registers for a given
+     * feature into the same ARMCPRegInfo array and define them all at once.
+     */
+    make_const = false;
+    if (arm_feature(env, ARM_FEATURE_EL3)) {
+        /*
+         * An EL2 register without EL2 but with EL3 is (usually) RES0.
+         * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+         */
+        int min_el = ctz32(r->access) / 2;
+        if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
+            if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
+                return;
+            }
+            make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
+        }
+    } else {
+        CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
+                                 ? PL2_RW : PL1_RW);
+        if ((r->access & max_el) == 0) {
+            return;
+        }
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         r2->opaque = opaque;
     }
 
-    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
-    if (isbanked) {
+    if (make_const) {
+        /* This should not have been a very special register to begin. */
+        int old_special = r2->type & ARM_CP_SPECIAL_MASK;
+        assert(old_special == 0 || old_special == ARM_CP_NOP);
         /*
-         * Register is banked (using both entries in array).
-         * Overwriting fieldoffset as the array is only used to define
-         * banked registers but later only fieldoffset is used.
+         * Set the special function to CONST, retaining the other flags.
+         * This is important for e.g. ARM_CP_SVE so that we still
+         * take the SVE trap if CPTR_EL3.EZ == 0.
          */
-        r2->fieldoffset = r->bank_fieldoffsets[ns];
-    }
+        r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
+        /*
+         * Usually, these registers become RES0, but there are a few
+         * special cases like VPIDR_EL2 which have a constant non-zero
+         * value with writes ignored.
+         */
+        if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
+            r2->resetvalue = 0;
+        }
+        /*
+         * ARM_CP_CONST has precedence, so removing the callbacks and
+         * offsets are not strictly necessary, but it is potentially
+         * less confusing to debug later.
+         */
+        r2->readfn = NULL;
+        r2->writefn = NULL;
+        r2->raw_readfn = NULL;
+        r2->raw_writefn = NULL;
+        r2->resetfn = NULL;
+        r2->fieldoffset = 0;
+        r2->bank_fieldoffsets[0] = 0;
+        r2->bank_fieldoffsets[1] = 0;
+    } else {
+        bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 
-    if (state == ARM_CP_STATE_AA32) {
         if (isbanked) {
             /*
-             * If the register is banked then we don't need to migrate or
-             * reset the 32-bit instance in certain cases:
-             *
-             * 1) If the register has both 32-bit and 64-bit instances then we
-             *    can count on the 64-bit instance taking care of the
-             *    non-secure bank.
-             * 2) If ARMv8 is enabled then we can count on a 64-bit version
-             *    taking care of the secure bank.  This requires that separate
-             *    32 and 64-bit definitions are provided.
+             * Register is banked (using both entries in array).
+             * Overwriting fieldoffset as the array is only used to define
+             * banked registers but later only fieldoffset is used.
              */
-            if ((r->state == ARM_CP_STATE_BOTH && ns) ||
-                (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
+            r2->fieldoffset = r->bank_fieldoffsets[ns];
+        }
+        if (state == ARM_CP_STATE_AA32) {
+            if (isbanked) {
+                /*
+                 * If the register is banked then we don't need to migrate or
+                 * reset the 32-bit instance in certain cases:
+                 *
+                 * 1) If the register has both 32-bit and 64-bit instances
+                 *    then we can count on the 64-bit instance taking care
+                 *    of the non-secure bank.
+                 * 2) If ARMv8 is enabled then we can count on a 64-bit
+                 *    version taking care of the secure bank.  This requires
+                 *    that separate 32 and 64-bit definitions are provided.
+                 */
+                if ((r->state == ARM_CP_STATE_BOTH && ns) ||
+                    (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
+                    r2->type |= ARM_CP_ALIAS;
+                }
+            } else if ((secstate != r->secure) && !ns) {
+                /*
+                 * The register is not banked so we only want to allow
+                 * migration of the non-secure instance.
+                 */
                 r2->type |= ARM_CP_ALIAS;
             }
-        } else if ((secstate != r->secure) && !ns) {
-            /*
-             * The register is not banked so we only want to allow migration
-             * of the non-secure instance.
-             */
-            r2->type |= ARM_CP_ALIAS;
-        }
 
-        if (HOST_BIG_ENDIAN &&
-            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
-            r2->fieldoffset += sizeof(uint32_t);
+            if (HOST_BIG_ENDIAN &&
+                r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
+                r2->fieldoffset += sizeof(uint32_t);
+            }
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * multiple times. Special registers (ie NOP/WFI) are
      * never migratable and not even raw-accessible.
      */
-    if (r->type & ARM_CP_SPECIAL_MASK) {
+    if (r2->type & ARM_CP_SPECIAL_MASK) {
         r2->type |= ARM_CP_NO_RAW;
     }
     if (((r->crm == CP_ANY) && crm != 0) ||
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.

This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that the virtualization cpregs
are now correctly not present.  This would be a migration compatibility
break, except that we have an existing bug in which migration of 32-bit
cpus with Security Extensions enabled does not work.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 158 ++++----------------------------------------
 1 file changed, 13 insertions(+), 145 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
 };
 
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
-    { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
-      .access = PL2_RW,
-      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
-    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 6, .crm = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
-      .access = PL2_RW, .accessfn = access_tda,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
-      .type = ARM_CP_CONST,
-      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .resetvalue = 0 },
-};
-
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
-    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-};
-
 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, v8_idregs);
         define_arm_cp_regs(cpu, v8_cp_reginfo);
     }
-    if (arm_feature(env, ARM_FEATURE_EL2)) {
+
+    /*
+     * Register the base EL2 cpregs.
+     * Pre v8, these registers are implemented only as part of the
+     * Virtualization Extensions (EL2 present).  Beginning with v8,
+     * if EL2 is missing but EL3 is enabled, mostly these become
+     * RES0 from EL3, with some specific exceptions.
+     */
+    if (arm_feature(env, ARM_FEATURE_EL2)
+        || (arm_feature(env, ARM_FEATURE_EL3)
+            && arm_feature(env, ARM_FEATURE_V8))) {
         uint64_t vmpidr_def = mpidr_read_val(env);
         ARMCPRegInfo vpidr_regs[] = {
             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             };
             define_one_arm_cp_reg(cpu, &rvbar);
         }
-    } else {
-        /* If EL2 is missing but higher ELs are enabled, we need to
-         * register the no_el2 reginfos.
-         */
-        if (arm_feature(env, ARM_FEATURE_EL3)) {
-            /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
-             * of MIDR_EL1 and MPIDR_EL1.
-             */
-            ARMCPRegInfo vpidr_regs[] = {
-                { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
-                  .type = ARM_CP_CONST, .resetvalue = cpu->midr,
-                  .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
-                { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
-                  .type = ARM_CP_NO_RAW,
-                  .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
-            };
-            define_arm_cp_regs(cpu, vpidr_regs);
-            define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
-            if (arm_feature(env, ARM_FEATURE_V8)) {
-                define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
-            }
-        }
     }
+
+    /* Register the base EL3 cpregs. */
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         define_arm_cp_regs(cpu, el3_cp_reginfo);
         ARMCPRegInfo el3_regs[] = {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 55 ++++++++++++++-------------------------------
 1 file changed, 17 insertions(+), 38 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 }
 
-static const ARMCPRegInfo zcr_el1_reginfo = {
-    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL1_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
-    .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_el2_reginfo = {
-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL2_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
-    .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL2_RW, .type = ARM_CP_SVE,
-    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
-};
-
-static const ARMCPRegInfo zcr_el3_reginfo = {
-    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL3_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
-    .writefn = zcr_write, .raw_writefn = raw_write
+static const ARMCPRegInfo zcr_reginfo[] = {
+    { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
+    { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
+    { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL3_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
 };
 
 void hw_watchpoint_update(ARMCPU *cpu, int n)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (cpu_isar_feature(aa64_sve, cpu)) {
-        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
-        if (arm_feature(env, ARM_FEATURE_EL2)) {
-            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
-        } else {
-            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
-        }
-        if (arm_feature(env, ARM_FEATURE_EL3)) {
-            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
-        }
+        define_arm_cp_regs(cpu, zcr_reginfo);
     }
 
 #ifdef TARGET_AARCH64
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This register is present for either VHE or Debugv8p2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 };
 
+static const ARMCPRegInfo contextidr_el2 = {
+    .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+    .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+    .access = PL2_RW,
+    .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
 static const ARMCPRegInfo vhe_reginfo[] = {
-    { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
-      .access = PL2_RW,
-      .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
     }
 
+    if (cpu_isar_feature(aa64_vh, cpu) ||
+        cpu_isar_feature(aa64_debugv8p2, cpu)) {
+        define_one_arm_cp_reg(cpu, &contextidr_el2);
+    }
     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
         define_arm_cp_regs(cpu, vhe_reginfo);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.

This will shortly be used from cpu_tcg.c also.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h |  6 ++++
 target/arm/cpu64.c     | 64 +++---------------------------------------
 target/arm/cpu_tcg.c   | 59 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+), 60 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
 #endif
 
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "hvf_arm.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
-#include "cpregs.h"
+#include "internals.h"
 
 
-#ifndef CONFIG_USER_ONLY
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
-    ARMCPU *cpu = env_archcpu(env);
-
-    /* Number of cores is in [25:24]; otherwise we RAZ */
-    return (cpu->core_count - 1) << 24;
-}
-#endif
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
-#ifndef CONFIG_USER_ONLY
-    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
-    { .name = "L2CTLR",
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
-#endif
-    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2ECTLR",
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUACTLR",
-      .cp = 15, .opc1 = 0, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUECTLR",
-      .cp = 15, .opc1 = 1, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUMERRSR",
-      .cp = 15, .opc1 = 2, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2MERRSR",
-      .cp = 15, .opc1 = 3, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-};
-
 static void aarch64_a57_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 static void aarch64_a53_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 static void aarch64_a72_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #endif
 #include "cpregs.h"
 
+#ifndef CONFIG_USER_ONLY
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    /* Number of cores is in [25:24]; otherwise we RAZ */
+    return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+      .access = PL1_RW, .readfn = l2ctlr_read,
+      .writefn = arm_cp_write_ignore },
+    { .name = "L2CTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+      .access = PL1_RW, .readfn = l2ctlr_read,
+      .writefn = arm_cp_write_ignore },
+    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2ECTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUACTLR",
+      .cp = 15, .opc1 = 0, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUECTLR",
+      .cp = 15, .opc1 = 1, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUMERRSR",
+      .cp = 15, .opc1 = 2, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2MERRSR",
+      .cp = 15, .opc1 = 3, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
+#endif /* !CONFIG_USER_ONLY */
+
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
 1 file changed, 92 insertions(+), 59 deletions(-)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t t;
 
-    cortex_a15_initfn(obj);
+    /* aarch64_a57_initfn, advertising none of the aarch64 features */
+    cpu->dtb_compatible = "arm,cortex-a57";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x411fd070;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0;
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
-    /* old-style VFP short-vector support */
-    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+    /* Add additional features supported by QEMU */
+    t = cpu->isar.id_isar5;
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    cpu->isar.id_isar5 = t;
+
+    t = cpu->isar.id_isar6;
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    cpu->isar.id_isar6 = t;
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    t = cpu->isar.id_mmfr3;
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    cpu->isar.id_mmfr3 = t;
+
+    t = cpu->isar.id_mmfr4;
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    cpu->isar.id_mmfr4 = t;
+
+    t = cpu->isar.id_pfr0;
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    cpu->isar.id_pfr0 = t;
+
+    t = cpu->isar.id_pfr2;
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    cpu->isar.id_pfr2 = t;
 
 #ifdef CONFIG_USER_ONLY
     /*
-     * We don't set these in system emulation mode for the moment,
-     * since we don't correctly set (all of) the ID registers to
-     * advertise them.
+     * Break with true ARMv8 and add back old-style VFP short-vector support.
+     * Only do this for user-mode, where -cpu max is the default, so that
+     * older v6 and v7 programs are more likely to work without adjustment.
      */
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    {
-        uint32_t t;
-
-        t = cpu->isar.id_isar5;
-        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-        cpu->isar.id_isar5 = t;
-
-        t = cpu->isar.id_isar6;
-        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-        t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-        t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-        cpu->isar.id_isar6 = t;
-
-        t = cpu->isar.mvfr1;
-        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-        cpu->isar.mvfr1 = t;
-
-        t = cpu->isar.mvfr2;
-        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-        cpu->isar.mvfr2 = t;
-
-        t = cpu->isar.id_mmfr3;
-        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-        cpu->isar.id_mmfr3 = t;
-
-        t = cpu->isar.id_mmfr4;
-        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-        cpu->isar.id_mmfr4 = t;
-
-        t = cpu->isar.id_pfr0;
-        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-        cpu->isar.id_pfr0 = t;
-
-        t = cpu->isar.id_pfr2;
-        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-        cpu->isar.id_pfr2 = t;
-    }
-#endif /* CONFIG_USER_ONLY */
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+#endif
 }
 #endif /* !TARGET_AARCH64 */
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.

Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
     cpu->isar.id_pfr2 = t;
 
+    t = cpu->isar.id_dfr0;
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    cpu->isar.id_dfr0 = t;
+
 #ifdef CONFIG_USER_ONLY
     /*
      * Break with true ARMv8 and add back old-style VFP short-vector support.
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h |   2 +
 target/arm/cpu64.c     |  50 +-----------------
 target/arm/cpu_tcg.c   | 114 ++++++++++++++++++++++-------------------
 3 files changed, 65 insertions(+), 101 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+void aa32_max_features(ARMCPU *cpu);
+
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     uint64_t t;
-    uint32_t u;
 
     if (kvm_enabled() || hvf_enabled()) {
         /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
     cpu->isar.id_aa64zfr0 = t;
 
-    /* Replicate the same data to the 32-bit id registers.  */
-    u = cpu->isar.id_isar5;
-    u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
-    u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
-    u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
-    u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
-    u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
-    u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
-    cpu->isar.id_isar5 = u;
-
-    u = cpu->isar.id_isar6;
-    u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
-    u = FIELD_DP32(u, ID_ISAR6, DP, 1);
-    u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
-    u = FIELD_DP32(u, ID_ISAR6, SB, 1);
-    u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
-    u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
-    u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
-    cpu->isar.id_isar6 = u;
-
-    u = cpu->isar.id_pfr0;
-    u = FIELD_DP32(u, ID_PFR0, DIT, 1);
-    cpu->isar.id_pfr0 = u;
-
-    u = cpu->isar.id_pfr2;
-    u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
-    cpu->isar.id_pfr2 = u;
-
-    u = cpu->isar.id_mmfr3;
-    u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
-    cpu->isar.id_mmfr3 = u;
-
-    u = cpu->isar.id_mmfr4;
-    u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
-    u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
-    cpu->isar.id_mmfr4 = u;
-
     t = cpu->isar.id_aa64dfr0;
     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
     cpu->isar.id_aa64dfr0 = t;
 
-    u = cpu->isar.id_dfr0;
-    u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-    cpu->isar.id_dfr0 = u;
-
-    u = cpu->isar.mvfr1;
-    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
-    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
-    cpu->isar.mvfr1 = u;
+    /* Replicate the same data to the 32-bit id registers.  */
+    aa32_max_features(cpu);
 
 #ifdef CONFIG_USER_ONLY
     /*
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #endif
 #include "cpregs.h"
 
+
+/* Share AArch32 -cpu max features with AArch64. */
+void aa32_max_features(ARMCPU *cpu)
+{
+    uint32_t t;
+
+    /* Add additional features supported by QEMU */
+    t = cpu->isar.id_isar5;
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    cpu->isar.id_isar5 = t;
+
+    t = cpu->isar.id_isar6;
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    cpu->isar.id_isar6 = t;
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    t = cpu->isar.id_mmfr3;
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    cpu->isar.id_mmfr3 = t;
+
+    t = cpu->isar.id_mmfr4;
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    cpu->isar.id_mmfr4 = t;
+
+    t = cpu->isar.id_pfr0;
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    cpu->isar.id_pfr0 = t;
+
+    t = cpu->isar.id_pfr2;
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    cpu->isar.id_pfr2 = t;
+
+    t = cpu->isar.id_dfr0;
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    cpu->isar.id_dfr0 = t;
+}
+
 #ifndef CONFIG_USER_ONLY
 static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    uint32_t t;
 
     /* aarch64_a57_initfn, advertising none of the aarch64 features */
     cpu->dtb_compatible = "arm,cortex-a57";
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
-    /* Add additional features supported by QEMU */
-    t = cpu->isar.id_isar5;
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-    cpu->isar.id_isar5 = t;
-
-    t = cpu->isar.id_isar6;
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-    cpu->isar.id_isar6 = t;
-
-    t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-    cpu->isar.mvfr1 = t;
-
-    t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-    cpu->isar.mvfr2 = t;
-
-    t = cpu->isar.id_mmfr3;
-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-    cpu->isar.id_mmfr3 = t;
-
-    t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-    cpu->isar.id_mmfr4 = t;
-
-    t = cpu->isar.id_pfr0;
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-    cpu->isar.id_pfr0 = t;
-
-    t = cpu->isar.id_pfr2;
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-    cpu->isar.id_pfr2 = t;
-
-    t = cpu->isar.id_dfr0;
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-    cpu->isar.id_dfr0 = t;
+    aa32_max_features(cpu);
 
 #ifdef CONFIG_USER_ONLY
     /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu64.c   | 100 +++++++++++++++++++++----------------------
 target/arm/cpu_tcg.c |  48 ++++++++++-----------
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     cpu->midr = t;
 
     t = cpu->isar.id_aa64isar0;
-    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
     t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
-    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
-    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
-    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
+    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
+    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
+    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
+    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
     cpu->isar.id_aa64isar0 = t;
 
     t = cpu->isar.id_aa64isar1;
-    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
-    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
-    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
+    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
+    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
+    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
+    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
+    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
     cpu->isar.id_aa64isar1 = t;
 
     t = cpu->isar.id_aa64pfr0;
+    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
+    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
+    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
     cpu->isar.id_aa64pfr0 = t;
 
     t = cpu->isar.id_aa64pfr1;
-    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
-    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
+    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
+    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
     /*
      * Begin with full support for MTE. This will be downgraded to MTE=0
      * during realize if the board provides no tag memory, much like
      * we do for EL2 with the virtualization=on property.
      */
-    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
+    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
     cpu->isar.id_aa64pfr1 = t;
 
     t = cpu->isar.id_aa64mmfr0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     cpu->isar.id_aa64mmfr0 = t;
 
     t = cpu->isar.id_aa64mmfr1;
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
-    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
-    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
-    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
+    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
+    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
     cpu->isar.id_aa64mmfr1 = t;
 
     t = cpu->isar.id_aa64mmfr2;
-    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
-    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
-    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
-    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
-    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
+    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
+    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
+    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
+    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
+    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
+    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
     cpu->isar.id_aa64mmfr2 = t;
 
     t = cpu->isar.id_aa64zfr0;
     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
-    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
+    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
+    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
+    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
+    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
     cpu->isar.id_aa64zfr0 = t;
 
     t = cpu->isar.id_aa64dfr0;
-    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
     cpu->isar.id_aa64dfr0 = t;
 
     /* Replicate the same data to the 32-bit id registers.  */
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
 
     /* Add additional features supported by QEMU */
     t = cpu->isar.id_isar5;
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
     t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
     cpu->isar.id_isar5 = t;
 
     t = cpu->isar.id_isar6;
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
     cpu->isar.id_isar6 = t;
 
     t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
     cpu->isar.mvfr1 = t;
 
     t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
     cpu->isar.mvfr2 = t;
 
     t = cpu->isar.id_mmfr3;
-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
     cpu->isar.id_mmfr4 = t;
 
     t = cpu->isar.id_pfr0;
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
     cpu->isar.id_pfr0 = t;
 
     t = cpu->isar.id_pfr2;
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
     cpu->isar.id_pfr2 = t;
 
     t = cpu->isar.id_dfr0;
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
     cpu->isar.id_dfr0 = t;
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          */
         unset_feature(env, ARM_FEATURE_EL3);
 
-        /* Disable the security extension feature bits in the processor feature
-         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
+        /*
+         * Disable the security extension feature bits in the processor
+         * feature registers as well.
          */
-        cpu->isar.id_pfr1 &= ~0xf0;
-        cpu->isar.id_aa64pfr0 &= ~0xf000;
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL3, 0);
     }
 
     if (!cpu->has_el2) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
-        /* Disable the hypervisor feature bits in the processor feature
-         * registers if we don't have EL2. These are id_pfr1[15:12] and
-         * id_aa64pfr0_el1[11:8].
+        /*
+         * Disable the hypervisor feature bits in the processor feature
+         * registers if we don't have EL2.
          */
-        cpu->isar.id_aa64pfr0 &= ~0xf00;
-        cpu->isar.id_pfr1 &= ~0xf000;
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL2, 0);
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
+                                       ID_PFR1, VIRTUALIZATION, 0);
     }
 
 #ifndef CONFIG_USER_ONLY
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE.  The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu.c              | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 2 ++
 4 files changed, 5 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU.  Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 2 +-
 target/arm/cpu_tcg.c          | 4 ++--
 3 files changed, 4 insertions(+), 3 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Add only the system registers required to implement zero error
records.  This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.

Add the EL2 registers required for injecting virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  5 +++
 target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
         uint64_t gcr_el1;
         uint64_t rgsr_el1;
+
+        /* Minimal RAS registers */
+        uint64_t disr_el1;
+        uint64_t vdisr_el2;
+        uint64_t vsesr_el2;
     } cp15;
 
     struct {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 };
 
+/*
+ * Check for traps to RAS registers, which are controlled
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
+ */
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+        return env->cp15.vdisr_el2;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+        return 0; /* RAZ/WI */
+    }
+    return env->cp15.disr_el1;
+}
+
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+        env->cp15.vdisr_el2 = val;
+        return;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+        return; /* RAZ/WI */
+    }
+    env->cp15.disr_el1 = val;
+}
+
+/*
+ * Minimal RAS implementation with no Error Records.
+ * Which means that all of the Error Record registers:
+ *   ERXADDR_EL1
+ *   ERXCTLR_EL1
+ *   ERXFR_EL1
+ *   ERXMISC0_EL1
+ *   ERXMISC1_EL1
+ *   ERXMISC2_EL1
+ *   ERXMISC3_EL1
+ *   ERXPFGCDN_EL1  (RASv1p1)
+ *   ERXPFGCTL_EL1  (RASv1p1)
+ *   ERXPFGF_EL1    (RASv1p1)
+ *   ERXSTATUS_EL1
+ * and
+ *   ERRSELR_EL1
+ * may generate UNDEFINED, which is the effect we get by not
+ * listing them at all.
+ */
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
+    { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
+      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
+      .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
+    { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
+      .access = PL1_R, .accessfn = access_terr,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
+    { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
+};
+
 /* Return the exception level to which exceptions should be taken
  * via SVEAccessTrap.  If an exception should be routed through
  * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_ssbs, cpu)) {
         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
     }
+    if (cpu_isar_feature(any_ras, cpu)) {
+        define_arm_cp_regs(cpu, minimal_ras_reginfo);
+    }
 
     if (cpu_isar_feature(aa64_vh, cpu) ||
         cpu_isar_feature(aa64_debugv8p2, cpu)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
         valid_mask &= ~SCR_NET;
 
+        if (cpu_isar_feature(aa64_ras, cpu)) {
+            valid_mask |= SCR_TERR;
+        }
         if (cpu_isar_feature(aa64_lor, cpu)) {
             valid_mask |= SCR_TLOR;
         }
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
+        if (cpu_isar_feature(aa32_ras, cpu)) {
+            valid_mask |= SCR_TERR;
+        }
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         if (cpu_isar_feature(aa64_vh, cpu)) {
             valid_mask |= HCR_E2H;
         }
+        if (cpu_isar_feature(aa64_ras, cpu)) {
+            valid_mask |= HCR_TERR | HCR_TEA;
+        }
         if (cpu_isar_feature(aa64_lor, cpu)) {
             valid_mask |= HCR_TLOR;
         }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |  2 ++
 target/arm/internals.h |  8 ++++++++
 target/arm/syndrome.h  |  5 +++++
 target/arm/cpu.c       | 38 +++++++++++++++++++++++++++++++++++++-
 target/arm/helper.c    | 40 +++++++++++++++++++++++++++++++++++++++-
 5 files changed, 91 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
 #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
 #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
+#define EXCP_VSERR          24
 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
 
 #define ARMV7M_EXCP_RESET   1
@@ -XXX,XX +XXX,XX @@ enum {
 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
 
 /* The usual mapping for an AArch64 system register to its AArch32
  * counterpart is for the 32 bit world to have access to the lower
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
  */
 void arm_cpu_update_vfiq(ARMCPU *cpu);
 
+/**
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
+ *
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
+ * following a change to the HCR_EL2.VSE bit.
+ */
+void arm_cpu_update_vserr(ARMCPU *cpu);
+
 /**
  * arm_mmu_idx_el:
  * @env: The cpu environment
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
     return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 }
 
+static inline uint32_t syn_serror(uint32_t extra)
+{
+    return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
+}
+
 #endif /* TARGET_ARM_SYNDROME_H */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
     return (cpu->power_state != PSCI_OFF)
         && cs->interrupt_request &
         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
-         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
+         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
          | CPU_INTERRUPT_EXITTB);
 }
 
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
             return false;
         }
         return !(env->daif & PSTATE_I);
+    case EXCP_VSERR:
+        if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
+            /* VIRQs are only taken when hypervized.  */
+            return false;
+        }
+        return !(env->daif & PSTATE_A);
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
             goto found;
         }
     }
+    if (interrupt_request & CPU_INTERRUPT_VSERR) {
+        excp_idx = EXCP_VSERR;
+        target_el = 1;
+        if (arm_excp_unmasked(cs, excp_idx, target_el,
+                              cur_el, secure, hcr_el2)) {
+            /* Taking a virtual abort clears HCR_EL2.VSE */
+            env->cp15.hcr_el2 &= ~HCR_VSE;
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+            goto found;
+        }
+    }
     return false;
 
  found:
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
     }
 }
 
+void arm_cpu_update_vserr(ARMCPU *cpu)
+{
+    /*
+     * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
+     */
+    CPUARMState *env = &cpu->env;
+    CPUState *cs = CPU(cpu);
+
+    bool new_state = env->cp15.hcr_el2 & HCR_VSE;
+
+    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
+        if (new_state) {
+            cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
+        } else {
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+        }
+    }
+}
+
 #ifndef CONFIG_USER_ONLY
 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
         }
     }
 
-    /* External aborts are not possible in QEMU so A bit is always clear */
+    if (hcr_el2 & HCR_AMO) {
+        if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
+            ret |= CPSR_A;
+        }
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
     g_assert(qemu_mutex_iothread_locked());
     arm_cpu_update_virq(cpu);
     arm_cpu_update_vfiq(cpu);
+    arm_cpu_update_vserr(cpu);
 }
 
 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
             [EXCP_LSERR] = "v8M LSERR UsageFault",
             [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
             [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
+            [EXCP_VSERR] = "Virtual SERR",
         };
 
         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
         mask = CPSR_A | CPSR_I | CPSR_F;
         offset = 4;
         break;
+    case EXCP_VSERR:
+        {
+            /*
+             * Note that this is reported as a data abort, but the DFAR
+             * has an UNKNOWN value.  Construct the SError syndrome from
+             * AET and ExT fields.
+             */
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
+
+            if (extended_addresses_enabled(env)) {
+                env->exception.fsr = arm_fi_to_lfsc(&fi);
+            } else {
+                env->exception.fsr = arm_fi_to_sfsc(&fi);
+            }
+            env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
+            A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
+            qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
+                          env->exception.fsr);
+
+            new_mode = ARM_CPU_MODE_ABT;
+            addr = 0x10;
+            mask = CPSR_A | CPSR_I;
+            offset = 8;
+        }
+        break;
     case EXCP_SMC:
         new_mode = ARM_CPU_MODE_MON;
         addr = 0x08;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     case EXCP_VFIQ:
         addr += 0x100;
         break;
+    case EXCP_VSERR:
+        addr += 0x180;
+        /* Construct the SError syndrome from IDS and ISS fields. */
+        env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
+        env->cp15.esr_el[new_el] = env->exception.syndrome;
+        break;
     default:
         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Check for and defer any pending virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  1 +
 target/arm/a32.decode      | 16 ++++++++------
 target/arm/t32.decode      | 18 ++++++++--------
 target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c | 17 +++++++++++++++
 target/arm/translate.c     | 23 ++++++++++++++++++++
 6 files changed, 103 insertions(+), 15 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
 DEF_HELPER_1(yield, void, env)
 DEF_HELPER_1(pre_hvc, void, env)
 DEF_HELPER_2(pre_smc, void, env, i32)
+DEF_HELPER_1(vesb, void, env)
 
 DEF_HELPER_3(cpsr_write, void, env, i32, i32)
 DEF_HELPER_2(cpsr_write_eret, void, env, i32)
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -XXX,XX +XXX,XX @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
 
 {
   {
-    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
-    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
-    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
+    [
+      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
+      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
+      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 
-    # TODO: Implement SEV, SEVL; may help SMP performance.
-    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
-    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
+      # TODO: Implement SEV, SEVL; may help SMP performance.
+      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
+      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
+
+      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
+    ]
 
     # The canonical nop ends in 00000000, but the whole of the
     # rest of the space executes as nop if otherwise unsupported.
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
   [
     # Hints, and CPS
     {
-      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
-      WFE        1111 0011 1010 1111 1000 0000 0000 0010
-      WFI        1111 0011 1010 1111 1000 0000 0000 0011
+      [
+        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
+        WFE      1111 0011 1010 1111 1000 0000 0000 0010
+        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 
-      # TODO: Implement SEV, SEVL; may help SMP performance.
-      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
-      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
+        # TODO: Implement SEV, SEVL; may help SMP performance.
+        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
+        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 
-      # For M-profile minimal-RAS ESB can be a NOP, which is the
-      # default behaviour since it is in the hint space.
-      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
+        ESB      1111 0011 1010 1111 1000 0000 0001 0000
+      ]
 
       # The canonical nop ends in 0000 0000, but the whole rest
       # of the space is "reserved hint, behaves as nop".
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                      access_type, mmu_idx, ra);
     }
 }
+
+/*
+ * This function corresponds to AArch64.vESBOperation().
+ * Note that the AArch32 version is not functionally different.
+ */
+void HELPER(vesb)(CPUARMState *env)
+{
+    /*
+     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
+     * and will return HCR_EL2.VSE == 0, so nothing happens.
+     */
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
+    bool pending = enabled && (hcr & HCR_VSE);
+    bool masked  = (env->daif & PSTATE_A);
+
+    /* If VSE pending and masked, defer the exception.  */
+    if (pending && masked) {
+        uint32_t syndrome;
+
+        if (arm_el_is_aa64(env, 1)) {
+            /* Copy across IDS and ISS from VSESR. */
+            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
+        } else {
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
+
+            if (extended_addresses_enabled(env)) {
+                syndrome = arm_fi_to_lfsc(&fi);
+            } else {
+                syndrome = arm_fi_to_sfsc(&fi);
+            }
+            /* Copy across AET and ExT from VSESR. */
+            syndrome |= env->cp15.vsesr_el2 & 0xd000;
+        }
+
+        /* Set VDISR_EL2.A along with the syndrome. */
+        env->cp15.vdisr_el2 = syndrome | (1u << 31);
+
+        /* Clear pending virtual SError */
+        env->cp15.hcr_el2 &= ~HCR_VSE;
+        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
+    }
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
             gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
         }
         break;
+    case 0b10000: /* ESB */
+        /* Without RAS, we must implement this as NOP. */
+        if (dc_isar_feature(aa64_ras, s)) {
+            /*
+             * QEMU does not have a source of physical SErrors,
+             * so we are only concerned with virtual SErrors.
+             * The pseudocode in the ARM for this case is
+             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+             *      AArch64.vESBOperation();
+             * Most of the condition can be evaluated at translation time.
+             * Test for EL2 present, and defer test for SEL2 to runtime.
+             */
+            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+                gen_helper_vesb(cpu_env);
+            }
+        }
+        break;
     case 0b11000: /* PACIAZ */
         if (s->pauth_active) {
             gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
     return true;
 }
 
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
+{
+    /*
+     * For M-profile, minimal-RAS ESB can be a NOP.
+     * Without RAS, we must implement this as NOP.
+     */
+    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
+        /*
+         * QEMU does not have a source of physical SErrors,
+         * so we are only concerned with virtual SErrors.
+         * The pseudocode in the ARM for this case is
+         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+         *      AArch32.vESBOperation();
+         * Most of the condition can be evaluated at translation time.
+         * Test for EL2 present, and defer test for SEL2 to runtime.
+         */
+        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+            gen_helper_vesb(cpu_env);
+        }
+    }
+    return true;
+}
+
 static bool trans_NOP(DisasContext *s, arg_NOP *a)
 {
     return true;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 2 files changed, 2 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns branch speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst |  3 ++
 target/arm/cpu.h              | 16 +++++++++
 target/arm/cpu.c              |  5 +++
 target/arm/cpu64.c            |  3 +-
 target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
 5 files changed, 86 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_BF16 (AArch64 BFloat16 instructions)
 - FEAT_BTI (Branch Target Identification)
 - FEAT_CSV2 (Cache speculation variant 2)
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
 - FEAT_DIT (Data Independent Timing instructions)
 - FEAT_DPB (DC CVAP instruction)
 - FEAT_Debugv8p2 (Debug changes for v8.2)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         ARMPACKey apdb;
         ARMPACKey apga;
     } keys;
+
+    uint64_t scxtnum_el[4];
 #endif
 
 #if defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
 #define SCTLR_WXN     (1U << 19)
 #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
 #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
+#define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
 #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
 #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
 #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
 }
 
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
+{
+    int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
+    if (key >= 2) {
+        return true;      /* FEAT_CSV2_2 */
+    }
+    if (key == 1) {
+        key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
+        return key >= 2;  /* FEAT_CSV2_1p2 */
+    }
+    return false;
+}
+
 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
              */
             env->cp15.gcr_el1 = 0x1ffff;
         }
+        /*
+         * Disable access to SCXTNUM_EL0 from CSV2_1p2.
+         * This is not yet exposed from the Linux kernel in any way.
+         */
+        env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
 #else
         /* Reset into the highest available EL */
         if (arm_feature(env, ARM_FEATURE_EL3)) {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr0 = t;
 
     t = cpu->isar.id_aa64pfr1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      * we do for EL2 with the virtualization=on property.
      */
     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
+    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr1 = t;
 
     t = cpu->isar.id_aa64mmfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= SCR_ATA;
         }
+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+            valid_mask |= SCR_ENSCXT;
+        }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
         if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
         }
+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+            valid_mask |= HCR_ENSCXT;
+        }
     }
 
     /* Clear RES0 bits.  */
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
         { K(3, 0,  5, 6, 0), K(3, 4,  5, 6, 0), K(3, 5, 5, 6, 0),
           "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
 
+        { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
+          "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
+          isar_feature_aa64_scxtnum },
+
         /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
         /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
     };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
     },
 };
 
-#endif
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
+                                     bool isread)
+{
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    int el = arm_current_el(env);
+
+    if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
+        if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
+            if (hcr & HCR_TGE) {
+                return CP_ACCESS_TRAP_EL2;
+            }
+            return CP_ACCESS_TRAP;
+        }
+    } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3
+        && arm_feature(env, ARM_FEATURE_EL3)
+        && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static const ARMCPRegInfo scxtnum_reginfo[] = {
+    { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL0_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
+    { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL1_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
+    { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL2_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
+    { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL3_RW,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
+};
+#endif /* TARGET_AARCH64 */
 
 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
                                      bool isread)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     }
+
+    if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+        define_arm_cp_regs(cpu, scxtnum_reginfo);
+    }
 #endif
 
     if (cpu_isar_feature(any_predinv, cpu)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns cache speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns not merging memory access, which TCG does
not implement.  Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/translate-a64.c    | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

Enable the a76 for virt and sbsa board use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/sbsa-ref.c        |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a53`` (64-bit)
 - ``cortex-a57`` (64-bit)
 - ``cortex-a72`` (64-bit)
+- ``cortex-a76`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
 static const char * const valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("max"),
 };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a53"),
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("a64fx"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
+static void aarch64_a76_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a76";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444C004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0b1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.18 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+    /* From B2.93 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+}
+
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
+    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable the n1 for virt and sbsa board use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/sbsa-ref.c        |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a76`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
+- ``neoverse-n1`` (64-bit)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
 
 Note that the default is ``cortex-a15``, so for an AArch64 guest you must
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
+    ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("max"),
 };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("a64fx"),
+    ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
     cpu->isar.mvfr2 = 0x00000043;
 }
 
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,neoverse-n1";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444c004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0c1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.23 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+    /* From B2.98 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+}
+
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+    { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
     { .name = "host",               .initfn = aarch64_host_initfn },
-- 
2.25.1

From: Leif Lindholm <quic_llindhol@quicinc.com>

The sbsa-ref machine is continuously evolving. Some of the changes we
want to make in the near future, to align with real components (e.g.
the GIC-700), will break compatibility for existing firmware.

Introduce two new properties to the DT generated on machine generation:
- machine-version-major
  To be incremented when a platform change makes the machine
  incompatible with existing firmware.
- machine-version-minor
  To be incremented when functionality is added to the machine
  without causing incompatibility with existing firmware.
  to be reset to 0 when machine-version-major is incremented.

This versioning scheme is *neither*:
- A QEMU versioned machine type; a given version of QEMU will emulate
  a given version of the platform.
- A reflection of level of SBSA (now SystemReady SR) support provided.

The version will increment on guest-visible functional changes only,
akin to a revision ID register found on a physical platform.

These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 
+    /*
+     * This versioning scheme is for informing platform fw only. It is neither:
+     * - A QEMU versioned machine type; a given version of QEMU will emulate
+     *   a given version of the platform.
+     * - A reflection of level of SBSA (now SystemReady SR) support provided.
+     *
+     * machine-version-major: updated when changes breaking fw compatibility
+     *                        are introduced.
+     * machine-version-minor: updated when features are added that don't break
+     *                        fw compatibility.
+     */
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
+
     if (ms->numa_state->have_numa_distance) {
         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
         uint32_t *matrix = g_malloc0(size);
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:

* hw/core/machine.c::machine_set_cpu_numa_node() to associate
    CPU with its NUMA node.

* hw/core/machine.c::machine_numa_finish_cpu_init() to record
    CPU slots with no NUMA mapping set.

* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
    cluster-id.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 qapi/machine.json          |  6 ++++--
 hw/core/machine-hmp-cmds.c |  4 ++++
 hw/core/machine.c          | 16 ++++++++++++++++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/qapi/machine.json b/qapi/machine.json
index XXXXXXX..XXXXXXX 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -XXX,XX +XXX,XX @@
 # @node-id: NUMA node ID the CPU belongs to
 # @socket-id: socket number within node/board the CPU belongs to
 # @die-id: die number within socket the CPU belongs to (since 4.1)
-# @core-id: core number within die the CPU belongs to
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
+# @core-id: core number within cluster the CPU belongs to
 # @thread-id: thread number within core the CPU belongs to
 #
-# Note: currently there are 5 properties that could be present
+# Note: currently there are 6 properties that could be present
 #       but management should be prepared to pass through other
 #       properties with device_add command to allow for future
 #       interface extension. This also requires the filed names to be kept in
@@ -XXX,XX +XXX,XX @@
   'data': { '*node-id': 'int',
             '*socket-id': 'int',
             '*die-id': 'int',
+            '*cluster-id': 'int',
             '*core-id': 'int',
             '*thread-id': 'int'
   }
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine-hmp-cmds.c
+++ b/hw/core/machine-hmp-cmds.c
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
         if (c->has_die_id) {
             monitor_printf(mon, "    die-id: \"%" PRIu64 "\"\n", c->die_id);
         }
+        if (c->has_cluster_id) {
+            monitor_printf(mon, "    cluster-id: \"%" PRIu64 "\"\n",
+                           c->cluster_id);
+        }
         if (c->has_core_id) {
             monitor_printf(mon, "    core-id: \"%" PRIu64 "\"\n", c->core_id);
         }
diff --git a/hw/core/machine.c b/hw/core/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
             return;
         }
 
+        if (props->has_cluster_id && !slot->props.has_cluster_id) {
+            error_setg(errp, "cluster-id is not supported");
+            return;
+        }
+
         if (props->has_socket_id && !slot->props.has_socket_id) {
             error_setg(errp, "socket-id is not supported");
             return;
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
                 continue;
         }
 
+        if (props->has_cluster_id &&
+            props->cluster_id != slot->props.cluster_id) {
+                continue;
+        }
+
         if (props->has_die_id && props->die_id != slot->props.die_id) {
                 continue;
         }
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
         }
         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
     }
+    if (cpu->props.has_cluster_id) {
+        if (s->len) {
+            g_string_append_printf(s, ", ");
+        }
+        g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
+    }
     if (cpu->props.has_core_id) {
         if (s->len) {
             g_string_append_printf(s, ", ");
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

The CPU topology isn't enabled on arm/virt machine yet, but we're
going to do it in next patch. After the CPU topology is enabled by
next patch, "thread-id=1" becomes invalid because the CPU core is
preferred on arm/virt machine. It means these two CPUs have 0/1
as their core IDs, but their thread IDs are all 0. It will trigger
test failure as the following message indicates:

[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test  ERROR
  1.48s   killed by signal 6 SIGABRT
  >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
      QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon         \
      QTEST_QEMU_BINARY=./qemu-system-aarch64                                       \
      QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83                                  \
      /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
  ――――――――――――――――――――――――――――――――――――――――――――――
  stderr:
  qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found

This fixes the issue by providing comprehensive SMP configurations
in aarch64_numa_cpu(). The SMP configurations aren't used before
the CPU topology is enabled in next patch.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/numa-test.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Gavin Shan <gshan@redhat.com>

Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.

This takes account of SMP configuration when the CPU topology
is populated. The die ID for the given CPU isn't assigned since
it's not supported on arm/virt machine. Besides, the used SMP
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
to avoid testing failure

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-4-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
     int n;
     unsigned int max_cpus = ms->smp.max_cpus;
     VirtMachineState *vms = VIRT_MACHINE(ms);
+    MachineClass *mc = MACHINE_GET_CLASS(vms);
 
     if (ms->possible_cpus) {
         assert(ms->possible_cpus->len == max_cpus);
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
         ms->possible_cpus->cpus[n].type = ms->cpu_type;
         ms->possible_cpus->cpus[n].arch_id =
             virt_cpu_mp_affinity(vms, n);
+
+        assert(!mc->smp_props.dies_supported);
+        ms->possible_cpus->cpus[n].props.has_socket_id = true;
+        ms->possible_cpus->cpus[n].props.socket_id =
+            n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
+        ms->possible_cpus->cpus[n].props.has_cluster_id = true;
+        ms->possible_cpus->cpus[n].props.cluster_id =
+            (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
+        ms->possible_cpus->cpus[n].props.has_core_id = true;
+        ms->possible_cpus->cpus[n].props.core_id =
+            (n / ms->smp.threads) % ms->smp.cores;
         ms->possible_cpus->cpus[n].props.has_thread_id = true;
-        ms->possible_cpus->cpus[n].props.thread_id = n;
+        ms->possible_cpus->cpus[n].props.thread_id =
+            n % ms->smp.threads;
     }
     return ms->possible_cpus;
 }
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

In aarch64_numa_cpu(), the CPU and NUMA association is something
like below. Two threads in the same core/cluster/socket are
associated with two individual NUMA nodes, which is unreal as
Igor Mammedov mentioned. We don't expect the association to break
NUMA-to-socket boundary, which matches with the real world.

NUMA-node  socket  cluster   core   thread
    ------------------------------------------
        0       0        0        0      0
        1       0        0        0      1

This corrects the topology for CPUs and their association with
NUMA nodes. After this patch is applied, the CPU and NUMA
association becomes something like below, which looks real.
Besides, socket/cluster/core/thread IDs are all checked when
the NUMA node IDs are verified. It helps to check if the CPU
topology is properly populated or not.

NUMA-node  socket  cluster   core   thread
    ------------------------------------------
       0        1        0        0       0
       1        0        0        0       0

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-5-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/numa-test.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/numa-test.c
+++ b/tests/qtest/numa-test.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
     g_autofree char *cli = NULL;
 
     cli = make_cli(data, "-machine "
-        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+        "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
-        "-numa cpu,node-id=1,thread-id=0 "
-        "-numa cpu,node-id=0,thread-id=1");
+        "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
+        "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
     qts = qtest_init(cli);
     cpus = get_cpus(qts, &resp);
     g_assert(cpus);
 
     while ((e = qlist_pop(cpus))) {
         QDict *cpu, *props;
-        int64_t thread, node;
+        int64_t socket, cluster, core, thread, node;
 
         cpu = qobject_to(QDict, e);
         g_assert(qdict_haskey(cpu, "props"));
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
 
         g_assert(qdict_haskey(props, "node-id"));
         node = qdict_get_int(props, "node-id");
+        g_assert(qdict_haskey(props, "socket-id"));
+        socket = qdict_get_int(props, "socket-id");
+        g_assert(qdict_haskey(props, "cluster-id"));
+        cluster = qdict_get_int(props, "cluster-id");
+        g_assert(qdict_haskey(props, "core-id"));
+        core = qdict_get_int(props, "core-id");
         g_assert(qdict_haskey(props, "thread-id"));
         thread = qdict_get_int(props, "thread-id");
 
-        if (thread == 0) {
+        if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
             g_assert_cmpint(node, ==, 1);
-        } else if (thread == 1) {
+        } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
             g_assert_cmpint(node, ==, 0);
         } else {
             g_assert(false);
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.

For example, the following warning messages are observed when the
Linux guest is booted with the following command lines.

/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
  -accel kvm -machine virt,gic-version=host               \
  -cpu host                                               \
  -smp 6,sockets=2,cores=3,threads=1                      \
  -m 1024M,slots=16,maxmem=64G                            \
  -object memory-backend-ram,id=mem0,size=128M            \
  -object memory-backend-ram,id=mem1,size=128M            \
  -object memory-backend-ram,id=mem2,size=128M            \
  -object memory-backend-ram,id=mem3,size=128M            \
  -object memory-backend-ram,id=mem4,size=128M            \
  -object memory-backend-ram,id=mem4,size=384M            \
  -numa node,nodeid=0,memdev=mem0                         \
  -numa node,nodeid=1,memdev=mem1                         \
  -numa node,nodeid=2,memdev=mem2                         \
  -numa node,nodeid=3,memdev=mem3                         \
  -numa node,nodeid=4,memdev=mem4                         \
  -numa node,nodeid=5,memdev=mem5
         :
  alternatives: patching kernel code
  BUG: arch topology borken
  the CLS domain not a subset of the MC domain
  <the above error log repeats>
  BUG: arch topology borken
  the DIE domain not a subset of the NODE domain

With current implementation of mc->get_default_cpu_node_id(),
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
That's incorrect because CPU#0/1/2 should be associated with same
NUMA node because they're seated in same socket.

This fixes the issue by considering the socket ID when the default
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
With this applied, no more CPU topology broken warnings are seen
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
there are no CPUs associated with NODE#2/3/4/5.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 
 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
 {
-    return idx % ms->numa_state->num_nodes;
+    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
+
+    return socket_id % ms->numa_state->num_nodes;
 }
 
 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.

This reworks build_pptt() to avoid by reusing the existing IDs in
ms->possible_cpus. Currently, the only user of build_pptt() is
arm/virt machine.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Tested-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20220503140304.855514-7-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
 1 file changed, 48 insertions(+), 63 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
                 const char *oem_id, const char *oem_table_id)
 {
     MachineClass *mc = MACHINE_GET_CLASS(ms);
-    GQueue *list = g_queue_new();
-    guint pptt_start = table_data->len;
-    guint parent_offset;
-    guint length, i;
-    int uid = 0;
-    int socket;
+    CPUArchIdList *cpus = ms->possible_cpus;
+    int64_t socket_id = -1, cluster_id = -1, core_id = -1;
+    uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
+    uint32_t pptt_start = table_data->len;
+    int n;
     AcpiTable table = { .sig = "PPTT", .rev = 2,
                         .oem_id = oem_id, .oem_table_id = oem_table_id };
 
     acpi_table_begin(&table, table_data);
 
-    for (socket = 0; socket < ms->smp.sockets; socket++) {
-        g_queue_push_tail(list,
-            GUINT_TO_POINTER(table_data->len - pptt_start));
-        build_processor_hierarchy_node(
-            table_data,
-            /*
-             * Physical package - represents the boundary
-             * of a physical package
-             */
-            (1 << 0),
-            0, socket, NULL, 0);
-    }
-
-    if (mc->smp_props.clusters_supported) {
-        length = g_queue_get_length(list);
-        for (i = 0; i < length; i++) {
-            int cluster;
-
-            parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-            for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
-                g_queue_push_tail(list,
-                    GUINT_TO_POINTER(table_data->len - pptt_start));
-                build_processor_hierarchy_node(
-                    table_data,
-                    (0 << 0), /* not a physical package */
-                    parent_offset, cluster, NULL, 0);
-            }
+    /*
+     * This works with the assumption that cpus[n].props.*_id has been
+     * sorted from top to down levels in mc->possible_cpu_arch_ids().
+     * Otherwise, the unexpected and duplicated containers will be
+     * created.
+     */
+    for (n = 0; n < cpus->len; n++) {
+        if (cpus->cpus[n].props.socket_id != socket_id) {
+            assert(cpus->cpus[n].props.socket_id > socket_id);
+            socket_id = cpus->cpus[n].props.socket_id;
+            cluster_id = -1;
+            core_id = -1;
+            socket_offset = table_data->len - pptt_start;
+            build_processor_hierarchy_node(table_data,
+                (1 << 0), /* Physical package */
+                0, socket_id, NULL, 0);
         }
-    }
 
-    length = g_queue_get_length(list);
-    for (i = 0; i < length; i++) {
-        int core;
-
-        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-        for (core = 0; core < ms->smp.cores; core++) {
-            if (ms->smp.threads > 1) {
-                g_queue_push_tail(list,
-                    GUINT_TO_POINTER(table_data->len - pptt_start));
-                build_processor_hierarchy_node(
-                    table_data,
-                    (0 << 0), /* not a physical package */
-                    parent_offset, core, NULL, 0);
-            } else {
-                build_processor_hierarchy_node(
-                    table_data,
-                    (1 << 1) | /* ACPI Processor ID valid */
-                    (1 << 3),  /* Node is a Leaf */
-                    parent_offset, uid++, NULL, 0);
+        if (mc->smp_props.clusters_supported) {
+            if (cpus->cpus[n].props.cluster_id != cluster_id) {
+                assert(cpus->cpus[n].props.cluster_id > cluster_id);
+                cluster_id = cpus->cpus[n].props.cluster_id;
+                core_id = -1;
+                cluster_offset = table_data->len - pptt_start;
+                build_processor_hierarchy_node(table_data,
+                    (0 << 0), /* Not a physical package */
+                    socket_offset, cluster_id, NULL, 0);
             }
+        } else {
+            cluster_offset = socket_offset;
         }
-    }
 
-    length = g_queue_get_length(list);
-    for (i = 0; i < length; i++) {
-        int thread;
+        if (ms->smp.threads == 1) {
+            build_processor_hierarchy_node(table_data,
+                (1 << 1) | /* ACPI Processor ID valid */
+                (1 << 3),  /* Node is a Leaf */
+                cluster_offset, n, NULL, 0);
+        } else {
+            if (cpus->cpus[n].props.core_id != core_id) {
+                assert(cpus->cpus[n].props.core_id > core_id);
+                core_id = cpus->cpus[n].props.core_id;
+                core_offset = table_data->len - pptt_start;
+                build_processor_hierarchy_node(table_data,
+                    (0 << 0), /* Not a physical package */
+                    cluster_offset, core_id, NULL, 0);
+            }
 
-        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-        for (thread = 0; thread < ms->smp.threads; thread++) {
-            build_processor_hierarchy_node(
-                table_data,
+            build_processor_hierarchy_node(table_data,
                 (1 << 1) | /* ACPI Processor ID valid */
                 (1 << 2) | /* Processor is a Thread */
                 (1 << 3),  /* Node is a Leaf */
-                parent_offset, uid++, NULL, 0);
+                core_offset, n, NULL, 0);
         }
     }
 
-    g_queue_free(list);
     acpi_table_end(linker, &table);
 }
 
-- 
2.25.1

Hi; here's a target-arm pullreq to go in before softfreeze.
This is actually pretty much entirely bugfixes (since the
SEL2 timers we implement here are a missing part of a feature
we claim to already implement).

thanks
-- PMM

The following changes since commit 98c7362b1efe651327385a25874a73e008c6549e:

Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging (2025-03-07 07:39:49 +0800)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250307

for you to fetch changes up to 0ce0739d46983e5e88fa9c149cb305689c9d8c6f:

target/rx: Remove TCG_CALL_NO_WG from helpers which write env (2025-03-07 15:03:20 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/smmu-common: Remove the repeated ttb field
 * hw/gpio: npcm7xx: fixup out-of-bounds access
 * tests/functional/test_arm_sx1: Check whether the serial console is working
 * target/arm: Fix minor bugs in generic timer register handling
 * target/arm: Implement SEL2 physical and virtual timers
 * target/arm: Correct STRD, LDRD atomicity and fault behaviour
 * target/arm: Make dummy debug registers RAZ, not NOP
 * util/qemu-timer.c: Don't warp timer from timerlist_rearm()
 * include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
 * hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
 * target/rx: Set exception vector base to 0xffffff80
 * target/rx: Remove TCG_CALL_NO_WG from helpers which write env

----------------------------------------------------------------
Alex Bennée (4):
      target/arm: Implement SEL2 physical and virtual timers
      target/arm: Document the architectural names of our GTIMERs
      hw/arm: enable secure EL2 timers for virt machine
      hw/arm: enable secure EL2 timers for sbsa machine

JianChunfu (2):
      hw/arm/smmu-common: Remove the repeated ttb field
      hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper

Keith Packard (2):
      target/rx: Set exception vector base to 0xffffff80
      target/rx: Remove TCG_CALL_NO_WG from helpers which write env

Patrick Venture (1):
      hw/gpio: npcm7xx: fixup out-of-bounds access

Peter Maydell (11):
      target/arm: Apply correct timer offset when calculating deadlines
      target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
      target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
      target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
      target/arm: Refactor handling of timer offset for direct register accesses
      target/arm: Correct LDRD atomicity and fault behaviour
      target/arm: Correct STRD atomicity
      target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
      target/arm: Make dummy debug registers RAZ, not NOP
      util/qemu-timer.c: Don't warp timer from timerlist_rearm()
      include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN

Thomas Huth (1):
      tests/functional/test_arm_sx1: Check whether the serial console is working

From: JianChunfu <jansef.jian@hj-micro.com>

SMMUTransCfg->ttb is never used in QEMU, TT base address
can be accessed by SMMUTransCfg->tt[i]->ttb.

Signed-off-by: JianChunfu <jansef.jian@hj-micro.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20250221031034.69822-1-jansef.jian@hj-micro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/smmu-common.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
     /* Used by stage-1 only. */
     bool aa64;                 /* arch64 or aarch32 translation table */
     bool record_faults;        /* record fault events */
-    uint64_t ttb;              /* TT base address */
     uint8_t oas;               /* output address width */
     uint8_t tbi;               /* Top Byte Ignore */
     int asid;
-- 
2.43.0

From: Patrick Venture <venture@google.com>

The reg isn't validated to be a possible register before
it's dereferenced for one case.  The mmio space registered
for the gpio device is 4KiB but there aren't that many
registers in the struct.

Cc: qemu-stable@nongnu.org
Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nuvoton NPCM7xx")
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250226024603.493148-1-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/npcm7xx_gpio.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/npcm7xx_gpio.c
+++ b/hw/gpio/npcm7xx_gpio.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
         return;
     }
 
-    diff = s->regs[reg] ^ value;
-
     switch (reg) {
     case NPCM7XX_GPIO_TLOCK1:
     case NPCM7XX_GPIO_TLOCK2:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
     case NPCM7XX_GPIO_PU:
     case NPCM7XX_GPIO_PD:
     case NPCM7XX_GPIO_IEM:
+        diff = s->regs[reg] ^ value;
         s->regs[reg] = value;
         npcm7xx_gpio_update_pins(s, diff);
         break;
-- 
2.43.0

From: Thomas Huth <thuth@redhat.com>

The kernel that is used in the sx1 test prints the usual Linux log
onto the serial console, but this test currently ignores it. To
make sure that the serial device is working properly, let's check
for some strings in the output here.

While we're at it, also add the test to the corresponding section
in the MAINTAINERS file.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250226104833.1176253-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS                      | 1 +
 tests/functional/test_arm_sx1.py | 7 ++++---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ S: Maintained
 F: hw/*/omap*
 F: include/hw/arm/omap.h
 F: docs/system/arm/sx1.rst
+F: tests/functional/test_arm_sx1.py
 
 IPack
 M: Alberto Garcia <berto@igalia.com>
diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/test_arm_sx1.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_arm_sx1.py
+++ b/tests/functional/test_arm_sx1.py
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_initrd(self):
         self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}')
         self.vm.add_args('-no-reboot')
         self.launch_kernel(zimage_path,
-                           initrd=initrd_path)
+                           initrd=initrd_path,
+                           wait_for='Boot successful')
         self.vm.wait(timeout=120)
 
     def test_arm_sx1_sd(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_sd(self):
         self.vm.add_args('-no-reboot')
         self.vm.add_args('-snapshot')
         self.vm.add_args('-drive', f'format=raw,if=sd,file={sd_fs_path}')
-        self.launch_kernel(zimage_path)
+        self.launch_kernel(zimage_path, wait_for='Boot successful')
         self.vm.wait(timeout=120)
 
     def test_arm_sx1_flash(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_flash(self):
         self.vm.add_args('-no-reboot')
         self.vm.add_args('-snapshot')
         self.vm.add_args('-drive', f'format=raw,if=pflash,file={flash_path}')
-        self.launch_kernel(zimage_path)
+        self.launch_kernel(zimage_path, wait_for='Boot successful')
         self.vm.wait(timeout=120)
 
 if __name__ == '__main__':
-- 
2.43.0

When we are calculating timer deadlines, the correct definition of
whether or not to apply an offset to the physical count is described
in the Arm ARM DDI4087 rev L.a section D12.2.4.1.  This is different
from when the offset should be applied for a direct read of the
counter sysreg.

We got this right for the EL1 physical timer and for the EL1 virtual
timer, but got all the rest wrong: they should be using a zero offset
always.

Factor the offset calculation out into a function that has a comment
documenting exactly which offset it is calculating and which gets the
HYP, SEC, and HYPVIRT cases right.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250204125009.2281315-2-peter.maydell@linaro.org
---
 target/arm/helper.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_cnt_offset(CPUARMState *env)
     return gt_phys_raw_cnt_offset(env);
 }
 
+static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
+{
+    /*
+     * Return the timer offset to use for indirect accesses to the timer.
+     * This is the Offset value as defined in D12.2.4.1 "Operation of the
+     * CompareValue views of the timers".
+     *
+     * The condition here is not always the same as the condition for
+     * whether to apply an offset register when doing a direct read of
+     * the counter sysreg; those conditions are described in the
+     * access pseudocode for each counter register.
+     */
+    switch (timeridx) {
+    case GTIMER_PHYS:
+        return gt_phys_raw_cnt_offset(env);
+    case GTIMER_VIRT:
+        return env->cp15.cntvoff_el2;
+    case GTIMER_HYP:
+    case GTIMER_SEC:
+    case GTIMER_HYPVIRT:
+        return 0;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 {
     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
          * Timer enabled: calculate and set current ISTATUS, irq, and
          * reset timer to when ISTATUS next has to change
          */
-        uint64_t offset = timeridx == GTIMER_VIRT ?
-            cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
+        uint64_t offset = gt_indirect_access_timer_offset(&cpu->env, timeridx);
         uint64_t count = gt_get_countervalue(&cpu->env);
         /* Note that this must be unsigned 64 bit arithmetic: */
         int istatus = count - offset >= gt->cval;
-- 
2.43.0

The CNTVOFF_EL2 offset register should only be applied for accessses
to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*).  We were
incorrectly applying it for the EL2 virtual timer (CNTHV_*).

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
 
     switch (timeridx) {
     case GTIMER_VIRT:
-    case GTIMER_HYPVIRT:
         offset = gt_virt_cnt_offset(env);
         break;
     case GTIMER_PHYS:
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     switch (timeridx) {
     case GTIMER_VIRT:
-    case GTIMER_HYPVIRT:
         offset = gt_virt_cnt_offset(env);
         break;
     case GTIMER_PHYS:
-- 
2.43.0

When we added Secure EL2 support, we missed that this needs an update
to the access code for the EL3 physical timer registers.  These are
supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.

(Note for stable backporting: for backports to branches where
CP_ACCESS_UNDEFINED is not defined, the old name to use instead
is CP_ACCESS_TRAP_UNCATEGORIZED.)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
         if (!arm_is_secure(env)) {
             return CP_ACCESS_UNDEFINED;
         }
+        if (arm_is_el2_enabled(env)) {
+            return CP_ACCESS_UNDEFINED;
+        }
         if (!(env->cp15.scr_el3 & SCR_ST)) {
             return CP_ACCESS_TRAP_EL3;
         }
-- 
2.43.0

Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the
EL1 virt timer.  This is almost correct, but the underlying
CNTV_TVAL_EL0 register behaves slightly differently.  CNTV_TVAL_EL02
always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if
we're at EL2 and HCR_EL2.E2H is 1.

We were getting this wrong, because we ended up in
gt_virt_cnt_offset() and did the E2H check.

Factor out the tval read/write calculation from the selection of the
offset, so that we can special case gt_virt_tval_read() and
gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250204125009.2281315-5-peter.maydell@linaro.org
---
 target/arm/helper.c | 36 +++++++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
     gt_recalc_timer(env_archcpu(env), timeridx);
 }
 
+static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset)
+{
+    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
+                      (gt_get_countervalue(env) - offset));
+}
+
 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
                              int timeridx)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
         break;
     }
 
-    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
-                      (gt_get_countervalue(env) - offset));
+    return do_tval_read(env, timeridx, offset);
+}
+
+static void do_tval_write(CPUARMState *env, int timeridx, uint64_t value,
+                          uint64_t offset)
+{
+    trace_arm_gt_tval_write(timeridx, value);
+    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
+                                         sextract64(value, 0, 32);
+    gt_recalc_timer(env_archcpu(env), timeridx);
 }
 
 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
         offset = gt_phys_cnt_offset(env);
         break;
     }
-
-    trace_arm_gt_tval_write(timeridx, value);
-    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
-                                         sextract64(value, 0, 32);
-    gt_recalc_timer(env_archcpu(env), timeridx);
+    do_tval_write(env, timeridx, value, offset);
 }
 
 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    return gt_tval_read(env, ri, GTIMER_VIRT);
+    /*
+     * This is CNTV_TVAL_EL02; unlike the underlying CNTV_TVAL_EL0
+     * we always apply CNTVOFF_EL2. Special case that here rather
+     * than going into the generic gt_tval_read() and then having
+     * to re-detect that it's this register.
+     * Note that the accessfn/perms mean we know we're at EL2 or EL3 here.
+     */
+    return do_tval_read(env, GTIMER_VIRT, env->cp15.cntvoff_el2);
 }
 
 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value)
 {
-    gt_tval_write(env, ri, GTIMER_VIRT, value);
+    /* Similarly for writes to CNTV_TVAL_EL02 */
+    do_tval_write(env, GTIMER_VIRT, value, env->cp15.cntvoff_el2);
 }
 
 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.43.0

When reading or writing the timer registers, sometimes we need to
apply one of the timer offsets.  Specifically, this happens for
direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and
their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0).  It
also applies for direct reads and writes of the CNT*_TVAL_EL*
registers that provide the 32-bit downcounting view of each timer.

We currently do this with duplicated code in gt_tval_read() and
gt_tval_write() and a special-case in gt_virt_cnt_read() and
gt_cnt_read().  Refactor this so that we handle it all in a single
function gt_direct_access_timer_offset(), to parallel how we handle
the offset for indirect accesses.

The call in the WFIT helper previously to gt_virt_cnt_offset() is
now to gt_direct_access_timer_offset(); this is the correct
behaviour, but it's not immediately obvious that it shouldn't be
considered an indirect access, so we add an explanatory comment.

This commit should make no behavioural changes.

(Cc to stable because the following bugfix commit will
depend on this one.)

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250204125009.2281315-6-peter.maydell@linaro.org
---
 target/arm/internals.h     |   5 +-
 target/arm/helper.c        | 103 +++++++++++++++++++------------------
 target/arm/tcg/op_helper.c |   8 ++-
 3 files changed, 62 insertions(+), 54 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type);
 uint64_t gt_get_countervalue(CPUARMState *env);
 /*
  * Return the currently applicable offset between the system counter
- * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2).
+ * and the counter for the specified timer, as used for direct register
+ * accesses.
  */
-uint64_t gt_virt_cnt_offset(CPUARMState *env);
+uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx);
 
 /*
  * Return mask of ARMMMUIdxBit values corresponding to an "invalidate
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
     return 0;
 }
 
-static uint64_t gt_phys_cnt_offset(CPUARMState *env)
-{
-    if (arm_current_el(env) >= 2) {
-        return 0;
-    }
-    return gt_phys_raw_cnt_offset(env);
-}
-
 static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
     }
 }
 
+uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx)
+{
+    /*
+     * Return the timer offset to use for direct accesses to the
+     * counter registers CNTPCT and CNTVCT, and for direct accesses
+     * to the CNT*_TVAL registers.
+     *
+     * This isn't exactly the same as the indirect-access offset,
+     * because here we also care about what EL the register access
+     * is being made from.
+     *
+     * This corresponds to the access pseudocode for the registers.
+     */
+    uint64_t hcr;
+
+    switch (timeridx) {
+    case GTIMER_PHYS:
+        if (arm_current_el(env) >= 2) {
+            return 0;
+        }
+        return gt_phys_raw_cnt_offset(env);
+    case GTIMER_VIRT:
+        switch (arm_current_el(env)) {
+        case 2:
+            hcr = arm_hcr_el2_eff(env);
+            if (hcr & HCR_E2H) {
+                return 0;
+            }
+            break;
+        case 0:
+            hcr = arm_hcr_el2_eff(env);
+            if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+                return 0;
+            }
+            break;
+        }
+        return env->cp15.cntvoff_el2;
+    case GTIMER_HYP:
+    case GTIMER_SEC:
+    case GTIMER_HYPVIRT:
+        return 0;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 {
     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
 
 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
-}
-
-uint64_t gt_virt_cnt_offset(CPUARMState *env)
-{
-    uint64_t hcr;
-
-    switch (arm_current_el(env)) {
-    case 2:
-        hcr = arm_hcr_el2_eff(env);
-        if (hcr & HCR_E2H) {
-            return 0;
-        }
-        break;
-    case 0:
-        hcr = arm_hcr_el2_eff(env);
-        if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
-            return 0;
-        }
-        break;
-    }
-
-    return env->cp15.cntvoff_el2;
+    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_PHYS);
+    return gt_get_countervalue(env) - offset;
 }
 
 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
+    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);
+    return gt_get_countervalue(env) - offset;
 }
 
 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset)
 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
                              int timeridx)
 {
-    uint64_t offset = 0;
-
-    switch (timeridx) {
-    case GTIMER_VIRT:
-        offset = gt_virt_cnt_offset(env);
-        break;
-    case GTIMER_PHYS:
-        offset = gt_phys_cnt_offset(env);
-        break;
-    }
+    uint64_t offset = gt_direct_access_timer_offset(env, timeridx);
 
     return do_tval_read(env, timeridx, offset);
 }
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                           int timeridx,
                           uint64_t value)
 {
-    uint64_t offset = 0;
+    uint64_t offset = gt_direct_access_timer_offset(env, timeridx);
 
-    switch (timeridx) {
-    case GTIMER_VIRT:
-        offset = gt_virt_cnt_offset(env);
-        break;
-    case GTIMER_PHYS:
-        offset = gt_phys_cnt_offset(env);
-        break;
-    }
     do_tval_write(env, timeridx, value, offset);
 }
 
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout)
     int target_el = check_wfx_trap(env, false, &excp);
     /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */
     uint64_t cntval = gt_get_countervalue(env);
-    uint64_t offset = gt_virt_cnt_offset(env);
+    /*
+     * We want the value that we would get if we read CNTVCT_EL0 from
+     * the current exception level, so the direct_access offset, not
+     * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(),
+     * which calls VirtualCounterTimer().
+     */
+    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);
     uint64_t cntvct = cntval - offset;
     uint64_t nexttick;
 
-- 
2.43.0

From: Alex Bennée <alex.bennee@linaro.org>

When FEAT_SEL2 was implemented the SEL2 timers were missed. This
shows up when building the latest Hafnium with SPMC_AT_EL=2. The
actual implementation utilises the same logic as the rest of the
timers so all we need to do is:

- define the timers and their access functions
  - conditionally add the correct system registers
  - create a new accessfn as the rules are subtly different to the
    existing secure timer

Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-7-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Cc: Andrei Homescu <ahomescu@google.com>
Cc: Arve Hjønnevåg <arve@google.com>
Cc: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
[PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED;
 offset logic now in gt_{indirect,direct}_access_timer_offset() ]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bsa.h |   2 +
 target/arm/cpu.h     |   2 +
 target/arm/gtimer.h  |   4 +-
 target/arm/cpu.c     |   4 ++
 target/arm/helper.c  | 163 +++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 174 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bsa.h
+++ b/include/hw/arm/bsa.h
@@ -XXX,XX +XXX,XX @@
 #define QEMU_ARM_BSA_H
 
 /* These are architectural INTID values */
+#define ARCH_TIMER_S_EL2_VIRT_IRQ  19
+#define ARCH_TIMER_S_EL2_IRQ       20
 #define VIRTUAL_PMU_IRQ            23
 #define ARCH_GIC_MAINT_IRQ         25
 #define ARCH_TIMER_NS_EL2_IRQ      26
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_gt_vtimer_cb(void *opaque);
 void arm_gt_htimer_cb(void *opaque);
 void arm_gt_stimer_cb(void *opaque);
 void arm_gt_hvtimer_cb(void *opaque);
+void arm_gt_sel2timer_cb(void *opaque);
+void arm_gt_sel2vtimer_cb(void *opaque);
 
 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gtimer.h
+++ b/target/arm/gtimer.h
@@ -XXX,XX +XXX,XX @@ enum {
     GTIMER_HYP      = 2,
     GTIMER_SEC      = 3,
     GTIMER_HYPVIRT  = 4,
-#define NUM_GTIMERS   5
+    GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */
+    GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */
+#define NUM_GTIMERS   7
 };
 
 #endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                                               arm_gt_stimer_cb, cpu);
         cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
                                                   arm_gt_hvtimer_cb, cpu);
+        cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                                     arm_gt_sel2timer_cb, cpu);
+        cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                                     arm_gt_sel2vtimer_cb, cpu);
     }
 #endif
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
     }
 }
 
+static CPAccessResult gt_sel2timer_access(CPUARMState *env,
+                                          const ARMCPRegInfo *ri,
+                                          bool isread)
+{
+    /*
+     * The AArch64 register view of the secure EL2 timers are mostly
+     * accessible from EL3 and EL2 although can also be trapped to EL2
+     * from EL1 depending on nested virt config.
+     */
+    switch (arm_current_el(env)) {
+    case 0: /* UNDEFINED */
+        return CP_ACCESS_UNDEFINED;
+    case 1:
+        if (!arm_is_secure(env)) {
+            /* UNDEFINED */
+            return CP_ACCESS_UNDEFINED;
+        } else if (arm_hcr_el2_eff(env) & HCR_NV) {
+            /* Aarch64.SystemAccessTrap(EL2, 0x18) */
+            return CP_ACCESS_TRAP_EL2;
+        }
+        /* UNDEFINED */
+        return CP_ACCESS_UNDEFINED;
+    case 2:
+        if (!arm_is_secure(env)) {
+            /* UNDEFINED */
+            return CP_ACCESS_UNDEFINED;
+        }
+        return CP_ACCESS_OK;
+    case 3:
+        if (env->cp15.scr_el3 & SCR_EEL2) {
+            return CP_ACCESS_OK;
+        } else {
+            return CP_ACCESS_UNDEFINED;
+        }
+    default:
+        g_assert_not_reached();
+    }
+}
+
 uint64_t gt_get_countervalue(CPUARMState *env)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
     case GTIMER_HYP:
     case GTIMER_SEC:
     case GTIMER_HYPVIRT:
+    case GTIMER_S_EL2_PHYS:
+    case GTIMER_S_EL2_VIRT:
         return 0;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx)
     case GTIMER_HYP:
     case GTIMER_SEC:
     case GTIMER_HYPVIRT:
+    case GTIMER_S_EL2_PHYS:
+    case GTIMER_S_EL2_VIRT:
         return 0;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
     gt_ctl_write(env, ri, GTIMER_SEC, value);
 }
 
+static void gt_sec_pel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    gt_timer_reset(env, ri, GTIMER_S_EL2_PHYS);
+}
+
+static void gt_sec_pel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                   uint64_t value)
+{
+    gt_cval_write(env, ri, GTIMER_S_EL2_PHYS, value);
+}
+
+static uint64_t gt_sec_pel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return gt_tval_read(env, ri, GTIMER_S_EL2_PHYS);
+}
+
+static void gt_sec_pel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    gt_tval_write(env, ri, GTIMER_S_EL2_PHYS, value);
+}
+
+static void gt_sec_pel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    gt_ctl_write(env, ri, GTIMER_S_EL2_PHYS, value);
+}
+
+static void gt_sec_vel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    gt_timer_reset(env, ri, GTIMER_S_EL2_VIRT);
+}
+
+static void gt_sec_vel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    gt_cval_write(env, ri, GTIMER_S_EL2_VIRT, value);
+}
+
+static uint64_t gt_sec_vel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return gt_tval_read(env, ri, GTIMER_S_EL2_VIRT);
+}
+
+static void gt_sec_vel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                   uint64_t value)
+{
+    gt_tval_write(env, ri, GTIMER_S_EL2_VIRT, value);
+}
+
+static void gt_sec_vel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    gt_ctl_write(env, ri, GTIMER_S_EL2_VIRT, value);
+}
+
 static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     gt_timer_reset(env, ri, GTIMER_HYPVIRT);
@@ -XXX,XX +XXX,XX @@ void arm_gt_stimer_cb(void *opaque)
     gt_recalc_timer(cpu, GTIMER_SEC);
 }
 
+void arm_gt_sel2timer_cb(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+
+    gt_recalc_timer(cpu, GTIMER_S_EL2_PHYS);
+}
+
+void arm_gt_sel2vtimer_cb(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+
+    gt_recalc_timer(cpu, GTIMER_S_EL2_VIRT);
+}
+
 void arm_gt_hvtimer_cb(void *opaque)
 {
     ARMCPU *cpu = opaque;
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
       .access = PL2_RW, .accessfn = sel2_access,
       .nv2_redirect_offset = 0x48,
       .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
+#ifndef CONFIG_USER_ONLY
+    /* Secure EL2 Physical Timer */
+    { .name = "CNTHPS_TVAL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .readfn = gt_sec_pel2_tval_read,
+      .writefn = gt_sec_pel2_tval_write,
+      .resetfn = gt_sec_pel2_timer_reset,
+    },
+    { .name = "CNTHPS_CTL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 1,
+      .type = ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].ctl),
+      .resetvalue = 0,
+      .writefn = gt_sec_pel2_ctl_write, .raw_writefn = raw_write,
+    },
+    { .name = "CNTHPS_CVAL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 2,
+      .type = ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].cval),
+      .writefn = gt_sec_pel2_cval_write, .raw_writefn = raw_write,
+    },
+    /* Secure EL2 Virtual Timer */
+    { .name = "CNTHVS_TVAL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .readfn = gt_sec_vel2_tval_read,
+      .writefn = gt_sec_vel2_tval_write,
+      .resetfn = gt_sec_vel2_timer_reset,
+    },
+    { .name = "CNTHVS_CTL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 1,
+      .type = ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].ctl),
+      .resetvalue = 0,
+      .writefn = gt_sec_vel2_ctl_write, .raw_writefn = raw_write,
+    },
+    { .name = "CNTHVS_CVAL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 2,
+      .type = ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].cval),
+      .writefn = gt_sec_vel2_cval_write, .raw_writefn = raw_write,
+    },
+#endif
 };
 
 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.43.0

From: Alex Bennée <alex.bennee@linaro.org>

As we are about to add more physical and virtual timers let's make it
clear what each timer does.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-8-peter.maydell@linaro.org
[PMM: Add timer register name prefix to each comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gtimer.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gtimer.h
+++ b/target/arm/gtimer.h
@@ -XXX,XX +XXX,XX @@
 #define TARGET_ARM_GTIMER_H
 
 enum {
-    GTIMER_PHYS     = 0,
-    GTIMER_VIRT     = 1,
-    GTIMER_HYP      = 2,
-    GTIMER_SEC      = 3,
-    GTIMER_HYPVIRT  = 4,
+    GTIMER_PHYS     = 0, /* CNTP_* ; EL1 physical timer */
+    GTIMER_VIRT     = 1, /* CNTV_* ; EL1 virtual timer */
+    GTIMER_HYP      = 2, /* CNTHP_* ; EL2 physical timer */
+    GTIMER_SEC      = 3, /* CNTPS_* ; EL3 physical timer */
+    GTIMER_HYPVIRT  = 4, /* CNTHV_* ; EL2 virtual timer ; only if FEAT_VHE */
     GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */
     GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */
 #define NUM_GTIMERS   7
-- 
2.43.0

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-9-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
             [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
+            [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
+            [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
         };
 
         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
-- 
2.43.0

Our LDRD implementation is wrong in two respects:

* if the address is 4-aligned and the load crosses a page boundary
   and the second load faults and the first load was to the
   base register (as in cases like "ldrd r2, r3, [r2]", then we
   must not update the base register before taking the fault
 * if the address is 8-aligned the access must be a 64-bit
   single-copy atomic access, not two 32-bit accesses

Rewrite the handling of the loads in LDRD to use a single
tcg_gen_qemu_ld_i64() and split the result into the destination
registers. This allows us to get the atomicity requirements
right, and also implicitly means that we won't update the
base register too early for the page-crossing case.

Note that because we no longer increment 'addr' by 4 in the course of
performing the LDRD we must change the adjustment value we pass to
op_addr_ri_post() and op_addr_rr_post(): it no longer needs to
subtract 4 to get the correct value to use if doing base register
writeback.

STRD has the same problem with not getting the atomicity right;
we will deal with that in the following commit.

Cc: qemu-stable@nongnu.org
Reported-by: Stu Grossman <stu.grossman@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250227142746.1698904-2-peter.maydell@linaro.org
---
 target/arm/tcg/translate.c | 70 +++++++++++++++++++++++++-------------
 1 file changed, 46 insertions(+), 24 deletions(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
     return true;
 }
 
+static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
+{
+    /*
+     * LDRD is required to be an atomic 64-bit access if the
+     * address is 8-aligned, two atomic 32-bit accesses if
+     * it's only 4-aligned, and to give an alignment fault
+     * if it's not 4-aligned. This is MO_ALIGN_4 | MO_ATOM_SUBALIGN.
+     * Rt is always the word from the lower address, and Rt2 the
+     * data from the higher address, regardless of endianness.
+     * So (like gen_load_exclusive) we avoid gen_aa32_ld_i64()
+     * so we don't get its SCTLR_B check, and instead do a 64-bit access
+     * using MO_BE if appropriate and then split the two halves.
+     *
+     * For M-profile, and for A-profile before LPAE, the 64-bit
+     * atomicity is not required. We could model that using
+     * the looser MO_ATOM_IFALIGN_PAIR, but providing a higher
+     * level of atomicity than required is harmless (we would not
+     * currently generate better code for IFALIGN_PAIR here).
+     *
+     * This also gives us the correct behaviour of not updating
+     * rt if the load of rt2 faults; this is required for cases
+     * like "ldrd r2, r3, [r2]" where rt is also the base register.
+     */
+    int mem_idx = get_mem_index(s);
+    MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
+    TCGv taddr = gen_aa32_addr(s, addr, opc);
+    TCGv_i64 t64 = tcg_temp_new_i64();
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 tmp2 = tcg_temp_new_i32();
+
+    tcg_gen_qemu_ld_i64(t64, taddr, mem_idx, opc);
+    if (s->be_data == MO_BE) {
+        tcg_gen_extr_i64_i32(tmp2, tmp, t64);
+    } else {
+        tcg_gen_extr_i64_i32(tmp, tmp2, t64);
+    }
+    store_reg(s, rt, tmp);
+    store_reg(s, rt2, tmp2);
+}
+
 static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
 {
-    int mem_idx = get_mem_index(s);
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     if (!ENABLE_ARCH_5TE) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     }
     addr = op_addr_rr_pre(s, a);
 
-    tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-    store_reg(s, a->rt, tmp);
-
-    tcg_gen_addi_i32(addr, addr, 4);
-
-    tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-    store_reg(s, a->rt + 1, tmp);
+    do_ldrd_load(s, addr, a->rt, a->rt + 1);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
-    op_addr_rr_post(s, a, addr, -4);
+    op_addr_rr_post(s, a, addr, 0);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
 
 static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
 {
-    int mem_idx = get_mem_index(s);
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     addr = op_addr_ri_pre(s, a);
 
-    tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-    store_reg(s, a->rt, tmp);
-
-    tcg_gen_addi_i32(addr, addr, 4);
-
-    tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-    store_reg(s, rt2, tmp);
+    do_ldrd_load(s, addr, a->rt, rt2);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
-    op_addr_ri_post(s, a, addr, -4);
+    op_addr_ri_post(s, a, addr, 0);
     return true;
 }
 
-- 
2.43.0

Our STRD implementation doesn't correctly implement the requirement:
 * if the address is 8-aligned the access must be a 64-bit
   single-copy atomic access, not two 32-bit accesses

Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64()
of a value produced by concatenating the two 32 bit source registers.
This allows us to get the atomicity right.

As with the LDRD change, now that we don't update 'addr' in the
course of performing the store we need to adjust the offset
we pass to op_addr_ri_post() and op_addr_rr_post().

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250227142746.1698904-3-peter.maydell@linaro.org
---
 target/arm/tcg/translate.c | 59 +++++++++++++++++++++++++-------------
 1 file changed, 39 insertions(+), 20 deletions(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     return true;
 }
 
+static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
+{
+    /*
+     * STRD is required to be an atomic 64-bit access if the
+     * address is 8-aligned, two atomic 32-bit accesses if
+     * it's only 4-aligned, and to give an alignment fault
+     * if it's not 4-aligned.
+     * Rt is always the word from the lower address, and Rt2 the
+     * data from the higher address, regardless of endianness.
+     * So (like gen_store_exclusive) we avoid gen_aa32_ld_i64()
+     * so we don't get its SCTLR_B check, and instead do a 64-bit access
+     * using MO_BE if appropriate, using a value constructed
+     * by putting the two halves together in the right order.
+     *
+     * As with LDRD, the 64-bit atomicity is not required for
+     * M-profile, or for A-profile before LPAE, and we provide
+     * the higher guarantee always for simplicity.
+     */
+    int mem_idx = get_mem_index(s);
+    MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
+    TCGv taddr = gen_aa32_addr(s, addr, opc);
+    TCGv_i32 t1 = load_reg(s, rt);
+    TCGv_i32 t2 = load_reg(s, rt2);
+    TCGv_i64 t64 = tcg_temp_new_i64();
+
+    if (s->be_data == MO_BE) {
+        tcg_gen_concat_i32_i64(t64, t2, t1);
+    } else {
+        tcg_gen_concat_i32_i64(t64, t1, t2);
+    }
+    tcg_gen_qemu_st_i64(t64, taddr, mem_idx, opc);
+}
+
 static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
 {
-    int mem_idx = get_mem_index(s);
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     if (!ENABLE_ARCH_5TE) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
     }
     addr = op_addr_rr_pre(s, a);
 
-    tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+    do_strd_store(s, addr, a->rt, a->rt + 1);
 
-    tcg_gen_addi_i32(addr, addr, 4);
-
-    tmp = load_reg(s, a->rt + 1);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-
-    op_addr_rr_post(s, a, addr, -4);
+    op_addr_rr_post(s, a, addr, 0);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a)
 
 static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
 {
-    int mem_idx = get_mem_index(s);
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     addr = op_addr_ri_pre(s, a);
 
-    tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+    do_strd_store(s, addr, a->rt, rt2);
 
-    tcg_gen_addi_i32(addr, addr, 4);
-
-    tmp = load_reg(s, rt2);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-
-    op_addr_ri_post(s, a, addr, -4);
+    op_addr_ri_post(s, a, addr, 0);
     return true;
 }
 
-- 
2.43.0

All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in
zero for the address_offset, so we can remove that argument.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250227142746.1698904-4-peter.maydell@linaro.org
---
 target/arm/tcg/translate.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a)
 }
 
 static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
-                            TCGv_i32 addr, int address_offset)
+                            TCGv_i32 addr)
 {
     if (!a->p) {
         TCGv_i32 ofs = load_reg(s, a->rm);
@@ -XXX,XX +XXX,XX @@ static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
     } else if (!a->w) {
         return;
     }
-    tcg_gen_addi_i32(addr, addr, address_offset);
     store_reg(s, a->rn, addr);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a,
      * Perform base writeback before the loaded value to
      * ensure correct behavior with overlapping index registers.
      */
-    op_addr_rr_post(s, a, addr, 0);
+    op_addr_rr_post(s, a, addr);
     store_reg_from_load(s, a->rt, tmp);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
     gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
     disas_set_da_iss(s, mop, issinfo);
 
-    op_addr_rr_post(s, a, addr, 0);
+    op_addr_rr_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     do_ldrd_load(s, addr, a->rt, a->rt + 1);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
-    op_addr_rr_post(s, a, addr, 0);
+    op_addr_rr_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
 
     do_strd_store(s, addr, a->rt, a->rt + 1);
 
-    op_addr_rr_post(s, a, addr, 0);
+    op_addr_rr_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a)
 }
 
 static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a,
-                            TCGv_i32 addr, int address_offset)
+                            TCGv_i32 addr)
 {
+    int address_offset = 0;
     if (!a->p) {
         if (a->u) {
-            address_offset += a->imm;
+            address_offset = a->imm;
         } else {
-            address_offset -= a->imm;
+            address_offset = -a->imm;
         }
     } else if (!a->w) {
         return;
@@ -XXX,XX +XXX,XX @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a,
      * Perform base writeback before the loaded value to
      * ensure correct behavior with overlapping index registers.
      */
-    op_addr_ri_post(s, a, addr, 0);
+    op_addr_ri_post(s, a, addr);
     store_reg_from_load(s, a->rt, tmp);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
     gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
     disas_set_da_iss(s, mop, issinfo);
 
-    op_addr_ri_post(s, a, addr, 0);
+    op_addr_ri_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     do_ldrd_load(s, addr, a->rt, rt2);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
-    op_addr_ri_post(s, a, addr, 0);
+    op_addr_ri_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
 
     do_strd_store(s, addr, a->rt, rt2);
 
-    op_addr_ri_post(s, a, addr, 0);
+    op_addr_ri_post(s, a, addr);
     return true;
 }
 
-- 
2.43.0

In debug_helper.c we provide a few dummy versions of
debug registers:
 * DBGVCR (AArch32 only): enable bits for vector-catch
   debug events
 * MDCCINT_EL1: interrupt enable bits for the DCC
   debug communications channel
 * DBGVCR32_EL2: the AArch64 accessor for the state in
   DBGVCR

We implemented these only to stop Linux crashing on startup,
but we chose to implement them as ARM_CP_NOP. This worked
for Linux where it only cares about trying to write to these
registers, but is very confusing behaviour for anything that
wants to read the registers (perhaps for context state switches),
because the destination register will be left with whatever
random value it happened to have before the read.

Model these registers instead as RAZ.

Fixes: 5e8b12ffbb8c68 ("target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0")
Fixes: 5dbdc4342f479d ("target-arm: Implement dummy MDCCINT_EL1")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2708
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250228162424.1917269-1-peter.maydell@linaro.org
---
 target/arm/debug_helper.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "DBGVCR",
       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tda,
-      .type = ARM_CP_NOP },
+      .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * Dummy MDCCINT_EL1, since we don't implement the Debug Communications
      * Channel but Linux may try to access this register. The 32-bit
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tdcc,
-      .type = ARM_CP_NOP },
+      .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * Dummy DBGCLAIM registers.
      * "The architecture does not define any functionality for the CLAIM tag bits.",
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_aa32_el1_reginfo[] = {
     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .accessfn = access_dbgvcr32,
-      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
+      .type = ARM_CP_CONST | ARM_CP_EL3_NO_EL2_KEEP,
+      .resetvalue = 0 },
 };
 
 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
-- 
2.43.0

Currently we call icount_start_warp_timer() from timerlist_rearm().
This produces incorrect behaviour, because timerlist_rearm() is
called, for instance, when a timer callback modifies its timer.  We
cannot decide here to warp the timer forwards to the next timer
deadline merely because all_cpu_threads_idle() is true, because the
timer callback we were called from (or some other callback later in
the list of callbacks being invoked) may be about to raise a CPU
interrupt and move a CPU from idle to ready.

The only valid place to choose to warp the timer forward is from the
main loop, when we know we have no outstanding IO or timer callbacks
that might be about to wake up a CPU.

For Arm guests, this bug was mostly latent until the refactoring
commit f6fc36deef6abc ("target/arm/helper: Implement
CNTHCTL_EL2.CNT[VP]MASK"), which exposed it because it refactored a
timer callback so that it happened to call timer_mod() first and
raise the interrupt second, when it had previously raised the
interrupt first and called timer_mod() afterwards.

This call seems to have originally derived from the
pre-record-and-replay icount code, which (as of e.g.  commit
db1a49726c3c in 2010) in this location did a call to
qemu_notify_event(), necessary to get the icount code in the vCPU
round-robin thread to stop and recalculate the icount deadline when a
timer was reprogrammed from the IO thread.  In current QEMU,
everything is done on the vCPU thread when we are in icount mode, so
there's no need to try to notify another thread here.

I suspect that the other reason why this call was doing icount timer
warping is that it pre-dates commit efab87cf79077a from 2015, which
added a call to icount_start_warp_timer() to main_loop_wait().  Once
the call in timerlist_rearm() has been removed, if the timer
callbacks don't cause any CPU to be woken up then we will end up
calling icount_start_warp_timer() from main_loop_wait() when the rr
main loop code calls rr_wait_io_event().

Remove the incorrect call from timerlist_rearm().

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2703
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250210135804.3526943-1-peter.maydell@linaro.org
---
 util/qemu-timer.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/util/qemu-timer.c b/util/qemu-timer.c
index XXXXXXX..XXXXXXX 100644
--- a/util/qemu-timer.c
+++ b/util/qemu-timer.c
@@ -XXX,XX +XXX,XX @@ static bool timer_mod_ns_locked(QEMUTimerList *timer_list,
 
 static void timerlist_rearm(QEMUTimerList *timer_list)
 {
-    /* Interrupt execution to force deadline recalculation.  */
-    if (icount_enabled() && timer_list->clock->type == QEMU_CLOCK_VIRTUAL) {
-        icount_start_warp_timer();
-    }
     timerlist_notify(timer_list);
 }
 
-- 
2.43.0

Expand the example in the comment documenting MO_ATOM_SUBALIGN,
to be clearer about the atomicity guarantees it represents.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250228103222.1838913-1-peter.maydell@linaro.org
---
 include/exec/memop.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/exec/memop.h b/include/exec/memop.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -XXX,XX +XXX,XX @@ typedef enum MemOp {
      *    Depending on alignment, one or both will be single-copy atomic.
      *    This is the atomicity e.g. of Arm FEAT_LSE2 LDP.
      * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts
-     *    by the alignment.  E.g. if the address is 0 mod 4, then each
-     *    4-byte subobject is single-copy atomic.
+     *    by the alignment.  E.g. if an 8-byte value is accessed at an
+     *    address which is 0 mod 8, then the whole 8-byte access is
+     *    single-copy atomic; otherwise, if it is accessed at 0 mod 4
+     *    then each 4-byte subobject is single-copy atomic; otherwise
+     *    if it is accessed at 0 mod 2 then the four 2-byte subobjects
+     *    are single-copy atomic.
      *    This is the atomicity e.g. of IBM Power.
      * MO_ATOM_NONE: the operation has no atomicity requirements.
      *
-- 
2.43.0

From: JianChunfu <jansef.jian@hj-micro.com>

Use a similar terminology smmu_hash_remove_by_sid_range() as the one
being used for other hash table matching functions since
smmuv3_invalidate_ste() name is not self explanatory, and introduce a
helper that invokes the g_hash_table_foreach_remove.

No functional change intended.

Signed-off-by: JianChunfu <jansef.jian@hj-micro.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20250228031438.3916-1-jansef.jian@hj-micro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmu-internal.h       |  5 -----
 include/hw/arm/smmu-common.h |  6 ++++++
 hw/arm/smmu-common.c         | 21 +++++++++++++++++++++
 hw/arm/smmuv3.c              | 19 ++-----------------
 hw/arm/trace-events          |  3 ++-
 5 files changed, 31 insertions(+), 23 deletions(-)

diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-internal.h
+++ b/hw/arm/smmu-internal.h
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBPageInvInfo {
     uint64_t mask;
 } SMMUIOTLBPageInvInfo;
 
-typedef struct SMMUSIDRange {
-    uint32_t start;
-    uint32_t end;
-} SMMUSIDRange;
-
 #endif
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBKey {
     uint8_t level;
 } SMMUIOTLBKey;
 
+typedef struct SMMUSIDRange {
+    uint32_t start;
+    uint32_t end;
+} SMMUSIDRange;
+
 struct SMMUState {
     /* <private> */
     SysBusDevice  dev;
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
                          uint8_t tg, uint64_t num_pages, uint8_t ttl);
 void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg,
                         uint64_t num_pages, uint8_t ttl);
+void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range);
 /* Unmap the range of all the notifiers registered to any IOMMU mr */
 void smmu_inv_notifiers_all(SMMUState *s);
 
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_vmid_ipa(gpointer key, gpointer value,
            ((entry->iova & ~info->mask) == info->iova);
 }
 
+static gboolean
+smmu_hash_remove_by_sid_range(gpointer key, gpointer value, gpointer user_data)
+{
+    SMMUDevice *sdev = (SMMUDevice *)key;
+    uint32_t sid = smmu_get_sid(sdev);
+    SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
+
+    if (sid < sid_range->start || sid > sid_range->end) {
+        return false;
+    }
+    trace_smmu_config_cache_inv(sid);
+    return true;
+}
+
+void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range)
+{
+    trace_smmu_configs_inv_sid_range(sid_range.start, sid_range.end);
+    g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_range,
+                                &sid_range);
+}
+
 void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
                          uint8_t tg, uint64_t num_pages, uint8_t ttl)
 {
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmuv3_flush_config(SMMUDevice *sdev)
     SMMUv3State *s = sdev->smmu;
     SMMUState *bc = &s->smmu_state;
 
-    trace_smmuv3_config_cache_inv(smmu_get_sid(sdev));
+    trace_smmu_config_cache_inv(smmu_get_sid(sdev));
     g_hash_table_remove(bc->configs, sdev);
 }
 
@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage)
     }
 }
 
-static gboolean
-smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
-{
-    SMMUDevice *sdev = (SMMUDevice *)key;
-    uint32_t sid = smmu_get_sid(sdev);
-    SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
-
-    if (sid < sid_range->start || sid > sid_range->end) {
-        return false;
-    }
-    trace_smmuv3_config_cache_inv(sid);
-    return true;
-}
-
 static int smmuv3_cmdq_consume(SMMUv3State *s)
 {
     SMMUState *bs = ARM_SMMU(s);
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
             sid_range.end = sid_range.start + mask;
 
             trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
-            g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
-                                        &sid_range);
+            smmu_configs_inv_sid_range(bs, sid_range);
             break;
         }
         case SMMU_CMD_CFGI_CD:
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=%d vmid=%d"
 smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=%d"
 smmu_iotlb_inv_vmid_s1(int vmid) "IOTLB invalidate vmid=%d"
 smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
+smmu_configs_inv_sid_range(uint32_t start, uint32_t end) "Config cache INV SID range from 0x%x to 0x%x"
+smmu_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
 smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
 smmu_iotlb_lookup_hit(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
 smmu_iotlb_lookup_miss(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_tlbi_nh(int vmid) "vmid=%d"
 smmuv3_cmdq_tlbi_nsnh(void) ""
 smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d"
 smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d"
-smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
 smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
 smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
 smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d"
-- 
2.43.0

From: Keith Packard <keithp@keithp.com>

The documentation says the vector is at 0xffffff80, instead of the
previous value of 0xffffffc0. That value must have been a bug because
the standard vector values (20, 21, 23, 25, 30) were all
past the end of the array.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/rx/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/rx/helper.c b/target/rx/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -XXX,XX +XXX,XX @@ void rx_cpu_do_interrupt(CPUState *cs)
         cpu_stl_data(env, env->isp, env->pc);
 
         if (vec < 0x100) {
-            env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4);
+            env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4);
         } else {
             env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4);
         }
-- 
2.43.0

From: Keith Packard <keithp@keithp.com>

Functions which modify TCG globals must not be marked TCG_CALL_NO_WG,
as that tells the optimizer that TCG global values already loaded in
machine registers are still valid, and so any changes which these
helpers make to the CPU state may be ignored.

The target/rx code chooses to put (among other things) all the PSW
bits and also ACC into globals, so the NO_WG flag on various
functions that touch the PSW or ACC is incorrect and must be removed.
This includes all the floating point helper functions, because
update_fpsw() will update PSW Z and S.

Signed-off-by: Keith Packard <keithp@keithp.com>
[PMM: Clarified commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/rx/helper.h | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/target/rx/helper.h b/target/rx/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/helper.h
+++ b/target/rx/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_privilege_violation, noreturn, env)
 DEF_HELPER_1(wait, noreturn, env)
 DEF_HELPER_2(rxint, noreturn, env, i32)
 DEF_HELPER_1(rxbrk, noreturn, env)
-DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
-DEF_HELPER_FLAGS_3(fsub, TCG_CALL_NO_WG, f32, env, f32, f32)
-DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, f32, env, f32, f32)
-DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32)
-DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_WG, void, env, f32, f32)
-DEF_HELPER_FLAGS_2(ftoi, TCG_CALL_NO_WG, i32, env, f32)
-DEF_HELPER_FLAGS_2(round, TCG_CALL_NO_WG, i32, env, f32)
-DEF_HELPER_FLAGS_2(itof, TCG_CALL_NO_WG, f32, env, i32)
+DEF_HELPER_3(fadd, f32, env, f32, f32)
+DEF_HELPER_3(fsub, f32, env, f32, f32)
+DEF_HELPER_3(fmul, f32, env, f32, f32)
+DEF_HELPER_3(fdiv, f32, env, f32, f32)
+DEF_HELPER_3(fcmp, void, env, f32, f32)
+DEF_HELPER_2(ftoi, i32, env, f32)
+DEF_HELPER_2(round, i32, env, f32)
+DEF_HELPER_2(itof, f32, env, i32)
 DEF_HELPER_2(set_fpsw, void, env, i32)
-DEF_HELPER_FLAGS_2(racw, TCG_CALL_NO_WG, void, env, i32)
-DEF_HELPER_FLAGS_2(set_psw_rte, TCG_CALL_NO_WG, void, env, i32)
-DEF_HELPER_FLAGS_2(set_psw, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_2(racw, void, env, i32)
+DEF_HELPER_2(set_psw_rte, void, env, i32)
+DEF_HELPER_2(set_psw, void, env, i32)
 DEF_HELPER_1(pack_psw, i32, env)
-DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32)
-DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
-DEF_HELPER_FLAGS_1(scmpu, TCG_CALL_NO_WG, void, env)
+DEF_HELPER_3(div, i32, env, i32, i32)
+DEF_HELPER_3(divu, i32, env, i32, i32)
+DEF_HELPER_1(scmpu, void, env)
 DEF_HELPER_1(smovu, void, env)
 DEF_HELPER_1(smovf, void, env)
 DEF_HELPER_1(smovb, void, env)
 DEF_HELPER_2(sstr, void, env, i32)
-DEF_HELPER_FLAGS_2(swhile, TCG_CALL_NO_WG, void, env, i32)
-DEF_HELPER_FLAGS_2(suntil, TCG_CALL_NO_WG, void, env, i32)
-DEF_HELPER_FLAGS_2(rmpa, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_2(swhile, void, env, i32)
+DEF_HELPER_2(suntil, void, env, i32)
+DEF_HELPER_2(rmpa, void, env, i32)
 DEF_HELPER_1(satr, void, env)
-- 
2.43.0