1 | target-arm queue: the big stuff here is the final part of | 1 | First arm pullreq of the cycle; this is mostly my softfloat NaN |
---|---|---|---|
2 | rth's patches for Cortex-A76 and Neoverse-N1 support; | 2 | handling series. (Lots more in my to-review queue, but I don't |
3 | also present are Gavin's NUMA series and a few other things. | 3 | like pullreqs growing too close to a hundred patches at a time :-)) |
4 | 4 | ||
5 | thanks | 5 | thanks |
6 | -- PMM | 6 | -- PMM |
7 | 7 | ||
8 | The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b: | 8 | The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17: |
9 | 9 | ||
10 | Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500) | 10 | Open 10.0 development tree (2024-12-10 17:41:17 +0000) |
11 | 11 | ||
12 | are available in the Git repository at: | 12 | are available in the Git repository at: |
13 | 13 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211 |
15 | 15 | ||
16 | for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34: | 16 | for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8: |
17 | 17 | ||
18 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100) | 18 | MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000) |
19 | 19 | ||
20 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
21 | target-arm queue: | 21 | target-arm queue: |
22 | * MAINTAINERS/.mailmap: update email for Leif Lindholm | 22 | * hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs |
23 | * hw/arm: add version information to sbsa-ref machine DT | 23 | * fpu: Make muladd NaN handling runtime-selected, not compile-time |
24 | * Enable new features for -cpu max: | 24 | * fpu: Make default NaN pattern runtime-selected, not compile-time |
25 | FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only), | 25 | * fpu: Minor NaN-related cleanups |
26 | FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH | 26 | * MAINTAINERS: email address updates |
27 | * Emulate Cortex-A76 | ||
28 | * Emulate Neoverse-N1 | ||
29 | * Fix the virt board default NUMA topology | ||
30 | 27 | ||
31 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
32 | Gavin Shan (6): | 29 | Bernhard Beschow (5): |
33 | qapi/machine.json: Add cluster-id | 30 | hw/net/lan9118: Extract lan9118_phy |
34 | qtest/numa-test: Specify CPU topology in aarch64_numa_cpu() | 31 | hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations |
35 | hw/arm/virt: Consider SMP configuration in CPU topology | 32 | hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register |
36 | qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu() | 33 | hw/net/lan9118_phy: Reuse MII constants |
37 | hw/arm/virt: Fix CPU's default NUMA node ID | 34 | hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement |
38 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table | ||
39 | 35 | ||
40 | Leif Lindholm (2): | 36 | Leif Lindholm (1): |
41 | MAINTAINERS/.mailmap: update email for Leif Lindholm | 37 | MAINTAINERS: update email address for Leif Lindholm |
42 | hw/arm: add versioning to sbsa-ref machine DT | ||
43 | 38 | ||
44 | Richard Henderson (24): | 39 | Peter Maydell (54): |
45 | target/arm: Handle cpreg registration for missing EL | 40 | fpu: handle raising Invalid for infzero in pick_nan_muladd |
46 | target/arm: Drop EL3 no EL2 fallbacks | 41 | fpu: Check for default_nan_mode before calling pickNaNMulAdd |
47 | target/arm: Merge zcr reginfo | 42 | softfloat: Allow runtime choice of inf * 0 + NaN result |
48 | target/arm: Adjust definition of CONTEXTIDR_EL2 | 43 | tests/fp: Explicitly set inf-zero-nan rule |
49 | target/arm: Move cortex impdef sysregs to cpu_tcg.c | 44 | target/arm: Set FloatInfZeroNaNRule explicitly |
50 | target/arm: Update qemu-system-arm -cpu max to cortex-a57 | 45 | target/s390: Set FloatInfZeroNaNRule explicitly |
51 | target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max | 46 | target/ppc: Set FloatInfZeroNaNRule explicitly |
52 | target/arm: Split out aa32_max_features | 47 | target/mips: Set FloatInfZeroNaNRule explicitly |
53 | target/arm: Annotate arm_max_initfn with FEAT identifiers | 48 | target/sparc: Set FloatInfZeroNaNRule explicitly |
54 | target/arm: Use field names for manipulating EL2 and EL3 modes | 49 | target/xtensa: Set FloatInfZeroNaNRule explicitly |
55 | target/arm: Enable FEAT_Debugv8p2 for -cpu max | 50 | target/x86: Set FloatInfZeroNaNRule explicitly |
56 | target/arm: Enable FEAT_Debugv8p4 for -cpu max | 51 | target/loongarch: Set FloatInfZeroNaNRule explicitly |
57 | target/arm: Add minimal RAS registers | 52 | target/hppa: Set FloatInfZeroNaNRule explicitly |
58 | target/arm: Enable SCR and HCR bits for RAS | 53 | softfloat: Pass have_snan to pickNaNMulAdd |
59 | target/arm: Implement virtual SError exceptions | 54 | softfloat: Allow runtime choice of NaN propagation for muladd |
60 | target/arm: Implement ESB instruction | 55 | tests/fp: Explicitly set 3-NaN propagation rule |
61 | target/arm: Enable FEAT_RAS for -cpu max | 56 | target/arm: Set Float3NaNPropRule explicitly |
62 | target/arm: Enable FEAT_IESB for -cpu max | 57 | target/loongarch: Set Float3NaNPropRule explicitly |
63 | target/arm: Enable FEAT_CSV2 for -cpu max | 58 | target/ppc: Set Float3NaNPropRule explicitly |
64 | target/arm: Enable FEAT_CSV2_2 for -cpu max | 59 | target/s390x: Set Float3NaNPropRule explicitly |
65 | target/arm: Enable FEAT_CSV3 for -cpu max | 60 | target/sparc: Set Float3NaNPropRule explicitly |
66 | target/arm: Enable FEAT_DGH for -cpu max | 61 | target/mips: Set Float3NaNPropRule explicitly |
67 | target/arm: Define cortex-a76 | 62 | target/xtensa: Set Float3NaNPropRule explicitly |
68 | target/arm: Define neoverse-n1 | 63 | target/i386: Set Float3NaNPropRule explicitly |
64 | target/hppa: Set Float3NaNPropRule explicitly | ||
65 | fpu: Remove use_first_nan field from float_status | ||
66 | target/m68k: Don't pass NULL float_status to floatx80_default_nan() | ||
67 | softfloat: Create floatx80 default NaN from parts64_default_nan | ||
68 | target/loongarch: Use normal float_status in fclass_s and fclass_d helpers | ||
69 | target/m68k: In frem helper, initialize local float_status from env->fp_status | ||
70 | target/m68k: Init local float_status from env fp_status in gdb get/set reg | ||
71 | target/sparc: Initialize local scratch float_status from env->fp_status | ||
72 | target/ppc: Use env->fp_status in helper_compute_fprf functions | ||
73 | fpu: Allow runtime choice of default NaN value | ||
74 | tests/fp: Set default NaN pattern explicitly | ||
75 | target/microblaze: Set default NaN pattern explicitly | ||
76 | target/i386: Set default NaN pattern explicitly | ||
77 | target/hppa: Set default NaN pattern explicitly | ||
78 | target/alpha: Set default NaN pattern explicitly | ||
79 | target/arm: Set default NaN pattern explicitly | ||
80 | target/loongarch: Set default NaN pattern explicitly | ||
81 | target/m68k: Set default NaN pattern explicitly | ||
82 | target/mips: Set default NaN pattern explicitly | ||
83 | target/openrisc: Set default NaN pattern explicitly | ||
84 | target/ppc: Set default NaN pattern explicitly | ||
85 | target/sh4: Set default NaN pattern explicitly | ||
86 | target/rx: Set default NaN pattern explicitly | ||
87 | target/s390x: Set default NaN pattern explicitly | ||
88 | target/sparc: Set default NaN pattern explicitly | ||
89 | target/xtensa: Set default NaN pattern explicitly | ||
90 | target/hexagon: Set default NaN pattern explicitly | ||
91 | target/riscv: Set default NaN pattern explicitly | ||
92 | target/tricore: Set default NaN pattern explicitly | ||
93 | fpu: Remove default handling for dnan_pattern | ||
69 | 94 | ||
70 | docs/system/arm/emulation.rst | 10 + | 95 | Richard Henderson (11): |
71 | docs/system/arm/virt.rst | 2 + | 96 | target/arm: Copy entire float_status in is_ebf |
72 | qapi/machine.json | 6 +- | 97 | softfloat: Inline pickNaNMulAdd |
73 | target/arm/cpregs.h | 11 + | 98 | softfloat: Use goto for default nan case in pick_nan_muladd |
74 | target/arm/cpu.h | 23 ++ | 99 | softfloat: Remove which from parts_pick_nan_muladd |
75 | target/arm/helper.h | 1 + | 100 | softfloat: Pad array size in pick_nan_muladd |
76 | target/arm/internals.h | 16 ++ | 101 | softfloat: Move propagateFloatx80NaN to softfloat.c |
77 | target/arm/syndrome.h | 5 + | 102 | softfloat: Use parts_pick_nan in propagateFloatx80NaN |
78 | target/arm/a32.decode | 16 +- | 103 | softfloat: Inline pickNaN |
79 | target/arm/t32.decode | 18 +- | 104 | softfloat: Share code between parts_pick_nan cases |
80 | hw/acpi/aml-build.c | 111 ++++---- | 105 | softfloat: Sink frac_cmp in parts_pick_nan until needed |
81 | hw/arm/sbsa-ref.c | 16 ++ | 106 | softfloat: Replace WHICH with RET in parts_pick_nan |
82 | hw/arm/virt.c | 21 +- | 107 | |
83 | hw/core/machine-hmp-cmds.c | 4 + | 108 | Vikram Garhwal (1): |
84 | hw/core/machine.c | 16 ++ | 109 | MAINTAINERS: Add correct email address for Vikram Garhwal |
85 | target/arm/cpu.c | 66 ++++- | 110 | |
86 | target/arm/cpu64.c | 353 ++++++++++++++----------- | 111 | MAINTAINERS | 4 +- |
87 | target/arm/cpu_tcg.c | 227 +++++++++++----- | 112 | include/fpu/softfloat-helpers.h | 38 +++- |
88 | target/arm/helper.c | 600 +++++++++++++++++++++++++----------------- | 113 | include/fpu/softfloat-types.h | 89 +++++++- |
89 | target/arm/op_helper.c | 43 +++ | 114 | include/hw/net/imx_fec.h | 9 +- |
90 | target/arm/translate-a64.c | 18 ++ | 115 | include/hw/net/lan9118_phy.h | 37 ++++ |
91 | target/arm/translate.c | 23 ++ | 116 | include/hw/net/mii.h | 6 + |
92 | tests/qtest/numa-test.c | 19 +- | 117 | target/mips/fpu_helper.h | 20 ++ |
93 | .mailmap | 3 +- | 118 | target/sparc/helper.h | 4 +- |
94 | MAINTAINERS | 2 +- | 119 | fpu/softfloat.c | 19 ++ |
95 | 25 files changed, 1068 insertions(+), 562 deletions(-) | 120 | hw/net/imx_fec.c | 146 ++------------ |
121 | hw/net/lan9118.c | 137 ++----------- | ||
122 | hw/net/lan9118_phy.c | 222 ++++++++++++++++++++ | ||
123 | linux-user/arm/nwfpe/fpa11.c | 5 + | ||
124 | target/alpha/cpu.c | 2 + | ||
125 | target/arm/cpu.c | 10 + | ||
126 | target/arm/tcg/vec_helper.c | 20 +- | ||
127 | target/hexagon/cpu.c | 2 + | ||
128 | target/hppa/fpu_helper.c | 12 ++ | ||
129 | target/i386/tcg/fpu_helper.c | 12 ++ | ||
130 | target/loongarch/tcg/fpu_helper.c | 14 +- | ||
131 | target/m68k/cpu.c | 14 +- | ||
132 | target/m68k/fpu_helper.c | 6 +- | ||
133 | target/m68k/helper.c | 6 +- | ||
134 | target/microblaze/cpu.c | 2 + | ||
135 | target/mips/msa.c | 10 + | ||
136 | target/openrisc/cpu.c | 2 + | ||
137 | target/ppc/cpu_init.c | 19 ++ | ||
138 | target/ppc/fpu_helper.c | 3 +- | ||
139 | target/riscv/cpu.c | 2 + | ||
140 | target/rx/cpu.c | 2 + | ||
141 | target/s390x/cpu.c | 5 + | ||
142 | target/sh4/cpu.c | 2 + | ||
143 | target/sparc/cpu.c | 6 + | ||
144 | target/sparc/fop_helper.c | 8 +- | ||
145 | target/sparc/translate.c | 4 +- | ||
146 | target/tricore/helper.c | 2 + | ||
147 | target/xtensa/cpu.c | 4 + | ||
148 | target/xtensa/fpu_helper.c | 3 +- | ||
149 | tests/fp/fp-bench.c | 7 + | ||
150 | tests/fp/fp-test-log2.c | 1 + | ||
151 | tests/fp/fp-test.c | 7 + | ||
152 | fpu/softfloat-parts.c.inc | 152 +++++++++++--- | ||
153 | fpu/softfloat-specialize.c.inc | 412 ++------------------------------------ | ||
154 | .mailmap | 5 +- | ||
155 | hw/net/Kconfig | 5 + | ||
156 | hw/net/meson.build | 1 + | ||
157 | hw/net/trace-events | 10 +- | ||
158 | 47 files changed, 778 insertions(+), 730 deletions(-) | ||
159 | create mode 100644 include/hw/net/lan9118_phy.h | ||
160 | create mode 100644 hw/net/lan9118_phy.c | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Virtual SError exceptions are raised by setting HCR_EL2.VSE, | 3 | A very similar implementation of the same device exists in imx_fec. Prepare for |
4 | and are routed to EL1 just like other virtual exceptions. | 4 | a common implementation by extracting a device model into its own files. |
5 | 5 | ||
6 | Some migration state has been moved into the new device model which breaks | ||
7 | migration compatibility for the following machines: | ||
8 | * smdkc210 | ||
9 | * realview-* | ||
10 | * vexpress-* | ||
11 | * kzm | ||
12 | * mps2-* | ||
13 | |||
14 | While breaking migration ABI, fix the size of the MII registers to be 16 bit, | ||
15 | as defined by IEEE 802.3u. | ||
16 | |||
17 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
18 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 20 | Message-id: 20241102125724.532843-2-shentey@gmail.com |
8 | Message-id: 20220506180242.216785-16-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 22 | --- |
11 | target/arm/cpu.h | 2 ++ | 23 | include/hw/net/lan9118_phy.h | 37 ++++++++ |
12 | target/arm/internals.h | 8 ++++++++ | 24 | hw/net/lan9118.c | 137 +++++----------------------- |
13 | target/arm/syndrome.h | 5 +++++ | 25 | hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++ |
14 | target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- | 26 | hw/net/Kconfig | 4 + |
15 | target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- | 27 | hw/net/meson.build | 1 + |
16 | 5 files changed, 91 insertions(+), 2 deletions(-) | 28 | 5 files changed, 233 insertions(+), 115 deletions(-) |
29 | create mode 100644 include/hw/net/lan9118_phy.h | ||
30 | create mode 100644 hw/net/lan9118_phy.c | ||
17 | 31 | ||
18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 32 | diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h |
33 | new file mode 100644 | ||
34 | index XXXXXXX..XXXXXXX | ||
35 | --- /dev/null | ||
36 | +++ b/include/hw/net/lan9118_phy.h | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | +/* | ||
39 | + * SMSC LAN9118 PHY emulation | ||
40 | + * | ||
41 | + * Copyright (c) 2009 CodeSourcery, LLC. | ||
42 | + * Written by Paul Brook | ||
43 | + * | ||
44 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
45 | + * See the COPYING file in the top-level directory. | ||
46 | + */ | ||
47 | + | ||
48 | +#ifndef HW_NET_LAN9118_PHY_H | ||
49 | +#define HW_NET_LAN9118_PHY_H | ||
50 | + | ||
51 | +#include "qom/object.h" | ||
52 | +#include "hw/sysbus.h" | ||
53 | + | ||
54 | +#define TYPE_LAN9118_PHY "lan9118-phy" | ||
55 | +OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY) | ||
56 | + | ||
57 | +typedef struct Lan9118PhyState { | ||
58 | + SysBusDevice parent_obj; | ||
59 | + | ||
60 | + uint16_t status; | ||
61 | + uint16_t control; | ||
62 | + uint16_t advertise; | ||
63 | + uint16_t ints; | ||
64 | + uint16_t int_mask; | ||
65 | + qemu_irq irq; | ||
66 | + bool link_down; | ||
67 | +} Lan9118PhyState; | ||
68 | + | ||
69 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down); | ||
70 | +void lan9118_phy_reset(Lan9118PhyState *s); | ||
71 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg); | ||
72 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val); | ||
73 | + | ||
74 | +#endif | ||
75 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | 76 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/cpu.h | 77 | --- a/hw/net/lan9118.c |
21 | +++ b/target/arm/cpu.h | 78 | +++ b/hw/net/lan9118.c |
22 | @@ -XXX,XX +XXX,XX @@ | 79 | @@ -XXX,XX +XXX,XX @@ |
23 | #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ | 80 | #include "net/net.h" |
24 | #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ | 81 | #include "net/eth.h" |
25 | #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ | 82 | #include "hw/irq.h" |
26 | +#define EXCP_VSERR 24 | 83 | +#include "hw/net/lan9118_phy.h" |
27 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ | 84 | #include "hw/net/lan9118.h" |
28 | 85 | #include "hw/ptimer.h" | |
29 | #define ARMV7M_EXCP_RESET 1 | 86 | #include "hw/qdev-properties.h" |
30 | @@ -XXX,XX +XXX,XX @@ enum { | 87 | @@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) |
31 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | 88 | #define MAC_CR_RXEN 0x00000004 |
32 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 | 89 | #define MAC_CR_RESERVED 0x7f404213 |
33 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 | 90 | |
34 | +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 | 91 | -#define PHY_INT_ENERGYON 0x80 |
35 | 92 | -#define PHY_INT_AUTONEG_COMPLETE 0x40 | |
36 | /* The usual mapping for an AArch64 system register to its AArch32 | 93 | -#define PHY_INT_FAULT 0x20 |
37 | * counterpart is for the 32 bit world to have access to the lower | 94 | -#define PHY_INT_DOWN 0x10 |
38 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 95 | -#define PHY_INT_AUTONEG_LP 0x08 |
39 | index XXXXXXX..XXXXXXX 100644 | 96 | -#define PHY_INT_PARFAULT 0x04 |
40 | --- a/target/arm/internals.h | 97 | -#define PHY_INT_AUTONEG_PAGE 0x02 |
41 | +++ b/target/arm/internals.h | 98 | - |
42 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu); | 99 | #define GPT_TIMER_EN 0x20000000 |
43 | */ | 100 | |
44 | void arm_cpu_update_vfiq(ARMCPU *cpu); | 101 | /* |
45 | 102 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | |
46 | +/** | 103 | uint32_t mac_mii_data; |
47 | + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit | 104 | uint32_t mac_flow; |
48 | + * | 105 | |
49 | + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, | 106 | - uint32_t phy_status; |
50 | + * following a change to the HCR_EL2.VSE bit. | 107 | - uint32_t phy_control; |
51 | + */ | 108 | - uint32_t phy_advertise; |
52 | +void arm_cpu_update_vserr(ARMCPU *cpu); | 109 | - uint32_t phy_int; |
53 | + | 110 | - uint32_t phy_int_mask; |
54 | /** | 111 | + Lan9118PhyState mii; |
55 | * arm_mmu_idx_el: | 112 | + IRQState mii_irq; |
56 | * @env: The cpu environment | 113 | |
57 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h | 114 | int32_t eeprom_writable; |
58 | index XXXXXXX..XXXXXXX 100644 | 115 | uint8_t eeprom[128]; |
59 | --- a/target/arm/syndrome.h | 116 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { |
60 | +++ b/target/arm/syndrome.h | 117 | |
61 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void) | 118 | static const VMStateDescription vmstate_lan9118 = { |
62 | return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; | 119 | .name = "lan9118", |
120 | - .version_id = 2, | ||
121 | - .minimum_version_id = 1, | ||
122 | + .version_id = 3, | ||
123 | + .minimum_version_id = 3, | ||
124 | .fields = (const VMStateField[]) { | ||
125 | VMSTATE_PTIMER(timer, lan9118_state), | ||
126 | VMSTATE_UINT32(irq_cfg, lan9118_state), | ||
127 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = { | ||
128 | VMSTATE_UINT32(mac_mii_acc, lan9118_state), | ||
129 | VMSTATE_UINT32(mac_mii_data, lan9118_state), | ||
130 | VMSTATE_UINT32(mac_flow, lan9118_state), | ||
131 | - VMSTATE_UINT32(phy_status, lan9118_state), | ||
132 | - VMSTATE_UINT32(phy_control, lan9118_state), | ||
133 | - VMSTATE_UINT32(phy_advertise, lan9118_state), | ||
134 | - VMSTATE_UINT32(phy_int, lan9118_state), | ||
135 | - VMSTATE_UINT32(phy_int_mask, lan9118_state), | ||
136 | VMSTATE_INT32(eeprom_writable, lan9118_state), | ||
137 | VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), | ||
138 | VMSTATE_INT32(tx_fifo_size, lan9118_state), | ||
139 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s) | ||
140 | lan9118_mac_changed(s); | ||
63 | } | 141 | } |
64 | 142 | ||
65 | +static inline uint32_t syn_serror(uint32_t extra) | 143 | -static void phy_update_irq(lan9118_state *s) |
66 | +{ | 144 | +static void lan9118_update_irq(void *opaque, int n, int level) |
67 | + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; | 145 | { |
68 | +} | 146 | - if (s->phy_int & s->phy_int_mask) { |
69 | + | 147 | + lan9118_state *s = opaque; |
70 | #endif /* TARGET_ARM_SYNDROME_H */ | 148 | + |
71 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 149 | + if (level) { |
72 | index XXXXXXX..XXXXXXX 100644 | 150 | s->int_sts |= PHY_INT; |
73 | --- a/target/arm/cpu.c | 151 | } else { |
74 | +++ b/target/arm/cpu.c | 152 | s->int_sts &= ~PHY_INT; |
75 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs) | 153 | @@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s) |
76 | return (cpu->power_state != PSCI_OFF) | 154 | lan9118_update(s); |
77 | && cs->interrupt_request & | ||
78 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | ||
79 | - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | ||
80 | + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | ||
81 | | CPU_INTERRUPT_EXITTB); | ||
82 | } | 155 | } |
83 | 156 | ||
84 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | 157 | -static void phy_update_link(lan9118_state *s) |
85 | return false; | 158 | -{ |
86 | } | 159 | - /* Autonegotiation status mirrors link status. */ |
87 | return !(env->daif & PSTATE_I); | 160 | - if (qemu_get_queue(s->nic)->link_down) { |
88 | + case EXCP_VSERR: | 161 | - s->phy_status &= ~0x0024; |
89 | + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { | 162 | - s->phy_int |= PHY_INT_DOWN; |
90 | + /* VIRQs are only taken when hypervized. */ | 163 | - } else { |
91 | + return false; | 164 | - s->phy_status |= 0x0024; |
92 | + } | 165 | - s->phy_int |= PHY_INT_ENERGYON; |
93 | + return !(env->daif & PSTATE_A); | 166 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; |
94 | default: | 167 | - } |
95 | g_assert_not_reached(); | 168 | - phy_update_irq(s); |
96 | } | 169 | -} |
97 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | 170 | - |
98 | goto found; | 171 | static void lan9118_set_link(NetClientState *nc) |
99 | } | 172 | { |
100 | } | 173 | - phy_update_link(qemu_get_nic_opaque(nc)); |
101 | + if (interrupt_request & CPU_INTERRUPT_VSERR) { | 174 | -} |
102 | + excp_idx = EXCP_VSERR; | 175 | - |
103 | + target_el = 1; | 176 | -static void phy_reset(lan9118_state *s) |
104 | + if (arm_excp_unmasked(cs, excp_idx, target_el, | 177 | -{ |
105 | + cur_el, secure, hcr_el2)) { | 178 | - s->phy_status = 0x7809; |
106 | + /* Taking a virtual abort clears HCR_EL2.VSE */ | 179 | - s->phy_control = 0x3000; |
107 | + env->cp15.hcr_el2 &= ~HCR_VSE; | 180 | - s->phy_advertise = 0x01e1; |
108 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | 181 | - s->phy_int_mask = 0; |
109 | + goto found; | 182 | - s->phy_int = 0; |
110 | + } | 183 | - phy_update_link(s); |
111 | + } | 184 | + lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii, |
112 | return false; | 185 | + nc->link_down); |
113 | 186 | } | |
114 | found: | 187 | |
115 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu) | 188 | static void lan9118_reset(DeviceState *d) |
189 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d) | ||
190 | s->read_word_n = 0; | ||
191 | s->write_word_n = 0; | ||
192 | |||
193 | - phy_reset(s); | ||
194 | - | ||
195 | s->eeprom_writable = 0; | ||
196 | lan9118_reload_eeprom(s); | ||
197 | } | ||
198 | @@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s) | ||
199 | uint32_t status; | ||
200 | |||
201 | /* FIXME: Honor TX disable, and allow queueing of packets. */ | ||
202 | - if (s->phy_control & 0x4000) { | ||
203 | + if (s->mii.control & 0x4000) { | ||
204 | /* This assumes the receive routine doesn't touch the VLANClient. */ | ||
205 | qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); | ||
206 | } else { | ||
207 | @@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val) | ||
116 | } | 208 | } |
117 | } | 209 | } |
118 | 210 | ||
119 | +void arm_cpu_update_vserr(ARMCPU *cpu) | 211 | -static uint32_t do_phy_read(lan9118_state *s, int reg) |
120 | +{ | 212 | -{ |
121 | + /* | 213 | - uint32_t val; |
122 | + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. | 214 | - |
123 | + */ | 215 | - switch (reg) { |
124 | + CPUARMState *env = &cpu->env; | 216 | - case 0: /* Basic Control */ |
125 | + CPUState *cs = CPU(cpu); | 217 | - return s->phy_control; |
126 | + | 218 | - case 1: /* Basic Status */ |
127 | + bool new_state = env->cp15.hcr_el2 & HCR_VSE; | 219 | - return s->phy_status; |
128 | + | 220 | - case 2: /* ID1 */ |
129 | + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { | 221 | - return 0x0007; |
130 | + if (new_state) { | 222 | - case 3: /* ID2 */ |
131 | + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); | 223 | - return 0xc0d1; |
132 | + } else { | 224 | - case 4: /* Auto-neg advertisement */ |
133 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | 225 | - return s->phy_advertise; |
226 | - case 5: /* Auto-neg Link Partner Ability */ | ||
227 | - return 0x0f71; | ||
228 | - case 6: /* Auto-neg Expansion */ | ||
229 | - return 1; | ||
230 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
231 | - case 29: /* Interrupt source. */ | ||
232 | - val = s->phy_int; | ||
233 | - s->phy_int = 0; | ||
234 | - phy_update_irq(s); | ||
235 | - return val; | ||
236 | - case 30: /* Interrupt mask */ | ||
237 | - return s->phy_int_mask; | ||
238 | - default: | ||
239 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
240 | - "do_phy_read: PHY read reg %d\n", reg); | ||
241 | - return 0; | ||
242 | - } | ||
243 | -} | ||
244 | - | ||
245 | -static void do_phy_write(lan9118_state *s, int reg, uint32_t val) | ||
246 | -{ | ||
247 | - switch (reg) { | ||
248 | - case 0: /* Basic Control */ | ||
249 | - if (val & 0x8000) { | ||
250 | - phy_reset(s); | ||
251 | - break; | ||
252 | - } | ||
253 | - s->phy_control = val & 0x7980; | ||
254 | - /* Complete autonegotiation immediately. */ | ||
255 | - if (val & 0x1000) { | ||
256 | - s->phy_status |= 0x0020; | ||
257 | - } | ||
258 | - break; | ||
259 | - case 4: /* Auto-neg advertisement */ | ||
260 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
261 | - break; | ||
262 | - /* TODO 17, 18, 27, 31 */ | ||
263 | - case 30: /* Interrupt mask */ | ||
264 | - s->phy_int_mask = val & 0xff; | ||
265 | - phy_update_irq(s); | ||
266 | - break; | ||
267 | - default: | ||
268 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
269 | - "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
270 | - } | ||
271 | -} | ||
272 | - | ||
273 | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) | ||
274 | { | ||
275 | switch (reg) { | ||
276 | @@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val) | ||
277 | if (val & 2) { | ||
278 | DPRINTF("PHY write %d = 0x%04x\n", | ||
279 | (val >> 6) & 0x1f, s->mac_mii_data); | ||
280 | - do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); | ||
281 | + lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data); | ||
282 | } else { | ||
283 | - s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); | ||
284 | + s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f); | ||
285 | DPRINTF("PHY read %d = 0x%04x\n", | ||
286 | (val >> 6) & 0x1f, s->mac_mii_data); | ||
287 | } | ||
288 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
289 | break; | ||
290 | case CSR_PMT_CTRL: | ||
291 | if (val & 0x400) { | ||
292 | - phy_reset(s); | ||
293 | + lan9118_phy_reset(&s->mii); | ||
294 | } | ||
295 | s->pmt_ctrl &= ~0x34e; | ||
296 | s->pmt_ctrl |= (val & 0x34e); | ||
297 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
298 | const MemoryRegionOps *mem_ops = | ||
299 | s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; | ||
300 | |||
301 | + qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0); | ||
302 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
303 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
304 | + return; | ||
305 | + } | ||
306 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); | ||
307 | + | ||
308 | memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s, | ||
309 | "lan9118-mmio", 0x100); | ||
310 | sysbus_init_mmio(sbd, &s->mmio); | ||
311 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
312 | new file mode 100644 | ||
313 | index XXXXXXX..XXXXXXX | ||
314 | --- /dev/null | ||
315 | +++ b/hw/net/lan9118_phy.c | ||
316 | @@ -XXX,XX +XXX,XX @@ | ||
317 | +/* | ||
318 | + * SMSC LAN9118 PHY emulation | ||
319 | + * | ||
320 | + * Copyright (c) 2009 CodeSourcery, LLC. | ||
321 | + * Written by Paul Brook | ||
322 | + * | ||
323 | + * This code is licensed under the GNU GPL v2 | ||
324 | + * | ||
325 | + * Contributions after 2012-01-13 are licensed under the terms of the | ||
326 | + * GNU GPL, version 2 or (at your option) any later version. | ||
327 | + */ | ||
328 | + | ||
329 | +#include "qemu/osdep.h" | ||
330 | +#include "hw/net/lan9118_phy.h" | ||
331 | +#include "hw/irq.h" | ||
332 | +#include "hw/resettable.h" | ||
333 | +#include "migration/vmstate.h" | ||
334 | +#include "qemu/log.h" | ||
335 | + | ||
336 | +#define PHY_INT_ENERGYON (1 << 7) | ||
337 | +#define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
338 | +#define PHY_INT_FAULT (1 << 5) | ||
339 | +#define PHY_INT_DOWN (1 << 4) | ||
340 | +#define PHY_INT_AUTONEG_LP (1 << 3) | ||
341 | +#define PHY_INT_PARFAULT (1 << 2) | ||
342 | +#define PHY_INT_AUTONEG_PAGE (1 << 1) | ||
343 | + | ||
344 | +static void lan9118_phy_update_irq(Lan9118PhyState *s) | ||
345 | +{ | ||
346 | + qemu_set_irq(s->irq, !!(s->ints & s->int_mask)); | ||
347 | +} | ||
348 | + | ||
349 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
350 | +{ | ||
351 | + uint16_t val; | ||
352 | + | ||
353 | + switch (reg) { | ||
354 | + case 0: /* Basic Control */ | ||
355 | + return s->control; | ||
356 | + case 1: /* Basic Status */ | ||
357 | + return s->status; | ||
358 | + case 2: /* ID1 */ | ||
359 | + return 0x0007; | ||
360 | + case 3: /* ID2 */ | ||
361 | + return 0xc0d1; | ||
362 | + case 4: /* Auto-neg advertisement */ | ||
363 | + return s->advertise; | ||
364 | + case 5: /* Auto-neg Link Partner Ability */ | ||
365 | + return 0x0f71; | ||
366 | + case 6: /* Auto-neg Expansion */ | ||
367 | + return 1; | ||
368 | + /* TODO 17, 18, 27, 29, 30, 31 */ | ||
369 | + case 29: /* Interrupt source. */ | ||
370 | + val = s->ints; | ||
371 | + s->ints = 0; | ||
372 | + lan9118_phy_update_irq(s); | ||
373 | + return val; | ||
374 | + case 30: /* Interrupt mask */ | ||
375 | + return s->int_mask; | ||
376 | + default: | ||
377 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
378 | + "lan9118_phy_read: PHY read reg %d\n", reg); | ||
379 | + return 0; | ||
380 | + } | ||
381 | +} | ||
382 | + | ||
383 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
384 | +{ | ||
385 | + switch (reg) { | ||
386 | + case 0: /* Basic Control */ | ||
387 | + if (val & 0x8000) { | ||
388 | + lan9118_phy_reset(s); | ||
389 | + break; | ||
134 | + } | 390 | + } |
135 | + } | 391 | + s->control = val & 0x7980; |
136 | +} | 392 | + /* Complete autonegotiation immediately. */ |
137 | + | 393 | + if (val & 0x1000) { |
138 | #ifndef CONFIG_USER_ONLY | 394 | + s->status |= 0x0020; |
139 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | ||
140 | { | ||
141 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/target/arm/helper.c | ||
144 | +++ b/target/arm/helper.c | ||
145 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
146 | } | ||
147 | } | ||
148 | |||
149 | - /* External aborts are not possible in QEMU so A bit is always clear */ | ||
150 | + if (hcr_el2 & HCR_AMO) { | ||
151 | + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { | ||
152 | + ret |= CPSR_A; | ||
153 | + } | ||
154 | + } | ||
155 | + | ||
156 | return ret; | ||
157 | } | ||
158 | |||
159 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
160 | g_assert(qemu_mutex_iothread_locked()); | ||
161 | arm_cpu_update_virq(cpu); | ||
162 | arm_cpu_update_vfiq(cpu); | ||
163 | + arm_cpu_update_vserr(cpu); | ||
164 | } | ||
165 | |||
166 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
167 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs) | ||
168 | [EXCP_LSERR] = "v8M LSERR UsageFault", | ||
169 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | ||
170 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", | ||
171 | + [EXCP_VSERR] = "Virtual SERR", | ||
172 | }; | ||
173 | |||
174 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | ||
175 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) | ||
176 | mask = CPSR_A | CPSR_I | CPSR_F; | ||
177 | offset = 4; | ||
178 | break; | ||
179 | + case EXCP_VSERR: | ||
180 | + { | ||
181 | + /* | ||
182 | + * Note that this is reported as a data abort, but the DFAR | ||
183 | + * has an UNKNOWN value. Construct the SError syndrome from | ||
184 | + * AET and ExT fields. | ||
185 | + */ | ||
186 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; | ||
187 | + | ||
188 | + if (extended_addresses_enabled(env)) { | ||
189 | + env->exception.fsr = arm_fi_to_lfsc(&fi); | ||
190 | + } else { | ||
191 | + env->exception.fsr = arm_fi_to_sfsc(&fi); | ||
192 | + } | ||
193 | + env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; | ||
194 | + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); | ||
195 | + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", | ||
196 | + env->exception.fsr); | ||
197 | + | ||
198 | + new_mode = ARM_CPU_MODE_ABT; | ||
199 | + addr = 0x10; | ||
200 | + mask = CPSR_A | CPSR_I; | ||
201 | + offset = 8; | ||
202 | + } | 395 | + } |
203 | + break; | 396 | + break; |
204 | case EXCP_SMC: | 397 | + case 4: /* Auto-neg advertisement */ |
205 | new_mode = ARM_CPU_MODE_MON; | 398 | + s->advertise = (val & 0x2d7f) | 0x80; |
206 | addr = 0x08; | ||
207 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
208 | case EXCP_VFIQ: | ||
209 | addr += 0x100; | ||
210 | break; | ||
211 | + case EXCP_VSERR: | ||
212 | + addr += 0x180; | ||
213 | + /* Construct the SError syndrome from IDS and ISS fields. */ | ||
214 | + env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | ||
215 | + env->cp15.esr_el[new_el] = env->exception.syndrome; | ||
216 | + break; | 399 | + break; |
217 | default: | 400 | + /* TODO 17, 18, 27, 31 */ |
218 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | 401 | + case 30: /* Interrupt mask */ |
219 | } | 402 | + s->int_mask = val & 0xff; |
403 | + lan9118_phy_update_irq(s); | ||
404 | + break; | ||
405 | + default: | ||
406 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
407 | + "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
408 | + } | ||
409 | +} | ||
410 | + | ||
411 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
412 | +{ | ||
413 | + s->link_down = link_down; | ||
414 | + | ||
415 | + /* Autonegotiation status mirrors link status. */ | ||
416 | + if (link_down) { | ||
417 | + s->status &= ~0x0024; | ||
418 | + s->ints |= PHY_INT_DOWN; | ||
419 | + } else { | ||
420 | + s->status |= 0x0024; | ||
421 | + s->ints |= PHY_INT_ENERGYON; | ||
422 | + s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
423 | + } | ||
424 | + lan9118_phy_update_irq(s); | ||
425 | +} | ||
426 | + | ||
427 | +void lan9118_phy_reset(Lan9118PhyState *s) | ||
428 | +{ | ||
429 | + s->control = 0x3000; | ||
430 | + s->status = 0x7809; | ||
431 | + s->advertise = 0x01e1; | ||
432 | + s->int_mask = 0; | ||
433 | + s->ints = 0; | ||
434 | + lan9118_phy_update_link(s, s->link_down); | ||
435 | +} | ||
436 | + | ||
437 | +static void lan9118_phy_reset_hold(Object *obj, ResetType type) | ||
438 | +{ | ||
439 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
440 | + | ||
441 | + lan9118_phy_reset(s); | ||
442 | +} | ||
443 | + | ||
444 | +static void lan9118_phy_init(Object *obj) | ||
445 | +{ | ||
446 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
447 | + | ||
448 | + qdev_init_gpio_out(DEVICE(s), &s->irq, 1); | ||
449 | +} | ||
450 | + | ||
451 | +static const VMStateDescription vmstate_lan9118_phy = { | ||
452 | + .name = "lan9118-phy", | ||
453 | + .version_id = 1, | ||
454 | + .minimum_version_id = 1, | ||
455 | + .fields = (const VMStateField[]) { | ||
456 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
457 | + VMSTATE_UINT16(status, Lan9118PhyState), | ||
458 | + VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
459 | + VMSTATE_UINT16(ints, Lan9118PhyState), | ||
460 | + VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
461 | + VMSTATE_BOOL(link_down, Lan9118PhyState), | ||
462 | + VMSTATE_END_OF_LIST() | ||
463 | + } | ||
464 | +}; | ||
465 | + | ||
466 | +static void lan9118_phy_class_init(ObjectClass *klass, void *data) | ||
467 | +{ | ||
468 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
469 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
470 | + | ||
471 | + rc->phases.hold = lan9118_phy_reset_hold; | ||
472 | + dc->vmsd = &vmstate_lan9118_phy; | ||
473 | +} | ||
474 | + | ||
475 | +static const TypeInfo types[] = { | ||
476 | + { | ||
477 | + .name = TYPE_LAN9118_PHY, | ||
478 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
479 | + .instance_size = sizeof(Lan9118PhyState), | ||
480 | + .instance_init = lan9118_phy_init, | ||
481 | + .class_init = lan9118_phy_class_init, | ||
482 | + } | ||
483 | +}; | ||
484 | + | ||
485 | +DEFINE_TYPES(types) | ||
486 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
487 | index XXXXXXX..XXXXXXX 100644 | ||
488 | --- a/hw/net/Kconfig | ||
489 | +++ b/hw/net/Kconfig | ||
490 | @@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI | ||
491 | config SMC91C111 | ||
492 | bool | ||
493 | |||
494 | +config LAN9118_PHY | ||
495 | + bool | ||
496 | + | ||
497 | config LAN9118 | ||
498 | bool | ||
499 | + select LAN9118_PHY | ||
500 | select PTIMER | ||
501 | |||
502 | config NE2000_ISA | ||
503 | diff --git a/hw/net/meson.build b/hw/net/meson.build | ||
504 | index XXXXXXX..XXXXXXX 100644 | ||
505 | --- a/hw/net/meson.build | ||
506 | +++ b/hw/net/meson.build | ||
507 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c')) | ||
508 | |||
509 | system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c')) | ||
510 | system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c')) | ||
511 | +system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c')) | ||
512 | system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) | ||
513 | system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c')) | ||
514 | system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) | ||
220 | -- | 515 | -- |
221 | 2.25.1 | 516 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local | 3 | imx_fec models the same PHY as lan9118_phy. The code is almost the same with |
4 | vpidr_regs definition, and rely on the squashing to ARM_CP_CONST | 4 | imx_fec having more logging and tracing. Merge these improvements into |
5 | while registering for v8. | 5 | lan9118_phy and reuse in imx_fec to fix the code duplication. |
6 | 6 | ||
7 | This is a behavior change for v7 cpus with Security Extensions and | 7 | Some migration state how resides in the new device model which breaks migration |
8 | without Virtualization Extensions, in that the virtualization cpregs | 8 | compatibility for the following machines: |
9 | are now correctly not present. This would be a migration compatibility | 9 | * imx25-pdk |
10 | break, except that we have an existing bug in which migration of 32-bit | 10 | * sabrelite |
11 | cpus with Security Extensions enabled does not work. | 11 | * mcimx7d-sabre |
12 | * mcimx6ul-evk | ||
12 | 13 | ||
14 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
15 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 17 | Message-id: 20241102125724.532843-3-shentey@gmail.com |
15 | Message-id: 20220506180242.216785-3-richard.henderson@linaro.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 19 | --- |
18 | target/arm/helper.c | 158 ++++---------------------------------------- | 20 | include/hw/net/imx_fec.h | 9 ++- |
19 | 1 file changed, 13 insertions(+), 145 deletions(-) | 21 | hw/net/imx_fec.c | 146 ++++----------------------------------- |
22 | hw/net/lan9118_phy.c | 82 ++++++++++++++++------ | ||
23 | hw/net/Kconfig | 1 + | ||
24 | hw/net/trace-events | 10 +-- | ||
25 | 5 files changed, 85 insertions(+), 163 deletions(-) | ||
20 | 26 | ||
21 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 27 | diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h |
22 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/helper.c | 29 | --- a/include/hw/net/imx_fec.h |
24 | +++ b/target/arm/helper.c | 30 | +++ b/include/hw/net/imx_fec.h |
25 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 31 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC) |
26 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | 32 | #define TYPE_IMX_ENET "imx.enet" |
33 | |||
34 | #include "hw/sysbus.h" | ||
35 | +#include "hw/net/lan9118_phy.h" | ||
36 | +#include "hw/irq.h" | ||
37 | #include "net/net.h" | ||
38 | |||
39 | #define ENET_EIR 1 | ||
40 | @@ -XXX,XX +XXX,XX @@ struct IMXFECState { | ||
41 | uint32_t tx_descriptor[ENET_TX_RING_NUM]; | ||
42 | uint32_t tx_ring_num; | ||
43 | |||
44 | - uint32_t phy_status; | ||
45 | - uint32_t phy_control; | ||
46 | - uint32_t phy_advertise; | ||
47 | - uint32_t phy_int; | ||
48 | - uint32_t phy_int_mask; | ||
49 | + Lan9118PhyState mii; | ||
50 | + IRQState mii_irq; | ||
51 | uint32_t phy_num; | ||
52 | bool phy_connected; | ||
53 | struct IMXFECState *phy_consumer; | ||
54 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/net/imx_fec.c | ||
57 | +++ b/hw/net/imx_fec.c | ||
58 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = { | ||
59 | |||
60 | static const VMStateDescription vmstate_imx_eth = { | ||
61 | .name = TYPE_IMX_FEC, | ||
62 | - .version_id = 2, | ||
63 | - .minimum_version_id = 2, | ||
64 | + .version_id = 3, | ||
65 | + .minimum_version_id = 3, | ||
66 | .fields = (const VMStateField[]) { | ||
67 | VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), | ||
68 | VMSTATE_UINT32(rx_descriptor, IMXFECState), | ||
69 | VMSTATE_UINT32(tx_descriptor[0], IMXFECState), | ||
70 | - VMSTATE_UINT32(phy_status, IMXFECState), | ||
71 | - VMSTATE_UINT32(phy_control, IMXFECState), | ||
72 | - VMSTATE_UINT32(phy_advertise, IMXFECState), | ||
73 | - VMSTATE_UINT32(phy_int, IMXFECState), | ||
74 | - VMSTATE_UINT32(phy_int_mask, IMXFECState), | ||
75 | VMSTATE_END_OF_LIST() | ||
76 | }, | ||
77 | .subsections = (const VMStateDescription * const []) { | ||
78 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = { | ||
79 | }, | ||
27 | }; | 80 | }; |
28 | 81 | ||
29 | -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ | 82 | -#define PHY_INT_ENERGYON (1 << 7) |
30 | -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | 83 | -#define PHY_INT_AUTONEG_COMPLETE (1 << 6) |
31 | - { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, | 84 | -#define PHY_INT_FAULT (1 << 5) |
32 | - .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | 85 | -#define PHY_INT_DOWN (1 << 4) |
33 | - .access = PL2_RW, | 86 | -#define PHY_INT_AUTONEG_LP (1 << 3) |
34 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | 87 | -#define PHY_INT_PARFAULT (1 << 2) |
35 | - { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, | 88 | -#define PHY_INT_AUTONEG_PAGE (1 << 1) |
36 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | 89 | - |
37 | - .access = PL2_RW, | 90 | static void imx_eth_update(IMXFECState *s); |
38 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | 91 | |
39 | - { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, | 92 | /* |
40 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | 93 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s); |
41 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 94 | * For now we don't handle any GPIO/interrupt line, so the OS will |
42 | - { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, | 95 | * have to poll for the PHY status. |
43 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | 96 | */ |
44 | - .access = PL2_RW, | 97 | -static void imx_phy_update_irq(IMXFECState *s) |
45 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | 98 | +static void imx_phy_update_irq(void *opaque, int n, int level) |
46 | - { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
47 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | ||
48 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
49 | - { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, | ||
50 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | ||
51 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
52 | - .resetvalue = 0 }, | ||
53 | - { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | ||
54 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | ||
55 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
56 | - { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, | ||
57 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | ||
58 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
59 | - .resetvalue = 0 }, | ||
60 | - { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, | ||
61 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | ||
62 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
63 | - .resetvalue = 0 }, | ||
64 | - { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, | ||
65 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | ||
66 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
67 | - .resetvalue = 0 }, | ||
68 | - { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | ||
69 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | ||
70 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
71 | - .resetvalue = 0 }, | ||
72 | - { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
73 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | ||
74 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
75 | - { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
76 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | ||
77 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
78 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | - { .name = "VTTBR", .state = ARM_CP_STATE_AA32, | ||
80 | - .cp = 15, .opc1 = 6, .crm = 2, | ||
81 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
82 | - .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
83 | - { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | ||
84 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | ||
85 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
86 | - { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, | ||
87 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | ||
88 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
89 | - { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
90 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | ||
91 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
92 | - { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, | ||
93 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | ||
94 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
95 | - { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | ||
96 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
97 | - .resetvalue = 0 }, | ||
98 | - { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
99 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | ||
100 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
101 | - { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, | ||
102 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | ||
103 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
104 | - { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | ||
105 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
106 | - .resetvalue = 0 }, | ||
107 | - { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, | ||
108 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | ||
109 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
110 | - { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | ||
111 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
112 | - .resetvalue = 0 }, | ||
113 | - { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | ||
114 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | ||
115 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
116 | - { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
117 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | ||
118 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
119 | - { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
120 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | ||
121 | - .access = PL2_RW, .accessfn = access_tda, | ||
122 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
123 | - { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
124 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | ||
125 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
126 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
127 | - { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
128 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | ||
129 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
130 | - { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
131 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | ||
132 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
133 | - { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | ||
134 | - .type = ARM_CP_CONST, | ||
135 | - .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | ||
136 | - .access = PL2_RW, .resetvalue = 0 }, | ||
137 | -}; | ||
138 | - | ||
139 | -/* Ditto, but for registers which exist in ARMv8 but not v7 */ | ||
140 | -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | ||
141 | - { .name = "HCR2", .state = ARM_CP_STATE_AA32, | ||
142 | - .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | ||
143 | - .access = PL2_RW, | ||
144 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
145 | -}; | ||
146 | - | ||
147 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
148 | { | 99 | { |
149 | ARMCPU *cpu = env_archcpu(env); | 100 | - imx_eth_update(s); |
150 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 101 | -} |
151 | define_arm_cp_regs(cpu, v8_idregs); | 102 | - |
152 | define_arm_cp_regs(cpu, v8_cp_reginfo); | 103 | -static void imx_phy_update_link(IMXFECState *s) |
153 | } | 104 | -{ |
154 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | 105 | - /* Autonegotiation status mirrors link status. */ |
155 | + | 106 | - if (qemu_get_queue(s->nic)->link_down) { |
156 | + /* | 107 | - trace_imx_phy_update_link("down"); |
157 | + * Register the base EL2 cpregs. | 108 | - s->phy_status &= ~0x0024; |
158 | + * Pre v8, these registers are implemented only as part of the | 109 | - s->phy_int |= PHY_INT_DOWN; |
159 | + * Virtualization Extensions (EL2 present). Beginning with v8, | ||
160 | + * if EL2 is missing but EL3 is enabled, mostly these become | ||
161 | + * RES0 from EL3, with some specific exceptions. | ||
162 | + */ | ||
163 | + if (arm_feature(env, ARM_FEATURE_EL2) | ||
164 | + || (arm_feature(env, ARM_FEATURE_EL3) | ||
165 | + && arm_feature(env, ARM_FEATURE_V8))) { | ||
166 | uint64_t vmpidr_def = mpidr_read_val(env); | ||
167 | ARMCPRegInfo vpidr_regs[] = { | ||
168 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
169 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
170 | }; | ||
171 | define_one_arm_cp_reg(cpu, &rvbar); | ||
172 | } | ||
173 | - } else { | 110 | - } else { |
174 | - /* If EL2 is missing but higher ELs are enabled, we need to | 111 | - trace_imx_phy_update_link("up"); |
175 | - * register the no_el2 reginfos. | 112 | - s->phy_status |= 0x0024; |
176 | - */ | 113 | - s->phy_int |= PHY_INT_ENERGYON; |
177 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | 114 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; |
178 | - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value | 115 | - } |
179 | - * of MIDR_EL1 and MPIDR_EL1. | 116 | - imx_phy_update_irq(s); |
180 | - */ | 117 | + imx_eth_update(opaque); |
181 | - ARMCPRegInfo vpidr_regs[] = { | 118 | } |
182 | - { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | 119 | |
183 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | 120 | static void imx_eth_set_link(NetClientState *nc) |
184 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | 121 | { |
185 | - .type = ARM_CP_CONST, .resetvalue = cpu->midr, | 122 | - imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); |
186 | - .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | 123 | -} |
187 | - { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, | 124 | - |
188 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | 125 | -static void imx_phy_reset(IMXFECState *s) |
189 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | 126 | -{ |
190 | - .type = ARM_CP_NO_RAW, | 127 | - trace_imx_phy_reset(); |
191 | - .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | 128 | - |
192 | - }; | 129 | - s->phy_status = 0x7809; |
193 | - define_arm_cp_regs(cpu, vpidr_regs); | 130 | - s->phy_control = 0x3000; |
194 | - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); | 131 | - s->phy_advertise = 0x01e1; |
195 | - if (arm_feature(env, ARM_FEATURE_V8)) { | 132 | - s->phy_int_mask = 0; |
196 | - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | 133 | - s->phy_int = 0; |
134 | - imx_phy_update_link(s); | ||
135 | + lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii, | ||
136 | + nc->link_down); | ||
137 | } | ||
138 | |||
139 | static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
140 | { | ||
141 | - uint32_t val; | ||
142 | uint32_t phy = reg / 32; | ||
143 | |||
144 | if (!s->phy_connected) { | ||
145 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
146 | |||
147 | reg %= 32; | ||
148 | |||
149 | - switch (reg) { | ||
150 | - case 0: /* Basic Control */ | ||
151 | - val = s->phy_control; | ||
152 | - break; | ||
153 | - case 1: /* Basic Status */ | ||
154 | - val = s->phy_status; | ||
155 | - break; | ||
156 | - case 2: /* ID1 */ | ||
157 | - val = 0x0007; | ||
158 | - break; | ||
159 | - case 3: /* ID2 */ | ||
160 | - val = 0xc0d1; | ||
161 | - break; | ||
162 | - case 4: /* Auto-neg advertisement */ | ||
163 | - val = s->phy_advertise; | ||
164 | - break; | ||
165 | - case 5: /* Auto-neg Link Partner Ability */ | ||
166 | - val = 0x0f71; | ||
167 | - break; | ||
168 | - case 6: /* Auto-neg Expansion */ | ||
169 | - val = 1; | ||
170 | - break; | ||
171 | - case 29: /* Interrupt source. */ | ||
172 | - val = s->phy_int; | ||
173 | - s->phy_int = 0; | ||
174 | - imx_phy_update_irq(s); | ||
175 | - break; | ||
176 | - case 30: /* Interrupt mask */ | ||
177 | - val = s->phy_int_mask; | ||
178 | - break; | ||
179 | - case 17: | ||
180 | - case 18: | ||
181 | - case 27: | ||
182 | - case 31: | ||
183 | - qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", | ||
184 | - TYPE_IMX_FEC, __func__, reg); | ||
185 | - val = 0; | ||
186 | - break; | ||
187 | - default: | ||
188 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
189 | - TYPE_IMX_FEC, __func__, reg); | ||
190 | - val = 0; | ||
191 | - break; | ||
192 | - } | ||
193 | - | ||
194 | - trace_imx_phy_read(val, phy, reg); | ||
195 | - | ||
196 | - return val; | ||
197 | + return lan9118_phy_read(&s->mii, reg); | ||
198 | } | ||
199 | |||
200 | static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
201 | @@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
202 | |||
203 | reg %= 32; | ||
204 | |||
205 | - trace_imx_phy_write(val, phy, reg); | ||
206 | - | ||
207 | - switch (reg) { | ||
208 | - case 0: /* Basic Control */ | ||
209 | - if (val & 0x8000) { | ||
210 | - imx_phy_reset(s); | ||
211 | - } else { | ||
212 | - s->phy_control = val & 0x7980; | ||
213 | - /* Complete autonegotiation immediately. */ | ||
214 | - if (val & 0x1000) { | ||
215 | - s->phy_status |= 0x0020; | ||
197 | - } | 216 | - } |
198 | - } | 217 | - } |
218 | - break; | ||
219 | - case 4: /* Auto-neg advertisement */ | ||
220 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
221 | - break; | ||
222 | - case 30: /* Interrupt mask */ | ||
223 | - s->phy_int_mask = val & 0xff; | ||
224 | - imx_phy_update_irq(s); | ||
225 | - break; | ||
226 | - case 17: | ||
227 | - case 18: | ||
228 | - case 27: | ||
229 | - case 31: | ||
230 | - qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", | ||
231 | - TYPE_IMX_FEC, __func__, reg); | ||
232 | - break; | ||
233 | - default: | ||
234 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
235 | - TYPE_IMX_FEC, __func__, reg); | ||
236 | - break; | ||
237 | - } | ||
238 | + lan9118_phy_write(&s->mii, reg, val); | ||
239 | } | ||
240 | |||
241 | static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) | ||
242 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d) | ||
243 | |||
244 | s->rx_descriptor = 0; | ||
245 | memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); | ||
246 | - | ||
247 | - /* We also reset the PHY */ | ||
248 | - imx_phy_reset(s); | ||
249 | } | ||
250 | |||
251 | static uint32_t imx_default_read(IMXFECState *s, uint32_t index) | ||
252 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp) | ||
253 | sysbus_init_irq(sbd, &s->irq[0]); | ||
254 | sysbus_init_irq(sbd, &s->irq[1]); | ||
255 | |||
256 | + qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0); | ||
257 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
258 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
259 | + return; | ||
260 | + } | ||
261 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); | ||
262 | + | ||
263 | qemu_macaddr_default_if_unset(&s->conf.macaddr); | ||
264 | |||
265 | s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, | ||
266 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
267 | index XXXXXXX..XXXXXXX 100644 | ||
268 | --- a/hw/net/lan9118_phy.c | ||
269 | +++ b/hw/net/lan9118_phy.c | ||
270 | @@ -XXX,XX +XXX,XX @@ | ||
271 | * Copyright (c) 2009 CodeSourcery, LLC. | ||
272 | * Written by Paul Brook | ||
273 | * | ||
274 | + * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> | ||
275 | + * | ||
276 | * This code is licensed under the GNU GPL v2 | ||
277 | * | ||
278 | * Contributions after 2012-01-13 are licensed under the terms of the | ||
279 | @@ -XXX,XX +XXX,XX @@ | ||
280 | #include "hw/resettable.h" | ||
281 | #include "migration/vmstate.h" | ||
282 | #include "qemu/log.h" | ||
283 | +#include "trace.h" | ||
284 | |||
285 | #define PHY_INT_ENERGYON (1 << 7) | ||
286 | #define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
287 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
288 | |||
289 | switch (reg) { | ||
290 | case 0: /* Basic Control */ | ||
291 | - return s->control; | ||
292 | + val = s->control; | ||
293 | + break; | ||
294 | case 1: /* Basic Status */ | ||
295 | - return s->status; | ||
296 | + val = s->status; | ||
297 | + break; | ||
298 | case 2: /* ID1 */ | ||
299 | - return 0x0007; | ||
300 | + val = 0x0007; | ||
301 | + break; | ||
302 | case 3: /* ID2 */ | ||
303 | - return 0xc0d1; | ||
304 | + val = 0xc0d1; | ||
305 | + break; | ||
306 | case 4: /* Auto-neg advertisement */ | ||
307 | - return s->advertise; | ||
308 | + val = s->advertise; | ||
309 | + break; | ||
310 | case 5: /* Auto-neg Link Partner Ability */ | ||
311 | - return 0x0f71; | ||
312 | + val = 0x0f71; | ||
313 | + break; | ||
314 | case 6: /* Auto-neg Expansion */ | ||
315 | - return 1; | ||
316 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
317 | + val = 1; | ||
318 | + break; | ||
319 | case 29: /* Interrupt source. */ | ||
320 | val = s->ints; | ||
321 | s->ints = 0; | ||
322 | lan9118_phy_update_irq(s); | ||
323 | - return val; | ||
324 | + break; | ||
325 | case 30: /* Interrupt mask */ | ||
326 | - return s->int_mask; | ||
327 | + val = s->int_mask; | ||
328 | + break; | ||
329 | + case 17: | ||
330 | + case 18: | ||
331 | + case 27: | ||
332 | + case 31: | ||
333 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
334 | + __func__, reg); | ||
335 | + val = 0; | ||
336 | + break; | ||
337 | default: | ||
338 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
339 | - "lan9118_phy_read: PHY read reg %d\n", reg); | ||
340 | - return 0; | ||
341 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
342 | + __func__, reg); | ||
343 | + val = 0; | ||
344 | + break; | ||
199 | } | 345 | } |
200 | + | 346 | + |
201 | + /* Register the base EL3 cpregs. */ | 347 | + trace_lan9118_phy_read(val, reg); |
202 | if (arm_feature(env, ARM_FEATURE_EL3)) { | 348 | + |
203 | define_arm_cp_regs(cpu, el3_cp_reginfo); | 349 | + return val; |
204 | ARMCPRegInfo el3_regs[] = { | 350 | } |
351 | |||
352 | void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
353 | { | ||
354 | + trace_lan9118_phy_write(val, reg); | ||
355 | + | ||
356 | switch (reg) { | ||
357 | case 0: /* Basic Control */ | ||
358 | if (val & 0x8000) { | ||
359 | lan9118_phy_reset(s); | ||
360 | - break; | ||
361 | - } | ||
362 | - s->control = val & 0x7980; | ||
363 | - /* Complete autonegotiation immediately. */ | ||
364 | - if (val & 0x1000) { | ||
365 | - s->status |= 0x0020; | ||
366 | + } else { | ||
367 | + s->control = val & 0x7980; | ||
368 | + /* Complete autonegotiation immediately. */ | ||
369 | + if (val & 0x1000) { | ||
370 | + s->status |= 0x0020; | ||
371 | + } | ||
372 | } | ||
373 | break; | ||
374 | case 4: /* Auto-neg advertisement */ | ||
375 | s->advertise = (val & 0x2d7f) | 0x80; | ||
376 | break; | ||
377 | - /* TODO 17, 18, 27, 31 */ | ||
378 | case 30: /* Interrupt mask */ | ||
379 | s->int_mask = val & 0xff; | ||
380 | lan9118_phy_update_irq(s); | ||
381 | break; | ||
382 | + case 17: | ||
383 | + case 18: | ||
384 | + case 27: | ||
385 | + case 31: | ||
386 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
387 | + __func__, reg); | ||
388 | + break; | ||
389 | default: | ||
390 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
391 | - "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
392 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
393 | + __func__, reg); | ||
394 | + break; | ||
395 | } | ||
396 | } | ||
397 | |||
398 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
399 | |||
400 | /* Autonegotiation status mirrors link status. */ | ||
401 | if (link_down) { | ||
402 | + trace_lan9118_phy_update_link("down"); | ||
403 | s->status &= ~0x0024; | ||
404 | s->ints |= PHY_INT_DOWN; | ||
405 | } else { | ||
406 | + trace_lan9118_phy_update_link("up"); | ||
407 | s->status |= 0x0024; | ||
408 | s->ints |= PHY_INT_ENERGYON; | ||
409 | s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
410 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
411 | |||
412 | void lan9118_phy_reset(Lan9118PhyState *s) | ||
413 | { | ||
414 | + trace_lan9118_phy_reset(); | ||
415 | + | ||
416 | s->control = 0x3000; | ||
417 | s->status = 0x7809; | ||
418 | s->advertise = 0x01e1; | ||
419 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = { | ||
420 | .version_id = 1, | ||
421 | .minimum_version_id = 1, | ||
422 | .fields = (const VMStateField[]) { | ||
423 | - VMSTATE_UINT16(control, Lan9118PhyState), | ||
424 | VMSTATE_UINT16(status, Lan9118PhyState), | ||
425 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
426 | VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
427 | VMSTATE_UINT16(ints, Lan9118PhyState), | ||
428 | VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
429 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
430 | index XXXXXXX..XXXXXXX 100644 | ||
431 | --- a/hw/net/Kconfig | ||
432 | +++ b/hw/net/Kconfig | ||
433 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC | ||
434 | |||
435 | config IMX_FEC | ||
436 | bool | ||
437 | + select LAN9118_PHY | ||
438 | |||
439 | config CADENCE | ||
440 | bool | ||
441 | diff --git a/hw/net/trace-events b/hw/net/trace-events | ||
442 | index XXXXXXX..XXXXXXX 100644 | ||
443 | --- a/hw/net/trace-events | ||
444 | +++ b/hw/net/trace-events | ||
445 | @@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" | ||
446 | allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 | ||
447 | allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 | ||
448 | |||
449 | +# lan9118_phy.c | ||
450 | +lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16 | ||
451 | +lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16 | ||
452 | +lan9118_phy_update_link(const char *s) "%s" | ||
453 | +lan9118_phy_reset(void) "" | ||
454 | + | ||
455 | # lance.c | ||
456 | lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" | ||
457 | lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" | ||
458 | @@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" | ||
459 | i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" | ||
460 | |||
461 | # imx_fec.c | ||
462 | -imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" | ||
463 | imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" | ||
464 | -imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" | ||
465 | imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" | ||
466 | -imx_phy_update_link(const char *s) "%s" | ||
467 | -imx_phy_reset(void) "" | ||
468 | imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" | ||
469 | imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" | ||
470 | imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" | ||
205 | -- | 471 | -- |
206 | 2.25.1 | 472 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | In aarch64_numa_cpu(), the CPU and NUMA association is something | 3 | Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and |
4 | like below. Two threads in the same core/cluster/socket are | 4 | fixes the MSB of selector field to be zero, as specified in the datasheet. |
5 | associated with two individual NUMA nodes, which is unreal as | ||
6 | Igor Mammedov mentioned. We don't expect the association to break | ||
7 | NUMA-to-socket boundary, which matches with the real world. | ||
8 | 5 | ||
9 | NUMA-node socket cluster core thread | 6 | Fixes: 2a424990170b "LAN9118 emulation" |
10 | ------------------------------------------ | 7 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
11 | 0 0 0 0 0 | 8 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
12 | 1 0 0 0 1 | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | 10 | Message-id: 20241102125724.532843-4-shentey@gmail.com | |
14 | This corrects the topology for CPUs and their association with | ||
15 | NUMA nodes. After this patch is applied, the CPU and NUMA | ||
16 | association becomes something like below, which looks real. | ||
17 | Besides, socket/cluster/core/thread IDs are all checked when | ||
18 | the NUMA node IDs are verified. It helps to check if the CPU | ||
19 | topology is properly populated or not. | ||
20 | |||
21 | NUMA-node socket cluster core thread | ||
22 | ------------------------------------------ | ||
23 | 0 1 0 0 0 | ||
24 | 1 0 0 0 0 | ||
25 | |||
26 | Suggested-by: Igor Mammedov <imammedo@redhat.com> | ||
27 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
28 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
29 | Message-id: 20220503140304.855514-5-gshan@redhat.com | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | --- | 12 | --- |
32 | tests/qtest/numa-test.c | 18 ++++++++++++------ | 13 | hw/net/lan9118_phy.c | 2 +- |
33 | 1 file changed, 12 insertions(+), 6 deletions(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
34 | 15 | ||
35 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c | 16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
36 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/tests/qtest/numa-test.c | 18 | --- a/hw/net/lan9118_phy.c |
38 | +++ b/tests/qtest/numa-test.c | 19 | +++ b/hw/net/lan9118_phy.c |
39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | 20 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) |
40 | g_autofree char *cli = NULL; | 21 | val = s->advertise; |
41 | 22 | break; | |
42 | cli = make_cli(data, "-machine " | 23 | case 5: /* Auto-neg Link Partner Ability */ |
43 | - "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " | 24 | - val = 0x0f71; |
44 | + "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 " | 25 | + val = 0x0fe1; |
45 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " | 26 | break; |
46 | - "-numa cpu,node-id=1,thread-id=0 " | 27 | case 6: /* Auto-neg Expansion */ |
47 | - "-numa cpu,node-id=0,thread-id=1"); | 28 | val = 1; |
48 | + "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 " | ||
49 | + "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0"); | ||
50 | qts = qtest_init(cli); | ||
51 | cpus = get_cpus(qts, &resp); | ||
52 | g_assert(cpus); | ||
53 | |||
54 | while ((e = qlist_pop(cpus))) { | ||
55 | QDict *cpu, *props; | ||
56 | - int64_t thread, node; | ||
57 | + int64_t socket, cluster, core, thread, node; | ||
58 | |||
59 | cpu = qobject_to(QDict, e); | ||
60 | g_assert(qdict_haskey(cpu, "props")); | ||
61 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | ||
62 | |||
63 | g_assert(qdict_haskey(props, "node-id")); | ||
64 | node = qdict_get_int(props, "node-id"); | ||
65 | + g_assert(qdict_haskey(props, "socket-id")); | ||
66 | + socket = qdict_get_int(props, "socket-id"); | ||
67 | + g_assert(qdict_haskey(props, "cluster-id")); | ||
68 | + cluster = qdict_get_int(props, "cluster-id"); | ||
69 | + g_assert(qdict_haskey(props, "core-id")); | ||
70 | + core = qdict_get_int(props, "core-id"); | ||
71 | g_assert(qdict_haskey(props, "thread-id")); | ||
72 | thread = qdict_get_int(props, "thread-id"); | ||
73 | |||
74 | - if (thread == 0) { | ||
75 | + if (socket == 0 && cluster == 0 && core == 0 && thread == 0) { | ||
76 | g_assert_cmpint(node, ==, 1); | ||
77 | - } else if (thread == 1) { | ||
78 | + } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) { | ||
79 | g_assert_cmpint(node, ==, 0); | ||
80 | } else { | ||
81 | g_assert(false); | ||
82 | -- | 29 | -- |
83 | 2.25.1 | 30 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Check for and defer any pending virtual SError. | 3 | Prefer named constants over magic values for better readability. |
4 | 4 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
7 | Message-id: 20220506180242.216785-17-richard.henderson@linaro.org | 7 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
8 | Message-id: 20241102125724.532843-5-shentey@gmail.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/helper.h | 1 + | 11 | include/hw/net/mii.h | 6 +++++ |
11 | target/arm/a32.decode | 16 ++++++++------ | 12 | hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++---------------- |
12 | target/arm/t32.decode | 18 ++++++++-------- | 13 | 2 files changed, 46 insertions(+), 23 deletions(-) |
13 | target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-a64.c | 17 +++++++++++++++ | ||
15 | target/arm/translate.c | 23 ++++++++++++++++++++ | ||
16 | 6 files changed, 103 insertions(+), 15 deletions(-) | ||
17 | 14 | ||
18 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 15 | diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h |
19 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper.h | 17 | --- a/include/hw/net/mii.h |
21 | +++ b/target/arm/helper.h | 18 | +++ b/include/hw/net/mii.h |
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env) | 19 | @@ -XXX,XX +XXX,XX @@ |
23 | DEF_HELPER_1(yield, void, env) | 20 | #define MII_BMSR_JABBER (1 << 1) /* Jabber detected */ |
24 | DEF_HELPER_1(pre_hvc, void, env) | 21 | #define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */ |
25 | DEF_HELPER_2(pre_smc, void, env, i32) | 22 | |
26 | +DEF_HELPER_1(vesb, void, env) | 23 | +#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */ |
27 | 24 | #define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */ | |
28 | DEF_HELPER_3(cpsr_write, void, env, i32, i32) | 25 | #define MII_ANAR_PAUSE (1 << 10) /* Try for pause */ |
29 | DEF_HELPER_2(cpsr_write_eret, void, env, i32) | 26 | #define MII_ANAR_TXFD (1 << 8) |
30 | diff --git a/target/arm/a32.decode b/target/arm/a32.decode | 27 | @@ -XXX,XX +XXX,XX @@ |
28 | #define MII_ANAR_10FD (1 << 6) | ||
29 | #define MII_ANAR_10 (1 << 5) | ||
30 | #define MII_ANAR_CSMACD (1 << 0) | ||
31 | +#define MII_ANAR_SELECT (0x001f) /* Selector bits */ | ||
32 | |||
33 | #define MII_ANLPAR_ACK (1 << 14) | ||
34 | #define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */ | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | #define RTL8201CP_PHYID1 0x0000 | ||
37 | #define RTL8201CP_PHYID2 0x8201 | ||
38 | |||
39 | +/* SMSC LAN9118 */ | ||
40 | +#define SMSCLAN9118_PHYID1 0x0007 | ||
41 | +#define SMSCLAN9118_PHYID2 0xc0d1 | ||
42 | + | ||
43 | /* RealTek 8211E */ | ||
44 | #define RTL8211E_PHYID1 0x001c | ||
45 | #define RTL8211E_PHYID2 0xc915 | ||
46 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | 47 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/target/arm/a32.decode | 48 | --- a/hw/net/lan9118_phy.c |
33 | +++ b/target/arm/a32.decode | 49 | +++ b/hw/net/lan9118_phy.c |
34 | @@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn | 50 | @@ -XXX,XX +XXX,XX @@ |
35 | 51 | ||
36 | { | 52 | #include "qemu/osdep.h" |
37 | { | 53 | #include "hw/net/lan9118_phy.h" |
38 | - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 | 54 | +#include "hw/net/mii.h" |
39 | - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 | 55 | #include "hw/irq.h" |
40 | - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 | 56 | #include "hw/resettable.h" |
41 | + [ | 57 | #include "migration/vmstate.h" |
42 | + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 | 58 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) |
43 | + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 | 59 | uint16_t val; |
44 | + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 | 60 | |
45 | 61 | switch (reg) { | |
46 | - # TODO: Implement SEV, SEVL; may help SMP performance. | 62 | - case 0: /* Basic Control */ |
47 | - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 | 63 | + case MII_BMCR: |
48 | - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 | 64 | val = s->control; |
49 | + # TODO: Implement SEV, SEVL; may help SMP performance. | 65 | break; |
50 | + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 | 66 | - case 1: /* Basic Status */ |
51 | + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 | 67 | + case MII_BMSR: |
52 | + | 68 | val = s->status; |
53 | + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 | 69 | break; |
54 | + ] | 70 | - case 2: /* ID1 */ |
55 | 71 | - val = 0x0007; | |
56 | # The canonical nop ends in 00000000, but the whole of the | 72 | + case MII_PHYID1: |
57 | # rest of the space executes as nop if otherwise unsupported. | 73 | + val = SMSCLAN9118_PHYID1; |
58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | 74 | break; |
59 | index XXXXXXX..XXXXXXX 100644 | 75 | - case 3: /* ID2 */ |
60 | --- a/target/arm/t32.decode | 76 | - val = 0xc0d1; |
61 | +++ b/target/arm/t32.decode | 77 | + case MII_PHYID2: |
62 | @@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm | 78 | + val = SMSCLAN9118_PHYID2; |
63 | [ | 79 | break; |
64 | # Hints, and CPS | 80 | - case 4: /* Auto-neg advertisement */ |
65 | { | 81 | + case MII_ANAR: |
66 | - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | 82 | val = s->advertise; |
67 | - WFE 1111 0011 1010 1111 1000 0000 0000 0010 | 83 | break; |
68 | - WFI 1111 0011 1010 1111 1000 0000 0000 0011 | 84 | - case 5: /* Auto-neg Link Partner Ability */ |
69 | + [ | 85 | - val = 0x0fe1; |
70 | + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | 86 | + case MII_ANLPAR: |
71 | + WFE 1111 0011 1010 1111 1000 0000 0000 0010 | 87 | + val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 | |
72 | + WFI 1111 0011 1010 1111 1000 0000 0000 0011 | 88 | + MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | |
73 | 89 | + MII_ANLPAR_10 | MII_ANLPAR_CSMACD; | |
74 | - # TODO: Implement SEV, SEVL; may help SMP performance. | 90 | break; |
75 | - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | 91 | - case 6: /* Auto-neg Expansion */ |
76 | - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | 92 | - val = 1; |
77 | + # TODO: Implement SEV, SEVL; may help SMP performance. | 93 | + case MII_ANER: |
78 | + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | 94 | + val = MII_ANER_NWAY; |
79 | + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | 95 | break; |
80 | 96 | case 29: /* Interrupt source. */ | |
81 | - # For M-profile minimal-RAS ESB can be a NOP, which is the | 97 | val = s->ints; |
82 | - # default behaviour since it is in the hint space. | 98 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) |
83 | - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 | 99 | trace_lan9118_phy_write(val, reg); |
84 | + ESB 1111 0011 1010 1111 1000 0000 0001 0000 | 100 | |
85 | + ] | 101 | switch (reg) { |
86 | 102 | - case 0: /* Basic Control */ | |
87 | # The canonical nop ends in 0000 0000, but the whole rest | 103 | - if (val & 0x8000) { |
88 | # of the space is "reserved hint, behaves as nop". | 104 | + case MII_BMCR: |
89 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | 105 | + if (val & MII_BMCR_RESET) { |
90 | index XXXXXXX..XXXXXXX 100644 | 106 | lan9118_phy_reset(s); |
91 | --- a/target/arm/op_helper.c | 107 | } else { |
92 | +++ b/target/arm/op_helper.c | 108 | - s->control = val & 0x7980; |
93 | @@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, | 109 | + s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | |
94 | access_type, mmu_idx, ra); | 110 | + MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD | |
95 | } | 111 | + MII_BMCR_CTST); |
96 | } | 112 | /* Complete autonegotiation immediately. */ |
97 | + | 113 | - if (val & 0x1000) { |
98 | +/* | 114 | - s->status |= 0x0020; |
99 | + * This function corresponds to AArch64.vESBOperation(). | 115 | + if (val & MII_BMCR_AUTOEN) { |
100 | + * Note that the AArch32 version is not functionally different. | 116 | + s->status |= MII_BMSR_AN_COMP; |
101 | + */ | 117 | } |
102 | +void HELPER(vesb)(CPUARMState *env) | ||
103 | +{ | ||
104 | + /* | ||
105 | + * The EL2Enabled() check is done inside arm_hcr_el2_eff, | ||
106 | + * and will return HCR_EL2.VSE == 0, so nothing happens. | ||
107 | + */ | ||
108 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
109 | + bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO); | ||
110 | + bool pending = enabled && (hcr & HCR_VSE); | ||
111 | + bool masked = (env->daif & PSTATE_A); | ||
112 | + | ||
113 | + /* If VSE pending and masked, defer the exception. */ | ||
114 | + if (pending && masked) { | ||
115 | + uint32_t syndrome; | ||
116 | + | ||
117 | + if (arm_el_is_aa64(env, 1)) { | ||
118 | + /* Copy across IDS and ISS from VSESR. */ | ||
119 | + syndrome = env->cp15.vsesr_el2 & 0x1ffffff; | ||
120 | + } else { | ||
121 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal }; | ||
122 | + | ||
123 | + if (extended_addresses_enabled(env)) { | ||
124 | + syndrome = arm_fi_to_lfsc(&fi); | ||
125 | + } else { | ||
126 | + syndrome = arm_fi_to_sfsc(&fi); | ||
127 | + } | ||
128 | + /* Copy across AET and ExT from VSESR. */ | ||
129 | + syndrome |= env->cp15.vsesr_el2 & 0xd000; | ||
130 | + } | ||
131 | + | ||
132 | + /* Set VDISR_EL2.A along with the syndrome. */ | ||
133 | + env->cp15.vdisr_el2 = syndrome | (1u << 31); | ||
134 | + | ||
135 | + /* Clear pending virtual SError */ | ||
136 | + env->cp15.hcr_el2 &= ~HCR_VSE; | ||
137 | + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); | ||
138 | + } | ||
139 | +} | ||
140 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
141 | index XXXXXXX..XXXXXXX 100644 | ||
142 | --- a/target/arm/translate-a64.c | ||
143 | +++ b/target/arm/translate-a64.c | ||
144 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, | ||
145 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
146 | } | 118 | } |
147 | break; | 119 | break; |
148 | + case 0b10000: /* ESB */ | 120 | - case 4: /* Auto-neg advertisement */ |
149 | + /* Without RAS, we must implement this as NOP. */ | 121 | - s->advertise = (val & 0x2d7f) | 0x80; |
150 | + if (dc_isar_feature(aa64_ras, s)) { | 122 | + case MII_ANAR: |
151 | + /* | 123 | + s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | |
152 | + * QEMU does not have a source of physical SErrors, | 124 | + MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | |
153 | + * so we are only concerned with virtual SErrors. | 125 | + MII_ANAR_SELECT)) |
154 | + * The pseudocode in the ARM for this case is | 126 | + | MII_ANAR_TX; |
155 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | 127 | break; |
156 | + * AArch64.vESBOperation(); | 128 | case 30: /* Interrupt mask */ |
157 | + * Most of the condition can be evaluated at translation time. | 129 | s->int_mask = val & 0xff; |
158 | + * Test for EL2 present, and defer test for SEL2 to runtime. | 130 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) |
159 | + */ | 131 | /* Autonegotiation status mirrors link status. */ |
160 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | 132 | if (link_down) { |
161 | + gen_helper_vesb(cpu_env); | 133 | trace_lan9118_phy_update_link("down"); |
162 | + } | 134 | - s->status &= ~0x0024; |
163 | + } | 135 | + s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST); |
164 | + break; | 136 | s->ints |= PHY_INT_DOWN; |
165 | case 0b11000: /* PACIAZ */ | 137 | } else { |
166 | if (s->pauth_active) { | 138 | trace_lan9118_phy_update_link("up"); |
167 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | 139 | - s->status |= 0x0024; |
168 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 140 | + s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST; |
169 | index XXXXXXX..XXXXXXX 100644 | 141 | s->ints |= PHY_INT_ENERGYON; |
170 | --- a/target/arm/translate.c | 142 | s->ints |= PHY_INT_AUTONEG_COMPLETE; |
171 | +++ b/target/arm/translate.c | 143 | } |
172 | @@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) | 144 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s) |
173 | return true; | ||
174 | } | ||
175 | |||
176 | +static bool trans_ESB(DisasContext *s, arg_ESB *a) | ||
177 | +{ | ||
178 | + /* | ||
179 | + * For M-profile, minimal-RAS ESB can be a NOP. | ||
180 | + * Without RAS, we must implement this as NOP. | ||
181 | + */ | ||
182 | + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) { | ||
183 | + /* | ||
184 | + * QEMU does not have a source of physical SErrors, | ||
185 | + * so we are only concerned with virtual SErrors. | ||
186 | + * The pseudocode in the ARM for this case is | ||
187 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
188 | + * AArch32.vESBOperation(); | ||
189 | + * Most of the condition can be evaluated at translation time. | ||
190 | + * Test for EL2 present, and defer test for SEL2 to runtime. | ||
191 | + */ | ||
192 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
193 | + gen_helper_vesb(cpu_env); | ||
194 | + } | ||
195 | + } | ||
196 | + return true; | ||
197 | +} | ||
198 | + | ||
199 | static bool trans_NOP(DisasContext *s, arg_NOP *a) | ||
200 | { | 145 | { |
201 | return true; | 146 | trace_lan9118_phy_reset(); |
147 | |||
148 | - s->control = 0x3000; | ||
149 | - s->status = 0x7809; | ||
150 | - s->advertise = 0x01e1; | ||
151 | + s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100; | ||
152 | + s->status = MII_BMSR_100TX_FD | ||
153 | + | MII_BMSR_100TX_HD | ||
154 | + | MII_BMSR_10T_FD | ||
155 | + | MII_BMSR_10T_HD | ||
156 | + | MII_BMSR_AUTONEG | ||
157 | + | MII_BMSR_EXTCAP; | ||
158 | + s->advertise = MII_ANAR_TXFD | ||
159 | + | MII_ANAR_TX | ||
160 | + | MII_ANAR_10FD | ||
161 | + | MII_ANAR_10 | ||
162 | + | MII_ANAR_CSMACD; | ||
163 | s->int_mask = 0; | ||
164 | s->ints = 0; | ||
165 | lan9118_phy_update_link(s, s->link_down); | ||
202 | -- | 166 | -- |
203 | 2.25.1 | 167 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns not merging memory access, which TCG does | 3 | The real device advertises this mode and the device model already advertises |
4 | not implement. Thus we can trivially enable this feature. | 4 | 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to |
5 | Add a comment to handle_hint for the DGH instruction, but no code. | 5 | make the model more realistic. |
6 | 6 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
9 | Message-id: 20220506180242.216785-23-richard.henderson@linaro.org | 9 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
10 | Message-id: 20241102125724.532843-6-shentey@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | docs/system/arm/emulation.rst | 1 + | 13 | hw/net/lan9118_phy.c | 4 ++-- |
13 | target/arm/cpu64.c | 1 + | 14 | 1 file changed, 2 insertions(+), 2 deletions(-) |
14 | target/arm/translate-a64.c | 1 + | ||
15 | 3 files changed, 3 insertions(+) | ||
16 | 15 | ||
17 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/docs/system/arm/emulation.rst | 18 | --- a/hw/net/lan9118_phy.c |
20 | +++ b/docs/system/arm/emulation.rst | 19 | +++ b/hw/net/lan9118_phy.c |
21 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 20 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) |
22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | ||
23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | ||
24 | - FEAT_CSV3 (Cache speculation variant 3) | ||
25 | +- FEAT_DGH (Data gathering hint) | ||
26 | - FEAT_DIT (Data Independent Timing instructions) | ||
27 | - FEAT_DPB (DC CVAP instruction) | ||
28 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
29 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/cpu64.c | ||
32 | +++ b/target/arm/cpu64.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
34 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | ||
35 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | ||
36 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | ||
37 | + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ | ||
38 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | ||
39 | cpu->isar.id_aa64isar1 = t; | ||
40 | |||
41 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/translate-a64.c | ||
44 | +++ b/target/arm/translate-a64.c | ||
45 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, | ||
46 | break; | 21 | break; |
47 | case 0b00100: /* SEV */ | 22 | case MII_ANAR: |
48 | case 0b00101: /* SEVL */ | 23 | s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | |
49 | + case 0b00110: /* DGH */ | 24 | - MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | |
50 | /* we treat all as NOP at least for now */ | 25 | - MII_ANAR_SELECT)) |
26 | + MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD | | ||
27 | + MII_ANAR_10 | MII_ANAR_SELECT)) | ||
28 | | MII_ANAR_TX; | ||
51 | break; | 29 | break; |
52 | case 0b00111: /* XPACLRI */ | 30 | case 30: /* Interrupt mask */ |
53 | -- | 31 | -- |
54 | 2.25.1 | 32 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | For IEEE fused multiply-add, the (0 * inf) + NaN case should raise | ||
2 | Invalid for the multiplication of 0 by infinity. Currently we handle | ||
3 | this in the per-architecture ifdef ladder in pickNaNMulAdd(). | ||
4 | However, since this isn't really architecture specific we can hoist | ||
5 | it up to the generic code. | ||
1 | 6 | ||
7 | For the cases where the infzero test in pickNaNMulAdd was | ||
8 | returning 2, we can delete the check entirely and allow the | ||
9 | code to fall into the normal pick-a-NaN handling, because this | ||
10 | will return 2 anyway (input 'c' being the only NaN in this case). | ||
11 | For the cases where infzero was returning 3 to indicate "return | ||
12 | the default NaN", we must retain that "return 3". | ||
13 | |||
14 | For Arm, this looks like it might be a behaviour change because we | ||
15 | used to set float_flag_invalid | float_flag_invalid_imz only if C is | ||
16 | a quiet NaN. However, it is not, because Arm target code never looks | ||
17 | at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we | ||
18 | already raised float_flag_invalid via the "abc_mask & | ||
19 | float_cmask_snan" check in pick_nan_muladd. | ||
20 | |||
21 | For any target architecture using the "default implementation" at the | ||
22 | bottom of the ifdef, this is a behaviour change but will be fixing a | ||
23 | bug (where we failed to raise the Invalid exception for (0 * inf + | ||
24 | QNaN). The architectures using the default case are: | ||
25 | * hppa | ||
26 | * i386 | ||
27 | * sh4 | ||
28 | * tricore | ||
29 | |||
30 | The x86, Tricore and SH4 CPU architecture manuals are clear that this | ||
31 | should have raised Invalid; HPPA is a bit vaguer but still seems | ||
32 | clear enough. | ||
33 | |||
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
35 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
36 | Message-id: 20241202131347.498124-2-peter.maydell@linaro.org | ||
37 | --- | ||
38 | fpu/softfloat-parts.c.inc | 13 +++++++------ | ||
39 | fpu/softfloat-specialize.c.inc | 29 +---------------------------- | ||
40 | 2 files changed, 8 insertions(+), 34 deletions(-) | ||
41 | |||
42 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/fpu/softfloat-parts.c.inc | ||
45 | +++ b/fpu/softfloat-parts.c.inc | ||
46 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
47 | int ab_mask, int abc_mask) | ||
48 | { | ||
49 | int which; | ||
50 | + bool infzero = (ab_mask == float_cmask_infzero); | ||
51 | |||
52 | if (unlikely(abc_mask & float_cmask_snan)) { | ||
53 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
54 | } | ||
55 | |||
56 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, | ||
57 | - ab_mask == float_cmask_infzero, s); | ||
58 | + if (infzero) { | ||
59 | + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ | ||
60 | + float_raise(float_flag_invalid | float_flag_invalid_imz, s); | ||
61 | + } | ||
62 | + | ||
63 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
64 | |||
65 | if (s->default_nan_mode || which == 3) { | ||
66 | - /* | ||
67 | - * Note that this check is after pickNaNMulAdd so that function | ||
68 | - * has an opportunity to set the Invalid flag for infzero. | ||
69 | - */ | ||
70 | parts_default_nan(a, s); | ||
71 | return a; | ||
72 | } | ||
73 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/fpu/softfloat-specialize.c.inc | ||
76 | +++ b/fpu/softfloat-specialize.c.inc | ||
77 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
78 | * the default NaN | ||
79 | */ | ||
80 | if (infzero && is_qnan(c_cls)) { | ||
81 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
82 | return 3; | ||
83 | } | ||
84 | |||
85 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
86 | * case sets InvalidOp and returns the default NaN | ||
87 | */ | ||
88 | if (infzero) { | ||
89 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
90 | return 3; | ||
91 | } | ||
92 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
93 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
94 | * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
95 | * case sets InvalidOp and returns the input value 'c' | ||
96 | */ | ||
97 | - if (infzero) { | ||
98 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
99 | - return 2; | ||
100 | - } | ||
101 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
102 | if (is_snan(c_cls)) { | ||
103 | return 2; | ||
104 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
105 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
106 | * case sets InvalidOp and returns the input value 'c' | ||
107 | */ | ||
108 | - if (infzero) { | ||
109 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
110 | - return 2; | ||
111 | - } | ||
112 | + | ||
113 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
114 | if (is_snan(c_cls)) { | ||
115 | return 2; | ||
116 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
117 | * to return an input NaN if we have one (ie c) rather than generating | ||
118 | * a default NaN | ||
119 | */ | ||
120 | - if (infzero) { | ||
121 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
122 | - return 2; | ||
123 | - } | ||
124 | |||
125 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
126 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
127 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
128 | return 1; | ||
129 | } | ||
130 | #elif defined(TARGET_RISCV) | ||
131 | - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ | ||
132 | - if (infzero) { | ||
133 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
134 | - } | ||
135 | return 3; /* default NaN */ | ||
136 | #elif defined(TARGET_S390X) | ||
137 | if (infzero) { | ||
138 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
139 | return 3; | ||
140 | } | ||
141 | |||
142 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
143 | return 2; | ||
144 | } | ||
145 | #elif defined(TARGET_SPARC) | ||
146 | - /* For (inf,0,nan) return c. */ | ||
147 | - if (infzero) { | ||
148 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
149 | - return 2; | ||
150 | - } | ||
151 | /* Prefer SNaN over QNaN, order C, B, A. */ | ||
152 | if (is_snan(c_cls)) { | ||
153 | return 2; | ||
154 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
155 | * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
156 | * an input NaN if we have one (ie c). | ||
157 | */ | ||
158 | - if (infzero) { | ||
159 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
160 | - return 2; | ||
161 | - } | ||
162 | if (status->use_first_nan) { | ||
163 | if (is_nan(a_cls)) { | ||
164 | return 0; | ||
165 | -- | ||
166 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | If the target sets default_nan_mode then we're always going to return | ||
2 | the default NaN, and pickNaNMulAdd() no longer has any side effects. | ||
3 | For consistency with pickNaN(), check for default_nan_mode before | ||
4 | calling pickNaNMulAdd(). | ||
1 | 5 | ||
6 | When we convert pickNaNMulAdd() to allow runtime selection of the NaN | ||
7 | propagation rule, this means we won't have to make the targets which | ||
8 | use default_nan_mode also set a propagation rule. | ||
9 | |||
10 | Since RiscV always uses default_nan_mode, this allows us to remove | ||
11 | its ifdef case from pickNaNMulAdd(). | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20241202131347.498124-3-peter.maydell@linaro.org | ||
16 | --- | ||
17 | fpu/softfloat-parts.c.inc | 8 ++++++-- | ||
18 | fpu/softfloat-specialize.c.inc | 9 +++++++-- | ||
19 | 2 files changed, 13 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/fpu/softfloat-parts.c.inc | ||
24 | +++ b/fpu/softfloat-parts.c.inc | ||
25 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
26 | float_raise(float_flag_invalid | float_flag_invalid_imz, s); | ||
27 | } | ||
28 | |||
29 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
30 | + if (s->default_nan_mode) { | ||
31 | + which = 3; | ||
32 | + } else { | ||
33 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
34 | + } | ||
35 | |||
36 | - if (s->default_nan_mode || which == 3) { | ||
37 | + if (which == 3) { | ||
38 | parts_default_nan(a, s); | ||
39 | return a; | ||
40 | } | ||
41 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/fpu/softfloat-specialize.c.inc | ||
44 | +++ b/fpu/softfloat-specialize.c.inc | ||
45 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
46 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
47 | bool infzero, float_status *status) | ||
48 | { | ||
49 | + /* | ||
50 | + * We guarantee not to require the target to tell us how to | ||
51 | + * pick a NaN if we're always returning the default NaN. | ||
52 | + * But if we're not in default-NaN mode then the target must | ||
53 | + * specify. | ||
54 | + */ | ||
55 | + assert(!status->default_nan_mode); | ||
56 | #if defined(TARGET_ARM) | ||
57 | /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
58 | * the default NaN | ||
59 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
60 | } else { | ||
61 | return 1; | ||
62 | } | ||
63 | -#elif defined(TARGET_RISCV) | ||
64 | - return 3; /* default NaN */ | ||
65 | #elif defined(TARGET_S390X) | ||
66 | if (infzero) { | ||
67 | return 3; | ||
68 | -- | ||
69 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | IEEE 758 does not define a fixed rule for what NaN to return in | |
2 | the case of a fused multiply-add of inf * 0 + NaN. Different | ||
3 | architectures thus do different things: | ||
4 | * some return the default NaN | ||
5 | * some return the input NaN | ||
6 | * Arm returns the default NaN if the input NaN is quiet, | ||
7 | and the input NaN if it is signalling | ||
8 | |||
9 | We want to make this logic be runtime selected rather than | ||
10 | hardcoded into the binary, because: | ||
11 | * this will let us have multiple targets in one QEMU binary | ||
12 | * the Arm FEAT_AFP architectural feature includes letting | ||
13 | the guest select a NaN propagation rule at runtime | ||
14 | |||
15 | In this commit we add an enum for the propagation rule, the field in | ||
16 | float_status, and the corresponding getters and setters. We change | ||
17 | pickNaNMulAdd to honour this, but because all targets still leave | ||
18 | this field at its default 0 value, the fallback logic will pick the | ||
19 | rule type with the old ifdef ladder. | ||
20 | |||
21 | Note that four architectures both use the muladd softfloat functions | ||
22 | and did not have a branch of the ifdef ladder to specify their | ||
23 | behaviour (and so were ending up with the "default" case, probably | ||
24 | wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set | ||
25 | default_nan_mode, and so will never get into pickNaNMulAdd(). For | ||
26 | HPPA and i386 we retain the same behaviour as the old default-case, | ||
27 | which is to not ever return the default NaN. This might not be | ||
28 | correct but it is not a behaviour change. | ||
29 | |||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
32 | Message-id: 20241202131347.498124-4-peter.maydell@linaro.org | ||
33 | --- | ||
34 | include/fpu/softfloat-helpers.h | 11 ++++ | ||
35 | include/fpu/softfloat-types.h | 23 +++++++++ | ||
36 | fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- | ||
37 | 3 files changed, 95 insertions(+), 30 deletions(-) | ||
38 | |||
39 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/include/fpu/softfloat-helpers.h | ||
42 | +++ b/include/fpu/softfloat-helpers.h | ||
43 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, | ||
44 | status->float_2nan_prop_rule = rule; | ||
45 | } | ||
46 | |||
47 | +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, | ||
48 | + float_status *status) | ||
49 | +{ | ||
50 | + status->float_infzeronan_rule = rule; | ||
51 | +} | ||
52 | + | ||
53 | static inline void set_flush_to_zero(bool val, float_status *status) | ||
54 | { | ||
55 | status->flush_to_zero = val; | ||
56 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) | ||
57 | return status->float_2nan_prop_rule; | ||
58 | } | ||
59 | |||
60 | +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) | ||
61 | +{ | ||
62 | + return status->float_infzeronan_rule; | ||
63 | +} | ||
64 | + | ||
65 | static inline bool get_flush_to_zero(float_status *status) | ||
66 | { | ||
67 | return status->flush_to_zero; | ||
68 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/include/fpu/softfloat-types.h | ||
71 | +++ b/include/fpu/softfloat-types.h | ||
72 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { | ||
73 | float_2nan_prop_x87, | ||
74 | } Float2NaNPropRule; | ||
75 | |||
76 | +/* | ||
77 | + * Rule for result of fused multiply-add 0 * Inf + NaN. | ||
78 | + * This must be a NaN, but implementations differ on whether this | ||
79 | + * is the input NaN or the default NaN. | ||
80 | + * | ||
81 | + * You don't need to set this if default_nan_mode is enabled. | ||
82 | + * When not in default-NaN mode, it is an error for the target | ||
83 | + * not to set the rule in float_status if it uses muladd, and we | ||
84 | + * will assert if we need to handle an input NaN and no rule was | ||
85 | + * selected. | ||
86 | + */ | ||
87 | +typedef enum __attribute__((__packed__)) { | ||
88 | + /* No propagation rule specified */ | ||
89 | + float_infzeronan_none = 0, | ||
90 | + /* Result is never the default NaN (so always the input NaN) */ | ||
91 | + float_infzeronan_dnan_never, | ||
92 | + /* Result is always the default NaN */ | ||
93 | + float_infzeronan_dnan_always, | ||
94 | + /* Result is the default NaN if the input NaN is quiet */ | ||
95 | + float_infzeronan_dnan_if_qnan, | ||
96 | +} FloatInfZeroNaNRule; | ||
97 | + | ||
98 | /* | ||
99 | * Floating Point Status. Individual architectures may maintain | ||
100 | * several versions of float_status for different functions. The | ||
101 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
102 | FloatRoundMode float_rounding_mode; | ||
103 | FloatX80RoundPrec floatx80_rounding_precision; | ||
104 | Float2NaNPropRule float_2nan_prop_rule; | ||
105 | + FloatInfZeroNaNRule float_infzeronan_rule; | ||
106 | bool tininess_before_rounding; | ||
107 | /* should denormalised results go to zero and set the inexact flag? */ | ||
108 | bool flush_to_zero; | ||
109 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/fpu/softfloat-specialize.c.inc | ||
112 | +++ b/fpu/softfloat-specialize.c.inc | ||
113 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
114 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
115 | bool infzero, float_status *status) | ||
116 | { | ||
117 | + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
118 | + | ||
119 | /* | ||
120 | * We guarantee not to require the target to tell us how to | ||
121 | * pick a NaN if we're always returning the default NaN. | ||
122 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
123 | * specify. | ||
124 | */ | ||
125 | assert(!status->default_nan_mode); | ||
126 | + | ||
127 | + if (rule == float_infzeronan_none) { | ||
128 | + /* | ||
129 | + * Temporarily fall back to ifdef ladder | ||
130 | + */ | ||
131 | #if defined(TARGET_ARM) | ||
132 | - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
133 | - * the default NaN | ||
134 | - */ | ||
135 | - if (infzero && is_qnan(c_cls)) { | ||
136 | - return 3; | ||
137 | + /* | ||
138 | + * For ARM, the (inf,zero,qnan) case returns the default NaN, | ||
139 | + * but (inf,zero,snan) returns the input NaN. | ||
140 | + */ | ||
141 | + rule = float_infzeronan_dnan_if_qnan; | ||
142 | +#elif defined(TARGET_MIPS) | ||
143 | + if (snan_bit_is_one(status)) { | ||
144 | + /* | ||
145 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
146 | + * case sets InvalidOp and returns the default NaN | ||
147 | + */ | ||
148 | + rule = float_infzeronan_dnan_always; | ||
149 | + } else { | ||
150 | + /* | ||
151 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
152 | + * case sets InvalidOp and returns the input value 'c' | ||
153 | + */ | ||
154 | + rule = float_infzeronan_dnan_never; | ||
155 | + } | ||
156 | +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
157 | + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
158 | + defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
159 | + /* | ||
160 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
161 | + * case sets InvalidOp and returns the input value 'c' | ||
162 | + */ | ||
163 | + /* | ||
164 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
165 | + * to return an input NaN if we have one (ie c) rather than generating | ||
166 | + * a default NaN | ||
167 | + */ | ||
168 | + rule = float_infzeronan_dnan_never; | ||
169 | +#elif defined(TARGET_S390X) | ||
170 | + rule = float_infzeronan_dnan_always; | ||
171 | +#endif | ||
172 | } | ||
173 | |||
174 | + if (infzero) { | ||
175 | + /* | ||
176 | + * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
177 | + * and some return the input NaN. | ||
178 | + */ | ||
179 | + switch (rule) { | ||
180 | + case float_infzeronan_dnan_never: | ||
181 | + return 2; | ||
182 | + case float_infzeronan_dnan_always: | ||
183 | + return 3; | ||
184 | + case float_infzeronan_dnan_if_qnan: | ||
185 | + return is_qnan(c_cls) ? 3 : 2; | ||
186 | + default: | ||
187 | + g_assert_not_reached(); | ||
188 | + } | ||
189 | + } | ||
190 | + | ||
191 | +#if defined(TARGET_ARM) | ||
192 | + | ||
193 | /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
194 | * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
195 | */ | ||
196 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
197 | } | ||
198 | #elif defined(TARGET_MIPS) | ||
199 | if (snan_bit_is_one(status)) { | ||
200 | - /* | ||
201 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
202 | - * case sets InvalidOp and returns the default NaN | ||
203 | - */ | ||
204 | - if (infzero) { | ||
205 | - return 3; | ||
206 | - } | ||
207 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
208 | if (is_snan(a_cls)) { | ||
209 | return 0; | ||
210 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
211 | return 2; | ||
212 | } | ||
213 | } else { | ||
214 | - /* | ||
215 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
216 | - * case sets InvalidOp and returns the input value 'c' | ||
217 | - */ | ||
218 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
219 | if (is_snan(c_cls)) { | ||
220 | return 2; | ||
221 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
222 | } | ||
223 | } | ||
224 | #elif defined(TARGET_LOONGARCH64) | ||
225 | - /* | ||
226 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
227 | - * case sets InvalidOp and returns the input value 'c' | ||
228 | - */ | ||
229 | - | ||
230 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
231 | if (is_snan(c_cls)) { | ||
232 | return 2; | ||
233 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
234 | return 1; | ||
235 | } | ||
236 | #elif defined(TARGET_PPC) | ||
237 | - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
238 | - * to return an input NaN if we have one (ie c) rather than generating | ||
239 | - * a default NaN | ||
240 | - */ | ||
241 | - | ||
242 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
243 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
244 | */ | ||
245 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
246 | return 1; | ||
247 | } | ||
248 | #elif defined(TARGET_S390X) | ||
249 | - if (infzero) { | ||
250 | - return 3; | ||
251 | - } | ||
252 | - | ||
253 | if (is_snan(a_cls)) { | ||
254 | return 0; | ||
255 | } else if (is_snan(b_cls)) { | ||
256 | -- | ||
257 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <quic_llindhol@quicinc.com> | 1 | Explicitly set a rule in the softfloat tests for the inf-zero-nan |
---|---|---|---|
2 | muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, | ||
3 | and so we should select here the Arm rule of | ||
4 | float_infzeronan_dnan_if_qnan. | ||
2 | 5 | ||
3 | The sbsa-ref machine is continuously evolving. Some of the changes we | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
4 | want to make in the near future, to align with real components (e.g. | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | the GIC-700), will break compatibility for existing firmware. | 8 | Message-id: 20241202131347.498124-5-peter.maydell@linaro.org |
9 | --- | ||
10 | tests/fp/fp-bench.c | 5 +++++ | ||
11 | tests/fp/fp-test.c | 5 +++++ | ||
12 | 2 files changed, 10 insertions(+) | ||
6 | 13 | ||
7 | Introduce two new properties to the DT generated on machine generation: | 14 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c |
8 | - machine-version-major | ||
9 | To be incremented when a platform change makes the machine | ||
10 | incompatible with existing firmware. | ||
11 | - machine-version-minor | ||
12 | To be incremented when functionality is added to the machine | ||
13 | without causing incompatibility with existing firmware. | ||
14 | to be reset to 0 when machine-version-major is incremented. | ||
15 | |||
16 | This versioning scheme is *neither*: | ||
17 | - A QEMU versioned machine type; a given version of QEMU will emulate | ||
18 | a given version of the platform. | ||
19 | - A reflection of level of SBSA (now SystemReady SR) support provided. | ||
20 | |||
21 | The version will increment on guest-visible functional changes only, | ||
22 | akin to a revision ID register found on a physical platform. | ||
23 | |||
24 | These properties are both introduced with the value 0. | ||
25 | (Hence, a machine where the DT is lacking these nodes is equivalent | ||
26 | to version 0.0.) | ||
27 | |||
28 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
29 | Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com | ||
30 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Cc: Radoslaw Biernacki <rad@semihalf.com> | ||
32 | Cc: Cédric Le Goater <clg@kaod.org> | ||
33 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
35 | --- | ||
36 | hw/arm/sbsa-ref.c | 14 ++++++++++++++ | ||
37 | 1 file changed, 14 insertions(+) | ||
38 | |||
39 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/hw/arm/sbsa-ref.c | 16 | --- a/tests/fp/fp-bench.c |
42 | +++ b/hw/arm/sbsa-ref.c | 17 | +++ b/tests/fp/fp-bench.c |
43 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms) | 18 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) |
44 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | 19 | { |
45 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | 20 | bench_func_t f; |
46 | 21 | ||
47 | + /* | 22 | + /* |
48 | + * This versioning scheme is for informing platform fw only. It is neither: | 23 | + * These implementation-defined choices for various things IEEE |
49 | + * - A QEMU versioned machine type; a given version of QEMU will emulate | 24 | + * doesn't specify match those used by the Arm architecture. |
50 | + * a given version of the platform. | ||
51 | + * - A reflection of level of SBSA (now SystemReady SR) support provided. | ||
52 | + * | ||
53 | + * machine-version-major: updated when changes breaking fw compatibility | ||
54 | + * are introduced. | ||
55 | + * machine-version-minor: updated when features are added that don't break | ||
56 | + * fw compatibility. | ||
57 | + */ | 25 | + */ |
58 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); | 26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); |
59 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0); | 27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); |
60 | + | 28 | |
61 | if (ms->numa_state->have_numa_distance) { | 29 | f = bench_funcs[operation][precision]; |
62 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); | 30 | g_assert(f); |
63 | uint32_t *matrix = g_malloc0(size); | 31 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c |
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/tests/fp/fp-test.c | ||
34 | +++ b/tests/fp/fp-test.c | ||
35 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
36 | { | ||
37 | unsigned int i; | ||
38 | |||
39 | + /* | ||
40 | + * These implementation-defined choices for various things IEEE | ||
41 | + * doesn't specify match those used by the Arm architecture. | ||
42 | + */ | ||
43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
44 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
45 | |||
46 | genCases_setLevel(test_level); | ||
47 | verCases_maxErrorCount = n_max_errors; | ||
64 | -- | 48 | -- |
65 | 2.25.1 | 49 | 2.34.1 |
66 | |||
67 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the FloatInfZeroNaNRule explicitly for the Arm target, |
---|---|---|---|
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
2 | 3 | ||
3 | The only portion of FEAT_Debugv8p2 that is relevant to QEMU | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | is CONTEXTIDR_EL2, which is also conditionally implemented | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | with FEAT_VHE. The rest of the debug extension concerns the | 6 | Message-id: 20241202131347.498124-6-peter.maydell@linaro.org |
6 | External debug interface, which is outside the scope of QEMU. | 7 | --- |
8 | target/arm/cpu.c | 3 +++ | ||
9 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
10 | 2 files changed, 4 insertions(+), 7 deletions(-) | ||
7 | 11 | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220506180242.216785-12-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | docs/system/arm/emulation.rst | 1 + | ||
14 | target/arm/cpu.c | 1 + | ||
15 | target/arm/cpu64.c | 1 + | ||
16 | target/arm/cpu_tcg.c | 2 ++ | ||
17 | 4 files changed, 5 insertions(+) | ||
18 | |||
19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/docs/system/arm/emulation.rst | ||
22 | +++ b/docs/system/arm/emulation.rst | ||
23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
24 | - FEAT_BTI (Branch Target Identification) | ||
25 | - FEAT_DIT (Data Independent Timing instructions) | ||
26 | - FEAT_DPB (DC CVAP instruction) | ||
27 | +- FEAT_Debugv8p2 (Debug changes for v8.2) | ||
28 | - FEAT_DotProd (Advanced SIMD dot product instructions) | ||
29 | - FEAT_FCMA (Floating-point complex number instructions) | ||
30 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | ||
31 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
32 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/target/arm/cpu.c | 14 | --- a/target/arm/cpu.c |
34 | +++ b/target/arm/cpu.c | 15 | +++ b/target/arm/cpu.c |
35 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
36 | * feature registers as well. | 17 | * * tininess-before-rounding |
18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then | ||
19 | * operand A over operand B (see FPProcessNaNs() pseudocode) | ||
20 | + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, | ||
21 | + * and the input NaN if it is signalling | ||
22 | */ | ||
23 | static void arm_set_default_fp_behaviours(float_status *s) | ||
24 | { | ||
25 | set_float_detect_tininess(float_tininess_before_rounding, s); | ||
26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | ||
27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
28 | } | ||
29 | |||
30 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) | ||
31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/fpu/softfloat-specialize.c.inc | ||
34 | +++ b/fpu/softfloat-specialize.c.inc | ||
35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
36 | /* | ||
37 | * Temporarily fall back to ifdef ladder | ||
37 | */ | 38 | */ |
38 | cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | 39 | -#if defined(TARGET_ARM) |
39 | + cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); | 40 | - /* |
40 | cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | 41 | - * For ARM, the (inf,zero,qnan) case returns the default NaN, |
41 | ID_AA64PFR0, EL3, 0); | 42 | - * but (inf,zero,snan) returns the input NaN. |
42 | } | 43 | - */ |
43 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 44 | - rule = float_infzeronan_dnan_if_qnan; |
44 | index XXXXXXX..XXXXXXX 100644 | 45 | -#elif defined(TARGET_MIPS) |
45 | --- a/target/arm/cpu64.c | 46 | +#if defined(TARGET_MIPS) |
46 | +++ b/target/arm/cpu64.c | 47 | if (snan_bit_is_one(status)) { |
47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 48 | /* |
48 | cpu->isar.id_aa64zfr0 = t; | 49 | * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) |
49 | |||
50 | t = cpu->isar.id_aa64dfr0; | ||
51 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ | ||
52 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | ||
53 | cpu->isar.id_aa64dfr0 = t; | ||
54 | |||
55 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/arm/cpu_tcg.c | ||
58 | +++ b/target/arm/cpu_tcg.c | ||
59 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
60 | cpu->isar.id_pfr2 = t; | ||
61 | |||
62 | t = cpu->isar.id_dfr0; | ||
63 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | ||
64 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | ||
65 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
66 | cpu->isar.id_dfr0 = t; | ||
67 | } | ||
68 | -- | 50 | -- |
69 | 2.25.1 | 51 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for s390, so we | ||
2 | can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-7-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/s390x/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/s390x/cpu.c | ||
15 | +++ b/target/s390x/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_float_detect_tininess(float_tininess_before_rounding, | ||
18 | &env->fpu_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
20 | + set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
21 | + &env->fpu_status); | ||
22 | /* fall through */ | ||
23 | case RESET_TYPE_S390_CPU_NORMAL: | ||
24 | env->psw.mask &= ~PSW_MASK_RI; | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | * a default NaN | ||
31 | */ | ||
32 | rule = float_infzeronan_dnan_never; | ||
33 | -#elif defined(TARGET_S390X) | ||
34 | - rule = float_infzeronan_dnan_always; | ||
35 | #endif | ||
36 | } | ||
37 | |||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the PPC target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/ppc/cpu_init.c | 7 +++++++ | ||
9 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
11 | |||
12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/ppc/cpu_init.c | ||
15 | +++ b/target/ppc/cpu_init.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | ||
20 | + /* | ||
21 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
22 | + * to return an input NaN if we have one (ie c) rather than generating | ||
23 | + * a default NaN | ||
24 | + */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
26 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); | ||
27 | |||
28 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { | ||
29 | ppc_spr_t *spr = &env->spr_cb[i]; | ||
30 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/fpu/softfloat-specialize.c.inc | ||
33 | +++ b/fpu/softfloat-specialize.c.inc | ||
34 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
35 | */ | ||
36 | rule = float_infzeronan_dnan_never; | ||
37 | } | ||
38 | -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
39 | +#elif defined(TARGET_SPARC) || \ | ||
40 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
41 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
42 | /* | ||
43 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
44 | * case sets InvalidOp and returns the input value 'c' | ||
45 | */ | ||
46 | - /* | ||
47 | - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
48 | - * to return an input NaN if we have one (ie c) rather than generating | ||
49 | - * a default NaN | ||
50 | - */ | ||
51 | rule = float_infzeronan_dnan_never; | ||
52 | #endif | ||
53 | } | ||
54 | -- | ||
55 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the MIPS target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-9-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/mips/fpu_helper.h | 9 +++++++++ | ||
9 | target/mips/msa.c | 4 ++++ | ||
10 | fpu/softfloat-specialize.c.inc | 16 +--------------- | ||
11 | 3 files changed, 14 insertions(+), 15 deletions(-) | ||
12 | |||
13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/mips/fpu_helper.h | ||
16 | +++ b/target/mips/fpu_helper.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env) | ||
18 | static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
19 | { | ||
20 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); | ||
21 | + FloatInfZeroNaNRule izn_rule; | ||
22 | |||
23 | /* | ||
24 | * With nan2008, SNaNs are silenced in the usual way. | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
26 | */ | ||
27 | set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); | ||
28 | set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); | ||
29 | + /* | ||
30 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
31 | + * case sets InvalidOp and returns the default NaN. | ||
32 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
33 | + * case sets InvalidOp and returns the input value 'c'. | ||
34 | + */ | ||
35 | + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | ||
36 | + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
37 | } | ||
38 | |||
39 | static inline void restore_fp_status(CPUMIPSState *env) | ||
40 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/mips/msa.c | ||
43 | +++ b/target/mips/msa.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
45 | |||
46 | /* set proper signanling bit meaning ("1" means "quiet") */ | ||
47 | set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); | ||
48 | + | ||
49 | + /* Inf * 0 + NaN returns the input NaN */ | ||
50 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, | ||
51 | + &env->active_tc.msa_fp_status); | ||
52 | } | ||
53 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/fpu/softfloat-specialize.c.inc | ||
56 | +++ b/fpu/softfloat-specialize.c.inc | ||
57 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
58 | /* | ||
59 | * Temporarily fall back to ifdef ladder | ||
60 | */ | ||
61 | -#if defined(TARGET_MIPS) | ||
62 | - if (snan_bit_is_one(status)) { | ||
63 | - /* | ||
64 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
65 | - * case sets InvalidOp and returns the default NaN | ||
66 | - */ | ||
67 | - rule = float_infzeronan_dnan_always; | ||
68 | - } else { | ||
69 | - /* | ||
70 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
71 | - * case sets InvalidOp and returns the input value 'c' | ||
72 | - */ | ||
73 | - rule = float_infzeronan_dnan_never; | ||
74 | - } | ||
75 | -#elif defined(TARGET_SPARC) || \ | ||
76 | +#if defined(TARGET_SPARC) || \ | ||
77 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
78 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
79 | /* | ||
80 | -- | ||
81 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the SPARC target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-10-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | * the CPU state struct so it won't get zeroed on reset. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
22 | |||
23 | cpu_exec_realizefn(cs, &local_err); | ||
24 | if (local_err != NULL) { | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | /* | ||
31 | * Temporarily fall back to ifdef ladder | ||
32 | */ | ||
33 | -#if defined(TARGET_SPARC) || \ | ||
34 | - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
35 | +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
36 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
37 | /* | ||
38 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the xtensa target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-11-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/xtensa/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 +- | ||
10 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
11 | |||
12 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/xtensa/cpu.c | ||
15 | +++ b/target/xtensa/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | reset_mmu(env); | ||
18 | cs->halted = env->runstall; | ||
19 | #endif | ||
20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
22 | set_no_signaling_nans(!dfpu, &env->fp_status); | ||
23 | xtensa_use_first_nan(env, !dfpu); | ||
24 | } | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | /* | ||
31 | * Temporarily fall back to ifdef ladder | ||
32 | */ | ||
33 | -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
34 | +#if defined(TARGET_HPPA) || \ | ||
35 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
36 | /* | ||
37 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the x86 target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-12-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/i386/tcg/fpu_helper.c | 7 +++++++ | ||
8 | fpu/softfloat-specialize.c.inc | 2 +- | ||
9 | 2 files changed, 8 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/i386/tcg/fpu_helper.c | ||
14 | +++ b/target/i386/tcg/fpu_helper.c | ||
15 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); | ||
19 | + /* | ||
20 | + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 | ||
21 | + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is | ||
22 | + * specified -- for 0 * inf + NaN the input NaN is selected, and if | ||
23 | + * there are multiple input NaNs they are selected in the order a, b, c. | ||
24 | + */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
26 | } | ||
27 | |||
28 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/fpu/softfloat-specialize.c.inc | ||
32 | +++ b/fpu/softfloat-specialize.c.inc | ||
33 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
34 | * Temporarily fall back to ifdef ladder | ||
35 | */ | ||
36 | #if defined(TARGET_HPPA) || \ | ||
37 | - defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
38 | + defined(TARGET_LOONGARCH) | ||
39 | /* | ||
40 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
41 | * case sets InvalidOp and returns the input value 'c' | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the loongarch target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-13-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/loongarch/tcg/fpu_helper.c | 5 +++++ | ||
8 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
9 | 2 files changed, 6 insertions(+), 6 deletions(-) | ||
10 | |||
11 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/loongarch/tcg/fpu_helper.c | ||
14 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
15 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
16 | &env->fp_status); | ||
17 | set_flush_to_zero(0, &env->fp_status); | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
19 | + /* | ||
20 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
21 | + * case sets InvalidOp and returns the input value 'c' | ||
22 | + */ | ||
23 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
24 | } | ||
25 | |||
26 | int ieee_ex_to_loongarch(int xcpt) | ||
27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/fpu/softfloat-specialize.c.inc | ||
30 | +++ b/fpu/softfloat-specialize.c.inc | ||
31 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
32 | /* | ||
33 | * Temporarily fall back to ifdef ladder | ||
34 | */ | ||
35 | -#if defined(TARGET_HPPA) || \ | ||
36 | - defined(TARGET_LOONGARCH) | ||
37 | - /* | ||
38 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
39 | - * case sets InvalidOp and returns the input value 'c' | ||
40 | - */ | ||
41 | +#if defined(TARGET_HPPA) | ||
42 | rule = float_infzeronan_dnan_never; | ||
43 | #endif | ||
44 | } | ||
45 | -- | ||
46 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the HPPA target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | As this is the last target to be converted to explicitly setting | ||
5 | the rule, we can remove the fallback code in pickNaNMulAdd() | ||
6 | entirely. | ||
7 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20241202131347.498124-14-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/hppa/fpu_helper.c | 2 ++ | ||
13 | fpu/softfloat-specialize.c.inc | 13 +------------ | ||
14 | 2 files changed, 3 insertions(+), 12 deletions(-) | ||
15 | |||
16 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/hppa/fpu_helper.c | ||
19 | +++ b/target/hppa/fpu_helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
21 | * HPPA does note implement a CPU reset method at all... | ||
22 | */ | ||
23 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
24 | + /* For inf * 0 + NaN, return the input NaN */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
26 | } | ||
27 | |||
28 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) | ||
29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/fpu/softfloat-specialize.c.inc | ||
32 | +++ b/fpu/softfloat-specialize.c.inc | ||
33 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
34 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
35 | bool infzero, float_status *status) | ||
36 | { | ||
37 | - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
38 | - | ||
39 | /* | ||
40 | * We guarantee not to require the target to tell us how to | ||
41 | * pick a NaN if we're always returning the default NaN. | ||
42 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
43 | */ | ||
44 | assert(!status->default_nan_mode); | ||
45 | |||
46 | - if (rule == float_infzeronan_none) { | ||
47 | - /* | ||
48 | - * Temporarily fall back to ifdef ladder | ||
49 | - */ | ||
50 | -#if defined(TARGET_HPPA) | ||
51 | - rule = float_infzeronan_dnan_never; | ||
52 | -#endif | ||
53 | - } | ||
54 | - | ||
55 | if (infzero) { | ||
56 | /* | ||
57 | * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
58 | * and some return the input NaN. | ||
59 | */ | ||
60 | - switch (rule) { | ||
61 | + switch (status->float_infzeronan_rule) { | ||
62 | case float_infzeronan_dnan_never: | ||
63 | return 2; | ||
64 | case float_infzeronan_dnan_always: | ||
65 | -- | ||
66 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The new implementation of pickNaNMulAdd() will find it convenient | ||
2 | to know whether at least one of the three arguments to the muladd | ||
3 | was a signaling NaN. We already calculate that in the caller, | ||
4 | so pass it in as a new bool have_snan. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-15-peter.maydell@linaro.org | ||
9 | --- | ||
10 | fpu/softfloat-parts.c.inc | 5 +++-- | ||
11 | fpu/softfloat-specialize.c.inc | 2 +- | ||
12 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/fpu/softfloat-parts.c.inc | ||
17 | +++ b/fpu/softfloat-parts.c.inc | ||
18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
19 | { | ||
20 | int which; | ||
21 | bool infzero = (ab_mask == float_cmask_infzero); | ||
22 | + bool have_snan = (abc_mask & float_cmask_snan); | ||
23 | |||
24 | - if (unlikely(abc_mask & float_cmask_snan)) { | ||
25 | + if (unlikely(have_snan)) { | ||
26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
27 | } | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
30 | if (s->default_nan_mode) { | ||
31 | which = 3; | ||
32 | } else { | ||
33 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
34 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); | ||
35 | } | ||
36 | |||
37 | if (which == 3) { | ||
38 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/fpu/softfloat-specialize.c.inc | ||
41 | +++ b/fpu/softfloat-specialize.c.inc | ||
42 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
43 | | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | ||
44 | *----------------------------------------------------------------------------*/ | ||
45 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
46 | - bool infzero, float_status *status) | ||
47 | + bool infzero, bool have_snan, float_status *status) | ||
48 | { | ||
49 | /* | ||
50 | * We guarantee not to require the target to tell us how to | ||
51 | -- | ||
52 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | IEEE 758 does not define a fixed rule for which NaN to pick as the |
---|---|---|---|
2 | 2 | result if both operands of a 3-operand fused multiply-add operation | |
3 | When the PPTT table is built, the CPU topology is re-calculated, but | 3 | are NaNs. As a result different architectures have ended up with |
4 | it's unecessary because the CPU topology has been populated in | 4 | different rules for propagating NaNs. |
5 | virt_possible_cpu_arch_ids() on arm/virt machine. | 5 | |
6 | 6 | QEMU currently hardcodes the NaN propagation logic into the binary | |
7 | This reworks build_pptt() to avoid by reusing the existing IDs in | 7 | because pickNaNMulAdd() has an ifdef ladder for different targets. |
8 | ms->possible_cpus. Currently, the only user of build_pptt() is | 8 | We want to make the propagation rule instead be selectable at |
9 | arm/virt machine. | 9 | runtime, because: |
10 | 10 | * this will let us have multiple targets in one QEMU binary | |
11 | Signed-off-by: Gavin Shan <gshan@redhat.com> | 11 | * the Arm FEAT_AFP architectural feature includes letting |
12 | Tested-by: Yanan Wang <wangyanan55@huawei.com> | 12 | the guest select a NaN propagation rule at runtime |
13 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | 13 | |
14 | Acked-by: Igor Mammedov <imammedo@redhat.com> | 14 | In this commit we add an enum for the propagation rule, the field in |
15 | Acked-by: Michael S. Tsirkin <mst@redhat.com> | 15 | float_status, and the corresponding getters and setters. We change |
16 | Message-id: 20220503140304.855514-7-gshan@redhat.com | 16 | pickNaNMulAdd to honour this, but because all targets still leave |
17 | this field at its default 0 value, the fallback logic will pick the | ||
18 | rule type with the old ifdef ladder. | ||
19 | |||
20 | It's valid not to set a propagation rule if default_nan_mode is | ||
21 | enabled, because in that case there's no need to pick a NaN; all the | ||
22 | callers of pickNaNMulAdd() catch this case and skip calling it. | ||
23 | |||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-id: 20241202131347.498124-16-peter.maydell@linaro.org | ||
18 | --- | 27 | --- |
19 | hw/acpi/aml-build.c | 111 +++++++++++++++++++------------------------- | 28 | include/fpu/softfloat-helpers.h | 11 +++ |
20 | 1 file changed, 48 insertions(+), 63 deletions(-) | 29 | include/fpu/softfloat-types.h | 55 +++++++++++ |
21 | 30 | fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ | |
22 | diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c | 31 | 3 files changed, 107 insertions(+), 126 deletions(-) |
32 | |||
33 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/hw/acpi/aml-build.c | 35 | --- a/include/fpu/softfloat-helpers.h |
25 | +++ b/hw/acpi/aml-build.c | 36 | +++ b/include/fpu/softfloat-helpers.h |
26 | @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, | 37 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, |
27 | const char *oem_id, const char *oem_table_id) | 38 | status->float_2nan_prop_rule = rule; |
39 | } | ||
40 | |||
41 | +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, | ||
42 | + float_status *status) | ||
43 | +{ | ||
44 | + status->float_3nan_prop_rule = rule; | ||
45 | +} | ||
46 | + | ||
47 | static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, | ||
48 | float_status *status) | ||
28 | { | 49 | { |
29 | MachineClass *mc = MACHINE_GET_CLASS(ms); | 50 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) |
30 | - GQueue *list = g_queue_new(); | 51 | return status->float_2nan_prop_rule; |
31 | - guint pptt_start = table_data->len; | 52 | } |
32 | - guint parent_offset; | 53 | |
33 | - guint length, i; | 54 | +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) |
34 | - int uid = 0; | 55 | +{ |
35 | - int socket; | 56 | + return status->float_3nan_prop_rule; |
36 | + CPUArchIdList *cpus = ms->possible_cpus; | 57 | +} |
37 | + int64_t socket_id = -1, cluster_id = -1, core_id = -1; | 58 | + |
38 | + uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0; | 59 | static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) |
39 | + uint32_t pptt_start = table_data->len; | 60 | { |
40 | + int n; | 61 | return status->float_infzeronan_rule; |
41 | AcpiTable table = { .sig = "PPTT", .rev = 2, | 62 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h |
42 | .oem_id = oem_id, .oem_table_id = oem_table_id }; | 63 | index XXXXXXX..XXXXXXX 100644 |
43 | 64 | --- a/include/fpu/softfloat-types.h | |
44 | acpi_table_begin(&table, table_data); | 65 | +++ b/include/fpu/softfloat-types.h |
45 | 66 | @@ -XXX,XX +XXX,XX @@ this code that are retained. | |
46 | - for (socket = 0; socket < ms->smp.sockets; socket++) { | 67 | #ifndef SOFTFLOAT_TYPES_H |
47 | - g_queue_push_tail(list, | 68 | #define SOFTFLOAT_TYPES_H |
48 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | 69 | |
49 | - build_processor_hierarchy_node( | 70 | +#include "hw/registerfields.h" |
50 | - table_data, | 71 | + |
51 | - /* | 72 | /* |
52 | - * Physical package - represents the boundary | 73 | * Software IEC/IEEE floating-point types. |
53 | - * of a physical package | 74 | */ |
54 | - */ | 75 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { |
55 | - (1 << 0), | 76 | float_2nan_prop_x87, |
56 | - 0, socket, NULL, 0); | 77 | } Float2NaNPropRule; |
57 | - } | 78 | |
58 | - | 79 | +/* |
59 | - if (mc->smp_props.clusters_supported) { | 80 | + * 3-input NaN propagation rule, for fused multiply-add. Individual |
60 | - length = g_queue_get_length(list); | 81 | + * architectures have different rules for which input NaN is |
61 | - for (i = 0; i < length; i++) { | 82 | + * propagated to the output when there is more than one NaN on the |
62 | - int cluster; | 83 | + * input. |
63 | - | 84 | + * |
64 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | 85 | + * If default_nan_mode is enabled then it is valid not to set a NaN |
65 | - for (cluster = 0; cluster < ms->smp.clusters; cluster++) { | 86 | + * propagation rule, because the softfloat code guarantees not to try |
66 | - g_queue_push_tail(list, | 87 | + * to pick a NaN to propagate in default NaN mode. When not in |
67 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | 88 | + * default-NaN mode, it is an error for the target not to set the rule |
68 | - build_processor_hierarchy_node( | 89 | + * in float_status if it uses a muladd, and we will assert if we need |
69 | - table_data, | 90 | + * to handle an input NaN and no rule was selected. |
70 | - (0 << 0), /* not a physical package */ | 91 | + * |
71 | - parent_offset, cluster, NULL, 0); | 92 | + * The naming scheme for Float3NaNPropRule values is: |
72 | - } | 93 | + * float_3nan_prop_s_abc: |
73 | + /* | 94 | + * = "Prefer SNaN over QNaN, then operand A over B over C" |
74 | + * This works with the assumption that cpus[n].props.*_id has been | 95 | + * float_3nan_prop_abc: |
75 | + * sorted from top to down levels in mc->possible_cpu_arch_ids(). | 96 | + * = "Prefer A over B over C regardless of SNaN vs QNAN" |
76 | + * Otherwise, the unexpected and duplicated containers will be | 97 | + * |
77 | + * created. | 98 | + * For QEMU, the multiply-add operation is A * B + C. |
78 | + */ | 99 | + */ |
79 | + for (n = 0; n < cpus->len; n++) { | 100 | + |
80 | + if (cpus->cpus[n].props.socket_id != socket_id) { | 101 | +/* |
81 | + assert(cpus->cpus[n].props.socket_id > socket_id); | 102 | + * We set the Float3NaNPropRule enum values up so we can select the |
82 | + socket_id = cpus->cpus[n].props.socket_id; | 103 | + * right value in pickNaNMulAdd in a data driven way. |
83 | + cluster_id = -1; | 104 | + */ |
84 | + core_id = -1; | 105 | +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ |
85 | + socket_offset = table_data->len - pptt_start; | 106 | +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ |
86 | + build_processor_hierarchy_node(table_data, | 107 | +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ |
87 | + (1 << 0), /* Physical package */ | 108 | +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ |
88 | + 0, socket_id, NULL, 0); | 109 | + |
89 | } | 110 | +#define PROPRULE(X, Y, Z) \ |
90 | - } | 111 | + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) |
91 | 112 | + | |
92 | - length = g_queue_get_length(list); | 113 | +typedef enum __attribute__((__packed__)) { |
93 | - for (i = 0; i < length; i++) { | 114 | + float_3nan_prop_none = 0, /* No propagation rule specified */ |
94 | - int core; | 115 | + float_3nan_prop_abc = PROPRULE(0, 1, 2), |
95 | - | 116 | + float_3nan_prop_acb = PROPRULE(0, 2, 1), |
96 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | 117 | + float_3nan_prop_bac = PROPRULE(1, 0, 2), |
97 | - for (core = 0; core < ms->smp.cores; core++) { | 118 | + float_3nan_prop_bca = PROPRULE(1, 2, 0), |
98 | - if (ms->smp.threads > 1) { | 119 | + float_3nan_prop_cab = PROPRULE(2, 0, 1), |
99 | - g_queue_push_tail(list, | 120 | + float_3nan_prop_cba = PROPRULE(2, 1, 0), |
100 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | 121 | + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, |
101 | - build_processor_hierarchy_node( | 122 | + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, |
102 | - table_data, | 123 | + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, |
103 | - (0 << 0), /* not a physical package */ | 124 | + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, |
104 | - parent_offset, core, NULL, 0); | 125 | + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, |
105 | - } else { | 126 | + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, |
106 | - build_processor_hierarchy_node( | 127 | +} Float3NaNPropRule; |
107 | - table_data, | 128 | + |
108 | - (1 << 1) | /* ACPI Processor ID valid */ | 129 | +#undef PROPRULE |
109 | - (1 << 3), /* Node is a Leaf */ | 130 | + |
110 | - parent_offset, uid++, NULL, 0); | 131 | /* |
111 | + if (mc->smp_props.clusters_supported) { | 132 | * Rule for result of fused multiply-add 0 * Inf + NaN. |
112 | + if (cpus->cpus[n].props.cluster_id != cluster_id) { | 133 | * This must be a NaN, but implementations differ on whether this |
113 | + assert(cpus->cpus[n].props.cluster_id > cluster_id); | 134 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { |
114 | + cluster_id = cpus->cpus[n].props.cluster_id; | 135 | FloatRoundMode float_rounding_mode; |
115 | + core_id = -1; | 136 | FloatX80RoundPrec floatx80_rounding_precision; |
116 | + cluster_offset = table_data->len - pptt_start; | 137 | Float2NaNPropRule float_2nan_prop_rule; |
117 | + build_processor_hierarchy_node(table_data, | 138 | + Float3NaNPropRule float_3nan_prop_rule; |
118 | + (0 << 0), /* Not a physical package */ | 139 | FloatInfZeroNaNRule float_infzeronan_rule; |
119 | + socket_offset, cluster_id, NULL, 0); | 140 | bool tininess_before_rounding; |
120 | } | 141 | /* should denormalised results go to zero and set the inexact flag? */ |
121 | + } else { | 142 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
122 | + cluster_offset = socket_offset; | 143 | index XXXXXXX..XXXXXXX 100644 |
123 | } | 144 | --- a/fpu/softfloat-specialize.c.inc |
124 | - } | 145 | +++ b/fpu/softfloat-specialize.c.inc |
125 | 146 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | |
126 | - length = g_queue_get_length(list); | 147 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
127 | - for (i = 0; i < length; i++) { | 148 | bool infzero, bool have_snan, float_status *status) |
128 | - int thread; | 149 | { |
129 | + if (ms->smp.threads == 1) { | 150 | + FloatClass cls[3] = { a_cls, b_cls, c_cls }; |
130 | + build_processor_hierarchy_node(table_data, | 151 | + Float3NaNPropRule rule = status->float_3nan_prop_rule; |
131 | + (1 << 1) | /* ACPI Processor ID valid */ | 152 | + int which; |
132 | + (1 << 3), /* Node is a Leaf */ | 153 | + |
133 | + cluster_offset, n, NULL, 0); | 154 | /* |
134 | + } else { | 155 | * We guarantee not to require the target to tell us how to |
135 | + if (cpus->cpus[n].props.core_id != core_id) { | 156 | * pick a NaN if we're always returning the default NaN. |
136 | + assert(cpus->cpus[n].props.core_id > core_id); | 157 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
137 | + core_id = cpus->cpus[n].props.core_id; | ||
138 | + core_offset = table_data->len - pptt_start; | ||
139 | + build_processor_hierarchy_node(table_data, | ||
140 | + (0 << 0), /* Not a physical package */ | ||
141 | + cluster_offset, core_id, NULL, 0); | ||
142 | + } | ||
143 | |||
144 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
145 | - for (thread = 0; thread < ms->smp.threads; thread++) { | ||
146 | - build_processor_hierarchy_node( | ||
147 | - table_data, | ||
148 | + build_processor_hierarchy_node(table_data, | ||
149 | (1 << 1) | /* ACPI Processor ID valid */ | ||
150 | (1 << 2) | /* Processor is a Thread */ | ||
151 | (1 << 3), /* Node is a Leaf */ | ||
152 | - parent_offset, uid++, NULL, 0); | ||
153 | + core_offset, n, NULL, 0); | ||
154 | } | 158 | } |
155 | } | 159 | } |
156 | 160 | ||
157 | - g_queue_free(list); | 161 | + if (rule == float_3nan_prop_none) { |
158 | acpi_table_end(linker, &table); | 162 | #if defined(TARGET_ARM) |
163 | - | ||
164 | - /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
165 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
166 | - */ | ||
167 | - if (is_snan(c_cls)) { | ||
168 | - return 2; | ||
169 | - } else if (is_snan(a_cls)) { | ||
170 | - return 0; | ||
171 | - } else if (is_snan(b_cls)) { | ||
172 | - return 1; | ||
173 | - } else if (is_qnan(c_cls)) { | ||
174 | - return 2; | ||
175 | - } else if (is_qnan(a_cls)) { | ||
176 | - return 0; | ||
177 | - } else { | ||
178 | - return 1; | ||
179 | - } | ||
180 | + /* | ||
181 | + * This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
182 | + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b | ||
183 | + */ | ||
184 | + rule = float_3nan_prop_s_cab; | ||
185 | #elif defined(TARGET_MIPS) | ||
186 | - if (snan_bit_is_one(status)) { | ||
187 | - /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
188 | - if (is_snan(a_cls)) { | ||
189 | - return 0; | ||
190 | - } else if (is_snan(b_cls)) { | ||
191 | - return 1; | ||
192 | - } else if (is_snan(c_cls)) { | ||
193 | - return 2; | ||
194 | - } else if (is_qnan(a_cls)) { | ||
195 | - return 0; | ||
196 | - } else if (is_qnan(b_cls)) { | ||
197 | - return 1; | ||
198 | + if (snan_bit_is_one(status)) { | ||
199 | + rule = float_3nan_prop_s_abc; | ||
200 | } else { | ||
201 | - return 2; | ||
202 | + rule = float_3nan_prop_s_cab; | ||
203 | } | ||
204 | - } else { | ||
205 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
206 | - if (is_snan(c_cls)) { | ||
207 | - return 2; | ||
208 | - } else if (is_snan(a_cls)) { | ||
209 | - return 0; | ||
210 | - } else if (is_snan(b_cls)) { | ||
211 | - return 1; | ||
212 | - } else if (is_qnan(c_cls)) { | ||
213 | - return 2; | ||
214 | - } else if (is_qnan(a_cls)) { | ||
215 | - return 0; | ||
216 | - } else { | ||
217 | - return 1; | ||
218 | - } | ||
219 | - } | ||
220 | #elif defined(TARGET_LOONGARCH64) | ||
221 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
222 | - if (is_snan(c_cls)) { | ||
223 | - return 2; | ||
224 | - } else if (is_snan(a_cls)) { | ||
225 | - return 0; | ||
226 | - } else if (is_snan(b_cls)) { | ||
227 | - return 1; | ||
228 | - } else if (is_qnan(c_cls)) { | ||
229 | - return 2; | ||
230 | - } else if (is_qnan(a_cls)) { | ||
231 | - return 0; | ||
232 | - } else { | ||
233 | - return 1; | ||
234 | - } | ||
235 | + rule = float_3nan_prop_s_cab; | ||
236 | #elif defined(TARGET_PPC) | ||
237 | - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
238 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
239 | - */ | ||
240 | - if (is_nan(a_cls)) { | ||
241 | - return 0; | ||
242 | - } else if (is_nan(c_cls)) { | ||
243 | - return 2; | ||
244 | - } else { | ||
245 | - return 1; | ||
246 | - } | ||
247 | + /* | ||
248 | + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
249 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
250 | + */ | ||
251 | + rule = float_3nan_prop_acb; | ||
252 | #elif defined(TARGET_S390X) | ||
253 | - if (is_snan(a_cls)) { | ||
254 | - return 0; | ||
255 | - } else if (is_snan(b_cls)) { | ||
256 | - return 1; | ||
257 | - } else if (is_snan(c_cls)) { | ||
258 | - return 2; | ||
259 | - } else if (is_qnan(a_cls)) { | ||
260 | - return 0; | ||
261 | - } else if (is_qnan(b_cls)) { | ||
262 | - return 1; | ||
263 | - } else { | ||
264 | - return 2; | ||
265 | - } | ||
266 | + rule = float_3nan_prop_s_abc; | ||
267 | #elif defined(TARGET_SPARC) | ||
268 | - /* Prefer SNaN over QNaN, order C, B, A. */ | ||
269 | - if (is_snan(c_cls)) { | ||
270 | - return 2; | ||
271 | - } else if (is_snan(b_cls)) { | ||
272 | - return 1; | ||
273 | - } else if (is_snan(a_cls)) { | ||
274 | - return 0; | ||
275 | - } else if (is_qnan(c_cls)) { | ||
276 | - return 2; | ||
277 | - } else if (is_qnan(b_cls)) { | ||
278 | - return 1; | ||
279 | - } else { | ||
280 | - return 0; | ||
281 | - } | ||
282 | + rule = float_3nan_prop_s_cba; | ||
283 | #elif defined(TARGET_XTENSA) | ||
284 | - /* | ||
285 | - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
286 | - * an input NaN if we have one (ie c). | ||
287 | - */ | ||
288 | - if (status->use_first_nan) { | ||
289 | - if (is_nan(a_cls)) { | ||
290 | - return 0; | ||
291 | - } else if (is_nan(b_cls)) { | ||
292 | - return 1; | ||
293 | + if (status->use_first_nan) { | ||
294 | + rule = float_3nan_prop_abc; | ||
295 | } else { | ||
296 | - return 2; | ||
297 | + rule = float_3nan_prop_cba; | ||
298 | } | ||
299 | - } else { | ||
300 | - if (is_nan(c_cls)) { | ||
301 | - return 2; | ||
302 | - } else if (is_nan(b_cls)) { | ||
303 | - return 1; | ||
304 | - } else { | ||
305 | - return 0; | ||
306 | - } | ||
307 | - } | ||
308 | #else | ||
309 | - /* A default implementation: prefer a to b to c. | ||
310 | - * This is unlikely to actually match any real implementation. | ||
311 | - */ | ||
312 | - if (is_nan(a_cls)) { | ||
313 | - return 0; | ||
314 | - } else if (is_nan(b_cls)) { | ||
315 | - return 1; | ||
316 | - } else { | ||
317 | - return 2; | ||
318 | - } | ||
319 | + rule = float_3nan_prop_abc; | ||
320 | #endif | ||
321 | + } | ||
322 | + | ||
323 | + assert(rule != float_3nan_prop_none); | ||
324 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
325 | + /* We have at least one SNaN input and should prefer it */ | ||
326 | + do { | ||
327 | + which = rule & R_3NAN_1ST_MASK; | ||
328 | + rule >>= R_3NAN_1ST_LENGTH; | ||
329 | + } while (!is_snan(cls[which])); | ||
330 | + } else { | ||
331 | + do { | ||
332 | + which = rule & R_3NAN_1ST_MASK; | ||
333 | + rule >>= R_3NAN_1ST_LENGTH; | ||
334 | + } while (!is_nan(cls[which])); | ||
335 | + } | ||
336 | + return which; | ||
159 | } | 337 | } |
160 | 338 | ||
339 | /*---------------------------------------------------------------------------- | ||
161 | -- | 340 | -- |
162 | 2.25.1 | 341 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Explicitly set a rule in the softfloat tests for propagating NaNs in |
---|---|---|---|
2 | the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and | ||
3 | so we should select here the Arm rule of float_3nan_prop_s_cab. | ||
2 | 4 | ||
3 | This feature is AArch64 only, and applies to physical SErrors, | ||
4 | which QEMU does not implement, thus the feature is a nop. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-19-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-17-peter.maydell@linaro.org | ||
10 | --- | 8 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 9 | tests/fp/fp-bench.c | 1 + |
12 | target/arm/cpu64.c | 1 + | 10 | tests/fp/fp-test.c | 1 + |
13 | 2 files changed, 2 insertions(+) | 11 | 2 files changed, 2 insertions(+) |
14 | 12 | ||
15 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 13 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c |
16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/docs/system/arm/emulation.rst | 15 | --- a/tests/fp/fp-bench.c |
18 | +++ b/docs/system/arm/emulation.rst | 16 | +++ b/tests/fp/fp-bench.c |
19 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 17 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) |
20 | - FEAT_FlagM2 (Enhancements to flag manipulation instructions) | 18 | * doesn't specify match those used by the Arm architecture. |
21 | - FEAT_HPDS (Hierarchical permission disables) | 19 | */ |
22 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) | 20 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); |
23 | +- FEAT_IESB (Implicit error synchronization event) | 21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); |
24 | - FEAT_JSCVT (JavaScript conversion instructions) | 22 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); |
25 | - FEAT_LOR (Limited ordering regions) | 23 | |
26 | - FEAT_LPA (Large Physical Address space) | 24 | f = bench_funcs[operation][precision]; |
27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 25 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c |
28 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/target/arm/cpu64.c | 27 | --- a/tests/fp/fp-test.c |
30 | +++ b/target/arm/cpu64.c | 28 | +++ b/tests/fp/fp-test.c |
31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 29 | @@ -XXX,XX +XXX,XX @@ void run_test(void) |
32 | t = cpu->isar.id_aa64mmfr2; | 30 | * doesn't specify match those used by the Arm architecture. |
33 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | 31 | */ |
34 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | 32 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); |
35 | + t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ | 33 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); |
36 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | 34 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); |
37 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | 35 | |
38 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | 36 | genCases_setLevel(test_level); |
39 | -- | 37 | -- |
40 | 2.25.1 | 38 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the Float3NaNPropRule explicitly for Arm, and remove the |
---|---|---|---|
2 | ifdef from pickNaNMulAdd(). | ||
2 | 3 | ||
3 | Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 | ||
4 | during arm_cpu_realizefn. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-11-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-18-peter.maydell@linaro.org | ||
10 | --- | 7 | --- |
11 | target/arm/cpu.c | 22 +++++++++++++--------- | 8 | target/arm/cpu.c | 5 +++++ |
12 | 1 file changed, 13 insertions(+), 9 deletions(-) | 9 | fpu/softfloat-specialize.c.inc | 8 +------- |
10 | 2 files changed, 6 insertions(+), 7 deletions(-) | ||
13 | 11 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 14 | --- a/target/arm/cpu.c |
17 | +++ b/target/arm/cpu.c | 15 | +++ b/target/arm/cpu.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
19 | */ | 17 | * * tininess-before-rounding |
20 | unset_feature(env, ARM_FEATURE_EL3); | 18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then |
21 | 19 | * operand A over operand B (see FPProcessNaNs() pseudocode) | |
22 | - /* Disable the security extension feature bits in the processor feature | 20 | + * * 3-input NaN propagation prefers SNaN over QNaN, and then |
23 | - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. | 21 | + * operand C over A over B (see FPProcessNaNs3() pseudocode, |
24 | + /* | 22 | + * but note that for QEMU muladd is a * b + c, whereas for |
25 | + * Disable the security extension feature bits in the processor | 23 | + * the pseudocode function the arguments are in the order c, a, b. |
26 | + * feature registers as well. | 24 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, |
27 | */ | 25 | * and the input NaN if it is signalling |
28 | - cpu->isar.id_pfr1 &= ~0xf0; | 26 | */ |
29 | - cpu->isar.id_aa64pfr0 &= ~0xf000; | 27 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) |
30 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | 28 | { |
31 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | 29 | set_float_detect_tininess(float_tininess_before_rounding, s); |
32 | + ID_AA64PFR0, EL3, 0); | 30 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); |
31 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); | ||
32 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
33 | } | ||
34 | |||
35 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/fpu/softfloat-specialize.c.inc | ||
38 | +++ b/fpu/softfloat-specialize.c.inc | ||
39 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
33 | } | 40 | } |
34 | 41 | ||
35 | if (!cpu->has_el2) { | 42 | if (rule == float_3nan_prop_none) { |
36 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 43 | -#if defined(TARGET_ARM) |
37 | } | 44 | - /* |
38 | 45 | - * This looks different from the ARM ARM pseudocode, because the ARM ARM | |
39 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | 46 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b |
40 | - /* Disable the hypervisor feature bits in the processor feature | 47 | - */ |
41 | - * registers if we don't have EL2. These are id_pfr1[15:12] and | 48 | - rule = float_3nan_prop_s_cab; |
42 | - * id_aa64pfr0_el1[11:8]. | 49 | -#elif defined(TARGET_MIPS) |
43 | + /* | 50 | +#if defined(TARGET_MIPS) |
44 | + * Disable the hypervisor feature bits in the processor feature | 51 | if (snan_bit_is_one(status)) { |
45 | + * registers if we don't have EL2. | 52 | rule = float_3nan_prop_s_abc; |
46 | */ | 53 | } else { |
47 | - cpu->isar.id_aa64pfr0 &= ~0xf00; | ||
48 | - cpu->isar.id_pfr1 &= ~0xf000; | ||
49 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
50 | + ID_AA64PFR0, EL2, 0); | ||
51 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, | ||
52 | + ID_PFR1, VIRTUALIZATION, 0); | ||
53 | } | ||
54 | |||
55 | #ifndef CONFIG_USER_ONLY | ||
56 | -- | 54 | -- |
57 | 2.25.1 | 55 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for loongarch, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-19-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/loongarch/tcg/fpu_helper.c | 1 + | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/loongarch/tcg/fpu_helper.c | ||
15 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
17 | * case sets InvalidOp and returns the input value 'c' | ||
18 | */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); | ||
21 | } | ||
22 | |||
23 | int ieee_ex_to_loongarch(int xcpt) | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
29 | } else { | ||
30 | rule = float_3nan_prop_s_cab; | ||
31 | } | ||
32 | -#elif defined(TARGET_LOONGARCH64) | ||
33 | - rule = float_3nan_prop_s_cab; | ||
34 | #elif defined(TARGET_PPC) | ||
35 | /* | ||
36 | * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for PPC, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-20-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/ppc/cpu_init.c | 8 ++++++++ | ||
9 | fpu/softfloat-specialize.c.inc | 6 ------ | ||
10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
11 | |||
12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/ppc/cpu_init.c | ||
15 | +++ b/target/ppc/cpu_init.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | ||
20 | + /* | ||
21 | + * NaN propagation for fused multiply-add: | ||
22 | + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
23 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
24 | + * whereas QEMU labels the operands as (a * b) + c. | ||
25 | + */ | ||
26 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); | ||
27 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); | ||
28 | /* | ||
29 | * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
30 | * to return an input NaN if we have one (ie c) rather than generating | ||
31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/fpu/softfloat-specialize.c.inc | ||
34 | +++ b/fpu/softfloat-specialize.c.inc | ||
35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
36 | } else { | ||
37 | rule = float_3nan_prop_s_cab; | ||
38 | } | ||
39 | -#elif defined(TARGET_PPC) | ||
40 | - /* | ||
41 | - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
42 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
43 | - */ | ||
44 | - rule = float_3nan_prop_acb; | ||
45 | #elif defined(TARGET_S390X) | ||
46 | rule = float_3nan_prop_s_abc; | ||
47 | #elif defined(TARGET_SPARC) | ||
48 | -- | ||
49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for s390x, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-21-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/s390x/cpu.c | 1 + | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/s390x/cpu.c | ||
15 | +++ b/target/s390x/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_float_detect_tininess(float_tininess_before_rounding, | ||
18 | &env->fpu_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
20 | + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
21 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
22 | &env->fpu_status); | ||
23 | /* fall through */ | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
29 | } else { | ||
30 | rule = float_3nan_prop_s_cab; | ||
31 | } | ||
32 | -#elif defined(TARGET_S390X) | ||
33 | - rule = float_3nan_prop_s_abc; | ||
34 | #elif defined(TARGET_SPARC) | ||
35 | rule = float_3nan_prop_s_cba; | ||
36 | #elif defined(TARGET_XTENSA) | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for SPARC, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-22-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | * the CPU state struct so it won't get zeroed on reset. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
20 | + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ | ||
21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | ||
22 | /* For inf * 0 + NaN, return the input NaN */ | ||
23 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
24 | |||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | } else { | ||
31 | rule = float_3nan_prop_s_cab; | ||
32 | } | ||
33 | -#elif defined(TARGET_SPARC) | ||
34 | - rule = float_3nan_prop_s_cba; | ||
35 | #elif defined(TARGET_XTENSA) | ||
36 | if (status->use_first_nan) { | ||
37 | rule = float_3nan_prop_abc; | ||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for Arm, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-23-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/mips/fpu_helper.h | 4 ++++ | ||
9 | target/mips/msa.c | 3 +++ | ||
10 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
11 | 3 files changed, 8 insertions(+), 7 deletions(-) | ||
12 | |||
13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/mips/fpu_helper.h | ||
16 | +++ b/target/mips/fpu_helper.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
18 | { | ||
19 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); | ||
20 | FloatInfZeroNaNRule izn_rule; | ||
21 | + Float3NaNPropRule nan3_rule; | ||
22 | |||
23 | /* | ||
24 | * With nan2008, SNaNs are silenced in the usual way. | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
26 | */ | ||
27 | izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | ||
28 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
29 | + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; | ||
30 | + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); | ||
31 | + | ||
32 | } | ||
33 | |||
34 | static inline void restore_fp_status(CPUMIPSState *env) | ||
35 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/mips/msa.c | ||
38 | +++ b/target/mips/msa.c | ||
39 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
40 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, | ||
41 | &env->active_tc.msa_fp_status); | ||
42 | |||
43 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, | ||
44 | + &env->active_tc.msa_fp_status); | ||
45 | + | ||
46 | /* clear float_status exception flags */ | ||
47 | set_float_exception_flags(0, &env->active_tc.msa_fp_status); | ||
48 | |||
49 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/fpu/softfloat-specialize.c.inc | ||
52 | +++ b/fpu/softfloat-specialize.c.inc | ||
53 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
54 | } | ||
55 | |||
56 | if (rule == float_3nan_prop_none) { | ||
57 | -#if defined(TARGET_MIPS) | ||
58 | - if (snan_bit_is_one(status)) { | ||
59 | - rule = float_3nan_prop_s_abc; | ||
60 | - } else { | ||
61 | - rule = float_3nan_prop_s_cab; | ||
62 | - } | ||
63 | -#elif defined(TARGET_XTENSA) | ||
64 | +#if defined(TARGET_XTENSA) | ||
65 | if (status->use_first_nan) { | ||
66 | rule = float_3nan_prop_abc; | ||
67 | } else { | ||
68 | -- | ||
69 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for xtensa, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-24-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/xtensa/fpu_helper.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 8 -------- | ||
10 | 2 files changed, 2 insertions(+), 8 deletions(-) | ||
11 | |||
12 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/xtensa/fpu_helper.c | ||
15 | +++ b/target/xtensa/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) | ||
17 | set_use_first_nan(use_first, &env->fp_status); | ||
18 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, | ||
19 | &env->fp_status); | ||
20 | + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, | ||
21 | + &env->fp_status); | ||
22 | } | ||
23 | |||
24 | void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | } | ||
31 | |||
32 | if (rule == float_3nan_prop_none) { | ||
33 | -#if defined(TARGET_XTENSA) | ||
34 | - if (status->use_first_nan) { | ||
35 | - rule = float_3nan_prop_abc; | ||
36 | - } else { | ||
37 | - rule = float_3nan_prop_cba; | ||
38 | - } | ||
39 | -#else | ||
40 | rule = float_3nan_prop_abc; | ||
41 | -#endif | ||
42 | } | ||
43 | |||
44 | assert(rule != float_3nan_prop_none); | ||
45 | -- | ||
46 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for i386. We had no | ||
2 | i386-specific behaviour in the old ifdef ladder, so we were using the | ||
3 | default "prefer a then b then c" fallback; this is actually the | ||
4 | correct per-the-spec handling for i386. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-25-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/i386/tcg/fpu_helper.c | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/i386/tcg/fpu_helper.c | ||
16 | +++ b/target/i386/tcg/fpu_helper.c | ||
17 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
18 | * there are multiple input NaNs they are selected in the order a, b, c. | ||
19 | */ | ||
20 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
21 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | ||
22 | } | ||
23 | |||
24 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for HPPA, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | HPPA is the only target that was using the default branch of the | ||
5 | ifdef ladder (other targets either do not use muladd or set | ||
6 | default_nan_mode), so we can remove the ifdef fallback entirely now | ||
7 | (allowing the "rule not set" case to fall into the default of the | ||
8 | switch statement and assert). | ||
9 | |||
10 | We add a TODO note that the HPPA rule is probably wrong; this is | ||
11 | not a behavioural change for this refactoring. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20241202131347.498124-26-peter.maydell@linaro.org | ||
16 | --- | ||
17 | target/hppa/fpu_helper.c | 8 ++++++++ | ||
18 | fpu/softfloat-specialize.c.inc | 4 ---- | ||
19 | 2 files changed, 8 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/hppa/fpu_helper.c | ||
24 | +++ b/target/hppa/fpu_helper.c | ||
25 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
26 | * HPPA does note implement a CPU reset method at all... | ||
27 | */ | ||
28 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
29 | + /* | ||
30 | + * TODO: The HPPA architecture reference only documents its NaN | ||
31 | + * propagation rule for 2-operand operations. Testing on real hardware | ||
32 | + * might be necessary to confirm whether this order for muladd is correct. | ||
33 | + * Not preferring the SNaN is almost certainly incorrect as it diverges | ||
34 | + * from the documented rules for 2-operand operations. | ||
35 | + */ | ||
36 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
37 | /* For inf * 0 + NaN, return the input NaN */ | ||
38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
39 | } | ||
40 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/fpu/softfloat-specialize.c.inc | ||
43 | +++ b/fpu/softfloat-specialize.c.inc | ||
44 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
45 | } | ||
46 | } | ||
47 | |||
48 | - if (rule == float_3nan_prop_none) { | ||
49 | - rule = float_3nan_prop_abc; | ||
50 | - } | ||
51 | - | ||
52 | assert(rule != float_3nan_prop_none); | ||
53 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
54 | /* We have at least one SNaN input and should prefer it */ | ||
55 | -- | ||
56 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The use_first_nan field in float_status was an xtensa-specific way to | ||
2 | select at runtime from two different NaN propagation rules. Now that | ||
3 | xtensa is using the target-agnostic NaN propagation rule selection | ||
4 | that we've just added, we can remove use_first_nan, because there is | ||
5 | no longer any code that reads it. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20241202131347.498124-27-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/fpu/softfloat-helpers.h | 5 ----- | ||
12 | include/fpu/softfloat-types.h | 1 - | ||
13 | target/xtensa/fpu_helper.c | 1 - | ||
14 | 3 files changed, 7 deletions(-) | ||
15 | |||
16 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/fpu/softfloat-helpers.h | ||
19 | +++ b/include/fpu/softfloat-helpers.h | ||
20 | @@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status) | ||
21 | status->snan_bit_is_one = val; | ||
22 | } | ||
23 | |||
24 | -static inline void set_use_first_nan(bool val, float_status *status) | ||
25 | -{ | ||
26 | - status->use_first_nan = val; | ||
27 | -} | ||
28 | - | ||
29 | static inline void set_no_signaling_nans(bool val, float_status *status) | ||
30 | { | ||
31 | status->no_signaling_nans = val; | ||
32 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/include/fpu/softfloat-types.h | ||
35 | +++ b/include/fpu/softfloat-types.h | ||
36 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
37 | * softfloat-specialize.inc.c) | ||
38 | */ | ||
39 | bool snan_bit_is_one; | ||
40 | - bool use_first_nan; | ||
41 | bool no_signaling_nans; | ||
42 | /* should overflowed results subtract re_bias to its exponent? */ | ||
43 | bool rebias_overflow; | ||
44 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/xtensa/fpu_helper.c | ||
47 | +++ b/target/xtensa/fpu_helper.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static const struct { | ||
49 | |||
50 | void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) | ||
51 | { | ||
52 | - set_use_first_nan(use_first, &env->fp_status); | ||
53 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, | ||
54 | &env->fp_status); | ||
55 | set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, | ||
56 | -- | ||
57 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) | ||
2 | to get the NaN bit pattern to reset the FPU registers. This | ||
3 | works because it happens that our implementation of | ||
4 | floatx80_default_nan() doesn't actually look at the float_status | ||
5 | pointer except for TARGET_MIPS. However, this isn't guaranteed, | ||
6 | and to be able to remove the ifdef in floatx80_default_nan() | ||
7 | we're going to need a real float_status here. | ||
1 | 8 | ||
9 | Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status | ||
10 | earlier, and thus can pass it to floatx80_default_nan(). | ||
11 | |||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20241202131347.498124-28-peter.maydell@linaro.org | ||
15 | --- | ||
16 | target/m68k/cpu.c | 12 +++++++----- | ||
17 | 1 file changed, 7 insertions(+), 5 deletions(-) | ||
18 | |||
19 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/m68k/cpu.c | ||
22 | +++ b/target/m68k/cpu.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
24 | CPUState *cs = CPU(obj); | ||
25 | M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); | ||
26 | CPUM68KState *env = cpu_env(cs); | ||
27 | - floatx80 nan = floatx80_default_nan(NULL); | ||
28 | + floatx80 nan; | ||
29 | int i; | ||
30 | |||
31 | if (mcc->parent_phases.hold) { | ||
32 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
33 | #else | ||
34 | cpu_m68k_set_sr(env, SR_S | SR_I); | ||
35 | #endif | ||
36 | - for (i = 0; i < 8; i++) { | ||
37 | - env->fregs[i].d = nan; | ||
38 | - } | ||
39 | - cpu_m68k_set_fpcr(env, 0); | ||
40 | /* | ||
41 | * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL | ||
42 | * 3.4 FLOATING-POINT INSTRUCTION DETAILS | ||
43 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
44 | * preceding paragraph for nonsignaling NaNs. | ||
45 | */ | ||
46 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
47 | + | ||
48 | + nan = floatx80_default_nan(&env->fp_status); | ||
49 | + for (i = 0; i < 8; i++) { | ||
50 | + env->fregs[i].d = nan; | ||
51 | + } | ||
52 | + cpu_m68k_set_fpcr(env, 0); | ||
53 | env->fpsr = 0; | ||
54 | |||
55 | /* TODO: We should set PC from the interrupt vector. */ | ||
56 | -- | ||
57 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | We create our 128-bit default NaN by calling parts64_default_nan() | ||
2 | and then adjusting the result. We can do the same trick for creating | ||
3 | the floatx80 default NaN, which lets us drop a target ifdef. | ||
1 | 4 | ||
5 | floatx80 is used only by: | ||
6 | i386 | ||
7 | m68k | ||
8 | arm nwfpe old floating-point emulation emulation support | ||
9 | (which is essentially dead, especially the parts involving floatx80) | ||
10 | PPC (only in the xsrqpxp instruction, which just rounds an input | ||
11 | value by converting to floatx80 and back, so will never generate | ||
12 | the default NaN) | ||
13 | |||
14 | The floatx80 default NaN as currently implemented is: | ||
15 | m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 | ||
16 | i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 | ||
17 | |||
18 | These are the same as the parts64_default_nan for these architectures. | ||
19 | |||
20 | This is technically a possible behaviour change for arm linux-user | ||
21 | nwfpe emulation emulation, because the default NaN will now have the | ||
22 | sign bit clear. But we were already generating a different floatx80 | ||
23 | default NaN from the real kernel emulation we are supposedly | ||
24 | following, which appears to use an all-bits-1 value: | ||
25 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 | ||
26 | |||
27 | This won't affect the only "real" use of the nwfpe emulation, which | ||
28 | is ancient binaries that used it as part of the old floating point | ||
29 | calling convention; that only uses loads and stores of 32 and 64 bit | ||
30 | floats, not any of the floatx80 behaviour the original hardware had. | ||
31 | We also get the nwfpe float64 default NaN value wrong: | ||
32 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 | ||
33 | so if we ever cared about this obscure corner the right fix would be | ||
34 | to correct that so nwfpe used its own default-NaN setting rather | ||
35 | than the Arm VFP one. | ||
36 | |||
37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
38 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
39 | Message-id: 20241202131347.498124-29-peter.maydell@linaro.org | ||
40 | --- | ||
41 | fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- | ||
42 | 1 file changed, 10 insertions(+), 10 deletions(-) | ||
43 | |||
44 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/fpu/softfloat-specialize.c.inc | ||
47 | +++ b/fpu/softfloat-specialize.c.inc | ||
48 | @@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) | ||
49 | floatx80 floatx80_default_nan(float_status *status) | ||
50 | { | ||
51 | floatx80 r; | ||
52 | + /* | ||
53 | + * Extrapolate from the choices made by parts64_default_nan to fill | ||
54 | + * in the floatx80 format. We assume that floatx80's explicit | ||
55 | + * integer bit is always set (this is true for i386 and m68k, | ||
56 | + * which are the only real users of this format). | ||
57 | + */ | ||
58 | + FloatParts64 p64; | ||
59 | + parts64_default_nan(&p64, status); | ||
60 | |||
61 | - /* None of the targets that have snan_bit_is_one use floatx80. */ | ||
62 | - assert(!snan_bit_is_one(status)); | ||
63 | -#if defined(TARGET_M68K) | ||
64 | - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); | ||
65 | - r.high = 0x7FFF; | ||
66 | -#else | ||
67 | - /* X86 */ | ||
68 | - r.low = UINT64_C(0xC000000000000000); | ||
69 | - r.high = 0xFFFF; | ||
70 | -#endif | ||
71 | + r.high = 0x7FFF | (p64.sign << 15); | ||
72 | + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; | ||
73 | return r; | ||
74 | } | ||
75 | |||
76 | -- | ||
77 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass | ||
2 | a zero-initialized float_status struct to float32_is_quiet_nan() and | ||
3 | float64_is_quiet_nan(), with the cryptic comment "for | ||
4 | snan_bit_is_one". | ||
1 | 5 | ||
6 | This pattern appears to have been copied from target/riscv, where it | ||
7 | is used because the functions there do not have ready access to the | ||
8 | CPU state struct. The comment presumably refers to the fact that the | ||
9 | main reason the is_quiet_nan() functions want the float_state is | ||
10 | because they want to know about the snan_bit_is_one config. | ||
11 | |||
12 | In the loongarch helpers, though, we have the CPU state struct | ||
13 | to hand. Use the usual env->fp_status here. This avoids our needing | ||
14 | to track that we need to update the initializer of the local | ||
15 | float_status structs when the core softfloat code adds new | ||
16 | options for targets to configure their behaviour. | ||
17 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20241202131347.498124-30-peter.maydell@linaro.org | ||
21 | --- | ||
22 | target/loongarch/tcg/fpu_helper.c | 6 ++---- | ||
23 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
24 | |||
25 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/loongarch/tcg/fpu_helper.c | ||
28 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
29 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) | ||
30 | } else if (float32_is_zero_or_denormal(f)) { | ||
31 | return sign ? 1 << 4 : 1 << 8; | ||
32 | } else if (float32_is_any_nan(f)) { | ||
33 | - float_status s = { }; /* for snan_bit_is_one */ | ||
34 | - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
35 | + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
36 | } else { | ||
37 | return sign ? 1 << 3 : 1 << 7; | ||
38 | } | ||
39 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) | ||
40 | } else if (float64_is_zero_or_denormal(f)) { | ||
41 | return sign ? 1 << 4 : 1 << 8; | ||
42 | } else if (float64_is_any_nan(f)) { | ||
43 | - float_status s = { }; /* for snan_bit_is_one */ | ||
44 | - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
45 | + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
46 | } else { | ||
47 | return sign ? 1 << 3 : 1 << 7; | ||
48 | } | ||
49 | -- | ||
50 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the frem helper, we have a local float_status because we want to | ||
2 | execute the floatx80_div() with a custom rounding mode. Instead of | ||
3 | zero-initializing the local float_status and then having to set it up | ||
4 | with the m68k standard behaviour (including the NaN propagation rule | ||
5 | and copying the rounding precision from env->fp_status), initialize | ||
6 | it as a complete copy of env->fp_status. This will avoid our having | ||
7 | to add new code in this function for every new config knob we add | ||
8 | to fp_status. | ||
1 | 9 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-31-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/m68k/fpu_helper.c | 6 ++---- | ||
15 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
16 | |||
17 | diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/m68k/fpu_helper.c | ||
20 | +++ b/target/m68k/fpu_helper.c | ||
21 | @@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) | ||
22 | |||
23 | fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); | ||
24 | if (!floatx80_is_any_nan(fp_rem)) { | ||
25 | - float_status fp_status = { }; | ||
26 | + /* Use local temporary fp_status to set different rounding mode */ | ||
27 | + float_status fp_status = env->fp_status; | ||
28 | uint32_t quotient; | ||
29 | int sign; | ||
30 | |||
31 | /* Calculate quotient directly using round to nearest mode */ | ||
32 | - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); | ||
33 | set_float_rounding_mode(float_round_nearest_even, &fp_status); | ||
34 | - set_floatx80_rounding_precision( | ||
35 | - get_floatx80_rounding_precision(&env->fp_status), &fp_status); | ||
36 | fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); | ||
37 | |||
38 | sign = extractFloatx80Sign(fp_quot.d); | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion | ||
2 | from float64 to floatx80 using a scratch float_status, because we | ||
3 | don't want the conversion to affect the CPU's floating point exception | ||
4 | status. Currently we use a zero-initialized float_status. This will | ||
5 | get steadily more awkward as we add config knobs to float_status | ||
6 | that the target must initialize. Avoid having to add any of that | ||
7 | configuration here by instead initializing our local float_status | ||
8 | from the env->fp_status. | ||
1 | 9 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-32-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/m68k/helper.c | 6 ++++-- | ||
15 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
16 | |||
17 | diff --git a/target/m68k/helper.c b/target/m68k/helper.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/m68k/helper.c | ||
20 | +++ b/target/m68k/helper.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) | ||
22 | CPUM68KState *env = &cpu->env; | ||
23 | |||
24 | if (n < 8) { | ||
25 | - float_status s = {}; | ||
26 | + /* Use scratch float_status so any exceptions don't change CPU state */ | ||
27 | + float_status s = env->fp_status; | ||
28 | return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); | ||
29 | } | ||
30 | switch (n) { | ||
31 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) | ||
32 | CPUM68KState *env = &cpu->env; | ||
33 | |||
34 | if (n < 8) { | ||
35 | - float_status s = {}; | ||
36 | + /* Use scratch float_status so any exceptions don't change CPU state */ | ||
37 | + float_status s = env->fp_status; | ||
38 | env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); | ||
39 | return 8; | ||
40 | } | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In the helper functions flcmps and flcmpd we use a scratch float_status |
---|---|---|---|
2 | so that we don't change the CPU state if the comparison raises any | ||
3 | floating point exception flags. Instead of zero-initializing this | ||
4 | scratch float_status, initialize it as a copy of env->fp_status. This | ||
5 | avoids the need to explicitly initialize settings like the NaN | ||
6 | propagation rule or others we might add to softfloat in future. | ||
2 | 7 | ||
3 | Previously we were defining some of these in user-only mode, | 8 | To do this we need to pass the CPU env pointer in to the helper. |
4 | but none of them are accessible from user-only, therefore | ||
5 | define them only in system mode. | ||
6 | 9 | ||
7 | This will shortly be used from cpu_tcg.c also. | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-33-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/sparc/helper.h | 4 ++-- | ||
15 | target/sparc/fop_helper.c | 8 ++++---- | ||
16 | target/sparc/translate.c | 4 ++-- | ||
17 | 3 files changed, 8 insertions(+), 8 deletions(-) | ||
8 | 18 | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | diff --git a/target/sparc/helper.h b/target/sparc/helper.h |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220506180242.216785-6-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/internals.h | 6 ++++ | ||
15 | target/arm/cpu64.c | 64 +++--------------------------------------- | ||
16 | target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ | ||
17 | 3 files changed, 69 insertions(+), 60 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/internals.h | 21 | --- a/target/sparc/helper.h |
22 | +++ b/target/arm/internals.h | 22 | +++ b/target/sparc/helper.h |
23 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); | 23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) |
24 | int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); | 24 | DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) |
25 | #endif | 25 | DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) |
26 | 26 | DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) | |
27 | +#ifdef CONFIG_USER_ONLY | 27 | -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) |
28 | +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | 28 | -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) |
29 | +#else | 29 | +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) |
30 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | 30 | +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) |
31 | +#endif | 31 | DEF_HELPER_2(raise_exception, noreturn, env, int) |
32 | + | 32 | |
33 | #endif | 33 | DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) |
34 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 34 | diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c |
35 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/target/arm/cpu64.c | 36 | --- a/target/sparc/fop_helper.c |
37 | +++ b/target/arm/cpu64.c | 37 | +++ b/target/sparc/fop_helper.c |
38 | @@ -XXX,XX +XXX,XX @@ | 38 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) |
39 | #include "hvf_arm.h" | 39 | return finish_fcmp(env, r, GETPC()); |
40 | #include "qapi/visitor.h" | 40 | } |
41 | #include "hw/qdev-properties.h" | 41 | |
42 | -#include "cpregs.h" | 42 | -uint32_t helper_flcmps(float32 src1, float32 src2) |
43 | +#include "internals.h" | 43 | +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) |
44 | |||
45 | |||
46 | -#ifndef CONFIG_USER_ONLY | ||
47 | -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
48 | -{ | ||
49 | - ARMCPU *cpu = env_archcpu(env); | ||
50 | - | ||
51 | - /* Number of cores is in [25:24]; otherwise we RAZ */ | ||
52 | - return (cpu->core_count - 1) << 24; | ||
53 | -} | ||
54 | -#endif | ||
55 | - | ||
56 | -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
57 | -#ifndef CONFIG_USER_ONLY | ||
58 | - { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
59 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | ||
60 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | ||
61 | - .writefn = arm_cp_write_ignore }, | ||
62 | - { .name = "L2CTLR", | ||
63 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | ||
64 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | ||
65 | - .writefn = arm_cp_write_ignore }, | ||
66 | -#endif | ||
67 | - { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
68 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | ||
69 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
70 | - { .name = "L2ECTLR", | ||
71 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | ||
72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
73 | - { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | ||
74 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | ||
75 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
76 | - { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
77 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | ||
78 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | - { .name = "CPUACTLR", | ||
80 | - .cp = 15, .opc1 = 0, .crm = 15, | ||
81 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
82 | - { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
83 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | ||
84 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
85 | - { .name = "CPUECTLR", | ||
86 | - .cp = 15, .opc1 = 1, .crm = 15, | ||
87 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
88 | - { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
89 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | ||
90 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
91 | - { .name = "CPUMERRSR", | ||
92 | - .cp = 15, .opc1 = 2, .crm = 15, | ||
93 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
94 | - { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
95 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | ||
96 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
97 | - { .name = "L2MERRSR", | ||
98 | - .cp = 15, .opc1 = 3, .crm = 15, | ||
99 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
100 | -}; | ||
101 | - | ||
102 | static void aarch64_a57_initfn(Object *obj) | ||
103 | { | 44 | { |
104 | ARMCPU *cpu = ARM_CPU(obj); | 45 | /* |
105 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | 46 | * FLCMP never raises an exception nor modifies any FSR fields. |
106 | cpu->gic_num_lrs = 4; | 47 | * Perform the comparison with a dummy fp environment. |
107 | cpu->gic_vpribits = 5; | 48 | */ |
108 | cpu->gic_vprebits = 5; | 49 | - float_status discard = { }; |
109 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 50 | + float_status discard = env->fp_status; |
110 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | 51 | FloatRelation r; |
52 | |||
53 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); | ||
54 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2) | ||
55 | g_assert_not_reached(); | ||
111 | } | 56 | } |
112 | 57 | ||
113 | static void aarch64_a53_initfn(Object *obj) | 58 | -uint32_t helper_flcmpd(float64 src1, float64 src2) |
114 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | 59 | +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) |
115 | cpu->gic_num_lrs = 4; | 60 | { |
116 | cpu->gic_vpribits = 5; | 61 | - float_status discard = { }; |
117 | cpu->gic_vprebits = 5; | 62 | + float_status discard = env->fp_status; |
118 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 63 | FloatRelation r; |
119 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | 64 | |
65 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); | ||
66 | diff --git a/target/sparc/translate.c b/target/sparc/translate.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/sparc/translate.c | ||
69 | +++ b/target/sparc/translate.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) | ||
71 | |||
72 | src1 = gen_load_fpr_F(dc, a->rs1); | ||
73 | src2 = gen_load_fpr_F(dc, a->rs2); | ||
74 | - gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); | ||
75 | + gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2); | ||
76 | return advance_pc(dc); | ||
120 | } | 77 | } |
121 | 78 | ||
122 | static void aarch64_a72_initfn(Object *obj) | 79 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) |
123 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | 80 | |
124 | cpu->gic_num_lrs = 4; | 81 | src1 = gen_load_fpr_D(dc, a->rs1); |
125 | cpu->gic_vpribits = 5; | 82 | src2 = gen_load_fpr_D(dc, a->rs2); |
126 | cpu->gic_vprebits = 5; | 83 | - gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); |
127 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 84 | + gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); |
128 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | 85 | return advance_pc(dc); |
129 | } | 86 | } |
130 | 87 | ||
131 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | ||
132 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
133 | index XXXXXXX..XXXXXXX 100644 | ||
134 | --- a/target/arm/cpu_tcg.c | ||
135 | +++ b/target/arm/cpu_tcg.c | ||
136 | @@ -XXX,XX +XXX,XX @@ | ||
137 | #endif | ||
138 | #include "cpregs.h" | ||
139 | |||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
142 | +{ | ||
143 | + ARMCPU *cpu = env_archcpu(env); | ||
144 | + | ||
145 | + /* Number of cores is in [25:24]; otherwise we RAZ */ | ||
146 | + return (cpu->core_count - 1) << 24; | ||
147 | +} | ||
148 | + | ||
149 | +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
150 | + { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
151 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | ||
152 | + .access = PL1_RW, .readfn = l2ctlr_read, | ||
153 | + .writefn = arm_cp_write_ignore }, | ||
154 | + { .name = "L2CTLR", | ||
155 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | ||
156 | + .access = PL1_RW, .readfn = l2ctlr_read, | ||
157 | + .writefn = arm_cp_write_ignore }, | ||
158 | + { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
159 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | ||
160 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
161 | + { .name = "L2ECTLR", | ||
162 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | ||
163 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
164 | + { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | ||
165 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | ||
166 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
167 | + { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
168 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | ||
169 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
170 | + { .name = "CPUACTLR", | ||
171 | + .cp = 15, .opc1 = 0, .crm = 15, | ||
172 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
173 | + { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
174 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | ||
175 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
176 | + { .name = "CPUECTLR", | ||
177 | + .cp = 15, .opc1 = 1, .crm = 15, | ||
178 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
179 | + { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
180 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | ||
181 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
182 | + { .name = "CPUMERRSR", | ||
183 | + .cp = 15, .opc1 = 2, .crm = 15, | ||
184 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
185 | + { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
186 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | ||
187 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
188 | + { .name = "L2MERRSR", | ||
189 | + .cp = 15, .opc1 = 3, .crm = 15, | ||
190 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
191 | +}; | ||
192 | + | ||
193 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) | ||
194 | +{ | ||
195 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
196 | +} | ||
197 | +#endif /* !CONFIG_USER_ONLY */ | ||
198 | + | ||
199 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | ||
200 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | ||
201 | |||
202 | -- | 88 | -- |
203 | 2.25.1 | 89 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the helper_compute_fprf functions, we pass a dummy float_status | ||
2 | in to the is_signaling_nan() function. This is unnecessary, because | ||
3 | we have convenient access to the CPU env pointer here and that | ||
4 | is already set up with the correct values for the snan_bit_is_one | ||
5 | and no_signaling_nans config settings. is_signaling_nan() doesn't | ||
6 | ever update the fp_status with any exception flags, so there is | ||
7 | no reason not to use env->fp_status here. | ||
1 | 8 | ||
9 | Use env->fp_status instead of the dummy fp_status. | ||
10 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20241202131347.498124-34-peter.maydell@linaro.org | ||
14 | --- | ||
15 | target/ppc/fpu_helper.c | 3 +-- | ||
16 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
17 | |||
18 | diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/ppc/fpu_helper.c | ||
21 | +++ b/target/ppc/fpu_helper.c | ||
22 | @@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ | ||
23 | } else if (tp##_is_infinity(arg)) { \ | ||
24 | fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ | ||
25 | } else { \ | ||
26 | - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ | ||
27 | - if (tp##_is_signaling_nan(arg, &dummy)) { \ | ||
28 | + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ | ||
29 | fprf = 0x00 << FPSCR_FPRF; \ | ||
30 | } else { \ | ||
31 | fprf = 0x11 << FPSCR_FPRF; \ | ||
32 | -- | ||
33 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns cache speculation, which TCG does | 3 | Now that float_status has a bunch of fp parameters, |
4 | not implement. Thus we can trivially enable this feature. | 4 | it is easier to copy an existing structure than create |
5 | one from scratch. Begin by copying the structure that | ||
6 | corresponds to the FPSR and make only the adjustments | ||
7 | required for BFloat16 semantics. | ||
5 | 8 | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Message-id: 20241203203949.483774-2-richard.henderson@linaro.org |
8 | Message-id: 20220506180242.216785-22-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 15 | target/arm/tcg/vec_helper.c | 20 +++++++------------- |
12 | target/arm/cpu64.c | 1 + | 16 | 1 file changed, 7 insertions(+), 13 deletions(-) |
13 | target/arm/cpu_tcg.c | 1 + | ||
14 | 3 files changed, 3 insertions(+) | ||
15 | 17 | ||
16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 18 | diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/emulation.rst | 20 | --- a/target/arm/tcg/vec_helper.c |
19 | +++ b/docs/system/arm/emulation.rst | 21 | +++ b/target/arm/tcg/vec_helper.c |
20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 22 | @@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) |
21 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | 23 | * no effect on AArch32 instructions. |
22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | 24 | */ |
23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | 25 | bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; |
24 | +- FEAT_CSV3 (Cache speculation variant 3) | 26 | - *statusp = (float_status){ |
25 | - FEAT_DIT (Data Independent Timing instructions) | 27 | - .tininess_before_rounding = float_tininess_before_rounding, |
26 | - FEAT_DPB (DC CVAP instruction) | 28 | - .float_rounding_mode = float_round_to_odd_inf, |
27 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 29 | - .flush_to_zero = true, |
28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 30 | - .flush_inputs_to_zero = true, |
29 | index XXXXXXX..XXXXXXX 100644 | 31 | - .default_nan_mode = true, |
30 | --- a/target/arm/cpu64.c | 32 | - }; |
31 | +++ b/target/arm/cpu64.c | 33 | + |
32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 34 | + *statusp = env->vfp.fp_status; |
33 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | 35 | + set_default_nan_mode(true, statusp); |
34 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | 36 | |
35 | t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | 37 | if (ebf) { |
36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ | 38 | - float_status *fpst = &env->vfp.fp_status; |
37 | cpu->isar.id_aa64pfr0 = t; | 39 | - set_flush_to_zero(get_flush_to_zero(fpst), statusp); |
38 | 40 | - set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); | |
39 | t = cpu->isar.id_aa64pfr1; | 41 | - set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); |
40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 42 | - |
41 | index XXXXXXX..XXXXXXX 100644 | 43 | /* EBF=1 needs to do a step with round-to-odd semantics */ |
42 | --- a/target/arm/cpu_tcg.c | 44 | *oddstatusp = *statusp; |
43 | +++ b/target/arm/cpu_tcg.c | 45 | set_float_rounding_mode(float_round_to_odd, oddstatusp); |
44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 46 | + } else { |
45 | cpu->isar.id_pfr0 = t; | 47 | + set_flush_to_zero(true, statusp); |
46 | 48 | + set_flush_inputs_to_zero(true, statusp); | |
47 | t = cpu->isar.id_pfr2; | 49 | + set_float_rounding_mode(float_round_to_odd_inf, statusp); |
48 | + t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ | 50 | } |
49 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | 51 | - |
50 | cpu->isar.id_pfr2 = t; | 52 | return ebf; |
53 | } | ||
51 | 54 | ||
52 | -- | 55 | -- |
53 | 2.25.1 | 56 | 2.34.1 |
57 | |||
58 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Currently we hardcode the default NaN value in parts64_default_nan() |
---|---|---|---|
2 | using a compile-time ifdef ladder. This is awkward for two cases: | ||
3 | * for single-QEMU-binary we can't hard-code target-specifics like this | ||
4 | * for Arm FEAT_AFP the default NaN value depends on FPCR.AH | ||
5 | (specifically the sign bit is different) | ||
2 | 6 | ||
3 | Add only the system registers required to implement zero error | 7 | Add a field to float_status to specify the default NaN value; fall |
4 | records. This means that all values for ERRSELR are out of range, | 8 | back to the old ifdef behaviour if these are not set. |
5 | which means that it and all of the indexed error record registers | ||
6 | need not be implemented. | ||
7 | 9 | ||
8 | Add the EL2 registers required for injecting virtual SError. | 10 | The default NaN value is specified by setting a uint8_t to a |
11 | pattern corresponding to the sign and upper fraction parts of | ||
12 | the NaN; the lower bits of the fraction are set from bit 0 of | ||
13 | the pattern. | ||
9 | 14 | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20220506180242.216785-14-richard.henderson@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20241202131347.498124-35-peter.maydell@linaro.org | ||
14 | --- | 18 | --- |
15 | target/arm/cpu.h | 5 +++ | 19 | include/fpu/softfloat-helpers.h | 11 +++++++ |
16 | target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ | 20 | include/fpu/softfloat-types.h | 10 ++++++ |
17 | 2 files changed, 89 insertions(+) | 21 | fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- |
22 | 3 files changed, 54 insertions(+), 22 deletions(-) | ||
18 | 23 | ||
19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 24 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h |
20 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/cpu.h | 26 | --- a/include/fpu/softfloat-helpers.h |
22 | +++ b/target/arm/cpu.h | 27 | +++ b/include/fpu/softfloat-helpers.h |
23 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 28 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, |
24 | uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ | 29 | status->float_infzeronan_rule = rule; |
25 | uint64_t gcr_el1; | 30 | } |
26 | uint64_t rgsr_el1; | 31 | |
27 | + | 32 | +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, |
28 | + /* Minimal RAS registers */ | 33 | + float_status *status) |
29 | + uint64_t disr_el1; | ||
30 | + uint64_t vdisr_el2; | ||
31 | + uint64_t vsesr_el2; | ||
32 | } cp15; | ||
33 | |||
34 | struct { | ||
35 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/helper.c | ||
38 | +++ b/target/arm/helper.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
40 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | ||
41 | }; | ||
42 | |||
43 | +/* | ||
44 | + * Check for traps to RAS registers, which are controlled | ||
45 | + * by HCR_EL2.TERR and SCR_EL3.TERR. | ||
46 | + */ | ||
47 | +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, | ||
48 | + bool isread) | ||
49 | +{ | 34 | +{ |
50 | + int el = arm_current_el(env); | 35 | + status->default_nan_pattern = dnan_pattern; |
51 | + | ||
52 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { | ||
53 | + return CP_ACCESS_TRAP_EL2; | ||
54 | + } | ||
55 | + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { | ||
56 | + return CP_ACCESS_TRAP_EL3; | ||
57 | + } | ||
58 | + return CP_ACCESS_OK; | ||
59 | +} | 36 | +} |
60 | + | 37 | + |
61 | +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 38 | static inline void set_flush_to_zero(bool val, float_status *status) |
39 | { | ||
40 | status->flush_to_zero = val; | ||
41 | @@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status | ||
42 | return status->float_infzeronan_rule; | ||
43 | } | ||
44 | |||
45 | +static inline uint8_t get_float_default_nan_pattern(float_status *status) | ||
62 | +{ | 46 | +{ |
63 | + int el = arm_current_el(env); | 47 | + return status->default_nan_pattern; |
64 | + | ||
65 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | ||
66 | + return env->cp15.vdisr_el2; | ||
67 | + } | ||
68 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | ||
69 | + return 0; /* RAZ/WI */ | ||
70 | + } | ||
71 | + return env->cp15.disr_el1; | ||
72 | +} | 48 | +} |
73 | + | 49 | + |
74 | +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | 50 | static inline bool get_flush_to_zero(float_status *status) |
75 | +{ | 51 | { |
76 | + int el = arm_current_el(env); | 52 | return status->flush_to_zero; |
53 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/include/fpu/softfloat-types.h | ||
56 | +++ b/include/fpu/softfloat-types.h | ||
57 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
58 | /* should denormalised inputs go to zero and set the input_denormal flag? */ | ||
59 | bool flush_inputs_to_zero; | ||
60 | bool default_nan_mode; | ||
61 | + /* | ||
62 | + * The pattern to use for the default NaN. Here the high bit specifies | ||
63 | + * the default NaN's sign bit, and bits 6..0 specify the high bits of the | ||
64 | + * fractional part. The low bits of the fractional part are copies of bit 0. | ||
65 | + * The exponent of the default NaN is (as for any NaN) always all 1s. | ||
66 | + * Note that a value of 0 here is not a valid NaN. The target must set | ||
67 | + * this to the correct non-zero value, or we will assert when trying to | ||
68 | + * create a default NaN. | ||
69 | + */ | ||
70 | + uint8_t default_nan_pattern; | ||
71 | /* | ||
72 | * The flags below are not used on all specializations and may | ||
73 | * constant fold away (see snan_bit_is_one()/no_signalling_nans() in | ||
74 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/fpu/softfloat-specialize.c.inc | ||
77 | +++ b/fpu/softfloat-specialize.c.inc | ||
78 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
79 | { | ||
80 | bool sign = 0; | ||
81 | uint64_t frac; | ||
82 | + uint8_t dnan_pattern = status->default_nan_pattern; | ||
83 | |||
84 | + if (dnan_pattern == 0) { | ||
85 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
86 | - /* !snan_bit_is_one, set all bits */ | ||
87 | - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; | ||
88 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
89 | + /* Sign bit clear, all frac bits set */ | ||
90 | + dnan_pattern = 0b01111111; | ||
91 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
92 | || defined(TARGET_MICROBLAZE) | ||
93 | - /* !snan_bit_is_one, set sign and msb */ | ||
94 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
95 | - sign = 1; | ||
96 | + /* Sign bit set, most significant frac bit set */ | ||
97 | + dnan_pattern = 0b11000000; | ||
98 | #elif defined(TARGET_HPPA) | ||
99 | - /* snan_bit_is_one, set msb-1. */ | ||
100 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); | ||
101 | + /* Sign bit clear, msb-1 frac bit set */ | ||
102 | + dnan_pattern = 0b00100000; | ||
103 | #elif defined(TARGET_HEXAGON) | ||
104 | - sign = 1; | ||
105 | - frac = ~0ULL; | ||
106 | + /* Sign bit set, all frac bits set. */ | ||
107 | + dnan_pattern = 0b11111111; | ||
108 | #else | ||
109 | - /* | ||
110 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
111 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
112 | - * do not have floating-point. | ||
113 | - */ | ||
114 | - if (snan_bit_is_one(status)) { | ||
115 | - /* set all bits other than msb */ | ||
116 | - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; | ||
117 | - } else { | ||
118 | - /* set msb */ | ||
119 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
120 | - } | ||
121 | + /* | ||
122 | + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
123 | + * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
124 | + * do not have floating-point. | ||
125 | + */ | ||
126 | + if (snan_bit_is_one(status)) { | ||
127 | + /* sign bit clear, set all frac bits other than msb */ | ||
128 | + dnan_pattern = 0b00111111; | ||
129 | + } else { | ||
130 | + /* sign bit clear, set frac msb */ | ||
131 | + dnan_pattern = 0b01000000; | ||
132 | + } | ||
133 | #endif | ||
134 | + } | ||
135 | + assert(dnan_pattern != 0); | ||
77 | + | 136 | + |
78 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | 137 | + sign = dnan_pattern >> 7; |
79 | + env->cp15.vdisr_el2 = val; | 138 | + /* |
80 | + return; | 139 | + * Place default_nan_pattern [6:0] into bits [62:56], |
81 | + } | 140 | + * and replecate bit [0] down into [55:0] |
82 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | 141 | + */ |
83 | + return; /* RAZ/WI */ | 142 | + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); |
84 | + } | 143 | + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); |
85 | + env->cp15.disr_el1 = val; | 144 | |
86 | +} | 145 | *p = (FloatParts64) { |
87 | + | 146 | .cls = float_class_qnan, |
88 | +/* | ||
89 | + * Minimal RAS implementation with no Error Records. | ||
90 | + * Which means that all of the Error Record registers: | ||
91 | + * ERXADDR_EL1 | ||
92 | + * ERXCTLR_EL1 | ||
93 | + * ERXFR_EL1 | ||
94 | + * ERXMISC0_EL1 | ||
95 | + * ERXMISC1_EL1 | ||
96 | + * ERXMISC2_EL1 | ||
97 | + * ERXMISC3_EL1 | ||
98 | + * ERXPFGCDN_EL1 (RASv1p1) | ||
99 | + * ERXPFGCTL_EL1 (RASv1p1) | ||
100 | + * ERXPFGF_EL1 (RASv1p1) | ||
101 | + * ERXSTATUS_EL1 | ||
102 | + * and | ||
103 | + * ERRSELR_EL1 | ||
104 | + * may generate UNDEFINED, which is the effect we get by not | ||
105 | + * listing them at all. | ||
106 | + */ | ||
107 | +static const ARMCPRegInfo minimal_ras_reginfo[] = { | ||
108 | + { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | ||
109 | + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | ||
110 | + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | ||
111 | + .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | ||
112 | + { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
113 | + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | ||
114 | + .access = PL1_R, .accessfn = access_terr, | ||
115 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
116 | + { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | ||
117 | + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | ||
118 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | ||
119 | + { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | ||
120 | + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | ||
121 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | ||
122 | +}; | ||
123 | + | ||
124 | /* Return the exception level to which exceptions should be taken | ||
125 | * via SVEAccessTrap. If an exception should be routed through | ||
126 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | ||
127 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
128 | if (cpu_isar_feature(aa64_ssbs, cpu)) { | ||
129 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | ||
130 | } | ||
131 | + if (cpu_isar_feature(any_ras, cpu)) { | ||
132 | + define_arm_cp_regs(cpu, minimal_ras_reginfo); | ||
133 | + } | ||
134 | |||
135 | if (cpu_isar_feature(aa64_vh, cpu) || | ||
136 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | ||
137 | -- | 147 | -- |
138 | 2.25.1 | 148 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the default NaN pattern explicitly for the tests/fp code. |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns branch speculation, which TCG does | ||
4 | not implement. Thus we can trivially enable this feature. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-20-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-36-peter.maydell@linaro.org | ||
10 | --- | 6 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 7 | tests/fp/fp-bench.c | 1 + |
12 | target/arm/cpu64.c | 1 + | 8 | tests/fp/fp-test-log2.c | 1 + |
13 | target/arm/cpu_tcg.c | 1 + | 9 | tests/fp/fp-test.c | 1 + |
14 | 3 files changed, 3 insertions(+) | 10 | 3 files changed, 3 insertions(+) |
15 | 11 | ||
16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 12 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c |
17 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/emulation.rst | 14 | --- a/tests/fp/fp-bench.c |
19 | +++ b/docs/system/arm/emulation.rst | 15 | +++ b/tests/fp/fp-bench.c |
20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 16 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) |
21 | - FEAT_BBM at level 2 (Translation table break-before-make levels) | 17 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); |
22 | - FEAT_BF16 (AArch64 BFloat16 instructions) | 18 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); |
23 | - FEAT_BTI (Branch Target Identification) | 19 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); |
24 | +- FEAT_CSV2 (Cache speculation variant 2) | 20 | + set_float_default_nan_pattern(0b01000000, &soft_status); |
25 | - FEAT_DIT (Data Independent Timing instructions) | 21 | |
26 | - FEAT_DPB (DC CVAP instruction) | 22 | f = bench_funcs[operation][precision]; |
27 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 23 | g_assert(f); |
28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 24 | diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c |
29 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/cpu64.c | 26 | --- a/tests/fp/fp-test-log2.c |
31 | +++ b/target/arm/cpu64.c | 27 | +++ b/tests/fp/fp-test-log2.c |
32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 28 | @@ -XXX,XX +XXX,XX @@ int main(int ac, char **av) |
33 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | 29 | int i; |
34 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | 30 | |
35 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | 31 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); |
36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ | 32 | + set_float_default_nan_pattern(0b01000000, &qsf); |
37 | cpu->isar.id_aa64pfr0 = t; | 33 | set_float_rounding_mode(float_round_nearest_even, &qsf); |
38 | 34 | ||
39 | t = cpu->isar.id_aa64pfr1; | 35 | test.d = 0.0; |
40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 36 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c |
41 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
42 | --- a/target/arm/cpu_tcg.c | 38 | --- a/tests/fp/fp-test.c |
43 | +++ b/target/arm/cpu_tcg.c | 39 | +++ b/tests/fp/fp-test.c |
44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 40 | @@ -XXX,XX +XXX,XX @@ void run_test(void) |
45 | cpu->isar.id_mmfr4 = t; | 41 | */ |
46 | 42 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | |
47 | t = cpu->isar.id_pfr0; | 43 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); |
48 | + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ | 44 | + set_float_default_nan_pattern(0b01000000, &qsf); |
49 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | 45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); |
50 | t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ | 46 | |
51 | cpu->isar.id_pfr0 = t; | 47 | genCases_setLevel(test_level); |
52 | -- | 48 | -- |
53 | 2.25.1 | 49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-37-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/microblaze/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/microblaze/cpu.c | ||
15 | +++ b/target/microblaze/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | * this architecture. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
20 | + /* Default NaN: sign bit set, most significant frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | ||
22 | |||
23 | #if defined(CONFIG_USER_ONLY) | ||
24 | /* start in user mode with interrupts enabled. */ | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
31 | /* Sign bit clear, all frac bits set */ | ||
32 | dnan_pattern = 0b01111111; | ||
33 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
34 | - || defined(TARGET_MICROBLAZE) | ||
35 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) | ||
36 | /* Sign bit set, most significant frac bit set */ | ||
37 | dnan_pattern = 0b11000000; | ||
38 | #elif defined(TARGET_HPPA) | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-38-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/i386/tcg/fpu_helper.c | 4 ++++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 --- | ||
10 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/i386/tcg/fpu_helper.c | ||
15 | +++ b/target/i386/tcg/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
17 | */ | ||
18 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
19 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | ||
20 | + /* Default NaN: sign bit set, most significant frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | ||
22 | + set_float_default_nan_pattern(0b11000000, &env->mmx_status); | ||
23 | + set_float_default_nan_pattern(0b11000000, &env->sse_status); | ||
24 | } | ||
25 | |||
26 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/fpu/softfloat-specialize.c.inc | ||
30 | +++ b/fpu/softfloat-specialize.c.inc | ||
31 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
32 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
33 | /* Sign bit clear, all frac bits set */ | ||
34 | dnan_pattern = 0b01111111; | ||
35 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) | ||
36 | - /* Sign bit set, most significant frac bit set */ | ||
37 | - dnan_pattern = 0b11000000; | ||
38 | #elif defined(TARGET_HPPA) | ||
39 | /* Sign bit clear, msb-1 frac bit set */ | ||
40 | dnan_pattern = 0b00100000; | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-39-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/hppa/fpu_helper.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 --- | ||
10 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/hppa/fpu_helper.c | ||
15 | +++ b/target/hppa/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
18 | /* For inf * 0 + NaN, return the input NaN */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + /* Default NaN: sign bit clear, msb-1 frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b00100000, &env->fp_status); | ||
22 | } | ||
23 | |||
24 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
31 | /* Sign bit clear, all frac bits set */ | ||
32 | dnan_pattern = 0b01111111; | ||
33 | -#elif defined(TARGET_HPPA) | ||
34 | - /* Sign bit clear, msb-1 frac bit set */ | ||
35 | - dnan_pattern = 0b00100000; | ||
36 | #elif defined(TARGET_HEXAGON) | ||
37 | /* Sign bit set, all frac bits set. */ | ||
38 | dnan_pattern = 0b11111111; | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for the alpha target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-40-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/alpha/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/alpha/cpu.c | ||
13 | +++ b/target/alpha/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj) | ||
15 | * operand in Fa. That is float_2nan_prop_ba. | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
18 | + /* Default NaN: sign bit clear, msb frac bit set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | #if defined(CONFIG_USER_ONLY) | ||
21 | env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; | ||
22 | cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the default NaN pattern explicitly for the arm target. |
---|---|---|---|
2 | This includes setting it for the old linux-user nwfpe emulation. | ||
3 | For nwfpe, our default doesn't match the real kernel, but we | ||
4 | avoid making a behaviour change in this commit. | ||
2 | 5 | ||
3 | There is no branch prediction in TCG, therefore there is no | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | need to actually include the context number into the predictor. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Therefore all we need to do is add the state for SCXTNUM_ELx. | 8 | Message-id: 20241202131347.498124-41-peter.maydell@linaro.org |
9 | --- | ||
10 | linux-user/arm/nwfpe/fpa11.c | 5 +++++ | ||
11 | target/arm/cpu.c | 2 ++ | ||
12 | 2 files changed, 7 insertions(+) | ||
6 | 13 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220506180242.216785-21-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | docs/system/arm/emulation.rst | 3 ++ | ||
13 | target/arm/cpu.h | 16 +++++++++ | ||
14 | target/arm/cpu.c | 5 +++ | ||
15 | target/arm/cpu64.c | 3 +- | ||
16 | target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- | ||
17 | 5 files changed, 86 insertions(+), 2 deletions(-) | ||
18 | |||
19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
20 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/docs/system/arm/emulation.rst | 16 | --- a/linux-user/arm/nwfpe/fpa11.c |
22 | +++ b/docs/system/arm/emulation.rst | 17 | +++ b/linux-user/arm/nwfpe/fpa11.c |
23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 18 | @@ -XXX,XX +XXX,XX @@ void resetFPA11(void) |
24 | - FEAT_BF16 (AArch64 BFloat16 instructions) | 19 | * this late date. |
25 | - FEAT_BTI (Branch Target Identification) | 20 | */ |
26 | - FEAT_CSV2 (Cache speculation variant 2) | 21 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); |
27 | +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | 22 | + /* |
28 | +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | 23 | + * Use the same default NaN value as Arm VFP. This doesn't match |
29 | +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) | 24 | + * the Linux kernel's nwfpe emulation, which uses an all-1s value. |
30 | - FEAT_DIT (Data Independent Timing instructions) | 25 | + */ |
31 | - FEAT_DPB (DC CVAP instruction) | 26 | + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); |
32 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
33 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/cpu.h | ||
36 | +++ b/target/arm/cpu.h | ||
37 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
38 | ARMPACKey apdb; | ||
39 | ARMPACKey apga; | ||
40 | } keys; | ||
41 | + | ||
42 | + uint64_t scxtnum_el[4]; | ||
43 | #endif | ||
44 | |||
45 | #if defined(CONFIG_USER_ONLY) | ||
46 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | ||
47 | #define SCTLR_WXN (1U << 19) | ||
48 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | ||
49 | #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ | ||
50 | +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ | ||
51 | #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ | ||
52 | #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ | ||
53 | #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ | ||
54 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) | ||
55 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; | ||
56 | } | 27 | } |
57 | 28 | ||
58 | +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) | 29 | void SetRoundingMode(const unsigned int opcode) |
59 | +{ | ||
60 | + int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); | ||
61 | + if (key >= 2) { | ||
62 | + return true; /* FEAT_CSV2_2 */ | ||
63 | + } | ||
64 | + if (key == 1) { | ||
65 | + key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); | ||
66 | + return key >= 2; /* FEAT_CSV2_1p2 */ | ||
67 | + } | ||
68 | + return false; | ||
69 | +} | ||
70 | + | ||
71 | static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) | ||
72 | { | ||
73 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; | ||
74 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
75 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
76 | --- a/target/arm/cpu.c | 32 | --- a/target/arm/cpu.c |
77 | +++ b/target/arm/cpu.c | 33 | +++ b/target/arm/cpu.c |
78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | 34 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
79 | */ | 35 | * the pseudocode function the arguments are in the order c, a, b. |
80 | env->cp15.gcr_el1 = 0x1ffff; | 36 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, |
81 | } | 37 | * and the input NaN if it is signalling |
82 | + /* | 38 | + * * Default NaN has sign bit clear, msb frac bit set |
83 | + * Disable access to SCXTNUM_EL0 from CSV2_1p2. | 39 | */ |
84 | + * This is not yet exposed from the Linux kernel in any way. | 40 | static void arm_set_default_fp_behaviours(float_status *s) |
85 | + */ | 41 | { |
86 | + env->cp15.sctlr_el[1] |= SCTLR_TSCXT; | 42 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) |
87 | #else | 43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); |
88 | /* Reset into the highest available EL */ | 44 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); |
89 | if (arm_feature(env, ARM_FEATURE_EL3)) { | 45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); |
90 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 46 | + set_float_default_nan_pattern(0b01000000, s); |
91 | index XXXXXXX..XXXXXXX 100644 | 47 | } |
92 | --- a/target/arm/cpu64.c | 48 | |
93 | +++ b/target/arm/cpu64.c | 49 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
94 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
95 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
96 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
97 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
98 | - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ | ||
99 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | ||
100 | cpu->isar.id_aa64pfr0 = t; | ||
101 | |||
102 | t = cpu->isar.id_aa64pfr1; | ||
103 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
104 | * we do for EL2 with the virtualization=on property. | ||
105 | */ | ||
106 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
107 | + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ | ||
108 | cpu->isar.id_aa64pfr1 = t; | ||
109 | |||
110 | t = cpu->isar.id_aa64mmfr0; | ||
111 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/helper.c | ||
114 | +++ b/target/arm/helper.c | ||
115 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
116 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
117 | valid_mask |= SCR_ATA; | ||
118 | } | ||
119 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
120 | + valid_mask |= SCR_ENSCXT; | ||
121 | + } | ||
122 | } else { | ||
123 | valid_mask &= ~(SCR_RW | SCR_ST); | ||
124 | if (cpu_isar_feature(aa32_ras, cpu)) { | ||
125 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
126 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
127 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | ||
128 | } | ||
129 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
130 | + valid_mask |= HCR_ENSCXT; | ||
131 | + } | ||
132 | } | ||
133 | |||
134 | /* Clear RES0 bits. */ | ||
135 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
136 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), | ||
137 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | ||
138 | |||
139 | + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), | ||
140 | + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", | ||
141 | + isar_feature_aa64_scxtnum }, | ||
142 | + | ||
143 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ | ||
144 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | ||
145 | }; | ||
146 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
147 | }, | ||
148 | }; | ||
149 | |||
150 | -#endif | ||
151 | +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, | ||
152 | + bool isread) | ||
153 | +{ | ||
154 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
155 | + int el = arm_current_el(env); | ||
156 | + | ||
157 | + if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { | ||
158 | + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { | ||
159 | + if (hcr & HCR_TGE) { | ||
160 | + return CP_ACCESS_TRAP_EL2; | ||
161 | + } | ||
162 | + return CP_ACCESS_TRAP; | ||
163 | + } | ||
164 | + } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | ||
165 | + return CP_ACCESS_TRAP_EL2; | ||
166 | + } | ||
167 | + if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | ||
168 | + return CP_ACCESS_TRAP_EL2; | ||
169 | + } | ||
170 | + if (el < 3 | ||
171 | + && arm_feature(env, ARM_FEATURE_EL3) | ||
172 | + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | ||
173 | + return CP_ACCESS_TRAP_EL3; | ||
174 | + } | ||
175 | + return CP_ACCESS_OK; | ||
176 | +} | ||
177 | + | ||
178 | +static const ARMCPRegInfo scxtnum_reginfo[] = { | ||
179 | + { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | ||
180 | + .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | ||
181 | + .access = PL0_RW, .accessfn = access_scxtnum, | ||
182 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, | ||
183 | + { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | ||
184 | + .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | ||
185 | + .access = PL1_RW, .accessfn = access_scxtnum, | ||
186 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, | ||
187 | + { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | ||
188 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | ||
189 | + .access = PL2_RW, .accessfn = access_scxtnum, | ||
190 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | ||
191 | + { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | ||
192 | + .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | ||
193 | + .access = PL3_RW, | ||
194 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | ||
195 | +}; | ||
196 | +#endif /* TARGET_AARCH64 */ | ||
197 | |||
198 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
199 | bool isread) | ||
200 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
201 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | ||
202 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
203 | } | ||
204 | + | ||
205 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
206 | + define_arm_cp_regs(cpu, scxtnum_reginfo); | ||
207 | + } | ||
208 | #endif | ||
209 | |||
210 | if (cpu_isar_feature(any_predinv, cpu)) { | ||
211 | -- | 50 | -- |
212 | 2.25.1 | 51 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for loongarch. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-42-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/loongarch/tcg/fpu_helper.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/loongarch/tcg/fpu_helper.c | ||
13 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
14 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
15 | */ | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); | ||
18 | + /* Default NaN: sign bit clear, msb frac bit set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | } | ||
21 | |||
22 | int ieee_ex_to_loongarch(int xcpt) | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for m68k. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-43-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/m68k/cpu.c | 2 ++ | ||
8 | fpu/softfloat-specialize.c.inc | 2 +- | ||
9 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/m68k/cpu.c | ||
14 | +++ b/target/m68k/cpu.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
16 | * preceding paragraph for nonsignaling NaNs. | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | + /* Default NaN: sign bit clear, all frac bits set */ | ||
20 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
21 | |||
22 | nan = floatx80_default_nan(&env->fp_status); | ||
23 | for (i = 0; i < 8; i++) { | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
29 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
30 | |||
31 | if (dnan_pattern == 0) { | ||
32 | -#if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
33 | +#if defined(TARGET_SPARC) | ||
34 | /* Sign bit clear, all frac bits set */ | ||
35 | dnan_pattern = 0b01111111; | ||
36 | #elif defined(TARGET_HEXAGON) | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | Set the default NaN pattern explicitly for MIPS. Note that this |
---|---|---|---|
2 | is our only target which currently changes the default NaN | ||
3 | at runtime (which it was previously doing indirectly when it | ||
4 | changed the snan_bit_is_one setting). | ||
2 | 5 | ||
3 | Currently, the SMP configuration isn't considered when the CPU | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | topology is populated. In this case, it's impossible to provide | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | the default CPU-to-NUMA mapping or association based on the socket | 8 | Message-id: 20241202131347.498124-44-peter.maydell@linaro.org |
6 | ID of the given CPU. | 9 | --- |
10 | target/mips/fpu_helper.h | 7 +++++++ | ||
11 | target/mips/msa.c | 3 +++ | ||
12 | 2 files changed, 10 insertions(+) | ||
7 | 13 | ||
8 | This takes account of SMP configuration when the CPU topology | 14 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h |
9 | is populated. The die ID for the given CPU isn't assigned since | ||
10 | it's not supported on arm/virt machine. Besides, the used SMP | ||
11 | configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted | ||
12 | to avoid testing failure | ||
13 | |||
14 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
15 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
16 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
17 | Message-id: 20220503140304.855514-4-gshan@redhat.com | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | hw/arm/virt.c | 15 ++++++++++++++- | ||
21 | 1 file changed, 14 insertions(+), 1 deletion(-) | ||
22 | |||
23 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/hw/arm/virt.c | 16 | --- a/target/mips/fpu_helper.h |
26 | +++ b/hw/arm/virt.c | 17 | +++ b/target/mips/fpu_helper.h |
27 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 18 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) |
28 | int n; | 19 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); |
29 | unsigned int max_cpus = ms->smp.max_cpus; | 20 | nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; |
30 | VirtMachineState *vms = VIRT_MACHINE(ms); | 21 | set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); |
31 | + MachineClass *mc = MACHINE_GET_CLASS(vms); | 22 | + /* |
32 | 23 | + * With nan2008, the default NaN value has the sign bit clear and the | |
33 | if (ms->possible_cpus) { | 24 | + * frac msb set; with the older mode, the sign bit is clear, and all |
34 | assert(ms->possible_cpus->len == max_cpus); | 25 | + * frac bits except the msb are set. |
35 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 26 | + */ |
36 | ms->possible_cpus->cpus[n].type = ms->cpu_type; | 27 | + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, |
37 | ms->possible_cpus->cpus[n].arch_id = | 28 | + &env->active_fpu.fp_status); |
38 | virt_cpu_mp_affinity(vms, n); | 29 | |
39 | + | 30 | } |
40 | + assert(!mc->smp_props.dies_supported); | 31 | |
41 | + ms->possible_cpus->cpus[n].props.has_socket_id = true; | 32 | diff --git a/target/mips/msa.c b/target/mips/msa.c |
42 | + ms->possible_cpus->cpus[n].props.socket_id = | 33 | index XXXXXXX..XXXXXXX 100644 |
43 | + n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); | 34 | --- a/target/mips/msa.c |
44 | + ms->possible_cpus->cpus[n].props.has_cluster_id = true; | 35 | +++ b/target/mips/msa.c |
45 | + ms->possible_cpus->cpus[n].props.cluster_id = | 36 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) |
46 | + (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; | 37 | /* Inf * 0 + NaN returns the input NaN */ |
47 | + ms->possible_cpus->cpus[n].props.has_core_id = true; | 38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, |
48 | + ms->possible_cpus->cpus[n].props.core_id = | 39 | &env->active_tc.msa_fp_status); |
49 | + (n / ms->smp.threads) % ms->smp.cores; | 40 | + /* Default NaN: sign bit clear, frac msb set */ |
50 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | 41 | + set_float_default_nan_pattern(0b01000000, |
51 | - ms->possible_cpus->cpus[n].props.thread_id = n; | 42 | + &env->active_tc.msa_fp_status); |
52 | + ms->possible_cpus->cpus[n].props.thread_id = | ||
53 | + n % ms->smp.threads; | ||
54 | } | ||
55 | return ms->possible_cpus; | ||
56 | } | 43 | } |
57 | -- | 44 | -- |
58 | 2.25.1 | 45 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for openrisc. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-45-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/openrisc/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/openrisc/cpu.c | ||
13 | +++ b/target/openrisc/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | */ | ||
16 | set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); | ||
17 | |||
18 | + /* Default NaN: sign bit clear, frac msb set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); | ||
20 | |||
21 | #ifndef CONFIG_USER_ONLY | ||
22 | cpu->env.picmr = 0x00000000; | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the default NaN pattern explicitly for ppc. |
---|---|---|---|
2 | 2 | ||
3 | We set this for qemu-system-aarch64, but failed to do so | ||
4 | for the strictly 32-bit emulation. | ||
5 | |||
6 | Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220506180242.216785-8-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-46-peter.maydell@linaro.org | ||
11 | --- | 6 | --- |
12 | target/arm/cpu_tcg.c | 4 ++++ | 7 | target/ppc/cpu_init.c | 4 ++++ |
13 | 1 file changed, 4 insertions(+) | 8 | 1 file changed, 4 insertions(+) |
14 | 9 | ||
15 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 10 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c |
16 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu_tcg.c | 12 | --- a/target/ppc/cpu_init.c |
18 | +++ b/target/arm/cpu_tcg.c | 13 | +++ b/target/ppc/cpu_init.c |
19 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | 14 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) |
20 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | 15 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
21 | cpu->isar.id_pfr2 = t; | 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); |
22 | 17 | ||
23 | + t = cpu->isar.id_dfr0; | 18 | + /* Default NaN: sign bit clear, set frac msb */ |
24 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
25 | + cpu->isar.id_dfr0 = t; | 20 | + set_float_default_nan_pattern(0b01000000, &env->vec_status); |
26 | + | 21 | + |
27 | #ifdef CONFIG_USER_ONLY | 22 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { |
28 | /* | 23 | ppc_spr_t *spr = &env->spr_cb[i]; |
29 | * Break with true ARMv8 and add back old-style VFP short-vector support. | 24 | |
30 | -- | 25 | -- |
31 | 2.25.1 | 26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for sh4. Note that sh4 | ||
2 | is one of the only three targets (the others being HPPA and | ||
3 | sometimes MIPS) that has snan_bit_is_one set. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-47-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/sh4/cpu.c | 2 ++ | ||
10 | 1 file changed, 2 insertions(+) | ||
11 | |||
12 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sh4/cpu.c | ||
15 | +++ b/target/sh4/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_flush_to_zero(1, &env->fp_status); | ||
18 | #endif | ||
19 | set_default_nan_mode(1, &env->fp_status); | ||
20 | + /* sign bit clear, set all frac bits other than msb */ | ||
21 | + set_float_default_nan_pattern(0b00111111, &env->fp_status); | ||
22 | } | ||
23 | |||
24 | static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for rx. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-48-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/rx/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/rx/cpu.c | ||
13 | +++ b/target/rx/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | * then prefer dest over source", which is float_2nan_prop_s_ab. | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
18 | + /* Default NaN value: sign bit clear, set frac msb */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | } | ||
21 | |||
22 | static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for s390x. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-49-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/s390x/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/s390x/cpu.c | ||
13 | +++ b/target/s390x/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
17 | &env->fpu_status); | ||
18 | + /* Default NaN value: sign bit clear, frac msb set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fpu_status); | ||
20 | /* fall through */ | ||
21 | case RESET_TYPE_S390_CPU_NORMAL: | ||
22 | env->psw.mask &= ~PSW_MASK_RI; | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for SPARC, and remove | ||
2 | the ifdef from parts64_default_nan. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-50-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 5 +---- | ||
10 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | ||
18 | /* For inf * 0 + NaN, return the input NaN */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + /* Default NaN value: sign bit clear, all frac bits set */ | ||
21 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
22 | |||
23 | cpu_exec_realizefn(cs, &local_err); | ||
24 | if (local_err != NULL) { | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
31 | |||
32 | if (dnan_pattern == 0) { | ||
33 | -#if defined(TARGET_SPARC) | ||
34 | - /* Sign bit clear, all frac bits set */ | ||
35 | - dnan_pattern = 0b01111111; | ||
36 | -#elif defined(TARGET_HEXAGON) | ||
37 | +#if defined(TARGET_HEXAGON) | ||
38 | /* Sign bit set, all frac bits set. */ | ||
39 | dnan_pattern = 0b11111111; | ||
40 | #else | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the default NaN pattern explicitly for xtensa. |
---|---|---|---|
2 | 2 | ||
3 | Update the legacy feature names to the current names. | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Provide feature names for id changes that were not marked. | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Sort the field updates into increasing bitfield order. | 5 | Message-id: 20241202131347.498124-51-peter.maydell@linaro.org |
6 | --- | ||
7 | target/xtensa/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
6 | 9 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220506180242.216785-10-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/cpu64.c | 100 +++++++++++++++++++++---------------------- | ||
13 | target/arm/cpu_tcg.c | 48 ++++++++++----------- | ||
14 | 2 files changed, 74 insertions(+), 74 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu64.c | 12 | --- a/target/xtensa/cpu.c |
19 | +++ b/target/arm/cpu64.c | 13 | +++ b/target/xtensa/cpu.c |
20 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 14 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) |
21 | cpu->midr = t; | 15 | /* For inf * 0 + NaN, return the input NaN */ |
22 | 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | |
23 | t = cpu->isar.id_aa64isar0; | 17 | set_no_signaling_nans(!dfpu, &env->fp_status); |
24 | - t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ | 18 | + /* Default NaN value: sign bit clear, set frac msb */ |
25 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
26 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ | 20 | xtensa_use_first_nan(env, !dfpu); |
27 | + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ | ||
28 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ | ||
29 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ | ||
30 | t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | ||
31 | - t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); | ||
32 | - t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); | ||
33 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); | ||
34 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); | ||
35 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); | ||
36 | - t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); | ||
37 | - t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); | ||
38 | - t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ | ||
39 | - t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | ||
40 | - t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); | ||
41 | + t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ | ||
42 | + t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | ||
43 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | ||
44 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ | ||
45 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ | ||
46 | + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ | ||
47 | + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ | ||
48 | + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ | ||
49 | + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | ||
50 | + t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ | ||
51 | cpu->isar.id_aa64isar0 = t; | ||
52 | |||
53 | t = cpu->isar.id_aa64isar1; | ||
54 | - t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); | ||
55 | - t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); | ||
56 | - t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); | ||
57 | - t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | ||
58 | - t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | ||
59 | - t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); | ||
60 | - t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); | ||
61 | - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ | ||
62 | - t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); | ||
63 | + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ | ||
64 | + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ | ||
65 | + t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ | ||
66 | + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ | ||
67 | + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ | ||
68 | + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | ||
69 | + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | ||
70 | + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | ||
71 | + t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | ||
72 | cpu->isar.id_aa64isar1 = t; | ||
73 | |||
74 | t = cpu->isar.id_aa64pfr0; | ||
75 | + t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | ||
76 | + t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | ||
77 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
78 | - t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); | ||
79 | - t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); | ||
80 | - t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); | ||
81 | - t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); | ||
82 | + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
83 | + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
84 | cpu->isar.id_aa64pfr0 = t; | ||
85 | |||
86 | t = cpu->isar.id_aa64pfr1; | ||
87 | - t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | ||
88 | - t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); | ||
89 | + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ | ||
90 | + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ | ||
91 | /* | ||
92 | * Begin with full support for MTE. This will be downgraded to MTE=0 | ||
93 | * during realize if the board provides no tag memory, much like | ||
94 | * we do for EL2 with the virtualization=on property. | ||
95 | */ | ||
96 | - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); | ||
97 | + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
98 | cpu->isar.id_aa64pfr1 = t; | ||
99 | |||
100 | t = cpu->isar.id_aa64mmfr0; | ||
101 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
102 | cpu->isar.id_aa64mmfr0 = t; | ||
103 | |||
104 | t = cpu->isar.id_aa64mmfr1; | ||
105 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | ||
106 | - t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); | ||
107 | - t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); | ||
108 | - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ | ||
109 | - t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ | ||
110 | - t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ | ||
111 | + t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | ||
112 | + t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | ||
113 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | ||
114 | + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | ||
115 | + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ | ||
116 | + t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | ||
117 | cpu->isar.id_aa64mmfr1 = t; | ||
118 | |||
119 | t = cpu->isar.id_aa64mmfr2; | ||
120 | - t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | ||
121 | - t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | ||
122 | - t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | ||
123 | - t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
124 | - t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
125 | - t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
126 | + t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | ||
127 | + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | ||
128 | + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
129 | + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | ||
130 | + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
131 | + t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
132 | cpu->isar.id_aa64mmfr2 = t; | ||
133 | |||
134 | t = cpu->isar.id_aa64zfr0; | ||
135 | t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); | ||
136 | - t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ | ||
137 | - t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); | ||
138 | - t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); | ||
139 | - t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); | ||
140 | - t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); | ||
141 | - t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); | ||
142 | - t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); | ||
143 | - t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
144 | + t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ | ||
145 | + t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ | ||
146 | + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ | ||
147 | + t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ | ||
148 | + t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ | ||
149 | + t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ | ||
150 | + t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ | ||
151 | + t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ | ||
152 | cpu->isar.id_aa64zfr0 = t; | ||
153 | |||
154 | t = cpu->isar.id_aa64dfr0; | ||
155 | - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
156 | + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | ||
157 | cpu->isar.id_aa64dfr0 = t; | ||
158 | |||
159 | /* Replicate the same data to the 32-bit id registers. */ | ||
160 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
161 | index XXXXXXX..XXXXXXX 100644 | ||
162 | --- a/target/arm/cpu_tcg.c | ||
163 | +++ b/target/arm/cpu_tcg.c | ||
164 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
165 | |||
166 | /* Add additional features supported by QEMU */ | ||
167 | t = cpu->isar.id_isar5; | ||
168 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
169 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
170 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
171 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ | ||
172 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ | ||
173 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ | ||
174 | t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
175 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
176 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
177 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ | ||
178 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ | ||
179 | cpu->isar.id_isar5 = t; | ||
180 | |||
181 | t = cpu->isar.id_isar6; | ||
182 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
183 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
184 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
185 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
186 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
187 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
188 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
189 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ | ||
190 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ | ||
191 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ | ||
192 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ | ||
193 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ | ||
194 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ | ||
195 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ | ||
196 | cpu->isar.id_isar6 = t; | ||
197 | |||
198 | t = cpu->isar.mvfr1; | ||
199 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
200 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
201 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ | ||
202 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ | ||
203 | cpu->isar.mvfr1 = t; | ||
204 | |||
205 | t = cpu->isar.mvfr2; | ||
206 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
207 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
208 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
209 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
210 | cpu->isar.mvfr2 = t; | ||
211 | |||
212 | t = cpu->isar.id_mmfr3; | ||
213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
214 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ | ||
215 | cpu->isar.id_mmfr3 = t; | ||
216 | |||
217 | t = cpu->isar.id_mmfr4; | ||
218 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
219 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
220 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
221 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
222 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ | ||
223 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
224 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ | ||
225 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ | ||
226 | cpu->isar.id_mmfr4 = t; | ||
227 | |||
228 | t = cpu->isar.id_pfr0; | ||
229 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
230 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
231 | cpu->isar.id_pfr0 = t; | ||
232 | |||
233 | t = cpu->isar.id_pfr2; | ||
234 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
235 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | ||
236 | cpu->isar.id_pfr2 = t; | ||
237 | |||
238 | t = cpu->isar.id_dfr0; | ||
239 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
240 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
241 | cpu->isar.id_dfr0 = t; | ||
242 | } | 21 | } |
243 | 22 | ||
244 | -- | 23 | -- |
245 | 2.25.1 | 24 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the default NaN pattern explicitly for hexagon. |
---|---|---|---|
2 | Remove the ifdef from parts64_default_nan(); the only | ||
3 | remaining unconverted targets all use the default case. | ||
2 | 4 | ||
3 | Instead of starting with cortex-a15 and adding v8 features to | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | This fixes the long-standing to-do where we only enabled v8 | 7 | Message-id: 20241202131347.498124-52-peter.maydell@linaro.org |
6 | features for user-only. | 8 | --- |
9 | target/hexagon/cpu.c | 2 ++ | ||
10 | fpu/softfloat-specialize.c.inc | 5 ----- | ||
11 | 2 files changed, 2 insertions(+), 5 deletions(-) | ||
7 | 12 | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220506180242.216785-7-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- | ||
14 | 1 file changed, 92 insertions(+), 59 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu_tcg.c | 15 | --- a/target/hexagon/cpu.c |
19 | +++ b/target/arm/cpu_tcg.c | 16 | +++ b/target/hexagon/cpu.c |
20 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | 17 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) |
21 | static void arm_max_initfn(Object *obj) | 18 | |
22 | { | 19 | set_default_nan_mode(1, &env->fp_status); |
23 | ARMCPU *cpu = ARM_CPU(obj); | 20 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); |
24 | + uint32_t t; | 21 | + /* Default NaN value: sign bit set, all frac bits set */ |
25 | 22 | + set_float_default_nan_pattern(0b11111111, &env->fp_status); | |
26 | - cortex_a15_initfn(obj); | ||
27 | + /* aarch64_a57_initfn, advertising none of the aarch64 features */ | ||
28 | + cpu->dtb_compatible = "arm,cortex-a57"; | ||
29 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
30 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
31 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
32 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
33 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
34 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
35 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
36 | + cpu->midr = 0x411fd070; | ||
37 | + cpu->revidr = 0x00000000; | ||
38 | + cpu->reset_fpsid = 0x41034070; | ||
39 | + cpu->isar.mvfr0 = 0x10110222; | ||
40 | + cpu->isar.mvfr1 = 0x12111111; | ||
41 | + cpu->isar.mvfr2 = 0x00000043; | ||
42 | + cpu->ctr = 0x8444c004; | ||
43 | + cpu->reset_sctlr = 0x00c50838; | ||
44 | + cpu->isar.id_pfr0 = 0x00000131; | ||
45 | + cpu->isar.id_pfr1 = 0x00011011; | ||
46 | + cpu->isar.id_dfr0 = 0x03010066; | ||
47 | + cpu->id_afr0 = 0x00000000; | ||
48 | + cpu->isar.id_mmfr0 = 0x10101105; | ||
49 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
50 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
51 | + cpu->isar.id_mmfr3 = 0x02102211; | ||
52 | + cpu->isar.id_isar0 = 0x02101110; | ||
53 | + cpu->isar.id_isar1 = 0x13112111; | ||
54 | + cpu->isar.id_isar2 = 0x21232042; | ||
55 | + cpu->isar.id_isar3 = 0x01112131; | ||
56 | + cpu->isar.id_isar4 = 0x00011142; | ||
57 | + cpu->isar.id_isar5 = 0x00011121; | ||
58 | + cpu->isar.id_isar6 = 0; | ||
59 | + cpu->isar.dbgdidr = 0x3516d000; | ||
60 | + cpu->clidr = 0x0a200023; | ||
61 | + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
62 | + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | ||
63 | + cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
64 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
65 | |||
66 | - /* old-style VFP short-vector support */ | ||
67 | - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
68 | + /* Add additional features supported by QEMU */ | ||
69 | + t = cpu->isar.id_isar5; | ||
70 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
71 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
72 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
73 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
74 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
75 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
76 | + cpu->isar.id_isar5 = t; | ||
77 | + | ||
78 | + t = cpu->isar.id_isar6; | ||
79 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
80 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
81 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
82 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
83 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
84 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
85 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
86 | + cpu->isar.id_isar6 = t; | ||
87 | + | ||
88 | + t = cpu->isar.mvfr1; | ||
89 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
90 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
91 | + cpu->isar.mvfr1 = t; | ||
92 | + | ||
93 | + t = cpu->isar.mvfr2; | ||
94 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
95 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
96 | + cpu->isar.mvfr2 = t; | ||
97 | + | ||
98 | + t = cpu->isar.id_mmfr3; | ||
99 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
100 | + cpu->isar.id_mmfr3 = t; | ||
101 | + | ||
102 | + t = cpu->isar.id_mmfr4; | ||
103 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
104 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
105 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
106 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
107 | + cpu->isar.id_mmfr4 = t; | ||
108 | + | ||
109 | + t = cpu->isar.id_pfr0; | ||
110 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
111 | + cpu->isar.id_pfr0 = t; | ||
112 | + | ||
113 | + t = cpu->isar.id_pfr2; | ||
114 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
115 | + cpu->isar.id_pfr2 = t; | ||
116 | |||
117 | #ifdef CONFIG_USER_ONLY | ||
118 | /* | ||
119 | - * We don't set these in system emulation mode for the moment, | ||
120 | - * since we don't correctly set (all of) the ID registers to | ||
121 | - * advertise them. | ||
122 | + * Break with true ARMv8 and add back old-style VFP short-vector support. | ||
123 | + * Only do this for user-mode, where -cpu max is the default, so that | ||
124 | + * older v6 and v7 programs are more likely to work without adjustment. | ||
125 | */ | ||
126 | - set_feature(&cpu->env, ARM_FEATURE_V8); | ||
127 | - { | ||
128 | - uint32_t t; | ||
129 | - | ||
130 | - t = cpu->isar.id_isar5; | ||
131 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
132 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
133 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
134 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
135 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
136 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
137 | - cpu->isar.id_isar5 = t; | ||
138 | - | ||
139 | - t = cpu->isar.id_isar6; | ||
140 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
141 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
142 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
143 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
144 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
145 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
146 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
147 | - cpu->isar.id_isar6 = t; | ||
148 | - | ||
149 | - t = cpu->isar.mvfr1; | ||
150 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
151 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
152 | - cpu->isar.mvfr1 = t; | ||
153 | - | ||
154 | - t = cpu->isar.mvfr2; | ||
155 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
156 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
157 | - cpu->isar.mvfr2 = t; | ||
158 | - | ||
159 | - t = cpu->isar.id_mmfr3; | ||
160 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
161 | - cpu->isar.id_mmfr3 = t; | ||
162 | - | ||
163 | - t = cpu->isar.id_mmfr4; | ||
164 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
165 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
166 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
167 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
168 | - cpu->isar.id_mmfr4 = t; | ||
169 | - | ||
170 | - t = cpu->isar.id_pfr0; | ||
171 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
172 | - cpu->isar.id_pfr0 = t; | ||
173 | - | ||
174 | - t = cpu->isar.id_pfr2; | ||
175 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
176 | - cpu->isar.id_pfr2 = t; | ||
177 | - } | ||
178 | -#endif /* CONFIG_USER_ONLY */ | ||
179 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
180 | +#endif | ||
181 | } | 23 | } |
182 | #endif /* !TARGET_AARCH64 */ | 24 | |
25 | static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) | ||
26 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/fpu/softfloat-specialize.c.inc | ||
29 | +++ b/fpu/softfloat-specialize.c.inc | ||
30 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
31 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
32 | |||
33 | if (dnan_pattern == 0) { | ||
34 | -#if defined(TARGET_HEXAGON) | ||
35 | - /* Sign bit set, all frac bits set. */ | ||
36 | - dnan_pattern = 0b11111111; | ||
37 | -#else | ||
38 | /* | ||
39 | * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
40 | * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
41 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
42 | /* sign bit clear, set frac msb */ | ||
43 | dnan_pattern = 0b01000000; | ||
44 | } | ||
45 | -#endif | ||
46 | } | ||
47 | assert(dnan_pattern != 0); | ||
183 | 48 | ||
184 | -- | 49 | -- |
185 | 2.25.1 | 50 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for riscv. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-53-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/riscv/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/riscv/cpu.c | ||
13 | +++ b/target/riscv/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | cs->exception_index = RISCV_EXCP_NONE; | ||
16 | env->load_res = -1; | ||
17 | set_default_nan_mode(1, &env->fp_status); | ||
18 | + /* Default NaN value: sign bit clear, frac msb set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | env->vill = true; | ||
21 | |||
22 | #ifndef CONFIG_USER_ONLY | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | Set the default NaN pattern explicitly for tricore. |
---|---|---|---|
2 | 2 | ||
3 | When CPU-to-NUMA association isn't explicitly provided by users, | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | the default one is given by mc->get_default_cpu_node_id(). However, | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | the CPU topology isn't fully considered in the default association | 5 | Message-id: 20241202131347.498124-54-peter.maydell@linaro.org |
6 | and this causes CPU topology broken warnings on booting Linux guest. | 6 | --- |
7 | target/tricore/helper.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
7 | 9 | ||
8 | For example, the following warning messages are observed when the | 10 | diff --git a/target/tricore/helper.c b/target/tricore/helper.c |
9 | Linux guest is booted with the following command lines. | ||
10 | |||
11 | /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ | ||
12 | -accel kvm -machine virt,gic-version=host \ | ||
13 | -cpu host \ | ||
14 | -smp 6,sockets=2,cores=3,threads=1 \ | ||
15 | -m 1024M,slots=16,maxmem=64G \ | ||
16 | -object memory-backend-ram,id=mem0,size=128M \ | ||
17 | -object memory-backend-ram,id=mem1,size=128M \ | ||
18 | -object memory-backend-ram,id=mem2,size=128M \ | ||
19 | -object memory-backend-ram,id=mem3,size=128M \ | ||
20 | -object memory-backend-ram,id=mem4,size=128M \ | ||
21 | -object memory-backend-ram,id=mem4,size=384M \ | ||
22 | -numa node,nodeid=0,memdev=mem0 \ | ||
23 | -numa node,nodeid=1,memdev=mem1 \ | ||
24 | -numa node,nodeid=2,memdev=mem2 \ | ||
25 | -numa node,nodeid=3,memdev=mem3 \ | ||
26 | -numa node,nodeid=4,memdev=mem4 \ | ||
27 | -numa node,nodeid=5,memdev=mem5 | ||
28 | : | ||
29 | alternatives: patching kernel code | ||
30 | BUG: arch topology borken | ||
31 | the CLS domain not a subset of the MC domain | ||
32 | <the above error log repeats> | ||
33 | BUG: arch topology borken | ||
34 | the DIE domain not a subset of the NODE domain | ||
35 | |||
36 | With current implementation of mc->get_default_cpu_node_id(), | ||
37 | CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately. | ||
38 | That's incorrect because CPU#0/1/2 should be associated with same | ||
39 | NUMA node because they're seated in same socket. | ||
40 | |||
41 | This fixes the issue by considering the socket ID when the default | ||
42 | CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids(). | ||
43 | With this applied, no more CPU topology broken warnings are seen | ||
44 | from the Linux guest. The 6 CPUs are associated with NODE#0/1, but | ||
45 | there are no CPUs associated with NODE#2/3/4/5. | ||
46 | |||
47 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
48 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
49 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
50 | Message-id: 20220503140304.855514-6-gshan@redhat.com | ||
51 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
52 | --- | ||
53 | hw/arm/virt.c | 4 +++- | ||
54 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
55 | |||
56 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
58 | --- a/hw/arm/virt.c | 12 | --- a/target/tricore/helper.c |
59 | +++ b/hw/arm/virt.c | 13 | +++ b/target/tricore/helper.c |
60 | @@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | 14 | @@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env) |
61 | 15 | set_flush_to_zero(1, &env->fp_status); | |
62 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) | 16 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); |
63 | { | 17 | set_default_nan_mode(1, &env->fp_status); |
64 | - return idx % ms->numa_state->num_nodes; | 18 | + /* Default NaN pattern: sign bit clear, frac msb set */ |
65 | + int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
66 | + | ||
67 | + return socket_id % ms->numa_state->num_nodes; | ||
68 | } | 20 | } |
69 | 21 | ||
70 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 22 | uint32_t psw_read(CPUTriCoreState *env) |
71 | -- | 23 | -- |
72 | 2.25.1 | 24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Now that all our targets have bene converted to explicitly specify | ||
2 | their pattern for the default NaN value we can remove the remaining | ||
3 | fallback code in parts64_default_nan(). | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-55-peter.maydell@linaro.org | ||
8 | --- | ||
9 | fpu/softfloat-specialize.c.inc | 14 -------------- | ||
10 | 1 file changed, 14 deletions(-) | ||
11 | |||
12 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/fpu/softfloat-specialize.c.inc | ||
15 | +++ b/fpu/softfloat-specialize.c.inc | ||
16 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
17 | uint64_t frac; | ||
18 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
19 | |||
20 | - if (dnan_pattern == 0) { | ||
21 | - /* | ||
22 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
23 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
24 | - * do not have floating-point. | ||
25 | - */ | ||
26 | - if (snan_bit_is_one(status)) { | ||
27 | - /* sign bit clear, set all frac bits other than msb */ | ||
28 | - dnan_pattern = 0b00111111; | ||
29 | - } else { | ||
30 | - /* sign bit clear, set frac msb */ | ||
31 | - dnan_pattern = 0b01000000; | ||
32 | - } | ||
33 | - } | ||
34 | assert(dnan_pattern != 0); | ||
35 | |||
36 | sign = dnan_pattern >> 7; | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable writes to the TERR and TEA bits when RAS is enabled. | 3 | Inline pickNaNMulAdd into its only caller. This makes |
4 | These bits are otherwise RES0. | 4 | one assert redundant with the immediately preceding IF. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-15-richard.henderson@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20241203203949.483774-3-richard.henderson@linaro.org | ||
9 | [PMM: keep comment from old code in new location] | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | target/arm/helper.c | 9 +++++++++ | 12 | fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++- |
12 | 1 file changed, 9 insertions(+) | 13 | fpu/softfloat-specialize.c.inc | 54 ---------------------------------- |
14 | 2 files changed, 40 insertions(+), 55 deletions(-) | ||
13 | 15 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 18 | --- a/fpu/softfloat-parts.c.inc |
17 | +++ b/target/arm/helper.c | 19 | +++ b/fpu/softfloat-parts.c.inc |
18 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
19 | } | 21 | } |
20 | valid_mask &= ~SCR_NET; | 22 | |
21 | 23 | if (s->default_nan_mode) { | |
22 | + if (cpu_isar_feature(aa64_ras, cpu)) { | 24 | + /* |
23 | + valid_mask |= SCR_TERR; | 25 | + * We guarantee not to require the target to tell us how to |
26 | + * pick a NaN if we're always returning the default NaN. | ||
27 | + * But if we're not in default-NaN mode then the target must | ||
28 | + * specify. | ||
29 | + */ | ||
30 | which = 3; | ||
31 | + } else if (infzero) { | ||
32 | + /* | ||
33 | + * Inf * 0 + NaN -- some implementations return the | ||
34 | + * default NaN here, and some return the input NaN. | ||
35 | + */ | ||
36 | + switch (s->float_infzeronan_rule) { | ||
37 | + case float_infzeronan_dnan_never: | ||
38 | + which = 2; | ||
39 | + break; | ||
40 | + case float_infzeronan_dnan_always: | ||
41 | + which = 3; | ||
42 | + break; | ||
43 | + case float_infzeronan_dnan_if_qnan: | ||
44 | + which = is_qnan(c->cls) ? 3 : 2; | ||
45 | + break; | ||
46 | + default: | ||
47 | + g_assert_not_reached(); | ||
24 | + } | 48 | + } |
25 | if (cpu_isar_feature(aa64_lor, cpu)) { | ||
26 | valid_mask |= SCR_TLOR; | ||
27 | } | ||
28 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
29 | } | ||
30 | } else { | 49 | } else { |
31 | valid_mask &= ~(SCR_RW | SCR_ST); | 50 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); |
32 | + if (cpu_isar_feature(aa32_ras, cpu)) { | 51 | + FloatClass cls[3] = { a->cls, b->cls, c->cls }; |
33 | + valid_mask |= SCR_TERR; | 52 | + Float3NaNPropRule rule = s->float_3nan_prop_rule; |
53 | + | ||
54 | + assert(rule != float_3nan_prop_none); | ||
55 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
56 | + /* We have at least one SNaN input and should prefer it */ | ||
57 | + do { | ||
58 | + which = rule & R_3NAN_1ST_MASK; | ||
59 | + rule >>= R_3NAN_1ST_LENGTH; | ||
60 | + } while (!is_snan(cls[which])); | ||
61 | + } else { | ||
62 | + do { | ||
63 | + which = rule & R_3NAN_1ST_MASK; | ||
64 | + rule >>= R_3NAN_1ST_LENGTH; | ||
65 | + } while (!is_nan(cls[which])); | ||
34 | + } | 66 | + } |
35 | } | 67 | } |
36 | 68 | ||
37 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | 69 | if (which == 3) { |
38 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | 70 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
39 | if (cpu_isar_feature(aa64_vh, cpu)) { | 71 | index XXXXXXX..XXXXXXX 100644 |
40 | valid_mask |= HCR_E2H; | 72 | --- a/fpu/softfloat-specialize.c.inc |
41 | } | 73 | +++ b/fpu/softfloat-specialize.c.inc |
42 | + if (cpu_isar_feature(aa64_ras, cpu)) { | 74 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
43 | + valid_mask |= HCR_TERR | HCR_TEA; | 75 | } |
44 | + } | 76 | } |
45 | if (cpu_isar_feature(aa64_lor, cpu)) { | 77 | |
46 | valid_mask |= HCR_TLOR; | 78 | -/*---------------------------------------------------------------------------- |
47 | } | 79 | -| Select which NaN to propagate for a three-input operation. |
80 | -| For the moment we assume that no CPU needs the 'larger significand' | ||
81 | -| information. | ||
82 | -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | ||
83 | -*----------------------------------------------------------------------------*/ | ||
84 | -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
85 | - bool infzero, bool have_snan, float_status *status) | ||
86 | -{ | ||
87 | - FloatClass cls[3] = { a_cls, b_cls, c_cls }; | ||
88 | - Float3NaNPropRule rule = status->float_3nan_prop_rule; | ||
89 | - int which; | ||
90 | - | ||
91 | - /* | ||
92 | - * We guarantee not to require the target to tell us how to | ||
93 | - * pick a NaN if we're always returning the default NaN. | ||
94 | - * But if we're not in default-NaN mode then the target must | ||
95 | - * specify. | ||
96 | - */ | ||
97 | - assert(!status->default_nan_mode); | ||
98 | - | ||
99 | - if (infzero) { | ||
100 | - /* | ||
101 | - * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
102 | - * and some return the input NaN. | ||
103 | - */ | ||
104 | - switch (status->float_infzeronan_rule) { | ||
105 | - case float_infzeronan_dnan_never: | ||
106 | - return 2; | ||
107 | - case float_infzeronan_dnan_always: | ||
108 | - return 3; | ||
109 | - case float_infzeronan_dnan_if_qnan: | ||
110 | - return is_qnan(c_cls) ? 3 : 2; | ||
111 | - default: | ||
112 | - g_assert_not_reached(); | ||
113 | - } | ||
114 | - } | ||
115 | - | ||
116 | - assert(rule != float_3nan_prop_none); | ||
117 | - if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
118 | - /* We have at least one SNaN input and should prefer it */ | ||
119 | - do { | ||
120 | - which = rule & R_3NAN_1ST_MASK; | ||
121 | - rule >>= R_3NAN_1ST_LENGTH; | ||
122 | - } while (!is_snan(cls[which])); | ||
123 | - } else { | ||
124 | - do { | ||
125 | - which = rule & R_3NAN_1ST_MASK; | ||
126 | - rule >>= R_3NAN_1ST_LENGTH; | ||
127 | - } while (!is_nan(cls[which])); | ||
128 | - } | ||
129 | - return which; | ||
130 | -} | ||
131 | - | ||
132 | /*---------------------------------------------------------------------------- | ||
133 | | Returns 1 if the double-precision floating-point value `a' is a quiet | ||
134 | | NaN; otherwise returns 0. | ||
48 | -- | 135 | -- |
49 | 2.25.1 | 136 | 2.34.1 |
137 | |||
138 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The CPU topology isn't enabled on arm/virt machine yet, but we're | 3 | Remove "3" as a special case for which and simply |
4 | going to do it in next patch. After the CPU topology is enabled by | 4 | branch to return the desired value. |
5 | next patch, "thread-id=1" becomes invalid because the CPU core is | ||
6 | preferred on arm/virt machine. It means these two CPUs have 0/1 | ||
7 | as their core IDs, but their thread IDs are all 0. It will trigger | ||
8 | test failure as the following message indicates: | ||
9 | 5 | ||
10 | [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | 1.48s killed by signal 6 SIGABRT | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \ | 8 | Message-id: 20241203203949.483774-4-richard.henderson@linaro.org |
13 | QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \ | ||
14 | QTEST_QEMU_BINARY=./qemu-system-aarch64 \ | ||
15 | QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \ | ||
16 | /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k | ||
17 | ―――――――――――――――――――――――――――――――――――――――――――――― | ||
18 | stderr: | ||
19 | qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found | ||
20 | |||
21 | This fixes the issue by providing comprehensive SMP configurations | ||
22 | in aarch64_numa_cpu(). The SMP configurations aren't used before | ||
23 | the CPU topology is enabled in next patch. | ||
24 | |||
25 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
26 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
27 | Message-id: 20220503140304.855514-3-gshan@redhat.com | ||
28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
29 | --- | 10 | --- |
30 | tests/qtest/numa-test.c | 3 ++- | 11 | fpu/softfloat-parts.c.inc | 20 ++++++++++---------- |
31 | 1 file changed, 2 insertions(+), 1 deletion(-) | 12 | 1 file changed, 10 insertions(+), 10 deletions(-) |
32 | 13 | ||
33 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
34 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/tests/qtest/numa-test.c | 16 | --- a/fpu/softfloat-parts.c.inc |
36 | +++ b/tests/qtest/numa-test.c | 17 | +++ b/fpu/softfloat-parts.c.inc |
37 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
38 | QTestState *qts; | 19 | * But if we're not in default-NaN mode then the target must |
39 | g_autofree char *cli = NULL; | 20 | * specify. |
40 | 21 | */ | |
41 | - cli = make_cli(data, "-machine smp.cpus=2 " | 22 | - which = 3; |
42 | + cli = make_cli(data, "-machine " | 23 | + goto default_nan; |
43 | + "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " | 24 | } else if (infzero) { |
44 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " | 25 | /* |
45 | "-numa cpu,node-id=1,thread-id=0 " | 26 | * Inf * 0 + NaN -- some implementations return the |
46 | "-numa cpu,node-id=0,thread-id=1"); | 27 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
28 | */ | ||
29 | switch (s->float_infzeronan_rule) { | ||
30 | case float_infzeronan_dnan_never: | ||
31 | - which = 2; | ||
32 | break; | ||
33 | case float_infzeronan_dnan_always: | ||
34 | - which = 3; | ||
35 | - break; | ||
36 | + goto default_nan; | ||
37 | case float_infzeronan_dnan_if_qnan: | ||
38 | - which = is_qnan(c->cls) ? 3 : 2; | ||
39 | + if (is_qnan(c->cls)) { | ||
40 | + goto default_nan; | ||
41 | + } | ||
42 | break; | ||
43 | default: | ||
44 | g_assert_not_reached(); | ||
45 | } | ||
46 | + which = 2; | ||
47 | } else { | ||
48 | FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
49 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
50 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
51 | } | ||
52 | } | ||
53 | |||
54 | - if (which == 3) { | ||
55 | - parts_default_nan(a, s); | ||
56 | - return a; | ||
57 | - } | ||
58 | - | ||
59 | switch (which) { | ||
60 | case 0: | ||
61 | break; | ||
62 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
63 | parts_silence_nan(a, s); | ||
64 | } | ||
65 | return a; | ||
66 | + | ||
67 | + default_nan: | ||
68 | + parts_default_nan(a, s); | ||
69 | + return a; | ||
70 | } | ||
71 | |||
72 | /* | ||
47 | -- | 73 | -- |
48 | 2.25.1 | 74 | 2.34.1 |
49 | 75 | ||
50 | 76 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | More gracefully handle cpregs when EL2 and/or EL3 are missing. | 3 | Assign the pointer return value to 'a' directly, |
4 | If the reg is entirely inaccessible, do not register it at all. | 4 | rather than going through an intermediary index. |
5 | If the reg is for EL2, and EL3 is present but EL2 is not, | ||
6 | either discard, squash to res0, const, or keep unchanged. | ||
7 | 5 | ||
8 | Per rule RJFFP, mark the 4 aarch32 hypervisor access registers | ||
9 | with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address | ||
10 | translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. | ||
11 | Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ. | ||
12 | |||
13 | This will simplify cpreg registration for conditional arm features. | ||
14 | |||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
17 | Message-id: 20220506180242.216785-2-richard.henderson@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20241203203949.483774-5-richard.henderson@linaro.org | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 10 | --- |
20 | target/arm/cpregs.h | 11 +++ | 11 | fpu/softfloat-parts.c.inc | 32 ++++++++++---------------------- |
21 | target/arm/helper.c | 178 ++++++++++++++++++++++++++++++-------------- | 12 | 1 file changed, 10 insertions(+), 22 deletions(-) |
22 | 2 files changed, 133 insertions(+), 56 deletions(-) | ||
23 | 13 | ||
24 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
25 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpregs.h | 16 | --- a/fpu/softfloat-parts.c.inc |
27 | +++ b/target/arm/cpregs.h | 17 | +++ b/fpu/softfloat-parts.c.inc |
28 | @@ -XXX,XX +XXX,XX @@ enum { | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
29 | ARM_CP_SVE = 1 << 14, | 19 | FloatPartsN *c, float_status *s, |
30 | /* Flag: Do not expose in gdb sysreg xml. */ | 20 | int ab_mask, int abc_mask) |
31 | ARM_CP_NO_GDB = 1 << 15, | ||
32 | + /* | ||
33 | + * Flags: If EL3 but not EL2... | ||
34 | + * - UNDEF: discard the cpreg, | ||
35 | + * - KEEP: retain the cpreg as is, | ||
36 | + * - C_NZ: set const on the cpreg, but retain resetvalue, | ||
37 | + * - else: set const on the cpreg, zero resetvalue, aka RES0. | ||
38 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | ||
39 | + */ | ||
40 | + ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, | ||
41 | + ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, | ||
42 | + ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, | ||
43 | }; | ||
44 | |||
45 | /* | ||
46 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/helper.c | ||
49 | +++ b/target/arm/helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
51 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, | ||
52 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, | ||
53 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | ||
54 | - .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU, | ||
55 | + .access = PL2_RW, | ||
56 | + .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | ||
57 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, | ||
58 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, | ||
59 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | ||
60 | - .access = PL2_RW, .resetvalue = 0, | ||
61 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | ||
62 | .writefn = dacr_write, .raw_writefn = raw_write, | ||
63 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | ||
64 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | ||
65 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | ||
66 | - .access = PL2_RW, .resetvalue = 0, | ||
67 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | ||
68 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | ||
69 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | ||
70 | .type = ARM_CP_ALIAS, | ||
71 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
72 | .writefn = tlbimva_hyp_is_write }, | ||
73 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, | ||
74 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | ||
75 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
76 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
77 | .writefn = tlbi_aa64_alle2_write }, | ||
78 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, | ||
79 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | ||
80 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
81 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
82 | .writefn = tlbi_aa64_vae2_write }, | ||
83 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, | ||
84 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | ||
85 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
86 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
87 | .writefn = tlbi_aa64_vae2_write }, | ||
88 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | ||
89 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | ||
90 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
91 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
92 | .writefn = tlbi_aa64_alle2is_write }, | ||
93 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, | ||
94 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | ||
95 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
96 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
97 | .writefn = tlbi_aa64_vae2is_write }, | ||
98 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, | ||
99 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | ||
100 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
101 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
102 | .writefn = tlbi_aa64_vae2is_write }, | ||
103 | #ifndef CONFIG_USER_ONLY | ||
104 | /* Unlike the other EL2-related AT operations, these must | ||
105 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
106 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | ||
108 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
109 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
110 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
111 | + .writefn = ats_write64 }, | ||
112 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | ||
113 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | ||
114 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
115 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
116 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
117 | + .writefn = ats_write64 }, | ||
118 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE | ||
119 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | ||
120 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | ||
121 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
122 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | ||
123 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | ||
124 | .access = PL2_RW, .accessfn = access_tda, | ||
125 | - .type = ARM_CP_NOP }, | ||
126 | + .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, | ||
127 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
128 | * Channel but Linux may try to access this register. The 32-bit | ||
129 | * alias is DBGDCCINT. | ||
130 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
131 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
132 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, | ||
133 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | ||
134 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
135 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
136 | .writefn = tlbi_aa64_rvae2is_write }, | ||
137 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | ||
138 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | ||
139 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
140 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
141 | .writefn = tlbi_aa64_rvae2is_write }, | ||
142 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | ||
143 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | ||
144 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
145 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
146 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, | ||
147 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | ||
148 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
149 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
150 | .writefn = tlbi_aa64_rvae2is_write }, | ||
151 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | ||
152 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | ||
153 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
154 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
155 | .writefn = tlbi_aa64_rvae2is_write }, | ||
156 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | ||
157 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | ||
158 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
159 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
160 | .writefn = tlbi_aa64_rvae2_write }, | ||
161 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | ||
162 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | ||
163 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
164 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
165 | .writefn = tlbi_aa64_rvae2_write }, | ||
166 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | ||
167 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | ||
168 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
169 | .writefn = tlbi_aa64_vae1is_write }, | ||
170 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, | ||
171 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | ||
172 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
173 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
174 | .writefn = tlbi_aa64_alle2is_write }, | ||
175 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, | ||
176 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | ||
177 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
178 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
179 | .writefn = tlbi_aa64_vae2is_write }, | ||
180 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, | ||
181 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | ||
182 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
183 | .writefn = tlbi_aa64_alle1is_write }, | ||
184 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, | ||
185 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | ||
186 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
187 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
188 | .writefn = tlbi_aa64_vae2is_write }, | ||
189 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, | ||
190 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | ||
191 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
192 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
193 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
194 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
195 | - .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, | ||
196 | + .resetvalue = cpu->midr, | ||
197 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
198 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | ||
199 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
200 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
201 | .access = PL2_RW, .resetvalue = cpu->midr, | ||
202 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
203 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
204 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, | ||
205 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
206 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
207 | - .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, | ||
208 | + .resetvalue = vmpidr_def, | ||
209 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
210 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | ||
211 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
212 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
213 | - .access = PL2_RW, | ||
214 | - .resetvalue = vmpidr_def, | ||
215 | + .access = PL2_RW, .resetvalue = vmpidr_def, | ||
216 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
217 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | ||
218 | }; | ||
219 | define_arm_cp_regs(cpu, vpidr_regs); | ||
220 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
221 | int crm, int opc1, int opc2, | ||
222 | const char *name) | ||
223 | { | 21 | { |
224 | + CPUARMState *env = &cpu->env; | 22 | - int which; |
225 | uint32_t key; | 23 | bool infzero = (ab_mask == float_cmask_infzero); |
226 | ARMCPRegInfo *r2; | 24 | bool have_snan = (abc_mask & float_cmask_snan); |
227 | bool is64 = r->type & ARM_CP_64BIT; | 25 | + FloatPartsN *ret; |
228 | bool ns = secstate & ARM_CP_SECSTATE_NS; | 26 | |
229 | int cp = r->cp; | 27 | if (unlikely(have_snan)) { |
230 | - bool isbanked; | 28 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
231 | size_t name_len; | 29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
232 | + bool make_const; | 30 | default: |
233 | 31 | g_assert_not_reached(); | |
234 | switch (state) { | 32 | } |
235 | case ARM_CP_STATE_AA32: | 33 | - which = 2; |
236 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 34 | + ret = c; |
35 | } else { | ||
36 | - FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
37 | + FloatPartsN *val[3] = { a, b, c }; | ||
38 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
39 | |||
40 | assert(rule != float_3nan_prop_none); | ||
41 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
42 | /* We have at least one SNaN input and should prefer it */ | ||
43 | do { | ||
44 | - which = rule & R_3NAN_1ST_MASK; | ||
45 | + ret = val[rule & R_3NAN_1ST_MASK]; | ||
46 | rule >>= R_3NAN_1ST_LENGTH; | ||
47 | - } while (!is_snan(cls[which])); | ||
48 | + } while (!is_snan(ret->cls)); | ||
49 | } else { | ||
50 | do { | ||
51 | - which = rule & R_3NAN_1ST_MASK; | ||
52 | + ret = val[rule & R_3NAN_1ST_MASK]; | ||
53 | rule >>= R_3NAN_1ST_LENGTH; | ||
54 | - } while (!is_nan(cls[which])); | ||
55 | + } while (!is_nan(ret->cls)); | ||
237 | } | 56 | } |
238 | } | 57 | } |
239 | 58 | ||
240 | + /* | 59 | - switch (which) { |
241 | + * Eliminate registers that are not present because the EL is missing. | 60 | - case 0: |
242 | + * Doing this here makes it easier to put all registers for a given | 61 | - break; |
243 | + * feature into the same ARMCPRegInfo array and define them all at once. | 62 | - case 1: |
244 | + */ | 63 | - a = b; |
245 | + make_const = false; | 64 | - break; |
246 | + if (arm_feature(env, ARM_FEATURE_EL3)) { | 65 | - case 2: |
247 | + /* | 66 | - a = c; |
248 | + * An EL2 register without EL2 but with EL3 is (usually) RES0. | 67 | - break; |
249 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | 68 | - default: |
250 | + */ | 69 | - g_assert_not_reached(); |
251 | + int min_el = ctz32(r->access) / 2; | 70 | + if (is_snan(ret->cls)) { |
252 | + if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | 71 | + parts_silence_nan(ret, s); |
253 | + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | ||
254 | + return; | ||
255 | + } | ||
256 | + make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | ||
257 | + } | ||
258 | + } else { | ||
259 | + CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | ||
260 | + ? PL2_RW : PL1_RW); | ||
261 | + if ((r->access & max_el) == 0) { | ||
262 | + return; | ||
263 | + } | ||
264 | + } | ||
265 | + | ||
266 | /* Combine cpreg and name into one allocation. */ | ||
267 | name_len = strlen(name) + 1; | ||
268 | r2 = g_malloc(sizeof(*r2) + name_len); | ||
269 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
270 | r2->opaque = opaque; | ||
271 | } | 72 | } |
272 | 73 | - if (is_snan(a->cls)) { | |
273 | - isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | 74 | - parts_silence_nan(a, s); |
274 | - if (isbanked) { | ||
275 | + if (make_const) { | ||
276 | + /* This should not have been a very special register to begin. */ | ||
277 | + int old_special = r2->type & ARM_CP_SPECIAL_MASK; | ||
278 | + assert(old_special == 0 || old_special == ARM_CP_NOP); | ||
279 | /* | ||
280 | - * Register is banked (using both entries in array). | ||
281 | - * Overwriting fieldoffset as the array is only used to define | ||
282 | - * banked registers but later only fieldoffset is used. | ||
283 | + * Set the special function to CONST, retaining the other flags. | ||
284 | + * This is important for e.g. ARM_CP_SVE so that we still | ||
285 | + * take the SVE trap if CPTR_EL3.EZ == 0. | ||
286 | */ | ||
287 | - r2->fieldoffset = r->bank_fieldoffsets[ns]; | ||
288 | - } | 75 | - } |
289 | + r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; | 76 | - return a; |
290 | + /* | 77 | + return ret; |
291 | + * Usually, these registers become RES0, but there are a few | 78 | |
292 | + * special cases like VPIDR_EL2 which have a constant non-zero | 79 | default_nan: |
293 | + * value with writes ignored. | 80 | parts_default_nan(a, s); |
294 | + */ | ||
295 | + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | ||
296 | + r2->resetvalue = 0; | ||
297 | + } | ||
298 | + /* | ||
299 | + * ARM_CP_CONST has precedence, so removing the callbacks and | ||
300 | + * offsets are not strictly necessary, but it is potentially | ||
301 | + * less confusing to debug later. | ||
302 | + */ | ||
303 | + r2->readfn = NULL; | ||
304 | + r2->writefn = NULL; | ||
305 | + r2->raw_readfn = NULL; | ||
306 | + r2->raw_writefn = NULL; | ||
307 | + r2->resetfn = NULL; | ||
308 | + r2->fieldoffset = 0; | ||
309 | + r2->bank_fieldoffsets[0] = 0; | ||
310 | + r2->bank_fieldoffsets[1] = 0; | ||
311 | + } else { | ||
312 | + bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | ||
313 | |||
314 | - if (state == ARM_CP_STATE_AA32) { | ||
315 | if (isbanked) { | ||
316 | /* | ||
317 | - * If the register is banked then we don't need to migrate or | ||
318 | - * reset the 32-bit instance in certain cases: | ||
319 | - * | ||
320 | - * 1) If the register has both 32-bit and 64-bit instances then we | ||
321 | - * can count on the 64-bit instance taking care of the | ||
322 | - * non-secure bank. | ||
323 | - * 2) If ARMv8 is enabled then we can count on a 64-bit version | ||
324 | - * taking care of the secure bank. This requires that separate | ||
325 | - * 32 and 64-bit definitions are provided. | ||
326 | + * Register is banked (using both entries in array). | ||
327 | + * Overwriting fieldoffset as the array is only used to define | ||
328 | + * banked registers but later only fieldoffset is used. | ||
329 | */ | ||
330 | - if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
331 | - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | ||
332 | + r2->fieldoffset = r->bank_fieldoffsets[ns]; | ||
333 | + } | ||
334 | + if (state == ARM_CP_STATE_AA32) { | ||
335 | + if (isbanked) { | ||
336 | + /* | ||
337 | + * If the register is banked then we don't need to migrate or | ||
338 | + * reset the 32-bit instance in certain cases: | ||
339 | + * | ||
340 | + * 1) If the register has both 32-bit and 64-bit instances | ||
341 | + * then we can count on the 64-bit instance taking care | ||
342 | + * of the non-secure bank. | ||
343 | + * 2) If ARMv8 is enabled then we can count on a 64-bit | ||
344 | + * version taking care of the secure bank. This requires | ||
345 | + * that separate 32 and 64-bit definitions are provided. | ||
346 | + */ | ||
347 | + if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
348 | + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | ||
349 | + r2->type |= ARM_CP_ALIAS; | ||
350 | + } | ||
351 | + } else if ((secstate != r->secure) && !ns) { | ||
352 | + /* | ||
353 | + * The register is not banked so we only want to allow | ||
354 | + * migration of the non-secure instance. | ||
355 | + */ | ||
356 | r2->type |= ARM_CP_ALIAS; | ||
357 | } | ||
358 | - } else if ((secstate != r->secure) && !ns) { | ||
359 | - /* | ||
360 | - * The register is not banked so we only want to allow migration | ||
361 | - * of the non-secure instance. | ||
362 | - */ | ||
363 | - r2->type |= ARM_CP_ALIAS; | ||
364 | - } | ||
365 | |||
366 | - if (HOST_BIG_ENDIAN && | ||
367 | - r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
368 | - r2->fieldoffset += sizeof(uint32_t); | ||
369 | + if (HOST_BIG_ENDIAN && | ||
370 | + r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
371 | + r2->fieldoffset += sizeof(uint32_t); | ||
372 | + } | ||
373 | } | ||
374 | } | ||
375 | |||
376 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
377 | * multiple times. Special registers (ie NOP/WFI) are | ||
378 | * never migratable and not even raw-accessible. | ||
379 | */ | ||
380 | - if (r->type & ARM_CP_SPECIAL_MASK) { | ||
381 | + if (r2->type & ARM_CP_SPECIAL_MASK) { | ||
382 | r2->type |= ARM_CP_NO_RAW; | ||
383 | } | ||
384 | if (((r->crm == CP_ANY) && crm != 0) || | ||
385 | -- | 81 | -- |
386 | 2.25.1 | 82 | 2.34.1 |
83 | |||
84 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | While all indices into val[] should be in [0-2], the mask |
4 | applied is two bits. To help static analysis see there is | ||
5 | no possibility of read beyond the end of the array, pad the | ||
6 | array to 4 entries, with the final being (implicitly) NULL. | ||
7 | |||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20220506180242.216785-18-richard.henderson@linaro.org | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Message-id: 20241203203949.483774-6-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | docs/system/arm/emulation.rst | 1 + | 13 | fpu/softfloat-parts.c.inc | 2 +- |
9 | target/arm/cpu64.c | 1 + | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | target/arm/cpu_tcg.c | 1 + | ||
11 | 3 files changed, 3 insertions(+) | ||
12 | 15 | ||
13 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/docs/system/arm/emulation.rst | 18 | --- a/fpu/softfloat-parts.c.inc |
16 | +++ b/docs/system/arm/emulation.rst | 19 | +++ b/fpu/softfloat-parts.c.inc |
17 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
18 | - FEAT_PMULL (PMULL, PMULL2 instructions) | 21 | } |
19 | - FEAT_PMUv3p1 (PMU Extensions v3.1) | 22 | ret = c; |
20 | - FEAT_PMUv3p4 (PMU Extensions v3.4) | 23 | } else { |
21 | +- FEAT_RAS (Reliability, availability, and serviceability) | 24 | - FloatPartsN *val[3] = { a, b, c }; |
22 | - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) | 25 | + FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c }; |
23 | - FEAT_RNG (Random number generator) | 26 | Float3NaNPropRule rule = s->float_3nan_prop_rule; |
24 | - FEAT_SB (Speculation Barrier) | 27 | |
25 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 28 | assert(rule != float_3nan_prop_none); |
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/cpu64.c | ||
28 | +++ b/target/arm/cpu64.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
30 | t = cpu->isar.id_aa64pfr0; | ||
31 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | ||
32 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | ||
33 | + t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ | ||
34 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
35 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
36 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
37 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/cpu_tcg.c | ||
40 | +++ b/target/arm/cpu_tcg.c | ||
41 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
42 | |||
43 | t = cpu->isar.id_pfr0; | ||
44 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
45 | + t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ | ||
46 | cpu->isar.id_pfr0 = t; | ||
47 | |||
48 | t = cpu->isar.id_pfr2; | ||
49 | -- | 29 | -- |
50 | 2.25.1 | 30 | 2.34.1 |
31 | |||
32 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable the n1 for virt and sbsa board use. | 3 | This function is part of the public interface and |
4 | is not "specialized" to any target in any way. | ||
4 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Message-id: 20241203203949.483774-7-richard.henderson@linaro.org |
7 | Message-id: 20220506180242.216785-25-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | docs/system/arm/virt.rst | 1 + | 11 | fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++ |
11 | hw/arm/sbsa-ref.c | 1 + | 12 | fpu/softfloat-specialize.c.inc | 52 ---------------------------------- |
12 | hw/arm/virt.c | 1 + | 13 | 2 files changed, 52 insertions(+), 52 deletions(-) |
13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 69 insertions(+) | ||
15 | 14 | ||
16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/virt.rst | 17 | --- a/fpu/softfloat.c |
19 | +++ b/docs/system/arm/virt.rst | 18 | +++ b/fpu/softfloat.c |
20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
21 | - ``cortex-a76`` (64-bit) | 20 | *zExpPtr = 1 - shiftCount; |
22 | - ``a64fx`` (64-bit) | ||
23 | - ``host`` (with KVM only) | ||
24 | +- ``neoverse-n1`` (64-bit) | ||
25 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | ||
26 | |||
27 | Note that the default is ``cortex-a15``, so for an AArch64 guest you must | ||
28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/hw/arm/sbsa-ref.c | ||
31 | +++ b/hw/arm/sbsa-ref.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = { | ||
33 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
34 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
35 | ARM_CPU_TYPE_NAME("cortex-a76"), | ||
36 | + ARM_CPU_TYPE_NAME("neoverse-n1"), | ||
37 | ARM_CPU_TYPE_NAME("max"), | ||
38 | }; | ||
39 | |||
40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/virt.c | ||
43 | +++ b/hw/arm/virt.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | ||
45 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
46 | ARM_CPU_TYPE_NAME("cortex-a76"), | ||
47 | ARM_CPU_TYPE_NAME("a64fx"), | ||
48 | + ARM_CPU_TYPE_NAME("neoverse-n1"), | ||
49 | ARM_CPU_TYPE_NAME("host"), | ||
50 | ARM_CPU_TYPE_NAME("max"), | ||
51 | }; | ||
52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/cpu64.c | ||
55 | +++ b/target/arm/cpu64.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj) | ||
57 | cpu->isar.mvfr2 = 0x00000043; | ||
58 | } | 21 | } |
59 | 22 | ||
60 | +static void aarch64_neoverse_n1_initfn(Object *obj) | 23 | +/*---------------------------------------------------------------------------- |
24 | +| Takes two extended double-precision floating-point values `a' and `b', one | ||
25 | +| of which is a NaN, and returns the appropriate NaN result. If either `a' or | ||
26 | +| `b' is a signaling NaN, the invalid exception is raised. | ||
27 | +*----------------------------------------------------------------------------*/ | ||
28 | + | ||
29 | +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) | ||
61 | +{ | 30 | +{ |
62 | + ARMCPU *cpu = ARM_CPU(obj); | 31 | + bool aIsLargerSignificand; |
32 | + FloatClass a_cls, b_cls; | ||
63 | + | 33 | + |
64 | + cpu->dtb_compatible = "arm,neoverse-n1"; | 34 | + /* This is not complete, but is good enough for pickNaN. */ |
65 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 35 | + a_cls = (!floatx80_is_any_nan(a) |
66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | 36 | + ? float_class_normal |
67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | 37 | + : floatx80_is_signaling_nan(a, status) |
68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | 38 | + ? float_class_snan |
69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | 39 | + : float_class_qnan); |
70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | 40 | + b_cls = (!floatx80_is_any_nan(b) |
71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | 41 | + ? float_class_normal |
72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | 42 | + : floatx80_is_signaling_nan(b, status) |
43 | + ? float_class_snan | ||
44 | + : float_class_qnan); | ||
73 | + | 45 | + |
74 | + /* Ordered by B2.4 AArch64 registers by functional group */ | 46 | + if (is_snan(a_cls) || is_snan(b_cls)) { |
75 | + cpu->clidr = 0x82000023; | 47 | + float_raise(float_flag_invalid, status); |
76 | + cpu->ctr = 0x8444c004; | 48 | + } |
77 | + cpu->dcz_blocksize = 4; | ||
78 | + cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; | ||
79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | ||
80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | ||
81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; | ||
82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | ||
83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | ||
84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | ||
85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; | ||
86 | + cpu->id_afr0 = 0x00000000; | ||
87 | + cpu->isar.id_dfr0 = 0x04010088; | ||
88 | + cpu->isar.id_isar0 = 0x02101110; | ||
89 | + cpu->isar.id_isar1 = 0x13112111; | ||
90 | + cpu->isar.id_isar2 = 0x21232042; | ||
91 | + cpu->isar.id_isar3 = 0x01112131; | ||
92 | + cpu->isar.id_isar4 = 0x00010142; | ||
93 | + cpu->isar.id_isar5 = 0x01011121; | ||
94 | + cpu->isar.id_isar6 = 0x00000010; | ||
95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
103 | + cpu->midr = 0x414fd0c1; /* r4p1 */ | ||
104 | + cpu->revidr = 0; | ||
105 | + | 49 | + |
106 | + /* From B2.23 CCSIDR_EL1 */ | 50 | + if (status->default_nan_mode) { |
107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | 51 | + return floatx80_default_nan(status); |
108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | 52 | + } |
109 | + cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ | ||
110 | + | 53 | + |
111 | + /* From B2.98 SCTLR_EL3 */ | 54 | + if (a.low < b.low) { |
112 | + cpu->reset_sctlr = 0x30c50838; | 55 | + aIsLargerSignificand = 0; |
56 | + } else if (b.low < a.low) { | ||
57 | + aIsLargerSignificand = 1; | ||
58 | + } else { | ||
59 | + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
60 | + } | ||
113 | + | 61 | + |
114 | + /* From B4.23 ICH_VTR_EL2 */ | 62 | + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
115 | + cpu->gic_num_lrs = 4; | 63 | + if (is_snan(b_cls)) { |
116 | + cpu->gic_vpribits = 5; | 64 | + return floatx80_silence_nan(b, status); |
117 | + cpu->gic_vprebits = 5; | 65 | + } |
118 | + | 66 | + return b; |
119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | 67 | + } else { |
120 | + cpu->isar.mvfr0 = 0x10110222; | 68 | + if (is_snan(a_cls)) { |
121 | + cpu->isar.mvfr1 = 0x13211111; | 69 | + return floatx80_silence_nan(a, status); |
122 | + cpu->isar.mvfr2 = 0x00000043; | 70 | + } |
71 | + return a; | ||
72 | + } | ||
123 | +} | 73 | +} |
124 | + | 74 | + |
125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | 75 | /*---------------------------------------------------------------------------- |
126 | { | 76 | | Takes an abstract floating-point value having sign `zSign', exponent `zExp', |
127 | /* | 77 | | and extended significand formed by the concatenation of `zSig0' and `zSig1', |
128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | 78 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
129 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | 79 | index XXXXXXX..XXXXXXX 100644 |
130 | { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | 80 | --- a/fpu/softfloat-specialize.c.inc |
131 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | 81 | +++ b/fpu/softfloat-specialize.c.inc |
132 | + { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, | 82 | @@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) |
133 | { .name = "max", .initfn = aarch64_max_initfn }, | 83 | return a; |
134 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | 84 | } |
135 | { .name = "host", .initfn = aarch64_host_initfn }, | 85 | |
86 | -/*---------------------------------------------------------------------------- | ||
87 | -| Takes two extended double-precision floating-point values `a' and `b', one | ||
88 | -| of which is a NaN, and returns the appropriate NaN result. If either `a' or | ||
89 | -| `b' is a signaling NaN, the invalid exception is raised. | ||
90 | -*----------------------------------------------------------------------------*/ | ||
91 | - | ||
92 | -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) | ||
93 | -{ | ||
94 | - bool aIsLargerSignificand; | ||
95 | - FloatClass a_cls, b_cls; | ||
96 | - | ||
97 | - /* This is not complete, but is good enough for pickNaN. */ | ||
98 | - a_cls = (!floatx80_is_any_nan(a) | ||
99 | - ? float_class_normal | ||
100 | - : floatx80_is_signaling_nan(a, status) | ||
101 | - ? float_class_snan | ||
102 | - : float_class_qnan); | ||
103 | - b_cls = (!floatx80_is_any_nan(b) | ||
104 | - ? float_class_normal | ||
105 | - : floatx80_is_signaling_nan(b, status) | ||
106 | - ? float_class_snan | ||
107 | - : float_class_qnan); | ||
108 | - | ||
109 | - if (is_snan(a_cls) || is_snan(b_cls)) { | ||
110 | - float_raise(float_flag_invalid, status); | ||
111 | - } | ||
112 | - | ||
113 | - if (status->default_nan_mode) { | ||
114 | - return floatx80_default_nan(status); | ||
115 | - } | ||
116 | - | ||
117 | - if (a.low < b.low) { | ||
118 | - aIsLargerSignificand = 0; | ||
119 | - } else if (b.low < a.low) { | ||
120 | - aIsLargerSignificand = 1; | ||
121 | - } else { | ||
122 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
123 | - } | ||
124 | - | ||
125 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | ||
126 | - if (is_snan(b_cls)) { | ||
127 | - return floatx80_silence_nan(b, status); | ||
128 | - } | ||
129 | - return b; | ||
130 | - } else { | ||
131 | - if (is_snan(a_cls)) { | ||
132 | - return floatx80_silence_nan(a, status); | ||
133 | - } | ||
134 | - return a; | ||
135 | - } | ||
136 | -} | ||
137 | - | ||
138 | /*---------------------------------------------------------------------------- | ||
139 | | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | ||
140 | | NaN; otherwise returns 0. | ||
136 | -- | 141 | -- |
137 | 2.25.1 | 142 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable the a76 for virt and sbsa board use. | 3 | Unpacking and repacking the parts may be slightly more work |
4 | than we did before, but we get to reuse more code. For a | ||
5 | code path handling exceptional values, this is an improvement. | ||
4 | 6 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241203203949.483774-8-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220506180242.216785-24-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | 11 | --- |
10 | docs/system/arm/virt.rst | 1 + | 12 | fpu/softfloat.c | 43 +++++-------------------------------------- |
11 | hw/arm/sbsa-ref.c | 1 + | 13 | 1 file changed, 5 insertions(+), 38 deletions(-) |
12 | hw/arm/virt.c | 1 + | ||
13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 69 insertions(+) | ||
15 | 14 | ||
16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/virt.rst | 17 | --- a/fpu/softfloat.c |
19 | +++ b/docs/system/arm/virt.rst | 18 | +++ b/fpu/softfloat.c |
20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
21 | - ``cortex-a53`` (64-bit) | 20 | |
22 | - ``cortex-a57`` (64-bit) | 21 | floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
23 | - ``cortex-a72`` (64-bit) | 22 | { |
24 | +- ``cortex-a76`` (64-bit) | 23 | - bool aIsLargerSignificand; |
25 | - ``a64fx`` (64-bit) | 24 | - FloatClass a_cls, b_cls; |
26 | - ``host`` (with KVM only) | 25 | + FloatParts128 pa, pb, *pr; |
27 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | 26 | |
28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | 27 | - /* This is not complete, but is good enough for pickNaN. */ |
29 | index XXXXXXX..XXXXXXX 100644 | 28 | - a_cls = (!floatx80_is_any_nan(a) |
30 | --- a/hw/arm/sbsa-ref.c | 29 | - ? float_class_normal |
31 | +++ b/hw/arm/sbsa-ref.c | 30 | - : floatx80_is_signaling_nan(a, status) |
32 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { | 31 | - ? float_class_snan |
33 | static const char * const valid_cpus[] = { | 32 | - : float_class_qnan); |
34 | ARM_CPU_TYPE_NAME("cortex-a57"), | 33 | - b_cls = (!floatx80_is_any_nan(b) |
35 | ARM_CPU_TYPE_NAME("cortex-a72"), | 34 | - ? float_class_normal |
36 | + ARM_CPU_TYPE_NAME("cortex-a76"), | 35 | - : floatx80_is_signaling_nan(b, status) |
37 | ARM_CPU_TYPE_NAME("max"), | 36 | - ? float_class_snan |
38 | }; | 37 | - : float_class_qnan); |
39 | 38 | - | |
40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 39 | - if (is_snan(a_cls) || is_snan(b_cls)) { |
41 | index XXXXXXX..XXXXXXX 100644 | 40 | - float_raise(float_flag_invalid, status); |
42 | --- a/hw/arm/virt.c | 41 | - } |
43 | +++ b/hw/arm/virt.c | 42 | - |
44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | 43 | - if (status->default_nan_mode) { |
45 | ARM_CPU_TYPE_NAME("cortex-a53"), | 44 | + if (!floatx80_unpack_canonical(&pa, a, status) || |
46 | ARM_CPU_TYPE_NAME("cortex-a57"), | 45 | + !floatx80_unpack_canonical(&pb, b, status)) { |
47 | ARM_CPU_TYPE_NAME("cortex-a72"), | 46 | return floatx80_default_nan(status); |
48 | + ARM_CPU_TYPE_NAME("cortex-a76"), | 47 | } |
49 | ARM_CPU_TYPE_NAME("a64fx"), | 48 | |
50 | ARM_CPU_TYPE_NAME("host"), | 49 | - if (a.low < b.low) { |
51 | ARM_CPU_TYPE_NAME("max"), | 50 | - aIsLargerSignificand = 0; |
52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 51 | - } else if (b.low < a.low) { |
53 | index XXXXXXX..XXXXXXX 100644 | 52 | - aIsLargerSignificand = 1; |
54 | --- a/target/arm/cpu64.c | 53 | - } else { |
55 | +++ b/target/arm/cpu64.c | 54 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; |
56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | 55 | - } |
57 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | 56 | - |
57 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | ||
58 | - if (is_snan(b_cls)) { | ||
59 | - return floatx80_silence_nan(b, status); | ||
60 | - } | ||
61 | - return b; | ||
62 | - } else { | ||
63 | - if (is_snan(a_cls)) { | ||
64 | - return floatx80_silence_nan(a, status); | ||
65 | - } | ||
66 | - return a; | ||
67 | - } | ||
68 | + pr = parts_pick_nan(&pa, &pb, status); | ||
69 | + return floatx80_round_pack_canonical(pr, status); | ||
58 | } | 70 | } |
59 | 71 | ||
60 | +static void aarch64_a76_initfn(Object *obj) | 72 | /*---------------------------------------------------------------------------- |
61 | +{ | ||
62 | + ARMCPU *cpu = ARM_CPU(obj); | ||
63 | + | ||
64 | + cpu->dtb_compatible = "arm,cortex-a76"; | ||
65 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
73 | + | ||
74 | + /* Ordered by B2.4 AArch64 registers by functional group */ | ||
75 | + cpu->clidr = 0x82000023; | ||
76 | + cpu->ctr = 0x8444C004; | ||
77 | + cpu->dcz_blocksize = 4; | ||
78 | + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; | ||
79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | ||
80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | ||
81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; | ||
82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | ||
83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | ||
84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | ||
85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; | ||
86 | + cpu->id_afr0 = 0x00000000; | ||
87 | + cpu->isar.id_dfr0 = 0x04010088; | ||
88 | + cpu->isar.id_isar0 = 0x02101110; | ||
89 | + cpu->isar.id_isar1 = 0x13112111; | ||
90 | + cpu->isar.id_isar2 = 0x21232042; | ||
91 | + cpu->isar.id_isar3 = 0x01112131; | ||
92 | + cpu->isar.id_isar4 = 0x00010142; | ||
93 | + cpu->isar.id_isar5 = 0x01011121; | ||
94 | + cpu->isar.id_isar6 = 0x00000010; | ||
95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
103 | + cpu->midr = 0x414fd0b1; /* r4p1 */ | ||
104 | + cpu->revidr = 0; | ||
105 | + | ||
106 | + /* From B2.18 CCSIDR_EL1 */ | ||
107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | ||
108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | ||
109 | + cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ | ||
110 | + | ||
111 | + /* From B2.93 SCTLR_EL3 */ | ||
112 | + cpu->reset_sctlr = 0x30c50838; | ||
113 | + | ||
114 | + /* From B4.23 ICH_VTR_EL2 */ | ||
115 | + cpu->gic_num_lrs = 4; | ||
116 | + cpu->gic_vpribits = 5; | ||
117 | + cpu->gic_vprebits = 5; | ||
118 | + | ||
119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | ||
120 | + cpu->isar.mvfr0 = 0x10110222; | ||
121 | + cpu->isar.mvfr1 = 0x13211111; | ||
122 | + cpu->isar.mvfr2 = 0x00000043; | ||
123 | +} | ||
124 | + | ||
125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | ||
126 | { | ||
127 | /* | ||
128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | ||
129 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, | ||
130 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, | ||
131 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | ||
132 | + { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | ||
133 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | ||
134 | { .name = "max", .initfn = aarch64_max_initfn }, | ||
135 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | ||
136 | -- | 73 | -- |
137 | 2.25.1 | 74 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Drop zcr_no_el2_reginfo and merge the 3 registers into one array, | 3 | Inline pickNaN into its only caller. This makes one assert |
4 | now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped | 4 | redundant with the immediately preceding IF. |
5 | while registering. | 5 | |
6 | |||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-4-richard.henderson@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20241203203949.483774-9-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/helper.c | 55 ++++++++++++++------------------------------- | 11 | fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++---- |
13 | 1 file changed, 17 insertions(+), 38 deletions(-) | 12 | fpu/softfloat-specialize.c.inc | 96 ---------------------------------- |
14 | 13 | 2 files changed, 73 insertions(+), 105 deletions(-) | |
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | |
15 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 17 | --- a/fpu/softfloat-parts.c.inc |
18 | +++ b/target/arm/helper.c | 18 | +++ b/fpu/softfloat-parts.c.inc |
19 | @@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 19 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) |
20 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
21 | float_status *s) | ||
22 | { | ||
23 | + int cmp, which; | ||
24 | + | ||
25 | if (is_snan(a->cls) || is_snan(b->cls)) { | ||
26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
27 | } | ||
28 | |||
29 | if (s->default_nan_mode) { | ||
30 | parts_default_nan(a, s); | ||
31 | - } else { | ||
32 | - int cmp = frac_cmp(a, b); | ||
33 | - if (cmp == 0) { | ||
34 | - cmp = a->sign < b->sign; | ||
35 | - } | ||
36 | + return a; | ||
37 | + } | ||
38 | |||
39 | - if (pickNaN(a->cls, b->cls, cmp > 0, s)) { | ||
40 | - a = b; | ||
41 | - } | ||
42 | + cmp = frac_cmp(a, b); | ||
43 | + if (cmp == 0) { | ||
44 | + cmp = a->sign < b->sign; | ||
45 | + } | ||
46 | + | ||
47 | + switch (s->float_2nan_prop_rule) { | ||
48 | + case float_2nan_prop_s_ab: | ||
49 | if (is_snan(a->cls)) { | ||
50 | - parts_silence_nan(a, s); | ||
51 | + which = 0; | ||
52 | + } else if (is_snan(b->cls)) { | ||
53 | + which = 1; | ||
54 | + } else if (is_qnan(a->cls)) { | ||
55 | + which = 0; | ||
56 | + } else { | ||
57 | + which = 1; | ||
58 | } | ||
59 | + break; | ||
60 | + case float_2nan_prop_s_ba: | ||
61 | + if (is_snan(b->cls)) { | ||
62 | + which = 1; | ||
63 | + } else if (is_snan(a->cls)) { | ||
64 | + which = 0; | ||
65 | + } else if (is_qnan(b->cls)) { | ||
66 | + which = 1; | ||
67 | + } else { | ||
68 | + which = 0; | ||
69 | + } | ||
70 | + break; | ||
71 | + case float_2nan_prop_ab: | ||
72 | + which = is_nan(a->cls) ? 0 : 1; | ||
73 | + break; | ||
74 | + case float_2nan_prop_ba: | ||
75 | + which = is_nan(b->cls) ? 1 : 0; | ||
76 | + break; | ||
77 | + case float_2nan_prop_x87: | ||
78 | + /* | ||
79 | + * This implements x87 NaN propagation rules: | ||
80 | + * SNaN + QNaN => return the QNaN | ||
81 | + * two SNaNs => return the one with the larger significand, silenced | ||
82 | + * two QNaNs => return the one with the larger significand | ||
83 | + * SNaN and a non-NaN => return the SNaN, silenced | ||
84 | + * QNaN and a non-NaN => return the QNaN | ||
85 | + * | ||
86 | + * If we get down to comparing significands and they are the same, | ||
87 | + * return the NaN with the positive sign bit (if any). | ||
88 | + */ | ||
89 | + if (is_snan(a->cls)) { | ||
90 | + if (is_snan(b->cls)) { | ||
91 | + which = cmp > 0 ? 0 : 1; | ||
92 | + } else { | ||
93 | + which = is_qnan(b->cls) ? 1 : 0; | ||
94 | + } | ||
95 | + } else if (is_qnan(a->cls)) { | ||
96 | + if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
97 | + which = 0; | ||
98 | + } else { | ||
99 | + which = cmp > 0 ? 0 : 1; | ||
100 | + } | ||
101 | + } else { | ||
102 | + which = 1; | ||
103 | + } | ||
104 | + break; | ||
105 | + default: | ||
106 | + g_assert_not_reached(); | ||
107 | + } | ||
108 | + | ||
109 | + if (which) { | ||
110 | + a = b; | ||
111 | + } | ||
112 | + if (is_snan(a->cls)) { | ||
113 | + parts_silence_nan(a, s); | ||
114 | } | ||
115 | return a; | ||
116 | } | ||
117 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/fpu/softfloat-specialize.c.inc | ||
120 | +++ b/fpu/softfloat-specialize.c.inc | ||
121 | @@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status) | ||
20 | } | 122 | } |
21 | } | 123 | } |
22 | 124 | ||
23 | -static const ARMCPRegInfo zcr_el1_reginfo = { | 125 | -/*---------------------------------------------------------------------------- |
24 | - .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | 126 | -| Select which NaN to propagate for a two-input operation. |
25 | - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | 127 | -| IEEE754 doesn't specify all the details of this, so the |
26 | - .access = PL1_RW, .type = ARM_CP_SVE, | 128 | -| algorithm is target-specific. |
27 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | 129 | -| The routine is passed various bits of information about the |
28 | - .writefn = zcr_write, .raw_writefn = raw_write | 130 | -| two NaNs and should return 0 to select NaN a and 1 for NaN b. |
29 | -}; | 131 | -| Note that signalling NaNs are always squashed to quiet NaNs |
132 | -| by the caller, by calling floatXX_silence_nan() before | ||
133 | -| returning them. | ||
134 | -| | ||
135 | -| aIsLargerSignificand is only valid if both a and b are NaNs | ||
136 | -| of some kind, and is true if a has the larger significand, | ||
137 | -| or if both a and b have the same significand but a is | ||
138 | -| positive but b is negative. It is only needed for the x87 | ||
139 | -| tie-break rule. | ||
140 | -*----------------------------------------------------------------------------*/ | ||
30 | - | 141 | - |
31 | -static const ARMCPRegInfo zcr_el2_reginfo = { | 142 | -static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
32 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | 143 | - bool aIsLargerSignificand, float_status *status) |
33 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | 144 | -{ |
34 | - .access = PL2_RW, .type = ARM_CP_SVE, | 145 | - /* |
35 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | 146 | - * We guarantee not to require the target to tell us how to |
36 | - .writefn = zcr_write, .raw_writefn = raw_write | 147 | - * pick a NaN if we're always returning the default NaN. |
37 | -}; | 148 | - * But if we're not in default-NaN mode then the target must |
149 | - * specify via set_float_2nan_prop_rule(). | ||
150 | - */ | ||
151 | - assert(!status->default_nan_mode); | ||
38 | - | 152 | - |
39 | -static const ARMCPRegInfo zcr_no_el2_reginfo = { | 153 | - switch (status->float_2nan_prop_rule) { |
40 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | 154 | - case float_2nan_prop_s_ab: |
41 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | 155 | - if (is_snan(a_cls)) { |
42 | - .access = PL2_RW, .type = ARM_CP_SVE, | 156 | - return 0; |
43 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore | 157 | - } else if (is_snan(b_cls)) { |
44 | -}; | 158 | - return 1; |
159 | - } else if (is_qnan(a_cls)) { | ||
160 | - return 0; | ||
161 | - } else { | ||
162 | - return 1; | ||
163 | - } | ||
164 | - break; | ||
165 | - case float_2nan_prop_s_ba: | ||
166 | - if (is_snan(b_cls)) { | ||
167 | - return 1; | ||
168 | - } else if (is_snan(a_cls)) { | ||
169 | - return 0; | ||
170 | - } else if (is_qnan(b_cls)) { | ||
171 | - return 1; | ||
172 | - } else { | ||
173 | - return 0; | ||
174 | - } | ||
175 | - break; | ||
176 | - case float_2nan_prop_ab: | ||
177 | - if (is_nan(a_cls)) { | ||
178 | - return 0; | ||
179 | - } else { | ||
180 | - return 1; | ||
181 | - } | ||
182 | - break; | ||
183 | - case float_2nan_prop_ba: | ||
184 | - if (is_nan(b_cls)) { | ||
185 | - return 1; | ||
186 | - } else { | ||
187 | - return 0; | ||
188 | - } | ||
189 | - break; | ||
190 | - case float_2nan_prop_x87: | ||
191 | - /* | ||
192 | - * This implements x87 NaN propagation rules: | ||
193 | - * SNaN + QNaN => return the QNaN | ||
194 | - * two SNaNs => return the one with the larger significand, silenced | ||
195 | - * two QNaNs => return the one with the larger significand | ||
196 | - * SNaN and a non-NaN => return the SNaN, silenced | ||
197 | - * QNaN and a non-NaN => return the QNaN | ||
198 | - * | ||
199 | - * If we get down to comparing significands and they are the same, | ||
200 | - * return the NaN with the positive sign bit (if any). | ||
201 | - */ | ||
202 | - if (is_snan(a_cls)) { | ||
203 | - if (is_snan(b_cls)) { | ||
204 | - return aIsLargerSignificand ? 0 : 1; | ||
205 | - } | ||
206 | - return is_qnan(b_cls) ? 1 : 0; | ||
207 | - } else if (is_qnan(a_cls)) { | ||
208 | - if (is_snan(b_cls) || !is_qnan(b_cls)) { | ||
209 | - return 0; | ||
210 | - } else { | ||
211 | - return aIsLargerSignificand ? 0 : 1; | ||
212 | - } | ||
213 | - } else { | ||
214 | - return 1; | ||
215 | - } | ||
216 | - default: | ||
217 | - g_assert_not_reached(); | ||
218 | - } | ||
219 | -} | ||
45 | - | 220 | - |
46 | -static const ARMCPRegInfo zcr_el3_reginfo = { | 221 | /*---------------------------------------------------------------------------- |
47 | - .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | 222 | | Returns 1 if the double-precision floating-point value `a' is a quiet |
48 | - .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | 223 | | NaN; otherwise returns 0. |
49 | - .access = PL3_RW, .type = ARM_CP_SVE, | ||
50 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
51 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
52 | +static const ARMCPRegInfo zcr_reginfo[] = { | ||
53 | + { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | ||
54 | + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | ||
55 | + .access = PL1_RW, .type = ARM_CP_SVE, | ||
56 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | ||
57 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
58 | + { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
59 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
60 | + .access = PL2_RW, .type = ARM_CP_SVE, | ||
61 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | ||
62 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
63 | + { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
64 | + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
65 | + .access = PL3_RW, .type = ARM_CP_SVE, | ||
66 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
67 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
68 | }; | ||
69 | |||
70 | void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
71 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
72 | } | ||
73 | |||
74 | if (cpu_isar_feature(aa64_sve, cpu)) { | ||
75 | - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); | ||
76 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | ||
77 | - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | ||
78 | - } else { | ||
79 | - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | ||
80 | - } | ||
81 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
82 | - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | ||
83 | - } | ||
84 | + define_arm_cp_regs(cpu, zcr_reginfo); | ||
85 | } | ||
86 | |||
87 | #ifdef TARGET_AARCH64 | ||
88 | -- | 224 | -- |
89 | 2.25.1 | 225 | 2.34.1 |
226 | |||
227 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns changes to the External Debug interface, | 3 | Remember if there was an SNaN, and use that to simplify |
4 | with Secure and Non-secure access to the debug registers, and all | 4 | float_2nan_prop_s_{ab,ba} to only the snan component. |
5 | of it is outside the scope of QEMU. Indicating support for this | 5 | Then, fall through to the corresponding |
6 | is mandatory with FEAT_SEL2, which we do implement. | 6 | float_2nan_prop_{ab,ba} case to handle any remaining |
7 | nans, which must be quiet. | ||
7 | 8 | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 20241203203949.483774-10-richard.henderson@linaro.org |
10 | Message-id: 20220506180242.216785-13-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 13 | --- |
13 | docs/system/arm/emulation.rst | 1 + | 14 | fpu/softfloat-parts.c.inc | 32 ++++++++++++-------------------- |
14 | target/arm/cpu64.c | 2 +- | 15 | 1 file changed, 12 insertions(+), 20 deletions(-) |
15 | target/arm/cpu_tcg.c | 4 ++-- | ||
16 | 3 files changed, 4 insertions(+), 3 deletions(-) | ||
17 | 16 | ||
18 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/docs/system/arm/emulation.rst | 19 | --- a/fpu/softfloat-parts.c.inc |
21 | +++ b/docs/system/arm/emulation.rst | 20 | +++ b/fpu/softfloat-parts.c.inc |
22 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 21 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) |
23 | - FEAT_DIT (Data Independent Timing instructions) | 22 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
24 | - FEAT_DPB (DC CVAP instruction) | 23 | float_status *s) |
25 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 24 | { |
26 | +- FEAT_Debugv8p4 (Debug changes for v8.4) | 25 | + bool have_snan = false; |
27 | - FEAT_DotProd (Advanced SIMD dot product instructions) | 26 | int cmp, which; |
28 | - FEAT_FCMA (Floating-point complex number instructions) | 27 | |
29 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | 28 | if (is_snan(a->cls) || is_snan(b->cls)) { |
30 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 29 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
31 | index XXXXXXX..XXXXXXX 100644 | 30 | + have_snan = true; |
32 | --- a/target/arm/cpu64.c | 31 | } |
33 | +++ b/target/arm/cpu64.c | 32 | |
34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 33 | if (s->default_nan_mode) { |
35 | cpu->isar.id_aa64zfr0 = t; | 34 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
36 | 35 | ||
37 | t = cpu->isar.id_aa64dfr0; | 36 | switch (s->float_2nan_prop_rule) { |
38 | - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ | 37 | case float_2nan_prop_s_ab: |
39 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ | 38 | - if (is_snan(a->cls)) { |
40 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | 39 | - which = 0; |
41 | cpu->isar.id_aa64dfr0 = t; | 40 | - } else if (is_snan(b->cls)) { |
42 | 41 | - which = 1; | |
43 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 42 | - } else if (is_qnan(a->cls)) { |
44 | index XXXXXXX..XXXXXXX 100644 | 43 | - which = 0; |
45 | --- a/target/arm/cpu_tcg.c | 44 | - } else { |
46 | +++ b/target/arm/cpu_tcg.c | 45 | - which = 1; |
47 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 46 | + if (have_snan) { |
48 | cpu->isar.id_pfr2 = t; | 47 | + which = is_snan(a->cls) ? 0 : 1; |
49 | 48 | + break; | |
50 | t = cpu->isar.id_dfr0; | 49 | } |
51 | - t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | 50 | - break; |
52 | - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | 51 | - case float_2nan_prop_s_ba: |
53 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ | 52 | - if (is_snan(b->cls)) { |
54 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ | 53 | - which = 1; |
55 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | 54 | - } else if (is_snan(a->cls)) { |
56 | cpu->isar.id_dfr0 = t; | 55 | - which = 0; |
57 | } | 56 | - } else if (is_qnan(b->cls)) { |
57 | - which = 1; | ||
58 | - } else { | ||
59 | - which = 0; | ||
60 | - } | ||
61 | - break; | ||
62 | + /* fall through */ | ||
63 | case float_2nan_prop_ab: | ||
64 | which = is_nan(a->cls) ? 0 : 1; | ||
65 | break; | ||
66 | + case float_2nan_prop_s_ba: | ||
67 | + if (have_snan) { | ||
68 | + which = is_snan(b->cls) ? 1 : 0; | ||
69 | + break; | ||
70 | + } | ||
71 | + /* fall through */ | ||
72 | case float_2nan_prop_ba: | ||
73 | which = is_nan(b->cls) ? 1 : 0; | ||
74 | break; | ||
58 | -- | 75 | -- |
59 | 2.25.1 | 76 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Share the code to set AArch32 max features so that we no | 3 | Move the fractional comparison to the end of the |
4 | longer have code drift between qemu{-system,}-{arm,aarch64}. | 4 | float_2nan_prop_x87 case. This is not required for |
5 | any other 2nan propagation rule. Reorganize the | ||
6 | x87 case itself to break out of the switch when the | ||
7 | fractional comparison is not required. | ||
5 | 8 | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 20241203203949.483774-11-richard.henderson@linaro.org |
8 | Message-id: 20220506180242.216785-9-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | target/arm/internals.h | 2 + | 14 | fpu/softfloat-parts.c.inc | 19 +++++++++---------- |
12 | target/arm/cpu64.c | 50 +----------------- | 15 | 1 file changed, 9 insertions(+), 10 deletions(-) |
13 | target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- | ||
14 | 3 files changed, 65 insertions(+), 101 deletions(-) | ||
15 | 16 | ||
16 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/internals.h | 19 | --- a/fpu/softfloat-parts.c.inc |
19 | +++ b/target/arm/internals.h | 20 | +++ b/fpu/softfloat-parts.c.inc |
20 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | 21 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
21 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | 22 | return a; |
22 | #endif | 23 | } |
23 | 24 | ||
24 | +void aa32_max_features(ARMCPU *cpu); | 25 | - cmp = frac_cmp(a, b); |
25 | + | 26 | - if (cmp == 0) { |
26 | #endif | 27 | - cmp = a->sign < b->sign; |
27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 28 | - } |
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/cpu64.c | ||
30 | +++ b/target/arm/cpu64.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
32 | { | ||
33 | ARMCPU *cpu = ARM_CPU(obj); | ||
34 | uint64_t t; | ||
35 | - uint32_t u; | ||
36 | |||
37 | if (kvm_enabled() || hvf_enabled()) { | ||
38 | /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ | ||
39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
40 | t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
41 | cpu->isar.id_aa64zfr0 = t; | ||
42 | |||
43 | - /* Replicate the same data to the 32-bit id registers. */ | ||
44 | - u = cpu->isar.id_isar5; | ||
45 | - u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ | ||
46 | - u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); | ||
47 | - u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); | ||
48 | - u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); | ||
49 | - u = FIELD_DP32(u, ID_ISAR5, RDM, 1); | ||
50 | - u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); | ||
51 | - cpu->isar.id_isar5 = u; | ||
52 | - | 29 | - |
53 | - u = cpu->isar.id_isar6; | 30 | switch (s->float_2nan_prop_rule) { |
54 | - u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); | 31 | case float_2nan_prop_s_ab: |
55 | - u = FIELD_DP32(u, ID_ISAR6, DP, 1); | 32 | if (have_snan) { |
56 | - u = FIELD_DP32(u, ID_ISAR6, FHM, 1); | 33 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
57 | - u = FIELD_DP32(u, ID_ISAR6, SB, 1); | 34 | * return the NaN with the positive sign bit (if any). |
58 | - u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); | 35 | */ |
59 | - u = FIELD_DP32(u, ID_ISAR6, BF16, 1); | 36 | if (is_snan(a->cls)) { |
60 | - u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); | 37 | - if (is_snan(b->cls)) { |
61 | - cpu->isar.id_isar6 = u; | 38 | - which = cmp > 0 ? 0 : 1; |
62 | - | 39 | - } else { |
63 | - u = cpu->isar.id_pfr0; | 40 | + if (!is_snan(b->cls)) { |
64 | - u = FIELD_DP32(u, ID_PFR0, DIT, 1); | 41 | which = is_qnan(b->cls) ? 1 : 0; |
65 | - cpu->isar.id_pfr0 = u; | 42 | + break; |
66 | - | 43 | } |
67 | - u = cpu->isar.id_pfr2; | 44 | } else if (is_qnan(a->cls)) { |
68 | - u = FIELD_DP32(u, ID_PFR2, SSBS, 1); | 45 | if (is_snan(b->cls) || !is_qnan(b->cls)) { |
69 | - cpu->isar.id_pfr2 = u; | 46 | which = 0; |
70 | - | 47 | - } else { |
71 | - u = cpu->isar.id_mmfr3; | 48 | - which = cmp > 0 ? 0 : 1; |
72 | - u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ | 49 | + break; |
73 | - cpu->isar.id_mmfr3 = u; | 50 | } |
74 | - | 51 | } else { |
75 | - u = cpu->isar.id_mmfr4; | 52 | which = 1; |
76 | - u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ | 53 | + break; |
77 | - u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | 54 | } |
78 | - u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ | 55 | + cmp = frac_cmp(a, b); |
79 | - u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ | 56 | + if (cmp == 0) { |
80 | - cpu->isar.id_mmfr4 = u; | 57 | + cmp = a->sign < b->sign; |
81 | - | 58 | + } |
82 | t = cpu->isar.id_aa64dfr0; | 59 | + which = cmp > 0 ? 0 : 1; |
83 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | 60 | break; |
84 | cpu->isar.id_aa64dfr0 = t; | 61 | default: |
85 | 62 | g_assert_not_reached(); | |
86 | - u = cpu->isar.id_dfr0; | ||
87 | - u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
88 | - cpu->isar.id_dfr0 = u; | ||
89 | - | ||
90 | - u = cpu->isar.mvfr1; | ||
91 | - u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
92 | - u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
93 | - cpu->isar.mvfr1 = u; | ||
94 | + /* Replicate the same data to the 32-bit id registers. */ | ||
95 | + aa32_max_features(cpu); | ||
96 | |||
97 | #ifdef CONFIG_USER_ONLY | ||
98 | /* | ||
99 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/target/arm/cpu_tcg.c | ||
102 | +++ b/target/arm/cpu_tcg.c | ||
103 | @@ -XXX,XX +XXX,XX @@ | ||
104 | #endif | ||
105 | #include "cpregs.h" | ||
106 | |||
107 | + | ||
108 | +/* Share AArch32 -cpu max features with AArch64. */ | ||
109 | +void aa32_max_features(ARMCPU *cpu) | ||
110 | +{ | ||
111 | + uint32_t t; | ||
112 | + | ||
113 | + /* Add additional features supported by QEMU */ | ||
114 | + t = cpu->isar.id_isar5; | ||
115 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
116 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
117 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
118 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
119 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
120 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
121 | + cpu->isar.id_isar5 = t; | ||
122 | + | ||
123 | + t = cpu->isar.id_isar6; | ||
124 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
125 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
126 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
127 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
128 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
129 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
130 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
131 | + cpu->isar.id_isar6 = t; | ||
132 | + | ||
133 | + t = cpu->isar.mvfr1; | ||
134 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
135 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
136 | + cpu->isar.mvfr1 = t; | ||
137 | + | ||
138 | + t = cpu->isar.mvfr2; | ||
139 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
140 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
141 | + cpu->isar.mvfr2 = t; | ||
142 | + | ||
143 | + t = cpu->isar.id_mmfr3; | ||
144 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
145 | + cpu->isar.id_mmfr3 = t; | ||
146 | + | ||
147 | + t = cpu->isar.id_mmfr4; | ||
148 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
149 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
150 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
151 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
152 | + cpu->isar.id_mmfr4 = t; | ||
153 | + | ||
154 | + t = cpu->isar.id_pfr0; | ||
155 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
156 | + cpu->isar.id_pfr0 = t; | ||
157 | + | ||
158 | + t = cpu->isar.id_pfr2; | ||
159 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
160 | + cpu->isar.id_pfr2 = t; | ||
161 | + | ||
162 | + t = cpu->isar.id_dfr0; | ||
163 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
164 | + cpu->isar.id_dfr0 = t; | ||
165 | +} | ||
166 | + | ||
167 | #ifndef CONFIG_USER_ONLY | ||
168 | static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
169 | { | ||
170 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
171 | static void arm_max_initfn(Object *obj) | ||
172 | { | ||
173 | ARMCPU *cpu = ARM_CPU(obj); | ||
174 | - uint32_t t; | ||
175 | |||
176 | /* aarch64_a57_initfn, advertising none of the aarch64 features */ | ||
177 | cpu->dtb_compatible = "arm,cortex-a57"; | ||
178 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
179 | cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
180 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
181 | |||
182 | - /* Add additional features supported by QEMU */ | ||
183 | - t = cpu->isar.id_isar5; | ||
184 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
185 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
186 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
187 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
188 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
189 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
190 | - cpu->isar.id_isar5 = t; | ||
191 | - | ||
192 | - t = cpu->isar.id_isar6; | ||
193 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
194 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
195 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
196 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
197 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
198 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
199 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
200 | - cpu->isar.id_isar6 = t; | ||
201 | - | ||
202 | - t = cpu->isar.mvfr1; | ||
203 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
204 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
205 | - cpu->isar.mvfr1 = t; | ||
206 | - | ||
207 | - t = cpu->isar.mvfr2; | ||
208 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
209 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
210 | - cpu->isar.mvfr2 = t; | ||
211 | - | ||
212 | - t = cpu->isar.id_mmfr3; | ||
213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
214 | - cpu->isar.id_mmfr3 = t; | ||
215 | - | ||
216 | - t = cpu->isar.id_mmfr4; | ||
217 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
218 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
219 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
220 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
221 | - cpu->isar.id_mmfr4 = t; | ||
222 | - | ||
223 | - t = cpu->isar.id_pfr0; | ||
224 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
225 | - cpu->isar.id_pfr0 = t; | ||
226 | - | ||
227 | - t = cpu->isar.id_pfr2; | ||
228 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
229 | - cpu->isar.id_pfr2 = t; | ||
230 | - | ||
231 | - t = cpu->isar.id_dfr0; | ||
232 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
233 | - cpu->isar.id_dfr0 = t; | ||
234 | + aa32_max_features(cpu); | ||
235 | |||
236 | #ifdef CONFIG_USER_ONLY | ||
237 | /* | ||
238 | -- | 63 | -- |
239 | 2.25.1 | 64 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This register is present for either VHE or Debugv8p2. | 3 | Replace the "index" selecting between A and B with a result variable |
4 | of the proper type. This improves clarity within the function. | ||
4 | 5 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-5-richard.henderson@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20241203203949.483774-12-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/helper.c | 15 +++++++++++---- | 11 | fpu/softfloat-parts.c.inc | 28 +++++++++++++--------------- |
11 | 1 file changed, 11 insertions(+), 4 deletions(-) | 12 | 1 file changed, 13 insertions(+), 15 deletions(-) |
12 | 13 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 16 | --- a/fpu/softfloat-parts.c.inc |
16 | +++ b/target/arm/helper.c | 17 | +++ b/fpu/softfloat-parts.c.inc |
17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = { | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
18 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 19 | float_status *s) |
19 | }; | 20 | { |
20 | 21 | bool have_snan = false; | |
21 | +static const ARMCPRegInfo contextidr_el2 = { | 22 | - int cmp, which; |
22 | + .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | 23 | + FloatPartsN *ret; |
23 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | 24 | + int cmp; |
24 | + .access = PL2_RW, | 25 | |
25 | + .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) | 26 | if (is_snan(a->cls) || is_snan(b->cls)) { |
26 | +}; | 27 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
27 | + | 28 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
28 | static const ARMCPRegInfo vhe_reginfo[] = { | 29 | switch (s->float_2nan_prop_rule) { |
29 | - { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | 30 | case float_2nan_prop_s_ab: |
30 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | 31 | if (have_snan) { |
31 | - .access = PL2_RW, | 32 | - which = is_snan(a->cls) ? 0 : 1; |
32 | - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, | 33 | + ret = is_snan(a->cls) ? a : b; |
33 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, | 34 | break; |
34 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | 35 | } |
35 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | 36 | /* fall through */ |
36 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 37 | case float_2nan_prop_ab: |
37 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | 38 | - which = is_nan(a->cls) ? 0 : 1; |
39 | + ret = is_nan(a->cls) ? a : b; | ||
40 | break; | ||
41 | case float_2nan_prop_s_ba: | ||
42 | if (have_snan) { | ||
43 | - which = is_snan(b->cls) ? 1 : 0; | ||
44 | + ret = is_snan(b->cls) ? b : a; | ||
45 | break; | ||
46 | } | ||
47 | /* fall through */ | ||
48 | case float_2nan_prop_ba: | ||
49 | - which = is_nan(b->cls) ? 1 : 0; | ||
50 | + ret = is_nan(b->cls) ? b : a; | ||
51 | break; | ||
52 | case float_2nan_prop_x87: | ||
53 | /* | ||
54 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
55 | */ | ||
56 | if (is_snan(a->cls)) { | ||
57 | if (!is_snan(b->cls)) { | ||
58 | - which = is_qnan(b->cls) ? 1 : 0; | ||
59 | + ret = is_qnan(b->cls) ? b : a; | ||
60 | break; | ||
61 | } | ||
62 | } else if (is_qnan(a->cls)) { | ||
63 | if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
64 | - which = 0; | ||
65 | + ret = a; | ||
66 | break; | ||
67 | } | ||
68 | } else { | ||
69 | - which = 1; | ||
70 | + ret = b; | ||
71 | break; | ||
72 | } | ||
73 | cmp = frac_cmp(a, b); | ||
74 | if (cmp == 0) { | ||
75 | cmp = a->sign < b->sign; | ||
76 | } | ||
77 | - which = cmp > 0 ? 0 : 1; | ||
78 | + ret = cmp > 0 ? a : b; | ||
79 | break; | ||
80 | default: | ||
81 | g_assert_not_reached(); | ||
38 | } | 82 | } |
39 | 83 | ||
40 | + if (cpu_isar_feature(aa64_vh, cpu) || | 84 | - if (which) { |
41 | + cpu_isar_feature(aa64_debugv8p2, cpu)) { | 85 | - a = b; |
42 | + define_one_arm_cp_reg(cpu, &contextidr_el2); | 86 | + if (is_snan(ret->cls)) { |
43 | + } | 87 | + parts_silence_nan(ret, s); |
44 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | ||
45 | define_arm_cp_regs(cpu, vhe_reginfo); | ||
46 | } | 88 | } |
89 | - if (is_snan(a->cls)) { | ||
90 | - parts_silence_nan(a, s); | ||
91 | - } | ||
92 | - return a; | ||
93 | + return ret; | ||
94 | } | ||
95 | |||
96 | static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
47 | -- | 97 | -- |
48 | 2.25.1 | 98 | 2.34.1 |
99 | |||
100 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <quic_llindhol@quicinc.com> | 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> |
---|---|---|---|
2 | 2 | ||
3 | NUVIA was acquired by Qualcomm in March 2021, but kept functioning on | 3 | I'm migrating to Qualcomm's new open source email infrastructure, so |
4 | separate infrastructure for a transitional period. We've now switched | 4 | update my email address, and update the mailmap to match. |
5 | over to contributing as Qualcomm Innovation Center (quicinc), so update | ||
6 | my email address to reflect this. | ||
7 | 5 | ||
8 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | 6 | Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
9 | Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com | 7 | Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> |
10 | Cc: Leif Lindholm <leif@nuviainc.com> | 8 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> |
11 | Cc: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
13 | [Fixed commit message typo] | 11 | Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com |
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 13 | --- |
16 | .mailmap | 3 ++- | ||
17 | MAINTAINERS | 2 +- | 14 | MAINTAINERS | 2 +- |
18 | 2 files changed, 3 insertions(+), 2 deletions(-) | 15 | .mailmap | 5 +++-- |
16 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
19 | 17 | ||
20 | diff --git a/.mailmap b/.mailmap | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/.mailmap | ||
23 | +++ b/.mailmap | ||
24 | @@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com> | ||
25 | Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> | ||
26 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> | ||
27 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> | ||
28 | -Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org> | ||
29 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> | ||
30 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> | ||
31 | Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org> | ||
32 | Paul Burton <paulburton@kernel.org> <paul.burton@mips.com> | ||
33 | Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com> | ||
34 | diff --git a/MAINTAINERS b/MAINTAINERS | 18 | diff --git a/MAINTAINERS b/MAINTAINERS |
35 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/MAINTAINERS | 20 | --- a/MAINTAINERS |
37 | +++ b/MAINTAINERS | 21 | +++ b/MAINTAINERS |
38 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h | 22 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h |
39 | SBSA-REF | 23 | SBSA-REF |
40 | M: Radoslaw Biernacki <rad@semihalf.com> | 24 | M: Radoslaw Biernacki <rad@semihalf.com> |
41 | M: Peter Maydell <peter.maydell@linaro.org> | 25 | M: Peter Maydell <peter.maydell@linaro.org> |
42 | -R: Leif Lindholm <leif@nuviainc.com> | 26 | -R: Leif Lindholm <quic_llindhol@quicinc.com> |
43 | +R: Leif Lindholm <quic_llindhol@quicinc.com> | 27 | +R: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
28 | R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
44 | L: qemu-arm@nongnu.org | 29 | L: qemu-arm@nongnu.org |
45 | S: Maintained | 30 | S: Maintained |
46 | F: hw/arm/sbsa-ref.c | 31 | diff --git a/.mailmap b/.mailmap |
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/.mailmap | ||
34 | +++ b/.mailmap | ||
35 | @@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> | ||
36 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> | ||
37 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> | ||
38 | Juan Quintela <quintela@trasno.org> <quintela@redhat.com> | ||
39 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> | ||
40 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> | ||
41 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com> | ||
42 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org> | ||
43 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com> | ||
44 | Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr> | ||
45 | Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com> | ||
46 | Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu> | ||
47 | -- | 47 | -- |
48 | 2.25.1 | 48 | 2.34.1 |
49 | 49 | ||
50 | 50 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Vikram Garhwal <vikram.garhwal@bytedance.com> |
---|---|---|---|
2 | 2 | ||
3 | This adds cluster-id in CPU instance properties, which will be used | 3 | Previously, maintainer role was paused due to inactive email id. Commit id: |
4 | by arm/virt machine. Besides, the cluster-id is also verified or | 4 | c009d715721861984c4987bcc78b7ee183e86d75. |
5 | dumped in various spots: | ||
6 | 5 | ||
7 | * hw/core/machine.c::machine_set_cpu_numa_node() to associate | 6 | Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com> |
8 | CPU with its NUMA node. | 7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> |
9 | 8 | Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com | |
10 | * hw/core/machine.c::machine_numa_finish_cpu_init() to record | ||
11 | CPU slots with no NUMA mapping set. | ||
12 | |||
13 | * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump | ||
14 | cluster-id. | ||
15 | |||
16 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
17 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
18 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
19 | Message-id: 20220503140304.855514-2-gshan@redhat.com | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | --- | 10 | --- |
22 | qapi/machine.json | 6 ++++-- | 11 | MAINTAINERS | 2 ++ |
23 | hw/core/machine-hmp-cmds.c | 4 ++++ | 12 | 1 file changed, 2 insertions(+) |
24 | hw/core/machine.c | 16 ++++++++++++++++ | ||
25 | 3 files changed, 24 insertions(+), 2 deletions(-) | ||
26 | 13 | ||
27 | diff --git a/qapi/machine.json b/qapi/machine.json | 14 | diff --git a/MAINTAINERS b/MAINTAINERS |
28 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/qapi/machine.json | 16 | --- a/MAINTAINERS |
30 | +++ b/qapi/machine.json | 17 | +++ b/MAINTAINERS |
31 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c |
32 | # @node-id: NUMA node ID the CPU belongs to | 19 | |
33 | # @socket-id: socket number within node/board the CPU belongs to | 20 | Xilinx CAN |
34 | # @die-id: die number within socket the CPU belongs to (since 4.1) | 21 | M: Francisco Iglesias <francisco.iglesias@amd.com> |
35 | -# @core-id: core number within die the CPU belongs to | 22 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> |
36 | +# @cluster-id: cluster number within die the CPU belongs to (since 7.1) | 23 | S: Maintained |
37 | +# @core-id: core number within cluster the CPU belongs to | 24 | F: hw/net/can/xlnx-* |
38 | # @thread-id: thread number within core the CPU belongs to | 25 | F: include/hw/net/xlnx-* |
39 | # | 26 | @@ -XXX,XX +XXX,XX @@ F: include/hw/rx/ |
40 | -# Note: currently there are 5 properties that could be present | 27 | CAN bus subsystem and hardware |
41 | +# Note: currently there are 6 properties that could be present | 28 | M: Pavel Pisa <pisa@cmp.felk.cvut.cz> |
42 | # but management should be prepared to pass through other | 29 | M: Francisco Iglesias <francisco.iglesias@amd.com> |
43 | # properties with device_add command to allow for future | 30 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> |
44 | # interface extension. This also requires the filed names to be kept in | 31 | S: Maintained |
45 | @@ -XXX,XX +XXX,XX @@ | 32 | W: https://canbus.pages.fel.cvut.cz/ |
46 | 'data': { '*node-id': 'int', | 33 | F: net/can/* |
47 | '*socket-id': 'int', | ||
48 | '*die-id': 'int', | ||
49 | + '*cluster-id': 'int', | ||
50 | '*core-id': 'int', | ||
51 | '*thread-id': 'int' | ||
52 | } | ||
53 | diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/hw/core/machine-hmp-cmds.c | ||
56 | +++ b/hw/core/machine-hmp-cmds.c | ||
57 | @@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) | ||
58 | if (c->has_die_id) { | ||
59 | monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); | ||
60 | } | ||
61 | + if (c->has_cluster_id) { | ||
62 | + monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n", | ||
63 | + c->cluster_id); | ||
64 | + } | ||
65 | if (c->has_core_id) { | ||
66 | monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); | ||
67 | } | ||
68 | diff --git a/hw/core/machine.c b/hw/core/machine.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/core/machine.c | ||
71 | +++ b/hw/core/machine.c | ||
72 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | ||
73 | return; | ||
74 | } | ||
75 | |||
76 | + if (props->has_cluster_id && !slot->props.has_cluster_id) { | ||
77 | + error_setg(errp, "cluster-id is not supported"); | ||
78 | + return; | ||
79 | + } | ||
80 | + | ||
81 | if (props->has_socket_id && !slot->props.has_socket_id) { | ||
82 | error_setg(errp, "socket-id is not supported"); | ||
83 | return; | ||
84 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | ||
85 | continue; | ||
86 | } | ||
87 | |||
88 | + if (props->has_cluster_id && | ||
89 | + props->cluster_id != slot->props.cluster_id) { | ||
90 | + continue; | ||
91 | + } | ||
92 | + | ||
93 | if (props->has_die_id && props->die_id != slot->props.die_id) { | ||
94 | continue; | ||
95 | } | ||
96 | @@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu) | ||
97 | } | ||
98 | g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); | ||
99 | } | ||
100 | + if (cpu->props.has_cluster_id) { | ||
101 | + if (s->len) { | ||
102 | + g_string_append_printf(s, ", "); | ||
103 | + } | ||
104 | + g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); | ||
105 | + } | ||
106 | if (cpu->props.has_core_id) { | ||
107 | if (s->len) { | ||
108 | g_string_append_printf(s, ", "); | ||
109 | -- | 34 | -- |
110 | 2.25.1 | 35 | 2.34.1 | diff view generated by jsdifflib |