Series comparison

-[PULL 00/32] target-arm queue
+[PULL 00/21] target-arm queue
-target-arm queue: the big stuff here is the final part of
+Here's another arm pullreq; nothing too exciting in here I think.
 rth's patches for Cortex-A76 and Neoverse-N1 support;
 also present are Gavin's NUMA series and a few other things.
 thanks
 -- PMM
-The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
+The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:
-  Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
+  Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2024-04-29 14:34:25 -0700)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240430
-for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
+for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:
-  hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
+  tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * MAINTAINERS/.mailmap: update email for Leif Lindholm
+ * hw/core/clock: allow clock_propagate on child clocks
- * hw/arm: add version information to sbsa-ref machine DT
+ * hvf: arm: Remove unused PL1_WRITE_MASK define
- * Enable new features for -cpu max:
+ * target/arm: Restrict translation disabled alignment check to VMSA
-   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
+ * docs/system/arm/emulation.rst: Add missing implemented features
-   FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
+ * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
- * Emulate Cortex-A76
+ * tests/avocado: update sunxi kernel from armbian to 6.6.16
- * Emulate Neoverse-N1
+ * target/arm: Make new CPUs default to 1GHz generic timer
- * Fix the virt board default NUMA topology
+ * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
  * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
  * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
  * hw/arm: Add DM163 display to B-L475E-IOT01A board
 ----------------------------------------------------------------
-Gavin Shan (6):
+Alexandra Diupina (1):
-      qapi/machine.json: Add cluster-id
+      hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
       qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
       hw/arm/virt: Consider SMP configuration in CPU topology
       qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
       hw/arm/virt: Fix CPU's default NUMA node ID
       hw/acpi/aml-build: Use existing CPU topology to build PPTT table
-Leif Lindholm (2):
+Inès Varhol (5):
-      MAINTAINERS/.mailmap: update email for Leif Lindholm
+      hw/display : Add device DM163
-      hw/arm: add versioning to sbsa-ref machine DT
+      hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
       hw/arm : Create Bl475eMachineState
       hw/arm : Connect DM163 to B-L475E-IOT01A
       tests/qtest : Add testcase for DM163
-Richard Henderson (24):
+Peter Maydell (10):
-      target/arm: Handle cpreg registration for missing EL
+      docs/system/arm/emulation.rst: Add missing implemented features
-      target/arm: Drop EL3 no EL2 fallbacks
+      target/arm: Enable FEAT_CSV2_3 for -cpu max
-      target/arm: Merge zcr reginfo
+      target/arm: Enable FEAT_ETS2 for -cpu max
-      target/arm: Adjust definition of CONTEXTIDR_EL2
+      target/arm: Implement ID_AA64MMFR3_EL1
-      target/arm: Move cortex impdef sysregs to cpu_tcg.c
+      target/arm: Enable FEAT_Spec_FPACC for -cpu max
-      target/arm: Update qemu-system-arm -cpu max to cortex-a57
+      tests/avocado: update sunxi kernel from armbian to 6.6.16
-      target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
+      target/arm: Refactor default generic timer frequency handling
-      target/arm: Split out aa32_max_features
+      hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
-      target/arm: Annotate arm_max_initfn with FEAT identifiers
+      hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
-      target/arm: Use field names for manipulating EL2 and EL3 modes
+      target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
       target/arm: Enable FEAT_Debugv8p2 for -cpu max
       target/arm: Enable FEAT_Debugv8p4 for -cpu max
       target/arm: Add minimal RAS registers
       target/arm: Enable SCR and HCR bits for RAS
       target/arm: Implement virtual SError exceptions
       target/arm: Implement ESB instruction
       target/arm: Enable FEAT_RAS for -cpu max
       target/arm: Enable FEAT_IESB for -cpu max
       target/arm: Enable FEAT_CSV2 for -cpu max
       target/arm: Enable FEAT_CSV2_2 for -cpu max
       target/arm: Enable FEAT_CSV3 for -cpu max
       target/arm: Enable FEAT_DGH for -cpu max
       target/arm: Define cortex-a76
       target/arm: Define neoverse-n1
- docs/system/arm/emulation.rst |  10 +
+Philippe Mathieu-Daudé (1):
- docs/system/arm/virt.rst      |   2 +
+      hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
- qapi/machine.json             |   6 +-
- target/arm/cpregs.h           |  11 +
+Raphael Poggi (1):
- target/arm/cpu.h              |  23 ++
+      hw/core/clock: allow clock_propagate on child clocks
- target/arm/helper.h           |   1 +
- target/arm/internals.h        |  16 ++
+Richard Henderson (1):
- target/arm/syndrome.h         |   5 +
+      target/arm: Restrict translation disabled alignment check to VMSA
- target/arm/a32.decode         |  16 +-
- target/arm/t32.decode         |  18 +-
+Thomas Huth (1):
- hw/acpi/aml-build.c           | 111 ++++----
+      hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
- hw/arm/sbsa-ref.c             |  16 ++
- hw/arm/virt.c                 |  21 +-
+Zenghui Yu (1):
- hw/core/machine-hmp-cmds.c    |   4 +
+      hvf: arm: Remove PL1_WRITE_MASK
- hw/core/machine.c             |  16 ++
- target/arm/cpu.c              |  66 ++++-
+ docs/system/arm/b-l475e-iot01a.rst  |   3 +-
- target/arm/cpu64.c            | 353 ++++++++++++++-----------
+ docs/system/arm/emulation.rst       |  42 ++++-
- target/arm/cpu_tcg.c          | 227 +++++++++++-----
+ include/hw/display/dm163.h          |  59 ++++++
- target/arm/helper.c           | 600 +++++++++++++++++++++++++-----------------
+ include/hw/watchdog/sbsa_gwdt.h     |   3 +-
- target/arm/op_helper.c        |  43 +++
+ target/arm/cpu.h                    |  28 +++
- target/arm/translate-a64.c    |  18 ++
+ target/arm/internals.h              |  15 +-
- target/arm/translate.c        |  23 ++
+ hw/arm/b-l475e-iot01a.c             | 105 +++++++++--
- tests/qtest/numa-test.c       |  19 +-
+ hw/arm/npcm7xx.c                    |   3 +-
- .mailmap                      |   3 +-
+ hw/arm/sbsa-ref.c                   |  16 ++
- MAINTAINERS                   |   2 +-
+ hw/arm/stm32l4x5_soc.c              |   6 +-
-files changed, 1068 insertions(+), 562 deletions(-)
+ hw/char/stm32l4x5_usart.c           |   1 +
  hw/core/clock.c                     |   1 -
  hw/core/machine.c                   |   4 +-
  hw/display/dm163.c                  | 349 ++++++++++++++++++++++++++++++++++++
  hw/dma/xlnx_dpdma.c                 |  20 +--
  hw/watchdog/sbsa_gwdt.c             |  15 +-
  target/arm/cpu.c                    |  42 +++--
  target/arm/cpu64.c                  |   2 +
  target/arm/helper.c                 |  22 +--
  target/arm/hvf/hvf.c                |   3 +-
  target/arm/kvm.c                    |   2 +
  target/arm/tcg/cpu32.c              |   6 +-
  target/arm/tcg/cpu64.c              |  28 ++-
  target/arm/tcg/hflags.c             |  12 +-
  tests/qtest/dm163-test.c            | 194 ++++++++++++++++++++
  tests/qtest/stm32l4x5_gpio-test.c   |  13 +-
  tests/qtest/stm32l4x5_syscfg-test.c |  17 +-
  hw/arm/Kconfig                      |   1 +
  hw/display/Kconfig                  |   3 +
  hw/display/meson.build              |   1 +
  hw/display/trace-events             |  14 ++
  tests/avocado/boot_linux_console.py |  70 ++++----
  tests/avocado/replay_kernel.py      |   8 +-
  tests/qtest/meson.build             |   2 +
 files changed, 987 insertions(+), 123 deletions(-)
  create mode 100644 include/hw/display/dm163.h
  create mode 100644 hw/display/dm163.c
  create mode 100644 tests/qtest/dm163-test.c

-[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
+[PULL 01/21] hw/core/clock: allow clock_propagate on child clocks
-From: Gavin Shan <gshan@redhat.com>
+From: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
-Currently, the SMP configuration isn't considered when the CPU
+clock_propagate() has an assert that clk->source is NULL, i.e. that
-topology is populated. In this case, it's impossible to provide
+you are calling it on a clock which has no source clock.  This made
-the default CPU-to-NUMA mapping or association based on the socket
+sense in the original design where the only way for a clock's
-ID of the given CPU.
+frequency to change if it had a source clock was when that source
 clock changed.  However, we subsequently added multiplier/divider
 support, but didn't look at what that meant for propagation.
-This takes account of SMP configuration when the CPU topology
+If a clock-management device changes the multiplier or divider value
-is populated. The die ID for the given CPU isn't assigned since
+on a clock, it needs to propagate that change down to child clocks,
-it's not supported on arm/virt machine. Besides, the used SMP
+even if the clock has a source clock set.  So the assertion is now
-configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
+incorrect.
 to avoid testing failure
-Signed-off-by: Gavin Shan <gshan@redhat.com>
+Remove the assertion.
-Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
-Acked-by: Igor Mammedov <imammedo@redhat.com>
+Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
-Message-id: 20220503140304.855514-4-gshan@redhat.com
+Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 [PMM: Rewrote the commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 15 ++++++++++++++-
+ hw/core/clock.c | 1 -
-file changed, 14 insertions(+), 1 deletion(-)
+file changed, 1 deletion(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/hw/core/clock.c b/hw/core/clock.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/hw/core/clock.c
-+++ b/hw/arm/virt.c
++++ b/hw/core/clock.c
-@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
+@@ -XXX,XX +XXX,XX @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
-     int n;
-     unsigned int max_cpus = ms->smp.max_cpus;
+ void clock_propagate(Clock *clk)
-     VirtMachineState *vms = VIRT_MACHINE(ms);
+ {
-+    MachineClass *mc = MACHINE_GET_CLASS(vms);
+-    assert(clk->source == NULL);
+     trace_clock_propagate(CLOCK_PATH(clk));
-     if (ms->possible_cpus) {
+     clock_propagate_period(clk, true);
          assert(ms->possible_cpus->len == max_cpus);
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
          ms->possible_cpus->cpus[n].type = ms->cpu_type;
          ms->possible_cpus->cpus[n].arch_id =
              virt_cpu_mp_affinity(vms, n);
 +
 +        assert(!mc->smp_props.dies_supported);
 +        ms->possible_cpus->cpus[n].props.has_socket_id = true;
 +        ms->possible_cpus->cpus[n].props.socket_id =
 +            n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
 +        ms->possible_cpus->cpus[n].props.has_cluster_id = true;
 +        ms->possible_cpus->cpus[n].props.cluster_id =
 +            (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
 +        ms->possible_cpus->cpus[n].props.has_core_id = true;
 +        ms->possible_cpus->cpus[n].props.core_id =
 +            (n / ms->smp.threads) % ms->smp.cores;
          ms->possible_cpus->cpus[n].props.has_thread_id = true;
 -        ms->possible_cpus->cpus[n].props.thread_id = n;
 +        ms->possible_cpus->cpus[n].props.thread_id =
 +            n % ms->smp.threads;
      }
      return ms->possible_cpus;
  }
 --
-.25.1
+.34.1

-[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
+[PULL 02/21] hvf: arm: Remove PL1_WRITE_MASK
-From: Gavin Shan <gshan@redhat.com>
+From: Zenghui Yu <zenghui.yu@linux.dev>
-When CPU-to-NUMA association isn't explicitly provided by users,
+As it had never been used since the first commit a1477da3ddeb ("hvf: Add
-the default one is given by mc->get_default_cpu_node_id(). However,
+Apple Silicon support").
 the CPU topology isn't fully considered in the default association
 and this causes CPU topology broken warnings on booting Linux guest.
-For example, the following warning messages are observed when the
+Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev>
-Linux guest is booted with the following command lines.
+Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
   /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
   -accel kvm -machine virt,gic-version=host               \
   -cpu host                                               \
   -smp 6,sockets=2,cores=3,threads=1                      \
   -m 1024M,slots=16,maxmem=64G                            \
   -object memory-backend-ram,id=mem0,size=128M            \
   -object memory-backend-ram,id=mem1,size=128M            \
   -object memory-backend-ram,id=mem2,size=128M            \
   -object memory-backend-ram,id=mem3,size=128M            \
   -object memory-backend-ram,id=mem4,size=128M            \
   -object memory-backend-ram,id=mem4,size=384M            \
   -numa node,nodeid=0,memdev=mem0                         \
   -numa node,nodeid=1,memdev=mem1                         \
   -numa node,nodeid=2,memdev=mem2                         \
   -numa node,nodeid=3,memdev=mem3                         \
   -numa node,nodeid=4,memdev=mem4                         \
   -numa node,nodeid=5,memdev=mem5
          :
   alternatives: patching kernel code
   BUG: arch topology borken
   the CLS domain not a subset of the MC domain
   <the above error log repeats>
   BUG: arch topology borken
   the DIE domain not a subset of the NODE domain
 With current implementation of mc->get_default_cpu_node_id(),
 CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
 That's incorrect because CPU#0/1/2 should be associated with same
 NUMA node because they're seated in same socket.
 This fixes the issue by considering the socket ID when the default
 CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
 With this applied, no more CPU topology broken warnings are seen
 from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
 there are no CPUs associated with NODE#2/3/4/5.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Message-id: 20220503140304.855514-6-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 4 +++-
+ target/arm/hvf/hvf.c | 1 -
-file changed, 3 insertions(+), 1 deletion(-)
+file changed, 1 deletion(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/target/arm/hvf/hvf.c
-+++ b/hw/arm/virt.c
++++ b/target/arm/hvf/hvf.c
-@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
+@@ -XXX,XX +XXX,XX @@ void hvf_arm_init_debug(void)
- static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
+ #define HVF_SYSREG(crn, crm, op0, op1, op2) \
- {
+         ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
--    return idx % ms->numa_state->num_nodes;
+-#define PL1_WRITE_MASK 0x4
-+    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
-+
+ #define SYSREG_OP0_SHIFT      20
-+    return socket_id % ms->numa_state->num_nodes;
+ #define SYSREG_OP0_MASK       0x3
  }
  static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
 --
-.25.1
+.34.1

-[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
+[PULL 03/21] target/arm: Restrict translation disabled alignment check to VMSA
 From: Richard Henderson <richard.henderson@linaro.org>
-Enable writes to the TERR and TEA bits when RAS is enabled.
+For cpus using PMSA, when the MPU is disabled, the default memory
-These bits are otherwise RES0.
+type is Normal, Non-cachable. This means that it should not
 have alignment restrictions enforced.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Cc: qemu-stable@nongnu.org
 Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
 Reported-by: Clément Chigot <chigot@adacore.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Tested-by: Clément Chigot <chigot@adacore.com>
 Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
 [PMM: trivial comment, commit message tweaks]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 9 +++++++++
+ target/arm/tcg/hflags.c | 12 ++++++++++--
-file changed, 9 insertions(+)
+file changed, 10 insertions(+), 2 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/tcg/hflags.c
-+++ b/target/arm/helper.c
++++ b/target/arm/tcg/hflags.c
-@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+@@ -XXX,XX +XXX,XX @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
          }
          valid_mask &= ~SCR_NET;
 +        if (cpu_isar_feature(aa64_ras, cpu)) {
 +            valid_mask |= SCR_TERR;
 +        }
          if (cpu_isar_feature(aa64_lor, cpu)) {
              valid_mask |= SCR_TLOR;
          }
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          }
      } else {
          valid_mask &= ~(SCR_RW | SCR_ST);
 +        if (cpu_isar_feature(aa32_ras, cpu)) {
 +            valid_mask |= SCR_TERR;
 +        }
      }
-     if (!arm_feature(env, ARM_FEATURE_EL2)) {
+     /*
-@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
+-     * If translation is disabled, then the default memory type is
-         if (cpu_isar_feature(aa64_vh, cpu)) {
+-     * Device(-nGnRnE) instead of Normal, which requires that alignment
-             valid_mask |= HCR_E2H;
++     * With PMSA, when the MPU is disabled, all memory types in the
-         }
++     * default map are Normal, so don't need aligment enforcing.
-+        if (cpu_isar_feature(aa64_ras, cpu)) {
++     */
-+            valid_mask |= HCR_TERR | HCR_TEA;
++    if (arm_feature(env, ARM_FEATURE_PMSA)) {
-+        }
++        return false;
-         if (cpu_isar_feature(aa64_lor, cpu)) {
++    }
-             valid_mask |= HCR_TLOR;
++
-         }
++    /*
 +     * With VMSA, if translation is disabled, then the default memory type
 +     * is Device(-nGnRnE) instead of Normal, which requires that alignment
       * be enforced.  Since this affects all ram, it is most efficient
       * to handle this during translation.
       */
 --
-.25.1
+.34.1

-[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
+[PULL 04/21] docs/system/arm/emulation.rst: Add missing implemented features
-From: Richard Henderson <richard.henderson@linaro.org>
+As of version DDI0487K.a of the Arm ARM, some architectural features
 which previously didn't have official names have been named.  Add
 these to the list of features which QEMU's TCG emulation supports.
 Mostly these are features which we thought of as part of baseline 8.0
 support.  For SVE and SVE2, the names have been brought into line
 with the FEAT_* naming convention of other extensions, and some
 sub-components split into separate FEAT_ items.  In a few cases (eg
 FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight.
-This extension concerns branch speculation, which TCG does
-not implement.  Thus we can trivially enable this feature.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ docs/system/arm/emulation.rst | 38 +++++++++++++++++++++++++++++++++--
- target/arm/cpu64.c            | 1 +
+file changed, 36 insertions(+), 2 deletions(-)
  target/arm/cpu_tcg.c          | 1 +
 files changed, 3 insertions(+)
 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/emulation.rst
 +++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@ Armv8 versions of the A-profile architecture. It also has support for
  the following architecture extensions:
  - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
 +- FEAT_AA32EL0 (Support for AArch32 at EL0)
 +- FEAT_AA32EL1 (Support for AArch32 at EL1)
 +- FEAT_AA32EL2 (Support for AArch32 at EL2)
 +- FEAT_AA32EL3 (Support for AArch32 at EL3)
  - FEAT_AA32HPD (AArch32 hierarchical permission disables)
  - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
 +- FEAT_AA64EL0 (Support for AArch64 at EL0)
 +- FEAT_AA64EL1 (Support for AArch64 at EL1)
 +- FEAT_AA64EL2 (Support for AArch64 at EL2)
 +- FEAT_AA64EL3 (Support for AArch64 at EL3)
 +- FEAT_AdvSIMD (Advanced SIMD Extension)
  - FEAT_AES (AESD and AESE instructions)
 +- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
 +- FEAT_ASID16 (16 bit ASID)
  - FEAT_BBM at level 2 (Translation table break-before-make levels)
  - FEAT_BF16 (AArch64 BFloat16 instructions)
  - FEAT_BTI (Branch Target Identification)
-+- FEAT_CSV2 (Cache speculation variant 2)
++- FEAT_CCIDX (Extended cache index)
  - FEAT_CRC32 (CRC32 instructions)
 +- FEAT_Crypto (Cryptographic Extension)
  - FEAT_CSV2 (Cache speculation variant 2)
  - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
  - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
  - FEAT_DGH (Data gathering hint)
  - FEAT_DIT (Data Independent Timing instructions)
  - FEAT_DPB (DC CVAP instruction)
++- FEAT_DPB2 (DC CVADP instruction)
++- FEAT_Debugv8p1 (Debug with VHE)
  - FEAT_Debugv8p2 (Debug changes for v8.2)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+ - FEAT_Debugv8p4 (Debug changes for v8.4)
-index XXXXXXX..XXXXXXX 100644
+ - FEAT_DotProd (Advanced SIMD dot product instructions)
---- a/target/arm/cpu64.c
+ - FEAT_DoubleFault (Double Fault Extension)
-+++ b/target/arm/cpu64.c
+ - FEAT_E0PD (Preventing EL0 access to halves of address maps)
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+ - FEAT_ECV (Enhanced Counter Virtualization)
-     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
++- FEAT_EL0 (Support for execution at EL0)
-     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
++- FEAT_EL1 (Support for execution at EL1)
-     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
++- FEAT_EL2 (Support for execution at EL2)
-+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
++- FEAT_EL3 (Support for execution at EL3)
-     cpu->isar.id_aa64pfr0 = t;
+ - FEAT_EPAC (Enhanced pointer authentication)
+ - FEAT_ETS (Enhanced Translation Synchronization)
-     t = cpu->isar.id_aa64pfr1;
+ - FEAT_EVT (Enhanced Virtualization Traps)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
++- FEAT_F32MM (Single-precision Matrix Multiplication)
-index XXXXXXX..XXXXXXX 100644
++- FEAT_F64MM (Double-precision Matrix Multiplication)
---- a/target/arm/cpu_tcg.c
+ - FEAT_FCMA (Floating-point complex number instructions)
-+++ b/target/arm/cpu_tcg.c
+ - FEAT_FGT (Fine-Grained Traps)
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+ - FEAT_FHM (Floating-point half-precision multiplication instructions)
-     cpu->isar.id_mmfr4 = t;
++- FEAT_FP (Floating Point extensions)
+ - FEAT_FP16 (Half-precision floating-point data processing)
-     t = cpu->isar.id_pfr0;
+ - FEAT_FPAC (Faulting on AUT* instructions)
-+    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CVS2 */
+ - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
-     t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-     t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
+ - FEAT_LSE (Large System Extensions)
-     cpu->isar.id_pfr0 = t;
+ - FEAT_LSE2 (Large System Extensions v2)
  - FEAT_LVA (Large Virtual Address space)
 +- FEAT_MixedEnd (Mixed-endian support)
 +- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
  - FEAT_MOPS (Standardization of memory operations)
  - FEAT_MTE (Memory Tagging Extension)
  - FEAT_MTE2 (Memory Tagging Extension)
  - FEAT_MTE3 (MTE Asymmetric Fault Handling)
 +- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
  - FEAT_NMI (Non-maskable Interrupt)
  - FEAT_NV (Nested Virtualization)
  - FEAT_NV2 (Enhanced nested virtualization support)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
  - FEAT_PAuth (Pointer authentication)
  - FEAT_PAuth2 (Enhancements to pointer authentication)
  - FEAT_PMULL (PMULL, PMULL2 instructions)
 +- FEAT_PMUv3 (PMU extension version 3)
  - FEAT_PMUv3p1 (PMU Extensions v3.1)
  - FEAT_PMUv3p4 (PMU Extensions v3.4)
  - FEAT_PMUv3p5 (PMU Extensions v3.5)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
  - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
  - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
  - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
 +- FEAT_SVE (Scalable Vector Extension)
 +- FEAT_SVE_AES (Scalable Vector AES instructions)
 +- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
 +- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
 +- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
 +- FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
 +- FEAT_SVE2 (Scalable Vector Extension version 2)
  - FEAT_SPECRES (Speculation restriction instructions)
  - FEAT_SSBS (Speculative Store Bypass Safe)
 +- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
 +- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
 +- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
  - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
  - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
  - FEAT_TLBIRANGE (TLB invalidate range instructions)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
  - FEAT_VHE (Virtualization Host Extensions)
  - FEAT_VMID16 (16-bit VMID)
  - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
 -- SVE (The Scalable Vector Extension)
 -- SVE2 (The Scalable Vector Extension v2)
  For information on the specifics of these extensions, please refer
  to the `Armv8-A Arm Architecture Reference Manual
 --
-.25.1
+.34.1

-[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
+[PULL 05/21] target/arm: Enable FEAT_CSV2_3 for -cpu max
-From: Richard Henderson <richard.henderson@linaro.org>
+FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose
 information about whether branch targets and branch history trained
 in one hardware described context can control speculative execution
 in a different hardware context.
-This extension concerns cache speculation, which TCG does
+There is no branch prediction in TCG, so we don't need to do anything
-not implement.  Thus we can trivially enable this feature.
+to be compliant with this.  Upadte the '-cpu max' ID registers to
 advertise the feature.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org
 ---
  docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 1 +
+ target/arm/tcg/cpu64.c        | 4 ++--
- target/arm/cpu_tcg.c          | 1 +
+files changed, 3 insertions(+), 2 deletions(-)
 files changed, 3 insertions(+)
 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/emulation.rst
 +++ b/docs/system/arm/emulation.rst
 @@ -XXX,XX +XXX,XX @@ the following architecture extensions:
  - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
  - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
  - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
-+- FEAT_CSV3 (Cache speculation variant 3)
++- FEAT_CSV2_3 (Cache speculation variant 2, version 3)
  - FEAT_CSV3 (Cache speculation variant 3)
  - FEAT_DGH (Data gathering hint)
  - FEAT_DIT (Data Independent Timing instructions)
- - FEAT_DPB (DC CVAP instruction)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
  - FEAT_Debugv8p2 (Debug changes for v8.2)
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/target/arm/tcg/cpu64.c
-+++ b/target/arm/cpu64.c
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
      t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
      t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-     t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
+-    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
-+    t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1);      /* FEAT_CSV3 */
++    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3);      /* FEAT_CSV2_3 */
      t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1);      /* FEAT_CSV3 */
      cpu->isar.id_aa64pfr0 = t;
-     t = cpu->isar.id_aa64pfr1;
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
+     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
-index XXXXXXX..XXXXXXX 100644
+     t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0);  /* FEAT_RASv1p1 + FEAT_DoubleFault */
---- a/target/arm/cpu_tcg.c
+     t = FIELD_DP64(t, ID_AA64PFR1, SME, 1);       /* FEAT_SME */
-+++ b/target/arm/cpu_tcg.c
+-    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
++    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
-     cpu->isar.id_pfr0 = t;
+     t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1);       /* FEAT_NMI */
+     cpu->isar.id_aa64pfr1 = t;
      t = cpu->isar.id_pfr2;
 +    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
      t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
      cpu->isar.id_pfr2 = t;
 --
-.25.1
+.34.1

-[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
+[PULL 06/21] target/arm: Enable FEAT_ETS2 for -cpu max
-From: Richard Henderson <richard.henderson@linaro.org>
+FEAT_ETS2 is a tighter set of guarantees about memory ordering
 involving translation table walks than the old FEAT_ETS; FEAT_ETS has
 been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
 now gives no greater guarantees than ETS == 0.
-This feature is AArch64 only, and applies to physical SErrors,
+FEAT_ETS2 requires:
-which QEMU does not implement, thus the feature is a nop.
+ * the virtual address of a load or store that appears in program
    order after a DSB cannot be translated until after the DSB
    completes (section B2.10.9)
  * TLB maintenance operations that only affect translations without
    execute permission are guaranteed complete after a DSB
    (R_BLDZX)
  * if a memory access RW2 is ordered-before memory access RW2,
    then RW1 is also ordered-before any translation table walk
    generated by RW2 that generates a Translation, Address size
    or Access flag fault (R_NNFPF, I_CLGHP)
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+As with FEAT_ETS, QEMU is already compliant, because we do not
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+reorder translation table walk memory accesses relative to other
-Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
+memory accesses, and we always guarantee to have finished TLB
 maintenance as soon as the TLB op is done.
 Update the documentation to list FEAT_ETS2 instead of the
 no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ docs/system/arm/emulation.rst | 2 +-
- target/arm/cpu64.c            | 1 +
+ target/arm/tcg/cpu32.c        | 2 +-
-files changed, 2 insertions(+)
+ target/arm/tcg/cpu64.c        | 2 +-
 files changed, 3 insertions(+), 3 deletions(-)
 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/emulation.rst
 +++ b/docs/system/arm/emulation.rst
 @@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
+ - FEAT_EL2 (Support for execution at EL2)
- - FEAT_HPDS (Hierarchical permission disables)
+ - FEAT_EL3 (Support for execution at EL3)
- - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
+ - FEAT_EPAC (Enhanced pointer authentication)
-+- FEAT_IESB (Implicit error synchronization event)
+-- FEAT_ETS (Enhanced Translation Synchronization)
- - FEAT_JSCVT (JavaScript conversion instructions)
++- FEAT_ETS2 (Enhanced Translation Synchronization)
- - FEAT_LOR (Limited ordering regions)
+ - FEAT_EVT (Enhanced Virtualization Traps)
- - FEAT_LPA (Large Physical Address space)
+ - FEAT_F32MM (Single-precision Matrix Multiplication)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+ - FEAT_F64MM (Double-precision Matrix Multiplication)
 diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/target/arm/tcg/cpu32.c
-+++ b/target/arm/cpu64.c
++++ b/target/arm/tcg/cpu32.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     t = cpu->isar.id_aa64mmfr2;
+     cpu->isar.id_mmfr4 = t;
-     t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
-     t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
+     t = cpu->isar.id_mmfr5;
-+    t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1);     /* FEAT_IESB */
+-    t = FIELD_DP32(t, ID_MMFR5, ETS, 1);          /* FEAT_ETS */
-     t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
++    t = FIELD_DP32(t, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
-     t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
+     cpu->isar.id_mmfr5 = t;
-     t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
      t = cpu->isar.id_pfr0;
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu64.c
 +++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
      t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
      t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1);      /* FEAT_ETS */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2);      /* FEAT_ETS2 */
      t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1);      /* FEAT_HCX */
      t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1);   /* FEAT_TIDCP1 */
      cpu->isar.id_aa64mmfr1 = t;
 --
-.25.1
+.34.1

-[PULL 14/32] target/arm: Add minimal RAS registers
+[PULL 07/21] target/arm: Implement ID_AA64MMFR3_EL1
-From: Richard Henderson <richard.henderson@linaro.org>
+Newer versions of the Arm ARM (e.g.  rev K.a) now define fields for
 ID_AA64MMFR3_EL1.  Implement this register, so that we can set the
 fields if we need to.  There's no behaviour change here since we
 don't currently set the register value to non-zero.
-Add only the system registers required to implement zero error
-records.  This means that all values for ERRSELR are out of range,
-which means that it and all of the indexed error record registers
-need not be implemented.
-Add the EL2 registers required for injecting virtual SError.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
 ---
- target/arm/cpu.h    |  5 +++
+ target/arm/cpu.h     | 17 +++++++++++++++++
- target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
+ target/arm/helper.c  |  6 ++++--
-files changed, 89 insertions(+)
+ target/arm/hvf/hvf.c |  2 ++
  target/arm/kvm.c     |  2 ++
 files changed, 25 insertions(+), 2 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
+         uint64_t id_aa64mmfr0;
-         uint64_t gcr_el1;
+         uint64_t id_aa64mmfr1;
-         uint64_t rgsr_el1;
+         uint64_t id_aa64mmfr2;
 +        uint64_t id_aa64mmfr3;
          uint64_t id_aa64dfr0;
          uint64_t id_aa64dfr1;
          uint64_t id_aa64zfr0;
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
  FIELD(ID_AA64MMFR2, EVT, 56, 4)
  FIELD(ID_AA64MMFR2, E0PD, 60, 4)
 +FIELD(ID_AA64MMFR3, TCRX, 0, 4)
 +FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
 +FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
 +FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
 +FIELD(ID_AA64MMFR3, S1POE, 16, 4)
 +FIELD(ID_AA64MMFR3, S2POE, 20, 4)
 +FIELD(ID_AA64MMFR3, AIE, 24, 4)
 +FIELD(ID_AA64MMFR3, MEC, 28, 4)
 +FIELD(ID_AA64MMFR3, D128, 32, 4)
 +FIELD(ID_AA64MMFR3, D128_2, 36, 4)
 +FIELD(ID_AA64MMFR3, SNERR, 40, 4)
 +FIELD(ID_AA64MMFR3, ANERR, 44, 4)
 +FIELD(ID_AA64MMFR3, SDERR, 52, 4)
 +FIELD(ID_AA64MMFR3, ADERR, 56, 4)
 +FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
 +
-+        /* Minimal RAS registers */
+ FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
-+        uint64_t disr_el1;
+ FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
-+        uint64_t vdisr_el2;
+ FIELD(ID_AA64DFR0, PMUVER, 8, 4)
 +        uint64_t vsesr_el2;
      } cp15;
      struct {
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
-       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
- };
-+/*
-+ * Check for traps to RAS registers, which are controlled
-+ * by HCR_EL2.TERR and SCR_EL3.TERR.
-+ */
-+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
-+                                  bool isread)
-+{
-+    int el = arm_current_el(env);
-+
-+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
-+        return CP_ACCESS_TRAP_EL2;
-+    }
-+    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
-+        return CP_ACCESS_TRAP_EL3;
-+    }
-+    return CP_ACCESS_OK;
-+}
-+
-+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-+{
-+    int el = arm_current_el(env);
-+
-+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
-+        return env->cp15.vdisr_el2;
-+    }
-+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
-+        return 0; /* RAZ/WI */
-+    }
-+    return env->cp15.disr_el1;
-+}
-+
-+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
-+{
-+    int el = arm_current_el(env);
-+
-+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
-+        env->cp15.vdisr_el2 = val;
-+        return;
-+    }
-+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
-+        return; /* RAZ/WI */
-+    }
-+    env->cp15.disr_el1 = val;
-+}
-+
-+/*
-+ * Minimal RAS implementation with no Error Records.
-+ * Which means that all of the Error Record registers:
-+ *   ERXADDR_EL1
-+ *   ERXCTLR_EL1
-+ *   ERXFR_EL1
-+ *   ERXMISC0_EL1
-+ *   ERXMISC1_EL1
-+ *   ERXMISC2_EL1
-+ *   ERXMISC3_EL1
-+ *   ERXPFGCDN_EL1  (RASv1p1)
-+ *   ERXPFGCTL_EL1  (RASv1p1)
-+ *   ERXPFGF_EL1    (RASv1p1)
-+ *   ERXSTATUS_EL1
-+ * and
-+ *   ERRSELR_EL1
-+ * may generate UNDEFINED, which is the effect we get by not
-+ * listing them at all.
-+ */
-+static const ARMCPRegInfo minimal_ras_reginfo[] = {
-+    { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
-+      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
-+      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
-+      .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
-+    { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
-+      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
-+      .access = PL1_R, .accessfn = access_terr,
-+      .type = ARM_CP_CONST, .resetvalue = 0 },
-+    { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
-+      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
-+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
-+    { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
-+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
-+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
-+};
-+
- /* Return the exception level to which exceptions should be taken
-  * via SVEAccessTrap.  If an exception should be routed through
-  * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
 @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-     if (cpu_isar_feature(aa64_ssbs, cpu)) {
+               .access = PL1_R, .type = ARM_CP_CONST,
-         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
+               .accessfn = access_aa64_tid3,
-     }
+               .resetvalue = cpu->isar.id_aa64mmfr2 },
-+    if (cpu_isar_feature(any_ras, cpu)) {
+-            { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
-+        define_arm_cp_regs(cpu, minimal_ras_reginfo);
++            { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64,
-+    }
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
+               .access = PL1_R, .type = ARM_CP_CONST,
-     if (cpu_isar_feature(aa64_vh, cpu) ||
+               .accessfn = access_aa64_tid3,
-         cpu_isar_feature(aa64_debugv8p2, cpu)) {
+-              .resetvalue = 0 },
 +              .resetvalue = cpu->isar.id_aa64mmfr3 },
              { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
                .access = PL1_R, .type = ARM_CP_CONST,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
              { .name = "ID_AA64MMFR2_EL1",
                .exported_bits = R_ID_AA64MMFR2_AT_MASK },
 +            { .name = "ID_AA64MMFR3_EL1",
 +              .exported_bits = 0 },
              { .name = "ID_AA64MMFR*_EL1_RESERVED",
                .is_glob = true },
              { .name = "ID_AA64DFR0_EL1",
 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/hvf/hvf.c
 +++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ static struct hvf_sreg_match hvf_sreg_match[] = {
  #endif
      { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
      { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
 +    /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
      { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
      { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
@@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
          { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
          { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
          { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
 +        /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
      };
      hv_vcpu_t fd;
      hv_return_t r = HV_SUCCESS;
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
                                ARM64_SYS_REG(3, 0, 0, 7, 1));
          err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
                                ARM64_SYS_REG(3, 0, 0, 7, 2));
 +        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3,
 +                              ARM64_SYS_REG(3, 0, 0, 7, 3));
          /*
           * Note that if AArch32 support is not present in the host,
 --
-.25.1
+.34.1

-[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
+[PULL 08/21] target/arm: Enable FEAT_Spec_FPACC for -cpu max
-From: Richard Henderson <richard.henderson@linaro.org>
+FEAT_Spec_FPACC is a feature describing speculative behaviour in the
 event of a PAC authontication failure when FEAT_FPACCOMBINE is
 implemented.  FEAT_Spec_FPACC means that the speculative use of
 pointers processed by a PAC Authentication is not materially
 different in terms of the impact on cached microarchitectural state
 (caches, TLBs, etc) between passing and failing of the PAC
 Authentication.
-This extension concerns not merging memory access, which TCG does
+QEMU doesn't do speculative execution, so we can advertise
-not implement.  Thus we can trivially enable this feature.
+this feature.
 Add a comment to handle_hint for the DGH instruction, but no code.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org
 ---
  docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 1 +
+ target/arm/tcg/cpu64.c        | 4 ++++
- target/arm/translate-a64.c    | 1 +
+files changed, 5 insertions(+)
 files changed, 3 insertions(+)
 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/emulation.rst
 +++ b/docs/system/arm/emulation.rst
 @@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+ - FEAT_FP16 (Half-precision floating-point data processing)
- - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
+ - FEAT_FPAC (Faulting on AUT* instructions)
- - FEAT_CSV3 (Cache speculation variant 3)
+ - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
-+- FEAT_DGH (Data gathering hint)
++- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions)
- - FEAT_DIT (Data Independent Timing instructions)
+ - FEAT_FRINTTS (Floating-point to integer instructions)
- - FEAT_DPB (DC CVAP instruction)
+ - FEAT_FlagM (Flag manipulation instructions v2)
- - FEAT_Debugv8p2 (Debug changes for v8.2)
+ - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/target/arm/tcg/cpu64.c
-+++ b/target/arm/cpu64.c
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
-     t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
+     t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1);     /* FEAT_E0PD */
-     t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
+     cpu->isar.id_aa64mmfr2 = t;
-     t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1);      /* FEAT_DGH */
++    t = cpu->isar.id_aa64mmfr3;
-     t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
++    t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
-     cpu->isar.id_aa64isar1 = t;
++    cpu->isar.id_aa64mmfr3 = t;
++
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+     t = cpu->isar.id_aa64zfr0;
-index XXXXXXX..XXXXXXX 100644
+     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
---- a/target/arm/translate-a64.c
+     t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
          break;
      case 0b00100: /* SEV */
      case 0b00101: /* SEVL */
 +    case 0b00110: /* DGH */
          /* we treat all as NOP at least for now */
          break;
      case 0b00111: /* XPACLRI */
 --
-.25.1
+.34.1

-[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
+[PULL 09/21] tests/avocado: update sunxi kernel from armbian to 6.6.16
-From: Gavin Shan <gshan@redhat.com>
+The Linux kernel 5.10.16 binary for sunxi has been removed from
 apt.armbian.com. This means that the avocado tests for these machines
 will be skipped (status CANCEL) if the old binary isn't present in
 the avocado cache.
-In aarch64_numa_cpu(), the CPU and NUMA association is something
+Update to 6.6.16, in the same way we did in commit e384db41d8661
-like below. Two threads in the same core/cluster/socket are
+when we moved to 5.10.16 in 2021.
 associated with two individual NUMA nodes, which is unreal as
 Igor Mammedov mentioned. We don't expect the association to break
 NUMA-to-socket boundary, which matches with the real world.
-    NUMA-node  socket  cluster   core   thread
+Cc: qemu-stable@nongnu.org
-    ------------------------------------------
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284
-0        0        0      0
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-0        0        0      1
+Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
 Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
 Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org
 ---
  tests/avocado/boot_linux_console.py | 70 ++++++++++++++---------------
  tests/avocado/replay_kernel.py      |  8 ++--
 files changed, 39 insertions(+), 39 deletions(-)
-This corrects the topology for CPUs and their association with
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
 NUMA nodes. After this patch is applied, the CPU and NUMA
 association becomes something like below, which looks real.
 Besides, socket/cluster/core/thread IDs are all checked when
 the NUMA node IDs are verified. It helps to check if the CPU
 topology is properly populated or not.
     NUMA-node  socket  cluster   core   thread
     ------------------------------------------
 1        0        0       0
 0        0        0       0
 Suggested-by: Igor Mammedov <imammedo@redhat.com>
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Acked-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20220503140304.855514-5-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/qtest/numa-test.c | 18 ++++++++++++------
 file changed, 12 insertions(+), 6 deletions(-)
 diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/numa-test.c
+--- a/tests/avocado/boot_linux_console.py
-+++ b/tests/qtest/numa-test.c
++++ b/tests/avocado/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
+@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
-     g_autofree char *cli = NULL;
+         :avocado: tags=accel:tcg
+         """
-     cli = make_cli(data, "-machine "
+         deb_url = ('https://apt.armbian.com/pool/main/l/'
--        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-+        "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
+-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
-         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
++                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
--        "-numa cpu,node-id=1,thread-id=0 "
++        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
--        "-numa cpu,node-id=0,thread-id=1");
+         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
-+        "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
+         kernel_path = self.extract_from_deb(deb_path,
-+        "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
+-                                            '/boot/vmlinuz-5.10.16-sunxi')
-     qts = qtest_init(cli);
+-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
-     cpus = get_cpus(qts, &resp);
++                                            '/boot/vmlinuz-6.6.16-current-sunxi')
-     g_assert(cpus);
++        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
+         dtb_path = self.extract_from_deb(deb_path, dtb_path)
-     while ((e = qlist_pop(cpus))) {
+         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
-         QDict *cpu, *props;
+                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
--        int64_t thread, node;
+@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
-+        int64_t socket, cluster, core, thread, node;
+         :avocado: tags=accel:tcg
+         """
-         cpu = qobject_to(QDict, e);
+         deb_url = ('https://apt.armbian.com/pool/main/l/'
-         g_assert(qdict_haskey(cpu, "props"));
+-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
+-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
++                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
-         g_assert(qdict_haskey(props, "node-id"));
++        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
-         node = qdict_get_int(props, "node-id");
+         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
-+        g_assert(qdict_haskey(props, "socket-id"));
+         kernel_path = self.extract_from_deb(deb_path,
-+        socket = qdict_get_int(props, "socket-id");
+-                                            '/boot/vmlinuz-5.10.16-sunxi')
-+        g_assert(qdict_haskey(props, "cluster-id"));
+-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
-+        cluster = qdict_get_int(props, "cluster-id");
++                                            '/boot/vmlinuz-6.6.16-current-sunxi')
-+        g_assert(qdict_haskey(props, "core-id"));
++        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
-+        core = qdict_get_int(props, "core-id");
+         dtb_path = self.extract_from_deb(deb_path, dtb_path)
-         g_assert(qdict_haskey(props, "thread-id"));
+         rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
-         thread = qdict_get_int(props, "thread-id");
+                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u(self):
--        if (thread == 0) {
+         :avocado: tags=machine:bpim2u
-+        if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
+         :avocado: tags=accel:tcg
-             g_assert_cmpint(node, ==, 1);
+         """
--        } else if (thread == 1) {
+-        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
-+        } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
+-                   'linux-image-current-sunxi_21.02.2_armhf.deb')
-             g_assert_cmpint(node, ==, 0);
+-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
-         } else {
++        deb_url = ('https://apt.armbian.com/pool/main/l/'
-             g_assert(false);
++                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                      'sun8i-r40-bananapi-m2-ultra.dtb')
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_initrd(self):
          :avocado: tags=accel:tcg
          :avocado: tags=machine:bpim2u
          """
 -        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
 -                   'linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +        deb_url = ('https://apt.armbian.com/pool/main/l/'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                      'sun8i-r40-bananapi-m2-ultra.dtb')
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_gmac(self):
          """
          self.require_netdev('user')
 -        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
 -                   'linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +        deb_url = ('https://apt.armbian.com/pool/main/l/'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                      'sun8i-r40-bananapi-m2-ultra.dtb')
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self):
          :avocado: tags=accel:tcg
          """
          deb_url = ('https://apt.armbian.com/pool/main/l/'
 -                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          self.vm.set_console()
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self):
          :avocado: tags=machine:orangepi-pc
          """
          deb_url = ('https://apt.armbian.com/pool/main/l/'
 -                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                        '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
          self.require_netdev('user')
          deb_url = ('https://apt.armbian.com/pool/main/l/'
 -                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
                        'buildroot-baseline/20221116.0/armel/rootfs.ext2.xz')
 diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/replay_kernel.py
 +++ b/tests/avocado/replay_kernel.py
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
          :avocado: tags=machine:cubieboard
          """
          deb_url = ('https://apt.armbian.com/pool/main/l/'
 -                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                        '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
 --
-.25.1
+.34.1

-[PULL 16/32] target/arm: Implement virtual SError exceptions
+[PULL 10/21] target/arm: Refactor default generic timer frequency handling
-From: Richard Henderson <richard.henderson@linaro.org>
+The generic timer frequency is settable by board code via a QOM
 property "cntfrq", but otherwise defaults to 62.5MHz.  The way this
 is done includes some complication resulting from how this was
 originally a fixed value with no QOM property.  Clean it up:
-Virtual SError exceptions are raised by setting HCR_EL2.VSE,
+ * always set cpu->gt_cntfrq_hz to some sensible value, whether
-and are routed to EL1 just like other virtual exceptions.
+   the CPU has the generic timer or not, and whether it's system
    or user-only emulation
  * this means we can always use gt_cntfrq_hz, and never need
    the old GTIMER_SCALE define
  * set the default value in exactly one place, in the realize fn
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+The aim here is to pave the way for handling the ARMv8.6 requirement
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+that the generic timer frequency is always 1GHz.  We're going to do
-Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
+that by having old CPU types keep their legacy-in-QEMU behaviour and
 having the default for any new CPU types be a 1GHz rather han 62.5MHz
 cntfrq, so we want the point where the default is decided to be in
 one place, and in code, not in a DEFINE_PROP_UINT64() initializer.
 This commit should have no behavioural changes.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
 ---
- target/arm/cpu.h       |  2 ++
+ target/arm/internals.h |  7 ++++---
- target/arm/internals.h |  8 ++++++++
+ target/arm/cpu.c       | 31 +++++++++++++++++--------------
- target/arm/syndrome.h  |  5 +++++
+ target/arm/helper.c    | 16 ++++++++--------
- target/arm/cpu.c       | 38 +++++++++++++++++++++++++++++++++++++-
+files changed, 29 insertions(+), 25 deletions(-)
  target/arm/helper.c    | 40 +++++++++++++++++++++++++++++++++++++++-
 files changed, 91 insertions(+), 2 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
- #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
- #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
- #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
-+#define EXCP_VSERR          24
- /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
- #define ARMV7M_EXCP_RESET   1
-@@ -XXX,XX +XXX,XX @@ enum {
- #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
- #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
- #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
-+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
- /* The usual mapping for an AArch64 system register to its AArch32
-  * counterpart is for the 32 bit world to have access to the lower
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
+@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
          || excp == EXCP_SEMIHOST;
  }
 -/* Scale factor for generic timers, ie number of ns per tick.
 - * This gives a 62.5MHz timer.
 +/*
 + * Default frequency for the generic timer, in Hz.
 + * This is 62.5MHz, which gives a 16 ns tick period.
   */
- void arm_cpu_update_vfiq(ARMCPU *cpu);
+-#define GTIMER_SCALE 16
++#define GTIMER_DEFAULT_HZ 62500000
-+/**
-+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
+ /* Bit definitions for the v7M CONTROL register */
-+ *
+ FIELD(V7M_CONTROL, NPRIV, 0, 1)
 + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
 + * following a change to the HCR_EL2.VSE bit.
 + */
 +void arm_cpu_update_vserr(ARMCPU *cpu);
 +
  /**
   * arm_mmu_idx_el:
   * @env: The cpu environment
 diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/syndrome.h
 +++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
      return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
  }
 +static inline uint32_t syn_serror(uint32_t extra)
 +{
 +    return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
 +}
 +
  #endif /* TARGET_ARM_SYNDROME_H */
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
      return (cpu->power_state != PSCI_OFF)
          && cs->interrupt_request &
          (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
 -         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
 +         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
           | CPU_INTERRUPT_EXITTB);
  }
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
              return false;
          }
          return !(env->daif & PSTATE_I);
 +    case EXCP_VSERR:
 +        if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
 +            /* VIRQs are only taken when hypervized.  */
 +            return false;
 +        }
 +        return !(env->daif & PSTATE_A);
      default:
          g_assert_not_reached();
      }
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
              goto found;
          }
      }
 +    if (interrupt_request & CPU_INTERRUPT_VSERR) {
 +        excp_idx = EXCP_VSERR;
 +        target_el = 1;
 +        if (arm_excp_unmasked(cs, excp_idx, target_el,
 +                              cur_el, secure, hcr_el2)) {
 +            /* Taking a virtual abort clears HCR_EL2.VSE */
 +            env->cp15.hcr_el2 &= ~HCR_VSE;
 +            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
 +            goto found;
 +        }
 +    }
      return false;
   found:
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
      }
  }
-+void arm_cpu_update_vserr(ARMCPU *cpu)
++/*
-+{
++ * 0 means "unset, use the default value". That default might vary depending
-+    /*
++ * on the CPU type, and is set in the realize fn.
-+     * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
++ */
-+     */
+ static Property arm_cpu_gt_cntfrq_property =
-+    CPUARMState *env = &cpu->env;
+-            DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
-+    CPUState *cs = CPU(cpu);
+-                               NANOSECONDS_PER_SECOND / GTIMER_SCALE);
-+
++            DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
-+    bool new_state = env->cp15.hcr_el2 & HCR_VSE;
-+
+ static Property arm_cpu_reset_cbar_property =
-+    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
+             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
-+        if (new_state) {
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-+            cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
+         return;
-+        } else {
+     }
-+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
-+        }
++    if (!cpu->gt_cntfrq_hz) {
 +        /*
 +         * 0 means "the board didn't set a value, use the default".
 +         * The default value of the generic timer frequency (as seen in
 +         * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
 +         * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
 +         * board doesn't set it.
 +         */
 +        cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
 +    }
-+}
 +
  #ifndef CONFIG_USER_ONLY
- static void arm_cpu_set_irq(void *opaque, int irq, int level)
+     /* The NVIC and M-profile CPU are two halves of a single piece of
- {
+      * hardware; trying to use one without the other is a command line
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      }
      {
 -        uint64_t scale;
 -
 -        if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
 -            if (!cpu->gt_cntfrq_hz) {
 -                error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
 -                           cpu->gt_cntfrq_hz);
 -                return;
 -            }
 -            scale = gt_cntfrq_period_ns(cpu);
 -        } else {
 -            scale = GTIMER_SCALE;
 -        }
 +        uint64_t scale = gt_cntfrq_period_ns(cpu);
          cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
                                                 arm_gt_ptimer_cb, cpu);
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
-         }
+       .resetvalue = 0 },
-     }
+ };
--    /* External aborts are not possible in QEMU so A bit is always clear */
++static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
-+    if (hcr_el2 & HCR_AMO) {
++{
-+        if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
++    ARMCPU *cpu = env_archcpu(env);
 +            ret |= CPSR_A;
 +        }
 +    }
 +
-     return ret;
++    cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
 +}
 +
  #ifndef CONFIG_USER_ONLY
  static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ void arm_gt_hvtimer_cb(void *opaque)
      gt_recalc_timer(cpu, GTIMER_HYPVIRT);
  }
-@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
+-static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
-     g_assert(qemu_mutex_iothread_locked());
+-{
-     arm_cpu_update_virq(cpu);
+-    ARMCPU *cpu = env_archcpu(env);
-     arm_cpu_update_vfiq(cpu);
+-
-+    arm_cpu_update_vserr(cpu);
+-    cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
- }
+-}
+-
- static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
-@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
+     /*
-             [EXCP_LSERR] = "v8M LSERR UsageFault",
+      * Note that CNTFRQ is purely reads-as-written for the benefit
-             [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
-             [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
+       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
-+            [EXCP_VSERR] = "Virtual SERR",
+       .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
-         };
+       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
+-      .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
-         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
++      .resetfn = arm_gt_cntfrq_reset,
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
+     },
-         mask = CPSR_A | CPSR_I | CPSR_F;
+     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
-         offset = 4;
+       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
          break;
 +    case EXCP_VSERR:
 +        {
 +            /*
 +             * Note that this is reported as a data abort, but the DFAR
 +             * has an UNKNOWN value.  Construct the SError syndrome from
 +             * AET and ExT fields.
 +             */
 +            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
 +
 +            if (extended_addresses_enabled(env)) {
 +                env->exception.fsr = arm_fi_to_lfsc(&fi);
 +            } else {
 +                env->exception.fsr = arm_fi_to_sfsc(&fi);
 +            }
 +            env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
 +            A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
 +            qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
 +                          env->exception.fsr);
 +
 +            new_mode = ARM_CPU_MODE_ABT;
 +            addr = 0x10;
 +            mask = CPSR_A | CPSR_I;
 +            offset = 8;
 +        }
 +        break;
      case EXCP_SMC:
          new_mode = ARM_CPU_MODE_MON;
          addr = 0x08;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
      case EXCP_VFIQ:
          addr += 0x100;
          break;
 +    case EXCP_VSERR:
 +        addr += 0x180;
 +        /* Construct the SError syndrome from IDS and ISS fields. */
 +        env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
 +        env->cp15.esr_el[new_el] = env->exception.syndrome;
 +        break;
      default:
          cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
      }
 --
-.25.1
+.34.1

-[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
+[PULL 11/21] hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
-From: Leif Lindholm <quic_llindhol@quicinc.com>
+Currently QEMU CPUs always run with a generic timer counter frequency
 of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz.  For older versions of
 the TF-A firmware that sbsa-ref runs, the frequency of the generic
 timer is hardcoded into the firmware, and so if the CPU actually has
 a different frequency then timers in the guest will be set
 incorrectly.
-The sbsa-ref machine is continuously evolving. Some of the changes we
+The default frequency used by the 'max' CPU is about to change, so
-want to make in the near future, to align with real components (e.g.
+make the sbsa-ref board force the CPU frequency to the value which
-the GIC-700), will break compatibility for existing firmware.
+the firmware expects.
-Introduce two new properties to the DT generated on machine generation:
+Newer versions of TF-A will read the frequency from the CPU's
-- machine-version-major
+CNTFRQ_EL0 register:
-  To be incremented when a platform change makes the machine
+ https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148
-  incompatible with existing firmware.
+so in the longer term we could make this board use the 1GHz
-- machine-version-minor
+frequency. We will need to make sure we update the binaries used
-  To be incremented when functionality is added to the machine
+by our avocado test
-  without causing incompatibility with existing firmware.
+ Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
-  to be reset to 0 when machine-version-major is incremented.
+before we can do that.
-This versioning scheme is *neither*:
-- A QEMU versioned machine type; a given version of QEMU will emulate
-  a given version of the platform.
-- A reflection of level of SBSA (now SystemReady SR) support provided.
-The version will increment on guest-visible functional changes only,
-akin to a revision ID register found on a physical platform.
-These properties are both introduced with the value 0.
-(Hence, a machine where the DT is lacking these nodes is equivalent
-to version 0.0.)
-Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
-Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
-Cc: Peter Maydell <peter.maydell@linaro.org>
-Cc: Radoslaw Biernacki <rad@semihalf.com>
-Cc: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
+Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
 ---
- hw/arm/sbsa-ref.c | 14 ++++++++++++++
+ hw/arm/sbsa-ref.c | 15 +++++++++++++++
-file changed, 14 insertions(+)
+file changed, 15 insertions(+)
 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/sbsa-ref.c
 +++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
+@@ -XXX,XX +XXX,XX @@
-     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
+ #define NUM_SMMU_IRQS   4
-     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
+ #define NUM_SATA_PORTS  6
-+    /*
++/*
-+     * This versioning scheme is for informing platform fw only. It is neither:
++ * Generic timer frequency in Hz (which drives both the CPU generic timers
-+     * - A QEMU versioned machine type; a given version of QEMU will emulate
++ * and the SBSA watchdog-timer). Older versions of the TF-A firmware
-+     *   a given version of the platform.
++ * typically used with sbsa-ref (including the binaries in our Avocado test
-+     * - A reflection of level of SBSA (now SystemReady SR) support provided.
++ * Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
-+     *
++ * assume it is this value.
-+     * machine-version-major: updated when changes breaking fw compatibility
++ *
-+     *                        are introduced.
++ * TODO: this value is not architecturally correct for an Armv8.6 or
-+     * machine-version-minor: updated when features are added that don't break
++ * better CPU, so we should move to 1GHz once the TF-A fix above has
-+     *                        fw compatibility.
++ * made it into a release and into our Avocado test.
-+     */
++ */
-+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
++#define SBSA_GTIMER_HZ 62500000
 +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
 +
-     if (ms->numa_state->have_numa_distance) {
+ enum {
-         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
+     SBSA_FLASH,
-         uint32_t *matrix = g_malloc0(size);
+     SBSA_MEM,
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
                                      &error_abort);
          }
 +        object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort);
 +
          object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
                                   &error_abort);
 --
-.25.1
+.34.1

-[PULL 25/32] target/arm: Define neoverse-n1
+[PULL 12/21] hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
-From: Richard Henderson <richard.henderson@linaro.org>
+Currently the sbsa_gdwt watchdog device hardcodes its frequency at
 .5MHz. In real hardware, this watchdog is supposed to be driven
 from the system counter, which also drives the CPU generic timers.
 Newer CPU types (in particular from Armv8.6) should have a CPU
 generic timer frequency of 1GHz, so we can't leave the watchdog
 on the old QEMU default of 62.5GHz.
-Enable the n1 for virt and sbsa board use.
+Make the frequency a QOM property so it can be set by the board,
 and have our only board that uses this device set that frequency
 to the same value it sets the CPU frequency.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
 ---
- docs/system/arm/virt.rst |  1 +
+ include/hw/watchdog/sbsa_gwdt.h |  3 +--
- hw/arm/sbsa-ref.c        |  1 +
+ hw/arm/sbsa-ref.c               |  1 +
- hw/arm/virt.c            |  1 +
+ hw/watchdog/sbsa_gwdt.c         | 15 ++++++++++++++-
- target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
+files changed, 16 insertions(+), 3 deletions(-)
 files changed, 69 insertions(+)
-diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
+diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/virt.rst
+--- a/include/hw/watchdog/sbsa_gwdt.h
-+++ b/docs/system/arm/virt.rst
++++ b/include/hw/watchdog/sbsa_gwdt.h
-@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
+@@ -XXX,XX +XXX,XX @@
- - ``cortex-a76`` (64-bit)
+ #define SBSA_GWDT_RMMIO_SIZE 0x1000
- - ``a64fx`` (64-bit)
+ #define SBSA_GWDT_CMMIO_SIZE 0x1000
- - ``host`` (with KVM only)
-+- ``neoverse-n1`` (64-bit)
+-#define SBSA_TIMER_FREQ      62500000 /* Hz */
- - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
+-
+ typedef struct SBSA_GWDTState {
- Note that the default is ``cortex-a15``, so for an AArch64 guest you must
+     /* <private> */
      SysBusDevice parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct SBSA_GWDTState {
      qemu_irq irq;
      QEMUTimer *timer;
 +    uint64_t freq;
      uint32_t id;
      uint32_t wcs;
 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/sbsa-ref.c
 +++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
+@@ -XXX,XX +XXX,XX @@ static void create_wdt(const SBSAMachineState *sms)
-     ARM_CPU_TYPE_NAME("cortex-a57"),
+     SysBusDevice *s = SYS_BUS_DEVICE(dev);
-     ARM_CPU_TYPE_NAME("cortex-a72"),
+     int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
-     ARM_CPU_TYPE_NAME("cortex-a76"),
-+    ARM_CPU_TYPE_NAME("neoverse-n1"),
++    qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ);
-     ARM_CPU_TYPE_NAME("max"),
+     sysbus_realize_and_unref(s, &error_fatal);
- };
+     sysbus_mmio_map(s, 0, rbase);
+     sysbus_mmio_map(s, 1, cbase);
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/hw/watchdog/sbsa_gwdt.c
-+++ b/hw/arm/virt.c
++++ b/hw/watchdog/sbsa_gwdt.c
-@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
+@@ -XXX,XX +XXX,XX @@
-     ARM_CPU_TYPE_NAME("cortex-a72"),
+ #include "qemu/osdep.h"
-     ARM_CPU_TYPE_NAME("cortex-a76"),
+ #include "sysemu/reset.h"
-     ARM_CPU_TYPE_NAME("a64fx"),
+ #include "sysemu/watchdog.h"
-+    ARM_CPU_TYPE_NAME("neoverse-n1"),
++#include "hw/qdev-properties.h"
-     ARM_CPU_TYPE_NAME("host"),
+ #include "hw/watchdog/sbsa_gwdt.h"
-     ARM_CPU_TYPE_NAME("max"),
+ #include "qemu/timer.h"
- };
+ #include "migration/vmstate.h"
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
-index XXXXXXX..XXXXXXX 100644
+         timeout = s->woru;
---- a/target/arm/cpu64.c
+         timeout <<= 32;
-+++ b/target/arm/cpu64.c
+         timeout |= s->worl;
-@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
+-        timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
-     cpu->isar.mvfr2 = 0x00000043;
++        timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, s->freq);
          timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
          if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
                  dev);
  }
-+static void aarch64_neoverse_n1_initfn(Object *obj)
++static Property wdt_sbsa_gwdt_props[] = {
-+{
++    /*
-+    ARMCPU *cpu = ARM_CPU(obj);
++     * Timer frequency in Hz. This must match the frequency used by
 +     * the CPU's generic timer. Default 62.5Hz matches QEMU's legacy
 +     * CPU timer frequency default.
 +     */
 +    DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq,
 +                       62500000),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
-+    cpu->dtb_compatible = "arm,neoverse-n1";
+ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444c004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0c1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.23 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
 +
 +    /* From B2.98 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +}
 +
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
  {
-     /*
+     DeviceClass *dc = DEVICE_CLASS(klass);
-@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
+@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
-     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
+     set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
-     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
+     dc->vmsd = &vmstate_sbsa_gwdt;
-     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+     dc->desc = "SBSA-compliant generic watchdog device";
-+    { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
++    device_class_set_props(dc, wdt_sbsa_gwdt_props);
-     { .name = "max",                .initfn = aarch64_max_initfn },
+ }
- #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-     { .name = "host",               .initfn = aarch64_host_initfn },
+ static const TypeInfo wdt_sbsa_gwdt_info = {
 --
-.25.1
+.34.1

-[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
+[PULL 13/21] target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
-From: Richard Henderson <richard.henderson@linaro.org>
+In previous versions of the Arm architecture, the frequency of the
+generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
-There is no branch prediction in TCG, therefore there is no
+and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
-need to actually include the context number into the predictor.
+In Armv8.6, the architecture standardized this frequency to 1GHz.
-Therefore all we need to do is add the state for SCXTNUM_ELx.
+Because there is no ID register feature field that indicates whether
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+a CPU is v8.6 or that it ought to have this counter frequency, we
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+implement this by changing our default CNTFRQ value for all CPUs,
-Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
+with exceptions for backwards compatibility:
  * CPU types which we already implement will retain the old
    default value. None of these are v8.6 CPUs, so this is
    architecturally OK.
  * CPUs used in versioned machine types with a version of 9.0
    or earlier will retain the old default value.
 The upshot is that the only CPU type that changes is 'max'; but any
 new type we add in future (whether v8.6 or not) will also get the new
 GHz default.
 It remains the case that the machine model can override the default
 value via the 'cntfrq' QOM property (regardless of the CPU type).
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst |  3 ++
+ target/arm/cpu.h       | 11 +++++++++++
- target/arm/cpu.h              | 16 +++++++++
+ target/arm/internals.h | 12 ++++++++++--
- target/arm/cpu.c              |  5 +++
+ hw/core/machine.c      |  4 +++-
- target/arm/cpu64.c            |  3 +-
+ target/arm/cpu.c       | 23 +++++++++++++++++------
- target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
+ target/arm/cpu64.c     |  2 ++
-files changed, 86 insertions(+), 2 deletions(-)
+ target/arm/tcg/cpu32.c |  4 ++++
+ target/arm/tcg/cpu64.c | 18 ++++++++++++++++++
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+files changed, 65 insertions(+), 9 deletions(-)
-index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/emulation.rst
 +++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
  - FEAT_BF16 (AArch64 BFloat16 instructions)
  - FEAT_BTI (Branch Target Identification)
  - FEAT_CSV2 (Cache speculation variant 2)
 +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
 +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
 +- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
  - FEAT_DIT (Data Independent Timing instructions)
  - FEAT_DPB (DC CVAP instruction)
  - FEAT_Debugv8p2 (Debug changes for v8.2)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-         ARMPACKey apdb;
+      */
-         ARMPACKey apga;
+     bool host_cpu_probe_failed;
-     } keys;
 +    /* QOM property to indicate we should use the back-compat CNTFRQ default */
 +    bool backcompat_cntfrq;
 +
-+    uint64_t scxtnum_el[4];
+     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
- #endif
+      * register.
+      */
- #if defined(CONFIG_USER_ONLY)
+@@ -XXX,XX +XXX,XX @@ enum arm_features {
-@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
+     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
- #define SCTLR_WXN     (1U << 19)
+     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
- #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
+     ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
- #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
++    /*
-+#define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
++     * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
- #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
++     * if the board doesn't set a value, instead of 1GHz. It is for backwards
- #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
++     * compatibility and used only with CPU definitions that were already
- #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
++     * in QEMU before we changed the default. It should not be set on any
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
++     * CPU types added in future.
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
++     */
- }
++    ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
+ };
-+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
-+{
+ static inline int arm_feature(CPUARMState *env, int feature)
-+    int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
+diff --git a/target/arm/internals.h b/target/arm/internals.h
-+    if (key >= 2) {
+index XXXXXXX..XXXXXXX 100644
-+        return true;      /* FEAT_CSV2_2 */
+--- a/target/arm/internals.h
-+    }
++++ b/target/arm/internals.h
-+    if (key == 1) {
+@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
-+        key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
-+        return key >= 2;  /* FEAT_CSV2_1p2 */
+ /*
-+    }
+  * Default frequency for the generic timer, in Hz.
-+    return false;
+- * This is 62.5MHz, which gives a 16 ns tick period.
-+}
++ * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
-+
++ * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
- static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
++ * which gives a 16ns tick period.
- {
++ *
-     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
++ * We will use the back-compat value:
 + *  - for QEMU CPU types added before we standardized on 1GHz
 + *  - for versioned machine types with a version of 9.0 or earlier
 + * In any case, the machine model may override via the cntfrq property.
   */
 -#define GTIMER_DEFAULT_HZ 62500000
 +#define GTIMER_DEFAULT_HZ 1000000000
 +#define GTIMER_BACKCOMPAT_HZ 62500000
  /* Bit definitions for the v7M CONTROL register */
  FIELD(V7M_CONTROL, NPRIV, 0, 1)
 diff --git a/hw/core/machine.c b/hw/core/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/machine.c
 +++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/virtio/virtio-iommu.h"
  #include "audio/audio.h"
 -GlobalProperty hw_compat_9_0[] = {};
 +GlobalProperty hw_compat_9_0[] = {
 +    {"arm-cpu", "backcompat-cntfrq", "true" },
 +};
  const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0);
  GlobalProperty hw_compat_8_2[] = {
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-              */
-             env->cp15.gcr_el1 = 0x1ffff;
+     if (!cpu->gt_cntfrq_hz) {
-         }
+         /*
-+        /*
+-         * 0 means "the board didn't set a value, use the default".
-+         * Disable access to SCXTNUM_EL0 from CSV2_1p2.
+-         * The default value of the generic timer frequency (as seen in
-+         * This is not yet exposed from the Linux kernel in any way.
+-         * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
-+         */
+-         * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
-+        env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
+-         * board doesn't set it.
- #else
++         * 0 means "the board didn't set a value, use the default". (We also
-         /* Reset into the highest available EL */
++         * get here for the CONFIG_USER_ONLY case.)
-         if (arm_feature(env, ARM_FEATURE_EL3)) {
++         * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
 +         * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
 +         * which gives a 16ns tick period.
 +         *
 +         * We will use the back-compat value:
 +         *  - for QEMU CPU types added before we standardized on 1GHz
 +         *  - for versioned machine types with a version of 9.0 or earlier
           */
 -        cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
 +        if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
 +            cpu->backcompat_cntfrq) {
 +            cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
 +        } else {
 +            cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
 +        }
      }
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_properties[] = {
                          mp_affinity, ARM64_AFFINITY_INVALID),
      DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
      DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
 +    /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
 +    DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
      DEFINE_PROP_END_OF_LIST()
  };
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
-     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+     set_feature(&cpu->env, ARM_FEATURE_V8);
-     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
--    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-     cpu->isar.id_aa64pfr0 = t;
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-     t = cpu->isar.id_aa64pfr1;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+     set_feature(&cpu->env, ARM_FEATURE_V8);
-      * we do for EL2 with the virtualization=on property.
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-      */
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-+    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-     cpu->isar.id_aa64pfr1 = t;
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-     t = cpu->isar.id_aa64mmfr0;
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu32.c
---- a/target/arm/helper.c
++++ b/target/arm/tcg/cpu32.c
-+++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
-@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-         if (cpu_isar_feature(aa64_mte, cpu)) {
+     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
-             valid_mask |= SCR_ATA;
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-         }
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
-+            valid_mask |= SCR_ENSCXT;
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-+        }
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-     } else {
+@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
-         valid_mask &= ~(SCR_RW | SCR_ST);
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-         if (cpu_isar_feature(aa32_ras, cpu)) {
+     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
-@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-         if (cpu_isar_feature(aa64_mte, cpu)) {
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-             valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
+     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
-         }
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-+            valid_mask |= HCR_ENSCXT;
+@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
-+        }
+     set_feature(&cpu->env, ARM_FEATURE_PMSA);
-     }
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-     /* Clear RES0 bits.  */
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-         { K(3, 0,  5, 6, 0), K(3, 4,  5, 6, 0), K(3, 5, 5, 6, 0),
+     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
-           "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
+     cpu->midr = 0x411fd133; /* r1p3 */
+@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
-+        { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
+     set_feature(&cpu->env, ARM_FEATURE_V8);
-+          "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-+          isar_feature_aa64_scxtnum },
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
      set_feature(&cpu->env, ARM_FEATURE_EL3);
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu64.c
 +++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a55_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
      set_feature(&cpu->env, ARM_FEATURE_EL3);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n2_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      uint64_t t;
      uint32_t u;
 +    /*
 +     * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
 +     * to because we started with aarch64_a57_initfn(). A 'max' CPU might
 +     * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and
 +     * because it is our "may change" CPU type we are OK with it not being
 +     * backwards-compatible with how it worked in old QEMU.
 +     */
 +    unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
 +
-         /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
+     /*
-         /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
+      * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
-     };
+      * one and try to apply errata workarounds or use impdef features we
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
      },
  };
 -#endif
 +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                     bool isread)
 +{
 +    uint64_t hcr = arm_hcr_el2_eff(env);
 +    int el = arm_current_el(env);
 +
 +    if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
 +        if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
 +            if (hcr & HCR_TGE) {
 +                return CP_ACCESS_TRAP_EL2;
 +            }
 +            return CP_ACCESS_TRAP;
 +        }
 +    } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
 +        return CP_ACCESS_TRAP_EL2;
 +    }
 +    if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
 +        return CP_ACCESS_TRAP_EL2;
 +    }
 +    if (el < 3
 +        && arm_feature(env, ARM_FEATURE_EL3)
 +        && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
 +        return CP_ACCESS_TRAP_EL3;
 +    }
 +    return CP_ACCESS_OK;
 +}
 +
 +static const ARMCPRegInfo scxtnum_reginfo[] = {
 +    { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL0_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
 +    { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL1_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
 +    { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL2_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
 +    { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL3_RW,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
 +};
 +#endif /* TARGET_AARCH64 */
  static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
                                       bool isread)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
          define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
      }
 +
 +    if (cpu_isar_feature(aa64_scxtnum, cpu)) {
 +        define_arm_cp_regs(cpu, scxtnum_reginfo);
 +    }
  #endif
      if (cpu_isar_feature(any_predinv, cpu)) {
 --
-.25.1
+.34.1

-[PULL 27/32] qapi/machine.json: Add cluster-id
+[PULL 14/21] hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
-From: Gavin Shan <gshan@redhat.com>
+From: Alexandra Diupina <adiupina@astralinux.ru>
-This adds cluster-id in CPU instance properties, which will be used
+The DMA descriptor structures for this device have
-by arm/virt machine. Besides, the cluster-id is also verified or
+a set of "address extension" fields which extend the 32
-dumped in various spots:
+bit source addresses with an extra 16 bits to give a
 bit address:
  https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field
-  * hw/core/machine.c::machine_set_cpu_numa_node() to associate
+However, we misimplemented this address extension in several ways:
-    CPU with its NUMA node.
+ * we only extracted 12 bits of the extension fields, not 16
  * we didn't shift the extension field up far enough
  * we accidentally did the shift as 32-bit arithmetic, which
    meant that we would have an overflow instead of setting
    bits [47:32] of the resulting 64-bit address
-  * hw/core/machine.c::machine_numa_finish_cpu_init() to record
+Add a type cast and use extract64() instead of extract32()
-    CPU slots with no NUMA mapping set.
+to avoid integer overflow on addition. Fix bit fields
 extraction according to documentation.
-  * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
+Found by Linux Verification Center (linuxtesting.org) with SVACE.
     cluster-id.
-Signed-off-by: Gavin Shan <gshan@redhat.com>
+Cc: qemu-stable@nongnu.org
-Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Fixes: d3c6369a96 ("introduce xlnx-dpdma")
-Acked-by: Igor Mammedov <imammedo@redhat.com>
+Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
-Message-id: 20220503140304.855514-2-gshan@redhat.com
+Message-id: 20240428181131.23801-1-adiupina@astralinux.ru
 [PMM: adjusted commit message]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- qapi/machine.json          |  6 ++++--
+ hw/dma/xlnx_dpdma.c | 20 ++++++++++----------
- hw/core/machine-hmp-cmds.c |  4 ++++
+file changed, 10 insertions(+), 10 deletions(-)
  hw/core/machine.c          | 16 ++++++++++++++++
 files changed, 24 insertions(+), 2 deletions(-)
-diff --git a/qapi/machine.json b/qapi/machine.json
+diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c
 index XXXXXXX..XXXXXXX 100644
---- a/qapi/machine.json
+--- a/hw/dma/xlnx_dpdma.c
-+++ b/qapi/machine.json
++++ b/hw/dma/xlnx_dpdma.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
- # @node-id: NUMA node ID the CPU belongs to
- # @socket-id: socket number within node/board the CPU belongs to
+     switch (frag) {
- # @die-id: die number within socket the CPU belongs to (since 4.1)
+     case 0:
--# @core-id: core number within die the CPU belongs to
+-        addr = desc->source_address
-+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
+-            + (extract32(desc->address_extension, 16, 12) << 20);
-+# @core-id: core number within cluster the CPU belongs to
++        addr = (uint64_t)desc->source_address
- # @thread-id: thread number within core the CPU belongs to
++            + (extract64(desc->address_extension, 16, 16) << 32);
- #
+         break;
--# Note: currently there are 5 properties that could be present
+     case 1:
-+# Note: currently there are 6 properties that could be present
+-        addr = desc->source_address2
- #       but management should be prepared to pass through other
+-            + (extract32(desc->address_extension_23, 0, 12) << 8);
- #       properties with device_add command to allow for future
++        addr = (uint64_t)desc->source_address2
- #       interface extension. This also requires the filed names to be kept in
++            + (extract64(desc->address_extension_23, 0, 16) << 32);
-@@ -XXX,XX +XXX,XX @@
+         break;
-   'data': { '*node-id': 'int',
+     case 2:
-             '*socket-id': 'int',
+-        addr = desc->source_address3
-             '*die-id': 'int',
+-            + (extract32(desc->address_extension_23, 16, 12) << 20);
-+            '*cluster-id': 'int',
++        addr = (uint64_t)desc->source_address3
-             '*core-id': 'int',
++            + (extract64(desc->address_extension_23, 16, 16) << 32);
-             '*thread-id': 'int'
+         break;
-   }
+     case 3:
-diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
+-        addr = desc->source_address4
-index XXXXXXX..XXXXXXX 100644
+-            + (extract32(desc->address_extension_45, 0, 12) << 8);
---- a/hw/core/machine-hmp-cmds.c
++        addr = (uint64_t)desc->source_address4
-+++ b/hw/core/machine-hmp-cmds.c
++            + (extract64(desc->address_extension_45, 0, 16) << 32);
-@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
+         break;
-         if (c->has_die_id) {
+     case 4:
-             monitor_printf(mon, "    die-id: \"%" PRIu64 "\"\n", c->die_id);
+-        addr = desc->source_address5
-         }
+-            + (extract32(desc->address_extension_45, 16, 12) << 20);
-+        if (c->has_cluster_id) {
++        addr = (uint64_t)desc->source_address5
-+            monitor_printf(mon, "    cluster-id: \"%" PRIu64 "\"\n",
++            + (extract64(desc->address_extension_45, 16, 16) << 32);
-+                           c->cluster_id);
+         break;
-+        }
+     default:
-         if (c->has_core_id) {
+         addr = 0;
              monitor_printf(mon, "    core-id: \"%" PRIu64 "\"\n", c->core_id);
          }
 diff --git a/hw/core/machine.c b/hw/core/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/machine.c
 +++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
              return;
          }
 +        if (props->has_cluster_id && !slot->props.has_cluster_id) {
 +            error_setg(errp, "cluster-id is not supported");
 +            return;
 +        }
 +
          if (props->has_socket_id && !slot->props.has_socket_id) {
              error_setg(errp, "socket-id is not supported");
              return;
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
                  continue;
          }
 +        if (props->has_cluster_id &&
 +            props->cluster_id != slot->props.cluster_id) {
 +                continue;
 +        }
 +
          if (props->has_die_id && props->die_id != slot->props.die_id) {
                  continue;
          }
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
          }
          g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
      }
 +    if (cpu->props.has_cluster_id) {
 +        if (s->len) {
 +            g_string_append_printf(s, ", ");
 +        }
 +        g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
 +    }
      if (cpu->props.has_core_id) {
          if (s->len) {
              g_string_append_printf(s, ", ");
 --
-.25.1
+.34.1

-[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
+[PULL 15/21] hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
-From: Leif Lindholm <quic_llindhol@quicinc.com>
+From: Thomas Huth <thuth@redhat.com>
-NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
+"make check-qtest-aarch64" recently started failing on FreeBSD builds,
-separate infrastructure for a transitional period. We've now switched
+and valgrind on Linux also detected that there is something fishy with
-over to contributing as Qualcomm Innovation Center (quicinc), so update
+the new stm32l4x5-usart: The code forgot to set the correct class_size
-my email address to reflect this.
+here, so the various class_init functions in this file wrote beyond
 the allocated buffer when setting the subc->type field.
-Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
+Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton")
-Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
+Signed-off-by: Thomas Huth <thuth@redhat.com>
-Cc: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Cc: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20240429075908.36302-1-thuth@redhat.com
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 [Fixed commit message typo]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- .mailmap    | 3 ++-
+ hw/char/stm32l4x5_usart.c | 1 +
- MAINTAINERS | 2 +-
+file changed, 1 insertion(+)
 files changed, 3 insertions(+), 2 deletions(-)
-diff --git a/.mailmap b/.mailmap
+diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
 index XXXXXXX..XXXXXXX 100644
---- a/.mailmap
+--- a/hw/char/stm32l4x5_usart.c
-+++ b/.mailmap
++++ b/hw/char/stm32l4x5_usart.c
-@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo stm32l4x5_usart_types[] = {
- Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
+         .parent         = TYPE_SYS_BUS_DEVICE,
- Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
+         .instance_size  = sizeof(Stm32l4x5UsartBaseState),
- James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
+         .instance_init  = stm32l4x5_usart_base_init,
--Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
++        .class_size     = sizeof(Stm32l4x5UsartBaseClass),
-+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
+         .class_init     = stm32l4x5_usart_base_class_init,
-+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
+         .abstract       = true,
- Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
+     }, {
  Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
  Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
  SBSA-REF
  M: Radoslaw Biernacki <rad@semihalf.com>
  M: Peter Maydell <peter.maydell@linaro.org>
 -R: Leif Lindholm <leif@nuviainc.com>
 +R: Leif Lindholm <quic_llindhol@quicinc.com>
  L: qemu-arm@nongnu.org
  S: Maintained
  F: hw/arm/sbsa-ref.c
 --
-.25.1
+.34.1

-[PULL 02/32] target/arm: Handle cpreg registration for missing EL
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-More gracefully handle cpregs when EL2 and/or EL3 are missing.
-If the reg is entirely inaccessible, do not register it at all.
-If the reg is for EL2, and EL3 is present but EL2 is not,
-either discard, squash to res0, const, or keep unchanged.
-Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
-with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
-translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
-Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
-This will simplify cpreg registration for conditional arm features.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h |  11 +++
- target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
-files changed, 133 insertions(+), 56 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ enum {
-     ARM_CP_SVE                   = 1 << 14,
-     /* Flag: Do not expose in gdb sysreg xml. */
-     ARM_CP_NO_GDB                = 1 << 15,
-+    /*
-+     * Flags: If EL3 but not EL2...
-+     *   - UNDEF: discard the cpreg,
-+     *   -  KEEP: retain the cpreg as is,
-+     *   -  C_NZ: set const on the cpreg, but retain resetvalue,
-+     *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
-+     * See rule RJFFP in section D1.1.3 of DDI0487H.a.
-+     */
-+    ARM_CP_EL3_NO_EL2_UNDEF      = 1 << 16,
-+    ARM_CP_EL3_NO_EL2_KEEP       = 1 << 17,
-+    ARM_CP_EL3_NO_EL2_C_NZ       = 1 << 18,
- };
- /*
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
-     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
-+      .access = PL2_RW,
-+      .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
-       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
-     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
--      .access = PL2_RW, .resetvalue = 0,
-+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
-       .writefn = dacr_write, .raw_writefn = raw_write,
-       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
-     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
--      .access = PL2_RW, .resetvalue = 0,
-+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
-       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
-     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
-       .type = ARM_CP_ALIAS,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-       .writefn = tlbimva_hyp_is_write },
-     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
--      .type = ARM_CP_NO_RAW, .access = PL2_W,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_alle2_write },
-     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
--      .type = ARM_CP_NO_RAW, .access = PL2_W,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_vae2_write },
-     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_vae2_write },
-     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_alle2is_write },
-     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
--      .type = ARM_CP_NO_RAW, .access = PL2_W,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_vae2is_write },
-     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_vae2is_write },
- #ifndef CONFIG_USER_ONLY
-     /* Unlike the other EL2-related AT operations, these must
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
-       .access = PL2_W, .accessfn = at_s1e2_access,
--      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
-+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
-+      .writefn = ats_write64 },
-     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
-       .access = PL2_W, .accessfn = at_s1e2_access,
--      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
-+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
-+      .writefn = ats_write64 },
-     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
-      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
-      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
-     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
-       .access = PL2_RW, .accessfn = access_tda,
--      .type = ARM_CP_NOP },
-+      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
-     /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
-      * Channel but Linux may try to access this register. The 32-bit
-      * alias is DBGDCCINT.
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
-       .access = PL2_W, .type = ARM_CP_NOP },
-     { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_rvae2is_write },
-    { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_rvae2is_write },
-     { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
-       .access = PL2_W, .type = ARM_CP_NOP },
-    { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_rvae2is_write },
-    { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_rvae2is_write },
-     { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_rvae2_write },
-    { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_rvae2_write },
-    { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
-       .writefn = tlbi_aa64_vae1is_write },
-     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_alle2is_write },
-     { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_vae2is_write },
-    { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
-       .writefn = tlbi_aa64_alle1is_write },
-     { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
-+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_vae2is_write },
-     { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
-               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
-               .access = PL2_RW, .accessfn = access_el3_aa32ns,
--              .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
-+              .resetvalue = cpu->midr,
-+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
-               .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
-             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
-               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
-               .access = PL2_RW, .resetvalue = cpu->midr,
-+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
-               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
-             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
-               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-               .access = PL2_RW, .accessfn = access_el3_aa32ns,
--              .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
-+              .resetvalue = vmpidr_def,
-+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
-               .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
-             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
-               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
--              .access = PL2_RW,
--              .resetvalue = vmpidr_def,
-+              .access = PL2_RW, .resetvalue = vmpidr_def,
-+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
-               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
-         };
-         define_arm_cp_regs(cpu, vpidr_regs);
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-                                    int crm, int opc1, int opc2,
-                                    const char *name)
- {
-+    CPUARMState *env = &cpu->env;
-     uint32_t key;
-     ARMCPRegInfo *r2;
-     bool is64 = r->type & ARM_CP_64BIT;
-     bool ns = secstate & ARM_CP_SECSTATE_NS;
-     int cp = r->cp;
--    bool isbanked;
-     size_t name_len;
-+    bool make_const;
-     switch (state) {
-     case ARM_CP_STATE_AA32:
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-         }
-     }
-+    /*
-+     * Eliminate registers that are not present because the EL is missing.
-+     * Doing this here makes it easier to put all registers for a given
-+     * feature into the same ARMCPRegInfo array and define them all at once.
-+     */
-+    make_const = false;
-+    if (arm_feature(env, ARM_FEATURE_EL3)) {
-+        /*
-+         * An EL2 register without EL2 but with EL3 is (usually) RES0.
-+         * See rule RJFFP in section D1.1.3 of DDI0487H.a.
-+         */
-+        int min_el = ctz32(r->access) / 2;
-+        if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
-+            if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
-+                return;
-+            }
-+            make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
-+        }
-+    } else {
-+        CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
-+                                 ? PL2_RW : PL1_RW);
-+        if ((r->access & max_el) == 0) {
-+            return;
-+        }
-+    }
-+
-     /* Combine cpreg and name into one allocation. */
-     name_len = strlen(name) + 1;
-     r2 = g_malloc(sizeof(*r2) + name_len);
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-         r2->opaque = opaque;
-     }
--    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
--    if (isbanked) {
-+    if (make_const) {
-+        /* This should not have been a very special register to begin. */
-+        int old_special = r2->type & ARM_CP_SPECIAL_MASK;
-+        assert(old_special == 0 || old_special == ARM_CP_NOP);
-         /*
--         * Register is banked (using both entries in array).
--         * Overwriting fieldoffset as the array is only used to define
--         * banked registers but later only fieldoffset is used.
-+         * Set the special function to CONST, retaining the other flags.
-+         * This is important for e.g. ARM_CP_SVE so that we still
-+         * take the SVE trap if CPTR_EL3.EZ == 0.
-          */
--        r2->fieldoffset = r->bank_fieldoffsets[ns];
--    }
-+        r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
-+        /*
-+         * Usually, these registers become RES0, but there are a few
-+         * special cases like VPIDR_EL2 which have a constant non-zero
-+         * value with writes ignored.
-+         */
-+        if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
-+            r2->resetvalue = 0;
-+        }
-+        /*
-+         * ARM_CP_CONST has precedence, so removing the callbacks and
-+         * offsets are not strictly necessary, but it is potentially
-+         * less confusing to debug later.
-+         */
-+        r2->readfn = NULL;
-+        r2->writefn = NULL;
-+        r2->raw_readfn = NULL;
-+        r2->raw_writefn = NULL;
-+        r2->resetfn = NULL;
-+        r2->fieldoffset = 0;
-+        r2->bank_fieldoffsets[0] = 0;
-+        r2->bank_fieldoffsets[1] = 0;
-+    } else {
-+        bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
--    if (state == ARM_CP_STATE_AA32) {
-         if (isbanked) {
-             /*
--             * If the register is banked then we don't need to migrate or
--             * reset the 32-bit instance in certain cases:
--             *
--             * 1) If the register has both 32-bit and 64-bit instances then we
--             *    can count on the 64-bit instance taking care of the
--             *    non-secure bank.
--             * 2) If ARMv8 is enabled then we can count on a 64-bit version
--             *    taking care of the secure bank.  This requires that separate
--             *    32 and 64-bit definitions are provided.
-+             * Register is banked (using both entries in array).
-+             * Overwriting fieldoffset as the array is only used to define
-+             * banked registers but later only fieldoffset is used.
-              */
--            if ((r->state == ARM_CP_STATE_BOTH && ns) ||
--                (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
-+            r2->fieldoffset = r->bank_fieldoffsets[ns];
-+        }
-+        if (state == ARM_CP_STATE_AA32) {
-+            if (isbanked) {
-+                /*
-+                 * If the register is banked then we don't need to migrate or
-+                 * reset the 32-bit instance in certain cases:
-+                 *
-+                 * 1) If the register has both 32-bit and 64-bit instances
-+                 *    then we can count on the 64-bit instance taking care
-+                 *    of the non-secure bank.
-+                 * 2) If ARMv8 is enabled then we can count on a 64-bit
-+                 *    version taking care of the secure bank.  This requires
-+                 *    that separate 32 and 64-bit definitions are provided.
-+                 */
-+                if ((r->state == ARM_CP_STATE_BOTH && ns) ||
-+                    (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
-+                    r2->type |= ARM_CP_ALIAS;
-+                }
-+            } else if ((secstate != r->secure) && !ns) {
-+                /*
-+                 * The register is not banked so we only want to allow
-+                 * migration of the non-secure instance.
-+                 */
-                 r2->type |= ARM_CP_ALIAS;
-             }
--        } else if ((secstate != r->secure) && !ns) {
--            /*
--             * The register is not banked so we only want to allow migration
--             * of the non-secure instance.
--             */
--            r2->type |= ARM_CP_ALIAS;
--        }
--        if (HOST_BIG_ENDIAN &&
--            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
--            r2->fieldoffset += sizeof(uint32_t);
-+            if (HOST_BIG_ENDIAN &&
-+                r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
-+                r2->fieldoffset += sizeof(uint32_t);
-+            }
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-      * multiple times. Special registers (ie NOP/WFI) are
-      * never migratable and not even raw-accessible.
-      */
--    if (r->type & ARM_CP_SPECIAL_MASK) {
-+    if (r2->type & ARM_CP_SPECIAL_MASK) {
-         r2->type |= ARM_CP_NO_RAW;
-     }
-     if (((r->crm == CP_ANY) && crm != 0) ||
---
-.25.1

-[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
-vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
-while registering for v8.
-This is a behavior change for v7 cpus with Security Extensions and
-without Virtualization Extensions, in that the virtualization cpregs
-are now correctly not present.  This would be a migration compatibility
-break, except that we have an existing bug in which migration of 32-bit
-cpus with Security Extensions enabled does not work.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.c | 158 ++++----------------------------------------
-file changed, 13 insertions(+), 145 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
- };
--/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
--static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
--    { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
--      .access = PL2_RW,
--      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
--    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
--      .access = PL2_RW,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
--      .access = PL2_RW,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
--      .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
--      .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
--      .access = PL2_RW, .type = ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
--      .access = PL2_RW, .accessfn = access_el3_aa32ns,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
--      .cp = 15, .opc1 = 6, .crm = 2,
--      .access = PL2_RW, .accessfn = access_el3_aa32ns,
--      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
--    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
--      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
--      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
--      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
--      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
--      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
--      .resetvalue = 0 },
--    { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
--      .access = PL2_RW, .accessfn = access_tda,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
--      .access = PL2_RW, .accessfn = access_el3_aa32ns,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
--      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
--      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--    { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
--      .type = ARM_CP_CONST,
--      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
--      .access = PL2_RW, .resetvalue = 0 },
--};
--
--/* Ditto, but for registers which exist in ARMv8 but not v7 */
--static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
--    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
--      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
--      .access = PL2_RW,
--      .type = ARM_CP_CONST, .resetvalue = 0 },
--};
--
- static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
- {
-     ARMCPU *cpu = env_archcpu(env);
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-         define_arm_cp_regs(cpu, v8_idregs);
-         define_arm_cp_regs(cpu, v8_cp_reginfo);
-     }
--    if (arm_feature(env, ARM_FEATURE_EL2)) {
-+
-+    /*
-+     * Register the base EL2 cpregs.
-+     * Pre v8, these registers are implemented only as part of the
-+     * Virtualization Extensions (EL2 present).  Beginning with v8,
-+     * if EL2 is missing but EL3 is enabled, mostly these become
-+     * RES0 from EL3, with some specific exceptions.
-+     */
-+    if (arm_feature(env, ARM_FEATURE_EL2)
-+        || (arm_feature(env, ARM_FEATURE_EL3)
-+            && arm_feature(env, ARM_FEATURE_V8))) {
-         uint64_t vmpidr_def = mpidr_read_val(env);
-         ARMCPRegInfo vpidr_regs[] = {
-             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-             };
-             define_one_arm_cp_reg(cpu, &rvbar);
-         }
--    } else {
--        /* If EL2 is missing but higher ELs are enabled, we need to
--         * register the no_el2 reginfos.
--         */
--        if (arm_feature(env, ARM_FEATURE_EL3)) {
--            /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
--             * of MIDR_EL1 and MPIDR_EL1.
--             */
--            ARMCPRegInfo vpidr_regs[] = {
--                { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
--                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
--                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
--                  .type = ARM_CP_CONST, .resetvalue = cpu->midr,
--                  .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
--                { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
--                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
--                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
--                  .type = ARM_CP_NO_RAW,
--                  .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
--            };
--            define_arm_cp_regs(cpu, vpidr_regs);
--            define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
--            if (arm_feature(env, ARM_FEATURE_V8)) {
--                define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
--            }
--        }
-     }
-+
-+    /* Register the base EL3 cpregs. */
-     if (arm_feature(env, ARM_FEATURE_EL3)) {
-         define_arm_cp_regs(cpu, el3_cp_reginfo);
-         ARMCPRegInfo el3_regs[] = {
---
-.25.1

-[PULL 04/32] target/arm: Merge zcr reginfo
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
-now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
-while registering.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.c | 55 ++++++++++++++-------------------------------
-file changed, 17 insertions(+), 38 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     }
- }
--static const ARMCPRegInfo zcr_el1_reginfo = {
--    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
--    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
--    .access = PL1_RW, .type = ARM_CP_SVE,
--    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
--    .writefn = zcr_write, .raw_writefn = raw_write
--};
--
--static const ARMCPRegInfo zcr_el2_reginfo = {
--    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
--    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
--    .access = PL2_RW, .type = ARM_CP_SVE,
--    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
--    .writefn = zcr_write, .raw_writefn = raw_write
--};
--
--static const ARMCPRegInfo zcr_no_el2_reginfo = {
--    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
--    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
--    .access = PL2_RW, .type = ARM_CP_SVE,
--    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
--};
--
--static const ARMCPRegInfo zcr_el3_reginfo = {
--    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
--    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
--    .access = PL3_RW, .type = ARM_CP_SVE,
--    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
--    .writefn = zcr_write, .raw_writefn = raw_write
-+static const ARMCPRegInfo zcr_reginfo[] = {
-+    { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
-+      .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
-+      .access = PL1_RW, .type = ARM_CP_SVE,
-+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
-+      .writefn = zcr_write, .raw_writefn = raw_write },
-+    { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-+      .access = PL2_RW, .type = ARM_CP_SVE,
-+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
-+      .writefn = zcr_write, .raw_writefn = raw_write },
-+    { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
-+      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
-+      .access = PL3_RW, .type = ARM_CP_SVE,
-+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
-+      .writefn = zcr_write, .raw_writefn = raw_write },
- };
- void hw_watchpoint_update(ARMCPU *cpu, int n)
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-     }
-     if (cpu_isar_feature(aa64_sve, cpu)) {
--        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
--        if (arm_feature(env, ARM_FEATURE_EL2)) {
--            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
--        } else {
--            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
--        }
--        if (arm_feature(env, ARM_FEATURE_EL3)) {
--            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
--        }
-+        define_arm_cp_regs(cpu, zcr_reginfo);
-     }
- #ifdef TARGET_AARCH64
---
-.25.1

-[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
+[PULL 16/21] hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
-From: Gavin Shan <gshan@redhat.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-The CPU topology isn't enabled on arm/virt machine yet, but we're
+Use little endian for derivative OTP fuse key.
 going to do it in next patch. After the CPU topology is enabled by
 next patch, "thread-id=1" becomes invalid because the CPU core is
 preferred on arm/virt machine. It means these two CPUs have 0/1
 as their core IDs, but their thread IDs are all 0. It will trigger
 test failure as the following message indicates:
-  [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test  ERROR
+Cc: qemu-stable@nongnu.org
-.48s   killed by signal 6 SIGABRT
+Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model")
-  >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
+Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com>
-      QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon         \
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-      QTEST_QEMU_BINARY=./qemu-system-aarch64                                       \
+Message-id: 20240422125813.1403-1-philmd@linaro.org
-      QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83                                  \
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
       /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
   ――――――――――――――――――――――――――――――――――――――――――――――
   stderr:
   qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
 This fixes the issue by providing comprehensive SMP configurations
 in aarch64_numa_cpu(). The SMP configurations aren't used before
 the CPU topology is enabled in next patch.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Message-id: 20220503140304.855514-3-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/qtest/numa-test.c | 3 ++-
+ hw/arm/npcm7xx.c | 3 ++-
 file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
+diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/numa-test.c
+--- a/hw/arm/npcm7xx.c
-+++ b/tests/qtest/numa-test.c
++++ b/hw/arm/npcm7xx.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
+@@ -XXX,XX +XXX,XX @@
-     QTestState *qts;
+ #include "hw/qdev-clock.h"
-     g_autofree char *cli = NULL;
+ #include "hw/qdev-properties.h"
+ #include "qapi/error.h"
--    cli = make_cli(data, "-machine smp.cpus=2 "
++#include "qemu/bswap.h"
-+    cli = make_cli(data, "-machine "
+ #include "qemu/units.h"
-+        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+ #include "sysemu/sysemu.h"
-         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
+ #include "target/arm/cpu-qom.h"
-         "-numa cpu,node-id=1,thread-id=0 "
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
-         "-numa cpu,node-id=0,thread-id=1");
+      * The initial mask of disabled modules indicates the chip derivative (e.g.
       * NPCM750 or NPCM730).
       */
 -    value = tswap32(nc->disabled_modules);
 +    value = cpu_to_le32(nc->disabled_modules);
      npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
                              sizeof(value));
  }
 --
-.25.1
+.34.1

-[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
+[PULL 17/21] hw/display : Add device DM163
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
-This register is present for either VHE or Debugv8p2.
+This device implements the IM120417002 colors shield v1.1 for Arduino
 (which relies on the DM163 8x3-channel led driving logic) and features
 a simple display of an 8x8 RGB matrix. The columns of the matrix are
 driven by the DM163 and the rows are driven externally.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
-Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
+Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr
 [PMM: updated to new reset hold method prototype]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 15 +++++++++++----
+ docs/system/arm/b-l475e-iot01a.rst |   3 +-
-file changed, 11 insertions(+), 4 deletions(-)
+ include/hw/display/dm163.h         |  59 +++++
  hw/display/dm163.c                 | 349 +++++++++++++++++++++++++++++
  hw/display/Kconfig                 |   3 +
  hw/display/meson.build             |   1 +
  hw/display/trace-events            |  14 ++
 files changed, 428 insertions(+), 1 deletion(-)
  create mode 100644 include/hw/display/dm163.h
  create mode 100644 hw/display/dm163.c
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/docs/system/arm/b-l475e-iot01a.rst
-+++ b/target/arm/helper.c
++++ b/docs/system/arm/b-l475e-iot01a.rst
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
+@@ -XXX,XX +XXX,XX @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors.
-       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ Supported devices
- };
+ """""""""""""""""
-+static const ARMCPRegInfo contextidr_el2 = {
+-Currently B-L475E-IOT01A machine's only supports the following devices:
-+    .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
++Currently B-L475E-IOT01A machines support the following devices:
-+    .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
-+    .access = PL2_RW,
+ - Cortex-M4F based STM32L4x5 SoC
-+    .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+ - STM32L4x5 EXTI (Extended interrupts and events controller)
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
  - STM32L4x5 RCC (Reset and clock control)
  - STM32L4x5 GPIOs (General-purpose I/Os)
  - STM32L4x5 USARTs, UARTs and LPUART (Serial ports)
 +- optional 8x8 led display (based on DM163 driver)
  Missing devices
  """""""""""""""
 diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/display/dm163.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU DM163 8x3-channel constant current led driver
 + * driving columns of associated 8x8 RGB matrix.
 + *
 + * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
 + * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
 + *
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + */
 +
 +#ifndef HW_DISPLAY_DM163_H
 +#define HW_DISPLAY_DM163_H
 +
 +#include "qom/object.h"
 +#include "hw/qdev-core.h"
 +
 +#define TYPE_DM163 "dm163"
 +OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163);
 +
 +#define RGB_MATRIX_NUM_ROWS 8
 +#define RGB_MATRIX_NUM_COLS 8
 +#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3)
 +/* The last row is filled with 0 (turned off row) */
 +#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1)
 +
 +typedef struct DM163State {
 +    DeviceState parent_obj;
 +
 +    /* DM163 driver */
 +    uint64_t bank0_shift_register[3];
 +    uint64_t bank1_shift_register[3];
 +    uint16_t latched_outputs[DM163_NUM_LEDS];
 +    uint16_t outputs[DM163_NUM_LEDS];
 +    qemu_irq sout;
 +
 +    uint8_t sin;
 +    uint8_t dck;
 +    uint8_t rst_b;
 +    uint8_t lat_b;
 +    uint8_t selbk;
 +    uint8_t en_b;
 +
 +    /* IM120417002 colors shield */
 +    uint8_t activated_rows;
 +
 +    /* 8x8 RGB matrix */
 +    QemuConsole *console;
 +    uint8_t redraw;
 +    /* Rows currently being displayed on the matrix. */
 +    /* The last row is filled with 0 (turned off row) */
 +    uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS];
 +    uint8_t last_buffer_idx;
 +    uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS];
 +    /* Used to simulate retinal persistence of rows */
 +    uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS];
 +} DM163State;
 +
 +#endif /* HW_DISPLAY_DM163_H */
 diff --git a/hw/display/dm163.c b/hw/display/dm163.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/display/dm163.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU DM163 8x3-channel constant current led driver
 + * driving columns of associated 8x8 RGB matrix.
 + *
 + * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
 + * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
 + *
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + */
 +
 +/*
 + * The reference used for the DM163 is the following :
 + * http://www.siti.com.tw/product/spec/LED/DM163.pdf
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "migration/vmstate.h"
 +#include "hw/irq.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/display/dm163.h"
 +#include "ui/console.h"
 +#include "trace.h"
 +
 +#define LED_SQUARE_SIZE 100
 +/* Number of frames a row stays visible after being turned off. */
 +#define ROW_PERSISTENCE 3
 +#define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1)
 +
 +static const VMStateDescription vmstate_dm163 = {
 +    .name = TYPE_DM163,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (const VMStateField[]) {
 +        VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3),
 +        VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3),
 +        VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS),
 +        VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS),
 +        VMSTATE_UINT8(dck, DM163State),
 +        VMSTATE_UINT8(en_b, DM163State),
 +        VMSTATE_UINT8(lat_b, DM163State),
 +        VMSTATE_UINT8(rst_b, DM163State),
 +        VMSTATE_UINT8(selbk, DM163State),
 +        VMSTATE_UINT8(sin, DM163State),
 +        VMSTATE_UINT8(activated_rows, DM163State),
 +        VMSTATE_UINT32_2DARRAY(buffer, DM163State, COLOR_BUFFER_SIZE,
 +                               RGB_MATRIX_NUM_COLS),
 +        VMSTATE_UINT8(last_buffer_idx, DM163State),
 +        VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_ROWS),
 +        VMSTATE_UINT8_ARRAY(row_persistence_delay, DM163State,
 +                            RGB_MATRIX_NUM_ROWS),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
- static const ARMCPRegInfo vhe_reginfo[] = {
++static void dm163_reset_hold(Object *obj, ResetType type)
--    { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
++{
--      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
++    DM163State *s = DM163(obj);
--      .access = PL2_RW,
++
--      .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
++    s->sin = 0;
-     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
++    s->dck = 0;
-       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
++    s->rst_b = 0;
-       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
++    /* Ensuring the first falling edge of lat_b isn't missed */
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
++    s->lat_b = 1;
-         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
++    s->selbk = 0;
-     }
++    s->en_b = 0;
++    /* Reset stops the PWM, not the shift and latched registers. */
-+    if (cpu_isar_feature(aa64_vh, cpu) ||
++    memset(s->outputs, 0, sizeof(s->outputs));
-+        cpu_isar_feature(aa64_debugv8p2, cpu)) {
++
-+        define_one_arm_cp_reg(cpu, &contextidr_el2);
++    s->activated_rows = 0;
-+    }
++    s->redraw = 0;
-     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
++    trace_dm163_redraw(s->redraw);
-         define_arm_cp_regs(cpu, vhe_reginfo);
++    for (unsigned i = 0; i < COLOR_BUFFER_SIZE; i++) {
-     }
++        memset(s->buffer[i], 0, sizeof(s->buffer[0]));
 +    }
 +    s->last_buffer_idx = 0;
 +    memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_row));
 +    memset(s->row_persistence_delay, 0, sizeof(s->row_persistence_delay));
 +}
 +
 +static void dm163_dck_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    if (new_state && !s->dck) {
 +        /*
 +         * On raising dck, sample selbk to get the bank to use, and
 +         * sample sin for the bit to enter into the bank shift buffer.
 +         */
 +        uint64_t *sb =
 +            s->selbk ? s->bank1_shift_register : s->bank0_shift_register;
 +        /* Output the outgoing bit on sout */
 +        const bool sout = (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) :
 +                           sb[2] & MAKE_64BIT_MASK(15, 1)) != 0;
 +        qemu_set_irq(s->sout, sout);
 +        /* Enter sin into the shift buffer */
 +        sb[2] = (sb[2] << 1) | ((sb[1] >> 63) & 1);
 +        sb[1] = (sb[1] << 1) | ((sb[0] >> 63) & 1);
 +        sb[0] = (sb[0] << 1) | s->sin;
 +    }
 +
 +    s->dck = new_state;
 +    trace_dm163_dck(new_state);
 +}
 +
 +static void dm163_propagate_outputs(DM163State *s)
 +{
 +    s->last_buffer_idx = (s->last_buffer_idx + 1) % RGB_MATRIX_NUM_ROWS;
 +    /* Values are output when reset is high and enable is low. */
 +    if (s->rst_b && !s->en_b) {
 +        memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs));
 +    } else {
 +        memset(s->outputs, 0, sizeof(s->outputs));
 +    }
 +    for (unsigned x = 0; x < RGB_MATRIX_NUM_COLS; x++) {
 +        /* Grouping the 3 RGB channels in a pixel value */
 +        const uint16_t b = extract16(s->outputs[3 * x + 0], 6, 8);
 +        const uint16_t g = extract16(s->outputs[3 * x + 1], 6, 8);
 +        const uint16_t r = extract16(s->outputs[3 * x + 2], 6, 8);
 +        uint32_t rgba = 0;
 +
 +        trace_dm163_channels(3 * x + 2, r);
 +        trace_dm163_channels(3 * x + 1, g);
 +        trace_dm163_channels(3 * x + 0, b);
 +
 +        rgba = deposit32(rgba,  0, 8, r);
 +        rgba = deposit32(rgba,  8, 8, g);
 +        rgba = deposit32(rgba, 16, 8, b);
 +
 +        /* Led values are sent from the last one to the first one */
 +        s->buffer[s->last_buffer_idx][RGB_MATRIX_NUM_COLS - x - 1] = rgba;
 +    }
 +    for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
 +        if (s->activated_rows & (1 << row)) {
 +            s->buffer_idx_of_row[row] = s->last_buffer_idx;
 +            s->redraw |= (1 << row);
 +            trace_dm163_redraw(s->redraw);
 +        }
 +    }
 +}
 +
 +static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    s->en_b = new_state;
 +    dm163_propagate_outputs(s);
 +    trace_dm163_en_b(new_state);
 +}
 +
 +static uint8_t dm163_bank0(const DM163State *s, uint8_t led)
 +{
 +    /*
 +     * Bank 0 uses 6 bits per led, so a value may be stored accross
 +     * two uint64_t entries.
 +     */
 +    const uint8_t low_bit = 6 * led;
 +    const uint8_t low_word = low_bit / 64;
 +    const uint8_t high_word = (low_bit + 5) / 64;
 +    const uint8_t low_shift = low_bit % 64;
 +
 +    if (low_word == high_word) {
 +        /* Simple case: the value belongs to one entry. */
 +        return extract64(s->bank0_shift_register[low_word], low_shift, 6);
 +    }
 +
 +    const uint8_t nb_bits_in_low_word = 64 - low_shift;
 +    const uint8_t nb_bits_in_high_word = 6 - nb_bits_in_low_word;
 +
 +    const uint64_t bits_in_low_word = \
 +        extract64(s->bank0_shift_register[low_word], low_shift,
 +                  nb_bits_in_low_word);
 +    const uint64_t bits_in_high_word = \
 +        extract64(s->bank0_shift_register[high_word], 0,
 +                  nb_bits_in_high_word);
 +    uint8_t val = 0;
 +
 +    val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word);
 +    val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word,
 +                    bits_in_high_word);
 +
 +    return val;
 +}
 +
 +static uint8_t dm163_bank1(const DM163State *s, uint8_t led)
 +{
 +    const uint64_t entry = s->bank1_shift_register[led / RGB_MATRIX_NUM_COLS];
 +    return extract64(entry, 8 * (led % RGB_MATRIX_NUM_COLS), 8);
 +}
 +
 +static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    if (s->lat_b && !new_state) {
 +        for (int led = 0; led < DM163_NUM_LEDS; led++) {
 +            s->latched_outputs[led] = dm163_bank0(s, led) * dm163_bank1(s, led);
 +        }
 +        dm163_propagate_outputs(s);
 +    }
 +
 +    s->lat_b = new_state;
 +    trace_dm163_lat_b(new_state);
 +}
 +
 +static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    s->rst_b = new_state;
 +    dm163_propagate_outputs(s);
 +    trace_dm163_rst_b(new_state);
 +}
 +
 +static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    s->selbk = new_state;
 +    trace_dm163_selbk(new_state);
 +}
 +
 +static void dm163_sin_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    s->sin = new_state;
 +    trace_dm163_sin(new_state);
 +}
 +
 +static void dm163_rows_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    if (new_state) {
 +        s->activated_rows |= (1 << line);
 +        s->buffer_idx_of_row[line] = s->last_buffer_idx;
 +        s->redraw |= (1 << line);
 +        trace_dm163_redraw(s->redraw);
 +    } else {
 +        s->activated_rows &= ~(1 << line);
 +        s->row_persistence_delay[line] = ROW_PERSISTENCE;
 +    }
 +    trace_dm163_activated_rows(s->activated_rows);
 +}
 +
 +static void dm163_invalidate_display(void *opaque)
 +{
 +    DM163State *s = (DM163State *)opaque;
 +    s->redraw = 0xFF;
 +    trace_dm163_redraw(s->redraw);
 +}
 +
 +static void update_row_persistence_delay(DM163State *s, unsigned row)
 +{
 +    if (s->row_persistence_delay[row]) {
 +        s->row_persistence_delay[row]--;
 +    } else {
 +        /*
 +         * If the ROW_PERSISTENCE delay is up,
 +         * the row is turned off.
 +         */
 +        s->buffer_idx_of_row[row] = TURNED_OFF_ROW;
 +        s->redraw |= (1 << row);
 +        trace_dm163_redraw(s->redraw);
 +    }
 +}
 +
 +static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest,
 +                                       unsigned row)
 +{
 +    for (unsigned _ = 0; _ < LED_SQUARE_SIZE; _++) {
 +        for (int x = 0; x < RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE; x++) {
 +            /* UI layer guarantees that there's 32 bits per pixel (Mar 2024) */
 +            *dest++ = s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUARE_SIZE];
 +        }
 +    }
 +
 +    dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row,
 +                    RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE);
 +    s->redraw &= ~(1 << row);
 +    trace_dm163_redraw(s->redraw);
 +
 +    return dest;
 +}
 +
 +static void dm163_update_display(void *opaque)
 +{
 +    DM163State *s = (DM163State *)opaque;
 +    DisplaySurface *surface = qemu_console_surface(s->console);
 +    uint32_t *dest;
 +
 +    dest = surface_data(surface);
 +    for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
 +        update_row_persistence_delay(s, row);
 +        if (!extract8(s->redraw, row, 1)) {
 +            dest += LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_COLS;
 +            continue;
 +        }
 +        dest = update_display_of_row(s, dest, row);
 +    }
 +}
 +
 +static const GraphicHwOps dm163_ops = {
 +    .invalidate  = dm163_invalidate_display,
 +    .gfx_update  = dm163_update_display,
 +};
 +
 +static void dm163_realize(DeviceState *dev, Error **errp)
 +{
 +    DM163State *s = DM163(dev);
 +
 +    qdev_init_gpio_in(dev, dm163_rows_gpio_handler, RGB_MATRIX_NUM_ROWS);
 +    qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1);
 +    qdev_init_gpio_out_named(dev, &s->sout, "sout", 1);
 +
 +    s->console = graphic_console_init(dev, 0, &dm163_ops, s);
 +    qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE,
 +                        RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE);
 +}
 +
 +static void dm163_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +
 +    dc->desc = "DM163";
 +    dc->vmsd = &vmstate_dm163;
 +    dc->realize = dm163_realize;
 +    rc->phases.hold = dm163_reset_hold;
 +    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 +}
 +
 +static const TypeInfo dm163_types[] = {
 +    {
 +        .name = TYPE_DM163,
 +        .parent = TYPE_DEVICE,
 +        .instance_size = sizeof(DM163State),
 +        .class_init = dm163_class_init
 +    }
 +};
 +
 +DEFINE_TYPES(dm163_types)
 diff --git a/hw/display/Kconfig b/hw/display/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/display/Kconfig
 +++ b/hw/display/Kconfig
@@ -XXX,XX +XXX,XX @@ config XLNX_DISPLAYPORT
      bool
      # defaults to "N", enabled by specific boards
      depends on PIXMAN
 +
 +config DM163
 +    bool
 diff --git a/hw/display/meson.build b/hw/display/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/display/meson.build
 +++ b/hw/display/meson.build
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c'))
  system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c'))
  system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c'))
 +system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c'))
  if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or
      config_all_devices.has_key('CONFIG_VGA_PCI') or
 diff --git a/hw/display/trace-events b/hw/display/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/display/trace-events
 +++ b/hw/display/trace-events
@@ -XXX,XX +XXX,XX @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%"PRI
  macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32
  macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32
  macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting mode to width %"PRId32 " height %"PRId32 " size %d"
 +
 +# dm163.c
 +dm163_redraw(uint8_t redraw) "0x%02x"
 +dm163_dck(unsigned new_state) "dck : %u"
 +dm163_en_b(unsigned new_state) "en_b : %u"
 +dm163_rst_b(unsigned new_state) "rst_b : %u"
 +dm163_lat_b(unsigned new_state) "lat_b : %u"
 +dm163_sin(unsigned new_state) "sin : %u"
 +dm163_selbk(unsigned new_state) "selbk : %u"
 +dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 ""
 +dm163_bits_ppi(unsigned dest_width) "dest_width : %u"
 +dm163_leds(int led, uint32_t value) "led %d: 0x%x"
 +dm163_channels(int channel, uint8_t value) "channel %d: 0x%x"
 +dm163_refresh_rate(uint32_t rr) "refresh rate %d"
 --
-.25.1
+.34.1

-[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
+[PULL 18/21] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
-From: Gavin Shan <gshan@redhat.com>
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
-When the PPTT table is built, the CPU topology is re-calculated, but
+Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
-it's unecessary because the CPU topology has been populated in
+to the optional DM163 display from the board code (GPIOs outputs need
-virt_possible_cpu_arch_ids() on arm/virt machine.
+to be connected to both SYSCFG inputs and DM163 inputs).
-This reworks build_pptt() to avoid by reusing the existing IDs in
+STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
 ms->possible_cpus. Currently, the only user of build_pptt() is
 arm/virt machine.
-Signed-off-by: Gavin Shan <gshan@redhat.com>
+Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
-Tested-by: Yanan Wang <wangyanan55@huawei.com>
+Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
-Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Acked-by: Igor Mammedov <imammedo@redhat.com>
+Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr
 Acked-by: Michael S. Tsirkin <mst@redhat.com>
 Message-id: 20220503140304.855514-7-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
+ hw/arm/stm32l4x5_soc.c              |  6 ++++--
-file changed, 48 insertions(+), 63 deletions(-)
+ tests/qtest/stm32l4x5_gpio-test.c   | 13 ++++++++-----
  tests/qtest/stm32l4x5_syscfg-test.c | 17 ++++++++++-------
 files changed, 22 insertions(+), 14 deletions(-)
-diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
+diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/acpi/aml-build.c
+--- a/hw/arm/stm32l4x5_soc.c
-+++ b/hw/acpi/aml-build.c
++++ b/hw/arm/stm32l4x5_soc.c
-@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
+@@ -XXX,XX +XXX,XX @@
-                 const char *oem_id, const char *oem_table_id)
+ /*
- {
+  * STM32L4x5 SoC family
-     MachineClass *mc = MACHINE_GET_CLASS(ms);
+  *
--    GQueue *list = g_queue_new();
+- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
--    guint pptt_start = table_data->len;
+- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
--    guint parent_offset;
++ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
--    guint length, i;
++ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
--    int uid = 0;
+  *
--    int socket;
+  * SPDX-License-Identifier: GPL-2.0-or-later
-+    CPUArchIdList *cpus = ms->possible_cpus;
+  *
-+    int64_t socket_id = -1, cluster_id = -1, core_id = -1;
+@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
 +    uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
 +    uint32_t pptt_start = table_data->len;
 +    int n;
      AcpiTable table = { .sig = "PPTT", .rev = 2,
                          .oem_id = oem_id, .oem_table_id = oem_table_id };
      acpi_table_begin(&table, table_data);
 -    for (socket = 0; socket < ms->smp.sockets; socket++) {
 -        g_queue_push_tail(list,
 -            GUINT_TO_POINTER(table_data->len - pptt_start));
 -        build_processor_hierarchy_node(
 -            table_data,
 -            /*
 -             * Physical package - represents the boundary
 -             * of a physical package
 -             */
 -            (1 << 0),
 -            0, socket, NULL, 0);
 -    }
 -
 -    if (mc->smp_props.clusters_supported) {
 -        length = g_queue_get_length(list);
 -        for (i = 0; i < length; i++) {
 -            int cluster;
 -
 -            parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -            for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
 -                g_queue_push_tail(list,
 -                    GUINT_TO_POINTER(table_data->len - pptt_start));
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (0 << 0), /* not a physical package */
 -                    parent_offset, cluster, NULL, 0);
 -            }
 +    /*
 +     * This works with the assumption that cpus[n].props.*_id has been
 +     * sorted from top to down levels in mc->possible_cpu_arch_ids().
 +     * Otherwise, the unexpected and duplicated containers will be
 +     * created.
 +     */
 +    for (n = 0; n < cpus->len; n++) {
 +        if (cpus->cpus[n].props.socket_id != socket_id) {
 +            assert(cpus->cpus[n].props.socket_id > socket_id);
 +            socket_id = cpus->cpus[n].props.socket_id;
 +            cluster_id = -1;
 +            core_id = -1;
 +            socket_offset = table_data->len - pptt_start;
 +            build_processor_hierarchy_node(table_data,
 +                (1 << 0), /* Physical package */
 +                0, socket_id, NULL, 0);
          }
 -    }
 -    length = g_queue_get_length(list);
 -    for (i = 0; i < length; i++) {
 -        int core;
 -
 -        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -        for (core = 0; core < ms->smp.cores; core++) {
 -            if (ms->smp.threads > 1) {
 -                g_queue_push_tail(list,
 -                    GUINT_TO_POINTER(table_data->len - pptt_start));
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (0 << 0), /* not a physical package */
 -                    parent_offset, core, NULL, 0);
 -            } else {
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (1 << 1) | /* ACPI Processor ID valid */
 -                    (1 << 3),  /* Node is a Leaf */
 -                    parent_offset, uid++, NULL, 0);
 +        if (mc->smp_props.clusters_supported) {
 +            if (cpus->cpus[n].props.cluster_id != cluster_id) {
 +                assert(cpus->cpus[n].props.cluster_id > cluster_id);
 +                cluster_id = cpus->cpus[n].props.cluster_id;
 +                core_id = -1;
 +                cluster_offset = table_data->len - pptt_start;
 +                build_processor_hierarchy_node(table_data,
 +                    (0 << 0), /* Not a physical package */
 +                    socket_offset, cluster_id, NULL, 0);
              }
 +        } else {
 +            cluster_offset = socket_offset;
          }
 -    }
 -    length = g_queue_get_length(list);
 -    for (i = 0; i < length; i++) {
 -        int thread;
 +        if (ms->smp.threads == 1) {
 +            build_processor_hierarchy_node(table_data,
 +                (1 << 1) | /* ACPI Processor ID valid */
 +                (1 << 3),  /* Node is a Leaf */
 +                cluster_offset, n, NULL, 0);
 +        } else {
 +            if (cpus->cpus[n].props.core_id != core_id) {
 +                assert(cpus->cpus[n].props.core_id > core_id);
 +                core_id = cpus->cpus[n].props.core_id;
 +                core_offset = table_data->len - pptt_start;
 +                build_processor_hierarchy_node(table_data,
 +                    (0 << 0), /* Not a physical package */
 +                    cluster_offset, core_id, NULL, 0);
 +            }
 -        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -        for (thread = 0; thread < ms->smp.threads; thread++) {
 -            build_processor_hierarchy_node(
 -                table_data,
 +            build_processor_hierarchy_node(table_data,
                  (1 << 1) | /* ACPI Processor ID valid */
                  (1 << 2) | /* Processor is a Thread */
                  (1 << 3),  /* Node is a Leaf */
 -                parent_offset, uid++, NULL, 0);
 +                core_offset, n, NULL, 0);
          }
      }
--    g_queue_free(list);
++    qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL);
-     acpi_table_end(linker, &table);
++
      /* EXTI device */
      busdev = SYS_BUS_DEVICE(&s->exti);
      if (!sysbus_realize(busdev, errp)) {
 diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/stm32l4x5_gpio-test.c
 +++ b/tests/qtest/stm32l4x5_gpio-test.c
@@ -XXX,XX +XXX,XX @@
  #define OTYPER_PUSH_PULL 0
  #define OTYPER_OPEN_DRAIN 1
 +/* SoC forwards GPIOs to SysCfg */
 +#define SYSCFG "/machine/soc"
 +
  const uint32_t moder_reset[NUM_GPIOS] = {
 xABFFFFFF,
 xFFFFFEBF,
@@ -XXX,XX +XXX,XX @@ static void test_gpio_output_mode(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      unsigned int gpio_id = get_gpio_id(gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Set a bit in ODR and check nothing happens */
      gpio_set_bit(gpio, ODR, pin, 1);
@@ -XXX,XX +XXX,XX @@ static void test_gpio_input_mode(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      unsigned int gpio_id = get_gpio_id(gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Configure a line as input, raise it, and check that the pin is high */
      gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@@ -XXX,XX +XXX,XX @@ static void test_pull_up_pull_down(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      unsigned int gpio_id = get_gpio_id(gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Configure a line as input with pull-up, check the line is set high */
      gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@@ -XXX,XX +XXX,XX @@ static void test_push_pull(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Setting a line high externally, configuring it in push-pull output */
      /* And checking the pin was disconnected */
@@ -XXX,XX +XXX,XX @@ static void test_open_drain(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Setting a line high externally, configuring it in open-drain output */
      /* And checking the pin was disconnected */
 diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/stm32l4x5_syscfg-test.c
 +++ b/tests/qtest/stm32l4x5_syscfg-test.c
@@ -XXX,XX +XXX,XX @@
  /*
   * QTest testcase for STM32L4x5_SYSCFG
   *
 - * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 - * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
 + * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
   *
   * This work is licensed under the terms of the GNU GPL, version 2 or later.
   * See the COPYING file in the top-level directory.
@@ -XXX,XX +XXX,XX @@
  #define SYSCFG_SWPR2 0x28
  #define INVALID_ADDR 0x2C
 +/* SoC forwards GPIOs to SysCfg */
 +#define SYSCFG "/machine/soc"
 +#define EXTI "/machine/soc/exti"
 +
  static void syscfg_writel(unsigned int offset, uint32_t value)
  {
      writel(SYSCFG_BASE_ADDR + offset, value);
@@ -XXX,XX +XXX,XX @@ static uint32_t syscfg_readl(unsigned int offset)
  static void syscfg_set_irq(int num, int level)
  {
 -   qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
 -                    NULL, num, level);
 +   qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
  }
+ static void system_reset(void)
+@@ -XXX,XX +XXX,XX @@ static void test_interrupt(void)
+      * Test that GPIO rising lines result in an irq
+      * with the right configuration
+      */
+-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
++    qtest_irq_intercept_in(global_qtest, EXTI);
+     /* GPIOA is the default source for EXTI lines 0 to 15 */
+@@ -XXX,XX +XXX,XX @@ static void test_irq_pin_multiplexer(void)
+      * Test that syscfg irq sets the right exti irq
+      */
+-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
++    qtest_irq_intercept_in(global_qtest, EXTI);
+     syscfg_set_irq(0, 1);
+@@ -XXX,XX +XXX,XX @@ static void test_irq_gpio_multiplexer(void)
+      * Test that an irq is generated only by the right GPIO
+      */
+-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
++    qtest_irq_intercept_in(global_qtest, EXTI);
+     /* GPIOA is the default source for EXTI lines 0 to 15 */
 --
-.25.1
+.34.1

-[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
+[PULL 19/21] hw/arm : Create Bl475eMachineState
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
-Previously we were defining some of these in user-only mode,
+Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
-but none of them are accessible from user-only, therefore
+Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
-define them only in system mode.
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr
 This will shortly be used from cpu_tcg.c also.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/internals.h |  6 ++++
+ hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++-------------
- target/arm/cpu64.c     | 64 +++---------------------------------------
+file changed, 32 insertions(+), 14 deletions(-)
  target/arm/cpu_tcg.c   | 59 ++++++++++++++++++++++++++++++++++++++
 files changed, 69 insertions(+), 60 deletions(-)
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/hw/arm/b-l475e-iot01a.c
-+++ b/target/arm/internals.h
++++ b/hw/arm/b-l475e-iot01a.c
-@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
+@@ -XXX,XX +XXX,XX @@
- int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
+  * B-L475E-IOT01A Discovery Kit machine
- #endif
+  * (B-L475E-IOT01A IoT Node)
+  *
-+#ifdef CONFIG_USER_ONLY
+- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
-+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
-+#else
++ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
-+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
++ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
-+#endif
+  *
   * SPDX-License-Identifier: GPL-2.0-or-later
   *
@@ -XXX,XX +XXX,XX @@
  /* B-L475E-IOT01A implementation is derived from netduinoplus2 */
 -static void b_l475e_iot01a_init(MachineState *machine)
 +#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
 +OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
 +
- #endif
++typedef struct Bl475eMachineState {
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
++    MachineState parent_obj;
-index XXXXXXX..XXXXXXX 100644
++
---- a/target/arm/cpu64.c
++    Stm32l4x5SocState soc;
-+++ b/target/arm/cpu64.c
++} Bl475eMachineState;
-@@ -XXX,XX +XXX,XX @@
++
- #include "hvf_arm.h"
++static void bl475e_init(MachineState *machine)
  #include "qapi/visitor.h"
  #include "hw/qdev-properties.h"
 -#include "cpregs.h"
 +#include "internals.h"
 -#ifndef CONFIG_USER_ONLY
 -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 -{
 -    ARMCPU *cpu = env_archcpu(env);
 -
 -    /* Number of cores is in [25:24]; otherwise we RAZ */
 -    return (cpu->core_count - 1) << 24;
 -}
 -#endif
 -
 -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
 -#ifndef CONFIG_USER_ONLY
 -    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
 -      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
 -      .writefn = arm_cp_write_ignore },
 -    { .name = "L2CTLR",
 -      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
 -      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
 -      .writefn = arm_cp_write_ignore },
 -#endif
 -    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2ECTLR",
 -      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUACTLR",
 -      .cp = 15, .opc1 = 0, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUECTLR",
 -      .cp = 15, .opc1 = 1, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUMERRSR",
 -      .cp = 15, .opc1 = 2, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2MERRSR",
 -      .cp = 15, .opc1 = 3, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -};
 -
  static void aarch64_a57_initfn(Object *obj)
  {
-     ARMCPU *cpu = ARM_CPU(obj);
++    Bl475eMachineState *s = B_L475E_IOT01A(machine);
-@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
+     const Stm32l4x5SocClass *sc;
-     cpu->gic_num_lrs = 4;
+-    DeviceState *dev;
-     cpu->gic_vpribits = 5;
-     cpu->gic_vprebits = 5;
+-    dev = qdev_new(TYPE_STM32L4X5XG_SOC);
--    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+-    object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
-+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 +    object_initialize_child(OBJECT(machine), "soc", &s->soc,
 +                            TYPE_STM32L4X5XG_SOC);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
 -    sc = STM32L4X5_SOC_GET_CLASS(dev);
 -    armv7m_load_kernel(ARM_CPU(first_cpu),
 -                       machine->kernel_filename,
 -                       0, sc->flash_size);
 +    sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
 +    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
 +                       sc->flash_size);
  }
- static void aarch64_a53_initfn(Object *obj)
+-static void b_l475e_iot01a_machine_init(MachineClass *mc)
-@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
++static void bl475e_machine_init(ObjectClass *oc, void *data)
-     cpu->gic_num_lrs = 4;
+ {
-     cpu->gic_vpribits = 5;
++    MachineClass *mc = MACHINE_CLASS(oc);
-     cpu->gic_vprebits = 5;
+     static const char *machine_valid_cpu_types[] = {
--    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+         ARM_CPU_TYPE_NAME("cortex-m4"),
-+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+         NULL
      };
      mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)";
 -    mc->init = b_l475e_iot01a_init;
 +    mc->init = bl475e_init;
      mc->valid_cpu_types = machine_valid_cpu_types;
      /* SRAM pre-allocated as part of the SoC instantiation */
      mc->default_ram_size = 0;
  }
- static void aarch64_a72_initfn(Object *obj)
+-DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init)
-@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
++static const TypeInfo bl475e_machine_type[] = {
-     cpu->gic_num_lrs = 4;
++    {
-     cpu->gic_vpribits = 5;
++        .name           = TYPE_B_L475E_IOT01A,
-     cpu->gic_vprebits = 5;
++        .parent         = TYPE_MACHINE,
--    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
++        .instance_size  = sizeof(Bl475eMachineState),
-+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
++        .class_init     = bl475e_machine_init,
- }
++    }
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #endif
  #include "cpregs.h"
 +#ifndef CONFIG_USER_ONLY
 +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +
 +    /* Number of cores is in [25:24]; otherwise we RAZ */
 +    return (cpu->core_count - 1) << 24;
 +}
 +
 +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
 +    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
 +      .access = PL1_RW, .readfn = l2ctlr_read,
 +      .writefn = arm_cp_write_ignore },
 +    { .name = "L2CTLR",
 +      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
 +      .access = PL1_RW, .readfn = l2ctlr_read,
 +      .writefn = arm_cp_write_ignore },
 +    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2ECTLR",
 +      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUACTLR",
 +      .cp = 15, .opc1 = 0, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUECTLR",
 +      .cp = 15, .opc1 = 1, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUMERRSR",
 +      .cp = 15, .opc1 = 2, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2MERRSR",
 +      .cp = 15, .opc1 = 3, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +};
 +
-+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
++DEFINE_TYPES(bl475e_machine_type)
 +{
 +    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +}
 +#endif /* !CONFIG_USER_ONLY */
 +
  /* CPU models. These are not needed for the AArch64 linux-user build. */
  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 --
-.25.1
+.34.1

-[PULL 17/32] target/arm: Implement ESB instruction
+[PULL 20/21] hw/arm : Connect DM163 to B-L475E-IOT01A
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
-Check for and defer any pending virtual SError.
+Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
+Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr
 Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.h        |  1 +
+ hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++--
- target/arm/a32.decode      | 16 ++++++++------
+ hw/arm/Kconfig          |  1 +
- target/arm/t32.decode      | 18 ++++++++--------
+files changed, 58 insertions(+), 2 deletions(-)
  target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-a64.c | 17 +++++++++++++++
  target/arm/translate.c     | 23 ++++++++++++++++++++
 files changed, 103 insertions(+), 15 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/hw/arm/b-l475e-iot01a.c
-+++ b/target/arm/helper.h
++++ b/hw/arm/b-l475e-iot01a.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
+@@ -XXX,XX +XXX,XX @@
- DEF_HELPER_1(yield, void, env)
+ #include "hw/boards.h"
- DEF_HELPER_1(pre_hvc, void, env)
+ #include "hw/qdev-properties.h"
- DEF_HELPER_2(pre_smc, void, env, i32)
+ #include "qemu/error-report.h"
-+DEF_HELPER_1(vesb, void, env)
+-#include "hw/arm/stm32l4x5_soc.h"
+ #include "hw/arm/boot.h"
- DEF_HELPER_3(cpsr_write, void, env, i32, i32)
++#include "hw/core/split-irq.h"
- DEF_HELPER_2(cpsr_write_eret, void, env, i32)
++#include "hw/arm/stm32l4x5_soc.h"
-diff --git a/target/arm/a32.decode b/target/arm/a32.decode
++#include "hw/gpio/stm32l4x5_gpio.h"
-index XXXXXXX..XXXXXXX 100644
++#include "hw/display/dm163.h"
---- a/target/arm/a32.decode
-+++ b/target/arm/a32.decode
+-/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
-@@ -XXX,XX +XXX,XX @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
++/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */
  {
    {
 -    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
 -    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
 -    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
 +    [
 +      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
 +      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
 +      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 -    # TODO: Implement SEV, SEVL; may help SMP performance.
 -    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
 -    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
 +      # TODO: Implement SEV, SEVL; may help SMP performance.
 +      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
 +      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
 +
 +      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
 +    ]
      # The canonical nop ends in 00000000, but the whole of the
      # rest of the space executes as nop if otherwise unsupported.
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
    [
      # Hints, and CPS
      {
 -      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
 -      WFE        1111 0011 1010 1111 1000 0000 0000 0010
 -      WFI        1111 0011 1010 1111 1000 0000 0000 0011
 +      [
 +        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
 +        WFE      1111 0011 1010 1111 1000 0000 0000 0010
 +        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 -      # TODO: Implement SEV, SEVL; may help SMP performance.
 -      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
 -      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
 +        # TODO: Implement SEV, SEVL; may help SMP performance.
 +        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
 +        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 -      # For M-profile minimal-RAS ESB can be a NOP, which is the
 -      # default behaviour since it is in the hint space.
 -      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +        ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +      ]
        # The canonical nop ends in 0000 0000, but the whole rest
        # of the space is "reserved hint, behaves as nop".
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/op_helper.c
 +++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                       access_type, mmu_idx, ra);
      }
  }
 +
 +/*
-+ * This function corresponds to AArch64.vESBOperation().
++ * There are actually 14 input pins in the DM163 device.
-+ * Note that the AArch32 version is not functionally different.
++ * Here the DM163 input pin EN isn't connected to the STM32L4x5
 + * GPIOs as the IM120417002 colors shield doesn't actually use
 + * this pin to drive the RGB matrix.
 + */
-+void HELPER(vesb)(CPUARMState *env)
++#define NUM_DM163_INPUTS 13
 +{
 +    /*
 +     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
 +     * and will return HCR_EL2.VSE == 0, so nothing happens.
 +     */
 +    uint64_t hcr = arm_hcr_el2_eff(env);
 +    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
 +    bool pending = enabled && (hcr & HCR_VSE);
 +    bool masked  = (env->daif & PSTATE_A);
 +
-+    /* If VSE pending and masked, defer the exception.  */
++static const unsigned dm163_input[NUM_DM163_INPUTS] = {
-+    if (pending && masked) {
++    1 * GPIO_NUM_PINS + 2,  /* ROW0  PB2       */
-+        uint32_t syndrome;
++    0 * GPIO_NUM_PINS + 15, /* ROW1  PA15      */
 +    0 * GPIO_NUM_PINS + 2,  /* ROW2  PA2       */
 +    0 * GPIO_NUM_PINS + 7,  /* ROW3  PA7       */
 +    0 * GPIO_NUM_PINS + 6,  /* ROW4  PA6       */
 +    0 * GPIO_NUM_PINS + 5,  /* ROW5  PA5       */
 +    1 * GPIO_NUM_PINS + 0,  /* ROW6  PB0       */
 +    0 * GPIO_NUM_PINS + 3,  /* ROW7  PA3       */
 +    0 * GPIO_NUM_PINS + 4,  /* SIN (SDA) PA4   */
 +    1 * GPIO_NUM_PINS + 1,  /* DCK (SCK) PB1   */
 +    2 * GPIO_NUM_PINS + 3,  /* RST_B (RST) PC3 */
 +    2 * GPIO_NUM_PINS + 4,  /* LAT_B (LAT) PC4 */
 +    2 * GPIO_NUM_PINS + 5,  /* SELBK (SB)  PC5 */
 +};
  #define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
  OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
@@ -XXX,XX +XXX,XX @@ typedef struct Bl475eMachineState {
      MachineState parent_obj;
      Stm32l4x5SocState soc;
 +    SplitIRQ gpio_splitters[NUM_DM163_INPUTS];
 +    DM163State dm163;
  } Bl475eMachineState;
  static void bl475e_init(MachineState *machine)
  {
      Bl475eMachineState *s = B_L475E_IOT01A(machine);
      const Stm32l4x5SocClass *sc;
 +    DeviceState *dev, *gpio_out_splitter;
 +    unsigned gpio, pin;
      object_initialize_child(OBJECT(machine), "soc", &s->soc,
                              TYPE_STM32L4X5XG_SOC);
@@ -XXX,XX +XXX,XX @@ static void bl475e_init(MachineState *machine)
      sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
      armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
                         sc->flash_size);
 +
-+        if (arm_el_is_aa64(env, 1)) {
++    if (object_class_by_name(TYPE_DM163)) {
-+            /* Copy across IDS and ISS from VSESR. */
++        object_initialize_child(OBJECT(machine), "dm163",
-+            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
++                                &s->dm163, TYPE_DM163);
-+        } else {
++        dev = DEVICE(&s->dm163);
-+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
++        qdev_realize(dev, NULL, &error_abort);
 +
-+            if (extended_addresses_enabled(env)) {
++        for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) {
-+                syndrome = arm_fi_to_lfsc(&fi);
++            object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]",
-+            } else {
++                                    &s->gpio_splitters[i], TYPE_SPLIT_IRQ);
-+                syndrome = arm_fi_to_sfsc(&fi);
++            gpio_out_splitter = DEVICE(&s->gpio_splitters[i]);
-+            }
++            qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2);
-+            /* Copy across AET and ExT from VSESR. */
++            qdev_realize(gpio_out_splitter, NULL, &error_fatal);
 +            syndrome |= env->cp15.vsesr_el2 & 0xd000;
 +        }
 +
-+        /* Set VDISR_EL2.A along with the syndrome. */
++            qdev_connect_gpio_out(gpio_out_splitter, 0,
-+        env->cp15.vdisr_el2 = syndrome | (1u << 31);
++                qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i]));
-+
++            qdev_connect_gpio_out(gpio_out_splitter, 1,
-+        /* Clear pending virtual SError */
++                qdev_get_gpio_in(dev, i));
-+        env->cp15.hcr_el2 &= ~HCR_VSE;
++            gpio = dm163_input[i] / GPIO_NUM_PINS;
-+        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
++            pin = dm163_input[i] % GPIO_NUM_PINS;
-+    }
++            qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin,
-+}
++                qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0));
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
              gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
          }
          break;
 +    case 0b10000: /* ESB */
 +        /* Without RAS, we must implement this as NOP. */
 +        if (dc_isar_feature(aa64_ras, s)) {
 +            /*
 +             * QEMU does not have a source of physical SErrors,
 +             * so we are only concerned with virtual SErrors.
 +             * The pseudocode in the ARM for this case is
 +             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
 +             *      AArch64.vESBOperation();
 +             * Most of the condition can be evaluated at translation time.
 +             * Test for EL2 present, and defer test for SEL2 to runtime.
 +             */
 +            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
 +                gen_helper_vesb(cpu_env);
 +            }
 +        }
 +        break;
      case 0b11000: /* PACIAZ */
          if (s->pauth_active) {
              gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
      return true;
  }
 +static bool trans_ESB(DisasContext *s, arg_ESB *a)
 +{
 +    /*
 +     * For M-profile, minimal-RAS ESB can be a NOP.
 +     * Without RAS, we must implement this as NOP.
 +     */
 +    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
 +        /*
 +         * QEMU does not have a source of physical SErrors,
 +         * so we are only concerned with virtual SErrors.
 +         * The pseudocode in the ARM for this case is
 +         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
 +         *      AArch32.vESBOperation();
 +         * Most of the condition can be evaluated at translation time.
 +         * Test for EL2 present, and defer test for SEL2 to runtime.
 +         */
 +        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
 +            gen_helper_vesb(cpu_env);
 +        }
 +    }
-+    return true;
+ }
-+}
-+
+ static void bl475e_machine_init(ObjectClass *oc, void *data)
- static bool trans_NOP(DisasContext *s, arg_NOP *a)
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
- {
+index XXXXXXX..XXXXXXX 100644
-     return true;
+--- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config B_L475E_IOT01A
      default y
      depends on TCG && ARM
      select STM32L4X5_SOC
 +    imply DM163
  config STM32L4X5_SOC
      bool
 --
-.25.1
+.34.1

-[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
+[PULL 21/21] tests/qtest : Add testcase for DM163
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
-Instead of starting with cortex-a15 and adding v8 features to
+`test_dm163_bank()`
-a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
+Checks that the pin "sout" of the DM163 led driver outputs the values
-This fixes the long-standing to-do where we only enabled v8
+received on pin "sin" with the expected latency (depending on the bank).
-features for user-only.
+`test_dm163_gpio_connection()`
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+DM163 device.
-Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
 Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
 Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
 Acked-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
+ tests/qtest/dm163-test.c | 194 +++++++++++++++++++++++++++++++++++++++
-file changed, 92 insertions(+), 59 deletions(-)
+ tests/qtest/meson.build  |   2 +
+files changed, 196 insertions(+)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
+ create mode 100644 tests/qtest/dm163-test.c
 diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/dm163-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTest testcase for DM163
 + *
 + * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
 + * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
 + *
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + */
 +
 +#include "qemu/osdep.h"
 +#include "libqtest.h"
 +
 +enum DM163_INPUTS {
 +    SIN = 8,
 +    DCK = 9,
 +    RST_B = 10,
 +    LAT_B = 11,
 +    SELBK = 12,
 +    EN_B = 13
 +};
 +
 +#define DEVICE_NAME "/machine/dm163"
 +#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name,   \
 +                                               value)
 +#define GPIO_PULSE(name)                                                       \
 +  do {                                                                         \
 +    GPIO_OUT(name, 1);                                                         \
 +    GPIO_OUT(name, 0);                                                         \
 +  } while (0)
 +
 +
 +static void rise_gpio_pin_dck(QTestState *qts)
 +{
 +    /* Configure output mode for pin PB1 */
 +    qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
 +    /* Write 1 in ODR for PB1 */
 +    qtest_writel(qts, 0x48000414, 0x00000002);
 +}
 +
 +static void lower_gpio_pin_dck(QTestState *qts)
 +{
 +    /* Configure output mode for pin PB1 */
 +    qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
 +    /* Write 0 in ODR for PB1 */
 +    qtest_writel(qts, 0x48000414, 0x00000000);
 +}
 +
 +static void rise_gpio_pin_selbk(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC5 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
 +    /* Write 1 in ODR for PC5 */
 +    qtest_writel(qts, 0x48000814, 0x00000020);
 +}
 +
 +static void lower_gpio_pin_selbk(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC5 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
 +    /* Write 0 in ODR for PC5 */
 +    qtest_writel(qts, 0x48000814, 0x00000000);
 +}
 +
 +static void rise_gpio_pin_lat_b(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC4 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
 +    /* Write 1 in ODR for PC4 */
 +    qtest_writel(qts, 0x48000814, 0x00000010);
 +}
 +
 +static void lower_gpio_pin_lat_b(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC4 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
 +    /* Write 0 in ODR for PC4 */
 +    qtest_writel(qts, 0x48000814, 0x00000000);
 +}
 +
 +static void rise_gpio_pin_rst_b(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC3 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
 +    /* Write 1 in ODR for PC3 */
 +    qtest_writel(qts, 0x48000814, 0x00000008);
 +}
 +
 +static void lower_gpio_pin_rst_b(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC3 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
 +    /* Write 0 in ODR for PC3 */
 +    qtest_writel(qts, 0x48000814, 0x00000000);
 +}
 +
 +static void rise_gpio_pin_sin(QTestState *qts)
 +{
 +    /* Configure output mode for pin PA4 */
 +    qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
 +    /* Write 1 in ODR for PA4 */
 +    qtest_writel(qts, 0x48000014, 0x00000010);
 +}
 +
 +static void lower_gpio_pin_sin(QTestState *qts)
 +{
 +    /* Configure output mode for pin PA4 */
 +    qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
 +    /* Write 0 in ODR for PA4 */
 +    qtest_writel(qts, 0x48000014, 0x00000000);
 +}
 +
 +static void test_dm163_bank(const void *opaque)
 +{
 +    const unsigned bank = (uintptr_t) opaque;
 +    const int width = bank ? 192 : 144;
 +
 +    QTestState *qts = qtest_initf("-M b-l475e-iot01a");
 +    qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout");
 +    GPIO_OUT(RST_B, 1);
 +    GPIO_OUT(EN_B, 0);
 +    GPIO_OUT(DCK, 0);
 +    GPIO_OUT(SELBK, bank);
 +    GPIO_OUT(LAT_B, 1);
 +
 +    /* Fill bank with zeroes */
 +    GPIO_OUT(SIN, 0);
 +    for (int i = 0; i < width; i++) {
 +        GPIO_PULSE(DCK);
 +    }
 +    /* Fill bank with ones, check that we get the previous zeroes */
 +    GPIO_OUT(SIN, 1);
 +    for (int i = 0; i < width; i++) {
 +        GPIO_PULSE(DCK);
 +        g_assert(!qtest_get_irq(qts, 0));
 +    }
 +
 +    /* Pulse one more bit in the bank, check that we get a one */
 +    GPIO_PULSE(DCK);
 +    g_assert(qtest_get_irq(qts, 0));
 +
 +    qtest_quit(qts);
 +}
 +
 +static void test_dm163_gpio_connection(void)
 +{
 +    QTestState *qts = qtest_init("-M b-l475e-iot01a");
 +    qtest_irq_intercept_in(qts, DEVICE_NAME);
 +
 +    g_assert_false(qtest_get_irq(qts, SIN));
 +    g_assert_false(qtest_get_irq(qts, DCK));
 +    g_assert_false(qtest_get_irq(qts, RST_B));
 +    g_assert_false(qtest_get_irq(qts, LAT_B));
 +    g_assert_false(qtest_get_irq(qts, SELBK));
 +
 +    rise_gpio_pin_dck(qts);
 +    g_assert_true(qtest_get_irq(qts, DCK));
 +    lower_gpio_pin_dck(qts);
 +    g_assert_false(qtest_get_irq(qts, DCK));
 +
 +    rise_gpio_pin_lat_b(qts);
 +    g_assert_true(qtest_get_irq(qts, LAT_B));
 +    lower_gpio_pin_lat_b(qts);
 +    g_assert_false(qtest_get_irq(qts, LAT_B));
 +
 +    rise_gpio_pin_selbk(qts);
 +    g_assert_true(qtest_get_irq(qts, SELBK));
 +    lower_gpio_pin_selbk(qts);
 +    g_assert_false(qtest_get_irq(qts, SELBK));
 +
 +    rise_gpio_pin_rst_b(qts);
 +    g_assert_true(qtest_get_irq(qts, RST_B));
 +    lower_gpio_pin_rst_b(qts);
 +    g_assert_false(qtest_get_irq(qts, RST_B));
 +
 +    rise_gpio_pin_sin(qts);
 +    g_assert_true(qtest_get_irq(qts, SIN));
 +    lower_gpio_pin_sin(qts);
 +    g_assert_false(qtest_get_irq(qts, SIN));
 +
 +    g_assert_false(qtest_get_irq(qts, DCK));
 +    g_assert_false(qtest_get_irq(qts, LAT_B));
 +    g_assert_false(qtest_get_irq(qts, SELBK));
 +    g_assert_false(qtest_get_irq(qts, RST_B));
 +}
 +
 +int main(int argc, char **argv)
 +{
 +    g_test_init(&argc, &argv, NULL);
 +    qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank);
 +    qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank);
 +    qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection);
 +    return g_test_run();
 +}
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
+--- a/tests/qtest/meson.build
-+++ b/target/arm/cpu_tcg.c
++++ b/tests/qtest/meson.build
-@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ qtests_arm = \
- static void arm_max_initfn(Object *obj)
+   (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
- {
+   (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
-     ARMCPU *cpu = ARM_CPU(obj);
+   (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
-+    uint32_t t;
++  (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and
++   config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \
--    cortex_a15_initfn(obj);
+   ['arm-cpu-features',
-+    /* aarch64_a57_initfn, advertising none of the aarch64 features */
+    'boot-serial-test']
 +    cpu->dtb_compatible = "arm,cortex-a57";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->midr = 0x411fd070;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034070;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x8444c004;
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10101105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_isar6 = 0;
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -    /* old-style VFP short-vector support */
 -    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 +    /* Add additional features supported by QEMU */
 +    t = cpu->isar.id_isar5;
 +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 +    cpu->isar.id_isar5 = t;
 +
 +    t = cpu->isar.id_isar6;
 +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 +    cpu->isar.id_isar6 = t;
 +
 +    t = cpu->isar.mvfr1;
 +    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 +    cpu->isar.mvfr1 = t;
 +
 +    t = cpu->isar.mvfr2;
 +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 +    cpu->isar.mvfr2 = t;
 +
 +    t = cpu->isar.id_mmfr3;
 +    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +    cpu->isar.id_mmfr3 = t;
 +
 +    t = cpu->isar.id_mmfr4;
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +    cpu->isar.id_mmfr4 = t;
 +
 +    t = cpu->isar.id_pfr0;
 +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 +    cpu->isar.id_pfr0 = t;
 +
 +    t = cpu->isar.id_pfr2;
 +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 +    cpu->isar.id_pfr2 = t;
  #ifdef CONFIG_USER_ONLY
      /*
 -     * We don't set these in system emulation mode for the moment,
 -     * since we don't correctly set (all of) the ID registers to
 -     * advertise them.
 +     * Break with true ARMv8 and add back old-style VFP short-vector support.
 +     * Only do this for user-mode, where -cpu max is the default, so that
 +     * older v6 and v7 programs are more likely to work without adjustment.
       */
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    {
 -        uint32_t t;
 -
 -        t = cpu->isar.id_isar5;
 -        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 -        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 -        cpu->isar.id_isar5 = t;
 -
 -        t = cpu->isar.id_isar6;
 -        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 -        cpu->isar.id_isar6 = t;
 -
 -        t = cpu->isar.mvfr1;
 -        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 -        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 -        cpu->isar.mvfr1 = t;
 -
 -        t = cpu->isar.mvfr2;
 -        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 -        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 -        cpu->isar.mvfr2 = t;
 -
 -        t = cpu->isar.id_mmfr3;
 -        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 -        cpu->isar.id_mmfr3 = t;
 -
 -        t = cpu->isar.id_mmfr4;
 -        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 -        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 -        cpu->isar.id_mmfr4 = t;
 -
 -        t = cpu->isar.id_pfr0;
 -        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 -        cpu->isar.id_pfr0 = t;
 -
 -        t = cpu->isar.id_pfr2;
 -        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 -        cpu->isar.id_pfr2 = t;
 -    }
 -#endif /* CONFIG_USER_ONLY */
 +    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 +#endif
  }
  #endif /* !TARGET_AARCH64 */
 --
-.25.1
+.34.1

-[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-We set this for qemu-system-aarch64, but failed to do so
-for the strictly 32-bit emulation.
-Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu_tcg.c | 4 ++++
-file changed, 4 insertions(+)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
-     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-     cpu->isar.id_pfr2 = t;
-+    t = cpu->isar.id_dfr0;
-+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-+    cpu->isar.id_dfr0 = t;
-+
- #ifdef CONFIG_USER_ONLY
-     /*
-      * Break with true ARMv8 and add back old-style VFP short-vector support.
---
-.25.1

-[PULL 09/32] target/arm: Split out aa32_max_features
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Share the code to set AArch32 max features so that we no
-longer have code drift between qemu{-system,}-{arm,aarch64}.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/internals.h |   2 +
- target/arm/cpu64.c     |  50 +-----------------
- target/arm/cpu_tcg.c   | 114 ++++++++++++++++++++++-------------------
-files changed, 65 insertions(+), 101 deletions(-)
-diff --git a/target/arm/internals.h b/target/arm/internals.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
-+++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
- void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
- #endif
-+void aa32_max_features(ARMCPU *cpu);
-+
- #endif
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
- {
-     ARMCPU *cpu = ARM_CPU(obj);
-     uint64_t t;
--    uint32_t u;
-     if (kvm_enabled() || hvf_enabled()) {
-         /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
-     cpu->isar.id_aa64zfr0 = t;
--    /* Replicate the same data to the 32-bit id registers.  */
--    u = cpu->isar.id_isar5;
--    u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
--    u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
--    u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
--    u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
--    u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
--    u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
--    cpu->isar.id_isar5 = u;
--
--    u = cpu->isar.id_isar6;
--    u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
--    u = FIELD_DP32(u, ID_ISAR6, DP, 1);
--    u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
--    u = FIELD_DP32(u, ID_ISAR6, SB, 1);
--    u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
--    u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
--    u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
--    cpu->isar.id_isar6 = u;
--
--    u = cpu->isar.id_pfr0;
--    u = FIELD_DP32(u, ID_PFR0, DIT, 1);
--    cpu->isar.id_pfr0 = u;
--
--    u = cpu->isar.id_pfr2;
--    u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
--    cpu->isar.id_pfr2 = u;
--
--    u = cpu->isar.id_mmfr3;
--    u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
--    cpu->isar.id_mmfr3 = u;
--
--    u = cpu->isar.id_mmfr4;
--    u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
--    u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
--    u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
--    u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
--    cpu->isar.id_mmfr4 = u;
--
-     t = cpu->isar.id_aa64dfr0;
-     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
-     cpu->isar.id_aa64dfr0 = t;
--    u = cpu->isar.id_dfr0;
--    u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
--    cpu->isar.id_dfr0 = u;
--
--    u = cpu->isar.mvfr1;
--    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
--    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
--    cpu->isar.mvfr1 = u;
-+    /* Replicate the same data to the 32-bit id registers.  */
-+    aa32_max_features(cpu);
- #ifdef CONFIG_USER_ONLY
-     /*
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@
- #endif
- #include "cpregs.h"
-+
-+/* Share AArch32 -cpu max features with AArch64. */
-+void aa32_max_features(ARMCPU *cpu)
-+{
-+    uint32_t t;
-+
-+    /* Add additional features supported by QEMU */
-+    t = cpu->isar.id_isar5;
-+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-+    cpu->isar.id_isar5 = t;
-+
-+    t = cpu->isar.id_isar6;
-+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-+    cpu->isar.id_isar6 = t;
-+
-+    t = cpu->isar.mvfr1;
-+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-+    cpu->isar.mvfr1 = t;
-+
-+    t = cpu->isar.mvfr2;
-+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-+    cpu->isar.mvfr2 = t;
-+
-+    t = cpu->isar.id_mmfr3;
-+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-+    cpu->isar.id_mmfr3 = t;
-+
-+    t = cpu->isar.id_mmfr4;
-+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-+    cpu->isar.id_mmfr4 = t;
-+
-+    t = cpu->isar.id_pfr0;
-+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-+    cpu->isar.id_pfr0 = t;
-+
-+    t = cpu->isar.id_pfr2;
-+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-+    cpu->isar.id_pfr2 = t;
-+
-+    t = cpu->isar.id_dfr0;
-+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-+    cpu->isar.id_dfr0 = t;
-+}
-+
- #ifndef CONFIG_USER_ONLY
- static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
- {
-@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
- static void arm_max_initfn(Object *obj)
- {
-     ARMCPU *cpu = ARM_CPU(obj);
--    uint32_t t;
-     /* aarch64_a57_initfn, advertising none of the aarch64 features */
-     cpu->dtb_compatible = "arm,cortex-a57";
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
-     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
-     define_cortex_a72_a57_a53_cp_reginfo(cpu);
--    /* Add additional features supported by QEMU */
--    t = cpu->isar.id_isar5;
--    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
--    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
--    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
--    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
--    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
--    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
--    cpu->isar.id_isar5 = t;
--
--    t = cpu->isar.id_isar6;
--    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
--    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
--    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
--    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
--    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
--    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
--    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
--    cpu->isar.id_isar6 = t;
--
--    t = cpu->isar.mvfr1;
--    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
--    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
--    cpu->isar.mvfr1 = t;
--
--    t = cpu->isar.mvfr2;
--    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
--    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
--    cpu->isar.mvfr2 = t;
--
--    t = cpu->isar.id_mmfr3;
--    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
--    cpu->isar.id_mmfr3 = t;
--
--    t = cpu->isar.id_mmfr4;
--    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
--    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
--    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
--    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
--    cpu->isar.id_mmfr4 = t;
--
--    t = cpu->isar.id_pfr0;
--    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
--    cpu->isar.id_pfr0 = t;
--
--    t = cpu->isar.id_pfr2;
--    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
--    cpu->isar.id_pfr2 = t;
--
--    t = cpu->isar.id_dfr0;
--    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
--    cpu->isar.id_dfr0 = t;
-+    aa32_max_features(cpu);
- #ifdef CONFIG_USER_ONLY
-     /*
---
-.25.1

-[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Update the legacy feature names to the current names.
-Provide feature names for id changes that were not marked.
-Sort the field updates into increasing bitfield order.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu64.c   | 100 +++++++++++++++++++++----------------------
- target/arm/cpu_tcg.c |  48 ++++++++++-----------
-files changed, 74 insertions(+), 74 deletions(-)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     cpu->midr = t;
-     t = cpu->isar.id_aa64isar0;
--    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
--    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
-     t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
--    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
--    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
--    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
-+    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
-     cpu->isar.id_aa64isar0 = t;
-     t = cpu->isar.id_aa64isar1;
--    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
--    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
--    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
--    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
-+    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
-+    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
-     cpu->isar.id_aa64isar1 = t;
-     t = cpu->isar.id_aa64pfr0;
-+    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
-+    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
-     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
--    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
--    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
--    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
--    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
-+    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
-+    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-     cpu->isar.id_aa64pfr0 = t;
-     t = cpu->isar.id_aa64pfr1;
--    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
--    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
-+    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
-+    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
-     /*
-      * Begin with full support for MTE. This will be downgraded to MTE=0
-      * during realize if the board provides no tag memory, much like
-      * we do for EL2 with the virtualization=on property.
-      */
--    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
-+    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
-     cpu->isar.id_aa64pfr1 = t;
-     t = cpu->isar.id_aa64mmfr0;
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     cpu->isar.id_aa64mmfr0 = t;
-     t = cpu->isar.id_aa64mmfr1;
--    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
--    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
--    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
--    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
--    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
--    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
-+    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
-+    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
-+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
-+    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
-+    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
-+    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-     cpu->isar.id_aa64mmfr1 = t;
-     t = cpu->isar.id_aa64mmfr2;
--    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
--    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
--    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
--    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
--    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
--    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
-+    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
-+    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
-+    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
-+    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
-+    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
-+    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
-     cpu->isar.id_aa64mmfr2 = t;
-     t = cpu->isar.id_aa64zfr0;
-     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
--    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
--    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
--    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
--    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
--    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
--    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
--    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
--    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
-+    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
-+    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
-+    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
-+    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
-+    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
-+    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
-+    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
-+    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
-     cpu->isar.id_aa64zfr0 = t;
-     t = cpu->isar.id_aa64dfr0;
--    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
-+    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
-     cpu->isar.id_aa64dfr0 = t;
-     /* Replicate the same data to the 32-bit id registers.  */
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     /* Add additional features supported by QEMU */
-     t = cpu->isar.id_isar5;
--    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
--    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
--    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
-+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
-+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
-     t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
--    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
--    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
-+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
-     cpu->isar.id_isar5 = t;
-     t = cpu->isar.id_isar6;
--    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
--    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
--    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
--    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
--    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
--    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
--    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
-+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
-+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
-+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
-+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
-+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
-+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
-     cpu->isar.id_isar6 = t;
-     t = cpu->isar.mvfr1;
--    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
--    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-+    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
-+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
-     cpu->isar.mvfr1 = t;
-     t = cpu->isar.mvfr2;
--    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
--    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
-+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
-     cpu->isar.mvfr2 = t;
-     t = cpu->isar.id_mmfr3;
--    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
-     cpu->isar.id_mmfr3 = t;
-     t = cpu->isar.id_mmfr4;
--    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
--    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
--    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
--    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
-+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
-+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
-+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
-     cpu->isar.id_mmfr4 = t;
-     t = cpu->isar.id_pfr0;
--    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
-     cpu->isar.id_pfr0 = t;
-     t = cpu->isar.id_pfr2;
--    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
-     cpu->isar.id_pfr2 = t;
-     t = cpu->isar.id_dfr0;
--    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
-     cpu->isar.id_dfr0 = t;
- }
---
-.25.1

-[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
-during arm_cpu_realizefn.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.c | 22 +++++++++++++---------
-file changed, 13 insertions(+), 9 deletions(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-          */
-         unset_feature(env, ARM_FEATURE_EL3);
--        /* Disable the security extension feature bits in the processor feature
--         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
-+        /*
-+         * Disable the security extension feature bits in the processor
-+         * feature registers as well.
-          */
--        cpu->isar.id_pfr1 &= ~0xf0;
--        cpu->isar.id_aa64pfr0 &= ~0xf000;
-+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
-+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-+                                           ID_AA64PFR0, EL3, 0);
-     }
-     if (!cpu->has_el2) {
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-     }
-     if (!arm_feature(env, ARM_FEATURE_EL2)) {
--        /* Disable the hypervisor feature bits in the processor feature
--         * registers if we don't have EL2. These are id_pfr1[15:12] and
--         * id_aa64pfr0_el1[11:8].
-+        /*
-+         * Disable the hypervisor feature bits in the processor feature
-+         * registers if we don't have EL2.
-          */
--        cpu->isar.id_aa64pfr0 &= ~0xf00;
--        cpu->isar.id_pfr1 &= ~0xf000;
-+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-+                                           ID_AA64PFR0, EL2, 0);
-+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
-+                                       ID_PFR1, VIRTUALIZATION, 0);
-     }
- #ifndef CONFIG_USER_ONLY
---
-.25.1

-[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The only portion of FEAT_Debugv8p2 that is relevant to QEMU
-is CONTEXTIDR_EL2, which is also conditionally implemented
-with FEAT_VHE.  The rest of the debug extension concerns the
-External debug interface, which is outside the scope of QEMU.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu.c              | 1 +
- target/arm/cpu64.c            | 1 +
- target/arm/cpu_tcg.c          | 2 ++
-files changed, 5 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_BTI (Branch Target Identification)
- - FEAT_DIT (Data Independent Timing instructions)
- - FEAT_DPB (DC CVAP instruction)
-+- FEAT_Debugv8p2 (Debug changes for v8.2)
- - FEAT_DotProd (Advanced SIMD dot product instructions)
- - FEAT_FCMA (Floating-point complex number instructions)
- - FEAT_FHM (Floating-point half-precision multiplication instructions)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-          * feature registers as well.
-          */
-         cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
-+        cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
-         cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-                                            ID_AA64PFR0, EL3, 0);
-     }
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     cpu->isar.id_aa64zfr0 = t;
-     t = cpu->isar.id_aa64dfr0;
-+    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8);  /* FEAT_Debugv8p2 */
-     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
-     cpu->isar.id_aa64dfr0 = t;
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     cpu->isar.id_pfr2 = t;
-     t = cpu->isar.id_dfr0;
-+    t = FIELD_DP32(t, ID_DFR0, COPDBG, 8);        /* FEAT_Debugv8p2 */
-+    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8);       /* FEAT_Debugv8p2 */
-     t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
-     cpu->isar.id_dfr0 = t;
- }
---
-.25.1

-[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This extension concerns changes to the External Debug interface,
-with Secure and Non-secure access to the debug registers, and all
-of it is outside the scope of QEMU.  Indicating support for this
-is mandatory with FEAT_SEL2, which we do implement.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 2 +-
- target/arm/cpu_tcg.c          | 4 ++--
-files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_DIT (Data Independent Timing instructions)
- - FEAT_DPB (DC CVAP instruction)
- - FEAT_Debugv8p2 (Debug changes for v8.2)
-+- FEAT_Debugv8p4 (Debug changes for v8.4)
- - FEAT_DotProd (Advanced SIMD dot product instructions)
- - FEAT_FCMA (Floating-point complex number instructions)
- - FEAT_FHM (Floating-point half-precision multiplication instructions)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     cpu->isar.id_aa64zfr0 = t;
-     t = cpu->isar.id_aa64dfr0;
--    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8);  /* FEAT_Debugv8p2 */
-+    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9);  /* FEAT_Debugv8p4 */
-     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
-     cpu->isar.id_aa64dfr0 = t;
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     cpu->isar.id_pfr2 = t;
-     t = cpu->isar.id_dfr0;
--    t = FIELD_DP32(t, ID_DFR0, COPDBG, 8);        /* FEAT_Debugv8p2 */
--    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8);       /* FEAT_Debugv8p2 */
-+    t = FIELD_DP32(t, ID_DFR0, COPDBG, 9);        /* FEAT_Debugv8p4 */
-+    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9);       /* FEAT_Debugv8p4 */
-     t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
-     cpu->isar.id_dfr0 = t;
- }
---
-.25.1

-[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 1 +
- target/arm/cpu_tcg.c          | 1 +
-files changed, 3 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
-+++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_PMULL (PMULL, PMULL2 instructions)
- - FEAT_PMUv3p1 (PMU Extensions v3.1)
- - FEAT_PMUv3p4 (PMU Extensions v3.4)
-+- FEAT_RAS (Reliability, availability, and serviceability)
- - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
- - FEAT_RNG (Random number generator)
- - FEAT_SB (Speculation Barrier)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     t = cpu->isar.id_aa64pfr0;
-     t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
-     t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
-+    t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1);       /* FEAT_RAS */
-     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
-     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-     t = cpu->isar.id_pfr0;
-     t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
-+    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
-     cpu->isar.id_pfr0 = t;
-     t = cpu->isar.id_pfr2;
---
-.25.1

-[PULL 24/32] target/arm: Define cortex-a76
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Enable the a76 for virt and sbsa board use.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/virt.rst |  1 +
- hw/arm/sbsa-ref.c        |  1 +
- hw/arm/virt.c            |  1 +
- target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
-files changed, 69 insertions(+)
-diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/virt.rst
-+++ b/docs/system/arm/virt.rst
-@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
- - ``cortex-a53`` (64-bit)
- - ``cortex-a57`` (64-bit)
- - ``cortex-a72`` (64-bit)
-+- ``cortex-a76`` (64-bit)
- - ``a64fx`` (64-bit)
- - ``host`` (with KVM only)
- - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
-diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/sbsa-ref.c
-+++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
- static const char * const valid_cpus[] = {
-     ARM_CPU_TYPE_NAME("cortex-a57"),
-     ARM_CPU_TYPE_NAME("cortex-a72"),
-+    ARM_CPU_TYPE_NAME("cortex-a76"),
-     ARM_CPU_TYPE_NAME("max"),
- };
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
-+++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
-     ARM_CPU_TYPE_NAME("cortex-a53"),
-     ARM_CPU_TYPE_NAME("cortex-a57"),
-     ARM_CPU_TYPE_NAME("cortex-a72"),
-+    ARM_CPU_TYPE_NAME("cortex-a76"),
-     ARM_CPU_TYPE_NAME("a64fx"),
-     ARM_CPU_TYPE_NAME("host"),
-     ARM_CPU_TYPE_NAME("max"),
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
-     define_cortex_a72_a57_a53_cp_reginfo(cpu);
- }
-+static void aarch64_a76_initfn(Object *obj)
-+{
-+    ARMCPU *cpu = ARM_CPU(obj);
-+
-+    cpu->dtb_compatible = "arm,cortex-a76";
-+    set_feature(&cpu->env, ARM_FEATURE_V8);
-+    set_feature(&cpu->env, ARM_FEATURE_NEON);
-+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-+    set_feature(&cpu->env, ARM_FEATURE_EL2);
-+    set_feature(&cpu->env, ARM_FEATURE_EL3);
-+    set_feature(&cpu->env, ARM_FEATURE_PMU);
-+
-+    /* Ordered by B2.4 AArch64 registers by functional group */
-+    cpu->clidr = 0x82000023;
-+    cpu->ctr = 0x8444C004;
-+    cpu->dcz_blocksize = 4;
-+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
-+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
-+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
-+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
-+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
-+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
-+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
-+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
-+    cpu->id_afr0       = 0x00000000;
-+    cpu->isar.id_dfr0  = 0x04010088;
-+    cpu->isar.id_isar0 = 0x02101110;
-+    cpu->isar.id_isar1 = 0x13112111;
-+    cpu->isar.id_isar2 = 0x21232042;
-+    cpu->isar.id_isar3 = 0x01112131;
-+    cpu->isar.id_isar4 = 0x00010142;
-+    cpu->isar.id_isar5 = 0x01011121;
-+    cpu->isar.id_isar6 = 0x00000010;
-+    cpu->isar.id_mmfr0 = 0x10201105;
-+    cpu->isar.id_mmfr1 = 0x40000000;
-+    cpu->isar.id_mmfr2 = 0x01260000;
-+    cpu->isar.id_mmfr3 = 0x02122211;
-+    cpu->isar.id_mmfr4 = 0x00021110;
-+    cpu->isar.id_pfr0  = 0x10010131;
-+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
-+    cpu->isar.id_pfr2  = 0x00000011;
-+    cpu->midr = 0x414fd0b1;          /* r4p1 */
-+    cpu->revidr = 0;
-+
-+    /* From B2.18 CCSIDR_EL1 */
-+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
-+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
-+    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
-+
-+    /* From B2.93 SCTLR_EL3 */
-+    cpu->reset_sctlr = 0x30c50838;
-+
-+    /* From B4.23 ICH_VTR_EL2 */
-+    cpu->gic_num_lrs = 4;
-+    cpu->gic_vpribits = 5;
-+    cpu->gic_vprebits = 5;
-+
-+    /* From B5.1 AdvSIMD AArch64 register summary */
-+    cpu->isar.mvfr0 = 0x10110222;
-+    cpu->isar.mvfr1 = 0x13211111;
-+    cpu->isar.mvfr2 = 0x00000043;
-+}
-+
- void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
- {
-     /*
-@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
-     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
-     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
-     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
-+    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
-     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
-     { .name = "max",                .initfn = aarch64_max_initfn },
- #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
---
-.25.1

target-arm queue: the big stuff here is the final part of
rth's patches for Cortex-A76 and Neoverse-N1 support;
also present are Gavin's NUMA series and a few other things.

thanks
-- PMM

The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:

Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509

for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:

hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)

----------------------------------------------------------------
target-arm queue:
 * MAINTAINERS/.mailmap: update email for Leif Lindholm
 * hw/arm: add version information to sbsa-ref machine DT
 * Enable new features for -cpu max:
   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
   FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
 * Emulate Cortex-A76
 * Emulate Neoverse-N1
 * Fix the virt board default NUMA topology

----------------------------------------------------------------
Gavin Shan (6):
      qapi/machine.json: Add cluster-id
      qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
      hw/arm/virt: Consider SMP configuration in CPU topology
      qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
      hw/arm/virt: Fix CPU's default NUMA node ID
      hw/acpi/aml-build: Use existing CPU topology to build PPTT table

Leif Lindholm (2):
      MAINTAINERS/.mailmap: update email for Leif Lindholm
      hw/arm: add versioning to sbsa-ref machine DT

Richard Henderson (24):
      target/arm: Handle cpreg registration for missing EL
      target/arm: Drop EL3 no EL2 fallbacks
      target/arm: Merge zcr reginfo
      target/arm: Adjust definition of CONTEXTIDR_EL2
      target/arm: Move cortex impdef sysregs to cpu_tcg.c
      target/arm: Update qemu-system-arm -cpu max to cortex-a57
      target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
      target/arm: Split out aa32_max_features
      target/arm: Annotate arm_max_initfn with FEAT identifiers
      target/arm: Use field names for manipulating EL2 and EL3 modes
      target/arm: Enable FEAT_Debugv8p2 for -cpu max
      target/arm: Enable FEAT_Debugv8p4 for -cpu max
      target/arm: Add minimal RAS registers
      target/arm: Enable SCR and HCR bits for RAS
      target/arm: Implement virtual SError exceptions
      target/arm: Implement ESB instruction
      target/arm: Enable FEAT_RAS for -cpu max
      target/arm: Enable FEAT_IESB for -cpu max
      target/arm: Enable FEAT_CSV2 for -cpu max
      target/arm: Enable FEAT_CSV2_2 for -cpu max
      target/arm: Enable FEAT_CSV3 for -cpu max
      target/arm: Enable FEAT_DGH for -cpu max
      target/arm: Define cortex-a76
      target/arm: Define neoverse-n1

From: Leif Lindholm <quic_llindhol@quicinc.com>

NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innovation Center (quicinc), so update
my email address to reflect this.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[Fixed commit message typo]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 .mailmap    | 3 ++-
 MAINTAINERS | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.mailmap b/.mailmap
index XXXXXXX..XXXXXXX 100644
--- a/.mailmap
+++ b/.mailmap
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
 James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
 Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
 Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
 Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
 SBSA-REF
 M: Radoslaw Biernacki <rad@semihalf.com>
 M: Peter Maydell <peter.maydell@linaro.org>
-R: Leif Lindholm <leif@nuviainc.com>
+R: Leif Lindholm <quic_llindhol@quicinc.com>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/sbsa-ref.c
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.

Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.

This will simplify cpreg registration for conditional arm features.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h |  11 +++
 target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
 2 files changed, 133 insertions(+), 56 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SVE                   = 1 << 14,
     /* Flag: Do not expose in gdb sysreg xml. */
     ARM_CP_NO_GDB                = 1 << 15,
+    /*
+     * Flags: If EL3 but not EL2...
+     *   - UNDEF: discard the cpreg,
+     *   -  KEEP: retain the cpreg as is,
+     *   -  C_NZ: set const on the cpreg, but retain resetvalue,
+     *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
+     * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+     */
+    ARM_CP_EL3_NO_EL2_UNDEF      = 1 << 16,
+    ARM_CP_EL3_NO_EL2_KEEP       = 1 << 17,
+    ARM_CP_EL3_NO_EL2_C_NZ       = 1 << 18,
 };
 
 /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
+      .access = PL2_RW,
+      .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
       .writefn = dacr_write, .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
       .type = ARM_CP_ALIAS,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .writefn = tlbimva_hyp_is_write },
     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2_write },
     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2_write },
     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2_write },
     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2is_write },
     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
 #ifndef CONFIG_USER_ONLY
     /* Unlike the other EL2-related AT operations, these must
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
       .access = PL2_W, .accessfn = at_s1e2_access,
-      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn = ats_write64 },
     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
       .access = PL2_W, .accessfn = at_s1e2_access,
-      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn = ats_write64 },
     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .accessfn = access_tda,
-      .type = ARM_CP_NOP },
+      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
     /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
      * Channel but Linux may try to access this register. The 32-bit
      * alias is DBGDCCINT.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
    { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NOP },
    { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
    { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2_write },
    { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2_write },
    { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2is_write },
     { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
    { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .writefn = tlbi_aa64_alle1is_write },
     { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL2_RW, .accessfn = access_el3_aa32ns,
-              .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
+              .resetvalue = cpu->midr,
+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL2_RW, .resetvalue = cpu->midr,
+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
               .access = PL2_RW, .accessfn = access_el3_aa32ns,
-              .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
+              .resetvalue = vmpidr_def,
+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-              .access = PL2_RW,
-              .resetvalue = vmpidr_def,
+              .access = PL2_RW, .resetvalue = vmpidr_def,
+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
         };
         define_arm_cp_regs(cpu, vpidr_regs);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
+    CPUARMState *env = &cpu->env;
     uint32_t key;
     ARMCPRegInfo *r2;
     bool is64 = r->type & ARM_CP_64BIT;
     bool ns = secstate & ARM_CP_SECSTATE_NS;
     int cp = r->cp;
-    bool isbanked;
     size_t name_len;
+    bool make_const;
 
     switch (state) {
     case ARM_CP_STATE_AA32:
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
     }
 
+    /*
+     * Eliminate registers that are not present because the EL is missing.
+     * Doing this here makes it easier to put all registers for a given
+     * feature into the same ARMCPRegInfo array and define them all at once.
+     */
+    make_const = false;
+    if (arm_feature(env, ARM_FEATURE_EL3)) {
+        /*
+         * An EL2 register without EL2 but with EL3 is (usually) RES0.
+         * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+         */
+        int min_el = ctz32(r->access) / 2;
+        if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
+            if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
+                return;
+            }
+            make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
+        }
+    } else {
+        CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
+                                 ? PL2_RW : PL1_RW);
+        if ((r->access & max_el) == 0) {
+            return;
+        }
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         r2->opaque = opaque;
     }
 
-    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
-    if (isbanked) {
+    if (make_const) {
+        /* This should not have been a very special register to begin. */
+        int old_special = r2->type & ARM_CP_SPECIAL_MASK;
+        assert(old_special == 0 || old_special == ARM_CP_NOP);
         /*
-         * Register is banked (using both entries in array).
-         * Overwriting fieldoffset as the array is only used to define
-         * banked registers but later only fieldoffset is used.
+         * Set the special function to CONST, retaining the other flags.
+         * This is important for e.g. ARM_CP_SVE so that we still
+         * take the SVE trap if CPTR_EL3.EZ == 0.
          */
-        r2->fieldoffset = r->bank_fieldoffsets[ns];
-    }
+        r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
+        /*
+         * Usually, these registers become RES0, but there are a few
+         * special cases like VPIDR_EL2 which have a constant non-zero
+         * value with writes ignored.
+         */
+        if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
+            r2->resetvalue = 0;
+        }
+        /*
+         * ARM_CP_CONST has precedence, so removing the callbacks and
+         * offsets are not strictly necessary, but it is potentially
+         * less confusing to debug later.
+         */
+        r2->readfn = NULL;
+        r2->writefn = NULL;
+        r2->raw_readfn = NULL;
+        r2->raw_writefn = NULL;
+        r2->resetfn = NULL;
+        r2->fieldoffset = 0;
+        r2->bank_fieldoffsets[0] = 0;
+        r2->bank_fieldoffsets[1] = 0;
+    } else {
+        bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 
-    if (state == ARM_CP_STATE_AA32) {
         if (isbanked) {
             /*
-             * If the register is banked then we don't need to migrate or
-             * reset the 32-bit instance in certain cases:
-             *
-             * 1) If the register has both 32-bit and 64-bit instances then we
-             *    can count on the 64-bit instance taking care of the
-             *    non-secure bank.
-             * 2) If ARMv8 is enabled then we can count on a 64-bit version
-             *    taking care of the secure bank.  This requires that separate
-             *    32 and 64-bit definitions are provided.
+             * Register is banked (using both entries in array).
+             * Overwriting fieldoffset as the array is only used to define
+             * banked registers but later only fieldoffset is used.
              */
-            if ((r->state == ARM_CP_STATE_BOTH && ns) ||
-                (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
+            r2->fieldoffset = r->bank_fieldoffsets[ns];
+        }
+        if (state == ARM_CP_STATE_AA32) {
+            if (isbanked) {
+                /*
+                 * If the register is banked then we don't need to migrate or
+                 * reset the 32-bit instance in certain cases:
+                 *
+                 * 1) If the register has both 32-bit and 64-bit instances
+                 *    then we can count on the 64-bit instance taking care
+                 *    of the non-secure bank.
+                 * 2) If ARMv8 is enabled then we can count on a 64-bit
+                 *    version taking care of the secure bank.  This requires
+                 *    that separate 32 and 64-bit definitions are provided.
+                 */
+                if ((r->state == ARM_CP_STATE_BOTH && ns) ||
+                    (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
+                    r2->type |= ARM_CP_ALIAS;
+                }
+            } else if ((secstate != r->secure) && !ns) {
+                /*
+                 * The register is not banked so we only want to allow
+                 * migration of the non-secure instance.
+                 */
                 r2->type |= ARM_CP_ALIAS;
             }
-        } else if ((secstate != r->secure) && !ns) {
-            /*
-             * The register is not banked so we only want to allow migration
-             * of the non-secure instance.
-             */
-            r2->type |= ARM_CP_ALIAS;
-        }
 
-        if (HOST_BIG_ENDIAN &&
-            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
-            r2->fieldoffset += sizeof(uint32_t);
+            if (HOST_BIG_ENDIAN &&
+                r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
+                r2->fieldoffset += sizeof(uint32_t);
+            }
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * multiple times. Special registers (ie NOP/WFI) are
      * never migratable and not even raw-accessible.
      */
-    if (r->type & ARM_CP_SPECIAL_MASK) {
+    if (r2->type & ARM_CP_SPECIAL_MASK) {
         r2->type |= ARM_CP_NO_RAW;
     }
     if (((r->crm == CP_ANY) && crm != 0) ||
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.

This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that the virtualization cpregs
are now correctly not present.  This would be a migration compatibility
break, except that we have an existing bug in which migration of 32-bit
cpus with Security Extensions enabled does not work.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 158 ++++----------------------------------------
 1 file changed, 13 insertions(+), 145 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
 };
 
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
-    { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
-      .access = PL2_RW,
-      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
-    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 6, .crm = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
-      .access = PL2_RW, .accessfn = access_tda,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
-      .type = ARM_CP_CONST,
-      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .resetvalue = 0 },
-};
-
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
-    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-};
-
 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, v8_idregs);
         define_arm_cp_regs(cpu, v8_cp_reginfo);
     }
-    if (arm_feature(env, ARM_FEATURE_EL2)) {
+
+    /*
+     * Register the base EL2 cpregs.
+     * Pre v8, these registers are implemented only as part of the
+     * Virtualization Extensions (EL2 present).  Beginning with v8,
+     * if EL2 is missing but EL3 is enabled, mostly these become
+     * RES0 from EL3, with some specific exceptions.
+     */
+    if (arm_feature(env, ARM_FEATURE_EL2)
+        || (arm_feature(env, ARM_FEATURE_EL3)
+            && arm_feature(env, ARM_FEATURE_V8))) {
         uint64_t vmpidr_def = mpidr_read_val(env);
         ARMCPRegInfo vpidr_regs[] = {
             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             };
             define_one_arm_cp_reg(cpu, &rvbar);
         }
-    } else {
-        /* If EL2 is missing but higher ELs are enabled, we need to
-         * register the no_el2 reginfos.
-         */
-        if (arm_feature(env, ARM_FEATURE_EL3)) {
-            /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
-             * of MIDR_EL1 and MPIDR_EL1.
-             */
-            ARMCPRegInfo vpidr_regs[] = {
-                { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
-                  .type = ARM_CP_CONST, .resetvalue = cpu->midr,
-                  .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
-                { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
-                  .type = ARM_CP_NO_RAW,
-                  .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
-            };
-            define_arm_cp_regs(cpu, vpidr_regs);
-            define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
-            if (arm_feature(env, ARM_FEATURE_V8)) {
-                define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
-            }
-        }
     }
+
+    /* Register the base EL3 cpregs. */
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         define_arm_cp_regs(cpu, el3_cp_reginfo);
         ARMCPRegInfo el3_regs[] = {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 55 ++++++++++++++-------------------------------
 1 file changed, 17 insertions(+), 38 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 }
 
-static const ARMCPRegInfo zcr_el1_reginfo = {
-    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL1_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
-    .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_el2_reginfo = {
-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL2_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
-    .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL2_RW, .type = ARM_CP_SVE,
-    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
-};
-
-static const ARMCPRegInfo zcr_el3_reginfo = {
-    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL3_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
-    .writefn = zcr_write, .raw_writefn = raw_write
+static const ARMCPRegInfo zcr_reginfo[] = {
+    { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
+    { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
+    { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL3_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
 };
 
 void hw_watchpoint_update(ARMCPU *cpu, int n)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (cpu_isar_feature(aa64_sve, cpu)) {
-        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
-        if (arm_feature(env, ARM_FEATURE_EL2)) {
-            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
-        } else {
-            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
-        }
-        if (arm_feature(env, ARM_FEATURE_EL3)) {
-            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
-        }
+        define_arm_cp_regs(cpu, zcr_reginfo);
     }
 
 #ifdef TARGET_AARCH64
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This register is present for either VHE or Debugv8p2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 };
 
+static const ARMCPRegInfo contextidr_el2 = {
+    .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+    .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+    .access = PL2_RW,
+    .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
 static const ARMCPRegInfo vhe_reginfo[] = {
-    { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
-      .access = PL2_RW,
-      .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
     }
 
+    if (cpu_isar_feature(aa64_vh, cpu) ||
+        cpu_isar_feature(aa64_debugv8p2, cpu)) {
+        define_one_arm_cp_reg(cpu, &contextidr_el2);
+    }
     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
         define_arm_cp_regs(cpu, vhe_reginfo);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.

This will shortly be used from cpu_tcg.c also.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h |  6 ++++
 target/arm/cpu64.c     | 64 +++---------------------------------------
 target/arm/cpu_tcg.c   | 59 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+), 60 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
 #endif
 
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "hvf_arm.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
-#include "cpregs.h"
+#include "internals.h"
 
 
-#ifndef CONFIG_USER_ONLY
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
-    ARMCPU *cpu = env_archcpu(env);
-
-    /* Number of cores is in [25:24]; otherwise we RAZ */
-    return (cpu->core_count - 1) << 24;
-}
-#endif
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
-#ifndef CONFIG_USER_ONLY
-    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
-    { .name = "L2CTLR",
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
-#endif
-    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2ECTLR",
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUACTLR",
-      .cp = 15, .opc1 = 0, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUECTLR",
-      .cp = 15, .opc1 = 1, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUMERRSR",
-      .cp = 15, .opc1 = 2, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2MERRSR",
-      .cp = 15, .opc1 = 3, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-};
-
 static void aarch64_a57_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 static void aarch64_a53_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 static void aarch64_a72_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #endif
 #include "cpregs.h"
 
+#ifndef CONFIG_USER_ONLY
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    /* Number of cores is in [25:24]; otherwise we RAZ */
+    return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+      .access = PL1_RW, .readfn = l2ctlr_read,
+      .writefn = arm_cp_write_ignore },
+    { .name = "L2CTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+      .access = PL1_RW, .readfn = l2ctlr_read,
+      .writefn = arm_cp_write_ignore },
+    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2ECTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUACTLR",
+      .cp = 15, .opc1 = 0, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUECTLR",
+      .cp = 15, .opc1 = 1, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUMERRSR",
+      .cp = 15, .opc1 = 2, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2MERRSR",
+      .cp = 15, .opc1 = 3, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
+#endif /* !CONFIG_USER_ONLY */
+
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
 1 file changed, 92 insertions(+), 59 deletions(-)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t t;
 
-    cortex_a15_initfn(obj);
+    /* aarch64_a57_initfn, advertising none of the aarch64 features */
+    cpu->dtb_compatible = "arm,cortex-a57";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x411fd070;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0;
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
-    /* old-style VFP short-vector support */
-    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+    /* Add additional features supported by QEMU */
+    t = cpu->isar.id_isar5;
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    cpu->isar.id_isar5 = t;
+
+    t = cpu->isar.id_isar6;
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    cpu->isar.id_isar6 = t;
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    t = cpu->isar.id_mmfr3;
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    cpu->isar.id_mmfr3 = t;
+
+    t = cpu->isar.id_mmfr4;
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    cpu->isar.id_mmfr4 = t;
+
+    t = cpu->isar.id_pfr0;
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    cpu->isar.id_pfr0 = t;
+
+    t = cpu->isar.id_pfr2;
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    cpu->isar.id_pfr2 = t;
 
 #ifdef CONFIG_USER_ONLY
     /*
-     * We don't set these in system emulation mode for the moment,
-     * since we don't correctly set (all of) the ID registers to
-     * advertise them.
+     * Break with true ARMv8 and add back old-style VFP short-vector support.
+     * Only do this for user-mode, where -cpu max is the default, so that
+     * older v6 and v7 programs are more likely to work without adjustment.
      */
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    {
-        uint32_t t;
-
-        t = cpu->isar.id_isar5;
-        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-        cpu->isar.id_isar5 = t;
-
-        t = cpu->isar.id_isar6;
-        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-        t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-        t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-        cpu->isar.id_isar6 = t;
-
-        t = cpu->isar.mvfr1;
-        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-        cpu->isar.mvfr1 = t;
-
-        t = cpu->isar.mvfr2;
-        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-        cpu->isar.mvfr2 = t;
-
-        t = cpu->isar.id_mmfr3;
-        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-        cpu->isar.id_mmfr3 = t;
-
-        t = cpu->isar.id_mmfr4;
-        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-        cpu->isar.id_mmfr4 = t;
-
-        t = cpu->isar.id_pfr0;
-        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-        cpu->isar.id_pfr0 = t;
-
-        t = cpu->isar.id_pfr2;
-        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-        cpu->isar.id_pfr2 = t;
-    }
-#endif /* CONFIG_USER_ONLY */
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+#endif
 }
 #endif /* !TARGET_AARCH64 */
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.

Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
     cpu->isar.id_pfr2 = t;
 
+    t = cpu->isar.id_dfr0;
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    cpu->isar.id_dfr0 = t;
+
 #ifdef CONFIG_USER_ONLY
     /*
      * Break with true ARMv8 and add back old-style VFP short-vector support.
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h |   2 +
 target/arm/cpu64.c     |  50 +-----------------
 target/arm/cpu_tcg.c   | 114 ++++++++++++++++++++++-------------------
 3 files changed, 65 insertions(+), 101 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+void aa32_max_features(ARMCPU *cpu);
+
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     uint64_t t;
-    uint32_t u;
 
     if (kvm_enabled() || hvf_enabled()) {
         /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
     cpu->isar.id_aa64zfr0 = t;
 
-    /* Replicate the same data to the 32-bit id registers.  */
-    u = cpu->isar.id_isar5;
-    u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
-    u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
-    u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
-    u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
-    u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
-    u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
-    cpu->isar.id_isar5 = u;
-
-    u = cpu->isar.id_isar6;
-    u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
-    u = FIELD_DP32(u, ID_ISAR6, DP, 1);
-    u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
-    u = FIELD_DP32(u, ID_ISAR6, SB, 1);
-    u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
-    u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
-    u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
-    cpu->isar.id_isar6 = u;
-
-    u = cpu->isar.id_pfr0;
-    u = FIELD_DP32(u, ID_PFR0, DIT, 1);
-    cpu->isar.id_pfr0 = u;
-
-    u = cpu->isar.id_pfr2;
-    u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
-    cpu->isar.id_pfr2 = u;
-
-    u = cpu->isar.id_mmfr3;
-    u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
-    cpu->isar.id_mmfr3 = u;
-
-    u = cpu->isar.id_mmfr4;
-    u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
-    u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
-    cpu->isar.id_mmfr4 = u;
-
     t = cpu->isar.id_aa64dfr0;
     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
     cpu->isar.id_aa64dfr0 = t;
 
-    u = cpu->isar.id_dfr0;
-    u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-    cpu->isar.id_dfr0 = u;
-
-    u = cpu->isar.mvfr1;
-    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
-    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
-    cpu->isar.mvfr1 = u;
+    /* Replicate the same data to the 32-bit id registers.  */
+    aa32_max_features(cpu);
 
 #ifdef CONFIG_USER_ONLY
     /*
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #endif
 #include "cpregs.h"
 
+
+/* Share AArch32 -cpu max features with AArch64. */
+void aa32_max_features(ARMCPU *cpu)
+{
+    uint32_t t;
+
+    /* Add additional features supported by QEMU */
+    t = cpu->isar.id_isar5;
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    cpu->isar.id_isar5 = t;
+
+    t = cpu->isar.id_isar6;
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    cpu->isar.id_isar6 = t;
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    t = cpu->isar.id_mmfr3;
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    cpu->isar.id_mmfr3 = t;
+
+    t = cpu->isar.id_mmfr4;
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    cpu->isar.id_mmfr4 = t;
+
+    t = cpu->isar.id_pfr0;
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    cpu->isar.id_pfr0 = t;
+
+    t = cpu->isar.id_pfr2;
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    cpu->isar.id_pfr2 = t;
+
+    t = cpu->isar.id_dfr0;
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    cpu->isar.id_dfr0 = t;
+}
+
 #ifndef CONFIG_USER_ONLY
 static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    uint32_t t;
 
     /* aarch64_a57_initfn, advertising none of the aarch64 features */
     cpu->dtb_compatible = "arm,cortex-a57";
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
-    /* Add additional features supported by QEMU */
-    t = cpu->isar.id_isar5;
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-    cpu->isar.id_isar5 = t;
-
-    t = cpu->isar.id_isar6;
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-    cpu->isar.id_isar6 = t;
-
-    t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-    cpu->isar.mvfr1 = t;
-
-    t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-    cpu->isar.mvfr2 = t;
-
-    t = cpu->isar.id_mmfr3;
-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-    cpu->isar.id_mmfr3 = t;
-
-    t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-    cpu->isar.id_mmfr4 = t;
-
-    t = cpu->isar.id_pfr0;
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-    cpu->isar.id_pfr0 = t;
-
-    t = cpu->isar.id_pfr2;
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-    cpu->isar.id_pfr2 = t;
-
-    t = cpu->isar.id_dfr0;
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-    cpu->isar.id_dfr0 = t;
+    aa32_max_features(cpu);
 
 #ifdef CONFIG_USER_ONLY
     /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu64.c   | 100 +++++++++++++++++++++----------------------
 target/arm/cpu_tcg.c |  48 ++++++++++-----------
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     cpu->midr = t;
 
     t = cpu->isar.id_aa64isar0;
-    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
     t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
-    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
-    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
-    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
+    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
+    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
+    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
+    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
     cpu->isar.id_aa64isar0 = t;
 
     t = cpu->isar.id_aa64isar1;
-    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
-    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
-    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
+    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
+    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
+    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
+    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
+    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
     cpu->isar.id_aa64isar1 = t;
 
     t = cpu->isar.id_aa64pfr0;
+    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
+    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
+    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
     cpu->isar.id_aa64pfr0 = t;
 
     t = cpu->isar.id_aa64pfr1;
-    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
-    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
+    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
+    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
     /*
      * Begin with full support for MTE. This will be downgraded to MTE=0
      * during realize if the board provides no tag memory, much like
      * we do for EL2 with the virtualization=on property.
      */
-    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
+    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
     cpu->isar.id_aa64pfr1 = t;
 
     t = cpu->isar.id_aa64mmfr0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     cpu->isar.id_aa64mmfr0 = t;
 
     t = cpu->isar.id_aa64mmfr1;
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
-    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
-    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
-    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
+    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
+    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
     cpu->isar.id_aa64mmfr1 = t;
 
     t = cpu->isar.id_aa64mmfr2;
-    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
-    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
-    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
-    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
-    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
+    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
+    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
+    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
+    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
+    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
+    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
     cpu->isar.id_aa64mmfr2 = t;
 
     t = cpu->isar.id_aa64zfr0;
     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
-    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
+    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
+    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
+    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
+    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
     cpu->isar.id_aa64zfr0 = t;
 
     t = cpu->isar.id_aa64dfr0;
-    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
     cpu->isar.id_aa64dfr0 = t;
 
     /* Replicate the same data to the 32-bit id registers.  */
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
 
     /* Add additional features supported by QEMU */
     t = cpu->isar.id_isar5;
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
     t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
     cpu->isar.id_isar5 = t;
 
     t = cpu->isar.id_isar6;
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
     cpu->isar.id_isar6 = t;
 
     t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
     cpu->isar.mvfr1 = t;
 
     t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
     cpu->isar.mvfr2 = t;
 
     t = cpu->isar.id_mmfr3;
-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
     cpu->isar.id_mmfr4 = t;
 
     t = cpu->isar.id_pfr0;
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
     cpu->isar.id_pfr0 = t;
 
     t = cpu->isar.id_pfr2;
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
     cpu->isar.id_pfr2 = t;
 
     t = cpu->isar.id_dfr0;
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
     cpu->isar.id_dfr0 = t;
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          */
         unset_feature(env, ARM_FEATURE_EL3);
 
-        /* Disable the security extension feature bits in the processor feature
-         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
+        /*
+         * Disable the security extension feature bits in the processor
+         * feature registers as well.
          */
-        cpu->isar.id_pfr1 &= ~0xf0;
-        cpu->isar.id_aa64pfr0 &= ~0xf000;
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL3, 0);
     }
 
     if (!cpu->has_el2) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
-        /* Disable the hypervisor feature bits in the processor feature
-         * registers if we don't have EL2. These are id_pfr1[15:12] and
-         * id_aa64pfr0_el1[11:8].
+        /*
+         * Disable the hypervisor feature bits in the processor feature
+         * registers if we don't have EL2.
          */
-        cpu->isar.id_aa64pfr0 &= ~0xf00;
-        cpu->isar.id_pfr1 &= ~0xf000;
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL2, 0);
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
+                                       ID_PFR1, VIRTUALIZATION, 0);
     }
 
 #ifndef CONFIG_USER_ONLY
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE.  The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu.c              | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 2 ++
 4 files changed, 5 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU.  Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 2 +-
 target/arm/cpu_tcg.c          | 4 ++--
 3 files changed, 4 insertions(+), 3 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Add only the system registers required to implement zero error
records.  This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.

Add the EL2 registers required for injecting virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  5 +++
 target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
         uint64_t gcr_el1;
         uint64_t rgsr_el1;
+
+        /* Minimal RAS registers */
+        uint64_t disr_el1;
+        uint64_t vdisr_el2;
+        uint64_t vsesr_el2;
     } cp15;
 
     struct {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 };
 
+/*
+ * Check for traps to RAS registers, which are controlled
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
+ */
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+        return env->cp15.vdisr_el2;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+        return 0; /* RAZ/WI */
+    }
+    return env->cp15.disr_el1;
+}
+
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+        env->cp15.vdisr_el2 = val;
+        return;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+        return; /* RAZ/WI */
+    }
+    env->cp15.disr_el1 = val;
+}
+
+/*
+ * Minimal RAS implementation with no Error Records.
+ * Which means that all of the Error Record registers:
+ *   ERXADDR_EL1
+ *   ERXCTLR_EL1
+ *   ERXFR_EL1
+ *   ERXMISC0_EL1
+ *   ERXMISC1_EL1
+ *   ERXMISC2_EL1
+ *   ERXMISC3_EL1
+ *   ERXPFGCDN_EL1  (RASv1p1)
+ *   ERXPFGCTL_EL1  (RASv1p1)
+ *   ERXPFGF_EL1    (RASv1p1)
+ *   ERXSTATUS_EL1
+ * and
+ *   ERRSELR_EL1
+ * may generate UNDEFINED, which is the effect we get by not
+ * listing them at all.
+ */
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
+    { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
+      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
+      .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
+    { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
+      .access = PL1_R, .accessfn = access_terr,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
+    { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
+};
+
 /* Return the exception level to which exceptions should be taken
  * via SVEAccessTrap.  If an exception should be routed through
  * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_ssbs, cpu)) {
         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
     }
+    if (cpu_isar_feature(any_ras, cpu)) {
+        define_arm_cp_regs(cpu, minimal_ras_reginfo);
+    }
 
     if (cpu_isar_feature(aa64_vh, cpu) ||
         cpu_isar_feature(aa64_debugv8p2, cpu)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
         valid_mask &= ~SCR_NET;
 
+        if (cpu_isar_feature(aa64_ras, cpu)) {
+            valid_mask |= SCR_TERR;
+        }
         if (cpu_isar_feature(aa64_lor, cpu)) {
             valid_mask |= SCR_TLOR;
         }
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
+        if (cpu_isar_feature(aa32_ras, cpu)) {
+            valid_mask |= SCR_TERR;
+        }
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         if (cpu_isar_feature(aa64_vh, cpu)) {
             valid_mask |= HCR_E2H;
         }
+        if (cpu_isar_feature(aa64_ras, cpu)) {
+            valid_mask |= HCR_TERR | HCR_TEA;
+        }
         if (cpu_isar_feature(aa64_lor, cpu)) {
             valid_mask |= HCR_TLOR;
         }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |  2 ++
 target/arm/internals.h |  8 ++++++++
 target/arm/syndrome.h  |  5 +++++
 target/arm/cpu.c       | 38 +++++++++++++++++++++++++++++++++++++-
 target/arm/helper.c    | 40 +++++++++++++++++++++++++++++++++++++++-
 5 files changed, 91 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
 #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
 #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
+#define EXCP_VSERR          24
 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
 
 #define ARMV7M_EXCP_RESET   1
@@ -XXX,XX +XXX,XX @@ enum {
 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
 
 /* The usual mapping for an AArch64 system register to its AArch32
  * counterpart is for the 32 bit world to have access to the lower
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
  */
 void arm_cpu_update_vfiq(ARMCPU *cpu);
 
+/**
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
+ *
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
+ * following a change to the HCR_EL2.VSE bit.
+ */
+void arm_cpu_update_vserr(ARMCPU *cpu);
+
 /**
  * arm_mmu_idx_el:
  * @env: The cpu environment
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
     return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 }
 
+static inline uint32_t syn_serror(uint32_t extra)
+{
+    return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
+}
+
 #endif /* TARGET_ARM_SYNDROME_H */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
     return (cpu->power_state != PSCI_OFF)
         && cs->interrupt_request &
         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
-         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
+         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
          | CPU_INTERRUPT_EXITTB);
 }
 
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
             return false;
         }
         return !(env->daif & PSTATE_I);
+    case EXCP_VSERR:
+        if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
+            /* VIRQs are only taken when hypervized.  */
+            return false;
+        }
+        return !(env->daif & PSTATE_A);
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
             goto found;
         }
     }
+    if (interrupt_request & CPU_INTERRUPT_VSERR) {
+        excp_idx = EXCP_VSERR;
+        target_el = 1;
+        if (arm_excp_unmasked(cs, excp_idx, target_el,
+                              cur_el, secure, hcr_el2)) {
+            /* Taking a virtual abort clears HCR_EL2.VSE */
+            env->cp15.hcr_el2 &= ~HCR_VSE;
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+            goto found;
+        }
+    }
     return false;
 
  found:
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
     }
 }
 
+void arm_cpu_update_vserr(ARMCPU *cpu)
+{
+    /*
+     * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
+     */
+    CPUARMState *env = &cpu->env;
+    CPUState *cs = CPU(cpu);
+
+    bool new_state = env->cp15.hcr_el2 & HCR_VSE;
+
+    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
+        if (new_state) {
+            cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
+        } else {
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+        }
+    }
+}
+
 #ifndef CONFIG_USER_ONLY
 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
         }
     }
 
-    /* External aborts are not possible in QEMU so A bit is always clear */
+    if (hcr_el2 & HCR_AMO) {
+        if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
+            ret |= CPSR_A;
+        }
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
     g_assert(qemu_mutex_iothread_locked());
     arm_cpu_update_virq(cpu);
     arm_cpu_update_vfiq(cpu);
+    arm_cpu_update_vserr(cpu);
 }
 
 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
             [EXCP_LSERR] = "v8M LSERR UsageFault",
             [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
             [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
+            [EXCP_VSERR] = "Virtual SERR",
         };
 
         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
         mask = CPSR_A | CPSR_I | CPSR_F;
         offset = 4;
         break;
+    case EXCP_VSERR:
+        {
+            /*
+             * Note that this is reported as a data abort, but the DFAR
+             * has an UNKNOWN value.  Construct the SError syndrome from
+             * AET and ExT fields.
+             */
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
+
+            if (extended_addresses_enabled(env)) {
+                env->exception.fsr = arm_fi_to_lfsc(&fi);
+            } else {
+                env->exception.fsr = arm_fi_to_sfsc(&fi);
+            }
+            env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
+            A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
+            qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
+                          env->exception.fsr);
+
+            new_mode = ARM_CPU_MODE_ABT;
+            addr = 0x10;
+            mask = CPSR_A | CPSR_I;
+            offset = 8;
+        }
+        break;
     case EXCP_SMC:
         new_mode = ARM_CPU_MODE_MON;
         addr = 0x08;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     case EXCP_VFIQ:
         addr += 0x100;
         break;
+    case EXCP_VSERR:
+        addr += 0x180;
+        /* Construct the SError syndrome from IDS and ISS fields. */
+        env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
+        env->cp15.esr_el[new_el] = env->exception.syndrome;
+        break;
     default:
         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Check for and defer any pending virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  1 +
 target/arm/a32.decode      | 16 ++++++++------
 target/arm/t32.decode      | 18 ++++++++--------
 target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c | 17 +++++++++++++++
 target/arm/translate.c     | 23 ++++++++++++++++++++
 6 files changed, 103 insertions(+), 15 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
 DEF_HELPER_1(yield, void, env)
 DEF_HELPER_1(pre_hvc, void, env)
 DEF_HELPER_2(pre_smc, void, env, i32)
+DEF_HELPER_1(vesb, void, env)
 
 DEF_HELPER_3(cpsr_write, void, env, i32, i32)
 DEF_HELPER_2(cpsr_write_eret, void, env, i32)
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -XXX,XX +XXX,XX @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
 
 {
   {
-    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
-    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
-    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
+    [
+      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
+      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
+      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 
-    # TODO: Implement SEV, SEVL; may help SMP performance.
-    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
-    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
+      # TODO: Implement SEV, SEVL; may help SMP performance.
+      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
+      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
+
+      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
+    ]
 
     # The canonical nop ends in 00000000, but the whole of the
     # rest of the space executes as nop if otherwise unsupported.
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
   [
     # Hints, and CPS
     {
-      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
-      WFE        1111 0011 1010 1111 1000 0000 0000 0010
-      WFI        1111 0011 1010 1111 1000 0000 0000 0011
+      [
+        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
+        WFE      1111 0011 1010 1111 1000 0000 0000 0010
+        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 
-      # TODO: Implement SEV, SEVL; may help SMP performance.
-      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
-      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
+        # TODO: Implement SEV, SEVL; may help SMP performance.
+        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
+        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 
-      # For M-profile minimal-RAS ESB can be a NOP, which is the
-      # default behaviour since it is in the hint space.
-      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
+        ESB      1111 0011 1010 1111 1000 0000 0001 0000
+      ]
 
       # The canonical nop ends in 0000 0000, but the whole rest
       # of the space is "reserved hint, behaves as nop".
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                      access_type, mmu_idx, ra);
     }
 }
+
+/*
+ * This function corresponds to AArch64.vESBOperation().
+ * Note that the AArch32 version is not functionally different.
+ */
+void HELPER(vesb)(CPUARMState *env)
+{
+    /*
+     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
+     * and will return HCR_EL2.VSE == 0, so nothing happens.
+     */
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
+    bool pending = enabled && (hcr & HCR_VSE);
+    bool masked  = (env->daif & PSTATE_A);
+
+    /* If VSE pending and masked, defer the exception.  */
+    if (pending && masked) {
+        uint32_t syndrome;
+
+        if (arm_el_is_aa64(env, 1)) {
+            /* Copy across IDS and ISS from VSESR. */
+            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
+        } else {
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
+
+            if (extended_addresses_enabled(env)) {
+                syndrome = arm_fi_to_lfsc(&fi);
+            } else {
+                syndrome = arm_fi_to_sfsc(&fi);
+            }
+            /* Copy across AET and ExT from VSESR. */
+            syndrome |= env->cp15.vsesr_el2 & 0xd000;
+        }
+
+        /* Set VDISR_EL2.A along with the syndrome. */
+        env->cp15.vdisr_el2 = syndrome | (1u << 31);
+
+        /* Clear pending virtual SError */
+        env->cp15.hcr_el2 &= ~HCR_VSE;
+        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
+    }
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
             gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
         }
         break;
+    case 0b10000: /* ESB */
+        /* Without RAS, we must implement this as NOP. */
+        if (dc_isar_feature(aa64_ras, s)) {
+            /*
+             * QEMU does not have a source of physical SErrors,
+             * so we are only concerned with virtual SErrors.
+             * The pseudocode in the ARM for this case is
+             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+             *      AArch64.vESBOperation();
+             * Most of the condition can be evaluated at translation time.
+             * Test for EL2 present, and defer test for SEL2 to runtime.
+             */
+            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+                gen_helper_vesb(cpu_env);
+            }
+        }
+        break;
     case 0b11000: /* PACIAZ */
         if (s->pauth_active) {
             gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
     return true;
 }
 
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
+{
+    /*
+     * For M-profile, minimal-RAS ESB can be a NOP.
+     * Without RAS, we must implement this as NOP.
+     */
+    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
+        /*
+         * QEMU does not have a source of physical SErrors,
+         * so we are only concerned with virtual SErrors.
+         * The pseudocode in the ARM for this case is
+         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+         *      AArch32.vESBOperation();
+         * Most of the condition can be evaluated at translation time.
+         * Test for EL2 present, and defer test for SEL2 to runtime.
+         */
+        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+            gen_helper_vesb(cpu_env);
+        }
+    }
+    return true;
+}
+
 static bool trans_NOP(DisasContext *s, arg_NOP *a)
 {
     return true;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 2 files changed, 2 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns branch speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst |  3 ++
 target/arm/cpu.h              | 16 +++++++++
 target/arm/cpu.c              |  5 +++
 target/arm/cpu64.c            |  3 +-
 target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
 5 files changed, 86 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_BF16 (AArch64 BFloat16 instructions)
 - FEAT_BTI (Branch Target Identification)
 - FEAT_CSV2 (Cache speculation variant 2)
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
 - FEAT_DIT (Data Independent Timing instructions)
 - FEAT_DPB (DC CVAP instruction)
 - FEAT_Debugv8p2 (Debug changes for v8.2)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         ARMPACKey apdb;
         ARMPACKey apga;
     } keys;
+
+    uint64_t scxtnum_el[4];
 #endif
 
 #if defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
 #define SCTLR_WXN     (1U << 19)
 #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
 #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
+#define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
 #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
 #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
 #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
 }
 
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
+{
+    int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
+    if (key >= 2) {
+        return true;      /* FEAT_CSV2_2 */
+    }
+    if (key == 1) {
+        key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
+        return key >= 2;  /* FEAT_CSV2_1p2 */
+    }
+    return false;
+}
+
 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
              */
             env->cp15.gcr_el1 = 0x1ffff;
         }
+        /*
+         * Disable access to SCXTNUM_EL0 from CSV2_1p2.
+         * This is not yet exposed from the Linux kernel in any way.
+         */
+        env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
 #else
         /* Reset into the highest available EL */
         if (arm_feature(env, ARM_FEATURE_EL3)) {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr0 = t;
 
     t = cpu->isar.id_aa64pfr1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      * we do for EL2 with the virtualization=on property.
      */
     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
+    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr1 = t;
 
     t = cpu->isar.id_aa64mmfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= SCR_ATA;
         }
+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+            valid_mask |= SCR_ENSCXT;
+        }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
         if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
         }
+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+            valid_mask |= HCR_ENSCXT;
+        }
     }
 
     /* Clear RES0 bits.  */
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
         { K(3, 0,  5, 6, 0), K(3, 4,  5, 6, 0), K(3, 5, 5, 6, 0),
           "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
 
+        { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
+          "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
+          isar_feature_aa64_scxtnum },
+
         /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
         /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
     };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
     },
 };
 
-#endif
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
+                                     bool isread)
+{
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    int el = arm_current_el(env);
+
+    if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
+        if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
+            if (hcr & HCR_TGE) {
+                return CP_ACCESS_TRAP_EL2;
+            }
+            return CP_ACCESS_TRAP;
+        }
+    } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3
+        && arm_feature(env, ARM_FEATURE_EL3)
+        && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static const ARMCPRegInfo scxtnum_reginfo[] = {
+    { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL0_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
+    { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL1_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
+    { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL2_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
+    { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL3_RW,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
+};
+#endif /* TARGET_AARCH64 */
 
 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
                                      bool isread)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     }
+
+    if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+        define_arm_cp_regs(cpu, scxtnum_reginfo);
+    }
 #endif
 
     if (cpu_isar_feature(any_predinv, cpu)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns cache speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns not merging memory access, which TCG does
not implement.  Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/translate-a64.c    | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

Enable the a76 for virt and sbsa board use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/sbsa-ref.c        |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a53`` (64-bit)
 - ``cortex-a57`` (64-bit)
 - ``cortex-a72`` (64-bit)
+- ``cortex-a76`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
 static const char * const valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("max"),
 };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a53"),
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("a64fx"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
+static void aarch64_a76_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a76";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444C004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0b1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.18 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+    /* From B2.93 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+}
+
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
+    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable the n1 for virt and sbsa board use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/sbsa-ref.c        |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a76`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
+- ``neoverse-n1`` (64-bit)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
 
 Note that the default is ``cortex-a15``, so for an AArch64 guest you must
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
+    ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("max"),
 };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("a64fx"),
+    ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
     cpu->isar.mvfr2 = 0x00000043;
 }
 
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,neoverse-n1";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444c004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0c1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.23 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+    /* From B2.98 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+}
+
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+    { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
     { .name = "host",               .initfn = aarch64_host_initfn },
-- 
2.25.1

From: Leif Lindholm <quic_llindhol@quicinc.com>

The sbsa-ref machine is continuously evolving. Some of the changes we
want to make in the near future, to align with real components (e.g.
the GIC-700), will break compatibility for existing firmware.

Introduce two new properties to the DT generated on machine generation:
- machine-version-major
  To be incremented when a platform change makes the machine
  incompatible with existing firmware.
- machine-version-minor
  To be incremented when functionality is added to the machine
  without causing incompatibility with existing firmware.
  to be reset to 0 when machine-version-major is incremented.

This versioning scheme is *neither*:
- A QEMU versioned machine type; a given version of QEMU will emulate
  a given version of the platform.
- A reflection of level of SBSA (now SystemReady SR) support provided.

The version will increment on guest-visible functional changes only,
akin to a revision ID register found on a physical platform.

These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 
+    /*
+     * This versioning scheme is for informing platform fw only. It is neither:
+     * - A QEMU versioned machine type; a given version of QEMU will emulate
+     *   a given version of the platform.
+     * - A reflection of level of SBSA (now SystemReady SR) support provided.
+     *
+     * machine-version-major: updated when changes breaking fw compatibility
+     *                        are introduced.
+     * machine-version-minor: updated when features are added that don't break
+     *                        fw compatibility.
+     */
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
+
     if (ms->numa_state->have_numa_distance) {
         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
         uint32_t *matrix = g_malloc0(size);
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:

* hw/core/machine.c::machine_set_cpu_numa_node() to associate
    CPU with its NUMA node.

* hw/core/machine.c::machine_numa_finish_cpu_init() to record
    CPU slots with no NUMA mapping set.

* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
    cluster-id.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 qapi/machine.json          |  6 ++++--
 hw/core/machine-hmp-cmds.c |  4 ++++
 hw/core/machine.c          | 16 ++++++++++++++++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/qapi/machine.json b/qapi/machine.json
index XXXXXXX..XXXXXXX 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -XXX,XX +XXX,XX @@
 # @node-id: NUMA node ID the CPU belongs to
 # @socket-id: socket number within node/board the CPU belongs to
 # @die-id: die number within socket the CPU belongs to (since 4.1)
-# @core-id: core number within die the CPU belongs to
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
+# @core-id: core number within cluster the CPU belongs to
 # @thread-id: thread number within core the CPU belongs to
 #
-# Note: currently there are 5 properties that could be present
+# Note: currently there are 6 properties that could be present
 #       but management should be prepared to pass through other
 #       properties with device_add command to allow for future
 #       interface extension. This also requires the filed names to be kept in
@@ -XXX,XX +XXX,XX @@
   'data': { '*node-id': 'int',
             '*socket-id': 'int',
             '*die-id': 'int',
+            '*cluster-id': 'int',
             '*core-id': 'int',
             '*thread-id': 'int'
   }
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine-hmp-cmds.c
+++ b/hw/core/machine-hmp-cmds.c
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
         if (c->has_die_id) {
             monitor_printf(mon, "    die-id: \"%" PRIu64 "\"\n", c->die_id);
         }
+        if (c->has_cluster_id) {
+            monitor_printf(mon, "    cluster-id: \"%" PRIu64 "\"\n",
+                           c->cluster_id);
+        }
         if (c->has_core_id) {
             monitor_printf(mon, "    core-id: \"%" PRIu64 "\"\n", c->core_id);
         }
diff --git a/hw/core/machine.c b/hw/core/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
             return;
         }
 
+        if (props->has_cluster_id && !slot->props.has_cluster_id) {
+            error_setg(errp, "cluster-id is not supported");
+            return;
+        }
+
         if (props->has_socket_id && !slot->props.has_socket_id) {
             error_setg(errp, "socket-id is not supported");
             return;
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
                 continue;
         }
 
+        if (props->has_cluster_id &&
+            props->cluster_id != slot->props.cluster_id) {
+                continue;
+        }
+
         if (props->has_die_id && props->die_id != slot->props.die_id) {
                 continue;
         }
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
         }
         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
     }
+    if (cpu->props.has_cluster_id) {
+        if (s->len) {
+            g_string_append_printf(s, ", ");
+        }
+        g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
+    }
     if (cpu->props.has_core_id) {
         if (s->len) {
             g_string_append_printf(s, ", ");
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

The CPU topology isn't enabled on arm/virt machine yet, but we're
going to do it in next patch. After the CPU topology is enabled by
next patch, "thread-id=1" becomes invalid because the CPU core is
preferred on arm/virt machine. It means these two CPUs have 0/1
as their core IDs, but their thread IDs are all 0. It will trigger
test failure as the following message indicates:

[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test  ERROR
  1.48s   killed by signal 6 SIGABRT
  >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
      QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon         \
      QTEST_QEMU_BINARY=./qemu-system-aarch64                                       \
      QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83                                  \
      /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
  ――――――――――――――――――――――――――――――――――――――――――――――
  stderr:
  qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found

This fixes the issue by providing comprehensive SMP configurations
in aarch64_numa_cpu(). The SMP configurations aren't used before
the CPU topology is enabled in next patch.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/numa-test.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Gavin Shan <gshan@redhat.com>

Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.

This takes account of SMP configuration when the CPU topology
is populated. The die ID for the given CPU isn't assigned since
it's not supported on arm/virt machine. Besides, the used SMP
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
to avoid testing failure

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-4-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
     int n;
     unsigned int max_cpus = ms->smp.max_cpus;
     VirtMachineState *vms = VIRT_MACHINE(ms);
+    MachineClass *mc = MACHINE_GET_CLASS(vms);
 
     if (ms->possible_cpus) {
         assert(ms->possible_cpus->len == max_cpus);
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
         ms->possible_cpus->cpus[n].type = ms->cpu_type;
         ms->possible_cpus->cpus[n].arch_id =
             virt_cpu_mp_affinity(vms, n);
+
+        assert(!mc->smp_props.dies_supported);
+        ms->possible_cpus->cpus[n].props.has_socket_id = true;
+        ms->possible_cpus->cpus[n].props.socket_id =
+            n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
+        ms->possible_cpus->cpus[n].props.has_cluster_id = true;
+        ms->possible_cpus->cpus[n].props.cluster_id =
+            (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
+        ms->possible_cpus->cpus[n].props.has_core_id = true;
+        ms->possible_cpus->cpus[n].props.core_id =
+            (n / ms->smp.threads) % ms->smp.cores;
         ms->possible_cpus->cpus[n].props.has_thread_id = true;
-        ms->possible_cpus->cpus[n].props.thread_id = n;
+        ms->possible_cpus->cpus[n].props.thread_id =
+            n % ms->smp.threads;
     }
     return ms->possible_cpus;
 }
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

In aarch64_numa_cpu(), the CPU and NUMA association is something
like below. Two threads in the same core/cluster/socket are
associated with two individual NUMA nodes, which is unreal as
Igor Mammedov mentioned. We don't expect the association to break
NUMA-to-socket boundary, which matches with the real world.

NUMA-node  socket  cluster   core   thread
    ------------------------------------------
        0       0        0        0      0
        1       0        0        0      1

This corrects the topology for CPUs and their association with
NUMA nodes. After this patch is applied, the CPU and NUMA
association becomes something like below, which looks real.
Besides, socket/cluster/core/thread IDs are all checked when
the NUMA node IDs are verified. It helps to check if the CPU
topology is properly populated or not.

NUMA-node  socket  cluster   core   thread
    ------------------------------------------
       0        1        0        0       0
       1        0        0        0       0

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-5-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/numa-test.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/numa-test.c
+++ b/tests/qtest/numa-test.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
     g_autofree char *cli = NULL;
 
     cli = make_cli(data, "-machine "
-        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+        "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
-        "-numa cpu,node-id=1,thread-id=0 "
-        "-numa cpu,node-id=0,thread-id=1");
+        "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
+        "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
     qts = qtest_init(cli);
     cpus = get_cpus(qts, &resp);
     g_assert(cpus);
 
     while ((e = qlist_pop(cpus))) {
         QDict *cpu, *props;
-        int64_t thread, node;
+        int64_t socket, cluster, core, thread, node;
 
         cpu = qobject_to(QDict, e);
         g_assert(qdict_haskey(cpu, "props"));
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
 
         g_assert(qdict_haskey(props, "node-id"));
         node = qdict_get_int(props, "node-id");
+        g_assert(qdict_haskey(props, "socket-id"));
+        socket = qdict_get_int(props, "socket-id");
+        g_assert(qdict_haskey(props, "cluster-id"));
+        cluster = qdict_get_int(props, "cluster-id");
+        g_assert(qdict_haskey(props, "core-id"));
+        core = qdict_get_int(props, "core-id");
         g_assert(qdict_haskey(props, "thread-id"));
         thread = qdict_get_int(props, "thread-id");
 
-        if (thread == 0) {
+        if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
             g_assert_cmpint(node, ==, 1);
-        } else if (thread == 1) {
+        } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
             g_assert_cmpint(node, ==, 0);
         } else {
             g_assert(false);
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.

For example, the following warning messages are observed when the
Linux guest is booted with the following command lines.

/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
  -accel kvm -machine virt,gic-version=host               \
  -cpu host                                               \
  -smp 6,sockets=2,cores=3,threads=1                      \
  -m 1024M,slots=16,maxmem=64G                            \
  -object memory-backend-ram,id=mem0,size=128M            \
  -object memory-backend-ram,id=mem1,size=128M            \
  -object memory-backend-ram,id=mem2,size=128M            \
  -object memory-backend-ram,id=mem3,size=128M            \
  -object memory-backend-ram,id=mem4,size=128M            \
  -object memory-backend-ram,id=mem4,size=384M            \
  -numa node,nodeid=0,memdev=mem0                         \
  -numa node,nodeid=1,memdev=mem1                         \
  -numa node,nodeid=2,memdev=mem2                         \
  -numa node,nodeid=3,memdev=mem3                         \
  -numa node,nodeid=4,memdev=mem4                         \
  -numa node,nodeid=5,memdev=mem5
         :
  alternatives: patching kernel code
  BUG: arch topology borken
  the CLS domain not a subset of the MC domain
  <the above error log repeats>
  BUG: arch topology borken
  the DIE domain not a subset of the NODE domain

With current implementation of mc->get_default_cpu_node_id(),
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
That's incorrect because CPU#0/1/2 should be associated with same
NUMA node because they're seated in same socket.

This fixes the issue by considering the socket ID when the default
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
With this applied, no more CPU topology broken warnings are seen
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
there are no CPUs associated with NODE#2/3/4/5.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 
 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
 {
-    return idx % ms->numa_state->num_nodes;
+    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
+
+    return socket_id % ms->numa_state->num_nodes;
 }
 
 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.

This reworks build_pptt() to avoid by reusing the existing IDs in
ms->possible_cpus. Currently, the only user of build_pptt() is
arm/virt machine.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Tested-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20220503140304.855514-7-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
 1 file changed, 48 insertions(+), 63 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
                 const char *oem_id, const char *oem_table_id)
 {
     MachineClass *mc = MACHINE_GET_CLASS(ms);
-    GQueue *list = g_queue_new();
-    guint pptt_start = table_data->len;
-    guint parent_offset;
-    guint length, i;
-    int uid = 0;
-    int socket;
+    CPUArchIdList *cpus = ms->possible_cpus;
+    int64_t socket_id = -1, cluster_id = -1, core_id = -1;
+    uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
+    uint32_t pptt_start = table_data->len;
+    int n;
     AcpiTable table = { .sig = "PPTT", .rev = 2,
                         .oem_id = oem_id, .oem_table_id = oem_table_id };
 
     acpi_table_begin(&table, table_data);
 
-    for (socket = 0; socket < ms->smp.sockets; socket++) {
-        g_queue_push_tail(list,
-            GUINT_TO_POINTER(table_data->len - pptt_start));
-        build_processor_hierarchy_node(
-            table_data,
-            /*
-             * Physical package - represents the boundary
-             * of a physical package
-             */
-            (1 << 0),
-            0, socket, NULL, 0);
-    }
-
-    if (mc->smp_props.clusters_supported) {
-        length = g_queue_get_length(list);
-        for (i = 0; i < length; i++) {
-            int cluster;
-
-            parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-            for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
-                g_queue_push_tail(list,
-                    GUINT_TO_POINTER(table_data->len - pptt_start));
-                build_processor_hierarchy_node(
-                    table_data,
-                    (0 << 0), /* not a physical package */
-                    parent_offset, cluster, NULL, 0);
-            }
+    /*
+     * This works with the assumption that cpus[n].props.*_id has been
+     * sorted from top to down levels in mc->possible_cpu_arch_ids().
+     * Otherwise, the unexpected and duplicated containers will be
+     * created.
+     */
+    for (n = 0; n < cpus->len; n++) {
+        if (cpus->cpus[n].props.socket_id != socket_id) {
+            assert(cpus->cpus[n].props.socket_id > socket_id);
+            socket_id = cpus->cpus[n].props.socket_id;
+            cluster_id = -1;
+            core_id = -1;
+            socket_offset = table_data->len - pptt_start;
+            build_processor_hierarchy_node(table_data,
+                (1 << 0), /* Physical package */
+                0, socket_id, NULL, 0);
         }
-    }
 
-    length = g_queue_get_length(list);
-    for (i = 0; i < length; i++) {
-        int core;
-
-        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-        for (core = 0; core < ms->smp.cores; core++) {
-            if (ms->smp.threads > 1) {
-                g_queue_push_tail(list,
-                    GUINT_TO_POINTER(table_data->len - pptt_start));
-                build_processor_hierarchy_node(
-                    table_data,
-                    (0 << 0), /* not a physical package */
-                    parent_offset, core, NULL, 0);
-            } else {
-                build_processor_hierarchy_node(
-                    table_data,
-                    (1 << 1) | /* ACPI Processor ID valid */
-                    (1 << 3),  /* Node is a Leaf */
-                    parent_offset, uid++, NULL, 0);
+        if (mc->smp_props.clusters_supported) {
+            if (cpus->cpus[n].props.cluster_id != cluster_id) {
+                assert(cpus->cpus[n].props.cluster_id > cluster_id);
+                cluster_id = cpus->cpus[n].props.cluster_id;
+                core_id = -1;
+                cluster_offset = table_data->len - pptt_start;
+                build_processor_hierarchy_node(table_data,
+                    (0 << 0), /* Not a physical package */
+                    socket_offset, cluster_id, NULL, 0);
             }
+        } else {
+            cluster_offset = socket_offset;
         }
-    }
 
-    length = g_queue_get_length(list);
-    for (i = 0; i < length; i++) {
-        int thread;
+        if (ms->smp.threads == 1) {
+            build_processor_hierarchy_node(table_data,
+                (1 << 1) | /* ACPI Processor ID valid */
+                (1 << 3),  /* Node is a Leaf */
+                cluster_offset, n, NULL, 0);
+        } else {
+            if (cpus->cpus[n].props.core_id != core_id) {
+                assert(cpus->cpus[n].props.core_id > core_id);
+                core_id = cpus->cpus[n].props.core_id;
+                core_offset = table_data->len - pptt_start;
+                build_processor_hierarchy_node(table_data,
+                    (0 << 0), /* Not a physical package */
+                    cluster_offset, core_id, NULL, 0);
+            }
 
-        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-        for (thread = 0; thread < ms->smp.threads; thread++) {
-            build_processor_hierarchy_node(
-                table_data,
+            build_processor_hierarchy_node(table_data,
                 (1 << 1) | /* ACPI Processor ID valid */
                 (1 << 2) | /* Processor is a Thread */
                 (1 << 3),  /* Node is a Leaf */
-                parent_offset, uid++, NULL, 0);
+                core_offset, n, NULL, 0);
         }
     }
 
-    g_queue_free(list);
     acpi_table_end(linker, &table);
 }
 
-- 
2.25.1

Here's another arm pullreq; nothing too exciting in here I think.

thanks
-- PMM

The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:

Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2024-04-29 14:34:25 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240430

for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:

tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/core/clock: allow clock_propagate on child clocks
 * hvf: arm: Remove unused PL1_WRITE_MASK define
 * target/arm: Restrict translation disabled alignment check to VMSA
 * docs/system/arm/emulation.rst: Add missing implemented features
 * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
 * tests/avocado: update sunxi kernel from armbian to 6.6.16
 * target/arm: Make new CPUs default to 1GHz generic timer
 * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
 * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
 * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
 * hw/arm: Add DM163 display to B-L475E-IOT01A board

----------------------------------------------------------------
Alexandra Diupina (1):
      hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields

Inès Varhol (5):
      hw/display : Add device DM163
      hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
      hw/arm : Create Bl475eMachineState
      hw/arm : Connect DM163 to B-L475E-IOT01A
      tests/qtest : Add testcase for DM163

Peter Maydell (10):
      docs/system/arm/emulation.rst: Add missing implemented features
      target/arm: Enable FEAT_CSV2_3 for -cpu max
      target/arm: Enable FEAT_ETS2 for -cpu max
      target/arm: Implement ID_AA64MMFR3_EL1
      target/arm: Enable FEAT_Spec_FPACC for -cpu max
      tests/avocado: update sunxi kernel from armbian to 6.6.16
      target/arm: Refactor default generic timer frequency handling
      hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
      hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
      target/arm: Default to 1GHz cntfrq for 'max' and new CPUs

Philippe Mathieu-Daudé (1):
      hw/arm/npcm7xx: Store derivative OTP fuse key in little endian

Raphael Poggi (1):
      hw/core/clock: allow clock_propagate on child clocks

Richard Henderson (1):
      target/arm: Restrict translation disabled alignment check to VMSA

Thomas Huth (1):
      hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size

Zenghui Yu (1):
      hvf: arm: Remove PL1_WRITE_MASK

From: Raphael Poggi <raphael.poggi@lynxleap.co.uk>

clock_propagate() has an assert that clk->source is NULL, i.e. that
you are calling it on a clock which has no source clock.  This made
sense in the original design where the only way for a clock's
frequency to change if it had a source clock was when that source
clock changed.  However, we subsequently added multiplier/divider
support, but didn't look at what that meant for propagation.

If a clock-management device changes the multiplier or divider value
on a clock, it needs to propagate that change down to child clocks,
even if the clock has a source clock set.  So the assertion is now
incorrect.

Remove the assertion.

Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Rewrote the commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/core/clock.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/core/clock.c b/hw/core/clock.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/clock.c
+++ b/hw/core/clock.c
@@ -XXX,XX +XXX,XX @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
 
 void clock_propagate(Clock *clk)
 {
-    assert(clk->source == NULL);
     trace_clock_propagate(CLOCK_PATH(clk));
     clock_propagate_period(clk, true);
 }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable. This means that it should not
have alignment restrictions enforced.

Cc: qemu-stable@nongnu.org
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
Reported-by: Clément Chigot <chigot@adacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Clément Chigot <chigot@adacore.com>
Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
[PMM: trivial comment, commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/hflags.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/hflags.c
+++ b/target/arm/tcg/hflags.c
@@ -XXX,XX +XXX,XX @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
     }
 
     /*
-     * If translation is disabled, then the default memory type is
-     * Device(-nGnRnE) instead of Normal, which requires that alignment
+     * With PMSA, when the MPU is disabled, all memory types in the
+     * default map are Normal, so don't need aligment enforcing.
+     */
+    if (arm_feature(env, ARM_FEATURE_PMSA)) {
+        return false;
+    }
+
+    /*
+     * With VMSA, if translation is disabled, then the default memory type
+     * is Device(-nGnRnE) instead of Normal, which requires that alignment
      * be enforced.  Since this affects all ram, it is most efficient
      * to handle this during translation.
      */
-- 
2.34.1

As of version DDI0487K.a of the Arm ARM, some architectural features
which previously didn't have official names have been named.  Add
these to the list of features which QEMU's TCG emulation supports.
Mostly these are features which we thought of as part of baseline 8.0
support.  For SVE and SVE2, the names have been brought into line
with the FEAT_* naming convention of other extensions, and some
sub-components split into separate FEAT_ items.  In a few cases (eg
FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org
---
 docs/system/arm/emulation.rst | 38 +++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ Armv8 versions of the A-profile architecture. It also has support for
 the following architecture extensions:
 
 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
+- FEAT_AA32EL0 (Support for AArch32 at EL0)
+- FEAT_AA32EL1 (Support for AArch32 at EL1)
+- FEAT_AA32EL2 (Support for AArch32 at EL2)
+- FEAT_AA32EL3 (Support for AArch32 at EL3)
 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
+- FEAT_AA64EL0 (Support for AArch64 at EL0)
+- FEAT_AA64EL1 (Support for AArch64 at EL1)
+- FEAT_AA64EL2 (Support for AArch64 at EL2)
+- FEAT_AA64EL3 (Support for AArch64 at EL3)
+- FEAT_AdvSIMD (Advanced SIMD Extension)
 - FEAT_AES (AESD and AESE instructions)
+- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
+- FEAT_ASID16 (16 bit ASID)
 - FEAT_BBM at level 2 (Translation table break-before-make levels)
 - FEAT_BF16 (AArch64 BFloat16 instructions)
 - FEAT_BTI (Branch Target Identification)
+- FEAT_CCIDX (Extended cache index)
 - FEAT_CRC32 (CRC32 instructions)
+- FEAT_Crypto (Cryptographic Extension)
 - FEAT_CSV2 (Cache speculation variant 2)
 - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
 - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_DGH (Data gathering hint)
 - FEAT_DIT (Data Independent Timing instructions)
 - FEAT_DPB (DC CVAP instruction)
+- FEAT_DPB2 (DC CVADP instruction)
+- FEAT_Debugv8p1 (Debug with VHE)
 - FEAT_Debugv8p2 (Debug changes for v8.2)
 - FEAT_Debugv8p4 (Debug changes for v8.4)
 - FEAT_DotProd (Advanced SIMD dot product instructions)
 - FEAT_DoubleFault (Double Fault Extension)
 - FEAT_E0PD (Preventing EL0 access to halves of address maps)
 - FEAT_ECV (Enhanced Counter Virtualization)
+- FEAT_EL0 (Support for execution at EL0)
+- FEAT_EL1 (Support for execution at EL1)
+- FEAT_EL2 (Support for execution at EL2)
+- FEAT_EL3 (Support for execution at EL3)
 - FEAT_EPAC (Enhanced pointer authentication)
 - FEAT_ETS (Enhanced Translation Synchronization)
 - FEAT_EVT (Enhanced Virtualization Traps)
+- FEAT_F32MM (Single-precision Matrix Multiplication)
+- FEAT_F64MM (Double-precision Matrix Multiplication)
 - FEAT_FCMA (Floating-point complex number instructions)
 - FEAT_FGT (Fine-Grained Traps)
 - FEAT_FHM (Floating-point half-precision multiplication instructions)
+- FEAT_FP (Floating Point extensions)
 - FEAT_FP16 (Half-precision floating-point data processing)
 - FEAT_FPAC (Faulting on AUT* instructions)
 - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_LSE (Large System Extensions)
 - FEAT_LSE2 (Large System Extensions v2)
 - FEAT_LVA (Large Virtual Address space)
+- FEAT_MixedEnd (Mixed-endian support)
+- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
 - FEAT_MOPS (Standardization of memory operations)
 - FEAT_MTE (Memory Tagging Extension)
 - FEAT_MTE2 (Memory Tagging Extension)
 - FEAT_MTE3 (MTE Asymmetric Fault Handling)
+- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
 - FEAT_NMI (Non-maskable Interrupt)
 - FEAT_NV (Nested Virtualization)
 - FEAT_NV2 (Enhanced nested virtualization support)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_PAuth (Pointer authentication)
 - FEAT_PAuth2 (Enhancements to pointer authentication)
 - FEAT_PMULL (PMULL, PMULL2 instructions)
+- FEAT_PMUv3 (PMU extension version 3)
 - FEAT_PMUv3p1 (PMU Extensions v3.1)
 - FEAT_PMUv3p4 (PMU Extensions v3.4)
 - FEAT_PMUv3p5 (PMU Extensions v3.5)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
 - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
 - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
+- FEAT_SVE (Scalable Vector Extension)
+- FEAT_SVE_AES (Scalable Vector AES instructions)
+- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
+- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
+- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
+- FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
+- FEAT_SVE2 (Scalable Vector Extension version 2)
 - FEAT_SPECRES (Speculation restriction instructions)
 - FEAT_SSBS (Speculative Store Bypass Safe)
+- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
+- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
+- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
 - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
 - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
 - FEAT_TLBIRANGE (TLB invalidate range instructions)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_VHE (Virtualization Host Extensions)
 - FEAT_VMID16 (16-bit VMID)
 - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
-- SVE (The Scalable Vector Extension)
-- SVE2 (The Scalable Vector Extension v2)
 
 For information on the specifics of these extensions, please refer
 to the `Armv8-A Arm Architecture Reference Manual
-- 
2.34.1

FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose
information about whether branch targets and branch history trained
in one hardware described context can control speculative execution
in a different hardware context.

There is no branch prediction in TCG, so we don't need to do anything
to be compliant with this.  Upadte the '-cpu max' ID registers to
advertise the feature.

FEAT_ETS2 is a tighter set of guarantees about memory ordering
involving translation table walks than the old FEAT_ETS; FEAT_ETS has
been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
now gives no greater guarantees than ETS == 0.

FEAT_ETS2 requires:
 * the virtual address of a load or store that appears in program
   order after a DSB cannot be translated until after the DSB
   completes (section B2.10.9)
 * TLB maintenance operations that only affect translations without
   execute permission are guaranteed complete after a DSB
   (R_BLDZX)
 * if a memory access RW2 is ordered-before memory access RW2,
   then RW1 is also ordered-before any translation table walk
   generated by RW2 that generates a Translation, Address size
   or Access flag fault (R_NNFPF, I_CLGHP)

As with FEAT_ETS, QEMU is already compliant, because we do not
reorder translation table walk memory accesses relative to other
memory accesses, and we always guarantee to have finished TLB
maintenance as soon as the TLB op is done.

Update the documentation to list FEAT_ETS2 instead of the
no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
---
 docs/system/arm/emulation.rst | 2 +-
 target/arm/tcg/cpu32.c        | 2 +-
 target/arm/tcg/cpu64.c        | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

Newer versions of the Arm ARM (e.g.  rev K.a) now define fields for
ID_AA64MMFR3_EL1.  Implement this register, so that we can set the
fields if we need to.  There's no behaviour change here since we
don't currently set the register value to non-zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
---
 target/arm/cpu.h     | 17 +++++++++++++++++
 target/arm/helper.c  |  6 ++++--
 target/arm/hvf/hvf.c |  2 ++
 target/arm/kvm.c     |  2 ++
 4 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
         uint64_t id_aa64mmfr0;
         uint64_t id_aa64mmfr1;
         uint64_t id_aa64mmfr2;
+        uint64_t id_aa64mmfr3;
         uint64_t id_aa64dfr0;
         uint64_t id_aa64dfr1;
         uint64_t id_aa64zfr0;
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
 FIELD(ID_AA64MMFR2, EVT, 56, 4)
 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
 
+FIELD(ID_AA64MMFR3, TCRX, 0, 4)
+FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
+FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
+FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
+FIELD(ID_AA64MMFR3, S1POE, 16, 4)
+FIELD(ID_AA64MMFR3, S2POE, 20, 4)
+FIELD(ID_AA64MMFR3, AIE, 24, 4)
+FIELD(ID_AA64MMFR3, MEC, 28, 4)
+FIELD(ID_AA64MMFR3, D128, 32, 4)
+FIELD(ID_AA64MMFR3, D128_2, 36, 4)
+FIELD(ID_AA64MMFR3, SNERR, 40, 4)
+FIELD(ID_AA64MMFR3, ANERR, 44, 4)
+FIELD(ID_AA64MMFR3, SDERR, 52, 4)
+FIELD(ID_AA64MMFR3, ADERR, 56, 4)
+FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
+
 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
               .resetvalue = cpu->isar.id_aa64mmfr2 },
-            { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+            { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
-              .resetvalue = 0 },
+              .resetvalue = cpu->isar.id_aa64mmfr3 },
             { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
               .access = PL1_R, .type = ARM_CP_CONST,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
             { .name = "ID_AA64MMFR2_EL1",
               .exported_bits = R_ID_AA64MMFR2_AT_MASK },
+            { .name = "ID_AA64MMFR3_EL1",
+              .exported_bits = 0 },
             { .name = "ID_AA64MMFR*_EL1_RESERVED",
               .is_glob = true },
             { .name = "ID_AA64DFR0_EL1",
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ static struct hvf_sreg_match hvf_sreg_match[] = {
 #endif
     { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
     { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
+    /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
 
     { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
     { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
@@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
         { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
         { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
+        /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
     };
     hv_vcpu_t fd;
     hv_return_t r = HV_SUCCESS;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
                               ARM64_SYS_REG(3, 0, 0, 7, 1));
         err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
                               ARM64_SYS_REG(3, 0, 0, 7, 2));
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3,
+                              ARM64_SYS_REG(3, 0, 0, 7, 3));
 
         /*
          * Note that if AArch32 support is not present in the host,
-- 
2.34.1

FEAT_Spec_FPACC is a feature describing speculative behaviour in the
event of a PAC authontication failure when FEAT_FPACCOMBINE is
implemented.  FEAT_Spec_FPACC means that the speculative use of
pointers processed by a PAC Authentication is not materially
different in terms of the impact on cached microarchitectural state
(caches, TLBs, etc) between passing and failing of the PAC
Authentication.

QEMU doesn't do speculative execution, so we can advertise
this feature.

The Linux kernel 5.10.16 binary for sunxi has been removed from
apt.armbian.com. This means that the avocado tests for these machines
will be skipped (status CANCEL) if the old binary isn't present in
the avocado cache.

Update to 6.6.16, in the same way we did in commit e384db41d8661
when we moved to 5.10.16 in 2021.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org
---
 tests/avocado/boot_linux_console.py | 70 ++++++++++++++---------------
 tests/avocado/replay_kernel.py      |  8 ++--
 2 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
         :avocado: tags=accel:tcg
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
         :avocado: tags=accel:tcg
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u(self):
         :avocado: tags=machine:bpim2u
         :avocado: tags=accel:tcg
         """
-        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
-                   'linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+        deb_url = ('https://apt.armbian.com/pool/main/l/'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                     'sun8i-r40-bananapi-m2-ultra.dtb')
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
 
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_initrd(self):
         :avocado: tags=accel:tcg
         :avocado: tags=machine:bpim2u
         """
-        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
-                   'linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+        deb_url = ('https://apt.armbian.com/pool/main/l/'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                     'sun8i-r40-bananapi-m2-ultra.dtb')
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_gmac(self):
         """
         self.require_netdev('user')
 
-        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
-                   'linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+        deb_url = ('https://apt.armbian.com/pool/main/l/'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                     'sun8i-r40-bananapi-m2-ultra.dtb')
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self):
         :avocado: tags=accel:tcg
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
 
         self.vm.set_console()
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self):
         :avocado: tags=machine:orangepi-pc
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
         self.require_netdev('user')
 
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
                       'buildroot-baseline/20221116.0/armel/rootfs.ext2.xz')
diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/replay_kernel.py
+++ b/tests/avocado/replay_kernel.py
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
         :avocado: tags=machine:cubieboard
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
-- 
2.34.1

The generic timer frequency is settable by board code via a QOM
property "cntfrq", but otherwise defaults to 62.5MHz.  The way this
is done includes some complication resulting from how this was
originally a fixed value with no QOM property.  Clean it up:

* always set cpu->gt_cntfrq_hz to some sensible value, whether
   the CPU has the generic timer or not, and whether it's system
   or user-only emulation
 * this means we can always use gt_cntfrq_hz, and never need
   the old GTIMER_SCALE define
 * set the default value in exactly one place, in the realize fn

The aim here is to pave the way for handling the ARMv8.6 requirement
that the generic timer frequency is always 1GHz.  We're going to do
that by having old CPU types keep their legacy-in-QEMU behaviour and
having the default for any new CPU types be a 1GHz rather han 62.5MHz
cntfrq, so we want the point where the default is decided to be in
one place, and in code, not in a DEFINE_PROP_UINT64() initializer.

This commit should have no behavioural changes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
---
 target/arm/internals.h |  7 ++++---
 target/arm/cpu.c       | 31 +++++++++++++++++--------------
 target/arm/helper.c    | 16 ++++++++--------
 3 files changed, 29 insertions(+), 25 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
         || excp == EXCP_SEMIHOST;
 }
 
-/* Scale factor for generic timers, ie number of ns per tick.
- * This gives a 62.5MHz timer.
+/*
+ * Default frequency for the generic timer, in Hz.
+ * This is 62.5MHz, which gives a 16 ns tick period.
  */
-#define GTIMER_SCALE 16
+#define GTIMER_DEFAULT_HZ 62500000
 
 /* Bit definitions for the v7M CONTROL register */
 FIELD(V7M_CONTROL, NPRIV, 0, 1)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
     }
 }
 
+/*
+ * 0 means "unset, use the default value". That default might vary depending
+ * on the CPU type, and is set in the realize fn.
+ */
 static Property arm_cpu_gt_cntfrq_property =
-            DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
-                               NANOSECONDS_PER_SECOND / GTIMER_SCALE);
+            DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
 
 static Property arm_cpu_reset_cbar_property =
             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         return;
     }
 
+    if (!cpu->gt_cntfrq_hz) {
+        /*
+         * 0 means "the board didn't set a value, use the default".
+         * The default value of the generic timer frequency (as seen in
+         * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
+         * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
+         * board doesn't set it.
+         */
+        cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
+    }
+
 #ifndef CONFIG_USER_ONLY
     /* The NVIC and M-profile CPU are two halves of a single piece of
      * hardware; trying to use one without the other is a command line
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     {
-        uint64_t scale;
-
-        if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
-            if (!cpu->gt_cntfrq_hz) {
-                error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
-                           cpu->gt_cntfrq_hz);
-                return;
-            }
-            scale = gt_cntfrq_period_ns(cpu);
-        } else {
-            scale = GTIMER_SCALE;
-        }
+        uint64_t scale = gt_cntfrq_period_ns(cpu);
 
         cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
                                                arm_gt_ptimer_cb, cpu);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
       .resetvalue = 0 },
 };
 
+static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
+}
+
 #ifndef CONFIG_USER_ONLY
 
 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ void arm_gt_hvtimer_cb(void *opaque)
     gt_recalc_timer(cpu, GTIMER_HYPVIRT);
 }
 
-static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
-{
-    ARMCPU *cpu = env_archcpu(env);
-
-    cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
-}
-
 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     /*
      * Note that CNTFRQ is purely reads-as-written for the benefit
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
       .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
-      .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
+      .resetfn = arm_gt_cntfrq_reset,
     },
     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
-- 
2.34.1

Currently QEMU CPUs always run with a generic timer counter frequency
of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz.  For older versions of
the TF-A firmware that sbsa-ref runs, the frequency of the generic
timer is hardcoded into the firmware, and so if the CPU actually has
a different frequency then timers in the guest will be set
incorrectly.

The default frequency used by the 'max' CPU is about to change, so
make the sbsa-ref board force the CPU frequency to the value which
the firmware expects.

Newer versions of TF-A will read the frequency from the CPU's
CNTFRQ_EL0 register:
 https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148
so in the longer term we could make this board use the 1GHz
frequency. We will need to make sure we update the binaries used
by our avocado test
 Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
before we can do that.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
---
 hw/arm/sbsa-ref.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@
 #define NUM_SMMU_IRQS   4
 #define NUM_SATA_PORTS  6
 
+/*
+ * Generic timer frequency in Hz (which drives both the CPU generic timers
+ * and the SBSA watchdog-timer). Older versions of the TF-A firmware
+ * typically used with sbsa-ref (including the binaries in our Avocado test
+ * Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
+ * assume it is this value.
+ *
+ * TODO: this value is not architecturally correct for an Armv8.6 or
+ * better CPU, so we should move to 1GHz once the TF-A fix above has
+ * made it into a release and into our Avocado test.
+ */
+#define SBSA_GTIMER_HZ 62500000
+
 enum {
     SBSA_FLASH,
     SBSA_MEM,
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
                                     &error_abort);
         }
 
+        object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort);
+
         object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
                                  &error_abort);
 
-- 
2.34.1

Currently the sbsa_gdwt watchdog device hardcodes its frequency at
62.5MHz. In real hardware, this watchdog is supposed to be driven
from the system counter, which also drives the CPU generic timers.
Newer CPU types (in particular from Armv8.6) should have a CPU
generic timer frequency of 1GHz, so we can't leave the watchdog
on the old QEMU default of 62.5GHz.

Make the frequency a QOM property so it can be set by the board,
and have our only board that uses this device set that frequency
to the same value it sets the CPU frequency.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
---
 include/hw/watchdog/sbsa_gwdt.h |  3 +--
 hw/arm/sbsa-ref.c               |  1 +
 hw/watchdog/sbsa_gwdt.c         | 15 ++++++++++++++-
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/watchdog/sbsa_gwdt.h
+++ b/include/hw/watchdog/sbsa_gwdt.h
@@ -XXX,XX +XXX,XX @@
 #define SBSA_GWDT_RMMIO_SIZE 0x1000
 #define SBSA_GWDT_CMMIO_SIZE 0x1000
 
-#define SBSA_TIMER_FREQ      62500000 /* Hz */
-
 typedef struct SBSA_GWDTState {
     /* <private> */
     SysBusDevice parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct SBSA_GWDTState {
     qemu_irq irq;
 
     QEMUTimer *timer;
+    uint64_t freq;
 
     uint32_t id;
     uint32_t wcs;
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_wdt(const SBSAMachineState *sms)
     SysBusDevice *s = SYS_BUS_DEVICE(dev);
     int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
 
+    qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ);
     sysbus_realize_and_unref(s, &error_fatal);
     sysbus_mmio_map(s, 0, rbase);
     sysbus_mmio_map(s, 1, cbase);
diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/sbsa_gwdt.c
+++ b/hw/watchdog/sbsa_gwdt.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "sysemu/reset.h"
 #include "sysemu/watchdog.h"
+#include "hw/qdev-properties.h"
 #include "hw/watchdog/sbsa_gwdt.h"
 #include "qemu/timer.h"
 #include "migration/vmstate.h"
@@ -XXX,XX +XXX,XX @@ static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
         timeout = s->woru;
         timeout <<= 32;
         timeout |= s->worl;
-        timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
+        timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, s->freq);
         timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 
         if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
                 dev);
 }
 
+static Property wdt_sbsa_gwdt_props[] = {
+    /*
+     * Timer frequency in Hz. This must match the frequency used by
+     * the CPU's generic timer. Default 62.5Hz matches QEMU's legacy
+     * CPU timer frequency default.
+     */
+    DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq,
+                       62500000),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
     set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
     dc->vmsd = &vmstate_sbsa_gwdt;
     dc->desc = "SBSA-compliant generic watchdog device";
+    device_class_set_props(dc, wdt_sbsa_gwdt_props);
 }
 
 static const TypeInfo wdt_sbsa_gwdt_info = {
-- 
2.34.1

In previous versions of the Arm architecture, the frequency of the
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
In Armv8.6, the architecture standardized this frequency to 1GHz.

Because there is no ID register feature field that indicates whether
a CPU is v8.6 or that it ought to have this counter frequency, we
implement this by changing our default CNTFRQ value for all CPUs,
with exceptions for backwards compatibility:

* CPU types which we already implement will retain the old
   default value. None of these are v8.6 CPUs, so this is
   architecturally OK.
 * CPUs used in versioned machine types with a version of 9.0
   or earlier will retain the old default value.

The upshot is that the only CPU type that changes is 'max'; but any
new type we add in future (whether v8.6 or not) will also get the new
1GHz default.

It remains the case that the machine model can override the default
value via the 'cntfrq' QOM property (regardless of the CPU type).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 11 +++++++++++
 target/arm/internals.h | 12 ++++++++++--
 hw/core/machine.c      |  4 +++-
 target/arm/cpu.c       | 23 +++++++++++++++++------
 target/arm/cpu64.c     |  2 ++
 target/arm/tcg/cpu32.c |  4 ++++
 target/arm/tcg/cpu64.c | 18 ++++++++++++++++++
 7 files changed, 65 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      */
     bool host_cpu_probe_failed;
 
+    /* QOM property to indicate we should use the back-compat CNTFRQ default */
+    bool backcompat_cntfrq;
+
     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
      * register.
      */
@@ -XXX,XX +XXX,XX @@ enum arm_features {
     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
     ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
+    /*
+     * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
+     * if the board doesn't set a value, instead of 1GHz. It is for backwards
+     * compatibility and used only with CPU definitions that were already
+     * in QEMU before we changed the default. It should not be set on any
+     * CPU types added in future.
+     */
+    ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
 };
 
 static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
 
 /*
  * Default frequency for the generic timer, in Hz.
- * This is 62.5MHz, which gives a 16 ns tick period.
+ * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
+ * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
+ * which gives a 16ns tick period.
+ *
+ * We will use the back-compat value:
+ *  - for QEMU CPU types added before we standardized on 1GHz
+ *  - for versioned machine types with a version of 9.0 or earlier
+ * In any case, the machine model may override via the cntfrq property.
  */
-#define GTIMER_DEFAULT_HZ 62500000
+#define GTIMER_DEFAULT_HZ 1000000000
+#define GTIMER_BACKCOMPAT_HZ 62500000
 
 /* Bit definitions for the v7M CONTROL register */
 FIELD(V7M_CONTROL, NPRIV, 0, 1)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/virtio/virtio-iommu.h"
 #include "audio/audio.h"
 
-GlobalProperty hw_compat_9_0[] = {};
+GlobalProperty hw_compat_9_0[] = {
+    {"arm-cpu", "backcompat-cntfrq", "true" },
+};
 const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0);
 
 GlobalProperty hw_compat_8_2[] = {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
     if (!cpu->gt_cntfrq_hz) {
         /*
-         * 0 means "the board didn't set a value, use the default".
-         * The default value of the generic timer frequency (as seen in
-         * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
-         * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
-         * board doesn't set it.
+         * 0 means "the board didn't set a value, use the default". (We also
+         * get here for the CONFIG_USER_ONLY case.)
+         * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
+         * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
+         * which gives a 16ns tick period.
+         *
+         * We will use the back-compat value:
+         *  - for QEMU CPU types added before we standardized on 1GHz
+         *  - for versioned machine types with a version of 9.0 or earlier
          */
-        cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
+        if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
+            cpu->backcompat_cntfrq) {
+            cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
+        } else {
+            cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
+        }
     }
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_properties[] = {
                         mp_affinity, ARM64_AFFINITY_INVALID),
     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
     DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
+    /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
+    DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
     DEFINE_PROP_END_OF_LIST()
 };
 
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_PMSA);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
     cpu->midr = 0x411fd133; /* r1p3 */
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a55_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n2_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     uint64_t t;
     uint32_t u;
 
+    /*
+     * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
+     * to because we started with aarch64_a57_initfn(). A 'max' CPU might
+     * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and
+     * because it is our "may change" CPU type we are OK with it not being
+     * backwards-compatible with how it worked in old QEMU.
+     */
+    unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
+
     /*
      * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
      * one and try to apply errata workarounds or use impdef features we
-- 
2.34.1

From: Alexandra Diupina <adiupina@astralinux.ru>

The DMA descriptor structures for this device have
a set of "address extension" fields which extend the 32
bit source addresses with an extra 16 bits to give a
48 bit address:
 https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field

However, we misimplemented this address extension in several ways:
 * we only extracted 12 bits of the extension fields, not 16
 * we didn't shift the extension field up far enough
 * we accidentally did the shift as 32-bit arithmetic, which
   meant that we would have an overflow instead of setting
   bits [47:32] of the resulting 64-bit address

Add a type cast and use extract64() instead of extract32()
to avoid integer overflow on addition. Fix bit fields
extraction according to documentation.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Cc: qemu-stable@nongnu.org
Fixes: d3c6369a96 ("introduce xlnx-dpdma")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Message-id: 20240428181131.23801-1-adiupina@astralinux.ru
[PMM: adjusted commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/dma/xlnx_dpdma.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/xlnx_dpdma.c
+++ b/hw/dma/xlnx_dpdma.c
@@ -XXX,XX +XXX,XX @@ static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
 
     switch (frag) {
     case 0:
-        addr = desc->source_address
-            + (extract32(desc->address_extension, 16, 12) << 20);
+        addr = (uint64_t)desc->source_address
+            + (extract64(desc->address_extension, 16, 16) << 32);
         break;
     case 1:
-        addr = desc->source_address2
-            + (extract32(desc->address_extension_23, 0, 12) << 8);
+        addr = (uint64_t)desc->source_address2
+            + (extract64(desc->address_extension_23, 0, 16) << 32);
         break;
     case 2:
-        addr = desc->source_address3
-            + (extract32(desc->address_extension_23, 16, 12) << 20);
+        addr = (uint64_t)desc->source_address3
+            + (extract64(desc->address_extension_23, 16, 16) << 32);
         break;
     case 3:
-        addr = desc->source_address4
-            + (extract32(desc->address_extension_45, 0, 12) << 8);
+        addr = (uint64_t)desc->source_address4
+            + (extract64(desc->address_extension_45, 0, 16) << 32);
         break;
     case 4:
-        addr = desc->source_address5
-            + (extract32(desc->address_extension_45, 16, 12) << 20);
+        addr = (uint64_t)desc->source_address5
+            + (extract64(desc->address_extension_45, 16, 16) << 32);
         break;
     default:
         addr = 0;
-- 
2.34.1

From: Thomas Huth <thuth@redhat.com>

"make check-qtest-aarch64" recently started failing on FreeBSD builds,
and valgrind on Linux also detected that there is something fishy with
the new stm32l4x5-usart: The code forgot to set the correct class_size
here, so the various class_init functions in this file wrote beyond
the allocated buffer when setting the subc->type field.

Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240429075908.36302-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/stm32l4x5_usart.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/stm32l4x5_usart.c
+++ b/hw/char/stm32l4x5_usart.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stm32l4x5_usart_types[] = {
         .parent         = TYPE_SYS_BUS_DEVICE,
         .instance_size  = sizeof(Stm32l4x5UsartBaseState),
         .instance_init  = stm32l4x5_usart_base_init,
+        .class_size     = sizeof(Stm32l4x5UsartBaseClass),
         .class_init     = stm32l4x5_usart_base_class_init,
         .abstract       = true,
     }, {
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Use little endian for derivative OTP fuse key.

Cc: qemu-stable@nongnu.org
Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model")
Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240422125813.1403-1-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
+#include "qemu/bswap.h"
 #include "qemu/units.h"
 #include "sysemu/sysemu.h"
 #include "target/arm/cpu-qom.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
      * The initial mask of disabled modules indicates the chip derivative (e.g.
      * NPCM750 or NPCM730).
      */
-    value = tswap32(nc->disabled_modules);
+    value = cpu_to_le32(nc->disabled_modules);
     npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
                             sizeof(value));
 }
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. The columns of the matrix are
driven by the DM163 and the rows are driven externally.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr
[PMM: updated to new reset hold method prototype]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/b-l475e-iot01a.rst |   3 +-
 include/hw/display/dm163.h         |  59 +++++
 hw/display/dm163.c                 | 349 +++++++++++++++++++++++++++++
 hw/display/Kconfig                 |   3 +
 hw/display/meson.build             |   1 +
 hw/display/trace-events            |  14 ++
 6 files changed, 428 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/display/dm163.h
 create mode 100644 hw/display/dm163.c

diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/b-l475e-iot01a.rst
+++ b/docs/system/arm/b-l475e-iot01a.rst
@@ -XXX,XX +XXX,XX @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors.
 Supported devices
 """""""""""""""""
 
-Currently B-L475E-IOT01A machine's only supports the following devices:
+Currently B-L475E-IOT01A machines support the following devices:
 
 - Cortex-M4F based STM32L4x5 SoC
 - STM32L4x5 EXTI (Extended interrupts and events controller)
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
 - STM32L4x5 RCC (Reset and clock control)
 - STM32L4x5 GPIOs (General-purpose I/Os)
 - STM32L4x5 USARTs, UARTs and LPUART (Serial ports)
+- optional 8x8 led display (based on DM163 driver)
 
 Missing devices
 """""""""""""""
diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/display/dm163.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU DM163 8x3-channel constant current led driver
+ * driving columns of associated 8x8 RGB matrix.
+ *
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_DISPLAY_DM163_H
+#define HW_DISPLAY_DM163_H
+
+#include "qom/object.h"
+#include "hw/qdev-core.h"
+
+#define TYPE_DM163 "dm163"
+OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163);
+
+#define RGB_MATRIX_NUM_ROWS 8
+#define RGB_MATRIX_NUM_COLS 8
+#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3)
+/* The last row is filled with 0 (turned off row) */
+#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1)
+
+typedef struct DM163State {
+    DeviceState parent_obj;
+
+    /* DM163 driver */
+    uint64_t bank0_shift_register[3];
+    uint64_t bank1_shift_register[3];
+    uint16_t latched_outputs[DM163_NUM_LEDS];
+    uint16_t outputs[DM163_NUM_LEDS];
+    qemu_irq sout;
+
+    uint8_t sin;
+    uint8_t dck;
+    uint8_t rst_b;
+    uint8_t lat_b;
+    uint8_t selbk;
+    uint8_t en_b;
+
+    /* IM120417002 colors shield */
+    uint8_t activated_rows;
+
+    /* 8x8 RGB matrix */
+    QemuConsole *console;
+    uint8_t redraw;
+    /* Rows currently being displayed on the matrix. */
+    /* The last row is filled with 0 (turned off row) */
+    uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS];
+    uint8_t last_buffer_idx;
+    uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS];
+    /* Used to simulate retinal persistence of rows */
+    uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS];
+} DM163State;
+
+#endif /* HW_DISPLAY_DM163_H */
diff --git a/hw/display/dm163.c b/hw/display/dm163.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/display/dm163.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU DM163 8x3-channel constant current led driver
+ * driving columns of associated 8x8 RGB matrix.
+ *
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+/*
+ * The reference used for the DM163 is the following :
+ * http://www.siti.com.tw/product/spec/LED/DM163.pdf
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/display/dm163.h"
+#include "ui/console.h"
+#include "trace.h"
+
+#define LED_SQUARE_SIZE 100
+/* Number of frames a row stays visible after being turned off. */
+#define ROW_PERSISTENCE 3
+#define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1)
+
+static const VMStateDescription vmstate_dm163 = {
+    .name = TYPE_DM163,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (const VMStateField[]) {
+        VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3),
+        VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3),
+        VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS),
+        VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS),
+        VMSTATE_UINT8(dck, DM163State),
+        VMSTATE_UINT8(en_b, DM163State),
+        VMSTATE_UINT8(lat_b, DM163State),
+        VMSTATE_UINT8(rst_b, DM163State),
+        VMSTATE_UINT8(selbk, DM163State),
+        VMSTATE_UINT8(sin, DM163State),
+        VMSTATE_UINT8(activated_rows, DM163State),
+        VMSTATE_UINT32_2DARRAY(buffer, DM163State, COLOR_BUFFER_SIZE,
+                               RGB_MATRIX_NUM_COLS),
+        VMSTATE_UINT8(last_buffer_idx, DM163State),
+        VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_ROWS),
+        VMSTATE_UINT8_ARRAY(row_persistence_delay, DM163State,
+                            RGB_MATRIX_NUM_ROWS),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void dm163_reset_hold(Object *obj, ResetType type)
+{
+    DM163State *s = DM163(obj);
+
+    s->sin = 0;
+    s->dck = 0;
+    s->rst_b = 0;
+    /* Ensuring the first falling edge of lat_b isn't missed */
+    s->lat_b = 1;
+    s->selbk = 0;
+    s->en_b = 0;
+    /* Reset stops the PWM, not the shift and latched registers. */
+    memset(s->outputs, 0, sizeof(s->outputs));
+
+    s->activated_rows = 0;
+    s->redraw = 0;
+    trace_dm163_redraw(s->redraw);
+    for (unsigned i = 0; i < COLOR_BUFFER_SIZE; i++) {
+        memset(s->buffer[i], 0, sizeof(s->buffer[0]));
+    }
+    s->last_buffer_idx = 0;
+    memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_row));
+    memset(s->row_persistence_delay, 0, sizeof(s->row_persistence_delay));
+}
+
+static void dm163_dck_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    if (new_state && !s->dck) {
+        /*
+         * On raising dck, sample selbk to get the bank to use, and
+         * sample sin for the bit to enter into the bank shift buffer.
+         */
+        uint64_t *sb =
+            s->selbk ? s->bank1_shift_register : s->bank0_shift_register;
+        /* Output the outgoing bit on sout */
+        const bool sout = (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) :
+                           sb[2] & MAKE_64BIT_MASK(15, 1)) != 0;
+        qemu_set_irq(s->sout, sout);
+        /* Enter sin into the shift buffer */
+        sb[2] = (sb[2] << 1) | ((sb[1] >> 63) & 1);
+        sb[1] = (sb[1] << 1) | ((sb[0] >> 63) & 1);
+        sb[0] = (sb[0] << 1) | s->sin;
+    }
+
+    s->dck = new_state;
+    trace_dm163_dck(new_state);
+}
+
+static void dm163_propagate_outputs(DM163State *s)
+{
+    s->last_buffer_idx = (s->last_buffer_idx + 1) % RGB_MATRIX_NUM_ROWS;
+    /* Values are output when reset is high and enable is low. */
+    if (s->rst_b && !s->en_b) {
+        memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs));
+    } else {
+        memset(s->outputs, 0, sizeof(s->outputs));
+    }
+    for (unsigned x = 0; x < RGB_MATRIX_NUM_COLS; x++) {
+        /* Grouping the 3 RGB channels in a pixel value */
+        const uint16_t b = extract16(s->outputs[3 * x + 0], 6, 8);
+        const uint16_t g = extract16(s->outputs[3 * x + 1], 6, 8);
+        const uint16_t r = extract16(s->outputs[3 * x + 2], 6, 8);
+        uint32_t rgba = 0;
+
+        trace_dm163_channels(3 * x + 2, r);
+        trace_dm163_channels(3 * x + 1, g);
+        trace_dm163_channels(3 * x + 0, b);
+
+        rgba = deposit32(rgba,  0, 8, r);
+        rgba = deposit32(rgba,  8, 8, g);
+        rgba = deposit32(rgba, 16, 8, b);
+
+        /* Led values are sent from the last one to the first one */
+        s->buffer[s->last_buffer_idx][RGB_MATRIX_NUM_COLS - x - 1] = rgba;
+    }
+    for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
+        if (s->activated_rows & (1 << row)) {
+            s->buffer_idx_of_row[row] = s->last_buffer_idx;
+            s->redraw |= (1 << row);
+            trace_dm163_redraw(s->redraw);
+        }
+    }
+}
+
+static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    s->en_b = new_state;
+    dm163_propagate_outputs(s);
+    trace_dm163_en_b(new_state);
+}
+
+static uint8_t dm163_bank0(const DM163State *s, uint8_t led)
+{
+    /*
+     * Bank 0 uses 6 bits per led, so a value may be stored accross
+     * two uint64_t entries.
+     */
+    const uint8_t low_bit = 6 * led;
+    const uint8_t low_word = low_bit / 64;
+    const uint8_t high_word = (low_bit + 5) / 64;
+    const uint8_t low_shift = low_bit % 64;
+
+    if (low_word == high_word) {
+        /* Simple case: the value belongs to one entry. */
+        return extract64(s->bank0_shift_register[low_word], low_shift, 6);
+    }
+
+    const uint8_t nb_bits_in_low_word = 64 - low_shift;
+    const uint8_t nb_bits_in_high_word = 6 - nb_bits_in_low_word;
+
+    const uint64_t bits_in_low_word = \
+        extract64(s->bank0_shift_register[low_word], low_shift,
+                  nb_bits_in_low_word);
+    const uint64_t bits_in_high_word = \
+        extract64(s->bank0_shift_register[high_word], 0,
+                  nb_bits_in_high_word);
+    uint8_t val = 0;
+
+    val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word);
+    val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word,
+                    bits_in_high_word);
+
+    return val;
+}
+
+static uint8_t dm163_bank1(const DM163State *s, uint8_t led)
+{
+    const uint64_t entry = s->bank1_shift_register[led / RGB_MATRIX_NUM_COLS];
+    return extract64(entry, 8 * (led % RGB_MATRIX_NUM_COLS), 8);
+}
+
+static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    if (s->lat_b && !new_state) {
+        for (int led = 0; led < DM163_NUM_LEDS; led++) {
+            s->latched_outputs[led] = dm163_bank0(s, led) * dm163_bank1(s, led);
+        }
+        dm163_propagate_outputs(s);
+    }
+
+    s->lat_b = new_state;
+    trace_dm163_lat_b(new_state);
+}
+
+static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    s->rst_b = new_state;
+    dm163_propagate_outputs(s);
+    trace_dm163_rst_b(new_state);
+}
+
+static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    s->selbk = new_state;
+    trace_dm163_selbk(new_state);
+}
+
+static void dm163_sin_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    s->sin = new_state;
+    trace_dm163_sin(new_state);
+}
+
+static void dm163_rows_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    if (new_state) {
+        s->activated_rows |= (1 << line);
+        s->buffer_idx_of_row[line] = s->last_buffer_idx;
+        s->redraw |= (1 << line);
+        trace_dm163_redraw(s->redraw);
+    } else {
+        s->activated_rows &= ~(1 << line);
+        s->row_persistence_delay[line] = ROW_PERSISTENCE;
+    }
+    trace_dm163_activated_rows(s->activated_rows);
+}
+
+static void dm163_invalidate_display(void *opaque)
+{
+    DM163State *s = (DM163State *)opaque;
+    s->redraw = 0xFF;
+    trace_dm163_redraw(s->redraw);
+}
+
+static void update_row_persistence_delay(DM163State *s, unsigned row)
+{
+    if (s->row_persistence_delay[row]) {
+        s->row_persistence_delay[row]--;
+    } else {
+        /*
+         * If the ROW_PERSISTENCE delay is up,
+         * the row is turned off.
+         */
+        s->buffer_idx_of_row[row] = TURNED_OFF_ROW;
+        s->redraw |= (1 << row);
+        trace_dm163_redraw(s->redraw);
+    }
+}
+
+static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest,
+                                       unsigned row)
+{
+    for (unsigned _ = 0; _ < LED_SQUARE_SIZE; _++) {
+        for (int x = 0; x < RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE; x++) {
+            /* UI layer guarantees that there's 32 bits per pixel (Mar 2024) */
+            *dest++ = s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUARE_SIZE];
+        }
+    }
+
+    dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row,
+                    RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE);
+    s->redraw &= ~(1 << row);
+    trace_dm163_redraw(s->redraw);
+
+    return dest;
+}
+
+static void dm163_update_display(void *opaque)
+{
+    DM163State *s = (DM163State *)opaque;
+    DisplaySurface *surface = qemu_console_surface(s->console);
+    uint32_t *dest;
+
+    dest = surface_data(surface);
+    for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
+        update_row_persistence_delay(s, row);
+        if (!extract8(s->redraw, row, 1)) {
+            dest += LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_COLS;
+            continue;
+        }
+        dest = update_display_of_row(s, dest, row);
+    }
+}
+
+static const GraphicHwOps dm163_ops = {
+    .invalidate  = dm163_invalidate_display,
+    .gfx_update  = dm163_update_display,
+};
+
+static void dm163_realize(DeviceState *dev, Error **errp)
+{
+    DM163State *s = DM163(dev);
+
+    qdev_init_gpio_in(dev, dm163_rows_gpio_handler, RGB_MATRIX_NUM_ROWS);
+    qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1);
+    qdev_init_gpio_out_named(dev, &s->sout, "sout", 1);
+
+    s->console = graphic_console_init(dev, 0, &dm163_ops, s);
+    qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE,
+                        RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE);
+}
+
+static void dm163_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    dc->desc = "DM163";
+    dc->vmsd = &vmstate_dm163;
+    dc->realize = dm163_realize;
+    rc->phases.hold = dm163_reset_hold;
+    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+}
+
+static const TypeInfo dm163_types[] = {
+    {
+        .name = TYPE_DM163,
+        .parent = TYPE_DEVICE,
+        .instance_size = sizeof(DM163State),
+        .class_init = dm163_class_init
+    }
+};
+
+DEFINE_TYPES(dm163_types)
diff --git a/hw/display/Kconfig b/hw/display/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/Kconfig
+++ b/hw/display/Kconfig
@@ -XXX,XX +XXX,XX @@ config XLNX_DISPLAYPORT
     bool
     # defaults to "N", enabled by specific boards
     depends on PIXMAN
+
+config DM163
+    bool
diff --git a/hw/display/meson.build b/hw/display/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/meson.build
+++ b/hw/display/meson.build
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c'))
 
 system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c'))
 system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c'))
+system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c'))
 
 if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or
     config_all_devices.has_key('CONFIG_VGA_PCI') or
diff --git a/hw/display/trace-events b/hw/display/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -XXX,XX +XXX,XX @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%"PRI
 macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32
 macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32
 macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting mode to width %"PRId32 " height %"PRId32 " size %d"
+
+# dm163.c
+dm163_redraw(uint8_t redraw) "0x%02x"
+dm163_dck(unsigned new_state) "dck : %u"
+dm163_en_b(unsigned new_state) "en_b : %u"
+dm163_rst_b(unsigned new_state) "rst_b : %u"
+dm163_lat_b(unsigned new_state) "lat_b : %u"
+dm163_sin(unsigned new_state) "sin : %u"
+dm163_selbk(unsigned new_state) "selbk : %u"
+dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 ""
+dm163_bits_ppi(unsigned dest_width) "dest_width : %u"
+dm163_leds(int led, uint32_t value) "led %d: 0x%x"
+dm163_channels(int channel, uint8_t value) "channel %d: 0x%x"
+dm163_refresh_rate(uint32_t rr) "refresh rate %d"
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
to the optional DM163 display from the board code (GPIOs outputs need
to be connected to both SYSCFG inputs and DM163 inputs).

STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stm32l4x5_soc.c              |  6 ++++--
 tests/qtest/stm32l4x5_gpio-test.c   | 13 ++++++++-----
 tests/qtest/stm32l4x5_syscfg-test.c | 17 ++++++++++-------
 3 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -XXX,XX +XXX,XX @@
 /*
  * STM32L4x5 SoC family
  *
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
  *
  * SPDX-License-Identifier: GPL-2.0-or-later
  *
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
         }
     }
 
+    qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL);
+
     /* EXTI device */
     busdev = SYS_BUS_DEVICE(&s->exti);
     if (!sysbus_realize(busdev, errp)) {
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/stm32l4x5_gpio-test.c
+++ b/tests/qtest/stm32l4x5_gpio-test.c
@@ -XXX,XX +XXX,XX @@
 #define OTYPER_PUSH_PULL 0
 #define OTYPER_OPEN_DRAIN 1
 
+/* SoC forwards GPIOs to SysCfg */
+#define SYSCFG "/machine/soc"
+
 const uint32_t moder_reset[NUM_GPIOS] = {
     0xABFFFFFF,
     0xFFFFFEBF,
@@ -XXX,XX +XXX,XX @@ static void test_gpio_output_mode(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     unsigned int gpio_id = get_gpio_id(gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Set a bit in ODR and check nothing happens */
     gpio_set_bit(gpio, ODR, pin, 1);
@@ -XXX,XX +XXX,XX @@ static void test_gpio_input_mode(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     unsigned int gpio_id = get_gpio_id(gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Configure a line as input, raise it, and check that the pin is high */
     gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@@ -XXX,XX +XXX,XX @@ static void test_pull_up_pull_down(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     unsigned int gpio_id = get_gpio_id(gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Configure a line as input with pull-up, check the line is set high */
     gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@@ -XXX,XX +XXX,XX @@ static void test_push_pull(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Setting a line high externally, configuring it in push-pull output */
     /* And checking the pin was disconnected */
@@ -XXX,XX +XXX,XX @@ static void test_open_drain(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Setting a line high externally, configuring it in open-drain output */
     /* And checking the pin was disconnected */
diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/stm32l4x5_syscfg-test.c
+++ b/tests/qtest/stm32l4x5_syscfg-test.c
@@ -XXX,XX +XXX,XX @@
 /*
  * QTest testcase for STM32L4x5_SYSCFG
  *
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -XXX,XX +XXX,XX @@
 #define SYSCFG_SWPR2 0x28
 #define INVALID_ADDR 0x2C
 
+/* SoC forwards GPIOs to SysCfg */
+#define SYSCFG "/machine/soc"
+#define EXTI "/machine/soc/exti"
+
 static void syscfg_writel(unsigned int offset, uint32_t value)
 {
     writel(SYSCFG_BASE_ADDR + offset, value);
@@ -XXX,XX +XXX,XX @@ static uint32_t syscfg_readl(unsigned int offset)
 
 static void syscfg_set_irq(int num, int level)
 {
-   qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
-                    NULL, num, level);
+   qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
 }
 
 static void system_reset(void)
@@ -XXX,XX +XXX,XX @@ static void test_interrupt(void)
      * Test that GPIO rising lines result in an irq
      * with the right configuration
      */
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+    qtest_irq_intercept_in(global_qtest, EXTI);
 
     /* GPIOA is the default source for EXTI lines 0 to 15 */
 
@@ -XXX,XX +XXX,XX @@ static void test_irq_pin_multiplexer(void)
      * Test that syscfg irq sets the right exti irq
      */
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+    qtest_irq_intercept_in(global_qtest, EXTI);
 
     syscfg_set_irq(0, 1);
 
@@ -XXX,XX +XXX,XX @@ static void test_irq_gpio_multiplexer(void)
      * Test that an irq is generated only by the right GPIO
      */
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+    qtest_irq_intercept_in(global_qtest, EXTI);
 
     /* GPIOA is the default source for EXTI lines 0 to 15 */
 
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++-------------
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -XXX,XX +XXX,XX @@
  * B-L475E-IOT01A Discovery Kit machine
  * (B-L475E-IOT01A IoT Node)
  *
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
  *
  * SPDX-License-Identifier: GPL-2.0-or-later
  *
@@ -XXX,XX +XXX,XX @@
 
 /* B-L475E-IOT01A implementation is derived from netduinoplus2 */
 
-static void b_l475e_iot01a_init(MachineState *machine)
+#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
+OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
+
+typedef struct Bl475eMachineState {
+    MachineState parent_obj;
+
+    Stm32l4x5SocState soc;
+} Bl475eMachineState;
+
+static void bl475e_init(MachineState *machine)
 {
+    Bl475eMachineState *s = B_L475E_IOT01A(machine);
     const Stm32l4x5SocClass *sc;
-    DeviceState *dev;
 
-    dev = qdev_new(TYPE_STM32L4X5XG_SOC);
-    object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    object_initialize_child(OBJECT(machine), "soc", &s->soc,
+                            TYPE_STM32L4X5XG_SOC);
+    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
 
-    sc = STM32L4X5_SOC_GET_CLASS(dev);
-    armv7m_load_kernel(ARM_CPU(first_cpu),
-                       machine->kernel_filename,
-                       0, sc->flash_size);
+    sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
+    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
+                       sc->flash_size);
 }
 
-static void b_l475e_iot01a_machine_init(MachineClass *mc)
+static void bl475e_machine_init(ObjectClass *oc, void *data)
 {
+    MachineClass *mc = MACHINE_CLASS(oc);
     static const char *machine_valid_cpu_types[] = {
         ARM_CPU_TYPE_NAME("cortex-m4"),
         NULL
     };
     mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)";
-    mc->init = b_l475e_iot01a_init;
+    mc->init = bl475e_init;
     mc->valid_cpu_types = machine_valid_cpu_types;
 
     /* SRAM pre-allocated as part of the SoC instantiation */
     mc->default_ram_size = 0;
 }
 
-DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init)
+static const TypeInfo bl475e_machine_type[] = {
+    {
+        .name           = TYPE_B_L475E_IOT01A,
+        .parent         = TYPE_MACHINE,
+        .instance_size  = sizeof(Bl475eMachineState),
+        .class_init     = bl475e_machine_init,
+    }
+};
+
+DEFINE_TYPES(bl475e_machine_type)
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++--
 hw/arm/Kconfig          |  1 +
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "hw/qdev-properties.h"
 #include "qemu/error-report.h"
-#include "hw/arm/stm32l4x5_soc.h"
 #include "hw/arm/boot.h"
+#include "hw/core/split-irq.h"
+#include "hw/arm/stm32l4x5_soc.h"
+#include "hw/gpio/stm32l4x5_gpio.h"
+#include "hw/display/dm163.h"
 
-/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
+/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */
+
+/*
+ * There are actually 14 input pins in the DM163 device.
+ * Here the DM163 input pin EN isn't connected to the STM32L4x5
+ * GPIOs as the IM120417002 colors shield doesn't actually use
+ * this pin to drive the RGB matrix.
+ */
+#define NUM_DM163_INPUTS 13
+
+static const unsigned dm163_input[NUM_DM163_INPUTS] = {
+    1 * GPIO_NUM_PINS + 2,  /* ROW0  PB2       */
+    0 * GPIO_NUM_PINS + 15, /* ROW1  PA15      */
+    0 * GPIO_NUM_PINS + 2,  /* ROW2  PA2       */
+    0 * GPIO_NUM_PINS + 7,  /* ROW3  PA7       */
+    0 * GPIO_NUM_PINS + 6,  /* ROW4  PA6       */
+    0 * GPIO_NUM_PINS + 5,  /* ROW5  PA5       */
+    1 * GPIO_NUM_PINS + 0,  /* ROW6  PB0       */
+    0 * GPIO_NUM_PINS + 3,  /* ROW7  PA3       */
+    0 * GPIO_NUM_PINS + 4,  /* SIN (SDA) PA4   */
+    1 * GPIO_NUM_PINS + 1,  /* DCK (SCK) PB1   */
+    2 * GPIO_NUM_PINS + 3,  /* RST_B (RST) PC3 */
+    2 * GPIO_NUM_PINS + 4,  /* LAT_B (LAT) PC4 */
+    2 * GPIO_NUM_PINS + 5,  /* SELBK (SB)  PC5 */
+};
 
 #define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
 OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
@@ -XXX,XX +XXX,XX @@ typedef struct Bl475eMachineState {
     MachineState parent_obj;
 
     Stm32l4x5SocState soc;
+    SplitIRQ gpio_splitters[NUM_DM163_INPUTS];
+    DM163State dm163;
 } Bl475eMachineState;
 
 static void bl475e_init(MachineState *machine)
 {
     Bl475eMachineState *s = B_L475E_IOT01A(machine);
     const Stm32l4x5SocClass *sc;
+    DeviceState *dev, *gpio_out_splitter;
+    unsigned gpio, pin;
 
     object_initialize_child(OBJECT(machine), "soc", &s->soc,
                             TYPE_STM32L4X5XG_SOC);
@@ -XXX,XX +XXX,XX @@ static void bl475e_init(MachineState *machine)
     sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
                        sc->flash_size);
+
+    if (object_class_by_name(TYPE_DM163)) {
+        object_initialize_child(OBJECT(machine), "dm163",
+                                &s->dm163, TYPE_DM163);
+        dev = DEVICE(&s->dm163);
+        qdev_realize(dev, NULL, &error_abort);
+
+        for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) {
+            object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]",
+                                    &s->gpio_splitters[i], TYPE_SPLIT_IRQ);
+            gpio_out_splitter = DEVICE(&s->gpio_splitters[i]);
+            qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2);
+            qdev_realize(gpio_out_splitter, NULL, &error_fatal);
+
+            qdev_connect_gpio_out(gpio_out_splitter, 0,
+                qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i]));
+            qdev_connect_gpio_out(gpio_out_splitter, 1,
+                qdev_get_gpio_in(dev, i));
+            gpio = dm163_input[i] / GPIO_NUM_PINS;
+            pin = dm163_input[i] % GPIO_NUM_PINS;
+            qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin,
+                qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0));
+        }
+    }
 }
 
 static void bl475e_machine_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config B_L475E_IOT01A
     default y
     depends on TCG && ARM
     select STM32L4X5_SOC
+    imply DM163
 
 config STM32L4X5_SOC
     bool
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

`test_dm163_bank()`
Checks that the pin "sout" of the DM163 led driver outputs the values
received on pin "sin" with the expected latency (depending on the bank).

`test_dm163_gpio_connection()`
Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
DM163 device.

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/dm163-test.c | 194 +++++++++++++++++++++++++++++++++++++++
 tests/qtest/meson.build  |   2 +
 2 files changed, 196 insertions(+)
 create mode 100644 tests/qtest/dm163-test.c

diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/dm163-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTest testcase for DM163
+ *
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+
+enum DM163_INPUTS {
+    SIN = 8,
+    DCK = 9,
+    RST_B = 10,
+    LAT_B = 11,
+    SELBK = 12,
+    EN_B = 13
+};
+
+#define DEVICE_NAME "/machine/dm163"
+#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name,   \
+                                               value)
+#define GPIO_PULSE(name)                                                       \
+  do {                                                                         \
+    GPIO_OUT(name, 1);                                                         \
+    GPIO_OUT(name, 0);                                                         \
+  } while (0)
+
+
+static void rise_gpio_pin_dck(QTestState *qts)
+{
+    /* Configure output mode for pin PB1 */
+    qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
+    /* Write 1 in ODR for PB1 */
+    qtest_writel(qts, 0x48000414, 0x00000002);
+}
+
+static void lower_gpio_pin_dck(QTestState *qts)
+{
+    /* Configure output mode for pin PB1 */
+    qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
+    /* Write 0 in ODR for PB1 */
+    qtest_writel(qts, 0x48000414, 0x00000000);
+}
+
+static void rise_gpio_pin_selbk(QTestState *qts)
+{
+    /* Configure output mode for pin PC5 */
+    qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
+    /* Write 1 in ODR for PC5 */
+    qtest_writel(qts, 0x48000814, 0x00000020);
+}
+
+static void lower_gpio_pin_selbk(QTestState *qts)
+{
+    /* Configure output mode for pin PC5 */
+    qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
+    /* Write 0 in ODR for PC5 */
+    qtest_writel(qts, 0x48000814, 0x00000000);
+}
+
+static void rise_gpio_pin_lat_b(QTestState *qts)
+{
+    /* Configure output mode for pin PC4 */
+    qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
+    /* Write 1 in ODR for PC4 */
+    qtest_writel(qts, 0x48000814, 0x00000010);
+}
+
+static void lower_gpio_pin_lat_b(QTestState *qts)
+{
+    /* Configure output mode for pin PC4 */
+    qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
+    /* Write 0 in ODR for PC4 */
+    qtest_writel(qts, 0x48000814, 0x00000000);
+}
+
+static void rise_gpio_pin_rst_b(QTestState *qts)
+{
+    /* Configure output mode for pin PC3 */
+    qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
+    /* Write 1 in ODR for PC3 */
+    qtest_writel(qts, 0x48000814, 0x00000008);
+}
+
+static void lower_gpio_pin_rst_b(QTestState *qts)
+{
+    /* Configure output mode for pin PC3 */
+    qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
+    /* Write 0 in ODR for PC3 */
+    qtest_writel(qts, 0x48000814, 0x00000000);
+}
+
+static void rise_gpio_pin_sin(QTestState *qts)
+{
+    /* Configure output mode for pin PA4 */
+    qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
+    /* Write 1 in ODR for PA4 */
+    qtest_writel(qts, 0x48000014, 0x00000010);
+}
+
+static void lower_gpio_pin_sin(QTestState *qts)
+{
+    /* Configure output mode for pin PA4 */
+    qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
+    /* Write 0 in ODR for PA4 */
+    qtest_writel(qts, 0x48000014, 0x00000000);
+}
+
+static void test_dm163_bank(const void *opaque)
+{
+    const unsigned bank = (uintptr_t) opaque;
+    const int width = bank ? 192 : 144;
+
+    QTestState *qts = qtest_initf("-M b-l475e-iot01a");
+    qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout");
+    GPIO_OUT(RST_B, 1);
+    GPIO_OUT(EN_B, 0);
+    GPIO_OUT(DCK, 0);
+    GPIO_OUT(SELBK, bank);
+    GPIO_OUT(LAT_B, 1);
+
+    /* Fill bank with zeroes */
+    GPIO_OUT(SIN, 0);
+    for (int i = 0; i < width; i++) {
+        GPIO_PULSE(DCK);
+    }
+    /* Fill bank with ones, check that we get the previous zeroes */
+    GPIO_OUT(SIN, 1);
+    for (int i = 0; i < width; i++) {
+        GPIO_PULSE(DCK);
+        g_assert(!qtest_get_irq(qts, 0));
+    }
+
+    /* Pulse one more bit in the bank, check that we get a one */
+    GPIO_PULSE(DCK);
+    g_assert(qtest_get_irq(qts, 0));
+
+    qtest_quit(qts);
+}
+
+static void test_dm163_gpio_connection(void)
+{
+    QTestState *qts = qtest_init("-M b-l475e-iot01a");
+    qtest_irq_intercept_in(qts, DEVICE_NAME);
+
+    g_assert_false(qtest_get_irq(qts, SIN));
+    g_assert_false(qtest_get_irq(qts, DCK));
+    g_assert_false(qtest_get_irq(qts, RST_B));
+    g_assert_false(qtest_get_irq(qts, LAT_B));
+    g_assert_false(qtest_get_irq(qts, SELBK));
+
+    rise_gpio_pin_dck(qts);
+    g_assert_true(qtest_get_irq(qts, DCK));
+    lower_gpio_pin_dck(qts);
+    g_assert_false(qtest_get_irq(qts, DCK));
+
+    rise_gpio_pin_lat_b(qts);
+    g_assert_true(qtest_get_irq(qts, LAT_B));
+    lower_gpio_pin_lat_b(qts);
+    g_assert_false(qtest_get_irq(qts, LAT_B));
+
+    rise_gpio_pin_selbk(qts);
+    g_assert_true(qtest_get_irq(qts, SELBK));
+    lower_gpio_pin_selbk(qts);
+    g_assert_false(qtest_get_irq(qts, SELBK));
+
+    rise_gpio_pin_rst_b(qts);
+    g_assert_true(qtest_get_irq(qts, RST_B));
+    lower_gpio_pin_rst_b(qts);
+    g_assert_false(qtest_get_irq(qts, RST_B));
+
+    rise_gpio_pin_sin(qts);
+    g_assert_true(qtest_get_irq(qts, SIN));
+    lower_gpio_pin_sin(qts);
+    g_assert_false(qtest_get_irq(qts, SIN));
+
+    g_assert_false(qtest_get_irq(qts, DCK));
+    g_assert_false(qtest_get_irq(qts, LAT_B));
+    g_assert_false(qtest_get_irq(qts, SELBK));
+    g_assert_false(qtest_get_irq(qts, RST_B));
+}
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+    qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank);
+    qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank);
+    qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection);
+    return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
   (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
   (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
   (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
+  (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and
+   config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \
   ['arm-cpu-features',
    'boot-serial-test']
 
-- 
2.34.1