1 | target-arm queue: the big stuff here is the final part of | 1 | Hi; here's a target-arm pullreq. Mostly this is RTH's FEAT_RME |
---|---|---|---|
2 | rth's patches for Cortex-A76 and Neoverse-N1 support; | 2 | series; there are also a handful of bug fixes including some |
3 | also present are Gavin's NUMA series and a few other things. | 3 | which aren't arm-specific but which it's convenient to include |
4 | here. | ||
4 | 5 | ||
5 | thanks | 6 | thanks |
6 | -- PMM | 7 | -- PMM |
7 | 8 | ||
8 | The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b: | 9 | The following changes since commit b455ce4c2f300c8ba47cba7232dd03261368a4cb: |
9 | 10 | ||
10 | Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500) | 11 | Merge tag 'q800-for-8.1-pull-request' of https://github.com/vivier/qemu-m68k into staging (2023-06-22 10:18:32 +0200) |
11 | 12 | ||
12 | are available in the Git repository at: | 13 | are available in the Git repository at: |
13 | 14 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509 | 15 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230623 |
15 | 16 | ||
16 | for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34: | 17 | for you to fetch changes up to 497fad38979c16b6412388927401e577eba43d26: |
17 | 18 | ||
18 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100) | 19 | pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym (2023-06-23 11:46:02 +0100) |
19 | 20 | ||
20 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
21 | target-arm queue: | 22 | target-arm queue: |
22 | * MAINTAINERS/.mailmap: update email for Leif Lindholm | 23 | * Add (experimental) support for FEAT_RME |
23 | * hw/arm: add version information to sbsa-ref machine DT | 24 | * host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang |
24 | * Enable new features for -cpu max: | 25 | * target/arm: Restructure has_vfp_d32 test |
25 | FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only), | 26 | * hw/arm/sbsa-ref: add ITS support in SBSA GIC |
26 | FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH | 27 | * target/arm: Fix sve predicate store, 8 <= VQ <= 15 |
27 | * Emulate Cortex-A76 | 28 | * pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym |
28 | * Emulate Neoverse-N1 | ||
29 | * Fix the virt board default NUMA topology | ||
30 | 29 | ||
31 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
32 | Gavin Shan (6): | 31 | Peter Maydell (2): |
33 | qapi/machine.json: Add cluster-id | 32 | host-utils: Avoid using __builtin_subcll on buggy versions of Apple Clang |
34 | qtest/numa-test: Specify CPU topology in aarch64_numa_cpu() | 33 | pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym |
35 | hw/arm/virt: Consider SMP configuration in CPU topology | ||
36 | qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu() | ||
37 | hw/arm/virt: Fix CPU's default NUMA node ID | ||
38 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table | ||
39 | 34 | ||
40 | Leif Lindholm (2): | 35 | Richard Henderson (23): |
41 | MAINTAINERS/.mailmap: update email for Leif Lindholm | 36 | target/arm: Add isar_feature_aa64_rme |
42 | hw/arm: add versioning to sbsa-ref machine DT | 37 | target/arm: Update SCR and HCR for RME |
38 | target/arm: SCR_EL3.NS may be RES1 | ||
39 | target/arm: Add RME cpregs | ||
40 | target/arm: Introduce ARMSecuritySpace | ||
41 | include/exec/memattrs: Add two bits of space to MemTxAttrs | ||
42 | target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx | ||
43 | target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} | ||
44 | target/arm: Remove __attribute__((nonnull)) from ptw.c | ||
45 | target/arm: Pipe ARMSecuritySpace through ptw.c | ||
46 | target/arm: NSTable is RES0 for the RME EL3 regime | ||
47 | target/arm: Handle Block and Page bits for security space | ||
48 | target/arm: Handle no-execute for Realm and Root regimes | ||
49 | target/arm: Use get_phys_addr_with_struct in S1_ptw_translate | ||
50 | target/arm: Move s1_is_el0 into S1Translate | ||
51 | target/arm: Use get_phys_addr_with_struct for stage2 | ||
52 | target/arm: Add GPC syndrome | ||
53 | target/arm: Implement GPC exceptions | ||
54 | target/arm: Implement the granule protection check | ||
55 | target/arm: Add cpu properties for enabling FEAT_RME | ||
56 | docs/system/arm: Document FEAT_RME | ||
57 | target/arm: Restructure has_vfp_d32 test | ||
58 | target/arm: Fix sve predicate store, 8 <= VQ <= 15 | ||
43 | 59 | ||
44 | Richard Henderson (24): | 60 | Shashi Mallela (1): |
45 | target/arm: Handle cpreg registration for missing EL | 61 | hw/arm/sbsa-ref: add ITS support in SBSA GIC |
46 | target/arm: Drop EL3 no EL2 fallbacks | ||
47 | target/arm: Merge zcr reginfo | ||
48 | target/arm: Adjust definition of CONTEXTIDR_EL2 | ||
49 | target/arm: Move cortex impdef sysregs to cpu_tcg.c | ||
50 | target/arm: Update qemu-system-arm -cpu max to cortex-a57 | ||
51 | target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max | ||
52 | target/arm: Split out aa32_max_features | ||
53 | target/arm: Annotate arm_max_initfn with FEAT identifiers | ||
54 | target/arm: Use field names for manipulating EL2 and EL3 modes | ||
55 | target/arm: Enable FEAT_Debugv8p2 for -cpu max | ||
56 | target/arm: Enable FEAT_Debugv8p4 for -cpu max | ||
57 | target/arm: Add minimal RAS registers | ||
58 | target/arm: Enable SCR and HCR bits for RAS | ||
59 | target/arm: Implement virtual SError exceptions | ||
60 | target/arm: Implement ESB instruction | ||
61 | target/arm: Enable FEAT_RAS for -cpu max | ||
62 | target/arm: Enable FEAT_IESB for -cpu max | ||
63 | target/arm: Enable FEAT_CSV2 for -cpu max | ||
64 | target/arm: Enable FEAT_CSV2_2 for -cpu max | ||
65 | target/arm: Enable FEAT_CSV3 for -cpu max | ||
66 | target/arm: Enable FEAT_DGH for -cpu max | ||
67 | target/arm: Define cortex-a76 | ||
68 | target/arm: Define neoverse-n1 | ||
69 | 62 | ||
70 | docs/system/arm/emulation.rst | 10 + | 63 | docs/system/arm/cpu-features.rst | 23 ++ |
71 | docs/system/arm/virt.rst | 2 + | 64 | docs/system/arm/emulation.rst | 1 + |
72 | qapi/machine.json | 6 +- | 65 | docs/system/arm/sbsa.rst | 14 + |
73 | target/arm/cpregs.h | 11 + | 66 | include/exec/memattrs.h | 9 +- |
74 | target/arm/cpu.h | 23 ++ | 67 | include/qemu/compiler.h | 13 + |
75 | target/arm/helper.h | 1 + | 68 | include/qemu/host-utils.h | 2 +- |
76 | target/arm/internals.h | 16 ++ | 69 | target/arm/cpu.h | 151 ++++++++--- |
77 | target/arm/syndrome.h | 5 + | 70 | target/arm/internals.h | 27 ++ |
78 | target/arm/a32.decode | 16 +- | 71 | target/arm/syndrome.h | 10 + |
79 | target/arm/t32.decode | 18 +- | 72 | hw/arm/sbsa-ref.c | 33 ++- |
80 | hw/acpi/aml-build.c | 111 ++++---- | 73 | target/arm/cpu.c | 32 ++- |
81 | hw/arm/sbsa-ref.c | 16 ++ | 74 | target/arm/helper.c | 162 ++++++++++- |
82 | hw/arm/virt.c | 21 +- | 75 | target/arm/ptw.c | 570 +++++++++++++++++++++++++++++++-------- |
83 | hw/core/machine-hmp-cmds.c | 4 + | 76 | target/arm/tcg/cpu64.c | 53 ++++ |
84 | hw/core/machine.c | 16 ++ | 77 | target/arm/tcg/tlb_helper.c | 96 ++++++- |
85 | target/arm/cpu.c | 66 ++++- | 78 | target/arm/tcg/translate-sve.c | 2 +- |
86 | target/arm/cpu64.c | 353 ++++++++++++++----------- | 79 | pc-bios/keymaps/meson.build | 2 +- |
87 | target/arm/cpu_tcg.c | 227 +++++++++++----- | 80 | 17 files changed, 1034 insertions(+), 166 deletions(-) |
88 | target/arm/helper.c | 600 +++++++++++++++++++++++++----------------- | ||
89 | target/arm/op_helper.c | 43 +++ | ||
90 | target/arm/translate-a64.c | 18 ++ | ||
91 | target/arm/translate.c | 23 ++ | ||
92 | tests/qtest/numa-test.c | 19 +- | ||
93 | .mailmap | 3 +- | ||
94 | MAINTAINERS | 2 +- | ||
95 | 25 files changed, 1068 insertions(+), 562 deletions(-) | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The only portion of FEAT_Debugv8p2 that is relevant to QEMU | 3 | Add the missing field for ID_AA64PFR0, and the predicate. |
4 | is CONTEXTIDR_EL2, which is also conditionally implemented | 4 | Disable it if EL3 is forced off by the board or command-line. |
5 | with FEAT_VHE. The rest of the debug extension concerns the | ||
6 | External debug interface, which is outside the scope of QEMU. | ||
7 | 5 | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20220506180242.216785-12-richard.henderson@linaro.org | 9 | Message-id: 20230620124418.805717-2-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | docs/system/arm/emulation.rst | 1 + | 12 | target/arm/cpu.h | 6 ++++++ |
14 | target/arm/cpu.c | 1 + | 13 | target/arm/cpu.c | 4 ++++ |
15 | target/arm/cpu64.c | 1 + | 14 | 2 files changed, 10 insertions(+) |
16 | target/arm/cpu_tcg.c | 2 ++ | ||
17 | 4 files changed, 5 insertions(+) | ||
18 | 15 | ||
19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/docs/system/arm/emulation.rst | 18 | --- a/target/arm/cpu.h |
22 | +++ b/docs/system/arm/emulation.rst | 19 | +++ b/target/arm/cpu.h |
23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 20 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, SEL2, 36, 4) |
24 | - FEAT_BTI (Branch Target Identification) | 21 | FIELD(ID_AA64PFR0, MPAM, 40, 4) |
25 | - FEAT_DIT (Data Independent Timing instructions) | 22 | FIELD(ID_AA64PFR0, AMU, 44, 4) |
26 | - FEAT_DPB (DC CVAP instruction) | 23 | FIELD(ID_AA64PFR0, DIT, 48, 4) |
27 | +- FEAT_Debugv8p2 (Debug changes for v8.2) | 24 | +FIELD(ID_AA64PFR0, RME, 52, 4) |
28 | - FEAT_DotProd (Advanced SIMD dot product instructions) | 25 | FIELD(ID_AA64PFR0, CSV2, 56, 4) |
29 | - FEAT_FCMA (Floating-point complex number instructions) | 26 | FIELD(ID_AA64PFR0, CSV3, 60, 4) |
30 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | 27 | |
28 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) | ||
29 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; | ||
30 | } | ||
31 | |||
32 | +static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) | ||
33 | +{ | ||
34 | + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0; | ||
35 | +} | ||
36 | + | ||
37 | static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) | ||
38 | { | ||
39 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; | ||
31 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 40 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
32 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/target/arm/cpu.c | 42 | --- a/target/arm/cpu.c |
34 | +++ b/target/arm/cpu.c | 43 | +++ b/target/arm/cpu.c |
35 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 44 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
36 | * feature registers as well. | 45 | cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); |
37 | */ | ||
38 | cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | ||
39 | + cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); | ||
40 | cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | 46 | cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, |
41 | ID_AA64PFR0, EL3, 0); | 47 | ID_AA64PFR0, EL3, 0); |
48 | + | ||
49 | + /* Disable the realm management extension, which requires EL3. */ | ||
50 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
51 | + ID_AA64PFR0, RME, 0); | ||
42 | } | 52 | } |
43 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 53 | |
44 | index XXXXXXX..XXXXXXX 100644 | 54 | if (!cpu->has_el2) { |
45 | --- a/target/arm/cpu64.c | ||
46 | +++ b/target/arm/cpu64.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
48 | cpu->isar.id_aa64zfr0 = t; | ||
49 | |||
50 | t = cpu->isar.id_aa64dfr0; | ||
51 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ | ||
52 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | ||
53 | cpu->isar.id_aa64dfr0 = t; | ||
54 | |||
55 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/arm/cpu_tcg.c | ||
58 | +++ b/target/arm/cpu_tcg.c | ||
59 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
60 | cpu->isar.id_pfr2 = t; | ||
61 | |||
62 | t = cpu->isar.id_dfr0; | ||
63 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | ||
64 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | ||
65 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
66 | cpu->isar.id_dfr0 = t; | ||
67 | } | ||
68 | -- | 55 | -- |
69 | 2.25.1 | 56 | 2.34.1 |
57 | |||
58 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | There is no branch prediction in TCG, therefore there is no | 3 | Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF |
4 | need to actually include the context number into the predictor. | 4 | to be set, and invalidate TLBs when NSE changes. |
5 | Therefore all we need to do is add the state for SCXTNUM_ELx. | ||
6 | 5 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-21-richard.henderson@linaro.org | 8 | Message-id: 20230620124418.805717-3-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | docs/system/arm/emulation.rst | 3 ++ | 11 | target/arm/cpu.h | 5 +++-- |
13 | target/arm/cpu.h | 16 +++++++++ | 12 | target/arm/helper.c | 10 ++++++++-- |
14 | target/arm/cpu.c | 5 +++ | 13 | 2 files changed, 11 insertions(+), 4 deletions(-) |
15 | target/arm/cpu64.c | 3 +- | ||
16 | target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- | ||
17 | 5 files changed, 86 insertions(+), 2 deletions(-) | ||
18 | 14 | ||
19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/docs/system/arm/emulation.rst | ||
22 | +++ b/docs/system/arm/emulation.rst | ||
23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
24 | - FEAT_BF16 (AArch64 BFloat16 instructions) | ||
25 | - FEAT_BTI (Branch Target Identification) | ||
26 | - FEAT_CSV2 (Cache speculation variant 2) | ||
27 | +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | ||
28 | +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | ||
29 | +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) | ||
30 | - FEAT_DIT (Data Independent Timing instructions) | ||
31 | - FEAT_DPB (DC CVAP instruction) | ||
32 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
33 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
34 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/cpu.h |
36 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/cpu.h |
37 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 19 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
38 | ARMPACKey apdb; | 20 | #define HCR_TERR (1ULL << 36) |
39 | ARMPACKey apga; | 21 | #define HCR_TEA (1ULL << 37) |
40 | } keys; | 22 | #define HCR_MIOCNCE (1ULL << 38) |
41 | + | 23 | -/* RES0 bit 39 */ |
42 | + uint64_t scxtnum_el[4]; | 24 | +#define HCR_TME (1ULL << 39) |
43 | #endif | 25 | #define HCR_APK (1ULL << 40) |
44 | 26 | #define HCR_API (1ULL << 41) | |
45 | #if defined(CONFIG_USER_ONLY) | 27 | #define HCR_NV (1ULL << 42) |
46 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | 28 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
47 | #define SCTLR_WXN (1U << 19) | 29 | #define HCR_NV2 (1ULL << 45) |
48 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | 30 | #define HCR_FWB (1ULL << 46) |
49 | #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ | 31 | #define HCR_FIEN (1ULL << 47) |
50 | +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ | 32 | -/* RES0 bit 48 */ |
51 | #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ | 33 | +#define HCR_GPF (1ULL << 48) |
52 | #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ | 34 | #define HCR_TID4 (1ULL << 49) |
53 | #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ | 35 | #define HCR_TICAB (1ULL << 50) |
54 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) | 36 | #define HCR_AMVOFFEN (1ULL << 51) |
55 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; | 37 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
56 | } | 38 | #define SCR_TRNDR (1ULL << 40) |
57 | 39 | #define SCR_ENTP2 (1ULL << 41) | |
58 | +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) | 40 | #define SCR_GPF (1ULL << 48) |
59 | +{ | 41 | +#define SCR_NSE (1ULL << 62) |
60 | + int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); | 42 | |
61 | + if (key >= 2) { | 43 | #define HSTR_TTEE (1 << 16) |
62 | + return true; /* FEAT_CSV2_2 */ | 44 | #define HSTR_TJDBX (1 << 17) |
63 | + } | ||
64 | + if (key == 1) { | ||
65 | + key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); | ||
66 | + return key >= 2; /* FEAT_CSV2_1p2 */ | ||
67 | + } | ||
68 | + return false; | ||
69 | +} | ||
70 | + | ||
71 | static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) | ||
72 | { | ||
73 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; | ||
74 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/target/arm/cpu.c | ||
77 | +++ b/target/arm/cpu.c | ||
78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | ||
79 | */ | ||
80 | env->cp15.gcr_el1 = 0x1ffff; | ||
81 | } | ||
82 | + /* | ||
83 | + * Disable access to SCXTNUM_EL0 from CSV2_1p2. | ||
84 | + * This is not yet exposed from the Linux kernel in any way. | ||
85 | + */ | ||
86 | + env->cp15.sctlr_el[1] |= SCTLR_TSCXT; | ||
87 | #else | ||
88 | /* Reset into the highest available EL */ | ||
89 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
90 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/target/arm/cpu64.c | ||
93 | +++ b/target/arm/cpu64.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
95 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
96 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
97 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
98 | - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ | ||
99 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | ||
100 | cpu->isar.id_aa64pfr0 = t; | ||
101 | |||
102 | t = cpu->isar.id_aa64pfr1; | ||
103 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
104 | * we do for EL2 with the virtualization=on property. | ||
105 | */ | ||
106 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
107 | + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ | ||
108 | cpu->isar.id_aa64pfr1 = t; | ||
109 | |||
110 | t = cpu->isar.id_aa64mmfr0; | ||
111 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 45 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
112 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
113 | --- a/target/arm/helper.c | 47 | --- a/target/arm/helper.c |
114 | +++ b/target/arm/helper.c | 48 | +++ b/target/arm/helper.c |
115 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 49 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
116 | if (cpu_isar_feature(aa64_mte, cpu)) { | 50 | if (cpu_isar_feature(aa64_fgt, cpu)) { |
117 | valid_mask |= SCR_ATA; | 51 | valid_mask |= SCR_FGTEN; |
118 | } | 52 | } |
119 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | 53 | + if (cpu_isar_feature(aa64_rme, cpu)) { |
120 | + valid_mask |= SCR_ENSCXT; | 54 | + valid_mask |= SCR_NSE | SCR_GPF; |
121 | + } | 55 | + } |
122 | } else { | 56 | } else { |
123 | valid_mask &= ~(SCR_RW | SCR_ST); | 57 | valid_mask &= ~(SCR_RW | SCR_ST); |
124 | if (cpu_isar_feature(aa32_ras, cpu)) { | 58 | if (cpu_isar_feature(aa32_ras, cpu)) { |
59 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
60 | env->cp15.scr_el3 = value; | ||
61 | |||
62 | /* | ||
63 | - * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then | ||
64 | + * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, | ||
65 | * we must invalidate all TLBs below EL3. | ||
66 | */ | ||
67 | - if (changed & SCR_NS) { | ||
68 | + if (changed & (SCR_NS | SCR_NSE)) { | ||
69 | tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | | ||
70 | ARMMMUIdxBit_E20_0 | | ||
71 | ARMMMUIdxBit_E10_1 | | ||
125 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | 72 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
126 | if (cpu_isar_feature(aa64_mte, cpu)) { | 73 | if (cpu_isar_feature(aa64_fwb, cpu)) { |
127 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | 74 | valid_mask |= HCR_FWB; |
128 | } | 75 | } |
129 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | 76 | + if (cpu_isar_feature(aa64_rme, cpu)) { |
130 | + valid_mask |= HCR_ENSCXT; | 77 | + valid_mask |= HCR_GPF; |
131 | + } | 78 | + } |
132 | } | 79 | } |
133 | 80 | ||
134 | /* Clear RES0 bits. */ | 81 | if (cpu_isar_feature(any_evt, cpu)) { |
135 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
136 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), | ||
137 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | ||
138 | |||
139 | + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), | ||
140 | + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", | ||
141 | + isar_feature_aa64_scxtnum }, | ||
142 | + | ||
143 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ | ||
144 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | ||
145 | }; | ||
146 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
147 | }, | ||
148 | }; | ||
149 | |||
150 | -#endif | ||
151 | +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, | ||
152 | + bool isread) | ||
153 | +{ | ||
154 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
155 | + int el = arm_current_el(env); | ||
156 | + | ||
157 | + if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { | ||
158 | + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { | ||
159 | + if (hcr & HCR_TGE) { | ||
160 | + return CP_ACCESS_TRAP_EL2; | ||
161 | + } | ||
162 | + return CP_ACCESS_TRAP; | ||
163 | + } | ||
164 | + } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | ||
165 | + return CP_ACCESS_TRAP_EL2; | ||
166 | + } | ||
167 | + if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | ||
168 | + return CP_ACCESS_TRAP_EL2; | ||
169 | + } | ||
170 | + if (el < 3 | ||
171 | + && arm_feature(env, ARM_FEATURE_EL3) | ||
172 | + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | ||
173 | + return CP_ACCESS_TRAP_EL3; | ||
174 | + } | ||
175 | + return CP_ACCESS_OK; | ||
176 | +} | ||
177 | + | ||
178 | +static const ARMCPRegInfo scxtnum_reginfo[] = { | ||
179 | + { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | ||
180 | + .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | ||
181 | + .access = PL0_RW, .accessfn = access_scxtnum, | ||
182 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, | ||
183 | + { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | ||
184 | + .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | ||
185 | + .access = PL1_RW, .accessfn = access_scxtnum, | ||
186 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, | ||
187 | + { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | ||
188 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | ||
189 | + .access = PL2_RW, .accessfn = access_scxtnum, | ||
190 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | ||
191 | + { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | ||
192 | + .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | ||
193 | + .access = PL3_RW, | ||
194 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | ||
195 | +}; | ||
196 | +#endif /* TARGET_AARCH64 */ | ||
197 | |||
198 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
199 | bool isread) | ||
200 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
201 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | ||
202 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
203 | } | ||
204 | + | ||
205 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
206 | + define_arm_cp_regs(cpu, scxtnum_reginfo); | ||
207 | + } | ||
208 | #endif | ||
209 | |||
210 | if (cpu_isar_feature(any_predinv, cpu)) { | ||
211 | -- | 82 | -- |
212 | 2.25.1 | 83 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable writes to the TERR and TEA bits when RAS is enabled. | 3 | With RME, SEL2 must also be present to support secure state. |
4 | These bits are otherwise RES0. | 4 | The NS bit is RES1 if SEL2 is not present. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-15-richard.henderson@linaro.org | 8 | Message-id: 20230620124418.805717-4-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/helper.c | 9 +++++++++ | 11 | target/arm/helper.c | 3 +++ |
12 | 1 file changed, 9 insertions(+) | 12 | 1 file changed, 3 insertions(+) |
13 | 13 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 16 | --- a/target/arm/helper.c |
17 | +++ b/target/arm/helper.c | 17 | +++ b/target/arm/helper.c |
18 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 18 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
19 | } | 19 | } |
20 | valid_mask &= ~SCR_NET; | 20 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
21 | 21 | valid_mask |= SCR_EEL2; | |
22 | + if (cpu_isar_feature(aa64_ras, cpu)) { | 22 | + } else if (cpu_isar_feature(aa64_rme, cpu)) { |
23 | + valid_mask |= SCR_TERR; | 23 | + /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */ |
24 | + } | 24 | + value |= SCR_NS; |
25 | if (cpu_isar_feature(aa64_lor, cpu)) { | ||
26 | valid_mask |= SCR_TLOR; | ||
27 | } | 25 | } |
28 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 26 | if (cpu_isar_feature(aa64_mte, cpu)) { |
29 | } | 27 | valid_mask |= SCR_ATA; |
30 | } else { | ||
31 | valid_mask &= ~(SCR_RW | SCR_ST); | ||
32 | + if (cpu_isar_feature(aa32_ras, cpu)) { | ||
33 | + valid_mask |= SCR_TERR; | ||
34 | + } | ||
35 | } | ||
36 | |||
37 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | ||
38 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
39 | if (cpu_isar_feature(aa64_vh, cpu)) { | ||
40 | valid_mask |= HCR_E2H; | ||
41 | } | ||
42 | + if (cpu_isar_feature(aa64_ras, cpu)) { | ||
43 | + valid_mask |= HCR_TERR | HCR_TEA; | ||
44 | + } | ||
45 | if (cpu_isar_feature(aa64_lor, cpu)) { | ||
46 | valid_mask |= HCR_TLOR; | ||
47 | } | ||
48 | -- | 28 | -- |
49 | 2.25.1 | 29 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add only the system registers required to implement zero error | 3 | This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS, |
4 | records. This means that all values for ERRSELR are out of range, | 4 | RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA. |
5 | which means that it and all of the indexed error record registers | ||
6 | need not be implemented. | ||
7 | |||
8 | Add the EL2 registers required for injecting virtual SError. | ||
9 | 5 | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Message-id: 20220506180242.216785-14-richard.henderson@linaro.org | 8 | Message-id: 20230620124418.805717-5-richard.henderson@linaro.org |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 10 | --- |
15 | target/arm/cpu.h | 5 +++ | 11 | target/arm/cpu.h | 19 ++++++++++ |
16 | target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ | 12 | target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ |
17 | 2 files changed, 89 insertions(+) | 13 | 2 files changed, 103 insertions(+) |
18 | 14 | ||
19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
20 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/cpu.h |
22 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/cpu.h |
23 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
24 | uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ | 20 | uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ |
25 | uint64_t gcr_el1; | 21 | uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ |
26 | uint64_t rgsr_el1; | 22 | uint64_t fgt_exec[1]; /* HFGITR */ |
27 | + | 23 | + |
28 | + /* Minimal RAS registers */ | 24 | + /* RME registers */ |
29 | + uint64_t disr_el1; | 25 | + uint64_t gpccr_el3; |
30 | + uint64_t vdisr_el2; | 26 | + uint64_t gptbr_el3; |
31 | + uint64_t vsesr_el2; | 27 | + uint64_t mfar_el3; |
32 | } cp15; | 28 | } cp15; |
33 | 29 | ||
34 | struct { | 30 | struct { |
31 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
32 | uint64_t reset_cbar; | ||
33 | uint32_t reset_auxcr; | ||
34 | bool reset_hivecs; | ||
35 | + uint8_t reset_l0gptsz; | ||
36 | |||
37 | /* | ||
38 | * Intermediate values used during property parsing. | ||
39 | @@ -XXX,XX +XXX,XX @@ FIELD(MVFR1, SIMDFMAC, 28, 4) | ||
40 | FIELD(MVFR2, SIMDMISC, 0, 4) | ||
41 | FIELD(MVFR2, FPMISC, 4, 4) | ||
42 | |||
43 | +FIELD(GPCCR, PPS, 0, 3) | ||
44 | +FIELD(GPCCR, IRGN, 8, 2) | ||
45 | +FIELD(GPCCR, ORGN, 10, 2) | ||
46 | +FIELD(GPCCR, SH, 12, 2) | ||
47 | +FIELD(GPCCR, PGS, 14, 2) | ||
48 | +FIELD(GPCCR, GPC, 16, 1) | ||
49 | +FIELD(GPCCR, GPCP, 17, 1) | ||
50 | +FIELD(GPCCR, L0GPTSZ, 20, 4) | ||
51 | + | ||
52 | +FIELD(MFAR, FPA, 12, 40) | ||
53 | +FIELD(MFAR, NSE, 62, 1) | ||
54 | +FIELD(MFAR, NS, 63, 1) | ||
55 | + | ||
56 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); | ||
57 | |||
58 | /* If adding a feature bit which corresponds to a Linux ELF | ||
35 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 59 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
36 | index XXXXXXX..XXXXXXX 100644 | 60 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/target/arm/helper.c | 61 | --- a/target/arm/helper.c |
38 | +++ b/target/arm/helper.c | 62 | +++ b/target/arm/helper.c |
39 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | 63 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = { |
40 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | 64 | .access = PL2_RW, .accessfn = access_esm, |
65 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
41 | }; | 66 | }; |
42 | 67 | + | |
43 | +/* | 68 | +static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
44 | + * Check for traps to RAS registers, which are controlled | 69 | + uint64_t value) |
45 | + * by HCR_EL2.TERR and SCR_EL3.TERR. | ||
46 | + */ | ||
47 | +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, | ||
48 | + bool isread) | ||
49 | +{ | 70 | +{ |
50 | + int el = arm_current_el(env); | 71 | + CPUState *cs = env_cpu(env); |
51 | + | 72 | + |
52 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { | 73 | + tlb_flush(cs); |
53 | + return CP_ACCESS_TRAP_EL2; | ||
54 | + } | ||
55 | + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { | ||
56 | + return CP_ACCESS_TRAP_EL3; | ||
57 | + } | ||
58 | + return CP_ACCESS_OK; | ||
59 | +} | 74 | +} |
60 | + | 75 | + |
61 | +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 76 | +static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
77 | + uint64_t value) | ||
62 | +{ | 78 | +{ |
63 | + int el = arm_current_el(env); | 79 | + /* L0GPTSZ is RO; other bits not mentioned are RES0. */ |
80 | + uint64_t rw_mask = R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | | ||
81 | + R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | | ||
82 | + R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; | ||
64 | + | 83 | + |
65 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | 84 | + env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); |
66 | + return env->cp15.vdisr_el2; | ||
67 | + } | ||
68 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | ||
69 | + return 0; /* RAZ/WI */ | ||
70 | + } | ||
71 | + return env->cp15.disr_el1; | ||
72 | +} | 85 | +} |
73 | + | 86 | + |
74 | +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | 87 | +static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
75 | +{ | 88 | +{ |
76 | + int el = arm_current_el(env); | 89 | + env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, |
77 | + | 90 | + env_archcpu(env)->reset_l0gptsz); |
78 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | ||
79 | + env->cp15.vdisr_el2 = val; | ||
80 | + return; | ||
81 | + } | ||
82 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | ||
83 | + return; /* RAZ/WI */ | ||
84 | + } | ||
85 | + env->cp15.disr_el1 = val; | ||
86 | +} | 91 | +} |
87 | + | 92 | + |
88 | +/* | 93 | +static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri, |
89 | + * Minimal RAS implementation with no Error Records. | 94 | + uint64_t value) |
90 | + * Which means that all of the Error Record registers: | 95 | +{ |
91 | + * ERXADDR_EL1 | 96 | + CPUState *cs = env_cpu(env); |
92 | + * ERXCTLR_EL1 | 97 | + |
93 | + * ERXFR_EL1 | 98 | + tlb_flush_all_cpus_synced(cs); |
94 | + * ERXMISC0_EL1 | 99 | +} |
95 | + * ERXMISC1_EL1 | 100 | + |
96 | + * ERXMISC2_EL1 | 101 | +static const ARMCPRegInfo rme_reginfo[] = { |
97 | + * ERXMISC3_EL1 | 102 | + { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64, |
98 | + * ERXPFGCDN_EL1 (RASv1p1) | 103 | + .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6, |
99 | + * ERXPFGCTL_EL1 (RASv1p1) | 104 | + .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset, |
100 | + * ERXPFGF_EL1 (RASv1p1) | 105 | + .fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) }, |
101 | + * ERXSTATUS_EL1 | 106 | + { .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64, |
102 | + * and | 107 | + .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4, |
103 | + * ERRSELR_EL1 | 108 | + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) }, |
104 | + * may generate UNDEFINED, which is the effect we get by not | 109 | + { .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64, |
105 | + * listing them at all. | 110 | + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5, |
106 | + */ | 111 | + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) }, |
107 | +static const ARMCPRegInfo minimal_ras_reginfo[] = { | 112 | + { .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64, |
108 | + { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | 113 | + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4, |
109 | + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | 114 | + .access = PL3_W, .type = ARM_CP_NO_RAW, |
110 | + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | 115 | + .writefn = tlbi_aa64_paall_write }, |
111 | + .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | 116 | + { .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64, |
112 | + { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | 117 | + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4, |
113 | + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | 118 | + .access = PL3_W, .type = ARM_CP_NO_RAW, |
114 | + .access = PL1_R, .accessfn = access_terr, | 119 | + .writefn = tlbi_aa64_paallos_write }, |
115 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | 120 | + /* |
116 | + { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | 121 | + * QEMU does not have a way to invalidate by physical address, thus |
117 | + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | 122 | + * invalidating a range of physical addresses is accomplished by |
118 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | 123 | + * flushing all tlb entries in the outer sharable domain, |
119 | + { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | 124 | + * just like PAALLOS. |
120 | + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | 125 | + */ |
121 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | 126 | + { .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64, |
127 | + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7, | ||
128 | + .access = PL3_W, .type = ARM_CP_NO_RAW, | ||
129 | + .writefn = tlbi_aa64_paallos_write }, | ||
130 | + { .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64, | ||
131 | + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3, | ||
132 | + .access = PL3_W, .type = ARM_CP_NO_RAW, | ||
133 | + .writefn = tlbi_aa64_paallos_write }, | ||
134 | + { .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64, | ||
135 | + .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1, | ||
136 | + .access = PL3_W, .type = ARM_CP_NOP }, | ||
122 | +}; | 137 | +}; |
123 | + | 138 | + |
124 | /* Return the exception level to which exceptions should be taken | 139 | +static const ARMCPRegInfo rme_mte_reginfo[] = { |
125 | * via SVEAccessTrap. If an exception should be routed through | 140 | + { .name = "DC_CIGDPAPA", .state = ARM_CP_STATE_AA64, |
126 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | 141 | + .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5, |
142 | + .access = PL3_W, .type = ARM_CP_NOP }, | ||
143 | +}; | ||
144 | #endif /* TARGET_AARCH64 */ | ||
145 | |||
146 | static void define_pmu_regs(ARMCPU *cpu) | ||
127 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 147 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
128 | if (cpu_isar_feature(aa64_ssbs, cpu)) { | 148 | if (cpu_isar_feature(aa64_fgt, cpu)) { |
129 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | 149 | define_arm_cp_regs(cpu, fgt_reginfo); |
130 | } | 150 | } |
131 | + if (cpu_isar_feature(any_ras, cpu)) { | 151 | + |
132 | + define_arm_cp_regs(cpu, minimal_ras_reginfo); | 152 | + if (cpu_isar_feature(aa64_rme, cpu)) { |
153 | + define_arm_cp_regs(cpu, rme_reginfo); | ||
154 | + if (cpu_isar_feature(aa64_mte, cpu)) { | ||
155 | + define_arm_cp_regs(cpu, rme_mte_reginfo); | ||
156 | + } | ||
133 | + } | 157 | + } |
134 | 158 | #endif | |
135 | if (cpu_isar_feature(aa64_vh, cpu) || | 159 | |
136 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | 160 | if (cpu_isar_feature(any_predinv, cpu)) { |
137 | -- | 161 | -- |
138 | 2.25.1 | 162 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This register is present for either VHE or Debugv8p2. | 3 | Introduce both the enumeration and functions to retrieve |
4 | the current state, and state outside of EL3. | ||
4 | 5 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-5-richard.henderson@linaro.org | 8 | Message-id: 20230620124418.805717-6-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/helper.c | 15 +++++++++++---- | 11 | target/arm/cpu.h | 89 ++++++++++++++++++++++++++++++++++----------- |
11 | 1 file changed, 11 insertions(+), 4 deletions(-) | 12 | target/arm/helper.c | 60 ++++++++++++++++++++++++++++++ |
13 | 2 files changed, 127 insertions(+), 22 deletions(-) | ||
12 | 14 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/cpu.h | ||
18 | +++ b/target/arm/cpu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature) | ||
20 | |||
21 | void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); | ||
22 | |||
23 | -#if !defined(CONFIG_USER_ONLY) | ||
24 | /* | ||
25 | + * ARM v9 security states. | ||
26 | + * The ordering of the enumeration corresponds to the low 2 bits | ||
27 | + * of the GPI value, and (except for Root) the concat of NSE:NS. | ||
28 | + */ | ||
29 | + | ||
30 | +typedef enum ARMSecuritySpace { | ||
31 | + ARMSS_Secure = 0, | ||
32 | + ARMSS_NonSecure = 1, | ||
33 | + ARMSS_Root = 2, | ||
34 | + ARMSS_Realm = 3, | ||
35 | +} ARMSecuritySpace; | ||
36 | + | ||
37 | +/* Return true if @space is secure, in the pre-v9 sense. */ | ||
38 | +static inline bool arm_space_is_secure(ARMSecuritySpace space) | ||
39 | +{ | ||
40 | + return space == ARMSS_Secure || space == ARMSS_Root; | ||
41 | +} | ||
42 | + | ||
43 | +/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ | ||
44 | +static inline ARMSecuritySpace arm_secure_to_space(bool secure) | ||
45 | +{ | ||
46 | + return secure ? ARMSS_Secure : ARMSS_NonSecure; | ||
47 | +} | ||
48 | + | ||
49 | +#if !defined(CONFIG_USER_ONLY) | ||
50 | +/** | ||
51 | + * arm_security_space_below_el3: | ||
52 | + * @env: cpu context | ||
53 | + * | ||
54 | + * Return the security space of exception levels below EL3, following | ||
55 | + * an exception return to those levels. Unlike arm_security_space, | ||
56 | + * this doesn't care about the current EL. | ||
57 | + */ | ||
58 | +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); | ||
59 | + | ||
60 | +/** | ||
61 | + * arm_is_secure_below_el3: | ||
62 | + * @env: cpu context | ||
63 | + * | ||
64 | * Return true if exception levels below EL3 are in secure state, | ||
65 | - * or would be following an exception return to that level. | ||
66 | - * Unlike arm_is_secure() (which is always a question about the | ||
67 | - * _current_ state of the CPU) this doesn't care about the current | ||
68 | - * EL or mode. | ||
69 | + * or would be following an exception return to those levels. | ||
70 | */ | ||
71 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | ||
72 | { | ||
73 | - assert(!arm_feature(env, ARM_FEATURE_M)); | ||
74 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
75 | - return !(env->cp15.scr_el3 & SCR_NS); | ||
76 | - } else { | ||
77 | - /* If EL3 is not supported then the secure state is implementation | ||
78 | - * defined, in which case QEMU defaults to non-secure. | ||
79 | - */ | ||
80 | - return false; | ||
81 | - } | ||
82 | + ARMSecuritySpace ss = arm_security_space_below_el3(env); | ||
83 | + return ss == ARMSS_Secure; | ||
84 | } | ||
85 | |||
86 | /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ | ||
87 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) | ||
88 | return false; | ||
89 | } | ||
90 | |||
91 | -/* Return true if the processor is in secure state */ | ||
92 | +/** | ||
93 | + * arm_security_space: | ||
94 | + * @env: cpu context | ||
95 | + * | ||
96 | + * Return the current security space of the cpu. | ||
97 | + */ | ||
98 | +ARMSecuritySpace arm_security_space(CPUARMState *env); | ||
99 | + | ||
100 | +/** | ||
101 | + * arm_is_secure: | ||
102 | + * @env: cpu context | ||
103 | + * | ||
104 | + * Return true if the processor is in secure state. | ||
105 | + */ | ||
106 | static inline bool arm_is_secure(CPUARMState *env) | ||
107 | { | ||
108 | - if (arm_feature(env, ARM_FEATURE_M)) { | ||
109 | - return env->v7m.secure; | ||
110 | - } | ||
111 | - if (arm_is_el3_or_mon(env)) { | ||
112 | - return true; | ||
113 | - } | ||
114 | - return arm_is_secure_below_el3(env); | ||
115 | + return arm_space_is_secure(arm_security_space(env)); | ||
116 | } | ||
117 | |||
118 | /* | ||
119 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el2_enabled(CPUARMState *env) | ||
120 | } | ||
121 | |||
122 | #else | ||
123 | +static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) | ||
124 | +{ | ||
125 | + return ARMSS_NonSecure; | ||
126 | +} | ||
127 | + | ||
128 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | ||
129 | { | ||
130 | return false; | ||
131 | } | ||
132 | |||
133 | +static inline ARMSecuritySpace arm_security_space(CPUARMState *env) | ||
134 | +{ | ||
135 | + return ARMSS_NonSecure; | ||
136 | +} | ||
137 | + | ||
138 | static inline bool arm_is_secure(CPUARMState *env) | ||
139 | { | ||
140 | return false; | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 141 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
14 | index XXXXXXX..XXXXXXX 100644 | 142 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 143 | --- a/target/arm/helper.c |
16 | +++ b/target/arm/helper.c | 144 | +++ b/target/arm/helper.c |
17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = { | 145 | @@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, |
18 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
19 | }; | ||
20 | |||
21 | +static const ARMCPRegInfo contextidr_el2 = { | ||
22 | + .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
23 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | ||
24 | + .access = PL2_RW, | ||
25 | + .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) | ||
26 | +}; | ||
27 | + | ||
28 | static const ARMCPRegInfo vhe_reginfo[] = { | ||
29 | - { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
30 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | ||
31 | - .access = PL2_RW, | ||
32 | - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, | ||
33 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, | ||
34 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | ||
35 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | ||
36 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
37 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | ||
38 | } | 146 | } |
39 | 147 | } | |
40 | + if (cpu_isar_feature(aa64_vh, cpu) || | 148 | #endif |
41 | + cpu_isar_feature(aa64_debugv8p2, cpu)) { | 149 | + |
42 | + define_one_arm_cp_reg(cpu, &contextidr_el2); | 150 | +#ifndef CONFIG_USER_ONLY |
43 | + } | 151 | +ARMSecuritySpace arm_security_space(CPUARMState *env) |
44 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | 152 | +{ |
45 | define_arm_cp_regs(cpu, vhe_reginfo); | 153 | + if (arm_feature(env, ARM_FEATURE_M)) { |
46 | } | 154 | + return arm_secure_to_space(env->v7m.secure); |
155 | + } | ||
156 | + | ||
157 | + /* | ||
158 | + * If EL3 is not supported then the secure state is implementation | ||
159 | + * defined, in which case QEMU defaults to non-secure. | ||
160 | + */ | ||
161 | + if (!arm_feature(env, ARM_FEATURE_EL3)) { | ||
162 | + return ARMSS_NonSecure; | ||
163 | + } | ||
164 | + | ||
165 | + /* Check for AArch64 EL3 or AArch32 Mon. */ | ||
166 | + if (is_a64(env)) { | ||
167 | + if (extract32(env->pstate, 2, 2) == 3) { | ||
168 | + if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { | ||
169 | + return ARMSS_Root; | ||
170 | + } else { | ||
171 | + return ARMSS_Secure; | ||
172 | + } | ||
173 | + } | ||
174 | + } else { | ||
175 | + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | ||
176 | + return ARMSS_Secure; | ||
177 | + } | ||
178 | + } | ||
179 | + | ||
180 | + return arm_security_space_below_el3(env); | ||
181 | +} | ||
182 | + | ||
183 | +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) | ||
184 | +{ | ||
185 | + assert(!arm_feature(env, ARM_FEATURE_M)); | ||
186 | + | ||
187 | + /* | ||
188 | + * If EL3 is not supported then the secure state is implementation | ||
189 | + * defined, in which case QEMU defaults to non-secure. | ||
190 | + */ | ||
191 | + if (!arm_feature(env, ARM_FEATURE_EL3)) { | ||
192 | + return ARMSS_NonSecure; | ||
193 | + } | ||
194 | + | ||
195 | + /* | ||
196 | + * Note NSE cannot be set without RME, and NSE & !NS is Reserved. | ||
197 | + * Ignoring NSE when !NS retains consistency without having to | ||
198 | + * modify other predicates. | ||
199 | + */ | ||
200 | + if (!(env->cp15.scr_el3 & SCR_NS)) { | ||
201 | + return ARMSS_Secure; | ||
202 | + } else if (env->cp15.scr_el3 & SCR_NSE) { | ||
203 | + return ARMSS_Realm; | ||
204 | + } else { | ||
205 | + return ARMSS_NonSecure; | ||
206 | + } | ||
207 | +} | ||
208 | +#endif /* !CONFIG_USER_ONLY */ | ||
47 | -- | 209 | -- |
48 | 2.25.1 | 210 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Share the code to set AArch32 max features so that we no | 3 | We will need 2 bits to represent ARMSecurityState. |
4 | longer have code drift between qemu{-system,}-{arm,aarch64}. | 4 | |
5 | Do not attempt to replace or widen secure, even though it | ||
6 | logically overlaps the new field -- there are uses within | ||
7 | e.g. hw/block/pflash_cfi01.c, which don't know anything | ||
8 | specific about ARM. | ||
5 | 9 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-9-richard.henderson@linaro.org | 12 | Message-id: 20230620124418.805717-7-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | target/arm/internals.h | 2 + | 15 | include/exec/memattrs.h | 9 ++++++++- |
12 | target/arm/cpu64.c | 50 +----------------- | 16 | 1 file changed, 8 insertions(+), 1 deletion(-) |
13 | target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- | ||
14 | 3 files changed, 65 insertions(+), 101 deletions(-) | ||
15 | 17 | ||
16 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 18 | diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h |
17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/internals.h | 20 | --- a/include/exec/memattrs.h |
19 | +++ b/target/arm/internals.h | 21 | +++ b/include/exec/memattrs.h |
20 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct MemTxAttrs { |
21 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | 23 | * "didn't specify" if necessary. |
22 | #endif | 24 | */ |
23 | 25 | unsigned int unspecified:1; | |
24 | +void aa32_max_features(ARMCPU *cpu); | 26 | - /* ARM/AMBA: TrustZone Secure access |
25 | + | 27 | + /* |
26 | #endif | 28 | + * ARM/AMBA: TrustZone Secure access |
27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 29 | * x86: System Management Mode access |
28 | index XXXXXXX..XXXXXXX 100644 | 30 | */ |
29 | --- a/target/arm/cpu64.c | 31 | unsigned int secure:1; |
30 | +++ b/target/arm/cpu64.c | 32 | + /* |
31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 33 | + * ARM: ArmSecuritySpace. This partially overlaps secure, but it is |
32 | { | 34 | + * easier to have both fields to assist code that does not understand |
33 | ARMCPU *cpu = ARM_CPU(obj); | 35 | + * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash). |
34 | uint64_t t; | 36 | + */ |
35 | - uint32_t u; | 37 | + unsigned int space:2; |
36 | 38 | /* Memory access is usermode (unprivileged) */ | |
37 | if (kvm_enabled() || hvf_enabled()) { | 39 | unsigned int user:1; |
38 | /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ | ||
39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
40 | t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
41 | cpu->isar.id_aa64zfr0 = t; | ||
42 | |||
43 | - /* Replicate the same data to the 32-bit id registers. */ | ||
44 | - u = cpu->isar.id_isar5; | ||
45 | - u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ | ||
46 | - u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); | ||
47 | - u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); | ||
48 | - u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); | ||
49 | - u = FIELD_DP32(u, ID_ISAR5, RDM, 1); | ||
50 | - u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); | ||
51 | - cpu->isar.id_isar5 = u; | ||
52 | - | ||
53 | - u = cpu->isar.id_isar6; | ||
54 | - u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); | ||
55 | - u = FIELD_DP32(u, ID_ISAR6, DP, 1); | ||
56 | - u = FIELD_DP32(u, ID_ISAR6, FHM, 1); | ||
57 | - u = FIELD_DP32(u, ID_ISAR6, SB, 1); | ||
58 | - u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); | ||
59 | - u = FIELD_DP32(u, ID_ISAR6, BF16, 1); | ||
60 | - u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); | ||
61 | - cpu->isar.id_isar6 = u; | ||
62 | - | ||
63 | - u = cpu->isar.id_pfr0; | ||
64 | - u = FIELD_DP32(u, ID_PFR0, DIT, 1); | ||
65 | - cpu->isar.id_pfr0 = u; | ||
66 | - | ||
67 | - u = cpu->isar.id_pfr2; | ||
68 | - u = FIELD_DP32(u, ID_PFR2, SSBS, 1); | ||
69 | - cpu->isar.id_pfr2 = u; | ||
70 | - | ||
71 | - u = cpu->isar.id_mmfr3; | ||
72 | - u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
73 | - cpu->isar.id_mmfr3 = u; | ||
74 | - | ||
75 | - u = cpu->isar.id_mmfr4; | ||
76 | - u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
77 | - u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
78 | - u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
79 | - u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
80 | - cpu->isar.id_mmfr4 = u; | ||
81 | - | ||
82 | t = cpu->isar.id_aa64dfr0; | ||
83 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
84 | cpu->isar.id_aa64dfr0 = t; | ||
85 | |||
86 | - u = cpu->isar.id_dfr0; | ||
87 | - u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
88 | - cpu->isar.id_dfr0 = u; | ||
89 | - | ||
90 | - u = cpu->isar.mvfr1; | ||
91 | - u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
92 | - u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
93 | - cpu->isar.mvfr1 = u; | ||
94 | + /* Replicate the same data to the 32-bit id registers. */ | ||
95 | + aa32_max_features(cpu); | ||
96 | |||
97 | #ifdef CONFIG_USER_ONLY | ||
98 | /* | ||
99 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/target/arm/cpu_tcg.c | ||
102 | +++ b/target/arm/cpu_tcg.c | ||
103 | @@ -XXX,XX +XXX,XX @@ | ||
104 | #endif | ||
105 | #include "cpregs.h" | ||
106 | |||
107 | + | ||
108 | +/* Share AArch32 -cpu max features with AArch64. */ | ||
109 | +void aa32_max_features(ARMCPU *cpu) | ||
110 | +{ | ||
111 | + uint32_t t; | ||
112 | + | ||
113 | + /* Add additional features supported by QEMU */ | ||
114 | + t = cpu->isar.id_isar5; | ||
115 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
116 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
117 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
118 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
119 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
120 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
121 | + cpu->isar.id_isar5 = t; | ||
122 | + | ||
123 | + t = cpu->isar.id_isar6; | ||
124 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
125 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
126 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
127 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
128 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
129 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
130 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
131 | + cpu->isar.id_isar6 = t; | ||
132 | + | ||
133 | + t = cpu->isar.mvfr1; | ||
134 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
135 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
136 | + cpu->isar.mvfr1 = t; | ||
137 | + | ||
138 | + t = cpu->isar.mvfr2; | ||
139 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
140 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
141 | + cpu->isar.mvfr2 = t; | ||
142 | + | ||
143 | + t = cpu->isar.id_mmfr3; | ||
144 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
145 | + cpu->isar.id_mmfr3 = t; | ||
146 | + | ||
147 | + t = cpu->isar.id_mmfr4; | ||
148 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
149 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
150 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
151 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
152 | + cpu->isar.id_mmfr4 = t; | ||
153 | + | ||
154 | + t = cpu->isar.id_pfr0; | ||
155 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
156 | + cpu->isar.id_pfr0 = t; | ||
157 | + | ||
158 | + t = cpu->isar.id_pfr2; | ||
159 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
160 | + cpu->isar.id_pfr2 = t; | ||
161 | + | ||
162 | + t = cpu->isar.id_dfr0; | ||
163 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
164 | + cpu->isar.id_dfr0 = t; | ||
165 | +} | ||
166 | + | ||
167 | #ifndef CONFIG_USER_ONLY | ||
168 | static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
169 | { | ||
170 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
171 | static void arm_max_initfn(Object *obj) | ||
172 | { | ||
173 | ARMCPU *cpu = ARM_CPU(obj); | ||
174 | - uint32_t t; | ||
175 | |||
176 | /* aarch64_a57_initfn, advertising none of the aarch64 features */ | ||
177 | cpu->dtb_compatible = "arm,cortex-a57"; | ||
178 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
179 | cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
180 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
181 | |||
182 | - /* Add additional features supported by QEMU */ | ||
183 | - t = cpu->isar.id_isar5; | ||
184 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
185 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
186 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
187 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
188 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
189 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
190 | - cpu->isar.id_isar5 = t; | ||
191 | - | ||
192 | - t = cpu->isar.id_isar6; | ||
193 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
194 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
195 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
196 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
197 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
198 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
199 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
200 | - cpu->isar.id_isar6 = t; | ||
201 | - | ||
202 | - t = cpu->isar.mvfr1; | ||
203 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
204 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
205 | - cpu->isar.mvfr1 = t; | ||
206 | - | ||
207 | - t = cpu->isar.mvfr2; | ||
208 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
209 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
210 | - cpu->isar.mvfr2 = t; | ||
211 | - | ||
212 | - t = cpu->isar.id_mmfr3; | ||
213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
214 | - cpu->isar.id_mmfr3 = t; | ||
215 | - | ||
216 | - t = cpu->isar.id_mmfr4; | ||
217 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
218 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
219 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
220 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
221 | - cpu->isar.id_mmfr4 = t; | ||
222 | - | ||
223 | - t = cpu->isar.id_pfr0; | ||
224 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
225 | - cpu->isar.id_pfr0 = t; | ||
226 | - | ||
227 | - t = cpu->isar.id_pfr2; | ||
228 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
229 | - cpu->isar.id_pfr2 = t; | ||
230 | - | ||
231 | - t = cpu->isar.id_dfr0; | ||
232 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
233 | - cpu->isar.id_dfr0 = t; | ||
234 | + aa32_max_features(cpu); | ||
235 | |||
236 | #ifdef CONFIG_USER_ONLY | ||
237 | /* | 40 | /* |
238 | -- | 41 | -- |
239 | 2.25.1 | 42 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns not merging memory access, which TCG does | 3 | It will be helpful to have ARMMMUIdx_Phys_* to be in the same |
4 | not implement. Thus we can trivially enable this feature. | 4 | relative order as ARMSecuritySpace enumerators. This requires |
5 | Add a comment to handle_hint for the DGH instruction, but no code. | 5 | the adjustment to the nstable check. While there, check for being |
6 | in secure state rather than rely on clearing the low bit making | ||
7 | no change to non-secure state. | ||
6 | 8 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-23-richard.henderson@linaro.org | 11 | Message-id: 20230620124418.805717-8-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 13 | --- |
12 | docs/system/arm/emulation.rst | 1 + | 14 | target/arm/cpu.h | 12 ++++++------ |
13 | target/arm/cpu64.c | 1 + | 15 | target/arm/ptw.c | 12 +++++------- |
14 | target/arm/translate-a64.c | 1 + | 16 | 2 files changed, 11 insertions(+), 13 deletions(-) |
15 | 3 files changed, 3 insertions(+) | ||
16 | 17 | ||
17 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
18 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/docs/system/arm/emulation.rst | 20 | --- a/target/arm/cpu.h |
20 | +++ b/docs/system/arm/emulation.rst | 21 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 22 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx { |
22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | 23 | ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, |
23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | 24 | ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, |
24 | - FEAT_CSV3 (Cache speculation variant 3) | 25 | |
25 | +- FEAT_DGH (Data gathering hint) | 26 | - /* TLBs with 1-1 mapping to the physical address spaces. */ |
26 | - FEAT_DIT (Data Independent Timing instructions) | 27 | - ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, |
27 | - FEAT_DPB (DC CVAP instruction) | 28 | - ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, |
28 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 29 | - |
29 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 30 | /* |
31 | * Used for second stage of an S12 page table walk, or for descriptor | ||
32 | * loads during first stage of an S1 page table walk. Note that both | ||
33 | * are in use simultaneously for SecureEL2: the security state for | ||
34 | * the S2 ptw is selected by the NS bit from the S1 ptw. | ||
35 | */ | ||
36 | - ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, | ||
37 | - ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, | ||
38 | + ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, | ||
39 | + ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, | ||
40 | + | ||
41 | + /* TLBs with 1-1 mapping to the physical address spaces. */ | ||
42 | + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, | ||
43 | + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, | ||
44 | |||
45 | /* | ||
46 | * These are not allocated TLBs and are used only for AT system | ||
47 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/target/arm/cpu64.c | 49 | --- a/target/arm/ptw.c |
32 | +++ b/target/arm/cpu64.c | 50 | +++ b/target/arm/ptw.c |
33 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 51 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
34 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | 52 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
35 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | 53 | descaddr &= ~7ULL; |
36 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | 54 | nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); |
37 | + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ | 55 | - if (nstable) { |
38 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | 56 | + if (nstable && ptw->in_secure) { |
39 | cpu->isar.id_aa64isar1 = t; | 57 | /* |
40 | 58 | * Stage2_S -> Stage2 or Phys_S -> Phys_NS | |
41 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 59 | - * Assert that the non-secure idx are even, and relative order. |
42 | index XXXXXXX..XXXXXXX 100644 | 60 | + * Assert the relative order of the secure/non-secure indexes. |
43 | --- a/target/arm/translate-a64.c | 61 | */ |
44 | +++ b/target/arm/translate-a64.c | 62 | - QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) != 0); |
45 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, | 63 | - QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) != 0); |
46 | break; | 64 | - QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 != ARMMMUIdx_Phys_S); |
47 | case 0b00100: /* SEV */ | 65 | - QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 != ARMMMUIdx_Stage2_S); |
48 | case 0b00101: /* SEVL */ | 66 | - ptw->in_ptw_idx &= ~1; |
49 | + case 0b00110: /* DGH */ | 67 | + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS); |
50 | /* we treat all as NOP at least for now */ | 68 | + QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); |
51 | break; | 69 | + ptw->in_ptw_idx += 1; |
52 | case 0b00111: /* XPACLRI */ | 70 | ptw->in_secure = false; |
71 | } | ||
72 | if (!S1_ptw_translate(env, ptw, descaddr, fi)) { | ||
53 | -- | 73 | -- |
54 | 2.25.1 | 74 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Check for and defer any pending virtual SError. | 3 | With FEAT_RME, there are four physical address spaces. |
4 | For now, just define the symbols, and mention them in | ||
5 | the same spots as the other Phys indexes in ptw.c. | ||
4 | 6 | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-17-richard.henderson@linaro.org | 10 | Message-id: 20230620124418.805717-9-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 12 | --- |
10 | target/arm/helper.h | 1 + | 13 | target/arm/cpu.h | 23 +++++++++++++++++++++-- |
11 | target/arm/a32.decode | 16 ++++++++------ | 14 | target/arm/ptw.c | 10 ++++++++-- |
12 | target/arm/t32.decode | 18 ++++++++-------- | 15 | 2 files changed, 29 insertions(+), 4 deletions(-) |
13 | target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-a64.c | 17 +++++++++++++++ | ||
15 | target/arm/translate.c | 23 ++++++++++++++++++++ | ||
16 | 6 files changed, 103 insertions(+), 15 deletions(-) | ||
17 | 16 | ||
18 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper.h | 19 | --- a/target/arm/cpu.h |
21 | +++ b/target/arm/helper.h | 20 | +++ b/target/arm/cpu.h |
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env) | 21 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx { |
23 | DEF_HELPER_1(yield, void, env) | 22 | ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, |
24 | DEF_HELPER_1(pre_hvc, void, env) | 23 | |
25 | DEF_HELPER_2(pre_smc, void, env, i32) | 24 | /* TLBs with 1-1 mapping to the physical address spaces. */ |
26 | +DEF_HELPER_1(vesb, void, env) | 25 | - ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, |
27 | 26 | - ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, | |
28 | DEF_HELPER_3(cpsr_write, void, env, i32, i32) | 27 | + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, |
29 | DEF_HELPER_2(cpsr_write_eret, void, env, i32) | 28 | + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, |
30 | diff --git a/target/arm/a32.decode b/target/arm/a32.decode | 29 | + ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, |
31 | index XXXXXXX..XXXXXXX 100644 | 30 | + ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, |
32 | --- a/target/arm/a32.decode | 31 | |
33 | +++ b/target/arm/a32.decode | 32 | /* |
34 | @@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn | 33 | * These are not allocated TLBs and are used only for AT system |
35 | 34 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMASIdx { | |
36 | { | 35 | ARMASIdx_TagS = 3, |
37 | { | 36 | } ARMASIdx; |
38 | - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 | 37 | |
39 | - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 | 38 | +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) |
40 | - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 | 39 | +{ |
41 | + [ | 40 | + /* Assert the relative order of the physical mmu indexes. */ |
42 | + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 | 41 | + QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); |
43 | + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 | 42 | + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); |
44 | + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 | 43 | + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); |
45 | 44 | + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); | |
46 | - # TODO: Implement SEV, SEVL; may help SMP performance. | ||
47 | - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 | ||
48 | - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 | ||
49 | + # TODO: Implement SEV, SEVL; may help SMP performance. | ||
50 | + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 | ||
51 | + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 | ||
52 | + | 45 | + |
53 | + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 | 46 | + return ARMMMUIdx_Phys_S + space; |
54 | + ] | ||
55 | |||
56 | # The canonical nop ends in 00000000, but the whole of the | ||
57 | # rest of the space executes as nop if otherwise unsupported. | ||
58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/t32.decode | ||
61 | +++ b/target/arm/t32.decode | ||
62 | @@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm | ||
63 | [ | ||
64 | # Hints, and CPS | ||
65 | { | ||
66 | - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | ||
67 | - WFE 1111 0011 1010 1111 1000 0000 0000 0010 | ||
68 | - WFI 1111 0011 1010 1111 1000 0000 0000 0011 | ||
69 | + [ | ||
70 | + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | ||
71 | + WFE 1111 0011 1010 1111 1000 0000 0000 0010 | ||
72 | + WFI 1111 0011 1010 1111 1000 0000 0000 0011 | ||
73 | |||
74 | - # TODO: Implement SEV, SEVL; may help SMP performance. | ||
75 | - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
76 | - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
77 | + # TODO: Implement SEV, SEVL; may help SMP performance. | ||
78 | + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
79 | + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
80 | |||
81 | - # For M-profile minimal-RAS ESB can be a NOP, which is the | ||
82 | - # default behaviour since it is in the hint space. | ||
83 | - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
84 | + ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
85 | + ] | ||
86 | |||
87 | # The canonical nop ends in 0000 0000, but the whole rest | ||
88 | # of the space is "reserved hint, behaves as nop". | ||
89 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
90 | index XXXXXXX..XXXXXXX 100644 | ||
91 | --- a/target/arm/op_helper.c | ||
92 | +++ b/target/arm/op_helper.c | ||
93 | @@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, | ||
94 | access_type, mmu_idx, ra); | ||
95 | } | ||
96 | } | ||
97 | + | ||
98 | +/* | ||
99 | + * This function corresponds to AArch64.vESBOperation(). | ||
100 | + * Note that the AArch32 version is not functionally different. | ||
101 | + */ | ||
102 | +void HELPER(vesb)(CPUARMState *env) | ||
103 | +{ | ||
104 | + /* | ||
105 | + * The EL2Enabled() check is done inside arm_hcr_el2_eff, | ||
106 | + * and will return HCR_EL2.VSE == 0, so nothing happens. | ||
107 | + */ | ||
108 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
109 | + bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO); | ||
110 | + bool pending = enabled && (hcr & HCR_VSE); | ||
111 | + bool masked = (env->daif & PSTATE_A); | ||
112 | + | ||
113 | + /* If VSE pending and masked, defer the exception. */ | ||
114 | + if (pending && masked) { | ||
115 | + uint32_t syndrome; | ||
116 | + | ||
117 | + if (arm_el_is_aa64(env, 1)) { | ||
118 | + /* Copy across IDS and ISS from VSESR. */ | ||
119 | + syndrome = env->cp15.vsesr_el2 & 0x1ffffff; | ||
120 | + } else { | ||
121 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal }; | ||
122 | + | ||
123 | + if (extended_addresses_enabled(env)) { | ||
124 | + syndrome = arm_fi_to_lfsc(&fi); | ||
125 | + } else { | ||
126 | + syndrome = arm_fi_to_sfsc(&fi); | ||
127 | + } | ||
128 | + /* Copy across AET and ExT from VSESR. */ | ||
129 | + syndrome |= env->cp15.vsesr_el2 & 0xd000; | ||
130 | + } | ||
131 | + | ||
132 | + /* Set VDISR_EL2.A along with the syndrome. */ | ||
133 | + env->cp15.vdisr_el2 = syndrome | (1u << 31); | ||
134 | + | ||
135 | + /* Clear pending virtual SError */ | ||
136 | + env->cp15.hcr_el2 &= ~HCR_VSE; | ||
137 | + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); | ||
138 | + } | ||
139 | +} | ||
140 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
141 | index XXXXXXX..XXXXXXX 100644 | ||
142 | --- a/target/arm/translate-a64.c | ||
143 | +++ b/target/arm/translate-a64.c | ||
144 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, | ||
145 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
146 | } | ||
147 | break; | ||
148 | + case 0b10000: /* ESB */ | ||
149 | + /* Without RAS, we must implement this as NOP. */ | ||
150 | + if (dc_isar_feature(aa64_ras, s)) { | ||
151 | + /* | ||
152 | + * QEMU does not have a source of physical SErrors, | ||
153 | + * so we are only concerned with virtual SErrors. | ||
154 | + * The pseudocode in the ARM for this case is | ||
155 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
156 | + * AArch64.vESBOperation(); | ||
157 | + * Most of the condition can be evaluated at translation time. | ||
158 | + * Test for EL2 present, and defer test for SEL2 to runtime. | ||
159 | + */ | ||
160 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
161 | + gen_helper_vesb(cpu_env); | ||
162 | + } | ||
163 | + } | ||
164 | + break; | ||
165 | case 0b11000: /* PACIAZ */ | ||
166 | if (s->pauth_active) { | ||
167 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | ||
168 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
169 | index XXXXXXX..XXXXXXX 100644 | ||
170 | --- a/target/arm/translate.c | ||
171 | +++ b/target/arm/translate.c | ||
172 | @@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) | ||
173 | return true; | ||
174 | } | ||
175 | |||
176 | +static bool trans_ESB(DisasContext *s, arg_ESB *a) | ||
177 | +{ | ||
178 | + /* | ||
179 | + * For M-profile, minimal-RAS ESB can be a NOP. | ||
180 | + * Without RAS, we must implement this as NOP. | ||
181 | + */ | ||
182 | + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) { | ||
183 | + /* | ||
184 | + * QEMU does not have a source of physical SErrors, | ||
185 | + * so we are only concerned with virtual SErrors. | ||
186 | + * The pseudocode in the ARM for this case is | ||
187 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
188 | + * AArch32.vESBOperation(); | ||
189 | + * Most of the condition can be evaluated at translation time. | ||
190 | + * Test for EL2 present, and defer test for SEL2 to runtime. | ||
191 | + */ | ||
192 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
193 | + gen_helper_vesb(cpu_env); | ||
194 | + } | ||
195 | + } | ||
196 | + return true; | ||
197 | +} | 47 | +} |
198 | + | 48 | + |
199 | static bool trans_NOP(DisasContext *s, arg_NOP *a) | 49 | +static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) |
50 | +{ | ||
51 | + assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); | ||
52 | + return idx - ARMMMUIdx_Phys_S; | ||
53 | +} | ||
54 | + | ||
55 | static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) | ||
200 | { | 56 | { |
201 | return true; | 57 | /* If all the CLIDR.Ctypem bits are 0 there are no caches, and |
58 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/ptw.c | ||
61 | +++ b/target/arm/ptw.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, | ||
63 | case ARMMMUIdx_E3: | ||
64 | break; | ||
65 | |||
66 | - case ARMMMUIdx_Phys_NS: | ||
67 | case ARMMMUIdx_Phys_S: | ||
68 | + case ARMMMUIdx_Phys_NS: | ||
69 | + case ARMMMUIdx_Phys_Root: | ||
70 | + case ARMMMUIdx_Phys_Realm: | ||
71 | /* No translation for physical address spaces. */ | ||
72 | return true; | ||
73 | |||
74 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, | ||
75 | switch (mmu_idx) { | ||
76 | case ARMMMUIdx_Stage2: | ||
77 | case ARMMMUIdx_Stage2_S: | ||
78 | - case ARMMMUIdx_Phys_NS: | ||
79 | case ARMMMUIdx_Phys_S: | ||
80 | + case ARMMMUIdx_Phys_NS: | ||
81 | + case ARMMMUIdx_Phys_Root: | ||
82 | + case ARMMMUIdx_Phys_Realm: | ||
83 | break; | ||
84 | |||
85 | default: | ||
86 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
87 | switch (mmu_idx) { | ||
88 | case ARMMMUIdx_Phys_S: | ||
89 | case ARMMMUIdx_Phys_NS: | ||
90 | + case ARMMMUIdx_Phys_Root: | ||
91 | + case ARMMMUIdx_Phys_Realm: | ||
92 | /* Checking Phys early avoids special casing later vs regime_el. */ | ||
93 | return get_phys_addr_disabled(env, address, access_type, mmu_idx, | ||
94 | is_secure, result, fi); | ||
202 | -- | 95 | -- |
203 | 2.25.1 | 96 | 2.34.1 |
97 | |||
98 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns cache speculation, which TCG does | 3 | This was added in 7e98e21c098 as part of a reorg in which |
4 | not implement. Thus we can trivially enable this feature. | 4 | one of the argument had been legally NULL, and this caught |
5 | actual instances. Now that the reorg is complete, this | ||
6 | serves little purpose. | ||
5 | 7 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-22-richard.henderson@linaro.org | 11 | Message-id: 20230620124418.805717-10-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 14 | target/arm/ptw.c | 6 ++---- |
12 | target/arm/cpu64.c | 1 + | 15 | 1 file changed, 2 insertions(+), 4 deletions(-) |
13 | target/arm/cpu_tcg.c | 1 + | ||
14 | 3 files changed, 3 insertions(+) | ||
15 | 16 | ||
16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 17 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/emulation.rst | 19 | --- a/target/arm/ptw.c |
19 | +++ b/docs/system/arm/emulation.rst | 20 | +++ b/target/arm/ptw.c |
20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 21 | @@ -XXX,XX +XXX,XX @@ typedef struct S1Translate { |
21 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | 22 | static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | 23 | uint64_t address, |
23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | 24 | MMUAccessType access_type, bool s1_is_el0, |
24 | +- FEAT_CSV3 (Cache speculation variant 3) | 25 | - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) |
25 | - FEAT_DIT (Data Independent Timing instructions) | 26 | - __attribute__((nonnull)); |
26 | - FEAT_DPB (DC CVAP instruction) | 27 | + GetPhysAddrResult *result, ARMMMUFaultInfo *fi); |
27 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 28 | |
28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 29 | static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
29 | index XXXXXXX..XXXXXXX 100644 | 30 | target_ulong address, |
30 | --- a/target/arm/cpu64.c | 31 | MMUAccessType access_type, |
31 | +++ b/target/arm/cpu64.c | 32 | GetPhysAddrResult *result, |
32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 33 | - ARMMMUFaultInfo *fi) |
33 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | 34 | - __attribute__((nonnull)); |
34 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | 35 | + ARMMMUFaultInfo *fi); |
35 | t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | 36 | |
36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ | 37 | /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ |
37 | cpu->isar.id_aa64pfr0 = t; | 38 | static const uint8_t pamax_map[] = { |
38 | |||
39 | t = cpu->isar.id_aa64pfr1; | ||
40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/cpu_tcg.c | ||
43 | +++ b/target/arm/cpu_tcg.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
45 | cpu->isar.id_pfr0 = t; | ||
46 | |||
47 | t = cpu->isar.id_pfr2; | ||
48 | + t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ | ||
49 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | ||
50 | cpu->isar.id_pfr2 = t; | ||
51 | |||
52 | -- | 39 | -- |
53 | 2.25.1 | 40 | 2.34.1 |
41 | |||
42 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Update the legacy feature names to the current names. | 3 | Add input and output space members to S1Translate. Set and adjust |
4 | Provide feature names for id changes that were not marked. | 4 | them in S1_ptw_translate, and the various points at which we drop |
5 | Sort the field updates into increasing bitfield order. | 5 | secure state. Initialize the space in get_phys_addr; for now leave |
6 | get_phys_addr_with_secure considering only secure vs non-secure spaces. | ||
6 | 7 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-10-richard.henderson@linaro.org | 10 | Message-id: 20230620124418.805717-11-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | target/arm/cpu64.c | 100 +++++++++++++++++++++---------------------- | 13 | target/arm/ptw.c | 86 +++++++++++++++++++++++++++++++++++++++--------- |
13 | target/arm/cpu_tcg.c | 48 ++++++++++----------- | 14 | 1 file changed, 71 insertions(+), 15 deletions(-) |
14 | 2 files changed, 74 insertions(+), 74 deletions(-) | ||
15 | 15 | ||
16 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 16 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu64.c | 18 | --- a/target/arm/ptw.c |
19 | +++ b/target/arm/cpu64.c | 19 | +++ b/target/arm/ptw.c |
20 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 20 | @@ -XXX,XX +XXX,XX @@ |
21 | cpu->midr = t; | 21 | typedef struct S1Translate { |
22 | 22 | ARMMMUIdx in_mmu_idx; | |
23 | t = cpu->isar.id_aa64isar0; | 23 | ARMMMUIdx in_ptw_idx; |
24 | - t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ | 24 | + ARMSecuritySpace in_space; |
25 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); | 25 | bool in_secure; |
26 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ | 26 | bool in_debug; |
27 | + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ | 27 | bool out_secure; |
28 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ | 28 | bool out_rw; |
29 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ | 29 | bool out_be; |
30 | t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | 30 | + ARMSecuritySpace out_space; |
31 | - t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); | 31 | hwaddr out_virt; |
32 | - t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); | 32 | hwaddr out_phys; |
33 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); | 33 | void *out_host; |
34 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); | 34 | @@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) |
35 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); | 35 | static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
36 | - t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); | 36 | hwaddr addr, ARMMMUFaultInfo *fi) |
37 | - t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); | 37 | { |
38 | - t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ | 38 | + ARMSecuritySpace space = ptw->in_space; |
39 | - t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | 39 | bool is_secure = ptw->in_secure; |
40 | - t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); | 40 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
41 | + t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ | 41 | ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; |
42 | + t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | 42 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
43 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | 43 | .in_mmu_idx = s2_mmu_idx, |
44 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ | 44 | .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), |
45 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ | 45 | .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, |
46 | + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ | 46 | + .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure |
47 | + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ | 47 | + : space == ARMSS_Realm ? ARMSS_Realm |
48 | + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ | 48 | + : ARMSS_NonSecure), |
49 | + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | 49 | .in_debug = true, |
50 | + t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ | 50 | }; |
51 | cpu->isar.id_aa64isar0 = t; | 51 | GetPhysAddrResult s2 = { }; |
52 | 52 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | |
53 | t = cpu->isar.id_aa64isar1; | 53 | ptw->out_phys = s2.f.phys_addr; |
54 | - t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); | 54 | pte_attrs = s2.cacheattrs.attrs; |
55 | - t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); | 55 | ptw->out_secure = s2.f.attrs.secure; |
56 | - t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); | 56 | + ptw->out_space = s2.f.attrs.space; |
57 | - t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | 57 | } else { |
58 | - t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | 58 | /* Regime is physical. */ |
59 | - t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); | 59 | ptw->out_phys = addr; |
60 | - t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); | 60 | pte_attrs = 0; |
61 | - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ | 61 | ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; |
62 | - t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); | 62 | + ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure |
63 | + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ | 63 | + : space == ARMSS_Realm ? ARMSS_Realm |
64 | + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ | 64 | + : ARMSS_NonSecure); |
65 | + t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ | 65 | } |
66 | + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ | 66 | ptw->out_host = NULL; |
67 | + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ | 67 | ptw->out_rw = false; |
68 | + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | 68 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
69 | + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | 69 | ptw->out_rw = full->prot & PAGE_WRITE; |
70 | + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | 70 | pte_attrs = full->pte_attrs; |
71 | + t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | 71 | ptw->out_secure = full->attrs.secure; |
72 | cpu->isar.id_aa64isar1 = t; | 72 | + ptw->out_space = full->attrs.space; |
73 | 73 | #else | |
74 | t = cpu->isar.id_aa64pfr0; | 74 | g_assert_not_reached(); |
75 | + t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | 75 | #endif |
76 | + t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | 76 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, |
77 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | 77 | } |
78 | - t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); | 78 | } else { |
79 | - t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); | 79 | /* Page tables are in MMIO. */ |
80 | - t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); | 80 | - MemTxAttrs attrs = { .secure = ptw->out_secure }; |
81 | - t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); | 81 | + MemTxAttrs attrs = { |
82 | + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | 82 | + .secure = ptw->out_secure, |
83 | + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | 83 | + .space = ptw->out_space, |
84 | cpu->isar.id_aa64pfr0 = t; | 84 | + }; |
85 | 85 | AddressSpace *as = arm_addressspace(cs, attrs); | |
86 | t = cpu->isar.id_aa64pfr1; | 86 | MemTxResult result = MEMTX_OK; |
87 | - t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | 87 | |
88 | - t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); | 88 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, |
89 | + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ | 89 | #endif |
90 | + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ | 90 | } else { |
91 | /* Page tables are in MMIO. */ | ||
92 | - MemTxAttrs attrs = { .secure = ptw->out_secure }; | ||
93 | + MemTxAttrs attrs = { | ||
94 | + .secure = ptw->out_secure, | ||
95 | + .space = ptw->out_space, | ||
96 | + }; | ||
97 | AddressSpace *as = arm_addressspace(cs, attrs); | ||
98 | MemTxResult result = MEMTX_OK; | ||
99 | |||
100 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw, | ||
101 | * regime, because the attribute will already be non-secure. | ||
102 | */ | ||
103 | result->f.attrs.secure = false; | ||
104 | + result->f.attrs.space = ARMSS_NonSecure; | ||
105 | } | ||
106 | result->f.phys_addr = phys_addr; | ||
107 | return false; | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
109 | * regime, because the attribute will already be non-secure. | ||
110 | */ | ||
111 | result->f.attrs.secure = false; | ||
112 | + result->f.attrs.space = ARMSS_NonSecure; | ||
113 | } | ||
114 | |||
115 | if (regime_is_stage2(mmu_idx)) { | ||
116 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | ||
117 | */ | ||
118 | if (sattrs.ns) { | ||
119 | result->f.attrs.secure = false; | ||
120 | + result->f.attrs.space = ARMSS_NonSecure; | ||
121 | } else if (!secure) { | ||
122 | /* | ||
123 | * NS access to S memory must fault. | ||
124 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
125 | bool is_secure = ptw->in_secure; | ||
126 | bool ret, ipa_secure; | ||
127 | ARMCacheAttrs cacheattrs1; | ||
128 | + ARMSecuritySpace ipa_space; | ||
129 | bool is_el0; | ||
130 | uint64_t hcr; | ||
131 | |||
132 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
133 | |||
134 | ipa = result->f.phys_addr; | ||
135 | ipa_secure = result->f.attrs.secure; | ||
136 | + ipa_space = result->f.attrs.space; | ||
137 | |||
138 | is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; | ||
139 | ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
140 | ptw->in_secure = ipa_secure; | ||
141 | + ptw->in_space = ipa_space; | ||
142 | ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); | ||
143 | |||
91 | /* | 144 | /* |
92 | * Begin with full support for MTE. This will be downgraded to MTE=0 | 145 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
93 | * during realize if the board provides no tag memory, much like | 146 | ARMMMUIdx s1_mmu_idx; |
94 | * we do for EL2 with the virtualization=on property. | 147 | |
148 | /* | ||
149 | - * The page table entries may downgrade secure to non-secure, but | ||
150 | - * cannot upgrade an non-secure translation regime's attributes | ||
151 | - * to secure. | ||
152 | + * The page table entries may downgrade Secure to NonSecure, but | ||
153 | + * cannot upgrade a NonSecure translation regime's attributes | ||
154 | + * to Secure or Realm. | ||
95 | */ | 155 | */ |
96 | - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); | 156 | result->f.attrs.secure = is_secure; |
97 | + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | 157 | + result->f.attrs.space = ptw->in_space; |
98 | cpu->isar.id_aa64pfr1 = t; | 158 | |
99 | 159 | switch (mmu_idx) { | |
100 | t = cpu->isar.id_aa64mmfr0; | 160 | case ARMMMUIdx_Phys_S: |
101 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 161 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
102 | cpu->isar.id_aa64mmfr0 = t; | 162 | |
103 | 163 | default: | |
104 | t = cpu->isar.id_aa64mmfr1; | 164 | /* Single stage uses physical for ptw. */ |
105 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | 165 | - ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; |
106 | - t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); | 166 | + ptw->in_ptw_idx = arm_space_to_phys(ptw->in_space); |
107 | - t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); | 167 | break; |
108 | - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ | 168 | } |
109 | - t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ | 169 | |
110 | - t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ | 170 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, |
111 | + t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | 171 | S1Translate ptw = { |
112 | + t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | 172 | .in_mmu_idx = mmu_idx, |
113 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | 173 | .in_secure = is_secure, |
114 | + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | 174 | + .in_space = arm_secure_to_space(is_secure), |
115 | + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ | 175 | }; |
116 | + t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | 176 | return get_phys_addr_with_struct(env, &ptw, address, access_type, |
117 | cpu->isar.id_aa64mmfr1 = t; | 177 | result, fi); |
118 | 178 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | |
119 | t = cpu->isar.id_aa64mmfr2; | 179 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
120 | - t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | 180 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) |
121 | - t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | 181 | { |
122 | - t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | 182 | - bool is_secure; |
123 | - t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | 183 | + S1Translate ptw = { |
124 | - t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | 184 | + .in_mmu_idx = mmu_idx, |
125 | - t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | 185 | + }; |
126 | + t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | 186 | + ARMSecuritySpace ss; |
127 | + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | 187 | |
128 | + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | 188 | switch (mmu_idx) { |
129 | + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | 189 | case ARMMMUIdx_E10_0: |
130 | + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | 190 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, |
131 | + t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | 191 | case ARMMMUIdx_Stage1_E1: |
132 | cpu->isar.id_aa64mmfr2 = t; | 192 | case ARMMMUIdx_Stage1_E1_PAN: |
133 | 193 | case ARMMMUIdx_E2: | |
134 | t = cpu->isar.id_aa64zfr0; | 194 | - is_secure = arm_is_secure_below_el3(env); |
135 | t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); | 195 | + ss = arm_security_space_below_el3(env); |
136 | - t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ | 196 | break; |
137 | - t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); | 197 | case ARMMMUIdx_Stage2: |
138 | - t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); | 198 | + /* |
139 | - t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); | 199 | + * For Secure EL2, we need this index to be NonSecure; |
140 | - t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); | 200 | + * otherwise this will already be NonSecure or Realm. |
141 | - t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); | 201 | + */ |
142 | - t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); | 202 | + ss = arm_security_space_below_el3(env); |
143 | - t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | 203 | + if (ss == ARMSS_Secure) { |
144 | + t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ | 204 | + ss = ARMSS_NonSecure; |
145 | + t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ | 205 | + } |
146 | + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ | 206 | + break; |
147 | + t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ | 207 | case ARMMMUIdx_Phys_NS: |
148 | + t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ | 208 | case ARMMMUIdx_MPrivNegPri: |
149 | + t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ | 209 | case ARMMMUIdx_MUserNegPri: |
150 | + t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ | 210 | case ARMMMUIdx_MPriv: |
151 | + t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ | 211 | case ARMMMUIdx_MUser: |
152 | cpu->isar.id_aa64zfr0 = t; | 212 | - is_secure = false; |
153 | 213 | + ss = ARMSS_NonSecure; | |
154 | t = cpu->isar.id_aa64dfr0; | 214 | break; |
155 | - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | 215 | - case ARMMMUIdx_E3: |
156 | + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | 216 | case ARMMMUIdx_Stage2_S: |
157 | cpu->isar.id_aa64dfr0 = t; | 217 | case ARMMMUIdx_Phys_S: |
158 | 218 | case ARMMMUIdx_MSPrivNegPri: | |
159 | /* Replicate the same data to the 32-bit id registers. */ | 219 | case ARMMMUIdx_MSUserNegPri: |
160 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 220 | case ARMMMUIdx_MSPriv: |
161 | index XXXXXXX..XXXXXXX 100644 | 221 | case ARMMMUIdx_MSUser: |
162 | --- a/target/arm/cpu_tcg.c | 222 | - is_secure = true; |
163 | +++ b/target/arm/cpu_tcg.c | 223 | + ss = ARMSS_Secure; |
164 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 224 | + break; |
165 | 225 | + case ARMMMUIdx_E3: | |
166 | /* Add additional features supported by QEMU */ | 226 | + if (arm_feature(env, ARM_FEATURE_AARCH64) && |
167 | t = cpu->isar.id_isar5; | 227 | + cpu_isar_feature(aa64_rme, env_archcpu(env))) { |
168 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | 228 | + ss = ARMSS_Root; |
169 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | 229 | + } else { |
170 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | 230 | + ss = ARMSS_Secure; |
171 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ | 231 | + } |
172 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ | 232 | + break; |
173 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ | 233 | + case ARMMMUIdx_Phys_Root: |
174 | t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | 234 | + ss = ARMSS_Root; |
175 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | 235 | + break; |
176 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | 236 | + case ARMMMUIdx_Phys_Realm: |
177 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ | 237 | + ss = ARMSS_Realm; |
178 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ | 238 | break; |
179 | cpu->isar.id_isar5 = t; | 239 | default: |
180 | 240 | g_assert_not_reached(); | |
181 | t = cpu->isar.id_isar6; | 241 | } |
182 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | 242 | - return get_phys_addr_with_secure(env, address, access_type, mmu_idx, |
183 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | 243 | - is_secure, result, fi); |
184 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | 244 | + |
185 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | 245 | + ptw.in_space = ss; |
186 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | 246 | + ptw.in_secure = arm_space_is_secure(ss); |
187 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | 247 | + return get_phys_addr_with_struct(env, &ptw, address, access_type, |
188 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | 248 | + result, fi); |
189 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ | ||
190 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ | ||
191 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ | ||
192 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ | ||
193 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ | ||
194 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ | ||
195 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ | ||
196 | cpu->isar.id_isar6 = t; | ||
197 | |||
198 | t = cpu->isar.mvfr1; | ||
199 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
200 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
201 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ | ||
202 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ | ||
203 | cpu->isar.mvfr1 = t; | ||
204 | |||
205 | t = cpu->isar.mvfr2; | ||
206 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
207 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
208 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
209 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
210 | cpu->isar.mvfr2 = t; | ||
211 | |||
212 | t = cpu->isar.id_mmfr3; | ||
213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
214 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ | ||
215 | cpu->isar.id_mmfr3 = t; | ||
216 | |||
217 | t = cpu->isar.id_mmfr4; | ||
218 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
219 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
220 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
221 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
222 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ | ||
223 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
224 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ | ||
225 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ | ||
226 | cpu->isar.id_mmfr4 = t; | ||
227 | |||
228 | t = cpu->isar.id_pfr0; | ||
229 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
230 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
231 | cpu->isar.id_pfr0 = t; | ||
232 | |||
233 | t = cpu->isar.id_pfr2; | ||
234 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
235 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | ||
236 | cpu->isar.id_pfr2 = t; | ||
237 | |||
238 | t = cpu->isar.id_dfr0; | ||
239 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
240 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
241 | cpu->isar.id_dfr0 = t; | ||
242 | } | 249 | } |
243 | 250 | ||
251 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, | ||
252 | @@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, | ||
253 | { | ||
254 | ARMCPU *cpu = ARM_CPU(cs); | ||
255 | CPUARMState *env = &cpu->env; | ||
256 | + ARMMMUIdx mmu_idx = arm_mmu_idx(env); | ||
257 | + ARMSecuritySpace ss = arm_security_space(env); | ||
258 | S1Translate ptw = { | ||
259 | - .in_mmu_idx = arm_mmu_idx(env), | ||
260 | - .in_secure = arm_is_secure(env), | ||
261 | + .in_mmu_idx = mmu_idx, | ||
262 | + .in_space = ss, | ||
263 | + .in_secure = arm_space_is_secure(ss), | ||
264 | .in_debug = true, | ||
265 | }; | ||
266 | GetPhysAddrResult res = {}; | ||
244 | -- | 267 | -- |
245 | 2.25.1 | 268 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local | 3 | Test in_space instead of in_secure so that we don't |
4 | vpidr_regs definition, and rely on the squashing to ARM_CP_CONST | 4 | switch out of Root space. |
5 | while registering for v8. | ||
6 | |||
7 | This is a behavior change for v7 cpus with Security Extensions and | ||
8 | without Virtualization Extensions, in that the virtualization cpregs | ||
9 | are now correctly not present. This would be a migration compatibility | ||
10 | break, except that we have an existing bug in which migration of 32-bit | ||
11 | cpus with Security Extensions enabled does not work. | ||
12 | 5 | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20220506180242.216785-3-richard.henderson@linaro.org | 8 | Message-id: 20230620124418.805717-12-richard.henderson@linaro.org |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 10 | --- |
18 | target/arm/helper.c | 158 ++++---------------------------------------- | 11 | target/arm/ptw.c | 28 ++++++++++++++-------------- |
19 | 1 file changed, 13 insertions(+), 145 deletions(-) | 12 | 1 file changed, 14 insertions(+), 14 deletions(-) |
20 | 13 | ||
21 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
22 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/helper.c | 16 | --- a/target/arm/ptw.c |
24 | +++ b/target/arm/helper.c | 17 | +++ b/target/arm/ptw.c |
25 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
26 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | ||
27 | }; | ||
28 | |||
29 | -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ | ||
30 | -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | ||
31 | - { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
32 | - .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | ||
33 | - .access = PL2_RW, | ||
34 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | ||
35 | - { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
36 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | ||
37 | - .access = PL2_RW, | ||
38 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
39 | - { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, | ||
40 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | ||
41 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
42 | - { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, | ||
43 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | ||
44 | - .access = PL2_RW, | ||
45 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
46 | - { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
47 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | ||
48 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
49 | - { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, | ||
50 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | ||
51 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
52 | - .resetvalue = 0 }, | ||
53 | - { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | ||
54 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | ||
55 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
56 | - { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, | ||
57 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | ||
58 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
59 | - .resetvalue = 0 }, | ||
60 | - { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, | ||
61 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | ||
62 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
63 | - .resetvalue = 0 }, | ||
64 | - { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, | ||
65 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | ||
66 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
67 | - .resetvalue = 0 }, | ||
68 | - { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | ||
69 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | ||
70 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
71 | - .resetvalue = 0 }, | ||
72 | - { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
73 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | ||
74 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
75 | - { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
76 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | ||
77 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
78 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | - { .name = "VTTBR", .state = ARM_CP_STATE_AA32, | ||
80 | - .cp = 15, .opc1 = 6, .crm = 2, | ||
81 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
82 | - .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
83 | - { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | ||
84 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | ||
85 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
86 | - { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, | ||
87 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | ||
88 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
89 | - { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
90 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | ||
91 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
92 | - { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, | ||
93 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | ||
94 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
95 | - { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | ||
96 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
97 | - .resetvalue = 0 }, | ||
98 | - { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
99 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | ||
100 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
101 | - { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, | ||
102 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | ||
103 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
104 | - { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | ||
105 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
106 | - .resetvalue = 0 }, | ||
107 | - { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, | ||
108 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | ||
109 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
110 | - { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | ||
111 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
112 | - .resetvalue = 0 }, | ||
113 | - { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | ||
114 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | ||
115 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
116 | - { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
117 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | ||
118 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
119 | - { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
120 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | ||
121 | - .access = PL2_RW, .accessfn = access_tda, | ||
122 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
123 | - { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
124 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | ||
125 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
126 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
127 | - { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
128 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | ||
129 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
130 | - { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
131 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | ||
132 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
133 | - { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | ||
134 | - .type = ARM_CP_CONST, | ||
135 | - .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | ||
136 | - .access = PL2_RW, .resetvalue = 0 }, | ||
137 | -}; | ||
138 | - | ||
139 | -/* Ditto, but for registers which exist in ARMv8 but not v7 */ | ||
140 | -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | ||
141 | - { .name = "HCR2", .state = ARM_CP_STATE_AA32, | ||
142 | - .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | ||
143 | - .access = PL2_RW, | ||
144 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
145 | -}; | ||
146 | - | ||
147 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
148 | { | 19 | { |
149 | ARMCPU *cpu = env_archcpu(env); | 20 | ARMCPU *cpu = env_archcpu(env); |
150 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 21 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
151 | define_arm_cp_regs(cpu, v8_idregs); | 22 | - bool is_secure = ptw->in_secure; |
152 | define_arm_cp_regs(cpu, v8_cp_reginfo); | 23 | int32_t level; |
24 | ARMVAParameters param; | ||
25 | uint64_t ttbr; | ||
26 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
27 | uint64_t descaddrmask; | ||
28 | bool aarch64 = arm_el_is_aa64(env, el); | ||
29 | uint64_t descriptor, new_descriptor; | ||
30 | - bool nstable; | ||
31 | |||
32 | /* TODO: This code does not support shareability levels. */ | ||
33 | if (aarch64) { | ||
34 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
35 | descaddrmask = MAKE_64BIT_MASK(0, 40); | ||
153 | } | 36 | } |
154 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | 37 | descaddrmask &= ~indexmask_grainsize; |
38 | - | ||
39 | - /* | ||
40 | - * Secure stage 1 accesses start with the page table in secure memory and | ||
41 | - * can be downgraded to non-secure at any step. Non-secure accesses | ||
42 | - * remain non-secure. We implement this by just ORing in the NSTable/NS | ||
43 | - * bits at each step. | ||
44 | - * Stage 2 never gets this kind of downgrade. | ||
45 | - */ | ||
46 | - tableattrs = is_secure ? 0 : (1 << 4); | ||
47 | + tableattrs = 0; | ||
48 | |||
49 | next_level: | ||
50 | descaddr |= (address >> (stride * (4 - level))) & indexmask; | ||
51 | descaddr &= ~7ULL; | ||
52 | - nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); | ||
53 | - if (nstable && ptw->in_secure) { | ||
155 | + | 54 | + |
156 | + /* | 55 | + /* |
157 | + * Register the base EL2 cpregs. | 56 | + * Process the NSTable bit from the previous level. This changes |
158 | + * Pre v8, these registers are implemented only as part of the | 57 | + * the table address space and the output space from Secure to |
159 | + * Virtualization Extensions (EL2 present). Beginning with v8, | 58 | + * NonSecure. With RME, the EL3 translation regime does not change |
160 | + * if EL2 is missing but EL3 is enabled, mostly these become | 59 | + * from Root to NonSecure. |
161 | + * RES0 from EL3, with some specific exceptions. | ||
162 | + */ | 60 | + */ |
163 | + if (arm_feature(env, ARM_FEATURE_EL2) | 61 | + if (ptw->in_space == ARMSS_Secure |
164 | + || (arm_feature(env, ARM_FEATURE_EL3) | 62 | + && !regime_is_stage2(mmu_idx) |
165 | + && arm_feature(env, ARM_FEATURE_V8))) { | 63 | + && extract32(tableattrs, 4, 1)) { |
166 | uint64_t vmpidr_def = mpidr_read_val(env); | 64 | /* |
167 | ARMCPRegInfo vpidr_regs[] = { | 65 | * Stage2_S -> Stage2 or Phys_S -> Phys_NS |
168 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | 66 | * Assert the relative order of the secure/non-secure indexes. |
169 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 67 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
170 | }; | 68 | QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); |
171 | define_one_arm_cp_reg(cpu, &rvbar); | 69 | ptw->in_ptw_idx += 1; |
172 | } | 70 | ptw->in_secure = false; |
173 | - } else { | 71 | + ptw->in_space = ARMSS_NonSecure; |
174 | - /* If EL2 is missing but higher ELs are enabled, we need to | ||
175 | - * register the no_el2 reginfos. | ||
176 | - */ | ||
177 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
178 | - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value | ||
179 | - * of MIDR_EL1 and MPIDR_EL1. | ||
180 | - */ | ||
181 | - ARMCPRegInfo vpidr_regs[] = { | ||
182 | - { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
183 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
184 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
185 | - .type = ARM_CP_CONST, .resetvalue = cpu->midr, | ||
186 | - .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
187 | - { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
188 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
189 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
190 | - .type = ARM_CP_NO_RAW, | ||
191 | - .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | ||
192 | - }; | ||
193 | - define_arm_cp_regs(cpu, vpidr_regs); | ||
194 | - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); | ||
195 | - if (arm_feature(env, ARM_FEATURE_V8)) { | ||
196 | - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | ||
197 | - } | ||
198 | - } | ||
199 | } | 72 | } |
200 | + | 73 | + |
201 | + /* Register the base EL3 cpregs. */ | 74 | if (!S1_ptw_translate(env, ptw, descaddr, fi)) { |
202 | if (arm_feature(env, ARM_FEATURE_EL3)) { | 75 | goto do_fault; |
203 | define_arm_cp_regs(cpu, el3_cp_reginfo); | 76 | } |
204 | ARMCPRegInfo el3_regs[] = { | 77 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
78 | */ | ||
79 | attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); | ||
80 | if (!regime_is_stage2(mmu_idx)) { | ||
81 | - attrs |= nstable << 5; /* NS */ | ||
82 | + attrs |= !ptw->in_secure << 5; /* NS */ | ||
83 | if (!param.hpd) { | ||
84 | attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ | ||
85 | /* | ||
205 | -- | 86 | -- |
206 | 2.25.1 | 87 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | More gracefully handle cpregs when EL2 and/or EL3 are missing. | 3 | With Realm security state, bit 55 of a block or page descriptor during |
4 | If the reg is entirely inaccessible, do not register it at all. | 4 | the stage2 walk becomes the NS bit; during the stage1 walk the bit 5 |
5 | If the reg is for EL2, and EL3 is present but EL2 is not, | 5 | NS bit is RES0. With Root security state, bit 11 of the block or page |
6 | either discard, squash to res0, const, or keep unchanged. | 6 | descriptor during the stage1 walk becomes the NSE bit. |
7 | 7 | ||
8 | Per rule RJFFP, mark the 4 aarch32 hypervisor access registers | 8 | Rather than collecting an NS bit and applying it later, compute the |
9 | with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address | 9 | output pa space from the input pa space and unconditionally assign. |
10 | translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. | 10 | This means that we no longer need to adjust the output space earlier |
11 | Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ. | 11 | for the NSTable bit. |
12 | |||
13 | This will simplify cpreg registration for conditional arm features. | ||
14 | 12 | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
17 | Message-id: 20220506180242.216785-2-richard.henderson@linaro.org | 15 | Message-id: 20230620124418.805717-13-richard.henderson@linaro.org |
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 17 | --- |
20 | target/arm/cpregs.h | 11 +++ | 18 | target/arm/ptw.c | 89 +++++++++++++++++++++++++++++++++++++++--------- |
21 | target/arm/helper.c | 178 ++++++++++++++++++++++++++++++-------------- | 19 | 1 file changed, 73 insertions(+), 16 deletions(-) |
22 | 2 files changed, 133 insertions(+), 56 deletions(-) | ||
23 | 20 | ||
24 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 21 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
25 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpregs.h | 23 | --- a/target/arm/ptw.c |
27 | +++ b/target/arm/cpregs.h | 24 | +++ b/target/arm/ptw.c |
28 | @@ -XXX,XX +XXX,XX @@ enum { | 25 | @@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) |
29 | ARM_CP_SVE = 1 << 14, | 26 | * @mmu_idx: MMU index indicating required translation regime |
30 | /* Flag: Do not expose in gdb sysreg xml. */ | 27 | * @is_aa64: TRUE if AArch64 |
31 | ARM_CP_NO_GDB = 1 << 15, | 28 | * @ap: The 2-bit simple AP (AP[2:1]) |
32 | + /* | 29 | - * @ns: NS (non-secure) bit |
33 | + * Flags: If EL3 but not EL2... | 30 | * @xn: XN (execute-never) bit |
34 | + * - UNDEF: discard the cpreg, | 31 | * @pxn: PXN (privileged execute-never) bit |
35 | + * - KEEP: retain the cpreg as is, | 32 | + * @in_pa: The original input pa space |
36 | + * - C_NZ: set const on the cpreg, but retain resetvalue, | 33 | + * @out_pa: The output pa space, modified by NSTable, NS, and NSE |
37 | + * - else: set const on the cpreg, zero resetvalue, aka RES0. | 34 | */ |
38 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | 35 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, |
39 | + */ | 36 | - int ap, int ns, int xn, int pxn) |
40 | + ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, | 37 | + int ap, int xn, int pxn, |
41 | + ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, | 38 | + ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) |
42 | + ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, | ||
43 | }; | ||
44 | |||
45 | /* | ||
46 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/helper.c | ||
49 | +++ b/target/arm/helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
51 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, | ||
52 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, | ||
53 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | ||
54 | - .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU, | ||
55 | + .access = PL2_RW, | ||
56 | + .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | ||
57 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, | ||
58 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, | ||
59 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | ||
60 | - .access = PL2_RW, .resetvalue = 0, | ||
61 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | ||
62 | .writefn = dacr_write, .raw_writefn = raw_write, | ||
63 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | ||
64 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | ||
65 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | ||
66 | - .access = PL2_RW, .resetvalue = 0, | ||
67 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | ||
68 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | ||
69 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | ||
70 | .type = ARM_CP_ALIAS, | ||
71 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
72 | .writefn = tlbimva_hyp_is_write }, | ||
73 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, | ||
74 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | ||
75 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
76 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
77 | .writefn = tlbi_aa64_alle2_write }, | ||
78 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, | ||
79 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | ||
80 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
81 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
82 | .writefn = tlbi_aa64_vae2_write }, | ||
83 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, | ||
84 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | ||
85 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
86 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
87 | .writefn = tlbi_aa64_vae2_write }, | ||
88 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | ||
89 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | ||
90 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
91 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
92 | .writefn = tlbi_aa64_alle2is_write }, | ||
93 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, | ||
94 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | ||
95 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
96 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
97 | .writefn = tlbi_aa64_vae2is_write }, | ||
98 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, | ||
99 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | ||
100 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
101 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
102 | .writefn = tlbi_aa64_vae2is_write }, | ||
103 | #ifndef CONFIG_USER_ONLY | ||
104 | /* Unlike the other EL2-related AT operations, these must | ||
105 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
106 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | ||
108 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
109 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
110 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
111 | + .writefn = ats_write64 }, | ||
112 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | ||
113 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | ||
114 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
115 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
116 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
117 | + .writefn = ats_write64 }, | ||
118 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE | ||
119 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | ||
120 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | ||
121 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
122 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | ||
123 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | ||
124 | .access = PL2_RW, .accessfn = access_tda, | ||
125 | - .type = ARM_CP_NOP }, | ||
126 | + .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, | ||
127 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
128 | * Channel but Linux may try to access this register. The 32-bit | ||
129 | * alias is DBGDCCINT. | ||
130 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
131 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
132 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, | ||
133 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | ||
134 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
135 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
136 | .writefn = tlbi_aa64_rvae2is_write }, | ||
137 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | ||
138 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | ||
139 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
140 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
141 | .writefn = tlbi_aa64_rvae2is_write }, | ||
142 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | ||
143 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | ||
144 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
145 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
146 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, | ||
147 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | ||
148 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
149 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
150 | .writefn = tlbi_aa64_rvae2is_write }, | ||
151 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | ||
152 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | ||
153 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
154 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
155 | .writefn = tlbi_aa64_rvae2is_write }, | ||
156 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | ||
157 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | ||
158 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
159 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
160 | .writefn = tlbi_aa64_rvae2_write }, | ||
161 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | ||
162 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | ||
163 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
164 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
165 | .writefn = tlbi_aa64_rvae2_write }, | ||
166 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | ||
167 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | ||
168 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
169 | .writefn = tlbi_aa64_vae1is_write }, | ||
170 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, | ||
171 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | ||
172 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
173 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
174 | .writefn = tlbi_aa64_alle2is_write }, | ||
175 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, | ||
176 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | ||
177 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
178 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
179 | .writefn = tlbi_aa64_vae2is_write }, | ||
180 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, | ||
181 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | ||
182 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
183 | .writefn = tlbi_aa64_alle1is_write }, | ||
184 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, | ||
185 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | ||
186 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
187 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
188 | .writefn = tlbi_aa64_vae2is_write }, | ||
189 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, | ||
190 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | ||
191 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
192 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
193 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
194 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
195 | - .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, | ||
196 | + .resetvalue = cpu->midr, | ||
197 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
198 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | ||
199 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
200 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
201 | .access = PL2_RW, .resetvalue = cpu->midr, | ||
202 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
203 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
204 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, | ||
205 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
206 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
207 | - .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, | ||
208 | + .resetvalue = vmpidr_def, | ||
209 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
210 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | ||
211 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
212 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
213 | - .access = PL2_RW, | ||
214 | - .resetvalue = vmpidr_def, | ||
215 | + .access = PL2_RW, .resetvalue = vmpidr_def, | ||
216 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
217 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | ||
218 | }; | ||
219 | define_arm_cp_regs(cpu, vpidr_regs); | ||
220 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
221 | int crm, int opc1, int opc2, | ||
222 | const char *name) | ||
223 | { | 39 | { |
224 | + CPUARMState *env = &cpu->env; | 40 | ARMCPU *cpu = env_archcpu(env); |
225 | uint32_t key; | 41 | bool is_user = regime_is_user(env, mmu_idx); |
226 | ARMCPRegInfo *r2; | 42 | @@ -XXX,XX +XXX,XX @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, |
227 | bool is64 = r->type & ARM_CP_64BIT; | ||
228 | bool ns = secstate & ARM_CP_SECSTATE_NS; | ||
229 | int cp = r->cp; | ||
230 | - bool isbanked; | ||
231 | size_t name_len; | ||
232 | + bool make_const; | ||
233 | |||
234 | switch (state) { | ||
235 | case ARM_CP_STATE_AA32: | ||
236 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
237 | } | 43 | } |
238 | } | 44 | } |
239 | 45 | ||
240 | + /* | 46 | - if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { |
241 | + * Eliminate registers that are not present because the EL is missing. | 47 | + if (out_pa == ARMSS_NonSecure && in_pa == ARMSS_Secure && |
242 | + * Doing this here makes it easier to put all registers for a given | 48 | + (env->cp15.scr_el3 & SCR_SIF)) { |
243 | + * feature into the same ARMCPRegInfo array and define them all at once. | 49 | return prot_rw; |
244 | + */ | 50 | } |
245 | + make_const = false; | 51 | |
246 | + if (arm_feature(env, ARM_FEATURE_EL3)) { | 52 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
53 | int32_t stride; | ||
54 | int addrsize, inputsize, outputsize; | ||
55 | uint64_t tcr = regime_tcr(env, mmu_idx); | ||
56 | - int ap, ns, xn, pxn; | ||
57 | + int ap, xn, pxn; | ||
58 | uint32_t el = regime_el(env, mmu_idx); | ||
59 | uint64_t descaddrmask; | ||
60 | bool aarch64 = arm_el_is_aa64(env, el); | ||
61 | uint64_t descriptor, new_descriptor; | ||
62 | + ARMSecuritySpace out_space; | ||
63 | |||
64 | /* TODO: This code does not support shareability levels. */ | ||
65 | if (aarch64) { | ||
66 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
67 | } | ||
68 | |||
69 | ap = extract32(attrs, 6, 2); | ||
70 | + out_space = ptw->in_space; | ||
71 | if (regime_is_stage2(mmu_idx)) { | ||
72 | - ns = mmu_idx == ARMMMUIdx_Stage2; | ||
247 | + /* | 73 | + /* |
248 | + * An EL2 register without EL2 but with EL3 is (usually) RES0. | 74 | + * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. |
249 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | 75 | + * The bit remains ignored for other security states. |
250 | + */ | 76 | + */ |
251 | + int min_el = ctz32(r->access) / 2; | 77 | + if (out_space == ARMSS_Realm && extract64(attrs, 55, 1)) { |
252 | + if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | 78 | + out_space = ARMSS_NonSecure; |
253 | + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | 79 | + } |
254 | + return; | 80 | xn = extract64(attrs, 53, 2); |
81 | result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); | ||
82 | } else { | ||
83 | - ns = extract32(attrs, 5, 1); | ||
84 | + int nse, ns = extract32(attrs, 5, 1); | ||
85 | + switch (out_space) { | ||
86 | + case ARMSS_Root: | ||
87 | + /* | ||
88 | + * R_GVZML: Bit 11 becomes the NSE field in the EL3 regime. | ||
89 | + * R_XTYPW: NSE and NS together select the output pa space. | ||
90 | + */ | ||
91 | + nse = extract32(attrs, 11, 1); | ||
92 | + out_space = (nse << 1) | ns; | ||
93 | + if (out_space == ARMSS_Secure && | ||
94 | + !cpu_isar_feature(aa64_sel2, cpu)) { | ||
95 | + out_space = ARMSS_NonSecure; | ||
255 | + } | 96 | + } |
256 | + make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | 97 | + break; |
98 | + case ARMSS_Secure: | ||
99 | + if (ns) { | ||
100 | + out_space = ARMSS_NonSecure; | ||
101 | + } | ||
102 | + break; | ||
103 | + case ARMSS_Realm: | ||
104 | + switch (mmu_idx) { | ||
105 | + case ARMMMUIdx_Stage1_E0: | ||
106 | + case ARMMMUIdx_Stage1_E1: | ||
107 | + case ARMMMUIdx_Stage1_E1_PAN: | ||
108 | + /* I_CZPRF: For Realm EL1&0 stage1, NS bit is RES0. */ | ||
109 | + break; | ||
110 | + case ARMMMUIdx_E2: | ||
111 | + case ARMMMUIdx_E20_0: | ||
112 | + case ARMMMUIdx_E20_2: | ||
113 | + case ARMMMUIdx_E20_2_PAN: | ||
114 | + /* | ||
115 | + * R_LYKFZ, R_WGRZN: For Realm EL2 and EL2&1, | ||
116 | + * NS changes the output to non-secure space. | ||
117 | + */ | ||
118 | + if (ns) { | ||
119 | + out_space = ARMSS_NonSecure; | ||
120 | + } | ||
121 | + break; | ||
122 | + default: | ||
123 | + g_assert_not_reached(); | ||
124 | + } | ||
125 | + break; | ||
126 | + case ARMSS_NonSecure: | ||
127 | + /* R_QRMFF: For NonSecure state, the NS bit is RES0. */ | ||
128 | + break; | ||
129 | + default: | ||
130 | + g_assert_not_reached(); | ||
257 | + } | 131 | + } |
258 | + } else { | 132 | xn = extract64(attrs, 54, 1); |
259 | + CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | 133 | pxn = extract64(attrs, 53, 1); |
260 | + ? PL2_RW : PL1_RW); | 134 | - result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
261 | + if ((r->access & max_el) == 0) { | ||
262 | + return; | ||
263 | + } | ||
264 | + } | ||
265 | + | 135 | + |
266 | /* Combine cpreg and name into one allocation. */ | 136 | + /* |
267 | name_len = strlen(name) + 1; | 137 | + * Note that we modified ptw->in_space earlier for NSTable, but |
268 | r2 = g_malloc(sizeof(*r2) + name_len); | 138 | + * result->f.attrs retains a copy of the original security space. |
269 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 139 | + */ |
270 | r2->opaque = opaque; | 140 | + result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, |
141 | + result->f.attrs.space, out_space); | ||
271 | } | 142 | } |
272 | 143 | ||
273 | - isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | 144 | if (!(result->f.prot & (1 << access_type))) { |
274 | - if (isbanked) { | 145 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
275 | + if (make_const) { | ||
276 | + /* This should not have been a very special register to begin. */ | ||
277 | + int old_special = r2->type & ARM_CP_SPECIAL_MASK; | ||
278 | + assert(old_special == 0 || old_special == ARM_CP_NOP); | ||
279 | /* | ||
280 | - * Register is banked (using both entries in array). | ||
281 | - * Overwriting fieldoffset as the array is only used to define | ||
282 | - * banked registers but later only fieldoffset is used. | ||
283 | + * Set the special function to CONST, retaining the other flags. | ||
284 | + * This is important for e.g. ARM_CP_SVE so that we still | ||
285 | + * take the SVE trap if CPTR_EL3.EZ == 0. | ||
286 | */ | ||
287 | - r2->fieldoffset = r->bank_fieldoffsets[ns]; | ||
288 | - } | ||
289 | + r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; | ||
290 | + /* | ||
291 | + * Usually, these registers become RES0, but there are a few | ||
292 | + * special cases like VPIDR_EL2 which have a constant non-zero | ||
293 | + * value with writes ignored. | ||
294 | + */ | ||
295 | + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | ||
296 | + r2->resetvalue = 0; | ||
297 | + } | ||
298 | + /* | ||
299 | + * ARM_CP_CONST has precedence, so removing the callbacks and | ||
300 | + * offsets are not strictly necessary, but it is potentially | ||
301 | + * less confusing to debug later. | ||
302 | + */ | ||
303 | + r2->readfn = NULL; | ||
304 | + r2->writefn = NULL; | ||
305 | + r2->raw_readfn = NULL; | ||
306 | + r2->raw_writefn = NULL; | ||
307 | + r2->resetfn = NULL; | ||
308 | + r2->fieldoffset = 0; | ||
309 | + r2->bank_fieldoffsets[0] = 0; | ||
310 | + r2->bank_fieldoffsets[1] = 0; | ||
311 | + } else { | ||
312 | + bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | ||
313 | |||
314 | - if (state == ARM_CP_STATE_AA32) { | ||
315 | if (isbanked) { | ||
316 | /* | ||
317 | - * If the register is banked then we don't need to migrate or | ||
318 | - * reset the 32-bit instance in certain cases: | ||
319 | - * | ||
320 | - * 1) If the register has both 32-bit and 64-bit instances then we | ||
321 | - * can count on the 64-bit instance taking care of the | ||
322 | - * non-secure bank. | ||
323 | - * 2) If ARMv8 is enabled then we can count on a 64-bit version | ||
324 | - * taking care of the secure bank. This requires that separate | ||
325 | - * 32 and 64-bit definitions are provided. | ||
326 | + * Register is banked (using both entries in array). | ||
327 | + * Overwriting fieldoffset as the array is only used to define | ||
328 | + * banked registers but later only fieldoffset is used. | ||
329 | */ | ||
330 | - if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
331 | - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | ||
332 | + r2->fieldoffset = r->bank_fieldoffsets[ns]; | ||
333 | + } | ||
334 | + if (state == ARM_CP_STATE_AA32) { | ||
335 | + if (isbanked) { | ||
336 | + /* | ||
337 | + * If the register is banked then we don't need to migrate or | ||
338 | + * reset the 32-bit instance in certain cases: | ||
339 | + * | ||
340 | + * 1) If the register has both 32-bit and 64-bit instances | ||
341 | + * then we can count on the 64-bit instance taking care | ||
342 | + * of the non-secure bank. | ||
343 | + * 2) If ARMv8 is enabled then we can count on a 64-bit | ||
344 | + * version taking care of the secure bank. This requires | ||
345 | + * that separate 32 and 64-bit definitions are provided. | ||
346 | + */ | ||
347 | + if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
348 | + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | ||
349 | + r2->type |= ARM_CP_ALIAS; | ||
350 | + } | ||
351 | + } else if ((secstate != r->secure) && !ns) { | ||
352 | + /* | ||
353 | + * The register is not banked so we only want to allow | ||
354 | + * migration of the non-secure instance. | ||
355 | + */ | ||
356 | r2->type |= ARM_CP_ALIAS; | ||
357 | } | ||
358 | - } else if ((secstate != r->secure) && !ns) { | ||
359 | - /* | ||
360 | - * The register is not banked so we only want to allow migration | ||
361 | - * of the non-secure instance. | ||
362 | - */ | ||
363 | - r2->type |= ARM_CP_ALIAS; | ||
364 | - } | ||
365 | |||
366 | - if (HOST_BIG_ENDIAN && | ||
367 | - r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
368 | - r2->fieldoffset += sizeof(uint32_t); | ||
369 | + if (HOST_BIG_ENDIAN && | ||
370 | + r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
371 | + r2->fieldoffset += sizeof(uint32_t); | ||
372 | + } | ||
373 | } | 146 | } |
374 | } | 147 | } |
375 | 148 | ||
376 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 149 | - if (ns) { |
377 | * multiple times. Special registers (ie NOP/WFI) are | 150 | - /* |
378 | * never migratable and not even raw-accessible. | 151 | - * The NS bit will (as required by the architecture) have no effect if |
379 | */ | 152 | - * the CPU doesn't support TZ or this is a non-secure translation |
380 | - if (r->type & ARM_CP_SPECIAL_MASK) { | 153 | - * regime, because the attribute will already be non-secure. |
381 | + if (r2->type & ARM_CP_SPECIAL_MASK) { | 154 | - */ |
382 | r2->type |= ARM_CP_NO_RAW; | 155 | - result->f.attrs.secure = false; |
383 | } | 156 | - result->f.attrs.space = ARMSS_NonSecure; |
384 | if (((r->crm == CP_ANY) && crm != 0) || | 157 | - } |
158 | + result->f.attrs.space = out_space; | ||
159 | + result->f.attrs.secure = arm_space_is_secure(out_space); | ||
160 | |||
161 | if (regime_is_stage2(mmu_idx)) { | ||
162 | result->cacheattrs.is_s2_format = true; | ||
385 | -- | 163 | -- |
386 | 2.25.1 | 164 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Drop zcr_no_el2_reginfo and merge the 3 registers into one array, | 3 | While Root and Realm may read and write data from other spaces, |
4 | now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped | 4 | neither may execute from other pa spaces. |
5 | while registering. | 5 | |
6 | This happens for Stage1 EL3, EL2, EL2&0, and Stage2 EL1&0. | ||
6 | 7 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-4-richard.henderson@linaro.org | 10 | Message-id: 20230620124418.805717-14-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | target/arm/helper.c | 55 ++++++++++++++------------------------------- | 13 | target/arm/ptw.c | 52 ++++++++++++++++++++++++++++++++++++++++++------ |
13 | 1 file changed, 17 insertions(+), 38 deletions(-) | 14 | 1 file changed, 46 insertions(+), 6 deletions(-) |
14 | 15 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 18 | --- a/target/arm/ptw.c |
18 | +++ b/target/arm/helper.c | 19 | +++ b/target/arm/ptw.c |
19 | @@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 20 | @@ -XXX,XX +XXX,XX @@ do_fault: |
21 | * @xn: XN (execute-never) bits | ||
22 | * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 | ||
23 | */ | ||
24 | -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) | ||
25 | +static int get_S2prot_noexecute(int s2ap) | ||
26 | { | ||
27 | int prot = 0; | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) | ||
30 | if (s2ap & 2) { | ||
31 | prot |= PAGE_WRITE; | ||
20 | } | 32 | } |
21 | } | 33 | + return prot; |
22 | 34 | +} | |
23 | -static const ARMCPRegInfo zcr_el1_reginfo = { | 35 | + |
24 | - .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | 36 | +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) |
25 | - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | 37 | +{ |
26 | - .access = PL1_RW, .type = ARM_CP_SVE, | 38 | + int prot = get_S2prot_noexecute(s2ap); |
27 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | 39 | |
28 | - .writefn = zcr_write, .raw_writefn = raw_write | 40 | if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { |
29 | -}; | 41 | switch (xn) { |
30 | - | 42 | @@ -XXX,XX +XXX,XX @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, |
31 | -static const ARMCPRegInfo zcr_el2_reginfo = { | 43 | } |
32 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
33 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
34 | - .access = PL2_RW, .type = ARM_CP_SVE, | ||
35 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | ||
36 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
37 | -}; | ||
38 | - | ||
39 | -static const ARMCPRegInfo zcr_no_el2_reginfo = { | ||
40 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
41 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
42 | - .access = PL2_RW, .type = ARM_CP_SVE, | ||
43 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore | ||
44 | -}; | ||
45 | - | ||
46 | -static const ARMCPRegInfo zcr_el3_reginfo = { | ||
47 | - .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
48 | - .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
49 | - .access = PL3_RW, .type = ARM_CP_SVE, | ||
50 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
51 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
52 | +static const ARMCPRegInfo zcr_reginfo[] = { | ||
53 | + { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | ||
54 | + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | ||
55 | + .access = PL1_RW, .type = ARM_CP_SVE, | ||
56 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | ||
57 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
58 | + { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
59 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
60 | + .access = PL2_RW, .type = ARM_CP_SVE, | ||
61 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | ||
62 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
63 | + { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
64 | + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
65 | + .access = PL3_RW, .type = ARM_CP_SVE, | ||
66 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
67 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
68 | }; | ||
69 | |||
70 | void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
71 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
72 | } | 44 | } |
73 | 45 | ||
74 | if (cpu_isar_feature(aa64_sve, cpu)) { | 46 | - if (out_pa == ARMSS_NonSecure && in_pa == ARMSS_Secure && |
75 | - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); | 47 | - (env->cp15.scr_el3 & SCR_SIF)) { |
76 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | 48 | - return prot_rw; |
77 | - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | 49 | + if (in_pa != out_pa) { |
78 | - } else { | 50 | + switch (in_pa) { |
79 | - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | 51 | + case ARMSS_Root: |
80 | - } | 52 | + /* |
81 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | 53 | + * R_ZWRVD: permission fault for insn fetched from non-Root, |
82 | - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | 54 | + * I_WWBFB: SIF has no effect in EL3. |
83 | - } | 55 | + */ |
84 | + define_arm_cp_regs(cpu, zcr_reginfo); | 56 | + return prot_rw; |
57 | + case ARMSS_Realm: | ||
58 | + /* | ||
59 | + * R_PKTDS: permission fault for insn fetched from non-Realm, | ||
60 | + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 | ||
61 | + * happens during any stage2 translation. | ||
62 | + */ | ||
63 | + switch (mmu_idx) { | ||
64 | + case ARMMMUIdx_E2: | ||
65 | + case ARMMMUIdx_E20_0: | ||
66 | + case ARMMMUIdx_E20_2: | ||
67 | + case ARMMMUIdx_E20_2_PAN: | ||
68 | + return prot_rw; | ||
69 | + default: | ||
70 | + break; | ||
71 | + } | ||
72 | + break; | ||
73 | + case ARMSS_Secure: | ||
74 | + if (env->cp15.scr_el3 & SCR_SIF) { | ||
75 | + return prot_rw; | ||
76 | + } | ||
77 | + break; | ||
78 | + default: | ||
79 | + /* Input NonSecure must have output NonSecure. */ | ||
80 | + g_assert_not_reached(); | ||
81 | + } | ||
85 | } | 82 | } |
86 | 83 | ||
87 | #ifdef TARGET_AARCH64 | 84 | /* TODO have_wxn should be replaced with |
85 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
86 | /* | ||
87 | * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. | ||
88 | * The bit remains ignored for other security states. | ||
89 | + * R_YMCSL: Executing an insn fetched from non-Realm causes | ||
90 | + * a stage2 permission fault. | ||
91 | */ | ||
92 | if (out_space == ARMSS_Realm && extract64(attrs, 55, 1)) { | ||
93 | out_space = ARMSS_NonSecure; | ||
94 | + result->f.prot = get_S2prot_noexecute(ap); | ||
95 | + } else { | ||
96 | + xn = extract64(attrs, 53, 2); | ||
97 | + result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); | ||
98 | } | ||
99 | - xn = extract64(attrs, 53, 2); | ||
100 | - result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); | ||
101 | } else { | ||
102 | int nse, ns = extract32(attrs, 5, 1); | ||
103 | switch (out_space) { | ||
88 | -- | 104 | -- |
89 | 2.25.1 | 105 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns branch speculation, which TCG does | 3 | Do not provide a fast-path for physical addresses, |
4 | not implement. Thus we can trivially enable this feature. | 4 | as those will need to be validated for GPC. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-20-richard.henderson@linaro.org | 8 | Message-id: 20230620124418.805717-15-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 11 | target/arm/ptw.c | 44 +++++++++++++++++--------------------------- |
12 | target/arm/cpu64.c | 1 + | 12 | 1 file changed, 17 insertions(+), 27 deletions(-) |
13 | target/arm/cpu_tcg.c | 1 + | ||
14 | 3 files changed, 3 insertions(+) | ||
15 | 13 | ||
16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/emulation.rst | 16 | --- a/target/arm/ptw.c |
19 | +++ b/docs/system/arm/emulation.rst | 17 | +++ b/target/arm/ptw.c |
20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 18 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
21 | - FEAT_BBM at level 2 (Translation table break-before-make levels) | 19 | * From gdbstub, do not use softmmu so that we don't modify the |
22 | - FEAT_BF16 (AArch64 BFloat16 instructions) | 20 | * state of the cpu at all, including softmmu tlb contents. |
23 | - FEAT_BTI (Branch Target Identification) | 21 | */ |
24 | +- FEAT_CSV2 (Cache speculation variant 2) | 22 | - if (regime_is_stage2(s2_mmu_idx)) { |
25 | - FEAT_DIT (Data Independent Timing instructions) | 23 | - S1Translate s2ptw = { |
26 | - FEAT_DPB (DC CVAP instruction) | 24 | - .in_mmu_idx = s2_mmu_idx, |
27 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 25 | - .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), |
28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 26 | - .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, |
29 | index XXXXXXX..XXXXXXX 100644 | 27 | - .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure |
30 | --- a/target/arm/cpu64.c | 28 | - : space == ARMSS_Realm ? ARMSS_Realm |
31 | +++ b/target/arm/cpu64.c | 29 | - : ARMSS_NonSecure), |
32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 30 | - .in_debug = true, |
33 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | 31 | - }; |
34 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | 32 | - GetPhysAddrResult s2 = { }; |
35 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | 33 | + S1Translate s2ptw = { |
36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ | 34 | + .in_mmu_idx = s2_mmu_idx, |
37 | cpu->isar.id_aa64pfr0 = t; | 35 | + .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), |
38 | 36 | + .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, | |
39 | t = cpu->isar.id_aa64pfr1; | 37 | + .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure |
40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 38 | + : space == ARMSS_Realm ? ARMSS_Realm |
41 | index XXXXXXX..XXXXXXX 100644 | 39 | + : ARMSS_NonSecure), |
42 | --- a/target/arm/cpu_tcg.c | 40 | + .in_debug = true, |
43 | +++ b/target/arm/cpu_tcg.c | 41 | + }; |
44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 42 | + GetPhysAddrResult s2 = { }; |
45 | cpu->isar.id_mmfr4 = t; | 43 | |
46 | 44 | - if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, | |
47 | t = cpu->isar.id_pfr0; | 45 | - false, &s2, fi)) { |
48 | + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ | 46 | - goto fail; |
49 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | 47 | - } |
50 | t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ | 48 | - ptw->out_phys = s2.f.phys_addr; |
51 | cpu->isar.id_pfr0 = t; | 49 | - pte_attrs = s2.cacheattrs.attrs; |
50 | - ptw->out_secure = s2.f.attrs.secure; | ||
51 | - ptw->out_space = s2.f.attrs.space; | ||
52 | - } else { | ||
53 | - /* Regime is physical. */ | ||
54 | - ptw->out_phys = addr; | ||
55 | - pte_attrs = 0; | ||
56 | - ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; | ||
57 | - ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure | ||
58 | - : space == ARMSS_Realm ? ARMSS_Realm | ||
59 | - : ARMSS_NonSecure); | ||
60 | + if (get_phys_addr_with_struct(env, &s2ptw, addr, | ||
61 | + MMU_DATA_LOAD, &s2, fi)) { | ||
62 | + goto fail; | ||
63 | } | ||
64 | + ptw->out_phys = s2.f.phys_addr; | ||
65 | + pte_attrs = s2.cacheattrs.attrs; | ||
66 | ptw->out_host = NULL; | ||
67 | ptw->out_rw = false; | ||
68 | + ptw->out_secure = s2.f.attrs.secure; | ||
69 | + ptw->out_space = s2.f.attrs.space; | ||
70 | } else { | ||
71 | #ifdef CONFIG_TCG | ||
72 | CPUTLBEntryFull *full; | ||
52 | -- | 73 | -- |
53 | 2.25.1 | 74 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns changes to the External Debug interface, | 3 | Instead of passing this to get_phys_addr_lpae, stash it |
4 | with Secure and Non-secure access to the debug registers, and all | 4 | in the S1Translate structure. |
5 | of it is outside the scope of QEMU. Indicating support for this | ||
6 | is mandatory with FEAT_SEL2, which we do implement. | ||
7 | 5 | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20220506180242.216785-13-richard.henderson@linaro.org | 9 | Message-id: 20230620124418.805717-16-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | docs/system/arm/emulation.rst | 1 + | 12 | target/arm/ptw.c | 27 ++++++++++++--------------- |
14 | target/arm/cpu64.c | 2 +- | 13 | 1 file changed, 12 insertions(+), 15 deletions(-) |
15 | target/arm/cpu_tcg.c | 4 ++-- | ||
16 | 3 files changed, 4 insertions(+), 3 deletions(-) | ||
17 | 14 | ||
18 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 15 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
19 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/docs/system/arm/emulation.rst | 17 | --- a/target/arm/ptw.c |
21 | +++ b/docs/system/arm/emulation.rst | 18 | +++ b/target/arm/ptw.c |
22 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 19 | @@ -XXX,XX +XXX,XX @@ typedef struct S1Translate { |
23 | - FEAT_DIT (Data Independent Timing instructions) | 20 | ARMSecuritySpace in_space; |
24 | - FEAT_DPB (DC CVAP instruction) | 21 | bool in_secure; |
25 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 22 | bool in_debug; |
26 | +- FEAT_Debugv8p4 (Debug changes for v8.4) | 23 | + /* |
27 | - FEAT_DotProd (Advanced SIMD dot product instructions) | 24 | + * If this is stage 2 of a stage 1+2 page table walk, then this must |
28 | - FEAT_FCMA (Floating-point complex number instructions) | 25 | + * be true if stage 1 is an EL0 access; otherwise this is ignored. |
29 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | 26 | + * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. |
30 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 27 | + */ |
31 | index XXXXXXX..XXXXXXX 100644 | 28 | + bool in_s1_is_el0; |
32 | --- a/target/arm/cpu64.c | 29 | bool out_secure; |
33 | +++ b/target/arm/cpu64.c | 30 | bool out_rw; |
34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 31 | bool out_be; |
35 | cpu->isar.id_aa64zfr0 = t; | 32 | @@ -XXX,XX +XXX,XX @@ typedef struct S1Translate { |
36 | 33 | } S1Translate; | |
37 | t = cpu->isar.id_aa64dfr0; | 34 | |
38 | - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ | 35 | static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
39 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ | 36 | - uint64_t address, |
40 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | 37 | - MMUAccessType access_type, bool s1_is_el0, |
41 | cpu->isar.id_aa64dfr0 = t; | 38 | + uint64_t address, MMUAccessType access_type, |
42 | 39 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi); | |
43 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 40 | |
44 | index XXXXXXX..XXXXXXX 100644 | 41 | static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
45 | --- a/target/arm/cpu_tcg.c | 42 | @@ -XXX,XX +XXX,XX @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, |
46 | +++ b/target/arm/cpu_tcg.c | 43 | * @ptw: Current and next stage parameters for the walk. |
47 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 44 | * @address: virtual address to get physical address for |
48 | cpu->isar.id_pfr2 = t; | 45 | * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH |
49 | 46 | - * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2 | |
50 | t = cpu->isar.id_dfr0; | 47 | - * (so this is a stage 2 page table walk), |
51 | - t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | 48 | - * must be true if this is stage 2 of a stage 1+2 |
52 | - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | 49 | - * walk for an EL0 access. If @mmu_idx is anything else, |
53 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ | 50 | - * @s1_is_el0 is ignored. |
54 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ | 51 | * @result: set on translation success, |
55 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | 52 | * @fi: set to fault info if the translation fails |
56 | cpu->isar.id_dfr0 = t; | 53 | */ |
57 | } | 54 | static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
55 | uint64_t address, | ||
56 | - MMUAccessType access_type, bool s1_is_el0, | ||
57 | + MMUAccessType access_type, | ||
58 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) | ||
59 | { | ||
60 | ARMCPU *cpu = env_archcpu(env); | ||
61 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
62 | result->f.prot = get_S2prot_noexecute(ap); | ||
63 | } else { | ||
64 | xn = extract64(attrs, 53, 2); | ||
65 | - result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); | ||
66 | + result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0); | ||
67 | } | ||
68 | } else { | ||
69 | int nse, ns = extract32(attrs, 5, 1); | ||
70 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
71 | bool ret, ipa_secure; | ||
72 | ARMCacheAttrs cacheattrs1; | ||
73 | ARMSecuritySpace ipa_space; | ||
74 | - bool is_el0; | ||
75 | uint64_t hcr; | ||
76 | |||
77 | ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); | ||
78 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
79 | ipa_secure = result->f.attrs.secure; | ||
80 | ipa_space = result->f.attrs.space; | ||
81 | |||
82 | - is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; | ||
83 | + ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; | ||
84 | ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
85 | ptw->in_secure = ipa_secure; | ||
86 | ptw->in_space = ipa_space; | ||
87 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
88 | ret = get_phys_addr_pmsav8(env, ipa, access_type, | ||
89 | ptw->in_mmu_idx, is_secure, result, fi); | ||
90 | } else { | ||
91 | - ret = get_phys_addr_lpae(env, ptw, ipa, access_type, | ||
92 | - is_el0, result, fi); | ||
93 | + ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); | ||
94 | } | ||
95 | fi->s2addr = ipa; | ||
96 | |||
97 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
98 | } | ||
99 | |||
100 | if (regime_using_lpae_format(env, mmu_idx)) { | ||
101 | - return get_phys_addr_lpae(env, ptw, address, access_type, false, | ||
102 | - result, fi); | ||
103 | + return get_phys_addr_lpae(env, ptw, address, access_type, result, fi); | ||
104 | } else if (arm_feature(env, ARM_FEATURE_V7) || | ||
105 | regime_sctlr(env, mmu_idx) & SCTLR_XP) { | ||
106 | return get_phys_addr_v6(env, ptw, address, access_type, result, fi); | ||
58 | -- | 107 | -- |
59 | 2.25.1 | 108 | 2.34.1 |
109 | |||
110 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This feature is AArch64 only, and applies to physical SErrors, | 3 | This fixes a bug in which we failed to initialize |
4 | which QEMU does not implement, thus the feature is a nop. | 4 | the result attributes properly after the memset. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-19-richard.henderson@linaro.org | 9 | Message-id: 20230620124418.805717-17-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 12 | target/arm/ptw.c | 11 +---------- |
12 | target/arm/cpu64.c | 1 + | 13 | 1 file changed, 1 insertion(+), 10 deletions(-) |
13 | 2 files changed, 2 insertions(+) | ||
14 | 14 | ||
15 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 15 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/docs/system/arm/emulation.rst | 17 | --- a/target/arm/ptw.c |
18 | +++ b/docs/system/arm/emulation.rst | 18 | +++ b/target/arm/ptw.c |
19 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 19 | @@ -XXX,XX +XXX,XX @@ typedef struct S1Translate { |
20 | - FEAT_FlagM2 (Enhancements to flag manipulation instructions) | 20 | void *out_host; |
21 | - FEAT_HPDS (Hierarchical permission disables) | 21 | } S1Translate; |
22 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) | 22 | |
23 | +- FEAT_IESB (Implicit error synchronization event) | 23 | -static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
24 | - FEAT_JSCVT (JavaScript conversion instructions) | 24 | - uint64_t address, MMUAccessType access_type, |
25 | - FEAT_LOR (Limited ordering regions) | 25 | - GetPhysAddrResult *result, ARMMMUFaultInfo *fi); |
26 | - FEAT_LPA (Large Physical Address space) | 26 | - |
27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 27 | static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
28 | index XXXXXXX..XXXXXXX 100644 | 28 | target_ulong address, |
29 | --- a/target/arm/cpu64.c | 29 | MMUAccessType access_type, |
30 | +++ b/target/arm/cpu64.c | 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, |
31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 31 | cacheattrs1 = result->cacheattrs; |
32 | t = cpu->isar.id_aa64mmfr2; | 32 | memset(result, 0, sizeof(*result)); |
33 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | 33 | |
34 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | 34 | - if (arm_feature(env, ARM_FEATURE_PMSA)) { |
35 | + t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ | 35 | - ret = get_phys_addr_pmsav8(env, ipa, access_type, |
36 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | 36 | - ptw->in_mmu_idx, is_secure, result, fi); |
37 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | 37 | - } else { |
38 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | 38 | - ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); |
39 | - } | ||
40 | + ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi); | ||
41 | fi->s2addr = ipa; | ||
42 | |||
43 | /* Combine the S1 and S2 perms. */ | ||
39 | -- | 44 | -- |
40 | 2.25.1 | 45 | 2.34.1 |
46 | |||
47 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable the n1 for virt and sbsa board use. | 3 | The function takes the fields as filled in by |
4 | the Arm ARM pseudocode for TakeGPCException. | ||
4 | 5 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-25-richard.henderson@linaro.org | 8 | Message-id: 20230620124418.805717-18-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | docs/system/arm/virt.rst | 1 + | 11 | target/arm/syndrome.h | 10 ++++++++++ |
11 | hw/arm/sbsa-ref.c | 1 + | 12 | 1 file changed, 10 insertions(+) |
12 | hw/arm/virt.c | 1 + | ||
13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 69 insertions(+) | ||
15 | 13 | ||
16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 14 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/virt.rst | 16 | --- a/target/arm/syndrome.h |
19 | +++ b/docs/system/arm/virt.rst | 17 | +++ b/target/arm/syndrome.h |
20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | 18 | @@ -XXX,XX +XXX,XX @@ enum arm_exception_class { |
21 | - ``cortex-a76`` (64-bit) | 19 | EC_SVEACCESSTRAP = 0x19, |
22 | - ``a64fx`` (64-bit) | 20 | EC_ERETTRAP = 0x1a, |
23 | - ``host`` (with KVM only) | 21 | EC_SMETRAP = 0x1d, |
24 | +- ``neoverse-n1`` (64-bit) | 22 | + EC_GPC = 0x1e, |
25 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | 23 | EC_INSNABORT = 0x20, |
26 | 24 | EC_INSNABORT_SAME_EL = 0x21, | |
27 | Note that the default is ``cortex-a15``, so for an AArch64 guest you must | 25 | EC_PCALIGNMENT = 0x22, |
28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | 26 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) |
29 | index XXXXXXX..XXXXXXX 100644 | 27 | (cv << 24) | (cond << 20) | rm; |
30 | --- a/hw/arm/sbsa-ref.c | ||
31 | +++ b/hw/arm/sbsa-ref.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = { | ||
33 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
34 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
35 | ARM_CPU_TYPE_NAME("cortex-a76"), | ||
36 | + ARM_CPU_TYPE_NAME("neoverse-n1"), | ||
37 | ARM_CPU_TYPE_NAME("max"), | ||
38 | }; | ||
39 | |||
40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/virt.c | ||
43 | +++ b/hw/arm/virt.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | ||
45 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
46 | ARM_CPU_TYPE_NAME("cortex-a76"), | ||
47 | ARM_CPU_TYPE_NAME("a64fx"), | ||
48 | + ARM_CPU_TYPE_NAME("neoverse-n1"), | ||
49 | ARM_CPU_TYPE_NAME("host"), | ||
50 | ARM_CPU_TYPE_NAME("max"), | ||
51 | }; | ||
52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/cpu64.c | ||
55 | +++ b/target/arm/cpu64.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj) | ||
57 | cpu->isar.mvfr2 = 0x00000043; | ||
58 | } | 28 | } |
59 | 29 | ||
60 | +static void aarch64_neoverse_n1_initfn(Object *obj) | 30 | +static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, |
31 | + int cm, int s1ptw, int wnr, int fsc) | ||
61 | +{ | 32 | +{ |
62 | + ARMCPU *cpu = ARM_CPU(obj); | 33 | + /* TODO: FEAT_NV2 adds VNCR */ |
63 | + | 34 | + return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) |
64 | + cpu->dtb_compatible = "arm,neoverse-n1"; | 35 | + | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) |
65 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 36 | + | (wnr << 6) | fsc; |
66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
73 | + | ||
74 | + /* Ordered by B2.4 AArch64 registers by functional group */ | ||
75 | + cpu->clidr = 0x82000023; | ||
76 | + cpu->ctr = 0x8444c004; | ||
77 | + cpu->dcz_blocksize = 4; | ||
78 | + cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; | ||
79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | ||
80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | ||
81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; | ||
82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | ||
83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | ||
84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | ||
85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; | ||
86 | + cpu->id_afr0 = 0x00000000; | ||
87 | + cpu->isar.id_dfr0 = 0x04010088; | ||
88 | + cpu->isar.id_isar0 = 0x02101110; | ||
89 | + cpu->isar.id_isar1 = 0x13112111; | ||
90 | + cpu->isar.id_isar2 = 0x21232042; | ||
91 | + cpu->isar.id_isar3 = 0x01112131; | ||
92 | + cpu->isar.id_isar4 = 0x00010142; | ||
93 | + cpu->isar.id_isar5 = 0x01011121; | ||
94 | + cpu->isar.id_isar6 = 0x00000010; | ||
95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
103 | + cpu->midr = 0x414fd0c1; /* r4p1 */ | ||
104 | + cpu->revidr = 0; | ||
105 | + | ||
106 | + /* From B2.23 CCSIDR_EL1 */ | ||
107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | ||
108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | ||
109 | + cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ | ||
110 | + | ||
111 | + /* From B2.98 SCTLR_EL3 */ | ||
112 | + cpu->reset_sctlr = 0x30c50838; | ||
113 | + | ||
114 | + /* From B4.23 ICH_VTR_EL2 */ | ||
115 | + cpu->gic_num_lrs = 4; | ||
116 | + cpu->gic_vpribits = 5; | ||
117 | + cpu->gic_vprebits = 5; | ||
118 | + | ||
119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | ||
120 | + cpu->isar.mvfr0 = 0x10110222; | ||
121 | + cpu->isar.mvfr1 = 0x13211111; | ||
122 | + cpu->isar.mvfr2 = 0x00000043; | ||
123 | +} | 37 | +} |
124 | + | 38 | + |
125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | 39 | static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) |
126 | { | 40 | { |
127 | /* | 41 | return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) |
128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | ||
129 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | ||
130 | { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | ||
131 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | ||
132 | + { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, | ||
133 | { .name = "max", .initfn = aarch64_max_initfn }, | ||
134 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | ||
135 | { .name = "host", .initfn = aarch64_host_initfn }, | ||
136 | -- | 42 | -- |
137 | 2.25.1 | 43 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Virtual SError exceptions are raised by setting HCR_EL2.VSE, | 3 | Handle GPC Fault types in arm_deliver_fault, reporting as |
4 | and are routed to EL1 just like other virtual exceptions. | 4 | either a GPC exception at EL3, or falling through to insn |
5 | or data aborts at various exception levels. | ||
5 | 6 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-16-richard.henderson@linaro.org | 9 | Message-id: 20230620124418.805717-19-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | target/arm/cpu.h | 2 ++ | 12 | target/arm/cpu.h | 1 + |
12 | target/arm/internals.h | 8 ++++++++ | 13 | target/arm/internals.h | 27 +++++++++++ |
13 | target/arm/syndrome.h | 5 +++++ | 14 | target/arm/helper.c | 5 ++ |
14 | target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- | 15 | target/arm/tcg/tlb_helper.c | 96 +++++++++++++++++++++++++++++++++++-- |
15 | target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- | 16 | 4 files changed, 126 insertions(+), 3 deletions(-) |
16 | 5 files changed, 91 insertions(+), 2 deletions(-) | ||
17 | 17 | ||
18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
19 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/cpu.h | 20 | --- a/target/arm/cpu.h |
21 | +++ b/target/arm/cpu.h | 21 | +++ b/target/arm/cpu.h |
22 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ |
23 | #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ | ||
24 | #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ | 23 | #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ |
25 | #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ | 24 | #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ |
26 | +#define EXCP_VSERR 24 | 25 | #define EXCP_VSERR 24 |
26 | +#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ | ||
27 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ | 27 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ |
28 | 28 | ||
29 | #define ARMV7M_EXCP_RESET 1 | 29 | #define ARMV7M_EXCP_RESET 1 |
30 | @@ -XXX,XX +XXX,XX @@ enum { | ||
31 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | ||
32 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 | ||
33 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 | ||
34 | +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 | ||
35 | |||
36 | /* The usual mapping for an AArch64 system register to its AArch32 | ||
37 | * counterpart is for the 32 bit world to have access to the lower | ||
38 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 30 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
39 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
40 | --- a/target/arm/internals.h | 32 | --- a/target/arm/internals.h |
41 | +++ b/target/arm/internals.h | 33 | +++ b/target/arm/internals.h |
42 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu); | 34 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMFaultType { |
43 | */ | 35 | ARMFault_ICacheMaint, |
44 | void arm_cpu_update_vfiq(ARMCPU *cpu); | 36 | ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ |
45 | 37 | ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ | |
46 | +/** | 38 | + ARMFault_GPCFOnWalk, |
47 | + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit | 39 | + ARMFault_GPCFOnOutput, |
48 | + * | 40 | } ARMFaultType; |
49 | + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, | 41 | |
50 | + * following a change to the HCR_EL2.VSE bit. | 42 | +typedef enum ARMGPCF { |
51 | + */ | 43 | + GPCF_None, |
52 | +void arm_cpu_update_vserr(ARMCPU *cpu); | 44 | + GPCF_AddressSize, |
45 | + GPCF_Walk, | ||
46 | + GPCF_EABT, | ||
47 | + GPCF_Fail, | ||
48 | +} ARMGPCF; | ||
53 | + | 49 | + |
54 | /** | 50 | /** |
55 | * arm_mmu_idx_el: | 51 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault |
56 | * @env: The cpu environment | 52 | * @type: Type of fault |
57 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h | 53 | + * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}. |
58 | index XXXXXXX..XXXXXXX 100644 | 54 | * @level: Table walk level (for translation, access flag and permission faults) |
59 | --- a/target/arm/syndrome.h | 55 | * @domain: Domain of the fault address (for non-LPAE CPUs only) |
60 | +++ b/target/arm/syndrome.h | 56 | * @s2addr: Address that caused a fault at stage 2 |
61 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void) | 57 | + * @paddr: physical address that caused a fault for gpc |
62 | return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; | 58 | + * @paddr_space: physical address space that caused a fault for gpc |
59 | * @stage2: True if we faulted at stage 2 | ||
60 | * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk | ||
61 | * @s1ns: True if we faulted on a non-secure IPA while in secure state | ||
62 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMFaultType { | ||
63 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | ||
64 | struct ARMMMUFaultInfo { | ||
65 | ARMFaultType type; | ||
66 | + ARMGPCF gpcf; | ||
67 | target_ulong s2addr; | ||
68 | + target_ulong paddr; | ||
69 | + ARMSecuritySpace paddr_space; | ||
70 | int level; | ||
71 | int domain; | ||
72 | bool stage2; | ||
73 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) | ||
74 | case ARMFault_Exclusive: | ||
75 | fsc = 0x35; | ||
76 | break; | ||
77 | + case ARMFault_GPCFOnWalk: | ||
78 | + assert(fi->level >= -1 && fi->level <= 3); | ||
79 | + if (fi->level < 0) { | ||
80 | + fsc = 0b100011; | ||
81 | + } else { | ||
82 | + fsc = 0b100100 | fi->level; | ||
83 | + } | ||
84 | + break; | ||
85 | + case ARMFault_GPCFOnOutput: | ||
86 | + fsc = 0b101000; | ||
87 | + break; | ||
88 | default: | ||
89 | /* Other faults can't occur in a context that requires a | ||
90 | * long-format status code. | ||
91 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/target/arm/helper.c | ||
94 | +++ b/target/arm/helper.c | ||
95 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs) | ||
96 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | ||
97 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", | ||
98 | [EXCP_VSERR] = "Virtual SERR", | ||
99 | + [EXCP_GPC] = "Granule Protection Check", | ||
100 | }; | ||
101 | |||
102 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | ||
103 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
104 | } | ||
105 | |||
106 | switch (cs->exception_index) { | ||
107 | + case EXCP_GPC: | ||
108 | + qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", | ||
109 | + env->cp15.mfar_el3); | ||
110 | + /* fall through */ | ||
111 | case EXCP_PREFETCH_ABORT: | ||
112 | case EXCP_DATA_ABORT: | ||
113 | /* | ||
114 | diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c | ||
115 | index XXXXXXX..XXXXXXX 100644 | ||
116 | --- a/target/arm/tcg/tlb_helper.c | ||
117 | +++ b/target/arm/tcg/tlb_helper.c | ||
118 | @@ -XXX,XX +XXX,XX @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, | ||
119 | return fsr; | ||
63 | } | 120 | } |
64 | 121 | ||
65 | +static inline uint32_t syn_serror(uint32_t extra) | 122 | +static bool report_as_gpc_exception(ARMCPU *cpu, int current_el, |
123 | + ARMMMUFaultInfo *fi) | ||
66 | +{ | 124 | +{ |
67 | + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; | 125 | + bool ret; |
126 | + | ||
127 | + switch (fi->gpcf) { | ||
128 | + case GPCF_None: | ||
129 | + return false; | ||
130 | + case GPCF_AddressSize: | ||
131 | + case GPCF_Walk: | ||
132 | + case GPCF_EABT: | ||
133 | + /* R_PYTGX: GPT faults are reported as GPC. */ | ||
134 | + ret = true; | ||
135 | + break; | ||
136 | + case GPCF_Fail: | ||
137 | + /* | ||
138 | + * R_BLYPM: A GPF at EL3 is reported as insn or data abort. | ||
139 | + * R_VBZMW, R_LXHQR: A GPF at EL[0-2] is reported as a GPC | ||
140 | + * if SCR_EL3.GPF is set, otherwise an insn or data abort. | ||
141 | + */ | ||
142 | + ret = (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el != 3; | ||
143 | + break; | ||
144 | + default: | ||
145 | + g_assert_not_reached(); | ||
146 | + } | ||
147 | + | ||
148 | + assert(cpu_isar_feature(aa64_rme, cpu)); | ||
149 | + assert(fi->type == ARMFault_GPCFOnWalk || | ||
150 | + fi->type == ARMFault_GPCFOnOutput); | ||
151 | + if (fi->gpcf == GPCF_AddressSize) { | ||
152 | + assert(fi->level == 0); | ||
153 | + } else { | ||
154 | + assert(fi->level >= 0 && fi->level <= 1); | ||
155 | + } | ||
156 | + | ||
157 | + return ret; | ||
68 | +} | 158 | +} |
69 | + | 159 | + |
70 | #endif /* TARGET_ARM_SYNDROME_H */ | 160 | +static unsigned encode_gpcsc(ARMMMUFaultInfo *fi) |
71 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 161 | +{ |
72 | index XXXXXXX..XXXXXXX 100644 | 162 | + static uint8_t const gpcsc[] = { |
73 | --- a/target/arm/cpu.c | 163 | + [GPCF_AddressSize] = 0b000000, |
74 | +++ b/target/arm/cpu.c | 164 | + [GPCF_Walk] = 0b000100, |
75 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs) | 165 | + [GPCF_Fail] = 0b001100, |
76 | return (cpu->power_state != PSCI_OFF) | 166 | + [GPCF_EABT] = 0b010100, |
77 | && cs->interrupt_request & | 167 | + }; |
78 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | 168 | + |
79 | - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | 169 | + /* Note that we've validated fi->gpcf and fi->level above. */ |
80 | + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | 170 | + return gpcsc[fi->gpcf] | fi->level; |
81 | | CPU_INTERRUPT_EXITTB); | 171 | +} |
82 | } | 172 | + |
83 | 173 | static G_NORETURN | |
84 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | 174 | void arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
85 | return false; | 175 | MMUAccessType access_type, |
86 | } | 176 | int mmu_idx, ARMMMUFaultInfo *fi) |
87 | return !(env->daif & PSTATE_I); | 177 | { |
88 | + case EXCP_VSERR: | 178 | CPUARMState *env = &cpu->env; |
89 | + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { | 179 | - int target_el; |
90 | + /* VIRQs are only taken when hypervized. */ | 180 | + int target_el = exception_target_el(env); |
91 | + return false; | 181 | + int current_el = arm_current_el(env); |
182 | bool same_el; | ||
183 | uint32_t syn, exc, fsr, fsc; | ||
184 | |||
185 | - target_el = exception_target_el(env); | ||
186 | + if (report_as_gpc_exception(cpu, current_el, fi)) { | ||
187 | + target_el = 3; | ||
188 | + | ||
189 | + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); | ||
190 | + | ||
191 | + syn = syn_gpc(fi->stage2 && fi->type == ARMFault_GPCFOnWalk, | ||
192 | + access_type == MMU_INST_FETCH, | ||
193 | + encode_gpcsc(fi), 0, fi->s1ptw, | ||
194 | + access_type == MMU_DATA_STORE, fsc); | ||
195 | + | ||
196 | + env->cp15.mfar_el3 = fi->paddr; | ||
197 | + switch (fi->paddr_space) { | ||
198 | + case ARMSS_Secure: | ||
199 | + break; | ||
200 | + case ARMSS_NonSecure: | ||
201 | + env->cp15.mfar_el3 |= R_MFAR_NS_MASK; | ||
202 | + break; | ||
203 | + case ARMSS_Root: | ||
204 | + env->cp15.mfar_el3 |= R_MFAR_NSE_MASK; | ||
205 | + break; | ||
206 | + case ARMSS_Realm: | ||
207 | + env->cp15.mfar_el3 |= R_MFAR_NSE_MASK | R_MFAR_NS_MASK; | ||
208 | + break; | ||
209 | + default: | ||
210 | + g_assert_not_reached(); | ||
92 | + } | 211 | + } |
93 | + return !(env->daif & PSTATE_A); | 212 | + |
94 | default: | 213 | + exc = EXCP_GPC; |
95 | g_assert_not_reached(); | 214 | + goto do_raise; |
96 | } | 215 | + } |
97 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | 216 | + |
98 | goto found; | 217 | + /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */ |
218 | + if (fi->gpcf == GPCF_Fail && target_el < 2) { | ||
219 | + if (arm_hcr_el2_eff(env) & HCR_GPF) { | ||
220 | + target_el = 2; | ||
221 | + } | ||
222 | + } | ||
223 | + | ||
224 | if (fi->stage2) { | ||
225 | target_el = 2; | ||
226 | env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; | ||
227 | @@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, | ||
228 | env->cp15.hpfar_el2 |= HPFAR_NS; | ||
99 | } | 229 | } |
100 | } | 230 | } |
101 | + if (interrupt_request & CPU_INTERRUPT_VSERR) { | 231 | - same_el = (arm_current_el(env) == target_el); |
102 | + excp_idx = EXCP_VSERR; | 232 | |
103 | + target_el = 1; | 233 | + same_el = current_el == target_el; |
104 | + if (arm_excp_unmasked(cs, excp_idx, target_el, | 234 | fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); |
105 | + cur_el, secure, hcr_el2)) { | 235 | |
106 | + /* Taking a virtual abort clears HCR_EL2.VSE */ | 236 | if (access_type == MMU_INST_FETCH) { |
107 | + env->cp15.hcr_el2 &= ~HCR_VSE; | 237 | @@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
108 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | 238 | exc = EXCP_DATA_ABORT; |
109 | + goto found; | ||
110 | + } | ||
111 | + } | ||
112 | return false; | ||
113 | |||
114 | found: | ||
115 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu) | ||
116 | } | 239 | } |
117 | } | 240 | |
118 | 241 | + do_raise: | |
119 | +void arm_cpu_update_vserr(ARMCPU *cpu) | 242 | env->exception.vaddress = addr; |
120 | +{ | 243 | env->exception.fsr = fsr; |
121 | + /* | 244 | raise_exception(env, exc, syn, target_el); |
122 | + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. | ||
123 | + */ | ||
124 | + CPUARMState *env = &cpu->env; | ||
125 | + CPUState *cs = CPU(cpu); | ||
126 | + | ||
127 | + bool new_state = env->cp15.hcr_el2 & HCR_VSE; | ||
128 | + | ||
129 | + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { | ||
130 | + if (new_state) { | ||
131 | + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
132 | + } else { | ||
133 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
134 | + } | ||
135 | + } | ||
136 | +} | ||
137 | + | ||
138 | #ifndef CONFIG_USER_ONLY | ||
139 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | ||
140 | { | ||
141 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/target/arm/helper.c | ||
144 | +++ b/target/arm/helper.c | ||
145 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
146 | } | ||
147 | } | ||
148 | |||
149 | - /* External aborts are not possible in QEMU so A bit is always clear */ | ||
150 | + if (hcr_el2 & HCR_AMO) { | ||
151 | + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { | ||
152 | + ret |= CPSR_A; | ||
153 | + } | ||
154 | + } | ||
155 | + | ||
156 | return ret; | ||
157 | } | ||
158 | |||
159 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
160 | g_assert(qemu_mutex_iothread_locked()); | ||
161 | arm_cpu_update_virq(cpu); | ||
162 | arm_cpu_update_vfiq(cpu); | ||
163 | + arm_cpu_update_vserr(cpu); | ||
164 | } | ||
165 | |||
166 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
167 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs) | ||
168 | [EXCP_LSERR] = "v8M LSERR UsageFault", | ||
169 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | ||
170 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", | ||
171 | + [EXCP_VSERR] = "Virtual SERR", | ||
172 | }; | ||
173 | |||
174 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | ||
175 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) | ||
176 | mask = CPSR_A | CPSR_I | CPSR_F; | ||
177 | offset = 4; | ||
178 | break; | ||
179 | + case EXCP_VSERR: | ||
180 | + { | ||
181 | + /* | ||
182 | + * Note that this is reported as a data abort, but the DFAR | ||
183 | + * has an UNKNOWN value. Construct the SError syndrome from | ||
184 | + * AET and ExT fields. | ||
185 | + */ | ||
186 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; | ||
187 | + | ||
188 | + if (extended_addresses_enabled(env)) { | ||
189 | + env->exception.fsr = arm_fi_to_lfsc(&fi); | ||
190 | + } else { | ||
191 | + env->exception.fsr = arm_fi_to_sfsc(&fi); | ||
192 | + } | ||
193 | + env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; | ||
194 | + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); | ||
195 | + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", | ||
196 | + env->exception.fsr); | ||
197 | + | ||
198 | + new_mode = ARM_CPU_MODE_ABT; | ||
199 | + addr = 0x10; | ||
200 | + mask = CPSR_A | CPSR_I; | ||
201 | + offset = 8; | ||
202 | + } | ||
203 | + break; | ||
204 | case EXCP_SMC: | ||
205 | new_mode = ARM_CPU_MODE_MON; | ||
206 | addr = 0x08; | ||
207 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
208 | case EXCP_VFIQ: | ||
209 | addr += 0x100; | ||
210 | break; | ||
211 | + case EXCP_VSERR: | ||
212 | + addr += 0x180; | ||
213 | + /* Construct the SError syndrome from IDS and ISS fields. */ | ||
214 | + env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | ||
215 | + env->cp15.esr_el[new_el] = env->exception.syndrome; | ||
216 | + break; | ||
217 | default: | ||
218 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | ||
219 | } | ||
220 | -- | 245 | -- |
221 | 2.25.1 | 246 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable the a76 for virt and sbsa board use. | 3 | Place the check at the end of get_phys_addr_with_struct, |
4 | so that we check all physical results. | ||
4 | 5 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-24-richard.henderson@linaro.org | 8 | Message-id: 20230620124418.805717-20-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | docs/system/arm/virt.rst | 1 + | 11 | target/arm/ptw.c | 249 +++++++++++++++++++++++++++++++++++++++++++---- |
11 | hw/arm/sbsa-ref.c | 1 + | 12 | 1 file changed, 232 insertions(+), 17 deletions(-) |
12 | hw/arm/virt.c | 1 + | ||
13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 69 insertions(+) | ||
15 | 13 | ||
16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/virt.rst | 16 | --- a/target/arm/ptw.c |
19 | +++ b/docs/system/arm/virt.rst | 17 | +++ b/target/arm/ptw.c |
20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | 18 | @@ -XXX,XX +XXX,XX @@ typedef struct S1Translate { |
21 | - ``cortex-a53`` (64-bit) | 19 | void *out_host; |
22 | - ``cortex-a57`` (64-bit) | 20 | } S1Translate; |
23 | - ``cortex-a72`` (64-bit) | 21 | |
24 | +- ``cortex-a76`` (64-bit) | 22 | -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
25 | - ``a64fx`` (64-bit) | 23 | - target_ulong address, |
26 | - ``host`` (with KVM only) | 24 | - MMUAccessType access_type, |
27 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | 25 | - GetPhysAddrResult *result, |
28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | 26 | - ARMMMUFaultInfo *fi); |
29 | index XXXXXXX..XXXXXXX 100644 | 27 | +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, |
30 | --- a/hw/arm/sbsa-ref.c | 28 | + target_ulong address, |
31 | +++ b/hw/arm/sbsa-ref.c | 29 | + MMUAccessType access_type, |
32 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { | 30 | + GetPhysAddrResult *result, |
33 | static const char * const valid_cpus[] = { | 31 | + ARMMMUFaultInfo *fi); |
34 | ARM_CPU_TYPE_NAME("cortex-a57"), | 32 | + |
35 | ARM_CPU_TYPE_NAME("cortex-a72"), | 33 | +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, |
36 | + ARM_CPU_TYPE_NAME("cortex-a76"), | 34 | + target_ulong address, |
37 | ARM_CPU_TYPE_NAME("max"), | 35 | + MMUAccessType access_type, |
38 | }; | 36 | + GetPhysAddrResult *result, |
39 | 37 | + ARMMMUFaultInfo *fi); | |
40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 38 | |
41 | index XXXXXXX..XXXXXXX 100644 | 39 | /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ |
42 | --- a/hw/arm/virt.c | 40 | static const uint8_t pamax_map[] = { |
43 | +++ b/hw/arm/virt.c | 41 | @@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, |
44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | 42 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; |
45 | ARM_CPU_TYPE_NAME("cortex-a53"), | 43 | } |
46 | ARM_CPU_TYPE_NAME("cortex-a57"), | 44 | |
47 | ARM_CPU_TYPE_NAME("cortex-a72"), | 45 | +static bool granule_protection_check(CPUARMState *env, uint64_t paddress, |
48 | + ARM_CPU_TYPE_NAME("cortex-a76"), | 46 | + ARMSecuritySpace pspace, |
49 | ARM_CPU_TYPE_NAME("a64fx"), | 47 | + ARMMMUFaultInfo *fi) |
50 | ARM_CPU_TYPE_NAME("host"), | ||
51 | ARM_CPU_TYPE_NAME("max"), | ||
52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/cpu64.c | ||
55 | +++ b/target/arm/cpu64.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
57 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
58 | } | ||
59 | |||
60 | +static void aarch64_a76_initfn(Object *obj) | ||
61 | +{ | 48 | +{ |
62 | + ARMCPU *cpu = ARM_CPU(obj); | 49 | + MemTxAttrs attrs = { |
63 | + | 50 | + .secure = true, |
64 | + cpu->dtb_compatible = "arm,cortex-a76"; | 51 | + .space = ARMSS_Root, |
65 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 52 | + }; |
66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | 53 | + ARMCPU *cpu = env_archcpu(env); |
67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | 54 | + uint64_t gpccr = env->cp15.gpccr_el3; |
68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | 55 | + unsigned pps, pgs, l0gptsz, level = 0; |
69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | 56 | + uint64_t tableaddr, pps_mask, align, entry, index; |
70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | 57 | + AddressSpace *as; |
71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | 58 | + MemTxResult result; |
72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | 59 | + int gpi; |
73 | + | 60 | + |
74 | + /* Ordered by B2.4 AArch64 registers by functional group */ | 61 | + if (!FIELD_EX64(gpccr, GPCCR, GPC)) { |
75 | + cpu->clidr = 0x82000023; | 62 | + return true; |
76 | + cpu->ctr = 0x8444C004; | 63 | + } |
77 | + cpu->dcz_blocksize = 4; | 64 | + |
78 | + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; | 65 | + /* |
79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | 66 | + * GPC Priority 1 (R_GMGRR): |
80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | 67 | + * R_JWCSM: If the configuration of GPCCR_EL3 is invalid, |
81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; | 68 | + * the access fails as GPT walk fault at level 0. |
82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | 69 | + */ |
83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | 70 | + |
84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | 71 | + /* |
85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; | 72 | + * Configuration of PPS to a value exceeding the implemented |
86 | + cpu->id_afr0 = 0x00000000; | 73 | + * physical address size is invalid. |
87 | + cpu->isar.id_dfr0 = 0x04010088; | 74 | + */ |
88 | + cpu->isar.id_isar0 = 0x02101110; | 75 | + pps = FIELD_EX64(gpccr, GPCCR, PPS); |
89 | + cpu->isar.id_isar1 = 0x13112111; | 76 | + if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { |
90 | + cpu->isar.id_isar2 = 0x21232042; | 77 | + goto fault_walk; |
91 | + cpu->isar.id_isar3 = 0x01112131; | 78 | + } |
92 | + cpu->isar.id_isar4 = 0x00010142; | 79 | + pps = pamax_map[pps]; |
93 | + cpu->isar.id_isar5 = 0x01011121; | 80 | + pps_mask = MAKE_64BIT_MASK(0, pps); |
94 | + cpu->isar.id_isar6 = 0x00000010; | 81 | + |
95 | + cpu->isar.id_mmfr0 = 0x10201105; | 82 | + switch (FIELD_EX64(gpccr, GPCCR, SH)) { |
96 | + cpu->isar.id_mmfr1 = 0x40000000; | 83 | + case 0b10: /* outer shareable */ |
97 | + cpu->isar.id_mmfr2 = 0x01260000; | 84 | + break; |
98 | + cpu->isar.id_mmfr3 = 0x02122211; | 85 | + case 0b00: /* non-shareable */ |
99 | + cpu->isar.id_mmfr4 = 0x00021110; | 86 | + case 0b11: /* inner shareable */ |
100 | + cpu->isar.id_pfr0 = 0x10010131; | 87 | + /* Inner and Outer non-cacheable requires Outer shareable. */ |
101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | 88 | + if (FIELD_EX64(gpccr, GPCCR, ORGN) == 0 && |
102 | + cpu->isar.id_pfr2 = 0x00000011; | 89 | + FIELD_EX64(gpccr, GPCCR, IRGN) == 0) { |
103 | + cpu->midr = 0x414fd0b1; /* r4p1 */ | 90 | + goto fault_walk; |
104 | + cpu->revidr = 0; | 91 | + } |
105 | + | 92 | + break; |
106 | + /* From B2.18 CCSIDR_EL1 */ | 93 | + default: /* reserved */ |
107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | 94 | + goto fault_walk; |
108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | 95 | + } |
109 | + cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ | 96 | + |
110 | + | 97 | + switch (FIELD_EX64(gpccr, GPCCR, PGS)) { |
111 | + /* From B2.93 SCTLR_EL3 */ | 98 | + case 0b00: /* 4KB */ |
112 | + cpu->reset_sctlr = 0x30c50838; | 99 | + pgs = 12; |
113 | + | 100 | + break; |
114 | + /* From B4.23 ICH_VTR_EL2 */ | 101 | + case 0b01: /* 64KB */ |
115 | + cpu->gic_num_lrs = 4; | 102 | + pgs = 16; |
116 | + cpu->gic_vpribits = 5; | 103 | + break; |
117 | + cpu->gic_vprebits = 5; | 104 | + case 0b10: /* 16KB */ |
118 | + | 105 | + pgs = 14; |
119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | 106 | + break; |
120 | + cpu->isar.mvfr0 = 0x10110222; | 107 | + default: /* reserved */ |
121 | + cpu->isar.mvfr1 = 0x13211111; | 108 | + goto fault_walk; |
122 | + cpu->isar.mvfr2 = 0x00000043; | 109 | + } |
110 | + | ||
111 | + /* Note this field is read-only and fixed at reset. */ | ||
112 | + l0gptsz = 30 + FIELD_EX64(gpccr, GPCCR, L0GPTSZ); | ||
113 | + | ||
114 | + /* | ||
115 | + * GPC Priority 2: Secure, Realm or Root address exceeds PPS. | ||
116 | + * R_CPDSB: A NonSecure physical address input exceeding PPS | ||
117 | + * does not experience any fault. | ||
118 | + */ | ||
119 | + if (paddress & ~pps_mask) { | ||
120 | + if (pspace == ARMSS_NonSecure) { | ||
121 | + return true; | ||
122 | + } | ||
123 | + goto fault_size; | ||
124 | + } | ||
125 | + | ||
126 | + /* GPC Priority 3: the base address of GPTBR_EL3 exceeds PPS. */ | ||
127 | + tableaddr = env->cp15.gptbr_el3 << 12; | ||
128 | + if (tableaddr & ~pps_mask) { | ||
129 | + goto fault_size; | ||
130 | + } | ||
131 | + | ||
132 | + /* | ||
133 | + * BADDR is aligned per a function of PPS and L0GPTSZ. | ||
134 | + * These bits of GPTBR_EL3 are RES0, but are not a configuration error, | ||
135 | + * unlike the RES0 bits of the GPT entries (R_XNKFZ). | ||
136 | + */ | ||
137 | + align = MAX(pps - l0gptsz + 3, 12); | ||
138 | + align = MAKE_64BIT_MASK(0, align); | ||
139 | + tableaddr &= ~align; | ||
140 | + | ||
141 | + as = arm_addressspace(env_cpu(env), attrs); | ||
142 | + | ||
143 | + /* Level 0 lookup. */ | ||
144 | + index = extract64(paddress, l0gptsz, pps - l0gptsz); | ||
145 | + tableaddr += index * 8; | ||
146 | + entry = address_space_ldq_le(as, tableaddr, attrs, &result); | ||
147 | + if (result != MEMTX_OK) { | ||
148 | + goto fault_eabt; | ||
149 | + } | ||
150 | + | ||
151 | + switch (extract32(entry, 0, 4)) { | ||
152 | + case 1: /* block descriptor */ | ||
153 | + if (entry >> 8) { | ||
154 | + goto fault_walk; /* RES0 bits not 0 */ | ||
155 | + } | ||
156 | + gpi = extract32(entry, 4, 4); | ||
157 | + goto found; | ||
158 | + case 3: /* table descriptor */ | ||
159 | + tableaddr = entry & ~0xf; | ||
160 | + align = MAX(l0gptsz - pgs - 1, 12); | ||
161 | + align = MAKE_64BIT_MASK(0, align); | ||
162 | + if (tableaddr & (~pps_mask | align)) { | ||
163 | + goto fault_walk; /* RES0 bits not 0 */ | ||
164 | + } | ||
165 | + break; | ||
166 | + default: /* invalid */ | ||
167 | + goto fault_walk; | ||
168 | + } | ||
169 | + | ||
170 | + /* Level 1 lookup */ | ||
171 | + level = 1; | ||
172 | + index = extract64(paddress, pgs + 4, l0gptsz - pgs - 4); | ||
173 | + tableaddr += index * 8; | ||
174 | + entry = address_space_ldq_le(as, tableaddr, attrs, &result); | ||
175 | + if (result != MEMTX_OK) { | ||
176 | + goto fault_eabt; | ||
177 | + } | ||
178 | + | ||
179 | + switch (extract32(entry, 0, 4)) { | ||
180 | + case 1: /* contiguous descriptor */ | ||
181 | + if (entry >> 10) { | ||
182 | + goto fault_walk; /* RES0 bits not 0 */ | ||
183 | + } | ||
184 | + /* | ||
185 | + * Because the softmmu tlb only works on units of TARGET_PAGE_SIZE, | ||
186 | + * and because we cannot invalidate by pa, and thus will always | ||
187 | + * flush entire tlbs, we don't actually care about the range here | ||
188 | + * and can simply extract the GPI as the result. | ||
189 | + */ | ||
190 | + if (extract32(entry, 8, 2) == 0) { | ||
191 | + goto fault_walk; /* reserved contig */ | ||
192 | + } | ||
193 | + gpi = extract32(entry, 4, 4); | ||
194 | + break; | ||
195 | + default: | ||
196 | + index = extract64(paddress, pgs, 4); | ||
197 | + gpi = extract64(entry, index * 4, 4); | ||
198 | + break; | ||
199 | + } | ||
200 | + | ||
201 | + found: | ||
202 | + switch (gpi) { | ||
203 | + case 0b0000: /* no access */ | ||
204 | + break; | ||
205 | + case 0b1111: /* all access */ | ||
206 | + return true; | ||
207 | + case 0b1000: | ||
208 | + case 0b1001: | ||
209 | + case 0b1010: | ||
210 | + case 0b1011: | ||
211 | + if (pspace == (gpi & 3)) { | ||
212 | + return true; | ||
213 | + } | ||
214 | + break; | ||
215 | + default: | ||
216 | + goto fault_walk; /* reserved */ | ||
217 | + } | ||
218 | + | ||
219 | + fi->gpcf = GPCF_Fail; | ||
220 | + goto fault_common; | ||
221 | + fault_eabt: | ||
222 | + fi->gpcf = GPCF_EABT; | ||
223 | + goto fault_common; | ||
224 | + fault_size: | ||
225 | + fi->gpcf = GPCF_AddressSize; | ||
226 | + goto fault_common; | ||
227 | + fault_walk: | ||
228 | + fi->gpcf = GPCF_Walk; | ||
229 | + fault_common: | ||
230 | + fi->level = level; | ||
231 | + fi->paddr = paddress; | ||
232 | + fi->paddr_space = pspace; | ||
233 | + return false; | ||
123 | +} | 234 | +} |
124 | + | 235 | + |
125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | 236 | static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) |
126 | { | 237 | { |
127 | /* | 238 | /* |
128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | 239 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
129 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, | 240 | }; |
130 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, | 241 | GetPhysAddrResult s2 = { }; |
131 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | 242 | |
132 | + { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | 243 | - if (get_phys_addr_with_struct(env, &s2ptw, addr, |
133 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | 244 | - MMU_DATA_LOAD, &s2, fi)) { |
134 | { .name = "max", .initfn = aarch64_max_initfn }, | 245 | + if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { |
135 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | 246 | goto fail; |
247 | } | ||
248 | + | ||
249 | ptw->out_phys = s2.f.phys_addr; | ||
250 | pte_attrs = s2.cacheattrs.attrs; | ||
251 | ptw->out_host = NULL; | ||
252 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
253 | |||
254 | fail: | ||
255 | assert(fi->type != ARMFault_None); | ||
256 | + if (fi->type == ARMFault_GPCFOnOutput) { | ||
257 | + fi->type = ARMFault_GPCFOnWalk; | ||
258 | + } | ||
259 | fi->s2addr = addr; | ||
260 | fi->stage2 = true; | ||
261 | fi->s1ptw = true; | ||
262 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, | ||
263 | ARMMMUFaultInfo *fi) | ||
264 | { | ||
265 | uint8_t memattr = 0x00; /* Device nGnRnE */ | ||
266 | - uint8_t shareability = 0; /* non-sharable */ | ||
267 | + uint8_t shareability = 0; /* non-shareable */ | ||
268 | int r_el; | ||
269 | |||
270 | switch (mmu_idx) { | ||
271 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, | ||
272 | } else { | ||
273 | memattr = 0x44; /* Normal, NC, No */ | ||
274 | } | ||
275 | - shareability = 2; /* outer sharable */ | ||
276 | + shareability = 2; /* outer shareable */ | ||
277 | } | ||
278 | result->cacheattrs.is_s2_format = false; | ||
279 | break; | ||
280 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
281 | ARMSecuritySpace ipa_space; | ||
282 | uint64_t hcr; | ||
283 | |||
284 | - ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); | ||
285 | + ret = get_phys_addr_nogpc(env, ptw, address, access_type, result, fi); | ||
286 | |||
287 | /* If S1 fails, return early. */ | ||
288 | if (ret) { | ||
289 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
290 | cacheattrs1 = result->cacheattrs; | ||
291 | memset(result, 0, sizeof(*result)); | ||
292 | |||
293 | - ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi); | ||
294 | + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); | ||
295 | fi->s2addr = ipa; | ||
296 | |||
297 | /* Combine the S1 and S2 perms. */ | ||
298 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
299 | return false; | ||
300 | } | ||
301 | |||
302 | -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
303 | +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, | ||
304 | target_ulong address, | ||
305 | MMUAccessType access_type, | ||
306 | GetPhysAddrResult *result, | ||
307 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
308 | } | ||
309 | } | ||
310 | |||
311 | +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, | ||
312 | + target_ulong address, | ||
313 | + MMUAccessType access_type, | ||
314 | + GetPhysAddrResult *result, | ||
315 | + ARMMMUFaultInfo *fi) | ||
316 | +{ | ||
317 | + if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { | ||
318 | + return true; | ||
319 | + } | ||
320 | + if (!granule_protection_check(env, result->f.phys_addr, | ||
321 | + result->f.attrs.space, fi)) { | ||
322 | + fi->type = ARMFault_GPCFOnOutput; | ||
323 | + return true; | ||
324 | + } | ||
325 | + return false; | ||
326 | +} | ||
327 | + | ||
328 | bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, | ||
329 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | ||
330 | bool is_secure, GetPhysAddrResult *result, | ||
331 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, | ||
332 | .in_secure = is_secure, | ||
333 | .in_space = arm_secure_to_space(is_secure), | ||
334 | }; | ||
335 | - return get_phys_addr_with_struct(env, &ptw, address, access_type, | ||
336 | - result, fi); | ||
337 | + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); | ||
338 | } | ||
339 | |||
340 | bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
341 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
342 | |||
343 | ptw.in_space = ss; | ||
344 | ptw.in_secure = arm_space_is_secure(ss); | ||
345 | - return get_phys_addr_with_struct(env, &ptw, address, access_type, | ||
346 | - result, fi); | ||
347 | + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); | ||
348 | } | ||
349 | |||
350 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, | ||
351 | @@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, | ||
352 | ARMMMUFaultInfo fi = {}; | ||
353 | bool ret; | ||
354 | |||
355 | - ret = get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); | ||
356 | + ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); | ||
357 | *attrs = res.f.attrs; | ||
358 | |||
359 | if (ret) { | ||
136 | -- | 360 | -- |
137 | 2.25.1 | 361 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Previously we were defining some of these in user-only mode, | 3 | Add an x-rme cpu property to enable FEAT_RME. |
4 | but none of them are accessible from user-only, therefore | 4 | Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ, |
5 | define them only in system mode. | 5 | for testing various possible configurations. |
6 | 6 | ||
7 | This will shortly be used from cpu_tcg.c also. | 7 | We're not currently completely sure whether FEAT_RME will |
8 | be OK to enable purely as a CPU-level property, or if it will | ||
9 | need board co-operation, so we're making these experimental | ||
10 | x- properties, so that the people developing the system | ||
11 | level software for RME can try to start using this and let | ||
12 | us know how it goes. The command line syntax for enabling | ||
13 | this will change in future, without backwards-compatibility. | ||
8 | 14 | ||
15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Message-id: 20230620124418.805717-21-richard.henderson@linaro.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220506180242.216785-6-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 19 | --- |
14 | target/arm/internals.h | 6 ++++ | 20 | target/arm/tcg/cpu64.c | 53 ++++++++++++++++++++++++++++++++++++++++++ |
15 | target/arm/cpu64.c | 64 +++--------------------------------------- | 21 | 1 file changed, 53 insertions(+) |
16 | target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ | ||
17 | 3 files changed, 69 insertions(+), 60 deletions(-) | ||
18 | 22 | ||
19 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 23 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
20 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/internals.h | 25 | --- a/target/arm/tcg/cpu64.c |
22 | +++ b/target/arm/internals.h | 26 | +++ b/target/arm/tcg/cpu64.c |
23 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); | 27 | @@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, |
24 | int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); | 28 | cpu->sve_max_vq = max_vq; |
25 | #endif | ||
26 | |||
27 | +#ifdef CONFIG_USER_ONLY | ||
28 | +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | ||
29 | +#else | ||
30 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | ||
31 | +#endif | ||
32 | + | ||
33 | #endif | ||
34 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/cpu64.c | ||
37 | +++ b/target/arm/cpu64.c | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | #include "hvf_arm.h" | ||
40 | #include "qapi/visitor.h" | ||
41 | #include "hw/qdev-properties.h" | ||
42 | -#include "cpregs.h" | ||
43 | +#include "internals.h" | ||
44 | |||
45 | |||
46 | -#ifndef CONFIG_USER_ONLY | ||
47 | -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
48 | -{ | ||
49 | - ARMCPU *cpu = env_archcpu(env); | ||
50 | - | ||
51 | - /* Number of cores is in [25:24]; otherwise we RAZ */ | ||
52 | - return (cpu->core_count - 1) << 24; | ||
53 | -} | ||
54 | -#endif | ||
55 | - | ||
56 | -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
57 | -#ifndef CONFIG_USER_ONLY | ||
58 | - { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
59 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | ||
60 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | ||
61 | - .writefn = arm_cp_write_ignore }, | ||
62 | - { .name = "L2CTLR", | ||
63 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | ||
64 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | ||
65 | - .writefn = arm_cp_write_ignore }, | ||
66 | -#endif | ||
67 | - { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
68 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | ||
69 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
70 | - { .name = "L2ECTLR", | ||
71 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | ||
72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
73 | - { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | ||
74 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | ||
75 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
76 | - { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
77 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | ||
78 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | - { .name = "CPUACTLR", | ||
80 | - .cp = 15, .opc1 = 0, .crm = 15, | ||
81 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
82 | - { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
83 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | ||
84 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
85 | - { .name = "CPUECTLR", | ||
86 | - .cp = 15, .opc1 = 1, .crm = 15, | ||
87 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
88 | - { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
89 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | ||
90 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
91 | - { .name = "CPUMERRSR", | ||
92 | - .cp = 15, .opc1 = 2, .crm = 15, | ||
93 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
94 | - { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
95 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | ||
96 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
97 | - { .name = "L2MERRSR", | ||
98 | - .cp = 15, .opc1 = 3, .crm = 15, | ||
99 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
100 | -}; | ||
101 | - | ||
102 | static void aarch64_a57_initfn(Object *obj) | ||
103 | { | ||
104 | ARMCPU *cpu = ARM_CPU(obj); | ||
105 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | ||
106 | cpu->gic_num_lrs = 4; | ||
107 | cpu->gic_vpribits = 5; | ||
108 | cpu->gic_vprebits = 5; | ||
109 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
110 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
111 | } | 29 | } |
112 | 30 | ||
113 | static void aarch64_a53_initfn(Object *obj) | 31 | +static bool cpu_arm_get_rme(Object *obj, Error **errp) |
114 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
115 | cpu->gic_num_lrs = 4; | ||
116 | cpu->gic_vpribits = 5; | ||
117 | cpu->gic_vprebits = 5; | ||
118 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
119 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
120 | } | ||
121 | |||
122 | static void aarch64_a72_initfn(Object *obj) | ||
123 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
124 | cpu->gic_num_lrs = 4; | ||
125 | cpu->gic_vpribits = 5; | ||
126 | cpu->gic_vprebits = 5; | ||
127 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
128 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
129 | } | ||
130 | |||
131 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | ||
132 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
133 | index XXXXXXX..XXXXXXX 100644 | ||
134 | --- a/target/arm/cpu_tcg.c | ||
135 | +++ b/target/arm/cpu_tcg.c | ||
136 | @@ -XXX,XX +XXX,XX @@ | ||
137 | #endif | ||
138 | #include "cpregs.h" | ||
139 | |||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
142 | +{ | 32 | +{ |
143 | + ARMCPU *cpu = env_archcpu(env); | 33 | + ARMCPU *cpu = ARM_CPU(obj); |
144 | + | 34 | + return cpu_isar_feature(aa64_rme, cpu); |
145 | + /* Number of cores is in [25:24]; otherwise we RAZ */ | ||
146 | + return (cpu->core_count - 1) << 24; | ||
147 | +} | 35 | +} |
148 | + | 36 | + |
149 | +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | 37 | +static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) |
150 | + { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | 38 | +{ |
151 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | 39 | + ARMCPU *cpu = ARM_CPU(obj); |
152 | + .access = PL1_RW, .readfn = l2ctlr_read, | 40 | + uint64_t t; |
153 | + .writefn = arm_cp_write_ignore }, | ||
154 | + { .name = "L2CTLR", | ||
155 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | ||
156 | + .access = PL1_RW, .readfn = l2ctlr_read, | ||
157 | + .writefn = arm_cp_write_ignore }, | ||
158 | + { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
159 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | ||
160 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
161 | + { .name = "L2ECTLR", | ||
162 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | ||
163 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
164 | + { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | ||
165 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | ||
166 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
167 | + { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
168 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | ||
169 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
170 | + { .name = "CPUACTLR", | ||
171 | + .cp = 15, .opc1 = 0, .crm = 15, | ||
172 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
173 | + { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
174 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | ||
175 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
176 | + { .name = "CPUECTLR", | ||
177 | + .cp = 15, .opc1 = 1, .crm = 15, | ||
178 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
179 | + { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
180 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | ||
181 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
182 | + { .name = "CPUMERRSR", | ||
183 | + .cp = 15, .opc1 = 2, .crm = 15, | ||
184 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
185 | + { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
186 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | ||
187 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
188 | + { .name = "L2MERRSR", | ||
189 | + .cp = 15, .opc1 = 3, .crm = 15, | ||
190 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
191 | +}; | ||
192 | + | 41 | + |
193 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) | 42 | + t = cpu->isar.id_aa64pfr0; |
43 | + t = FIELD_DP64(t, ID_AA64PFR0, RME, value); | ||
44 | + cpu->isar.id_aa64pfr0 = t; | ||
45 | +} | ||
46 | + | ||
47 | +static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, | ||
48 | + void *opaque, Error **errp) | ||
194 | +{ | 49 | +{ |
195 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 50 | + ARMCPU *cpu = ARM_CPU(obj); |
51 | + uint32_t value; | ||
52 | + | ||
53 | + if (!visit_type_uint32(v, name, &value, errp)) { | ||
54 | + return; | ||
55 | + } | ||
56 | + | ||
57 | + /* Encode the value for the GPCCR_EL3 field. */ | ||
58 | + switch (value) { | ||
59 | + case 30: | ||
60 | + case 34: | ||
61 | + case 36: | ||
62 | + case 39: | ||
63 | + cpu->reset_l0gptsz = value - 30; | ||
64 | + break; | ||
65 | + default: | ||
66 | + error_setg(errp, "invalid value for l0gptsz"); | ||
67 | + error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); | ||
68 | + break; | ||
69 | + } | ||
196 | +} | 70 | +} |
197 | +#endif /* !CONFIG_USER_ONLY */ | ||
198 | + | 71 | + |
199 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | 72 | +static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, |
200 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | 73 | + void *opaque, Error **errp) |
74 | +{ | ||
75 | + ARMCPU *cpu = ARM_CPU(obj); | ||
76 | + uint32_t value = cpu->reset_l0gptsz + 30; | ||
77 | + | ||
78 | + visit_type_uint32(v, name, &value, errp); | ||
79 | +} | ||
80 | + | ||
81 | static Property arm_cpu_lpa2_property = | ||
82 | DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); | ||
83 | |||
84 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
85 | aarch64_add_sme_properties(obj); | ||
86 | object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, | ||
87 | cpu_max_set_sve_max_vq, NULL, NULL); | ||
88 | + object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme); | ||
89 | + object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, | ||
90 | + cpu_max_set_l0gptsz, NULL, NULL); | ||
91 | qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); | ||
92 | } | ||
201 | 93 | ||
202 | -- | 94 | -- |
203 | 2.25.1 | 95 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20220506180242.216785-18-richard.henderson@linaro.org | 4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
5 | Message-id: 20230622143046.1578160-1-richard.henderson@linaro.org | ||
6 | [PMM: fixed typo; note experimental status in emulation.rst too] | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 8 | --- |
8 | docs/system/arm/emulation.rst | 1 + | 9 | docs/system/arm/cpu-features.rst | 23 +++++++++++++++++++++++ |
9 | target/arm/cpu64.c | 1 + | 10 | docs/system/arm/emulation.rst | 1 + |
10 | target/arm/cpu_tcg.c | 1 + | 11 | 2 files changed, 24 insertions(+) |
11 | 3 files changed, 3 insertions(+) | ||
12 | 12 | ||
13 | diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/docs/system/arm/cpu-features.rst | ||
16 | +++ b/docs/system/arm/cpu-features.rst | ||
17 | @@ -XXX,XX +XXX,XX @@ As with ``sve-default-vector-length``, if the default length is larger | ||
18 | than the maximum vector length enabled, the actual vector length will | ||
19 | be reduced. If this property is set to ``-1`` then the default vector | ||
20 | length is set to the maximum possible length. | ||
21 | + | ||
22 | +RME CPU Properties | ||
23 | +================== | ||
24 | + | ||
25 | +The status of RME support with QEMU is experimental. At this time we | ||
26 | +only support RME within the CPU proper, not within the SMMU or GIC. | ||
27 | +The feature is enabled by the CPU property ``x-rme``, with the ``x-`` | ||
28 | +prefix present as a reminder of the experimental status, and defaults off. | ||
29 | + | ||
30 | +The method for enabling RME will change in some future QEMU release | ||
31 | +without notice or backward compatibility. | ||
32 | + | ||
33 | +RME Level 0 GPT Size Property | ||
34 | +----------------------------- | ||
35 | + | ||
36 | +To aid firmware developers in testing different possible CPU | ||
37 | +configurations, ``x-l0gptsz=S`` may be used to specify the value | ||
38 | +to encode into ``GPCCR_EL3.L0GPTSZ``, a read-only field that | ||
39 | +specifies the size of the Level 0 Granule Protection Table. | ||
40 | +Legal values for ``S`` are 30, 34, 36, and 39; the default is 30. | ||
41 | + | ||
42 | +As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or | ||
43 | +removed in some future QEMU release. | ||
13 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 44 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
14 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/docs/system/arm/emulation.rst | 46 | --- a/docs/system/arm/emulation.rst |
16 | +++ b/docs/system/arm/emulation.rst | 47 | +++ b/docs/system/arm/emulation.rst |
17 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 48 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
18 | - FEAT_PMULL (PMULL, PMULL2 instructions) | 49 | - FEAT_RAS (Reliability, availability, and serviceability) |
19 | - FEAT_PMUv3p1 (PMU Extensions v3.1) | 50 | - FEAT_RASv1p1 (RAS Extension v1.1) |
20 | - FEAT_PMUv3p4 (PMU Extensions v3.4) | ||
21 | +- FEAT_RAS (Reliability, availability, and serviceability) | ||
22 | - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) | 51 | - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) |
52 | +- FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental) | ||
23 | - FEAT_RNG (Random number generator) | 53 | - FEAT_RNG (Random number generator) |
54 | - FEAT_S2FWB (Stage 2 forced Write-Back) | ||
24 | - FEAT_SB (Speculation Barrier) | 55 | - FEAT_SB (Speculation Barrier) |
25 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/cpu64.c | ||
28 | +++ b/target/arm/cpu64.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
30 | t = cpu->isar.id_aa64pfr0; | ||
31 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | ||
32 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | ||
33 | + t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ | ||
34 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
35 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
36 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
37 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/cpu_tcg.c | ||
40 | +++ b/target/arm/cpu_tcg.c | ||
41 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
42 | |||
43 | t = cpu->isar.id_pfr0; | ||
44 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
45 | + t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ | ||
46 | cpu->isar.id_pfr0 = t; | ||
47 | |||
48 | t = cpu->isar.id_pfr2; | ||
49 | -- | 56 | -- |
50 | 2.25.1 | 57 | 2.34.1 |
58 | |||
59 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | We use __builtin_subcll() to do a 64-bit subtract with borrow-in and |
---|---|---|---|
2 | borrow-out when the host compiler supports it. Unfortunately some | ||
3 | versions of Apple Clang have a bug in their implementation of this | ||
4 | intrinsic which means it returns the wrong value. The effect is that | ||
5 | a QEMU built with the affected compiler will hang when emulating x86 | ||
6 | or m68k float80 division. | ||
2 | 7 | ||
3 | The CPU topology isn't enabled on arm/virt machine yet, but we're | 8 | The upstream LLVM issue is: |
4 | going to do it in next patch. After the CPU topology is enabled by | 9 | https://github.com/llvm/llvm-project/issues/55253 |
5 | next patch, "thread-id=1" becomes invalid because the CPU core is | ||
6 | preferred on arm/virt machine. It means these two CPUs have 0/1 | ||
7 | as their core IDs, but their thread IDs are all 0. It will trigger | ||
8 | test failure as the following message indicates: | ||
9 | 10 | ||
10 | [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR | 11 | The commit that introduced the bug apparently never made it into an |
11 | 1.48s killed by signal 6 SIGABRT | 12 | upstream LLVM release without the subsequent fix |
12 | >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \ | 13 | https://github.com/llvm/llvm-project/commit/fffb6e6afdbaba563189c1f715058ed401fbc88d |
13 | QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \ | 14 | but unfortunately it did make it into Apple Clang 14.0, as shipped |
14 | QTEST_QEMU_BINARY=./qemu-system-aarch64 \ | 15 | in Xcode 14.3 (14.2 is reported to be OK). The Apple bug number is |
15 | QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \ | 16 | FB12210478. |
16 | /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k | ||
17 | ―――――――――――――――――――――――――――――――――――――――――――――― | ||
18 | stderr: | ||
19 | qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found | ||
20 | 17 | ||
21 | This fixes the issue by providing comprehensive SMP configurations | 18 | Add ifdefs to avoid use of __builtin_subcll() on Apple Clang version |
22 | in aarch64_numa_cpu(). The SMP configurations aren't used before | 19 | 14 or greater. There is not currently a version of Apple Clang which |
23 | the CPU topology is enabled in next patch. | 20 | has the bug fix -- when one appears we should be able to add an upper |
21 | bound to the ifdef condition so we can start using the builtin again. | ||
22 | We make the lower bound a conservative "any Apple clang with major | ||
23 | version 14 or greater" because the consequences of incorrectly | ||
24 | disabling the builtin when it would work are pretty small and the | ||
25 | consequences of not disabling it when we should are pretty bad. | ||
24 | 26 | ||
25 | Signed-off-by: Gavin Shan <gshan@redhat.com> | 27 | Many thanks to those users who both reported this bug and also |
26 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | 28 | did a lot of work in identifying the root cause; in particular |
27 | Message-id: 20220503140304.855514-3-gshan@redhat.com | 29 | to Daniel Bertalan and osy. |
30 | |||
31 | Cc: qemu-stable@nongnu.org | ||
32 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1631 | ||
33 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1659 | ||
28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
35 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
36 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | ||
37 | Tested-by: Daniel Bertalan <dani@danielbertalan.dev> | ||
38 | Tested-by: Tested-By: Solra Bizna <solra@bizna.name> | ||
39 | Message-id: 20230622130823.1631719-1-peter.maydell@linaro.org | ||
29 | --- | 40 | --- |
30 | tests/qtest/numa-test.c | 3 ++- | 41 | include/qemu/compiler.h | 13 +++++++++++++ |
31 | 1 file changed, 2 insertions(+), 1 deletion(-) | 42 | include/qemu/host-utils.h | 2 +- |
43 | 2 files changed, 14 insertions(+), 1 deletion(-) | ||
32 | 44 | ||
33 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c | 45 | diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h |
34 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/tests/qtest/numa-test.c | 47 | --- a/include/qemu/compiler.h |
36 | +++ b/tests/qtest/numa-test.c | 48 | +++ b/include/qemu/compiler.h |
37 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | 49 | @@ -XXX,XX +XXX,XX @@ |
38 | QTestState *qts; | 50 | #define QEMU_DISABLE_CFI |
39 | g_autofree char *cli = NULL; | 51 | #endif |
40 | 52 | ||
41 | - cli = make_cli(data, "-machine smp.cpus=2 " | 53 | +/* |
42 | + cli = make_cli(data, "-machine " | 54 | + * Apple clang version 14 has a bug in its __builtin_subcll(); define |
43 | + "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " | 55 | + * BUILTIN_SUBCLL_BROKEN for the offending versions so we can avoid it. |
44 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " | 56 | + * When a version of Apple clang which has this bug fixed is released |
45 | "-numa cpu,node-id=1,thread-id=0 " | 57 | + * we can add an upper bound to this check. |
46 | "-numa cpu,node-id=0,thread-id=1"); | 58 | + * See https://gitlab.com/qemu-project/qemu/-/issues/1631 |
59 | + * and https://gitlab.com/qemu-project/qemu/-/issues/1659 for details. | ||
60 | + * The bug never made it into any upstream LLVM releases, only Apple ones. | ||
61 | + */ | ||
62 | +#if defined(__apple_build_version__) && __clang_major__ >= 14 | ||
63 | +#define BUILTIN_SUBCLL_BROKEN | ||
64 | +#endif | ||
65 | + | ||
66 | #endif /* COMPILER_H */ | ||
67 | diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/include/qemu/host-utils.h | ||
70 | +++ b/include/qemu/host-utils.h | ||
71 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t uadd64_carry(uint64_t x, uint64_t y, bool *pcarry) | ||
72 | */ | ||
73 | static inline uint64_t usub64_borrow(uint64_t x, uint64_t y, bool *pborrow) | ||
74 | { | ||
75 | -#if __has_builtin(__builtin_subcll) | ||
76 | +#if __has_builtin(__builtin_subcll) && !defined(BUILTIN_SUBCLL_BROKEN) | ||
77 | unsigned long long b = *pborrow; | ||
78 | x = __builtin_subcll(x, y, b, &b); | ||
79 | *pborrow = b & 1; | ||
47 | -- | 80 | -- |
48 | 2.25.1 | 81 | 2.34.1 |
49 | 82 | ||
50 | 83 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 | 3 | One cannot test for feature aa32_simd_r32 without first |
4 | during arm_cpu_realizefn. | 4 | testing if AArch32 mode is supported at all. This leads to |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither |
7 | |||
8 | for Apple M1 cpus. | ||
9 | |||
10 | We already have a check for ARMv8-A never setting vfp-d32 true, | ||
11 | so restructure the code so that AArch64 avoids the test entirely. | ||
12 | |||
13 | Reported-by: Mads Ynddal <mads@ynddal.dk> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-11-richard.henderson@linaro.org | 15 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
16 | Tested-by: Mads Ynddal <m.ynddal@samsung.com> | ||
17 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
18 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
19 | Reviewed-by: Mads Ynddal <m.ynddal@samsung.com> | ||
20 | Message-id: 20230619140216.402530-1-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 22 | --- |
11 | target/arm/cpu.c | 22 +++++++++++++--------- | 23 | target/arm/cpu.c | 28 +++++++++++++++------------- |
12 | 1 file changed, 13 insertions(+), 9 deletions(-) | 24 | 1 file changed, 15 insertions(+), 13 deletions(-) |
13 | 25 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 26 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
15 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 28 | --- a/target/arm/cpu.c |
17 | +++ b/target/arm/cpu.c | 29 | +++ b/target/arm/cpu.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 30 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj) |
19 | */ | 31 | * KVM does not currently allow us to lie to the guest about its |
20 | unset_feature(env, ARM_FEATURE_EL3); | 32 | * ID/feature registers, so the guest always sees what the host has. |
21 | 33 | */ | |
22 | - /* Disable the security extension feature bits in the processor feature | 34 | - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) |
23 | - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. | 35 | - ? cpu_isar_feature(aa64_fp_simd, cpu) |
24 | + /* | 36 | - : cpu_isar_feature(aa32_vfp, cpu)) { |
25 | + * Disable the security extension feature bits in the processor | 37 | - cpu->has_vfp = true; |
26 | + * feature registers as well. | 38 | - if (!kvm_enabled()) { |
27 | */ | 39 | - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); |
28 | - cpu->isar.id_pfr1 &= ~0xf0; | 40 | + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
29 | - cpu->isar.id_aa64pfr0 &= ~0xf000; | 41 | + if (cpu_isar_feature(aa64_fp_simd, cpu)) { |
30 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | 42 | + cpu->has_vfp = true; |
31 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | 43 | + cpu->has_vfp_d32 = true; |
32 | + ID_AA64PFR0, EL3, 0); | 44 | + if (tcg_enabled() || qtest_enabled()) { |
33 | } | 45 | + qdev_property_add_static(DEVICE(obj), |
34 | 46 | + &arm_cpu_has_vfp_property); | |
35 | if (!cpu->has_el2) { | 47 | + } |
36 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 48 | } |
37 | } | 49 | - } |
38 | 50 | - | |
39 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | 51 | - if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) { |
40 | - /* Disable the hypervisor feature bits in the processor feature | 52 | - cpu->has_vfp_d32 = true; |
41 | - * registers if we don't have EL2. These are id_pfr1[15:12] and | 53 | - if (!kvm_enabled()) { |
42 | - * id_aa64pfr0_el1[11:8]. | 54 | + } else if (cpu_isar_feature(aa32_vfp, cpu)) { |
43 | + /* | 55 | + cpu->has_vfp = true; |
44 | + * Disable the hypervisor feature bits in the processor feature | 56 | + if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
45 | + * registers if we don't have EL2. | 57 | + cpu->has_vfp_d32 = true; |
46 | */ | 58 | /* |
47 | - cpu->isar.id_aa64pfr0 &= ~0xf00; | 59 | * The permitted values of the SIMDReg bits [3:0] on |
48 | - cpu->isar.id_pfr1 &= ~0xf000; | 60 | * Armv8-A are either 0b0000 and 0b0010. On such CPUs, |
49 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | 61 | * make sure that has_vfp_d32 can not be set to false. |
50 | + ID_AA64PFR0, EL2, 0); | 62 | */ |
51 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, | 63 | - if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) && |
52 | + ID_PFR1, VIRTUALIZATION, 0); | 64 | - !arm_feature(&cpu->env, ARM_FEATURE_M))) { |
53 | } | 65 | + if ((tcg_enabled() || qtest_enabled()) |
54 | 66 | + && !(arm_feature(&cpu->env, ARM_FEATURE_V8) | |
55 | #ifndef CONFIG_USER_ONLY | 67 | + && !arm_feature(&cpu->env, ARM_FEATURE_M))) { |
68 | qdev_property_add_static(DEVICE(obj), | ||
69 | &arm_cpu_has_vfp_d32_property); | ||
70 | } | ||
56 | -- | 71 | -- |
57 | 2.25.1 | 72 | 2.34.1 |
73 | |||
74 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <quic_llindhol@quicinc.com> | 1 | From: Shashi Mallela <shashi.mallela@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The sbsa-ref machine is continuously evolving. Some of the changes we | 3 | Create ITS as part of SBSA platform GIC initialization. |
4 | want to make in the near future, to align with real components (e.g. | ||
5 | the GIC-700), will break compatibility for existing firmware. | ||
6 | 4 | ||
7 | Introduce two new properties to the DT generated on machine generation: | 5 | GIC ITS information is in DeviceTree so TF-A can pass it to EDK2. |
8 | - machine-version-major | ||
9 | To be incremented when a platform change makes the machine | ||
10 | incompatible with existing firmware. | ||
11 | - machine-version-minor | ||
12 | To be incremented when functionality is added to the machine | ||
13 | without causing incompatibility with existing firmware. | ||
14 | to be reset to 0 when machine-version-major is incremented. | ||
15 | 6 | ||
16 | This versioning scheme is *neither*: | 7 | Bumping platform version to 0.2 as this is important hardware change. |
17 | - A QEMU versioned machine type; a given version of QEMU will emulate | ||
18 | a given version of the platform. | ||
19 | - A reflection of level of SBSA (now SystemReady SR) support provided. | ||
20 | 8 | ||
21 | The version will increment on guest-visible functional changes only, | 9 | Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> |
22 | akin to a revision ID register found on a physical platform. | 10 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
23 | 11 | Message-id: 20230619170913.517373-2-marcin.juszkiewicz@linaro.org | |
24 | These properties are both introduced with the value 0. | 12 | Co-authored-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
25 | (Hence, a machine where the DT is lacking these nodes is equivalent | 13 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
26 | to version 0.0.) | ||
27 | |||
28 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
29 | Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com | ||
30 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Cc: Radoslaw Biernacki <rad@semihalf.com> | ||
32 | Cc: Cédric Le Goater <clg@kaod.org> | ||
33 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
35 | --- | 16 | --- |
36 | hw/arm/sbsa-ref.c | 14 ++++++++++++++ | 17 | docs/system/arm/sbsa.rst | 14 ++++++++++++++ |
37 | 1 file changed, 14 insertions(+) | 18 | hw/arm/sbsa-ref.c | 33 ++++++++++++++++++++++++++++++--- |
19 | 2 files changed, 44 insertions(+), 3 deletions(-) | ||
38 | 20 | ||
21 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/docs/system/arm/sbsa.rst | ||
24 | +++ b/docs/system/arm/sbsa.rst | ||
25 | @@ -XXX,XX +XXX,XX @@ to be a complete compliant DT. It currently reports: | ||
26 | - platform version | ||
27 | - GIC addresses | ||
28 | |||
29 | +Platform version | ||
30 | +'''''''''''''''' | ||
31 | + | ||
32 | The platform version is only for informing platform firmware about | ||
33 | what kind of ``sbsa-ref`` board it is running on. It is neither | ||
34 | a QEMU versioned machine type nor a reflection of the level of the | ||
35 | @@ -XXX,XX +XXX,XX @@ SBSA/SystemReady SR support provided. | ||
36 | The ``machine-version-major`` value is updated when changes breaking | ||
37 | fw compatibility are introduced. The ``machine-version-minor`` value | ||
38 | is updated when features are added that don't break fw compatibility. | ||
39 | + | ||
40 | +Platform version changes: | ||
41 | + | ||
42 | +0.0 | ||
43 | + Devicetree holds information about CPUs, memory and platform version. | ||
44 | + | ||
45 | +0.1 | ||
46 | + GIC information is present in devicetree. | ||
47 | + | ||
48 | +0.2 | ||
49 | + GIC ITS information is present in devicetree. | ||
39 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | 50 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
40 | index XXXXXXX..XXXXXXX 100644 | 51 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/hw/arm/sbsa-ref.c | 52 | --- a/hw/arm/sbsa-ref.c |
42 | +++ b/hw/arm/sbsa-ref.c | 53 | +++ b/hw/arm/sbsa-ref.c |
54 | @@ -XXX,XX +XXX,XX @@ enum { | ||
55 | SBSA_CPUPERIPHS, | ||
56 | SBSA_GIC_DIST, | ||
57 | SBSA_GIC_REDIST, | ||
58 | + SBSA_GIC_ITS, | ||
59 | SBSA_SECURE_EC, | ||
60 | SBSA_GWDT_WS0, | ||
61 | SBSA_GWDT_REFRESH, | ||
62 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = { | ||
63 | [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, | ||
64 | [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, | ||
65 | [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, | ||
66 | + [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, | ||
67 | [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, | ||
68 | [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, | ||
69 | [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, | ||
70 | @@ -XXX,XX +XXX,XX @@ static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) | ||
71 | 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, | ||
72 | 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); | ||
73 | |||
74 | + nodename = g_strdup_printf("/intc/its"); | ||
75 | + qemu_fdt_add_subnode(sms->fdt, nodename); | ||
76 | + qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", | ||
77 | + 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, | ||
78 | + 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); | ||
79 | + | ||
80 | g_free(nodename); | ||
81 | } | ||
82 | + | ||
83 | /* | ||
84 | * Firmware on this machine only uses ACPI table to load OS, these limited | ||
85 | * device tree nodes are just to let firmware know the info which varies from | ||
43 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms) | 86 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms) |
44 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | 87 | * fw compatibility. |
45 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | 88 | */ |
46 | 89 | qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); | |
47 | + /* | 90 | - qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1); |
48 | + * This versioning scheme is for informing platform fw only. It is neither: | 91 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2); |
49 | + * - A QEMU versioned machine type; a given version of QEMU will emulate | 92 | |
50 | + * a given version of the platform. | ||
51 | + * - A reflection of level of SBSA (now SystemReady SR) support provided. | ||
52 | + * | ||
53 | + * machine-version-major: updated when changes breaking fw compatibility | ||
54 | + * are introduced. | ||
55 | + * machine-version-minor: updated when features are added that don't break | ||
56 | + * fw compatibility. | ||
57 | + */ | ||
58 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); | ||
59 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0); | ||
60 | + | ||
61 | if (ms->numa_state->have_numa_distance) { | 93 | if (ms->numa_state->have_numa_distance) { |
62 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); | 94 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); |
63 | uint32_t *matrix = g_malloc0(size); | 95 | @@ -XXX,XX +XXX,XX @@ static void create_secure_ram(SBSAMachineState *sms, |
96 | memory_region_add_subregion(secure_sysmem, base, secram); | ||
97 | } | ||
98 | |||
99 | -static void create_gic(SBSAMachineState *sms) | ||
100 | +static void create_its(SBSAMachineState *sms) | ||
101 | +{ | ||
102 | + const char *itsclass = its_class_name(); | ||
103 | + DeviceState *dev; | ||
104 | + | ||
105 | + dev = qdev_new(itsclass); | ||
106 | + | ||
107 | + object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), | ||
108 | + &error_abort); | ||
109 | + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
110 | + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); | ||
111 | +} | ||
112 | + | ||
113 | +static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) | ||
114 | { | ||
115 | unsigned int smp_cpus = MACHINE(sms)->smp.cpus; | ||
116 | SysBusDevice *gicbusdev; | ||
117 | @@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms) | ||
118 | qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); | ||
119 | qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); | ||
120 | |||
121 | + object_property_set_link(OBJECT(sms->gic), "sysmem", | ||
122 | + OBJECT(mem), &error_fatal); | ||
123 | + qdev_prop_set_bit(sms->gic, "has-lpi", true); | ||
124 | + | ||
125 | gicbusdev = SYS_BUS_DEVICE(sms->gic); | ||
126 | sysbus_realize_and_unref(gicbusdev, &error_fatal); | ||
127 | sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); | ||
128 | @@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms) | ||
129 | sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, | ||
130 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | ||
131 | } | ||
132 | + create_its(sms); | ||
133 | } | ||
134 | |||
135 | static void create_uart(const SBSAMachineState *sms, int uart, | ||
136 | @@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine) | ||
137 | |||
138 | create_secure_ram(sms, secure_sysmem); | ||
139 | |||
140 | - create_gic(sms); | ||
141 | + create_gic(sms, sysmem); | ||
142 | |||
143 | create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); | ||
144 | create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); | ||
64 | -- | 145 | -- |
65 | 2.25.1 | 146 | 2.34.1 |
66 | |||
67 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We set this for qemu-system-aarch64, but failed to do so | 3 | Brown bag time: store instead of load results in uninitialized temp. |
4 | for the strictly 32-bit emulation. | ||
5 | 4 | ||
6 | Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") | 5 | |
6 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1704 | ||
7 | Reported-by: Mark Rutland <mark.rutland@arm.com> | ||
8 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20230620134659.817559-1-richard.henderson@linaro.org | ||
11 | Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r") | ||
12 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220506180242.216785-8-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 16 | --- |
12 | target/arm/cpu_tcg.c | 4 ++++ | 17 | target/arm/tcg/translate-sve.c | 2 +- |
13 | 1 file changed, 4 insertions(+) | 18 | 1 file changed, 1 insertion(+), 1 deletion(-) |
14 | 19 | ||
15 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 20 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c |
16 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu_tcg.c | 22 | --- a/target/arm/tcg/translate-sve.c |
18 | +++ b/target/arm/cpu_tcg.c | 23 | +++ b/target/arm/tcg/translate-sve.c |
19 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | 24 | @@ -XXX,XX +XXX,XX @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, |
20 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | 25 | /* Predicate register stores can be any multiple of 2. */ |
21 | cpu->isar.id_pfr2 = t; | 26 | if (len_remain >= 8) { |
22 | 27 | t0 = tcg_temp_new_i64(); | |
23 | + t = cpu->isar.id_dfr0; | 28 | - tcg_gen_st_i64(t0, base, vofs + len_align); |
24 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | 29 | + tcg_gen_ld_i64(t0, base, vofs + len_align); |
25 | + cpu->isar.id_dfr0 = t; | 30 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE); |
26 | + | 31 | len_remain -= 8; |
27 | #ifdef CONFIG_USER_ONLY | 32 | len_align += 8; |
28 | /* | ||
29 | * Break with true ARMv8 and add back old-style VFP short-vector support. | ||
30 | -- | 33 | -- |
31 | 2.25.1 | 34 | 2.34.1 |
35 | |||
36 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <quic_llindhol@quicinc.com> | 1 | The xkb official name for the Arabic keyboard layout is 'ara'. |
---|---|---|---|
2 | However xkb has for at least the past 15 years also permitted it to | ||
3 | be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this | ||
4 | synoynm was removed, which breaks compilation of QEMU: | ||
2 | 5 | ||
3 | NUVIA was acquired by Qualcomm in March 2021, but kept functioning on | 6 | FAILED: pc-bios/keymaps/ar |
4 | separate infrastructure for a transitional period. We've now switched | 7 | /home/fred/qemu-git/src/qemu/build-full/qemu-keymap -f pc-bios/keymaps/ar -l ar |
5 | over to contributing as Qualcomm Innovation Center (quicinc), so update | 8 | xkbcommon: ERROR: Couldn't find file "symbols/ar" in include paths |
6 | my email address to reflect this. | 9 | xkbcommon: ERROR: 1 include paths searched: |
10 | xkbcommon: ERROR: /usr/share/X11/xkb | ||
11 | xkbcommon: ERROR: 3 include paths could not be added: | ||
12 | xkbcommon: ERROR: /home/fred/.config/xkb | ||
13 | xkbcommon: ERROR: /home/fred/.xkb | ||
14 | xkbcommon: ERROR: /etc/xkb | ||
15 | xkbcommon: ERROR: Abandoning symbols file "(unnamed)" | ||
16 | xkbcommon: ERROR: Failed to compile xkb_symbols | ||
17 | xkbcommon: ERROR: Failed to compile keymap | ||
7 | 18 | ||
8 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | 19 | The upstream xkeyboard-config change removing the compat |
9 | Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com | 20 | mapping is: |
10 | Cc: Leif Lindholm <leif@nuviainc.com> | 21 | https://gitlab.freedesktop.org/xkeyboard-config/xkeyboard-config/-/commit/470ad2cd8fea84d7210377161d86b31999bb5ea6 |
11 | Cc: Peter Maydell <peter.maydell@linaro.org> | 22 | |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 23 | Make QEMU always ask for the 'ara' xkb layout, which should work on |
13 | [Fixed commit message typo] | 24 | both older and newer xkeyboard-config. We leave the QEMU name for |
25 | this keyboard layout as 'ar'; it is not the only one where our name | ||
26 | for it deviates from the xkb standard name. | ||
27 | |||
28 | Cc: qemu-stable@nongnu.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
30 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
31 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
32 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | ||
33 | Message-id: 20230620162024.1132013-1-peter.maydell@linaro.org | ||
34 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1709 | ||
15 | --- | 35 | --- |
16 | .mailmap | 3 ++- | 36 | pc-bios/keymaps/meson.build | 2 +- |
17 | MAINTAINERS | 2 +- | 37 | 1 file changed, 1 insertion(+), 1 deletion(-) |
18 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
19 | 38 | ||
20 | diff --git a/.mailmap b/.mailmap | 39 | diff --git a/pc-bios/keymaps/meson.build b/pc-bios/keymaps/meson.build |
21 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/.mailmap | 41 | --- a/pc-bios/keymaps/meson.build |
23 | +++ b/.mailmap | 42 | +++ b/pc-bios/keymaps/meson.build |
24 | @@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com> | 43 | @@ -XXX,XX +XXX,XX @@ |
25 | Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> | 44 | keymaps = { |
26 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> | 45 | - 'ar': '-l ar', |
27 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> | 46 | + 'ar': '-l ara', |
28 | -Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org> | 47 | 'bepo': '-l fr -v dvorak', |
29 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> | 48 | 'cz': '-l cz', |
30 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> | 49 | 'da': '-l dk', |
31 | Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org> | ||
32 | Paul Burton <paulburton@kernel.org> <paul.burton@mips.com> | ||
33 | Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com> | ||
34 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/MAINTAINERS | ||
37 | +++ b/MAINTAINERS | ||
38 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h | ||
39 | SBSA-REF | ||
40 | M: Radoslaw Biernacki <rad@semihalf.com> | ||
41 | M: Peter Maydell <peter.maydell@linaro.org> | ||
42 | -R: Leif Lindholm <leif@nuviainc.com> | ||
43 | +R: Leif Lindholm <quic_llindhol@quicinc.com> | ||
44 | L: qemu-arm@nongnu.org | ||
45 | S: Maintained | ||
46 | F: hw/arm/sbsa-ref.c | ||
47 | -- | 50 | -- |
48 | 2.25.1 | 51 | 2.34.1 |
49 | 52 | ||
50 | 53 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Instead of starting with cortex-a15 and adding v8 features to | ||
4 | a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. | ||
5 | This fixes the long-standing to-do where we only enabled v8 | ||
6 | features for user-only. | ||
7 | |||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220506180242.216785-7-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- | ||
14 | 1 file changed, 92 insertions(+), 59 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/cpu_tcg.c | ||
19 | +++ b/target/arm/cpu_tcg.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
21 | static void arm_max_initfn(Object *obj) | ||
22 | { | ||
23 | ARMCPU *cpu = ARM_CPU(obj); | ||
24 | + uint32_t t; | ||
25 | |||
26 | - cortex_a15_initfn(obj); | ||
27 | + /* aarch64_a57_initfn, advertising none of the aarch64 features */ | ||
28 | + cpu->dtb_compatible = "arm,cortex-a57"; | ||
29 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
30 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
31 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
32 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
33 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
34 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
35 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
36 | + cpu->midr = 0x411fd070; | ||
37 | + cpu->revidr = 0x00000000; | ||
38 | + cpu->reset_fpsid = 0x41034070; | ||
39 | + cpu->isar.mvfr0 = 0x10110222; | ||
40 | + cpu->isar.mvfr1 = 0x12111111; | ||
41 | + cpu->isar.mvfr2 = 0x00000043; | ||
42 | + cpu->ctr = 0x8444c004; | ||
43 | + cpu->reset_sctlr = 0x00c50838; | ||
44 | + cpu->isar.id_pfr0 = 0x00000131; | ||
45 | + cpu->isar.id_pfr1 = 0x00011011; | ||
46 | + cpu->isar.id_dfr0 = 0x03010066; | ||
47 | + cpu->id_afr0 = 0x00000000; | ||
48 | + cpu->isar.id_mmfr0 = 0x10101105; | ||
49 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
50 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
51 | + cpu->isar.id_mmfr3 = 0x02102211; | ||
52 | + cpu->isar.id_isar0 = 0x02101110; | ||
53 | + cpu->isar.id_isar1 = 0x13112111; | ||
54 | + cpu->isar.id_isar2 = 0x21232042; | ||
55 | + cpu->isar.id_isar3 = 0x01112131; | ||
56 | + cpu->isar.id_isar4 = 0x00011142; | ||
57 | + cpu->isar.id_isar5 = 0x00011121; | ||
58 | + cpu->isar.id_isar6 = 0; | ||
59 | + cpu->isar.dbgdidr = 0x3516d000; | ||
60 | + cpu->clidr = 0x0a200023; | ||
61 | + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
62 | + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | ||
63 | + cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
64 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
65 | |||
66 | - /* old-style VFP short-vector support */ | ||
67 | - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
68 | + /* Add additional features supported by QEMU */ | ||
69 | + t = cpu->isar.id_isar5; | ||
70 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
71 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
72 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
73 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
74 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
75 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
76 | + cpu->isar.id_isar5 = t; | ||
77 | + | ||
78 | + t = cpu->isar.id_isar6; | ||
79 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
80 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
81 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
82 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
83 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
84 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
85 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
86 | + cpu->isar.id_isar6 = t; | ||
87 | + | ||
88 | + t = cpu->isar.mvfr1; | ||
89 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
90 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
91 | + cpu->isar.mvfr1 = t; | ||
92 | + | ||
93 | + t = cpu->isar.mvfr2; | ||
94 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
95 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
96 | + cpu->isar.mvfr2 = t; | ||
97 | + | ||
98 | + t = cpu->isar.id_mmfr3; | ||
99 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
100 | + cpu->isar.id_mmfr3 = t; | ||
101 | + | ||
102 | + t = cpu->isar.id_mmfr4; | ||
103 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
104 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
105 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
106 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
107 | + cpu->isar.id_mmfr4 = t; | ||
108 | + | ||
109 | + t = cpu->isar.id_pfr0; | ||
110 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
111 | + cpu->isar.id_pfr0 = t; | ||
112 | + | ||
113 | + t = cpu->isar.id_pfr2; | ||
114 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
115 | + cpu->isar.id_pfr2 = t; | ||
116 | |||
117 | #ifdef CONFIG_USER_ONLY | ||
118 | /* | ||
119 | - * We don't set these in system emulation mode for the moment, | ||
120 | - * since we don't correctly set (all of) the ID registers to | ||
121 | - * advertise them. | ||
122 | + * Break with true ARMv8 and add back old-style VFP short-vector support. | ||
123 | + * Only do this for user-mode, where -cpu max is the default, so that | ||
124 | + * older v6 and v7 programs are more likely to work without adjustment. | ||
125 | */ | ||
126 | - set_feature(&cpu->env, ARM_FEATURE_V8); | ||
127 | - { | ||
128 | - uint32_t t; | ||
129 | - | ||
130 | - t = cpu->isar.id_isar5; | ||
131 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
132 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
133 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
134 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
135 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
136 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
137 | - cpu->isar.id_isar5 = t; | ||
138 | - | ||
139 | - t = cpu->isar.id_isar6; | ||
140 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
141 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
142 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
143 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
144 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
145 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
146 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
147 | - cpu->isar.id_isar6 = t; | ||
148 | - | ||
149 | - t = cpu->isar.mvfr1; | ||
150 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
151 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
152 | - cpu->isar.mvfr1 = t; | ||
153 | - | ||
154 | - t = cpu->isar.mvfr2; | ||
155 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
156 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
157 | - cpu->isar.mvfr2 = t; | ||
158 | - | ||
159 | - t = cpu->isar.id_mmfr3; | ||
160 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
161 | - cpu->isar.id_mmfr3 = t; | ||
162 | - | ||
163 | - t = cpu->isar.id_mmfr4; | ||
164 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
165 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
166 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
167 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
168 | - cpu->isar.id_mmfr4 = t; | ||
169 | - | ||
170 | - t = cpu->isar.id_pfr0; | ||
171 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
172 | - cpu->isar.id_pfr0 = t; | ||
173 | - | ||
174 | - t = cpu->isar.id_pfr2; | ||
175 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
176 | - cpu->isar.id_pfr2 = t; | ||
177 | - } | ||
178 | -#endif /* CONFIG_USER_ONLY */ | ||
179 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
180 | +#endif | ||
181 | } | ||
182 | #endif /* !TARGET_AARCH64 */ | ||
183 | |||
184 | -- | ||
185 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | This adds cluster-id in CPU instance properties, which will be used | ||
4 | by arm/virt machine. Besides, the cluster-id is also verified or | ||
5 | dumped in various spots: | ||
6 | |||
7 | * hw/core/machine.c::machine_set_cpu_numa_node() to associate | ||
8 | CPU with its NUMA node. | ||
9 | |||
10 | * hw/core/machine.c::machine_numa_finish_cpu_init() to record | ||
11 | CPU slots with no NUMA mapping set. | ||
12 | |||
13 | * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump | ||
14 | cluster-id. | ||
15 | |||
16 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
17 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
18 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
19 | Message-id: 20220503140304.855514-2-gshan@redhat.com | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
21 | --- | ||
22 | qapi/machine.json | 6 ++++-- | ||
23 | hw/core/machine-hmp-cmds.c | 4 ++++ | ||
24 | hw/core/machine.c | 16 ++++++++++++++++ | ||
25 | 3 files changed, 24 insertions(+), 2 deletions(-) | ||
26 | |||
27 | diff --git a/qapi/machine.json b/qapi/machine.json | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/qapi/machine.json | ||
30 | +++ b/qapi/machine.json | ||
31 | @@ -XXX,XX +XXX,XX @@ | ||
32 | # @node-id: NUMA node ID the CPU belongs to | ||
33 | # @socket-id: socket number within node/board the CPU belongs to | ||
34 | # @die-id: die number within socket the CPU belongs to (since 4.1) | ||
35 | -# @core-id: core number within die the CPU belongs to | ||
36 | +# @cluster-id: cluster number within die the CPU belongs to (since 7.1) | ||
37 | +# @core-id: core number within cluster the CPU belongs to | ||
38 | # @thread-id: thread number within core the CPU belongs to | ||
39 | # | ||
40 | -# Note: currently there are 5 properties that could be present | ||
41 | +# Note: currently there are 6 properties that could be present | ||
42 | # but management should be prepared to pass through other | ||
43 | # properties with device_add command to allow for future | ||
44 | # interface extension. This also requires the filed names to be kept in | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | 'data': { '*node-id': 'int', | ||
47 | '*socket-id': 'int', | ||
48 | '*die-id': 'int', | ||
49 | + '*cluster-id': 'int', | ||
50 | '*core-id': 'int', | ||
51 | '*thread-id': 'int' | ||
52 | } | ||
53 | diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/hw/core/machine-hmp-cmds.c | ||
56 | +++ b/hw/core/machine-hmp-cmds.c | ||
57 | @@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) | ||
58 | if (c->has_die_id) { | ||
59 | monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); | ||
60 | } | ||
61 | + if (c->has_cluster_id) { | ||
62 | + monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n", | ||
63 | + c->cluster_id); | ||
64 | + } | ||
65 | if (c->has_core_id) { | ||
66 | monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); | ||
67 | } | ||
68 | diff --git a/hw/core/machine.c b/hw/core/machine.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/core/machine.c | ||
71 | +++ b/hw/core/machine.c | ||
72 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | ||
73 | return; | ||
74 | } | ||
75 | |||
76 | + if (props->has_cluster_id && !slot->props.has_cluster_id) { | ||
77 | + error_setg(errp, "cluster-id is not supported"); | ||
78 | + return; | ||
79 | + } | ||
80 | + | ||
81 | if (props->has_socket_id && !slot->props.has_socket_id) { | ||
82 | error_setg(errp, "socket-id is not supported"); | ||
83 | return; | ||
84 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | ||
85 | continue; | ||
86 | } | ||
87 | |||
88 | + if (props->has_cluster_id && | ||
89 | + props->cluster_id != slot->props.cluster_id) { | ||
90 | + continue; | ||
91 | + } | ||
92 | + | ||
93 | if (props->has_die_id && props->die_id != slot->props.die_id) { | ||
94 | continue; | ||
95 | } | ||
96 | @@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu) | ||
97 | } | ||
98 | g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); | ||
99 | } | ||
100 | + if (cpu->props.has_cluster_id) { | ||
101 | + if (s->len) { | ||
102 | + g_string_append_printf(s, ", "); | ||
103 | + } | ||
104 | + g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); | ||
105 | + } | ||
106 | if (cpu->props.has_core_id) { | ||
107 | if (s->len) { | ||
108 | g_string_append_printf(s, ", "); | ||
109 | -- | ||
110 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | Currently, the SMP configuration isn't considered when the CPU | ||
4 | topology is populated. In this case, it's impossible to provide | ||
5 | the default CPU-to-NUMA mapping or association based on the socket | ||
6 | ID of the given CPU. | ||
7 | |||
8 | This takes account of SMP configuration when the CPU topology | ||
9 | is populated. The die ID for the given CPU isn't assigned since | ||
10 | it's not supported on arm/virt machine. Besides, the used SMP | ||
11 | configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted | ||
12 | to avoid testing failure | ||
13 | |||
14 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
15 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
16 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
17 | Message-id: 20220503140304.855514-4-gshan@redhat.com | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | hw/arm/virt.c | 15 ++++++++++++++- | ||
21 | 1 file changed, 14 insertions(+), 1 deletion(-) | ||
22 | |||
23 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/hw/arm/virt.c | ||
26 | +++ b/hw/arm/virt.c | ||
27 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | ||
28 | int n; | ||
29 | unsigned int max_cpus = ms->smp.max_cpus; | ||
30 | VirtMachineState *vms = VIRT_MACHINE(ms); | ||
31 | + MachineClass *mc = MACHINE_GET_CLASS(vms); | ||
32 | |||
33 | if (ms->possible_cpus) { | ||
34 | assert(ms->possible_cpus->len == max_cpus); | ||
35 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | ||
36 | ms->possible_cpus->cpus[n].type = ms->cpu_type; | ||
37 | ms->possible_cpus->cpus[n].arch_id = | ||
38 | virt_cpu_mp_affinity(vms, n); | ||
39 | + | ||
40 | + assert(!mc->smp_props.dies_supported); | ||
41 | + ms->possible_cpus->cpus[n].props.has_socket_id = true; | ||
42 | + ms->possible_cpus->cpus[n].props.socket_id = | ||
43 | + n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); | ||
44 | + ms->possible_cpus->cpus[n].props.has_cluster_id = true; | ||
45 | + ms->possible_cpus->cpus[n].props.cluster_id = | ||
46 | + (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; | ||
47 | + ms->possible_cpus->cpus[n].props.has_core_id = true; | ||
48 | + ms->possible_cpus->cpus[n].props.core_id = | ||
49 | + (n / ms->smp.threads) % ms->smp.cores; | ||
50 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | ||
51 | - ms->possible_cpus->cpus[n].props.thread_id = n; | ||
52 | + ms->possible_cpus->cpus[n].props.thread_id = | ||
53 | + n % ms->smp.threads; | ||
54 | } | ||
55 | return ms->possible_cpus; | ||
56 | } | ||
57 | -- | ||
58 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | In aarch64_numa_cpu(), the CPU and NUMA association is something | ||
4 | like below. Two threads in the same core/cluster/socket are | ||
5 | associated with two individual NUMA nodes, which is unreal as | ||
6 | Igor Mammedov mentioned. We don't expect the association to break | ||
7 | NUMA-to-socket boundary, which matches with the real world. | ||
8 | |||
9 | NUMA-node socket cluster core thread | ||
10 | ------------------------------------------ | ||
11 | 0 0 0 0 0 | ||
12 | 1 0 0 0 1 | ||
13 | |||
14 | This corrects the topology for CPUs and their association with | ||
15 | NUMA nodes. After this patch is applied, the CPU and NUMA | ||
16 | association becomes something like below, which looks real. | ||
17 | Besides, socket/cluster/core/thread IDs are all checked when | ||
18 | the NUMA node IDs are verified. It helps to check if the CPU | ||
19 | topology is properly populated or not. | ||
20 | |||
21 | NUMA-node socket cluster core thread | ||
22 | ------------------------------------------ | ||
23 | 0 1 0 0 0 | ||
24 | 1 0 0 0 0 | ||
25 | |||
26 | Suggested-by: Igor Mammedov <imammedo@redhat.com> | ||
27 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
28 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
29 | Message-id: 20220503140304.855514-5-gshan@redhat.com | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
31 | --- | ||
32 | tests/qtest/numa-test.c | 18 ++++++++++++------ | ||
33 | 1 file changed, 12 insertions(+), 6 deletions(-) | ||
34 | |||
35 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/tests/qtest/numa-test.c | ||
38 | +++ b/tests/qtest/numa-test.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | ||
40 | g_autofree char *cli = NULL; | ||
41 | |||
42 | cli = make_cli(data, "-machine " | ||
43 | - "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " | ||
44 | + "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 " | ||
45 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " | ||
46 | - "-numa cpu,node-id=1,thread-id=0 " | ||
47 | - "-numa cpu,node-id=0,thread-id=1"); | ||
48 | + "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 " | ||
49 | + "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0"); | ||
50 | qts = qtest_init(cli); | ||
51 | cpus = get_cpus(qts, &resp); | ||
52 | g_assert(cpus); | ||
53 | |||
54 | while ((e = qlist_pop(cpus))) { | ||
55 | QDict *cpu, *props; | ||
56 | - int64_t thread, node; | ||
57 | + int64_t socket, cluster, core, thread, node; | ||
58 | |||
59 | cpu = qobject_to(QDict, e); | ||
60 | g_assert(qdict_haskey(cpu, "props")); | ||
61 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | ||
62 | |||
63 | g_assert(qdict_haskey(props, "node-id")); | ||
64 | node = qdict_get_int(props, "node-id"); | ||
65 | + g_assert(qdict_haskey(props, "socket-id")); | ||
66 | + socket = qdict_get_int(props, "socket-id"); | ||
67 | + g_assert(qdict_haskey(props, "cluster-id")); | ||
68 | + cluster = qdict_get_int(props, "cluster-id"); | ||
69 | + g_assert(qdict_haskey(props, "core-id")); | ||
70 | + core = qdict_get_int(props, "core-id"); | ||
71 | g_assert(qdict_haskey(props, "thread-id")); | ||
72 | thread = qdict_get_int(props, "thread-id"); | ||
73 | |||
74 | - if (thread == 0) { | ||
75 | + if (socket == 0 && cluster == 0 && core == 0 && thread == 0) { | ||
76 | g_assert_cmpint(node, ==, 1); | ||
77 | - } else if (thread == 1) { | ||
78 | + } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) { | ||
79 | g_assert_cmpint(node, ==, 0); | ||
80 | } else { | ||
81 | g_assert(false); | ||
82 | -- | ||
83 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | When CPU-to-NUMA association isn't explicitly provided by users, | ||
4 | the default one is given by mc->get_default_cpu_node_id(). However, | ||
5 | the CPU topology isn't fully considered in the default association | ||
6 | and this causes CPU topology broken warnings on booting Linux guest. | ||
7 | |||
8 | For example, the following warning messages are observed when the | ||
9 | Linux guest is booted with the following command lines. | ||
10 | |||
11 | /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ | ||
12 | -accel kvm -machine virt,gic-version=host \ | ||
13 | -cpu host \ | ||
14 | -smp 6,sockets=2,cores=3,threads=1 \ | ||
15 | -m 1024M,slots=16,maxmem=64G \ | ||
16 | -object memory-backend-ram,id=mem0,size=128M \ | ||
17 | -object memory-backend-ram,id=mem1,size=128M \ | ||
18 | -object memory-backend-ram,id=mem2,size=128M \ | ||
19 | -object memory-backend-ram,id=mem3,size=128M \ | ||
20 | -object memory-backend-ram,id=mem4,size=128M \ | ||
21 | -object memory-backend-ram,id=mem4,size=384M \ | ||
22 | -numa node,nodeid=0,memdev=mem0 \ | ||
23 | -numa node,nodeid=1,memdev=mem1 \ | ||
24 | -numa node,nodeid=2,memdev=mem2 \ | ||
25 | -numa node,nodeid=3,memdev=mem3 \ | ||
26 | -numa node,nodeid=4,memdev=mem4 \ | ||
27 | -numa node,nodeid=5,memdev=mem5 | ||
28 | : | ||
29 | alternatives: patching kernel code | ||
30 | BUG: arch topology borken | ||
31 | the CLS domain not a subset of the MC domain | ||
32 | <the above error log repeats> | ||
33 | BUG: arch topology borken | ||
34 | the DIE domain not a subset of the NODE domain | ||
35 | |||
36 | With current implementation of mc->get_default_cpu_node_id(), | ||
37 | CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately. | ||
38 | That's incorrect because CPU#0/1/2 should be associated with same | ||
39 | NUMA node because they're seated in same socket. | ||
40 | |||
41 | This fixes the issue by considering the socket ID when the default | ||
42 | CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids(). | ||
43 | With this applied, no more CPU topology broken warnings are seen | ||
44 | from the Linux guest. The 6 CPUs are associated with NODE#0/1, but | ||
45 | there are no CPUs associated with NODE#2/3/4/5. | ||
46 | |||
47 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
48 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
49 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
50 | Message-id: 20220503140304.855514-6-gshan@redhat.com | ||
51 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
52 | --- | ||
53 | hw/arm/virt.c | 4 +++- | ||
54 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
55 | |||
56 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/arm/virt.c | ||
59 | +++ b/hw/arm/virt.c | ||
60 | @@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | ||
61 | |||
62 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) | ||
63 | { | ||
64 | - return idx % ms->numa_state->num_nodes; | ||
65 | + int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; | ||
66 | + | ||
67 | + return socket_id % ms->numa_state->num_nodes; | ||
68 | } | ||
69 | |||
70 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | ||
71 | -- | ||
72 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | When the PPTT table is built, the CPU topology is re-calculated, but | ||
4 | it's unecessary because the CPU topology has been populated in | ||
5 | virt_possible_cpu_arch_ids() on arm/virt machine. | ||
6 | |||
7 | This reworks build_pptt() to avoid by reusing the existing IDs in | ||
8 | ms->possible_cpus. Currently, the only user of build_pptt() is | ||
9 | arm/virt machine. | ||
10 | |||
11 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
12 | Tested-by: Yanan Wang <wangyanan55@huawei.com> | ||
13 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
14 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
15 | Acked-by: Michael S. Tsirkin <mst@redhat.com> | ||
16 | Message-id: 20220503140304.855514-7-gshan@redhat.com | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | hw/acpi/aml-build.c | 111 +++++++++++++++++++------------------------- | ||
20 | 1 file changed, 48 insertions(+), 63 deletions(-) | ||
21 | |||
22 | diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/hw/acpi/aml-build.c | ||
25 | +++ b/hw/acpi/aml-build.c | ||
26 | @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, | ||
27 | const char *oem_id, const char *oem_table_id) | ||
28 | { | ||
29 | MachineClass *mc = MACHINE_GET_CLASS(ms); | ||
30 | - GQueue *list = g_queue_new(); | ||
31 | - guint pptt_start = table_data->len; | ||
32 | - guint parent_offset; | ||
33 | - guint length, i; | ||
34 | - int uid = 0; | ||
35 | - int socket; | ||
36 | + CPUArchIdList *cpus = ms->possible_cpus; | ||
37 | + int64_t socket_id = -1, cluster_id = -1, core_id = -1; | ||
38 | + uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0; | ||
39 | + uint32_t pptt_start = table_data->len; | ||
40 | + int n; | ||
41 | AcpiTable table = { .sig = "PPTT", .rev = 2, | ||
42 | .oem_id = oem_id, .oem_table_id = oem_table_id }; | ||
43 | |||
44 | acpi_table_begin(&table, table_data); | ||
45 | |||
46 | - for (socket = 0; socket < ms->smp.sockets; socket++) { | ||
47 | - g_queue_push_tail(list, | ||
48 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
49 | - build_processor_hierarchy_node( | ||
50 | - table_data, | ||
51 | - /* | ||
52 | - * Physical package - represents the boundary | ||
53 | - * of a physical package | ||
54 | - */ | ||
55 | - (1 << 0), | ||
56 | - 0, socket, NULL, 0); | ||
57 | - } | ||
58 | - | ||
59 | - if (mc->smp_props.clusters_supported) { | ||
60 | - length = g_queue_get_length(list); | ||
61 | - for (i = 0; i < length; i++) { | ||
62 | - int cluster; | ||
63 | - | ||
64 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
65 | - for (cluster = 0; cluster < ms->smp.clusters; cluster++) { | ||
66 | - g_queue_push_tail(list, | ||
67 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
68 | - build_processor_hierarchy_node( | ||
69 | - table_data, | ||
70 | - (0 << 0), /* not a physical package */ | ||
71 | - parent_offset, cluster, NULL, 0); | ||
72 | - } | ||
73 | + /* | ||
74 | + * This works with the assumption that cpus[n].props.*_id has been | ||
75 | + * sorted from top to down levels in mc->possible_cpu_arch_ids(). | ||
76 | + * Otherwise, the unexpected and duplicated containers will be | ||
77 | + * created. | ||
78 | + */ | ||
79 | + for (n = 0; n < cpus->len; n++) { | ||
80 | + if (cpus->cpus[n].props.socket_id != socket_id) { | ||
81 | + assert(cpus->cpus[n].props.socket_id > socket_id); | ||
82 | + socket_id = cpus->cpus[n].props.socket_id; | ||
83 | + cluster_id = -1; | ||
84 | + core_id = -1; | ||
85 | + socket_offset = table_data->len - pptt_start; | ||
86 | + build_processor_hierarchy_node(table_data, | ||
87 | + (1 << 0), /* Physical package */ | ||
88 | + 0, socket_id, NULL, 0); | ||
89 | } | ||
90 | - } | ||
91 | |||
92 | - length = g_queue_get_length(list); | ||
93 | - for (i = 0; i < length; i++) { | ||
94 | - int core; | ||
95 | - | ||
96 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
97 | - for (core = 0; core < ms->smp.cores; core++) { | ||
98 | - if (ms->smp.threads > 1) { | ||
99 | - g_queue_push_tail(list, | ||
100 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
101 | - build_processor_hierarchy_node( | ||
102 | - table_data, | ||
103 | - (0 << 0), /* not a physical package */ | ||
104 | - parent_offset, core, NULL, 0); | ||
105 | - } else { | ||
106 | - build_processor_hierarchy_node( | ||
107 | - table_data, | ||
108 | - (1 << 1) | /* ACPI Processor ID valid */ | ||
109 | - (1 << 3), /* Node is a Leaf */ | ||
110 | - parent_offset, uid++, NULL, 0); | ||
111 | + if (mc->smp_props.clusters_supported) { | ||
112 | + if (cpus->cpus[n].props.cluster_id != cluster_id) { | ||
113 | + assert(cpus->cpus[n].props.cluster_id > cluster_id); | ||
114 | + cluster_id = cpus->cpus[n].props.cluster_id; | ||
115 | + core_id = -1; | ||
116 | + cluster_offset = table_data->len - pptt_start; | ||
117 | + build_processor_hierarchy_node(table_data, | ||
118 | + (0 << 0), /* Not a physical package */ | ||
119 | + socket_offset, cluster_id, NULL, 0); | ||
120 | } | ||
121 | + } else { | ||
122 | + cluster_offset = socket_offset; | ||
123 | } | ||
124 | - } | ||
125 | |||
126 | - length = g_queue_get_length(list); | ||
127 | - for (i = 0; i < length; i++) { | ||
128 | - int thread; | ||
129 | + if (ms->smp.threads == 1) { | ||
130 | + build_processor_hierarchy_node(table_data, | ||
131 | + (1 << 1) | /* ACPI Processor ID valid */ | ||
132 | + (1 << 3), /* Node is a Leaf */ | ||
133 | + cluster_offset, n, NULL, 0); | ||
134 | + } else { | ||
135 | + if (cpus->cpus[n].props.core_id != core_id) { | ||
136 | + assert(cpus->cpus[n].props.core_id > core_id); | ||
137 | + core_id = cpus->cpus[n].props.core_id; | ||
138 | + core_offset = table_data->len - pptt_start; | ||
139 | + build_processor_hierarchy_node(table_data, | ||
140 | + (0 << 0), /* Not a physical package */ | ||
141 | + cluster_offset, core_id, NULL, 0); | ||
142 | + } | ||
143 | |||
144 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
145 | - for (thread = 0; thread < ms->smp.threads; thread++) { | ||
146 | - build_processor_hierarchy_node( | ||
147 | - table_data, | ||
148 | + build_processor_hierarchy_node(table_data, | ||
149 | (1 << 1) | /* ACPI Processor ID valid */ | ||
150 | (1 << 2) | /* Processor is a Thread */ | ||
151 | (1 << 3), /* Node is a Leaf */ | ||
152 | - parent_offset, uid++, NULL, 0); | ||
153 | + core_offset, n, NULL, 0); | ||
154 | } | ||
155 | } | ||
156 | |||
157 | - g_queue_free(list); | ||
158 | acpi_table_end(linker, &table); | ||
159 | } | ||
160 | |||
161 | -- | ||
162 | 2.25.1 | diff view generated by jsdifflib |