[PULL 00/32] target-arm queue
[PULL 00/33] target-arm queue
1
target-arm queue: the big stuff here is the final part of
1
Hi; here's a target-arm pullreq. Mostly this is some decodetree
2
rth's patches for Cortex-A76 and Neoverse-N1 support;
2
conversion patches from me, plus a scattering of other bug fixes.
3
also present are Gavin's NUMA series and a few other things.
4
3
5
thanks
4
thanks
6
-- PMM
5
-- PMM
7
6
8
The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
7
The following changes since commit e3660cc1e3cb136af50c0eaaeac27943c2438d1d:
9
8
10
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
9
Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into staging (2023-06-16 12:30:16 +0200)
11
10
12
are available in the Git repository at:
11
are available in the Git repository at:
13
12
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230619
15
14
16
for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
15
for you to fetch changes up to 074259c0f2ac40042dce766d870318cc22f388eb:
17
16
18
hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
17
hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property (2023-06-19 15:27:21 +0100)
19
18
20
----------------------------------------------------------------
19
----------------------------------------------------------------
21
target-arm queue:
20
target-arm queue:
22
* MAINTAINERS/.mailmap: update email for Leif Lindholm
21
* Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
23
* hw/arm: add version information to sbsa-ref machine DT
22
* Return correct result for LDG when ATA=0
24
* Enable new features for -cpu max:
23
* Conversion of system insns, loads and stores to decodetree
25
FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
24
* hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
26
FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
25
* hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
27
* Emulate Cortex-A76
26
* hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop
28
* Emulate Neoverse-N1
27
* hw/arm/Kconfig: sbsa-ref uses Bochs display
29
* Fix the virt board default NUMA topology
28
* imx_serial: set wake bit when we receive a data byte
29
* docs: sbsa: document board to firmware interface
30
* hw/misc/bcm2835_property: avoid hard-coded constants
30
31
31
----------------------------------------------------------------
32
----------------------------------------------------------------
32
Gavin Shan (6):
33
Marcin Juszkiewicz (2):
33
qapi/machine.json: Add cluster-id
34
hw/arm/Kconfig: sbsa-ref uses Bochs display
34
qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
35
docs: sbsa: document board to firmware interface
35
hw/arm/virt: Consider SMP configuration in CPU topology
36
qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
37
hw/arm/virt: Fix CPU's default NUMA node ID
38
hw/acpi/aml-build: Use existing CPU topology to build PPTT table
39
36
40
Leif Lindholm (2):
37
Martin Kaiser (1):
41
MAINTAINERS/.mailmap: update email for Leif Lindholm
38
imx_serial: set wake bit when we receive a data byte
42
hw/arm: add versioning to sbsa-ref machine DT
43
39
44
Richard Henderson (24):
40
Peter Maydell (26):
45
target/arm: Handle cpreg registration for missing EL
41
target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
46
target/arm: Drop EL3 no EL2 fallbacks
42
target/arm: Return correct result for LDG when ATA=0
47
target/arm: Merge zcr reginfo
43
target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode
48
target/arm: Adjust definition of CONTEXTIDR_EL2
44
target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores
49
target/arm: Move cortex impdef sysregs to cpu_tcg.c
45
target/arm: Convert hint instruction space to decodetree
50
target/arm: Update qemu-system-arm -cpu max to cortex-a57
46
target/arm: Convert barrier insns to decodetree
51
target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
47
target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree
52
target/arm: Split out aa32_max_features
48
target/arm: Convert MSR (immediate) to decodetree
53
target/arm: Annotate arm_max_initfn with FEAT identifiers
49
target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree
54
target/arm: Use field names for manipulating EL2 and EL3 modes
50
target/arm: Convert exception generation instructions to decodetree
55
target/arm: Enable FEAT_Debugv8p2 for -cpu max
51
target/arm: Convert load/store exclusive and ordered to decodetree
56
target/arm: Enable FEAT_Debugv8p4 for -cpu max
52
target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
57
target/arm: Add minimal RAS registers
53
target/arm: Convert load reg (literal) group to decodetree
58
target/arm: Enable SCR and HCR bits for RAS
54
target/arm: Convert load/store-pair to decodetree
59
target/arm: Implement virtual SError exceptions
55
target/arm: Convert ld/st reg+imm9 insns to decodetree
60
target/arm: Implement ESB instruction
56
target/arm: Convert LDR/STR with 12-bit immediate to decodetree
61
target/arm: Enable FEAT_RAS for -cpu max
57
target/arm: Convert LDR/STR reg+reg to decodetree
62
target/arm: Enable FEAT_IESB for -cpu max
58
target/arm: Convert atomic memory ops to decodetree
63
target/arm: Enable FEAT_CSV2 for -cpu max
59
target/arm: Convert load (pointer auth) insns to decodetree
64
target/arm: Enable FEAT_CSV2_2 for -cpu max
60
target/arm: Convert LDAPR/STLR (imm) to decodetree
65
target/arm: Enable FEAT_CSV3 for -cpu max
61
target/arm: Convert load/store (multiple structures) to decodetree
66
target/arm: Enable FEAT_DGH for -cpu max
62
target/arm: Convert load/store single structure to decodetree
67
target/arm: Define cortex-a76
63
target/arm: Convert load/store tags insns to decodetree
68
target/arm: Define neoverse-n1
64
hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
65
hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
66
hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop
69
67
70
docs/system/arm/emulation.rst | 10 +
68
Sergey Kambalin (4):
71
docs/system/arm/virt.rst | 2 +
69
hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h'
72
qapi/machine.json | 6 +-
70
hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitions
73
target/arm/cpregs.h | 11 +
71
hw/misc/bcm2835_property: Replace magic frequency values by definitions
74
target/arm/cpu.h | 23 ++
72
hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property
75
target/arm/helper.h | 1 +
73
76
target/arm/internals.h | 16 ++
74
docs/system/arm/sbsa.rst | 38 +-
77
target/arm/syndrome.h | 5 +
75
include/hw/arm/raspi_platform.h | 10 +
78
target/arm/a32.decode | 16 +-
76
include/hw/char/imx_serial.h | 1 +
79
target/arm/t32.decode | 18 +-
77
include/hw/misc/raspberrypi-fw-defs.h | 163 ++
80
hw/acpi/aml-build.c | 111 ++++----
78
target/arm/tcg/a64.decode | 403 ++++
81
hw/arm/sbsa-ref.c | 16 ++
79
hw/char/imx_serial.c | 5 +-
82
hw/arm/virt.c | 21 +-
80
hw/intc/allwinner-a10-pic.c | 2 +-
83
hw/core/machine-hmp-cmds.c | 4 +
81
hw/misc/bcm2835_property.c | 112 +-
84
hw/core/machine.c | 16 ++
82
hw/sd/allwinner-sdhost.c | 2 +-
85
target/arm/cpu.c | 66 ++++-
83
hw/timer/nrf51_timer.c | 7 +-
86
target/arm/cpu64.c | 353 ++++++++++++++-----------
84
target/arm/tcg/translate-a64.c | 3319 +++++++++++++++------------------
87
target/arm/cpu_tcg.c | 227 +++++++++++-----
85
hw/arm/Kconfig | 1 +
88
target/arm/helper.c | 600 +++++++++++++++++++++++++-----------------
86
12 files changed, 2157 insertions(+), 1906 deletions(-)
89
target/arm/op_helper.c | 43 +++
87
create mode 100644 include/hw/misc/raspberrypi-fw-defs.h
90
target/arm/translate-a64.c | 18 ++
91
target/arm/translate.c | 23 ++
92
tests/qtest/numa-test.c | 19 +-
93
.mailmap | 3 +-
94
MAINTAINERS | 2 +-
95
25 files changed, 1068 insertions(+), 562 deletions(-)
diff view generated by jsdifflib
[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
[PULL 01/33] target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
1
From: Gavin Shan <gshan@redhat.com>
1
The atomic memory operations are supposed to return the old memory
2
data value in the destination register. This value is not
3
sign-extended, even if the operation is the signed minimum or
4
maximum. (In the pseudocode for the instructions the returned data
5
value is passed to ZeroExtend() to create the value in the register.)
2
6
3
In aarch64_numa_cpu(), the CPU and NUMA association is something
7
We got this wrong because we were doing a 32-to-64 zero extend on the
4
like below. Two threads in the same core/cluster/socket are
8
result for 8 and 16 bit data values, rather than the correct amount
5
associated with two individual NUMA nodes, which is unreal as
9
of zero extension.
6
Igor Mammedov mentioned. We don't expect the association to break
7
NUMA-to-socket boundary, which matches with the real world.
8
10
9
NUMA-node socket cluster core thread
11
Fix the bug by using ext8u and ext16u for the MO_8 and MO_16 data
10
------------------------------------------
12
sizes rather than ext32u.
11
0 0 0 0 0
12
1 0 0 0 1
13
13
14
This corrects the topology for CPUs and their association with
14
Cc: qemu-stable@nongnu.org
15
NUMA nodes. After this patch is applied, the CPU and NUMA
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
association becomes something like below, which looks real.
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Besides, socket/cluster/core/thread IDs are all checked when
17
Message-id: 20230602155223.2040685-2-peter.maydell@linaro.org
18
the NUMA node IDs are verified. It helps to check if the CPU
18
---
19
topology is properly populated or not.
19
target/arm/tcg/translate-a64.c | 18 ++++++++++++++++--
20
1 file changed, 16 insertions(+), 2 deletions(-)
20
21
21
NUMA-node socket cluster core thread
22
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
22
------------------------------------------
23
0 1 0 0 0
24
1 0 0 0 0
25
26
Suggested-by: Igor Mammedov <imammedo@redhat.com>
27
Signed-off-by: Gavin Shan <gshan@redhat.com>
28
Acked-by: Igor Mammedov <imammedo@redhat.com>
29
Message-id: 20220503140304.855514-5-gshan@redhat.com
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
32
tests/qtest/numa-test.c | 18 ++++++++++++------
33
1 file changed, 12 insertions(+), 6 deletions(-)
34
35
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
36
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
37
--- a/tests/qtest/numa-test.c
24
--- a/target/arm/tcg/translate-a64.c
38
+++ b/tests/qtest/numa-test.c
25
+++ b/target/arm/tcg/translate-a64.c
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
26
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
40
g_autofree char *cli = NULL;
27
*/
41
28
fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop);
42
cli = make_cli(data, "-machine "
29
43
- "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
30
- if ((mop & MO_SIGN) && size != MO_64) {
44
+ "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
31
- tcg_gen_ext32u_i64(tcg_rt, tcg_rt);
45
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
32
+ if (mop & MO_SIGN) {
46
- "-numa cpu,node-id=1,thread-id=0 "
33
+ switch (size) {
47
- "-numa cpu,node-id=0,thread-id=1");
34
+ case MO_8:
48
+ "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
35
+ tcg_gen_ext8u_i64(tcg_rt, tcg_rt);
49
+ "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
36
+ break;
50
qts = qtest_init(cli);
37
+ case MO_16:
51
cpus = get_cpus(qts, &resp);
38
+ tcg_gen_ext16u_i64(tcg_rt, tcg_rt);
52
g_assert(cpus);
39
+ break;
53
40
+ case MO_32:
54
while ((e = qlist_pop(cpus))) {
41
+ tcg_gen_ext32u_i64(tcg_rt, tcg_rt);
55
QDict *cpu, *props;
42
+ break;
56
- int64_t thread, node;
43
+ case MO_64:
57
+ int64_t socket, cluster, core, thread, node;
44
+ break;
58
45
+ default:
59
cpu = qobject_to(QDict, e);
46
+ g_assert_not_reached();
60
g_assert(qdict_haskey(cpu, "props"));
47
+ }
61
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
48
}
62
49
}
63
g_assert(qdict_haskey(props, "node-id"));
50
64
node = qdict_get_int(props, "node-id");
65
+ g_assert(qdict_haskey(props, "socket-id"));
66
+ socket = qdict_get_int(props, "socket-id");
67
+ g_assert(qdict_haskey(props, "cluster-id"));
68
+ cluster = qdict_get_int(props, "cluster-id");
69
+ g_assert(qdict_haskey(props, "core-id"));
70
+ core = qdict_get_int(props, "core-id");
71
g_assert(qdict_haskey(props, "thread-id"));
72
thread = qdict_get_int(props, "thread-id");
73
74
- if (thread == 0) {
75
+ if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
76
g_assert_cmpint(node, ==, 1);
77
- } else if (thread == 1) {
78
+ } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
79
g_assert_cmpint(node, ==, 0);
80
} else {
81
g_assert(false);
82
--
51
--
83
2.25.1
52
2.34.1
diff view generated by jsdifflib
[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
[PULL 02/33] target/arm: Return correct result for LDG when ATA=0
1
From: Gavin Shan <gshan@redhat.com>
1
The LDG instruction loads the tag from a memory address (identified
2
by [Xn + offset]), and then merges that tag into the destination
3
register Xt. We implemented this correctly for the case when
4
allocation tags are enabled, but didn't get it right when ATA=0:
5
instead of merging the tag bits into Xt, we merged them into the
6
memory address [Xn + offset] and then set Xt to that.
2
7
3
Currently, the SMP configuration isn't considered when the CPU
8
Merge the tag bits into the old Xt value, as they should be.
4
topology is populated. In this case, it's impossible to provide
5
the default CPU-to-NUMA mapping or association based on the socket
6
ID of the given CPU.
7
9
8
This takes account of SMP configuration when the CPU topology
10
Cc: qemu-stable@nongnu.org
9
is populated. The die ID for the given CPU isn't assigned since
11
Fixes: c15294c1e36a7dd9b25 ("target/arm: Implement LDG, STG, ST2G instructions")
10
it's not supported on arm/virt machine. Besides, the used SMP
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
12
to avoid testing failure
13
14
Signed-off-by: Gavin Shan <gshan@redhat.com>
15
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
16
Acked-by: Igor Mammedov <imammedo@redhat.com>
17
Message-id: 20220503140304.855514-4-gshan@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
14
---
20
hw/arm/virt.c | 15 ++++++++++++++-
15
target/arm/tcg/translate-a64.c | 6 +++++-
21
1 file changed, 14 insertions(+), 1 deletion(-)
16
1 file changed, 5 insertions(+), 1 deletion(-)
22
17
23
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
24
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/virt.c
20
--- a/target/arm/tcg/translate-a64.c
26
+++ b/hw/arm/virt.c
21
+++ b/target/arm/tcg/translate-a64.c
27
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
22
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
28
int n;
23
if (s->ata) {
29
unsigned int max_cpus = ms->smp.max_cpus;
24
gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt);
30
VirtMachineState *vms = VIRT_MACHINE(ms);
25
} else {
31
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
26
+ /*
32
27
+ * Tag access disabled: we must check for aborts on the load
33
if (ms->possible_cpus) {
28
+ * load from [rn+offset], and then insert a 0 tag into rt.
34
assert(ms->possible_cpus->len == max_cpus);
29
+ */
35
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
30
clean_addr = clean_data_tbi(s, addr);
36
ms->possible_cpus->cpus[n].type = ms->cpu_type;
31
gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8);
37
ms->possible_cpus->cpus[n].arch_id =
32
- gen_address_with_allocation_tag0(tcg_rt, addr);
38
virt_cpu_mp_affinity(vms, n);
33
+ gen_address_with_allocation_tag0(tcg_rt, tcg_rt);
39
+
34
}
40
+ assert(!mc->smp_props.dies_supported);
35
} else {
41
+ ms->possible_cpus->cpus[n].props.has_socket_id = true;
36
tcg_rt = cpu_reg_sp(s, rt);
42
+ ms->possible_cpus->cpus[n].props.socket_id =
43
+ n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
44
+ ms->possible_cpus->cpus[n].props.has_cluster_id = true;
45
+ ms->possible_cpus->cpus[n].props.cluster_id =
46
+ (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
47
+ ms->possible_cpus->cpus[n].props.has_core_id = true;
48
+ ms->possible_cpus->cpus[n].props.core_id =
49
+ (n / ms->smp.threads) % ms->smp.cores;
50
ms->possible_cpus->cpus[n].props.has_thread_id = true;
51
- ms->possible_cpus->cpus[n].props.thread_id = n;
52
+ ms->possible_cpus->cpus[n].props.thread_id =
53
+ n % ms->smp.threads;
54
}
55
return ms->possible_cpus;
56
}
57
--
37
--
58
2.25.1
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/33] target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode
1
In disas_ldst_reg_imm9() we missed one place where a call to
2
a gen_mte_check* function should now be passed the memop we
3
have created rather than just being passed the size. Fix this.
1
4
5
Fixes: 0a9091424d ("target/arm: Pass memop to gen_mte_check1*")
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
---
10
target/arm/tcg/translate-a64.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/translate-a64.c
16
+++ b/target/arm/tcg/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
18
19
clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store,
20
writeback || rn != 31,
21
- size, is_unpriv, memidx);
22
+ memop, is_unpriv, memidx);
23
24
if (is_vector) {
25
if (is_store) {
26
--
27
2.34.1
28
29
diff view generated by jsdifflib
[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
[PULL 04/33] target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the recent refactoring we missed a few places which should be
2
calling finalize_memop_asimd() for ASIMD loads and stores but
3
instead are just calling finalize_memop(); fix these.
2
4
3
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
5
For the disas_ldst_single_struct() and disas_ldst_multiple_struct()
4
during arm_cpu_realizefn.
6
cases, this is not a behaviour change because there the size
7
is never MO_128 and the two finalize functions do the same thing.
5
8
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
---
11
target/arm/cpu.c | 22 +++++++++++++---------
12
target/arm/tcg/translate-a64.c | 10 ++++++----
12
1 file changed, 13 insertions(+), 9 deletions(-)
13
1 file changed, 6 insertions(+), 4 deletions(-)
13
14
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
--- a/target/arm/tcg/translate-a64.c
17
+++ b/target/arm/cpu.c
18
+++ b/target/arm/tcg/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
19
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
19
*/
20
if (!fp_access_check(s)) {
20
unset_feature(env, ARM_FEATURE_EL3);
21
return;
21
22
}
22
- /* Disable the security extension feature bits in the processor feature
23
+ memop = finalize_memop_asimd(s, size);
23
- * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
24
} else {
24
+ /*
25
if (size == 3 && opc == 2) {
25
+ * Disable the security extension feature bits in the processor
26
/* PRFM - prefetch */
26
+ * feature registers as well.
27
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
27
*/
28
is_store = (opc == 0);
28
- cpu->isar.id_pfr1 &= ~0xf0;
29
is_signed = !is_store && extract32(opc, 1, 1);
29
- cpu->isar.id_aa64pfr0 &= ~0xf000;
30
is_extended = (size < 3) && extract32(opc, 0, 1);
30
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
31
+ memop = finalize_memop(s, size + is_signed * MO_SIGN);
31
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
32
+ ID_AA64PFR0, EL3, 0);
33
}
32
}
34
33
35
if (!cpu->has_el2) {
34
if (rn == 31) {
36
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
35
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
36
37
tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
38
39
- memop = finalize_memop(s, size + is_signed * MO_SIGN);
40
clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, memop);
41
42
if (is_vector) {
43
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
44
if (!fp_access_check(s)) {
45
return;
46
}
47
+ memop = finalize_memop_asimd(s, size);
48
} else {
49
if (size == 3 && opc == 2) {
50
/* PRFM - prefetch */
51
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
52
is_store = (opc == 0);
53
is_signed = !is_store && extract32(opc, 1, 1);
54
is_extended = (size < 3) && extract32(opc, 0, 1);
55
+ memop = finalize_memop(s, size + is_signed * MO_SIGN);
37
}
56
}
38
57
39
if (!arm_feature(env, ARM_FEATURE_EL2)) {
58
if (rn == 31) {
40
- /* Disable the hypervisor feature bits in the processor feature
59
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
41
- * registers if we don't have EL2. These are id_pfr1[15:12] and
60
offset = imm12 << size;
42
- * id_aa64pfr0_el1[11:8].
61
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
43
+ /*
62
44
+ * Disable the hypervisor feature bits in the processor feature
63
- memop = finalize_memop(s, size + is_signed * MO_SIGN);
45
+ * registers if we don't have EL2.
64
clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, memop);
46
*/
65
47
- cpu->isar.id_aa64pfr0 &= ~0xf00;
66
if (is_vector) {
48
- cpu->isar.id_pfr1 &= ~0xf000;
67
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
49
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
68
* promote consecutive little-endian elements below.
50
+ ID_AA64PFR0, EL2, 0);
69
*/
51
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
70
clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31,
52
+ ID_PFR1, VIRTUALIZATION, 0);
71
- total, finalize_memop(s, size));
53
}
72
+ total, finalize_memop_asimd(s, size));
54
73
55
#ifndef CONFIG_USER_ONLY
74
/*
75
* Consecutive little-endian elements from a single register
76
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
77
total = selem << scale;
78
tcg_rn = cpu_reg_sp(s, rn);
79
80
- mop = finalize_memop(s, scale);
81
+ mop = finalize_memop_asimd(s, scale);
82
83
clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
84
total, mop);
56
--
85
--
57
2.25.1
86
2.34.1
diff view generated by jsdifflib
[PULL 17/32] target/arm: Implement ESB instruction
[PULL 05/33] target/arm: Convert hint instruction space to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the various instructions in the hint instruction space
2
to decodetree.
2
3
3
Check for and defer any pending virtual SError.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230602155223.2040685-3-peter.maydell@linaro.org
7
---
8
target/arm/tcg/a64.decode | 31 ++++
9
target/arm/tcg/translate-a64.c | 277 ++++++++++++++++++---------------
10
2 files changed, 185 insertions(+), 123 deletions(-)
4
11
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.h | 1 +
11
target/arm/a32.decode | 16 ++++++++------
12
target/arm/t32.decode | 18 ++++++++--------
13
target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-a64.c | 17 +++++++++++++++
15
target/arm/translate.c | 23 ++++++++++++++++++++
16
6 files changed, 103 insertions(+), 15 deletions(-)
17
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
14
--- a/target/arm/tcg/a64.decode
21
+++ b/target/arm/helper.h
15
+++ b/target/arm/tcg/a64.decode
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
16
@@ -XXX,XX +XXX,XX @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
23
DEF_HELPER_1(yield, void, env)
17
# the processor is in halting debug state (which we don't implement).
24
DEF_HELPER_1(pre_hvc, void, env)
18
# The pattern is listed here as documentation.
25
DEF_HELPER_2(pre_smc, void, env, i32)
19
# DRPS 1101011 0101 11111 000000 11111 00000
26
+DEF_HELPER_1(vesb, void, env)
20
+
27
21
+# Hint instruction group
28
DEF_HELPER_3(cpsr_write, void, env, i32, i32)
22
+{
29
DEF_HELPER_2(cpsr_write_eret, void, env, i32)
23
+ [
30
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
24
+ YIELD 1101 0101 0000 0011 0010 0000 001 11111
25
+ WFE 1101 0101 0000 0011 0010 0000 010 11111
26
+ WFI 1101 0101 0000 0011 0010 0000 011 11111
27
+ # We implement WFE to never block, so our SEV/SEVL are NOPs
28
+ # SEV 1101 0101 0000 0011 0010 0000 100 11111
29
+ # SEVL 1101 0101 0000 0011 0010 0000 101 11111
30
+ # Our DGL is a NOP because we don't merge memory accesses anyway.
31
+ # DGL 1101 0101 0000 0011 0010 0000 110 11111
32
+ XPACLRI 1101 0101 0000 0011 0010 0000 111 11111
33
+ PACIA1716 1101 0101 0000 0011 0010 0001 000 11111
34
+ PACIB1716 1101 0101 0000 0011 0010 0001 010 11111
35
+ AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111
36
+ AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111
37
+ ESB 1101 0101 0000 0011 0010 0010 000 11111
38
+ PACIAZ 1101 0101 0000 0011 0010 0011 000 11111
39
+ PACIASP 1101 0101 0000 0011 0010 0011 001 11111
40
+ PACIBZ 1101 0101 0000 0011 0010 0011 010 11111
41
+ PACIBSP 1101 0101 0000 0011 0010 0011 011 11111
42
+ AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111
43
+ AUTIASP 1101 0101 0000 0011 0010 0011 101 11111
44
+ AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111
45
+ AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111
46
+ ]
47
+ # The canonical NOP has CRm == op2 == 0, but all of the space
48
+ # that isn't specifically allocated to an instruction must NOP
49
+ NOP 1101 0101 0000 0011 0010 ---- --- 11111
50
+}
51
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
31
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/a32.decode
53
--- a/target/arm/tcg/translate-a64.c
33
+++ b/target/arm/a32.decode
54
+++ b/target/arm/tcg/translate-a64.c
34
@@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
55
@@ -XXX,XX +XXX,XX @@ static bool trans_ERETA(DisasContext *s, arg_reta *a)
35
36
{
37
{
38
- YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
39
- WFE ---- 0011 0010 0000 1111 ---- 0000 0010
40
- WFI ---- 0011 0010 0000 1111 ---- 0000 0011
41
+ [
42
+ YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
43
+ WFE ---- 0011 0010 0000 1111 ---- 0000 0010
44
+ WFI ---- 0011 0010 0000 1111 ---- 0000 0011
45
46
- # TODO: Implement SEV, SEVL; may help SMP performance.
47
- # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
48
- # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
49
+ # TODO: Implement SEV, SEVL; may help SMP performance.
50
+ # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
51
+ # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
52
+
53
+ ESB ---- 0011 0010 0000 1111 ---- 0001 0000
54
+ ]
55
56
# The canonical nop ends in 00000000, but the whole of the
57
# rest of the space executes as nop if otherwise unsupported.
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
63
[
64
# Hints, and CPS
65
{
66
- YIELD 1111 0011 1010 1111 1000 0000 0000 0001
67
- WFE 1111 0011 1010 1111 1000 0000 0000 0010
68
- WFI 1111 0011 1010 1111 1000 0000 0000 0011
69
+ [
70
+ YIELD 1111 0011 1010 1111 1000 0000 0000 0001
71
+ WFE 1111 0011 1010 1111 1000 0000 0000 0010
72
+ WFI 1111 0011 1010 1111 1000 0000 0000 0011
73
74
- # TODO: Implement SEV, SEVL; may help SMP performance.
75
- # SEV 1111 0011 1010 1111 1000 0000 0000 0100
76
- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
77
+ # TODO: Implement SEV, SEVL; may help SMP performance.
78
+ # SEV 1111 0011 1010 1111 1000 0000 0000 0100
79
+ # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
80
81
- # For M-profile minimal-RAS ESB can be a NOP, which is the
82
- # default behaviour since it is in the hint space.
83
- # ESB 1111 0011 1010 1111 1000 0000 0001 0000
84
+ ESB 1111 0011 1010 1111 1000 0000 0001 0000
85
+ ]
86
87
# The canonical nop ends in 0000 0000, but the whole rest
88
# of the space is "reserved hint, behaves as nop".
89
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/op_helper.c
92
+++ b/target/arm/op_helper.c
93
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
94
access_type, mmu_idx, ra);
95
}
96
}
97
+
98
+/*
99
+ * This function corresponds to AArch64.vESBOperation().
100
+ * Note that the AArch32 version is not functionally different.
101
+ */
102
+void HELPER(vesb)(CPUARMState *env)
103
+{
104
+ /*
105
+ * The EL2Enabled() check is done inside arm_hcr_el2_eff,
106
+ * and will return HCR_EL2.VSE == 0, so nothing happens.
107
+ */
108
+ uint64_t hcr = arm_hcr_el2_eff(env);
109
+ bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
110
+ bool pending = enabled && (hcr & HCR_VSE);
111
+ bool masked = (env->daif & PSTATE_A);
112
+
113
+ /* If VSE pending and masked, defer the exception. */
114
+ if (pending && masked) {
115
+ uint32_t syndrome;
116
+
117
+ if (arm_el_is_aa64(env, 1)) {
118
+ /* Copy across IDS and ISS from VSESR. */
119
+ syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
120
+ } else {
121
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
122
+
123
+ if (extended_addresses_enabled(env)) {
124
+ syndrome = arm_fi_to_lfsc(&fi);
125
+ } else {
126
+ syndrome = arm_fi_to_sfsc(&fi);
127
+ }
128
+ /* Copy across AET and ExT from VSESR. */
129
+ syndrome |= env->cp15.vsesr_el2 & 0xd000;
130
+ }
131
+
132
+ /* Set VDISR_EL2.A along with the syndrome. */
133
+ env->cp15.vdisr_el2 = syndrome | (1u << 31);
134
+
135
+ /* Clear pending virtual SError */
136
+ env->cp15.hcr_el2 &= ~HCR_VSE;
137
+ cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
138
+ }
139
+}
140
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
141
index XXXXXXX..XXXXXXX 100644
142
--- a/target/arm/translate-a64.c
143
+++ b/target/arm/translate-a64.c
144
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
145
gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
146
}
147
break;
148
+ case 0b10000: /* ESB */
149
+ /* Without RAS, we must implement this as NOP. */
150
+ if (dc_isar_feature(aa64_ras, s)) {
151
+ /*
152
+ * QEMU does not have a source of physical SErrors,
153
+ * so we are only concerned with virtual SErrors.
154
+ * The pseudocode in the ARM for this case is
155
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
156
+ * AArch64.vESBOperation();
157
+ * Most of the condition can be evaluated at translation time.
158
+ * Test for EL2 present, and defer test for SEL2 to runtime.
159
+ */
160
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
161
+ gen_helper_vesb(cpu_env);
162
+ }
163
+ }
164
+ break;
165
case 0b11000: /* PACIAZ */
166
if (s->pauth_active) {
167
gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
168
diff --git a/target/arm/translate.c b/target/arm/translate.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/arm/translate.c
171
+++ b/target/arm/translate.c
172
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
173
return true;
56
return true;
174
}
57
}
175
58
59
-/* HINT instruction group, including various allocated HINTs */
60
-static void handle_hint(DisasContext *s, uint32_t insn,
61
- unsigned int op1, unsigned int op2, unsigned int crm)
62
+static bool trans_NOP(DisasContext *s, arg_NOP *a)
63
{
64
- unsigned int selector = crm << 3 | op2;
65
+ return true;
66
+}
67
68
- if (op1 != 3) {
69
- unallocated_encoding(s);
70
- return;
71
+static bool trans_YIELD(DisasContext *s, arg_YIELD *a)
72
+{
73
+ /*
74
+ * When running in MTTCG we don't generate jumps to the yield and
75
+ * WFE helpers as it won't affect the scheduling of other vCPUs.
76
+ * If we wanted to more completely model WFE/SEV so we don't busy
77
+ * spin unnecessarily we would need to do something more involved.
78
+ */
79
+ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
80
+ s->base.is_jmp = DISAS_YIELD;
81
}
82
+ return true;
83
+}
84
85
- switch (selector) {
86
- case 0b00000: /* NOP */
87
- break;
88
- case 0b00011: /* WFI */
89
- s->base.is_jmp = DISAS_WFI;
90
- break;
91
- case 0b00001: /* YIELD */
92
- /* When running in MTTCG we don't generate jumps to the yield and
93
- * WFE helpers as it won't affect the scheduling of other vCPUs.
94
- * If we wanted to more completely model WFE/SEV so we don't busy
95
- * spin unnecessarily we would need to do something more involved.
96
+static bool trans_WFI(DisasContext *s, arg_WFI *a)
97
+{
98
+ s->base.is_jmp = DISAS_WFI;
99
+ return true;
100
+}
101
+
102
+static bool trans_WFE(DisasContext *s, arg_WFI *a)
103
+{
104
+ /*
105
+ * When running in MTTCG we don't generate jumps to the yield and
106
+ * WFE helpers as it won't affect the scheduling of other vCPUs.
107
+ * If we wanted to more completely model WFE/SEV so we don't busy
108
+ * spin unnecessarily we would need to do something more involved.
109
+ */
110
+ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
111
+ s->base.is_jmp = DISAS_WFE;
112
+ }
113
+ return true;
114
+}
115
+
116
+static bool trans_XPACLRI(DisasContext *s, arg_XPACLRI *a)
117
+{
118
+ if (s->pauth_active) {
119
+ gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]);
120
+ }
121
+ return true;
122
+}
123
+
124
+static bool trans_PACIA1716(DisasContext *s, arg_PACIA1716 *a)
125
+{
126
+ if (s->pauth_active) {
127
+ gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
128
+ }
129
+ return true;
130
+}
131
+
132
+static bool trans_PACIB1716(DisasContext *s, arg_PACIB1716 *a)
133
+{
134
+ if (s->pauth_active) {
135
+ gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
136
+ }
137
+ return true;
138
+}
139
+
140
+static bool trans_AUTIA1716(DisasContext *s, arg_AUTIA1716 *a)
141
+{
142
+ if (s->pauth_active) {
143
+ gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
144
+ }
145
+ return true;
146
+}
147
+
148
+static bool trans_AUTIB1716(DisasContext *s, arg_AUTIB1716 *a)
149
+{
150
+ if (s->pauth_active) {
151
+ gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
152
+ }
153
+ return true;
154
+}
155
+
176
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
156
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
177
+{
157
+{
178
+ /*
158
+ /* Without RAS, we must implement this as NOP. */
179
+ * For M-profile, minimal-RAS ESB can be a NOP.
159
+ if (dc_isar_feature(aa64_ras, s)) {
180
+ * Without RAS, we must implement this as NOP.
181
+ */
182
+ if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
183
+ /*
160
+ /*
184
+ * QEMU does not have a source of physical SErrors,
161
+ * QEMU does not have a source of physical SErrors,
185
+ * so we are only concerned with virtual SErrors.
162
+ * so we are only concerned with virtual SErrors.
186
+ * The pseudocode in the ARM for this case is
163
+ * The pseudocode in the ARM for this case is
187
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
164
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
188
+ * AArch32.vESBOperation();
165
+ * AArch64.vESBOperation();
189
+ * Most of the condition can be evaluated at translation time.
166
+ * Most of the condition can be evaluated at translation time.
190
+ * Test for EL2 present, and defer test for SEL2 to runtime.
167
+ * Test for EL2 present, and defer test for SEL2 to runtime.
191
+ */
168
*/
169
- if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
170
- s->base.is_jmp = DISAS_YIELD;
192
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
171
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
193
+ gen_helper_vesb(cpu_env);
172
+ gen_helper_vesb(cpu_env);
194
+ }
173
}
195
+ }
174
- break;
196
+ return true;
175
- case 0b00010: /* WFE */
197
+}
176
- if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
198
+
177
- s->base.is_jmp = DISAS_WFE;
199
static bool trans_NOP(DisasContext *s, arg_NOP *a)
178
- }
200
{
179
- break;
201
return true;
180
- case 0b00100: /* SEV */
181
- case 0b00101: /* SEVL */
182
- case 0b00110: /* DGH */
183
- /* we treat all as NOP at least for now */
184
- break;
185
- case 0b00111: /* XPACLRI */
186
- if (s->pauth_active) {
187
- gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]);
188
- }
189
- break;
190
- case 0b01000: /* PACIA1716 */
191
- if (s->pauth_active) {
192
- gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
193
- }
194
- break;
195
- case 0b01010: /* PACIB1716 */
196
- if (s->pauth_active) {
197
- gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
198
- }
199
- break;
200
- case 0b01100: /* AUTIA1716 */
201
- if (s->pauth_active) {
202
- gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
203
- }
204
- break;
205
- case 0b01110: /* AUTIB1716 */
206
- if (s->pauth_active) {
207
- gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
208
- }
209
- break;
210
- case 0b10000: /* ESB */
211
- /* Without RAS, we must implement this as NOP. */
212
- if (dc_isar_feature(aa64_ras, s)) {
213
- /*
214
- * QEMU does not have a source of physical SErrors,
215
- * so we are only concerned with virtual SErrors.
216
- * The pseudocode in the ARM for this case is
217
- * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
218
- * AArch64.vESBOperation();
219
- * Most of the condition can be evaluated at translation time.
220
- * Test for EL2 present, and defer test for SEL2 to runtime.
221
- */
222
- if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
223
- gen_helper_vesb(cpu_env);
224
- }
225
- }
226
- break;
227
- case 0b11000: /* PACIAZ */
228
- if (s->pauth_active) {
229
- gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
230
- tcg_constant_i64(0));
231
- }
232
- break;
233
- case 0b11001: /* PACIASP */
234
- if (s->pauth_active) {
235
- gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
236
- }
237
- break;
238
- case 0b11010: /* PACIBZ */
239
- if (s->pauth_active) {
240
- gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30],
241
- tcg_constant_i64(0));
242
- }
243
- break;
244
- case 0b11011: /* PACIBSP */
245
- if (s->pauth_active) {
246
- gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
247
- }
248
- break;
249
- case 0b11100: /* AUTIAZ */
250
- if (s->pauth_active) {
251
- gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30],
252
- tcg_constant_i64(0));
253
- }
254
- break;
255
- case 0b11101: /* AUTIASP */
256
- if (s->pauth_active) {
257
- gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
258
- }
259
- break;
260
- case 0b11110: /* AUTIBZ */
261
- if (s->pauth_active) {
262
- gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30],
263
- tcg_constant_i64(0));
264
- }
265
- break;
266
- case 0b11111: /* AUTIBSP */
267
- if (s->pauth_active) {
268
- gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
269
- }
270
- break;
271
- default:
272
- /* default specified as NOP equivalent */
273
- break;
274
}
275
+ return true;
276
+}
277
+
278
+static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ *a)
279
+{
280
+ if (s->pauth_active) {
281
+ gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0));
282
+ }
283
+ return true;
284
+}
285
+
286
+static bool trans_PACIASP(DisasContext *s, arg_PACIASP *a)
287
+{
288
+ if (s->pauth_active) {
289
+ gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
290
+ }
291
+ return true;
292
+}
293
+
294
+static bool trans_PACIBZ(DisasContext *s, arg_PACIBZ *a)
295
+{
296
+ if (s->pauth_active) {
297
+ gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0));
298
+ }
299
+ return true;
300
+}
301
+
302
+static bool trans_PACIBSP(DisasContext *s, arg_PACIBSP *a)
303
+{
304
+ if (s->pauth_active) {
305
+ gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
306
+ }
307
+ return true;
308
+}
309
+
310
+static bool trans_AUTIAZ(DisasContext *s, arg_AUTIAZ *a)
311
+{
312
+ if (s->pauth_active) {
313
+ gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0));
314
+ }
315
+ return true;
316
+}
317
+
318
+static bool trans_AUTIASP(DisasContext *s, arg_AUTIASP *a)
319
+{
320
+ if (s->pauth_active) {
321
+ gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
322
+ }
323
+ return true;
324
+}
325
+
326
+static bool trans_AUTIBZ(DisasContext *s, arg_AUTIBZ *a)
327
+{
328
+ if (s->pauth_active) {
329
+ gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0));
330
+ }
331
+ return true;
332
+}
333
+
334
+static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a)
335
+{
336
+ if (s->pauth_active) {
337
+ gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
338
+ }
339
+ return true;
340
}
341
342
static void gen_clrex(DisasContext *s, uint32_t insn)
343
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
344
return;
345
}
346
switch (crn) {
347
- case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
348
- handle_hint(s, insn, op1, op2, crm);
349
- break;
350
case 3: /* CLREX, DSB, DMB, ISB */
351
handle_sync(s, insn, op1, op2, crm);
352
break;
202
--
353
--
203
2.25.1
354
2.34.1
diff view generated by jsdifflib
[PULL 27/32] qapi/machine.json: Add cluster-id
[PULL 06/33] target/arm: Convert barrier insns to decodetree
1
From: Gavin Shan <gshan@redhat.com>
1
Convert the insns in the "Barriers" instruction class to
2
decodetree: CLREX, DSB, DMB, ISB and SB.
2
3
3
This adds cluster-id in CPU instance properties, which will be used
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
by arm/virt machine. Besides, the cluster-id is also verified or
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
dumped in various spots:
6
Message-id: 20230602155223.2040685-4-peter.maydell@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
---
9
target/arm/tcg/a64.decode | 7 +++
10
target/arm/tcg/translate-a64.c | 92 ++++++++++++++--------------------
11
2 files changed, 46 insertions(+), 53 deletions(-)
6
12
7
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
13
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
8
CPU with its NUMA node.
9
10
* hw/core/machine.c::machine_numa_finish_cpu_init() to record
11
CPU slots with no NUMA mapping set.
12
13
* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
14
cluster-id.
15
16
Signed-off-by: Gavin Shan <gshan@redhat.com>
17
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
18
Acked-by: Igor Mammedov <imammedo@redhat.com>
19
Message-id: 20220503140304.855514-2-gshan@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
qapi/machine.json | 6 ++++--
23
hw/core/machine-hmp-cmds.c | 4 ++++
24
hw/core/machine.c | 16 ++++++++++++++++
25
3 files changed, 24 insertions(+), 2 deletions(-)
26
27
diff --git a/qapi/machine.json b/qapi/machine.json
28
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
29
--- a/qapi/machine.json
15
--- a/target/arm/tcg/a64.decode
30
+++ b/qapi/machine.json
16
+++ b/target/arm/tcg/a64.decode
31
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
32
# @node-id: NUMA node ID the CPU belongs to
18
# that isn't specifically allocated to an instruction must NOP
33
# @socket-id: socket number within node/board the CPU belongs to
19
NOP 1101 0101 0000 0011 0010 ---- --- 11111
34
# @die-id: die number within socket the CPU belongs to (since 4.1)
20
}
35
-# @core-id: core number within die the CPU belongs to
21
+
36
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
22
+# Barriers
37
+# @core-id: core number within cluster the CPU belongs to
23
+
38
# @thread-id: thread number within core the CPU belongs to
24
+CLREX 1101 0101 0000 0011 0011 ---- 010 11111
39
#
25
+DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
40
-# Note: currently there are 5 properties that could be present
26
+ISB 1101 0101 0000 0011 0011 ---- 110 11111
41
+# Note: currently there are 6 properties that could be present
27
+SB 1101 0101 0000 0011 0011 0000 111 11111
42
# but management should be prepared to pass through other
28
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
43
# properties with device_add command to allow for future
44
# interface extension. This also requires the filed names to be kept in
45
@@ -XXX,XX +XXX,XX @@
46
'data': { '*node-id': 'int',
47
'*socket-id': 'int',
48
'*die-id': 'int',
49
+ '*cluster-id': 'int',
50
'*core-id': 'int',
51
'*thread-id': 'int'
52
}
53
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
54
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/core/machine-hmp-cmds.c
30
--- a/target/arm/tcg/translate-a64.c
56
+++ b/hw/core/machine-hmp-cmds.c
31
+++ b/target/arm/tcg/translate-a64.c
57
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
32
@@ -XXX,XX +XXX,XX @@ static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a)
58
if (c->has_die_id) {
33
return true;
59
monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
34
}
60
}
35
61
+ if (c->has_cluster_id) {
36
-static void gen_clrex(DisasContext *s, uint32_t insn)
62
+ monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n",
37
+static bool trans_CLREX(DisasContext *s, arg_CLREX *a)
63
+ c->cluster_id);
38
{
64
+ }
39
tcg_gen_movi_i64(cpu_exclusive_addr, -1);
65
if (c->has_core_id) {
40
+ return true;
66
monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
41
}
67
}
42
68
diff --git a/hw/core/machine.c b/hw/core/machine.c
43
-/* CLREX, DSB, DMB, ISB */
69
index XXXXXXX..XXXXXXX 100644
44
-static void handle_sync(DisasContext *s, uint32_t insn,
70
--- a/hw/core/machine.c
45
- unsigned int op1, unsigned int op2, unsigned int crm)
71
+++ b/hw/core/machine.c
46
+static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a)
72
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
47
{
48
+ /* We handle DSB and DMB the same way */
49
TCGBar bar;
50
51
- if (op1 != 3) {
52
- unallocated_encoding(s);
53
- return;
54
+ switch (a->types) {
55
+ case 1: /* MBReqTypes_Reads */
56
+ bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST;
57
+ break;
58
+ case 2: /* MBReqTypes_Writes */
59
+ bar = TCG_BAR_SC | TCG_MO_ST_ST;
60
+ break;
61
+ default: /* MBReqTypes_All */
62
+ bar = TCG_BAR_SC | TCG_MO_ALL;
63
+ break;
64
}
65
+ tcg_gen_mb(bar);
66
+ return true;
67
+}
68
69
- switch (op2) {
70
- case 2: /* CLREX */
71
- gen_clrex(s, insn);
72
- return;
73
- case 4: /* DSB */
74
- case 5: /* DMB */
75
- switch (crm & 3) {
76
- case 1: /* MBReqTypes_Reads */
77
- bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST;
78
- break;
79
- case 2: /* MBReqTypes_Writes */
80
- bar = TCG_BAR_SC | TCG_MO_ST_ST;
81
- break;
82
- default: /* MBReqTypes_All */
83
- bar = TCG_BAR_SC | TCG_MO_ALL;
84
- break;
85
- }
86
- tcg_gen_mb(bar);
87
- return;
88
- case 6: /* ISB */
89
- /* We need to break the TB after this insn to execute
90
- * a self-modified code correctly and also to take
91
- * any pending interrupts immediately.
92
- */
93
- reset_btype(s);
94
- gen_goto_tb(s, 0, 4);
95
- return;
96
+static bool trans_ISB(DisasContext *s, arg_ISB *a)
97
+{
98
+ /*
99
+ * We need to break the TB after this insn to execute
100
+ * self-modifying code correctly and also to take
101
+ * any pending interrupts immediately.
102
+ */
103
+ reset_btype(s);
104
+ gen_goto_tb(s, 0, 4);
105
+ return true;
106
+}
107
108
- case 7: /* SB */
109
- if (crm != 0 || !dc_isar_feature(aa64_sb, s)) {
110
- goto do_unallocated;
111
- }
112
- /*
113
- * TODO: There is no speculation barrier opcode for TCG;
114
- * MB and end the TB instead.
115
- */
116
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
117
- gen_goto_tb(s, 0, 4);
118
- return;
119
-
120
- default:
121
- do_unallocated:
122
- unallocated_encoding(s);
123
- return;
124
+static bool trans_SB(DisasContext *s, arg_SB *a)
125
+{
126
+ if (!dc_isar_feature(aa64_sb, s)) {
127
+ return false;
128
}
129
+ /*
130
+ * TODO: There is no speculation barrier opcode for TCG;
131
+ * MB and end the TB instead.
132
+ */
133
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
134
+ gen_goto_tb(s, 0, 4);
135
+ return true;
136
}
137
138
static void gen_xaflag(void)
139
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
73
return;
140
return;
74
}
141
}
75
142
switch (crn) {
76
+ if (props->has_cluster_id && !slot->props.has_cluster_id) {
143
- case 3: /* CLREX, DSB, DMB, ISB */
77
+ error_setg(errp, "cluster-id is not supported");
144
- handle_sync(s, insn, op1, op2, crm);
78
+ return;
145
- break;
79
+ }
146
case 4: /* MSR (immediate) */
80
+
147
handle_msr_i(s, insn, op1, op2, crm);
81
if (props->has_socket_id && !slot->props.has_socket_id) {
148
break;
82
error_setg(errp, "socket-id is not supported");
83
return;
84
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
85
continue;
86
}
87
88
+ if (props->has_cluster_id &&
89
+ props->cluster_id != slot->props.cluster_id) {
90
+ continue;
91
+ }
92
+
93
if (props->has_die_id && props->die_id != slot->props.die_id) {
94
continue;
95
}
96
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
97
}
98
g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
99
}
100
+ if (cpu->props.has_cluster_id) {
101
+ if (s->len) {
102
+ g_string_append_printf(s, ", ");
103
+ }
104
+ g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
105
+ }
106
if (cpu->props.has_core_id) {
107
if (s->len) {
108
g_string_append_printf(s, ", ");
109
--
149
--
110
2.25.1
150
2.34.1
151
152
diff view generated by jsdifflib
[PULL 16/32] target/arm: Implement virtual SError exceptions
[PULL 07/33] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the CFINV, XAFLAG and AXFLAG insns to decodetree.
2
The old decoder handles these in handle_msr_i(), but
3
the architecture defines them as separate instructions
4
from MSR (immediate).
2
5
3
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
and are routed to EL1 just like other virtual exceptions.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230602155223.2040685-5-peter.maydell@linaro.org
9
---
10
target/arm/tcg/a64.decode | 6 ++++
11
target/arm/tcg/translate-a64.c | 53 +++++++++++++++++-----------------
12
2 files changed, 32 insertions(+), 27 deletions(-)
5
13
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 2 ++
12
target/arm/internals.h | 8 ++++++++
13
target/arm/syndrome.h | 5 +++++
14
target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++-
15
target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++-
16
5 files changed, 91 insertions(+), 2 deletions(-)
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
16
--- a/target/arm/tcg/a64.decode
21
+++ b/target/arm/cpu.h
17
+++ b/target/arm/tcg/a64.decode
22
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ CLREX 1101 0101 0000 0011 0011 ---- 010 11111
23
#define EXCP_LSERR 21 /* v8M LSERR SecureFault */
19
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
24
#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
20
ISB 1101 0101 0000 0011 0011 ---- 110 11111
25
#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
21
SB 1101 0101 0000 0011 0011 0000 111 11111
26
+#define EXCP_VSERR 24
22
+
27
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
23
+# PSTATE
28
24
+
29
#define ARMV7M_EXCP_RESET 1
25
+CFINV 1101 0101 0000 0 000 0100 0000 000 11111
30
@@ -XXX,XX +XXX,XX @@ enum {
26
+XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111
31
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
27
+AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111
32
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
28
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
33
#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
34
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
35
36
/* The usual mapping for an AArch64 system register to its AArch32
37
* counterpart is for the 32 bit world to have access to the lower
38
diff --git a/target/arm/internals.h b/target/arm/internals.h
39
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/internals.h
30
--- a/target/arm/tcg/translate-a64.c
41
+++ b/target/arm/internals.h
31
+++ b/target/arm/tcg/translate-a64.c
42
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
32
@@ -XXX,XX +XXX,XX @@ static bool trans_SB(DisasContext *s, arg_SB *a)
43
*/
33
return true;
44
void arm_cpu_update_vfiq(ARMCPU *cpu);
45
46
+/**
47
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
48
+ *
49
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
50
+ * following a change to the HCR_EL2.VSE bit.
51
+ */
52
+void arm_cpu_update_vserr(ARMCPU *cpu);
53
+
54
/**
55
* arm_mmu_idx_el:
56
* @env: The cpu environment
57
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/syndrome.h
60
+++ b/target/arm/syndrome.h
61
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
62
return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
63
}
34
}
64
35
65
+static inline uint32_t syn_serror(uint32_t extra)
36
-static void gen_xaflag(void)
66
+{
37
+static bool trans_CFINV(DisasContext *s, arg_CFINV *a)
67
+ return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
38
{
39
- TCGv_i32 z = tcg_temp_new_i32();
40
+ if (!dc_isar_feature(aa64_condm_4, s)) {
41
+ return false;
42
+ }
43
+ tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
44
+ return true;
68
+}
45
+}
69
+
46
+
70
#endif /* TARGET_ARM_SYNDROME_H */
47
+static bool trans_XAFLAG(DisasContext *s, arg_XAFLAG *a)
71
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/cpu.c
74
+++ b/target/arm/cpu.c
75
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
76
return (cpu->power_state != PSCI_OFF)
77
&& cs->interrupt_request &
78
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
79
- | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
80
+ | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
81
| CPU_INTERRUPT_EXITTB);
82
}
83
84
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
85
return false;
86
}
87
return !(env->daif & PSTATE_I);
88
+ case EXCP_VSERR:
89
+ if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
90
+ /* VIRQs are only taken when hypervized. */
91
+ return false;
92
+ }
93
+ return !(env->daif & PSTATE_A);
94
default:
95
g_assert_not_reached();
96
}
97
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
98
goto found;
99
}
100
}
101
+ if (interrupt_request & CPU_INTERRUPT_VSERR) {
102
+ excp_idx = EXCP_VSERR;
103
+ target_el = 1;
104
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
105
+ cur_el, secure, hcr_el2)) {
106
+ /* Taking a virtual abort clears HCR_EL2.VSE */
107
+ env->cp15.hcr_el2 &= ~HCR_VSE;
108
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
109
+ goto found;
110
+ }
111
+ }
112
return false;
113
114
found:
115
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
116
}
117
}
118
119
+void arm_cpu_update_vserr(ARMCPU *cpu)
120
+{
48
+{
121
+ /*
49
+ TCGv_i32 z;
122
+ * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
123
+ */
124
+ CPUARMState *env = &cpu->env;
125
+ CPUState *cs = CPU(cpu);
126
+
50
+
127
+ bool new_state = env->cp15.hcr_el2 & HCR_VSE;
51
+ if (!dc_isar_feature(aa64_condm_5, s)) {
128
+
52
+ return false;
129
+ if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
130
+ if (new_state) {
131
+ cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
132
+ } else {
133
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
134
+ }
135
+ }
136
+}
137
+
138
#ifndef CONFIG_USER_ONLY
139
static void arm_cpu_set_irq(void *opaque, int irq, int level)
140
{
141
diff --git a/target/arm/helper.c b/target/arm/helper.c
142
index XXXXXXX..XXXXXXX 100644
143
--- a/target/arm/helper.c
144
+++ b/target/arm/helper.c
145
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
146
}
147
}
148
149
- /* External aborts are not possible in QEMU so A bit is always clear */
150
+ if (hcr_el2 & HCR_AMO) {
151
+ if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
152
+ ret |= CPSR_A;
153
+ }
154
+ }
53
+ }
155
+
54
+
156
return ret;
55
+ z = tcg_temp_new_i32();
56
57
tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0);
58
59
@@ -XXX,XX +XXX,XX @@ static void gen_xaflag(void)
60
61
/* C | Z */
62
tcg_gen_or_i32(cpu_CF, cpu_CF, z);
63
+
64
+ return true;
157
}
65
}
158
66
159
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
67
-static void gen_axflag(void)
160
g_assert(qemu_mutex_iothread_locked());
68
+static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a)
161
arm_cpu_update_virq(cpu);
69
{
162
arm_cpu_update_vfiq(cpu);
70
+ if (!dc_isar_feature(aa64_condm_5, s)) {
163
+ arm_cpu_update_vserr(cpu);
71
+ return false;
72
+ }
73
+
74
tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */
75
tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */
76
77
@@ -XXX,XX +XXX,XX @@ static void gen_axflag(void)
78
79
tcg_gen_movi_i32(cpu_NF, 0);
80
tcg_gen_movi_i32(cpu_VF, 0);
81
+
82
+ return true;
164
}
83
}
165
84
166
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
85
/* MSR (immediate) - move immediate to processor state field */
167
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
86
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
168
[EXCP_LSERR] = "v8M LSERR UsageFault",
87
s->base.is_jmp = DISAS_TOO_MANY;
169
[EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
88
170
[EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
89
switch (op) {
171
+ [EXCP_VSERR] = "Virtual SERR",
90
- case 0x00: /* CFINV */
172
};
91
- if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) {
173
92
- goto do_unallocated;
174
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
93
- }
175
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
94
- tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
176
mask = CPSR_A | CPSR_I | CPSR_F;
95
- s->base.is_jmp = DISAS_NEXT;
177
offset = 4;
96
- break;
178
break;
97
-
179
+ case EXCP_VSERR:
98
- case 0x01: /* XAFlag */
180
+ {
99
- if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
181
+ /*
100
- goto do_unallocated;
182
+ * Note that this is reported as a data abort, but the DFAR
101
- }
183
+ * has an UNKNOWN value. Construct the SError syndrome from
102
- gen_xaflag();
184
+ * AET and ExT fields.
103
- s->base.is_jmp = DISAS_NEXT;
185
+ */
104
- break;
186
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
105
-
187
+
106
- case 0x02: /* AXFlag */
188
+ if (extended_addresses_enabled(env)) {
107
- if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
189
+ env->exception.fsr = arm_fi_to_lfsc(&fi);
108
- goto do_unallocated;
190
+ } else {
109
- }
191
+ env->exception.fsr = arm_fi_to_sfsc(&fi);
110
- gen_axflag();
192
+ }
111
- s->base.is_jmp = DISAS_NEXT;
193
+ env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
112
- break;
194
+ A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
113
-
195
+ qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
114
case 0x03: /* UAO */
196
+ env->exception.fsr);
115
if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) {
197
+
116
goto do_unallocated;
198
+ new_mode = ARM_CPU_MODE_ABT;
199
+ addr = 0x10;
200
+ mask = CPSR_A | CPSR_I;
201
+ offset = 8;
202
+ }
203
+ break;
204
case EXCP_SMC:
205
new_mode = ARM_CPU_MODE_MON;
206
addr = 0x08;
207
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
208
case EXCP_VFIQ:
209
addr += 0x100;
210
break;
211
+ case EXCP_VSERR:
212
+ addr += 0x180;
213
+ /* Construct the SError syndrome from IDS and ISS fields. */
214
+ env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
215
+ env->cp15.esr_el[new_el] = env->exception.syndrome;
216
+ break;
217
default:
218
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
219
}
220
--
117
--
221
2.25.1
118
2.34.1
diff view generated by jsdifflib
[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
[PULL 08/33] target/arm: Convert MSR (immediate) to decodetree
1
From: Gavin Shan <gshan@redhat.com>
1
Convert the MSR (immediate) insn to decodetree. Our implementation
2
has basically no commonality between the different destinations,
3
so we decode the destination register in a64.decode.
2
4
3
When CPU-to-NUMA association isn't explicitly provided by users,
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
the default one is given by mc->get_default_cpu_node_id(). However,
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
the CPU topology isn't fully considered in the default association
7
Message-id: 20230602155223.2040685-6-peter.maydell@linaro.org
6
and this causes CPU topology broken warnings on booting Linux guest.
8
---
9
target/arm/tcg/a64.decode | 13 ++
10
target/arm/tcg/translate-a64.c | 251 ++++++++++++++++-----------------
11
2 files changed, 136 insertions(+), 128 deletions(-)
7
12
8
For example, the following warning messages are observed when the
13
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
9
Linux guest is booted with the following command lines.
10
11
/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
12
-accel kvm -machine virt,gic-version=host \
13
-cpu host \
14
-smp 6,sockets=2,cores=3,threads=1 \
15
-m 1024M,slots=16,maxmem=64G \
16
-object memory-backend-ram,id=mem0,size=128M \
17
-object memory-backend-ram,id=mem1,size=128M \
18
-object memory-backend-ram,id=mem2,size=128M \
19
-object memory-backend-ram,id=mem3,size=128M \
20
-object memory-backend-ram,id=mem4,size=128M \
21
-object memory-backend-ram,id=mem4,size=384M \
22
-numa node,nodeid=0,memdev=mem0 \
23
-numa node,nodeid=1,memdev=mem1 \
24
-numa node,nodeid=2,memdev=mem2 \
25
-numa node,nodeid=3,memdev=mem3 \
26
-numa node,nodeid=4,memdev=mem4 \
27
-numa node,nodeid=5,memdev=mem5
28
:
29
alternatives: patching kernel code
30
BUG: arch topology borken
31
the CLS domain not a subset of the MC domain
32
<the above error log repeats>
33
BUG: arch topology borken
34
the DIE domain not a subset of the NODE domain
35
36
With current implementation of mc->get_default_cpu_node_id(),
37
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
38
That's incorrect because CPU#0/1/2 should be associated with same
39
NUMA node because they're seated in same socket.
40
41
This fixes the issue by considering the socket ID when the default
42
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
43
With this applied, no more CPU topology broken warnings are seen
44
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
45
there are no CPUs associated with NODE#2/3/4/5.
46
47
Signed-off-by: Gavin Shan <gshan@redhat.com>
48
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
49
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
50
Message-id: 20220503140304.855514-6-gshan@redhat.com
51
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
52
---
53
hw/arm/virt.c | 4 +++-
54
1 file changed, 3 insertions(+), 1 deletion(-)
55
56
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
57
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/arm/virt.c
15
--- a/target/arm/tcg/a64.decode
59
+++ b/hw/arm/virt.c
16
+++ b/target/arm/tcg/a64.decode
60
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
17
@@ -XXX,XX +XXX,XX @@ SB 1101 0101 0000 0011 0011 0000 111 11111
61
18
CFINV 1101 0101 0000 0 000 0100 0000 000 11111
62
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
19
XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111
20
AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111
21
+
22
+# These are architecturally all "MSR (immediate)"; we decode the destination
23
+# register too because there is no commonality in our implementation.
24
+@msr_i .... .... .... . ... .... imm:4 ... .....
25
+MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i
26
+MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i
27
+MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i
28
+MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i
29
+MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i
30
+MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
31
+MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
32
+MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
33
+MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
34
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/tcg/translate-a64.c
37
+++ b/target/arm/tcg/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@ static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a)
39
return true;
40
}
41
42
-/* MSR (immediate) - move immediate to processor state field */
43
-static void handle_msr_i(DisasContext *s, uint32_t insn,
44
- unsigned int op1, unsigned int op2, unsigned int crm)
45
+static bool trans_MSR_i_UAO(DisasContext *s, arg_i *a)
63
{
46
{
64
- return idx % ms->numa_state->num_nodes;
47
- int op = op1 << 3 | op2;
65
+ int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
48
-
66
+
49
- /* End the TB by default, chaining is ok. */
67
+ return socket_id % ms->numa_state->num_nodes;
50
- s->base.is_jmp = DISAS_TOO_MANY;
51
-
52
- switch (op) {
53
- case 0x03: /* UAO */
54
- if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) {
55
- goto do_unallocated;
56
- }
57
- if (crm & 1) {
58
- set_pstate_bits(PSTATE_UAO);
59
- } else {
60
- clear_pstate_bits(PSTATE_UAO);
61
- }
62
- gen_rebuild_hflags(s);
63
- break;
64
-
65
- case 0x04: /* PAN */
66
- if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) {
67
- goto do_unallocated;
68
- }
69
- if (crm & 1) {
70
- set_pstate_bits(PSTATE_PAN);
71
- } else {
72
- clear_pstate_bits(PSTATE_PAN);
73
- }
74
- gen_rebuild_hflags(s);
75
- break;
76
-
77
- case 0x05: /* SPSel */
78
- if (s->current_el == 0) {
79
- goto do_unallocated;
80
- }
81
- gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP));
82
- break;
83
-
84
- case 0x19: /* SSBS */
85
- if (!dc_isar_feature(aa64_ssbs, s)) {
86
- goto do_unallocated;
87
- }
88
- if (crm & 1) {
89
- set_pstate_bits(PSTATE_SSBS);
90
- } else {
91
- clear_pstate_bits(PSTATE_SSBS);
92
- }
93
- /* Don't need to rebuild hflags since SSBS is a nop */
94
- break;
95
-
96
- case 0x1a: /* DIT */
97
- if (!dc_isar_feature(aa64_dit, s)) {
98
- goto do_unallocated;
99
- }
100
- if (crm & 1) {
101
- set_pstate_bits(PSTATE_DIT);
102
- } else {
103
- clear_pstate_bits(PSTATE_DIT);
104
- }
105
- /* There's no need to rebuild hflags because DIT is a nop */
106
- break;
107
-
108
- case 0x1e: /* DAIFSet */
109
- gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm));
110
- break;
111
-
112
- case 0x1f: /* DAIFClear */
113
- gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm));
114
- /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
115
- s->base.is_jmp = DISAS_UPDATE_EXIT;
116
- break;
117
-
118
- case 0x1c: /* TCO */
119
- if (dc_isar_feature(aa64_mte, s)) {
120
- /* Full MTE is enabled -- set the TCO bit as directed. */
121
- if (crm & 1) {
122
- set_pstate_bits(PSTATE_TCO);
123
- } else {
124
- clear_pstate_bits(PSTATE_TCO);
125
- }
126
- gen_rebuild_hflags(s);
127
- /* Many factors, including TCO, go into MTE_ACTIVE. */
128
- s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
129
- } else if (dc_isar_feature(aa64_mte_insn_reg, s)) {
130
- /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
131
- s->base.is_jmp = DISAS_NEXT;
132
- } else {
133
- goto do_unallocated;
134
- }
135
- break;
136
-
137
- case 0x1b: /* SVCR* */
138
- if (!dc_isar_feature(aa64_sme, s) || crm < 2 || crm > 7) {
139
- goto do_unallocated;
140
- }
141
- if (sme_access_check(s)) {
142
- int old = s->pstate_sm | (s->pstate_za << 1);
143
- int new = (crm & 1) * 3;
144
- int msk = (crm >> 1) & 3;
145
-
146
- if ((old ^ new) & msk) {
147
- /* At least one bit changes. */
148
- gen_helper_set_svcr(cpu_env, tcg_constant_i32(new),
149
- tcg_constant_i32(msk));
150
- } else {
151
- s->base.is_jmp = DISAS_NEXT;
152
- }
153
- }
154
- break;
155
-
156
- default:
157
- do_unallocated:
158
- unallocated_encoding(s);
159
- return;
160
+ if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) {
161
+ return false;
162
}
163
+ if (a->imm & 1) {
164
+ set_pstate_bits(PSTATE_UAO);
165
+ } else {
166
+ clear_pstate_bits(PSTATE_UAO);
167
+ }
168
+ gen_rebuild_hflags(s);
169
+ s->base.is_jmp = DISAS_TOO_MANY;
170
+ return true;
171
+}
172
+
173
+static bool trans_MSR_i_PAN(DisasContext *s, arg_i *a)
174
+{
175
+ if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) {
176
+ return false;
177
+ }
178
+ if (a->imm & 1) {
179
+ set_pstate_bits(PSTATE_PAN);
180
+ } else {
181
+ clear_pstate_bits(PSTATE_PAN);
182
+ }
183
+ gen_rebuild_hflags(s);
184
+ s->base.is_jmp = DISAS_TOO_MANY;
185
+ return true;
186
+}
187
+
188
+static bool trans_MSR_i_SPSEL(DisasContext *s, arg_i *a)
189
+{
190
+ if (s->current_el == 0) {
191
+ return false;
192
+ }
193
+ gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(a->imm & PSTATE_SP));
194
+ s->base.is_jmp = DISAS_TOO_MANY;
195
+ return true;
196
+}
197
+
198
+static bool trans_MSR_i_SBSS(DisasContext *s, arg_i *a)
199
+{
200
+ if (!dc_isar_feature(aa64_ssbs, s)) {
201
+ return false;
202
+ }
203
+ if (a->imm & 1) {
204
+ set_pstate_bits(PSTATE_SSBS);
205
+ } else {
206
+ clear_pstate_bits(PSTATE_SSBS);
207
+ }
208
+ /* Don't need to rebuild hflags since SSBS is a nop */
209
+ s->base.is_jmp = DISAS_TOO_MANY;
210
+ return true;
211
+}
212
+
213
+static bool trans_MSR_i_DIT(DisasContext *s, arg_i *a)
214
+{
215
+ if (!dc_isar_feature(aa64_dit, s)) {
216
+ return false;
217
+ }
218
+ if (a->imm & 1) {
219
+ set_pstate_bits(PSTATE_DIT);
220
+ } else {
221
+ clear_pstate_bits(PSTATE_DIT);
222
+ }
223
+ /* There's no need to rebuild hflags because DIT is a nop */
224
+ s->base.is_jmp = DISAS_TOO_MANY;
225
+ return true;
226
+}
227
+
228
+static bool trans_MSR_i_TCO(DisasContext *s, arg_i *a)
229
+{
230
+ if (dc_isar_feature(aa64_mte, s)) {
231
+ /* Full MTE is enabled -- set the TCO bit as directed. */
232
+ if (a->imm & 1) {
233
+ set_pstate_bits(PSTATE_TCO);
234
+ } else {
235
+ clear_pstate_bits(PSTATE_TCO);
236
+ }
237
+ gen_rebuild_hflags(s);
238
+ /* Many factors, including TCO, go into MTE_ACTIVE. */
239
+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
240
+ return true;
241
+ } else if (dc_isar_feature(aa64_mte_insn_reg, s)) {
242
+ /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
243
+ return true;
244
+ } else {
245
+ /* Insn not present */
246
+ return false;
247
+ }
248
+}
249
+
250
+static bool trans_MSR_i_DAIFSET(DisasContext *s, arg_i *a)
251
+{
252
+ gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(a->imm));
253
+ s->base.is_jmp = DISAS_TOO_MANY;
254
+ return true;
255
+}
256
+
257
+static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a)
258
+{
259
+ gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(a->imm));
260
+ /* Exit the cpu loop to re-evaluate pending IRQs. */
261
+ s->base.is_jmp = DISAS_UPDATE_EXIT;
262
+ return true;
263
+}
264
+
265
+static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a)
266
+{
267
+ if (!dc_isar_feature(aa64_sme, s) || a->mask == 0) {
268
+ return false;
269
+ }
270
+ if (sme_access_check(s)) {
271
+ int old = s->pstate_sm | (s->pstate_za << 1);
272
+ int new = a->imm * 3;
273
+
274
+ if ((old ^ new) & a->mask) {
275
+ /* At least one bit changes. */
276
+ gen_helper_set_svcr(cpu_env, tcg_constant_i32(new),
277
+ tcg_constant_i32(a->mask));
278
+ s->base.is_jmp = DISAS_TOO_MANY;
279
+ }
280
+ }
281
+ return true;
68
}
282
}
69
283
70
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
284
static void gen_get_nzcv(TCGv_i64 tcg_rt)
285
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
286
rt = extract32(insn, 0, 5);
287
288
if (op0 == 0) {
289
- if (l || rt != 31) {
290
- unallocated_encoding(s);
291
- return;
292
- }
293
- switch (crn) {
294
- case 4: /* MSR (immediate) */
295
- handle_msr_i(s, insn, op1, op2, crm);
296
- break;
297
- default:
298
- unallocated_encoding(s);
299
- break;
300
- }
301
+ unallocated_encoding(s);
302
return;
303
}
304
handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
71
--
305
--
72
2.25.1
306
2.34.1
diff view generated by jsdifflib
[PULL 04/32] target/arm: Merge zcr reginfo
[PULL 09/33] target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are
2
all essentially the same instruction (system register access).
2
3
3
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
while registering.
6
Message-id: 20230602155223.2040685-7-peter.maydell@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
---
9
target/arm/tcg/a64.decode | 8 ++++++++
10
target/arm/tcg/translate-a64.c | 32 +++++---------------------------
11
2 files changed, 13 insertions(+), 27 deletions(-)
6
12
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.c | 55 ++++++++++++++-------------------------------
13
1 file changed, 17 insertions(+), 38 deletions(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
15
--- a/target/arm/tcg/a64.decode
18
+++ b/target/arm/helper.c
16
+++ b/target/arm/tcg/a64.decode
19
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
17
@@ -XXX,XX +XXX,XX @@ MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
18
MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
19
MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
20
MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
21
+
22
+# MRS, MSR (register), SYS, SYSL. These are all essentially the
23
+# same instruction as far as QEMU is concerned.
24
+# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have
25
+# to hand-decode it.
26
+SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
27
+SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
28
+SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3
29
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/tcg/translate-a64.c
32
+++ b/target/arm/tcg/translate-a64.c
33
@@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
34
* These are all essentially the same insn in 'read' and 'write'
35
* versions, with varying op0 fields.
36
*/
37
-static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
38
+static void handle_sys(DisasContext *s, bool isread,
39
unsigned int op0, unsigned int op1, unsigned int op2,
40
unsigned int crn, unsigned int crm, unsigned int rt)
41
{
42
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
20
}
43
}
21
}
44
}
22
45
23
-static const ARMCPRegInfo zcr_el1_reginfo = {
46
-/* System
24
- .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
47
- * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
25
- .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
48
- * +---------------------+---+-----+-----+-------+-------+-----+------+
26
- .access = PL1_RW, .type = ARM_CP_SVE,
49
- * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
27
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
50
- * +---------------------+---+-----+-----+-------+-------+-----+------+
28
- .writefn = zcr_write, .raw_writefn = raw_write
51
- */
29
-};
52
-static void disas_system(DisasContext *s, uint32_t insn)
53
+static bool trans_SYS(DisasContext *s, arg_SYS *a)
54
{
55
- unsigned int l, op0, op1, crn, crm, op2, rt;
56
- l = extract32(insn, 21, 1);
57
- op0 = extract32(insn, 19, 2);
58
- op1 = extract32(insn, 16, 3);
59
- crn = extract32(insn, 12, 4);
60
- crm = extract32(insn, 8, 4);
61
- op2 = extract32(insn, 5, 3);
62
- rt = extract32(insn, 0, 5);
30
-
63
-
31
-static const ARMCPRegInfo zcr_el2_reginfo = {
64
- if (op0 == 0) {
32
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
65
- unallocated_encoding(s);
33
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
66
- return;
34
- .access = PL2_RW, .type = ARM_CP_SVE,
67
- }
35
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
68
- handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
36
- .writefn = zcr_write, .raw_writefn = raw_write
69
+ handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt);
37
-};
70
+ return true;
38
-
71
}
39
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
72
40
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
73
/* Exception generation
41
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
74
@@ -XXX,XX +XXX,XX @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
42
- .access = PL2_RW, .type = ARM_CP_SVE,
75
switch (extract32(insn, 25, 7)) {
43
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
76
case 0x6a: /* Exception generation / System */
44
-};
77
if (insn & (1 << 24)) {
45
-
78
- if (extract32(insn, 22, 2) == 0) {
46
-static const ARMCPRegInfo zcr_el3_reginfo = {
79
- disas_system(s, insn);
47
- .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
80
- } else {
48
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
81
- unallocated_encoding(s);
49
- .access = PL3_RW, .type = ARM_CP_SVE,
82
- }
50
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
83
+ unallocated_encoding(s);
51
- .writefn = zcr_write, .raw_writefn = raw_write
84
} else {
52
+static const ARMCPRegInfo zcr_reginfo[] = {
85
disas_exc(s, insn);
53
+ { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
86
}
54
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
55
+ .access = PL1_RW, .type = ARM_CP_SVE,
56
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
57
+ .writefn = zcr_write, .raw_writefn = raw_write },
58
+ { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
59
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
60
+ .access = PL2_RW, .type = ARM_CP_SVE,
61
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
62
+ .writefn = zcr_write, .raw_writefn = raw_write },
63
+ { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
64
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
65
+ .access = PL3_RW, .type = ARM_CP_SVE,
66
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
67
+ .writefn = zcr_write, .raw_writefn = raw_write },
68
};
69
70
void hw_watchpoint_update(ARMCPU *cpu, int n)
71
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
72
}
73
74
if (cpu_isar_feature(aa64_sve, cpu)) {
75
- define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
76
- if (arm_feature(env, ARM_FEATURE_EL2)) {
77
- define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
78
- } else {
79
- define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
80
- }
81
- if (arm_feature(env, ARM_FEATURE_EL3)) {
82
- define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
83
- }
84
+ define_arm_cp_regs(cpu, zcr_reginfo);
85
}
86
87
#ifdef TARGET_AARCH64
88
--
87
--
89
2.25.1
88
2.34.1
89
90
diff view generated by jsdifflib
[PULL 09/32] target/arm: Split out aa32_max_features
[PULL 10/33] target/arm: Convert exception generation instructions to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the exception generation instructions SVC, HVC, SMC, BRK and
2
HLT to decodetree.
2
3
3
Share the code to set AArch32 max features so that we no
4
The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and
4
longer have code drift between qemu{-system,}-{arm,aarch64}.
5
DCPS3 just in order to then make them UNDEF; as with DRPS, we don't
6
bother to decode them, but document the patterns in a64.decode.
5
7
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org
10
---
11
---
11
target/arm/internals.h | 2 +
12
target/arm/tcg/a64.decode | 15 +++
12
target/arm/cpu64.c | 50 +-----------------
13
target/arm/tcg/translate-a64.c | 173 ++++++++++++---------------------
13
target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++-------------------
14
2 files changed, 79 insertions(+), 109 deletions(-)
14
3 files changed, 65 insertions(+), 101 deletions(-)
15
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
18
--- a/target/arm/tcg/a64.decode
19
+++ b/target/arm/internals.h
19
+++ b/target/arm/tcg/a64.decode
20
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
20
@@ -XXX,XX +XXX,XX @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
21
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
21
SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
22
#endif
22
SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
23
23
SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3
24
+void aa32_max_features(ARMCPU *cpu);
24
+
25
+
25
+# Exception generation
26
#endif
26
+
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
27
+@i16 .... .... ... imm:16 ... .. &i
28
+SVC 1101 0100 000 ................ 000 01 @i16
29
+HVC 1101 0100 000 ................ 000 10 @i16
30
+SMC 1101 0100 000 ................ 000 11 @i16
31
+BRK 1101 0100 001 ................ 000 00 @i16
32
+HLT 1101 0100 010 ................ 000 00 @i16
33
+# These insns always UNDEF unless in halting debug state, which
34
+# we don't implement. So we don't need to decode them. The patterns
35
+# are listed here as documentation.
36
+# DCPS1 1101 0100 101 ................ 000 01 @i16
37
+# DCPS2 1101 0100 101 ................ 000 10 @i16
38
+# DCPS3 1101 0100 101 ................ 000 11 @i16
39
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
28
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu64.c
41
--- a/target/arm/tcg/translate-a64.c
30
+++ b/target/arm/cpu64.c
42
+++ b/target/arm/tcg/translate-a64.c
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
43
@@ -XXX,XX +XXX,XX @@ static bool trans_SYS(DisasContext *s, arg_SYS *a)
44
return true;
45
}
46
47
-/* Exception generation
48
- *
49
- * 31 24 23 21 20 5 4 2 1 0
50
- * +-----------------+-----+------------------------+-----+----+
51
- * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
52
- * +-----------------------+------------------------+----------+
53
- */
54
-static void disas_exc(DisasContext *s, uint32_t insn)
55
+static bool trans_SVC(DisasContext *s, arg_i *a)
32
{
56
{
33
ARMCPU *cpu = ARM_CPU(obj);
57
- int opc = extract32(insn, 21, 3);
34
uint64_t t;
58
- int op2_ll = extract32(insn, 0, 5);
35
- uint32_t u;
59
- int imm16 = extract32(insn, 5, 16);
36
60
- uint32_t syndrome;
37
if (kvm_enabled() || hvf_enabled()) {
38
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
40
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
41
cpu->isar.id_aa64zfr0 = t;
42
43
- /* Replicate the same data to the 32-bit id registers. */
44
- u = cpu->isar.id_isar5;
45
- u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
46
- u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
47
- u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
48
- u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
49
- u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
50
- u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
51
- cpu->isar.id_isar5 = u;
52
-
61
-
53
- u = cpu->isar.id_isar6;
62
- switch (opc) {
54
- u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
63
- case 0:
55
- u = FIELD_DP32(u, ID_ISAR6, DP, 1);
64
- /* For SVC, HVC and SMC we advance the single-step state
56
- u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
65
- * machine before taking the exception. This is architecturally
57
- u = FIELD_DP32(u, ID_ISAR6, SB, 1);
66
- * mandated, to ensure that single-stepping a system call
58
- u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
67
- * instruction works properly.
59
- u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
68
- */
60
- u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
69
- switch (op2_ll) {
61
- cpu->isar.id_isar6 = u;
70
- case 1: /* SVC */
62
-
71
- syndrome = syn_aa64_svc(imm16);
63
- u = cpu->isar.id_pfr0;
72
- if (s->fgt_svc) {
64
- u = FIELD_DP32(u, ID_PFR0, DIT, 1);
73
- gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
65
- cpu->isar.id_pfr0 = u;
74
- break;
66
-
75
- }
67
- u = cpu->isar.id_pfr2;
76
- gen_ss_advance(s);
68
- u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
77
- gen_exception_insn(s, 4, EXCP_SWI, syndrome);
69
- cpu->isar.id_pfr2 = u;
78
- break;
70
-
79
- case 2: /* HVC */
71
- u = cpu->isar.id_mmfr3;
80
- if (s->current_el == 0) {
72
- u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
81
- unallocated_encoding(s);
73
- cpu->isar.id_mmfr3 = u;
82
- break;
74
-
83
- }
75
- u = cpu->isar.id_mmfr4;
84
- /* The pre HVC helper handles cases when HVC gets trapped
76
- u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
85
- * as an undefined insn by runtime configuration.
77
- u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
86
- */
78
- u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
87
- gen_a64_update_pc(s, 0);
79
- u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
88
- gen_helper_pre_hvc(cpu_env);
80
- cpu->isar.id_mmfr4 = u;
89
- gen_ss_advance(s);
81
-
90
- gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2);
82
t = cpu->isar.id_aa64dfr0;
91
- break;
83
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
92
- case 3: /* SMC */
84
cpu->isar.id_aa64dfr0 = t;
93
- if (s->current_el == 0) {
85
94
- unallocated_encoding(s);
86
- u = cpu->isar.id_dfr0;
95
- break;
87
- u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
96
- }
88
- cpu->isar.id_dfr0 = u;
97
- gen_a64_update_pc(s, 0);
89
-
98
- gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
90
- u = cpu->isar.mvfr1;
99
- gen_ss_advance(s);
91
- u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
100
- gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3);
92
- u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
101
- break;
93
- cpu->isar.mvfr1 = u;
102
- default:
94
+ /* Replicate the same data to the 32-bit id registers. */
103
- unallocated_encoding(s);
95
+ aa32_max_features(cpu);
104
- break;
96
105
- }
97
#ifdef CONFIG_USER_ONLY
106
- break;
98
/*
107
- case 1:
99
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
108
- if (op2_ll != 0) {
100
index XXXXXXX..XXXXXXX 100644
109
- unallocated_encoding(s);
101
--- a/target/arm/cpu_tcg.c
110
- break;
102
+++ b/target/arm/cpu_tcg.c
111
- }
103
@@ -XXX,XX +XXX,XX @@
112
- /* BRK */
104
#endif
113
- gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16));
105
#include "cpregs.h"
114
- break;
106
115
- case 2:
107
+
116
- if (op2_ll != 0) {
108
+/* Share AArch32 -cpu max features with AArch64. */
117
- unallocated_encoding(s);
109
+void aa32_max_features(ARMCPU *cpu)
118
- break;
119
- }
120
- /* HLT. This has two purposes.
121
- * Architecturally, it is an external halting debug instruction.
122
- * Since QEMU doesn't implement external debug, we treat this as
123
- * it is required for halting debug disabled: it will UNDEF.
124
- * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
125
- */
126
- if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) {
127
- gen_exception_internal_insn(s, EXCP_SEMIHOST);
128
- } else {
129
- unallocated_encoding(s);
130
- }
131
- break;
132
- case 5:
133
- if (op2_ll < 1 || op2_ll > 3) {
134
- unallocated_encoding(s);
135
- break;
136
- }
137
- /* DCPS1, DCPS2, DCPS3 */
138
- unallocated_encoding(s);
139
- break;
140
- default:
141
- unallocated_encoding(s);
142
- break;
143
+ /*
144
+ * For SVC, HVC and SMC we advance the single-step state
145
+ * machine before taking the exception. This is architecturally
146
+ * mandated, to ensure that single-stepping a system call
147
+ * instruction works properly.
148
+ */
149
+ uint32_t syndrome = syn_aa64_svc(a->imm);
150
+ if (s->fgt_svc) {
151
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
152
+ return true;
153
}
154
+ gen_ss_advance(s);
155
+ gen_exception_insn(s, 4, EXCP_SWI, syndrome);
156
+ return true;
157
}
158
159
-/* Branches, exception generating and system instructions */
160
-static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
161
+static bool trans_HVC(DisasContext *s, arg_i *a)
162
{
163
- switch (extract32(insn, 25, 7)) {
164
- case 0x6a: /* Exception generation / System */
165
- if (insn & (1 << 24)) {
166
- unallocated_encoding(s);
167
- } else {
168
- disas_exc(s, insn);
169
- }
170
- break;
171
- default:
172
+ if (s->current_el == 0) {
173
unallocated_encoding(s);
174
- break;
175
+ return true;
176
}
177
+ /*
178
+ * The pre HVC helper handles cases when HVC gets trapped
179
+ * as an undefined insn by runtime configuration.
180
+ */
181
+ gen_a64_update_pc(s, 0);
182
+ gen_helper_pre_hvc(cpu_env);
183
+ /* Architecture requires ss advance before we do the actual work */
184
+ gen_ss_advance(s);
185
+ gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2);
186
+ return true;
187
+}
188
+
189
+static bool trans_SMC(DisasContext *s, arg_i *a)
110
+{
190
+{
111
+ uint32_t t;
191
+ if (s->current_el == 0) {
112
+
192
+ unallocated_encoding(s);
113
+ /* Add additional features supported by QEMU */
193
+ return true;
114
+ t = cpu->isar.id_isar5;
194
+ }
115
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
195
+ gen_a64_update_pc(s, 0);
116
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
196
+ gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm)));
117
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
197
+ /* Architecture requires ss advance before we do the actual work */
118
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
198
+ gen_ss_advance(s);
119
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
199
+ gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3);
120
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
200
+ return true;
121
+ cpu->isar.id_isar5 = t;
122
+
123
+ t = cpu->isar.id_isar6;
124
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
125
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
126
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
127
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
128
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
129
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
130
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
131
+ cpu->isar.id_isar6 = t;
132
+
133
+ t = cpu->isar.mvfr1;
134
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
135
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
136
+ cpu->isar.mvfr1 = t;
137
+
138
+ t = cpu->isar.mvfr2;
139
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
140
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
141
+ cpu->isar.mvfr2 = t;
142
+
143
+ t = cpu->isar.id_mmfr3;
144
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
145
+ cpu->isar.id_mmfr3 = t;
146
+
147
+ t = cpu->isar.id_mmfr4;
148
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
149
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
150
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
151
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
152
+ cpu->isar.id_mmfr4 = t;
153
+
154
+ t = cpu->isar.id_pfr0;
155
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
156
+ cpu->isar.id_pfr0 = t;
157
+
158
+ t = cpu->isar.id_pfr2;
159
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
160
+ cpu->isar.id_pfr2 = t;
161
+
162
+ t = cpu->isar.id_dfr0;
163
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
164
+ cpu->isar.id_dfr0 = t;
165
+}
201
+}
166
+
202
+
167
#ifndef CONFIG_USER_ONLY
203
+static bool trans_BRK(DisasContext *s, arg_i *a)
168
static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
204
+{
205
+ gen_exception_bkpt_insn(s, syn_aa64_bkpt(a->imm));
206
+ return true;
207
+}
208
+
209
+static bool trans_HLT(DisasContext *s, arg_i *a)
210
+{
211
+ /*
212
+ * HLT. This has two purposes.
213
+ * Architecturally, it is an external halting debug instruction.
214
+ * Since QEMU doesn't implement external debug, we treat this as
215
+ * it is required for halting debug disabled: it will UNDEF.
216
+ * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
217
+ */
218
+ if (semihosting_enabled(s->current_el == 0) && a->imm == 0xf000) {
219
+ gen_exception_internal_insn(s, EXCP_SEMIHOST);
220
+ } else {
221
+ unallocated_encoding(s);
222
+ }
223
+ return true;
224
}
225
226
/*
227
@@ -XXX,XX +XXX,XX @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype)
228
static void disas_a64_legacy(DisasContext *s, uint32_t insn)
169
{
229
{
170
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
230
switch (extract32(insn, 25, 4)) {
171
static void arm_max_initfn(Object *obj)
231
- case 0xa: case 0xb: /* Branch, exception generation and system insns */
172
{
232
- disas_b_exc_sys(s, insn);
173
ARMCPU *cpu = ARM_CPU(obj);
233
- break;
174
- uint32_t t;
234
case 0x4:
175
235
case 0x6:
176
/* aarch64_a57_initfn, advertising none of the aarch64 features */
236
case 0xc:
177
cpu->dtb_compatible = "arm,cortex-a57";
178
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
179
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
180
define_cortex_a72_a57_a53_cp_reginfo(cpu);
181
182
- /* Add additional features supported by QEMU */
183
- t = cpu->isar.id_isar5;
184
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
185
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
186
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
187
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
188
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
189
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
190
- cpu->isar.id_isar5 = t;
191
-
192
- t = cpu->isar.id_isar6;
193
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
194
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
195
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
196
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
197
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
198
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
199
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
200
- cpu->isar.id_isar6 = t;
201
-
202
- t = cpu->isar.mvfr1;
203
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
204
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
205
- cpu->isar.mvfr1 = t;
206
-
207
- t = cpu->isar.mvfr2;
208
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
- cpu->isar.mvfr2 = t;
211
-
212
- t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
- cpu->isar.id_mmfr3 = t;
215
-
216
- t = cpu->isar.id_mmfr4;
217
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
218
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
219
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
220
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
221
- cpu->isar.id_mmfr4 = t;
222
-
223
- t = cpu->isar.id_pfr0;
224
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
225
- cpu->isar.id_pfr0 = t;
226
-
227
- t = cpu->isar.id_pfr2;
228
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
229
- cpu->isar.id_pfr2 = t;
230
-
231
- t = cpu->isar.id_dfr0;
232
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
233
- cpu->isar.id_dfr0 = t;
234
+ aa32_max_features(cpu);
235
236
#ifdef CONFIG_USER_ONLY
237
/*
238
--
237
--
239
2.25.1
238
2.34.1
diff view generated by jsdifflib
[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
[PULL 11/33] target/arm: Convert load/store exclusive and ordered to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the instructions in the load/store exclusive (STXR,
2
2
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
3
This extension concerns changes to the External Debug interface,
3
LDAR, LDLAR) to decodetree.
4
with Secure and Non-secure access to the debug registers, and all
4
5
of it is outside the scope of QEMU. Indicating support for this
5
Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
6
is mandatory with FEAT_SEL2, which we do implement.
6
in the legacy decoder where we were not checking that the RES1 bits
7
7
in the Rs and Rt2 fields were set.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
The new function ldst_iss_sf() is equivalent to the existing
10
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
10
disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field
11
rather than taking an undecoded two-bit opc field and extracting
12
'ext' from it. Once all the loads and stores have been converted
13
to decodetree disas_ldst_compute_iss_sf() will be unused and
14
can be deleted.
15
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
12
---
19
---
13
docs/system/arm/emulation.rst | 1 +
20
target/arm/tcg/a64.decode | 11 +++
14
target/arm/cpu64.c | 2 +-
21
target/arm/tcg/translate-a64.c | 154 ++++++++++++++++++++-------------
15
target/arm/cpu_tcg.c | 4 ++--
22
2 files changed, 103 insertions(+), 62 deletions(-)
16
3 files changed, 4 insertions(+), 3 deletions(-)
23
17
24
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
18
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/emulation.rst
26
--- a/target/arm/tcg/a64.decode
21
+++ b/docs/system/arm/emulation.rst
27
+++ b/target/arm/tcg/a64.decode
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
28
@@ -XXX,XX +XXX,XX @@ HLT 1101 0100 010 ................ 000 00 @i16
23
- FEAT_DIT (Data Independent Timing instructions)
29
# DCPS1 1101 0100 101 ................ 000 01 @i16
24
- FEAT_DPB (DC CVAP instruction)
30
# DCPS2 1101 0100 101 ................ 000 10 @i16
25
- FEAT_Debugv8p2 (Debug changes for v8.2)
31
# DCPS3 1101 0100 101 ................ 000 11 @i16
26
+- FEAT_Debugv8p4 (Debug changes for v8.4)
32
+
27
- FEAT_DotProd (Advanced SIMD dot product instructions)
33
+# Loads and stores
28
- FEAT_FCMA (Floating-point complex number instructions)
34
+
29
- FEAT_FHM (Floating-point half-precision multiplication instructions)
35
+&stxr rn rt rt2 rs sz lasr
30
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
36
+&stlr rn rt sz lasr
37
+@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr
38
+@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr
39
+STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR
40
+LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR
41
+STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR
42
+LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR
43
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
31
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu64.c
45
--- a/target/arm/tcg/translate-a64.c
33
+++ b/target/arm/cpu64.c
46
+++ b/target/arm/tcg/translate-a64.c
34
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
47
@@ -XXX,XX +XXX,XX @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
35
cpu->isar.id_aa64zfr0 = t;
48
return regsize == 64;
36
49
}
37
t = cpu->isar.id_aa64dfr0;
50
38
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
51
+static bool ldst_iss_sf(int size, bool sign, bool ext)
39
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
52
+{
40
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
53
+
41
cpu->isar.id_aa64dfr0 = t;
54
+ if (sign) {
42
55
+ /*
43
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
56
+ * Signed loads are 64 bit results if we are not going to
44
index XXXXXXX..XXXXXXX 100644
57
+ * do a zero-extend from 32 to 64 after the load.
45
--- a/target/arm/cpu_tcg.c
58
+ * (For a store, sign and ext are always false.)
46
+++ b/target/arm/cpu_tcg.c
59
+ */
47
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
60
+ return !ext;
48
cpu->isar.id_pfr2 = t;
61
+ } else {
49
62
+ /* Unsigned loads/stores work at the specified size */
50
t = cpu->isar.id_dfr0;
63
+ return size == MO_64;
51
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
64
+ }
52
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
65
+}
53
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
66
+
54
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
67
+static bool trans_STXR(DisasContext *s, arg_stxr *a)
55
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
68
+{
56
cpu->isar.id_dfr0 = t;
69
+ if (a->rn == 31) {
70
+ gen_check_sp_alignment(s);
71
+ }
72
+ if (a->lasr) {
73
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
74
+ }
75
+ gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, false);
76
+ return true;
77
+}
78
+
79
+static bool trans_LDXR(DisasContext *s, arg_stxr *a)
80
+{
81
+ if (a->rn == 31) {
82
+ gen_check_sp_alignment(s);
83
+ }
84
+ gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, false);
85
+ if (a->lasr) {
86
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
87
+ }
88
+ return true;
89
+}
90
+
91
+static bool trans_STLR(DisasContext *s, arg_stlr *a)
92
+{
93
+ TCGv_i64 clean_addr;
94
+ MemOp memop;
95
+ bool iss_sf = ldst_iss_sf(a->sz, false, false);
96
+
97
+ /*
98
+ * StoreLORelease is the same as Store-Release for QEMU, but
99
+ * needs the feature-test.
100
+ */
101
+ if (!a->lasr && !dc_isar_feature(aa64_lor, s)) {
102
+ return false;
103
+ }
104
+ /* Generate ISS for non-exclusive accesses including LASR. */
105
+ if (a->rn == 31) {
106
+ gen_check_sp_alignment(s);
107
+ }
108
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
109
+ memop = check_ordered_align(s, a->rn, 0, true, a->sz);
110
+ clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn),
111
+ true, a->rn != 31, memop);
112
+ do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt,
113
+ iss_sf, a->lasr);
114
+ return true;
115
+}
116
+
117
+static bool trans_LDAR(DisasContext *s, arg_stlr *a)
118
+{
119
+ TCGv_i64 clean_addr;
120
+ MemOp memop;
121
+ bool iss_sf = ldst_iss_sf(a->sz, false, false);
122
+
123
+ /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
124
+ if (!a->lasr && !dc_isar_feature(aa64_lor, s)) {
125
+ return false;
126
+ }
127
+ /* Generate ISS for non-exclusive accesses including LASR. */
128
+ if (a->rn == 31) {
129
+ gen_check_sp_alignment(s);
130
+ }
131
+ memop = check_ordered_align(s, a->rn, 0, false, a->sz);
132
+ clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn),
133
+ false, a->rn != 31, memop);
134
+ do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, memop, false, true,
135
+ a->rt, iss_sf, a->lasr);
136
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
137
+ return true;
138
+}
139
+
140
/* Load/store exclusive
141
*
142
* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
143
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
144
int is_lasr = extract32(insn, 15, 1);
145
int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr;
146
int size = extract32(insn, 30, 2);
147
- TCGv_i64 clean_addr;
148
- MemOp memop;
149
150
switch (o2_L_o1_o0) {
151
- case 0x0: /* STXR */
152
- case 0x1: /* STLXR */
153
- if (rn == 31) {
154
- gen_check_sp_alignment(s);
155
- }
156
- if (is_lasr) {
157
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
158
- }
159
- gen_store_exclusive(s, rs, rt, rt2, rn, size, false);
160
- return;
161
-
162
- case 0x4: /* LDXR */
163
- case 0x5: /* LDAXR */
164
- if (rn == 31) {
165
- gen_check_sp_alignment(s);
166
- }
167
- gen_load_exclusive(s, rt, rt2, rn, size, false);
168
- if (is_lasr) {
169
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
170
- }
171
- return;
172
-
173
- case 0x8: /* STLLR */
174
- if (!dc_isar_feature(aa64_lor, s)) {
175
- break;
176
- }
177
- /* StoreLORelease is the same as Store-Release for QEMU. */
178
- /* fall through */
179
- case 0x9: /* STLR */
180
- /* Generate ISS for non-exclusive accesses including LASR. */
181
- if (rn == 31) {
182
- gen_check_sp_alignment(s);
183
- }
184
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
185
- memop = check_ordered_align(s, rn, 0, true, size);
186
- clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
187
- true, rn != 31, memop);
188
- do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt,
189
- disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
190
- return;
191
-
192
- case 0xc: /* LDLAR */
193
- if (!dc_isar_feature(aa64_lor, s)) {
194
- break;
195
- }
196
- /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
197
- /* fall through */
198
- case 0xd: /* LDAR */
199
- /* Generate ISS for non-exclusive accesses including LASR. */
200
- if (rn == 31) {
201
- gen_check_sp_alignment(s);
202
- }
203
- memop = check_ordered_align(s, rn, 0, false, size);
204
- clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
205
- false, rn != 31, memop);
206
- do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true,
207
- rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
208
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
209
- return;
210
-
211
case 0x2: case 0x3: /* CASP / STXP */
212
if (size & 2) { /* STXP / STLXP */
213
if (rn == 31) {
214
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
215
return;
216
}
217
break;
218
+ default:
219
+ /* Handled in decodetree */
220
+ break;
221
}
222
unallocated_encoding(s);
57
}
223
}
58
--
224
--
59
2.25.1
225
2.34.1
diff view generated by jsdifflib
[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
[PULL 12/33] target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP),
2
compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and
3
swap (CAS, CASA, CASAL, CASL) instructions to decodetree.
2
4
3
There is no branch prediction in TCG, therefore there is no
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
need to actually include the context number into the predictor.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Therefore all we need to do is add the state for SCXTNUM_ELx.
7
Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org
8
---
9
target/arm/tcg/a64.decode | 11 +++
10
target/arm/tcg/translate-a64.c | 121 ++++++++++++---------------------
11
2 files changed, 53 insertions(+), 79 deletions(-)
6
12
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 3 ++
13
target/arm/cpu.h | 16 +++++++++
14
target/arm/cpu.c | 5 +++
15
target/arm/cpu64.c | 3 +-
16
target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++-
17
5 files changed, 86 insertions(+), 2 deletions(-)
18
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
15
--- a/target/arm/tcg/a64.decode
22
+++ b/docs/system/arm/emulation.rst
16
+++ b/target/arm/tcg/a64.decode
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
17
@@ -XXX,XX +XXX,XX @@ HLT 1101 0100 010 ................ 000 00 @i16
24
- FEAT_BF16 (AArch64 BFloat16 instructions)
18
&stlr rn rt sz lasr
25
- FEAT_BTI (Branch Target Identification)
19
@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr
26
- FEAT_CSV2 (Cache speculation variant 2)
20
@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr
27
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
21
+%imm1_30_p2 30:1 !function=plus_2
28
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
22
+@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2
29
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
23
STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR
30
- FEAT_DIT (Data Independent Timing instructions)
24
LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR
31
- FEAT_DPB (DC CVAP instruction)
25
STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR
32
- FEAT_Debugv8p2 (Debug changes for v8.2)
26
LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
27
+
28
+STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP
29
+LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP
30
+
31
+# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine
32
+# acquire/release semantics because QEMU's cmpxchg always has those)
33
+CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
34
+# CAS, CASA, CASAL, CASL
35
+CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
36
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
34
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
38
--- a/target/arm/tcg/translate-a64.c
36
+++ b/target/arm/cpu.h
39
+++ b/target/arm/tcg/translate-a64.c
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
40
@@ -XXX,XX +XXX,XX @@ static bool trans_LDAR(DisasContext *s, arg_stlr *a)
38
ARMPACKey apdb;
41
return true;
39
ARMPACKey apga;
40
} keys;
41
+
42
+ uint64_t scxtnum_el[4];
43
#endif
44
45
#if defined(CONFIG_USER_ONLY)
46
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
47
#define SCTLR_WXN (1U << 19)
48
#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
49
#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
50
+#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
51
#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
52
#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
53
#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
54
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
55
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
56
}
42
}
57
43
58
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
44
-/* Load/store exclusive
59
+{
45
- *
60
+ int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
46
- * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
61
+ if (key >= 2) {
47
- * +-----+-------------+----+---+----+------+----+-------+------+------+
62
+ return true; /* FEAT_CSV2_2 */
48
- * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
49
- * +-----+-------------+----+---+----+------+----+-------+------+------+
50
- *
51
- * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
52
- * L: 0 -> store, 1 -> load
53
- * o2: 0 -> exclusive, 1 -> not
54
- * o1: 0 -> single register, 1 -> register pair
55
- * o0: 1 -> load-acquire/store-release, 0 -> not
56
- */
57
-static void disas_ldst_excl(DisasContext *s, uint32_t insn)
58
+static bool trans_STXP(DisasContext *s, arg_stxr *a)
59
{
60
- int rt = extract32(insn, 0, 5);
61
- int rn = extract32(insn, 5, 5);
62
- int rt2 = extract32(insn, 10, 5);
63
- int rs = extract32(insn, 16, 5);
64
- int is_lasr = extract32(insn, 15, 1);
65
- int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr;
66
- int size = extract32(insn, 30, 2);
67
-
68
- switch (o2_L_o1_o0) {
69
- case 0x2: case 0x3: /* CASP / STXP */
70
- if (size & 2) { /* STXP / STLXP */
71
- if (rn == 31) {
72
- gen_check_sp_alignment(s);
73
- }
74
- if (is_lasr) {
75
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
76
- }
77
- gen_store_exclusive(s, rs, rt, rt2, rn, size, true);
78
- return;
79
- }
80
- if (rt2 == 31
81
- && ((rt | rs) & 1) == 0
82
- && dc_isar_feature(aa64_atomics, s)) {
83
- /* CASP / CASPL */
84
- gen_compare_and_swap_pair(s, rs, rt, rn, size | 2);
85
- return;
86
- }
87
- break;
88
-
89
- case 0x6: case 0x7: /* CASPA / LDXP */
90
- if (size & 2) { /* LDXP / LDAXP */
91
- if (rn == 31) {
92
- gen_check_sp_alignment(s);
93
- }
94
- gen_load_exclusive(s, rt, rt2, rn, size, true);
95
- if (is_lasr) {
96
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
97
- }
98
- return;
99
- }
100
- if (rt2 == 31
101
- && ((rt | rs) & 1) == 0
102
- && dc_isar_feature(aa64_atomics, s)) {
103
- /* CASPA / CASPAL */
104
- gen_compare_and_swap_pair(s, rs, rt, rn, size | 2);
105
- return;
106
- }
107
- break;
108
-
109
- case 0xa: /* CAS */
110
- case 0xb: /* CASL */
111
- case 0xe: /* CASA */
112
- case 0xf: /* CASAL */
113
- if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) {
114
- gen_compare_and_swap(s, rs, rt, rn, size);
115
- return;
116
- }
117
- break;
118
- default:
119
- /* Handled in decodetree */
120
- break;
121
+ if (a->rn == 31) {
122
+ gen_check_sp_alignment(s);
123
}
124
- unallocated_encoding(s);
125
+ if (a->lasr) {
126
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
63
+ }
127
+ }
64
+ if (key == 1) {
128
+ gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, true);
65
+ key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
129
+ return true;
66
+ return key >= 2; /* FEAT_CSV2_1p2 */
67
+ }
68
+ return false;
69
+}
130
+}
70
+
131
+
71
static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
132
+static bool trans_LDXP(DisasContext *s, arg_stxr *a)
72
{
73
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
74
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/cpu.c
77
+++ b/target/arm/cpu.c
78
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
79
*/
80
env->cp15.gcr_el1 = 0x1ffff;
81
}
82
+ /*
83
+ * Disable access to SCXTNUM_EL0 from CSV2_1p2.
84
+ * This is not yet exposed from the Linux kernel in any way.
85
+ */
86
+ env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
87
#else
88
/* Reset into the highest available EL */
89
if (arm_feature(env, ARM_FEATURE_EL3)) {
90
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/cpu64.c
93
+++ b/target/arm/cpu64.c
94
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
95
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
96
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
97
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
98
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
99
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
100
cpu->isar.id_aa64pfr0 = t;
101
102
t = cpu->isar.id_aa64pfr1;
103
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
104
* we do for EL2 with the virtualization=on property.
105
*/
106
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
107
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
108
cpu->isar.id_aa64pfr1 = t;
109
110
t = cpu->isar.id_aa64mmfr0;
111
diff --git a/target/arm/helper.c b/target/arm/helper.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/helper.c
114
+++ b/target/arm/helper.c
115
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
116
if (cpu_isar_feature(aa64_mte, cpu)) {
117
valid_mask |= SCR_ATA;
118
}
119
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
120
+ valid_mask |= SCR_ENSCXT;
121
+ }
122
} else {
123
valid_mask &= ~(SCR_RW | SCR_ST);
124
if (cpu_isar_feature(aa32_ras, cpu)) {
125
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
126
if (cpu_isar_feature(aa64_mte, cpu)) {
127
valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
128
}
129
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
130
+ valid_mask |= HCR_ENSCXT;
131
+ }
132
}
133
134
/* Clear RES0 bits. */
135
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
136
{ K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
137
"TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
138
139
+ { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
140
+ "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
141
+ isar_feature_aa64_scxtnum },
142
+
143
/* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
144
/* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
145
};
146
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
147
},
148
};
149
150
-#endif
151
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
152
+ bool isread)
153
+{
133
+{
154
+ uint64_t hcr = arm_hcr_el2_eff(env);
134
+ if (a->rn == 31) {
155
+ int el = arm_current_el(env);
135
+ gen_check_sp_alignment(s);
156
+
157
+ if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
158
+ if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
159
+ if (hcr & HCR_TGE) {
160
+ return CP_ACCESS_TRAP_EL2;
161
+ }
162
+ return CP_ACCESS_TRAP;
163
+ }
164
+ } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
165
+ return CP_ACCESS_TRAP_EL2;
166
+ }
136
+ }
167
+ if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
137
+ gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, true);
168
+ return CP_ACCESS_TRAP_EL2;
138
+ if (a->lasr) {
139
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
169
+ }
140
+ }
170
+ if (el < 3
141
+ return true;
171
+ && arm_feature(env, ARM_FEATURE_EL3)
172
+ && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
173
+ return CP_ACCESS_TRAP_EL3;
174
+ }
175
+ return CP_ACCESS_OK;
176
+}
142
+}
177
+
143
+
178
+static const ARMCPRegInfo scxtnum_reginfo[] = {
144
+static bool trans_CASP(DisasContext *s, arg_CASP *a)
179
+ { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
145
+{
180
+ .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
146
+ if (!dc_isar_feature(aa64_atomics, s)) {
181
+ .access = PL0_RW, .accessfn = access_scxtnum,
147
+ return false;
182
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
148
+ }
183
+ { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
149
+ if (((a->rt | a->rs) & 1) != 0) {
184
+ .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
150
+ return false;
185
+ .access = PL1_RW, .accessfn = access_scxtnum,
151
+ }
186
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
187
+ { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
188
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
189
+ .access = PL2_RW, .accessfn = access_scxtnum,
190
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
191
+ { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
192
+ .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
193
+ .access = PL3_RW,
194
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
195
+};
196
+#endif /* TARGET_AARCH64 */
197
198
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
199
bool isread)
200
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
201
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
202
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
203
}
204
+
152
+
205
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
153
+ gen_compare_and_swap_pair(s, a->rs, a->rt, a->rn, a->sz);
206
+ define_arm_cp_regs(cpu, scxtnum_reginfo);
154
+ return true;
155
+}
156
+
157
+static bool trans_CAS(DisasContext *s, arg_CAS *a)
158
+{
159
+ if (!dc_isar_feature(aa64_atomics, s)) {
160
+ return false;
207
+ }
161
+ }
208
#endif
162
+ gen_compare_and_swap(s, a->rs, a->rt, a->rn, a->sz);
209
163
+ return true;
210
if (cpu_isar_feature(any_predinv, cpu)) {
164
}
165
166
/*
167
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
168
static void disas_ldst(DisasContext *s, uint32_t insn)
169
{
170
switch (extract32(insn, 24, 6)) {
171
- case 0x08: /* Load/store exclusive */
172
- disas_ldst_excl(s, insn);
173
- break;
174
case 0x18: case 0x1c: /* Load register (literal) */
175
disas_ld_lit(s, insn);
176
break;
211
--
177
--
212
2.25.1
178
2.34.1
diff view generated by jsdifflib
[PULL 25/32] target/arm: Define neoverse-n1
[PULL 13/33] target/arm: Convert load reg (literal) group to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the "Load register (literal)" instruction class to
2
decodetree.
2
3
3
Enable the n1 for virt and sbsa board use.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230602155223.2040685-11-peter.maydell@linaro.org
7
---
8
target/arm/tcg/a64.decode | 13 ++++++
9
target/arm/tcg/translate-a64.c | 76 ++++++++++------------------------
10
2 files changed, 35 insertions(+), 54 deletions(-)
4
11
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
docs/system/arm/virt.rst | 1 +
11
hw/arm/sbsa-ref.c | 1 +
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
15
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/virt.rst
14
--- a/target/arm/tcg/a64.decode
19
+++ b/docs/system/arm/virt.rst
15
+++ b/target/arm/tcg/a64.decode
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
16
@@ -XXX,XX +XXX,XX @@ LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP
21
- ``cortex-a76`` (64-bit)
17
CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
22
- ``a64fx`` (64-bit)
18
# CAS, CASA, CASAL, CASL
23
- ``host`` (with KVM only)
19
CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
24
+- ``neoverse-n1`` (64-bit)
20
+
25
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
21
+&ldlit rt imm sz sign
26
22
+@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19
27
Note that the default is ``cortex-a15``, so for an AArch64 guest you must
23
+
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
24
+LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0
25
+LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0
26
+LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1
27
+LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0
28
+LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0
29
+LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0
30
+
31
+# PRFM
32
+NOP 11 011 0 00 ------------------- -----
33
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/sbsa-ref.c
35
--- a/target/arm/tcg/translate-a64.c
31
+++ b/hw/arm/sbsa-ref.c
36
+++ b/target/arm/tcg/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
37
@@ -XXX,XX +XXX,XX @@ static bool trans_CAS(DisasContext *s, arg_CAS *a)
33
ARM_CPU_TYPE_NAME("cortex-a57"),
38
return true;
34
ARM_CPU_TYPE_NAME("cortex-a72"),
35
ARM_CPU_TYPE_NAME("cortex-a76"),
36
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
37
ARM_CPU_TYPE_NAME("max"),
38
};
39
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a72"),
46
ARM_CPU_TYPE_NAME("cortex-a76"),
47
ARM_CPU_TYPE_NAME("a64fx"),
48
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
49
ARM_CPU_TYPE_NAME("host"),
50
ARM_CPU_TYPE_NAME("max"),
51
};
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
57
cpu->isar.mvfr2 = 0x00000043;
58
}
39
}
59
40
60
+static void aarch64_neoverse_n1_initfn(Object *obj)
41
-/*
61
+{
42
- * Load register (literal)
62
+ ARMCPU *cpu = ARM_CPU(obj);
43
- *
44
- * 31 30 29 27 26 25 24 23 5 4 0
45
- * +-----+-------+---+-----+-------------------+-------+
46
- * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
47
- * +-----+-------+---+-----+-------------------+-------+
48
- *
49
- * V: 1 -> vector (simd/fp)
50
- * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
51
- * 10-> 32 bit signed, 11 -> prefetch
52
- * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
53
- */
54
-static void disas_ld_lit(DisasContext *s, uint32_t insn)
55
+static bool trans_LD_lit(DisasContext *s, arg_ldlit *a)
56
{
57
- int rt = extract32(insn, 0, 5);
58
- int64_t imm = sextract32(insn, 5, 19) << 2;
59
- bool is_vector = extract32(insn, 26, 1);
60
- int opc = extract32(insn, 30, 2);
61
- bool is_signed = false;
62
- int size = 2;
63
- TCGv_i64 tcg_rt, clean_addr;
64
+ bool iss_sf = ldst_iss_sf(a->sz, a->sign, false);
65
+ TCGv_i64 tcg_rt = cpu_reg(s, a->rt);
66
+ TCGv_i64 clean_addr = tcg_temp_new_i64();
67
+ MemOp memop = finalize_memop(s, a->sz + a->sign * MO_SIGN);
63
+
68
+
64
+ cpu->dtb_compatible = "arm,neoverse-n1";
69
+ gen_pc_plus_diff(s, clean_addr, a->imm);
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
70
+ do_gpr_ld(s, tcg_rt, clean_addr, memop,
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
71
+ false, true, a->rt, iss_sf, false);
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
72
+ return true;
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
73
+
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
75
+ cpu->clidr = 0x82000023;
76
+ cpu->ctr = 0x8444c004;
77
+ cpu->dcz_blocksize = 4;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0c1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.23 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
110
+
111
+ /* From B2.98 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
123
+}
73
+}
124
+
74
+
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
75
+static bool trans_LD_lit_v(DisasContext *s, arg_ldlit *a)
76
+{
77
+ /* Load register (literal), vector version */
78
+ TCGv_i64 clean_addr;
79
MemOp memop;
80
81
- if (is_vector) {
82
- if (opc == 3) {
83
- unallocated_encoding(s);
84
- return;
85
- }
86
- size = 2 + opc;
87
- if (!fp_access_check(s)) {
88
- return;
89
- }
90
- memop = finalize_memop_asimd(s, size);
91
- } else {
92
- if (opc == 3) {
93
- /* PRFM (literal) : prefetch */
94
- return;
95
- }
96
- size = 2 + extract32(opc, 0, 1);
97
- is_signed = extract32(opc, 1, 1);
98
- memop = finalize_memop(s, size + is_signed * MO_SIGN);
99
+ if (!fp_access_check(s)) {
100
+ return true;
101
}
102
-
103
- tcg_rt = cpu_reg(s, rt);
104
-
105
+ memop = finalize_memop_asimd(s, a->sz);
106
clean_addr = tcg_temp_new_i64();
107
- gen_pc_plus_diff(s, clean_addr, imm);
108
-
109
- if (is_vector) {
110
- do_fp_ld(s, rt, clean_addr, memop);
111
- } else {
112
- /* Only unsigned 32bit loads target 32bit registers. */
113
- bool iss_sf = opc != 0;
114
- do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, false);
115
- }
116
+ gen_pc_plus_diff(s, clean_addr, a->imm);
117
+ do_fp_ld(s, a->rt, clean_addr, memop);
118
+ return true;
119
}
120
121
/*
122
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
123
static void disas_ldst(DisasContext *s, uint32_t insn)
126
{
124
{
127
/*
125
switch (extract32(insn, 24, 6)) {
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
126
- case 0x18: case 0x1c: /* Load register (literal) */
129
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
127
- disas_ld_lit(s, insn);
130
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
128
- break;
131
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
129
case 0x28: case 0x29:
132
+ { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
130
case 0x2c: case 0x2d: /* Load/store pair (all forms) */
133
{ .name = "max", .initfn = aarch64_max_initfn },
131
disas_ldst_pair(s, insn);
134
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
135
{ .name = "host", .initfn = aarch64_host_initfn },
136
--
132
--
137
2.25.1
133
2.34.1
diff view generated by jsdifflib
[PULL 02/32] target/arm: Handle cpreg registration for missing EL
[PULL 14/33] target/arm: Convert load/store-pair to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the load/store register pair insns (LDP, STP,
2
LDNP, STNP, LDPSW, STGP) to decodetree.
2
3
3
More gracefully handle cpregs when EL2 and/or EL3 are missing.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
If the reg is entirely inaccessible, do not register it at all.
5
Message-id: 20230602155223.2040685-12-peter.maydell@linaro.org
5
If the reg is for EL2, and EL3 is present but EL2 is not,
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
either discard, squash to res0, const, or keep unchanged.
7
---
8
target/arm/tcg/a64.decode | 61 +++++
9
target/arm/tcg/translate-a64.c | 422 ++++++++++++++++-----------------
10
2 files changed, 268 insertions(+), 215 deletions(-)
7
11
8
Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
9
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
10
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
11
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
12
13
This will simplify cpreg registration for conditional arm features.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/cpregs.h | 11 +++
21
target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
22
2 files changed, 133 insertions(+), 56 deletions(-)
23
24
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
25
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpregs.h
14
--- a/target/arm/tcg/a64.decode
27
+++ b/target/arm/cpregs.h
15
+++ b/target/arm/tcg/a64.decode
28
@@ -XXX,XX +XXX,XX @@ enum {
16
@@ -XXX,XX +XXX,XX @@ LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0
29
ARM_CP_SVE = 1 << 14,
17
30
/* Flag: Do not expose in gdb sysreg xml. */
18
# PRFM
31
ARM_CP_NO_GDB = 1 << 15,
19
NOP 11 011 0 00 ------------------- -----
20
+
21
+&ldstpair rt2 rt rn imm sz sign w p
22
+@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair
23
+
24
+# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches
25
+# so we ignore hints about data access patterns, and handle these like
26
+# plain signed offset.
27
+STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
28
+LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
29
+STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
30
+LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
31
+STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
32
+LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
33
+STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
34
+LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
35
+STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
36
+LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
37
+
38
+# STP and LDP: post-indexed
39
+STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
40
+LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
41
+LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1
42
+STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
43
+LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
44
+STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
45
+LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
46
+STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
47
+LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
48
+STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
49
+LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
50
+
51
+# STP and LDP: offset
52
+STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
53
+LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
54
+LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0
55
+STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
56
+LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
57
+STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
58
+LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
59
+STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
60
+LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
61
+STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
62
+LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
63
+
64
+# STP and LDP: pre-indexed
65
+STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
66
+LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
67
+LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1
68
+STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
69
+LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
70
+STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
71
+LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
72
+STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
73
+LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
74
+STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
75
+LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
76
+
77
+# STGP: store tag and pair
78
+STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
79
+STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
80
+STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
81
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/tcg/translate-a64.c
84
+++ b/target/arm/tcg/translate-a64.c
85
@@ -XXX,XX +XXX,XX @@ static bool trans_LD_lit_v(DisasContext *s, arg_ldlit *a)
86
return true;
87
}
88
89
-/*
90
- * LDNP (Load Pair - non-temporal hint)
91
- * LDP (Load Pair - non vector)
92
- * LDPSW (Load Pair Signed Word - non vector)
93
- * STNP (Store Pair - non-temporal hint)
94
- * STP (Store Pair - non vector)
95
- * LDNP (Load Pair of SIMD&FP - non-temporal hint)
96
- * LDP (Load Pair of SIMD&FP)
97
- * STNP (Store Pair of SIMD&FP - non-temporal hint)
98
- * STP (Store Pair of SIMD&FP)
99
- *
100
- * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
101
- * +-----+-------+---+---+-------+---+-----------------------------+
102
- * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
103
- * +-----+-------+---+---+-------+---+-------+-------+------+------+
104
- *
105
- * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
106
- * LDPSW/STGP 01
107
- * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
108
- * V: 0 -> GPR, 1 -> Vector
109
- * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
110
- * 10 -> signed offset, 11 -> pre-index
111
- * L: 0 -> Store 1 -> Load
112
- *
113
- * Rt, Rt2 = GPR or SIMD registers to be stored
114
- * Rn = general purpose register containing address
115
- * imm7 = signed offset (multiple of 4 or 8 depending on size)
116
- */
117
-static void disas_ldst_pair(DisasContext *s, uint32_t insn)
118
+static void op_addr_ldstpair_pre(DisasContext *s, arg_ldstpair *a,
119
+ TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr,
120
+ uint64_t offset, bool is_store, MemOp mop)
121
{
122
- int rt = extract32(insn, 0, 5);
123
- int rn = extract32(insn, 5, 5);
124
- int rt2 = extract32(insn, 10, 5);
125
- uint64_t offset = sextract64(insn, 15, 7);
126
- int index = extract32(insn, 23, 2);
127
- bool is_vector = extract32(insn, 26, 1);
128
- bool is_load = extract32(insn, 22, 1);
129
- int opc = extract32(insn, 30, 2);
130
- bool is_signed = false;
131
- bool postindex = false;
132
- bool wback = false;
133
- bool set_tag = false;
134
- TCGv_i64 clean_addr, dirty_addr;
135
- MemOp mop;
136
- int size;
137
-
138
- if (opc == 3) {
139
- unallocated_encoding(s);
140
- return;
141
- }
142
-
143
- if (is_vector) {
144
- size = 2 + opc;
145
- } else if (opc == 1 && !is_load) {
146
- /* STGP */
147
- if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) {
148
- unallocated_encoding(s);
149
- return;
150
- }
151
- size = 3;
152
- set_tag = true;
153
- } else {
154
- size = 2 + extract32(opc, 1, 1);
155
- is_signed = extract32(opc, 0, 1);
156
- if (!is_load && is_signed) {
157
- unallocated_encoding(s);
158
- return;
159
- }
160
- }
161
-
162
- switch (index) {
163
- case 1: /* post-index */
164
- postindex = true;
165
- wback = true;
166
- break;
167
- case 0:
168
- /* signed offset with "non-temporal" hint. Since we don't emulate
169
- * caches we don't care about hints to the cache system about
170
- * data access patterns, and handle this identically to plain
171
- * signed offset.
172
- */
173
- if (is_signed) {
174
- /* There is no non-temporal-hint version of LDPSW */
175
- unallocated_encoding(s);
176
- return;
177
- }
178
- postindex = false;
179
- break;
180
- case 2: /* signed offset, rn not updated */
181
- postindex = false;
182
- break;
183
- case 3: /* pre-index */
184
- postindex = false;
185
- wback = true;
186
- break;
187
- }
188
-
189
- if (is_vector && !fp_access_check(s)) {
190
- return;
191
- }
192
-
193
- offset <<= (set_tag ? LOG2_TAG_GRANULE : size);
194
-
195
- if (rn == 31) {
196
+ if (a->rn == 31) {
197
gen_check_sp_alignment(s);
198
}
199
200
- dirty_addr = read_cpu_reg_sp(s, rn, 1);
201
- if (!postindex) {
202
+ *dirty_addr = read_cpu_reg_sp(s, a->rn, 1);
203
+ if (!a->p) {
204
+ tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset);
205
+ }
206
+
207
+ *clean_addr = gen_mte_checkN(s, *dirty_addr, is_store,
208
+ (a->w || a->rn != 31), 2 << a->sz, mop);
209
+}
210
+
211
+static void op_addr_ldstpair_post(DisasContext *s, arg_ldstpair *a,
212
+ TCGv_i64 dirty_addr, uint64_t offset)
213
+{
214
+ if (a->w) {
215
+ if (a->p) {
216
+ tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
217
+ }
218
+ tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr);
219
+ }
220
+}
221
+
222
+static bool trans_STP(DisasContext *s, arg_ldstpair *a)
223
+{
224
+ uint64_t offset = a->imm << a->sz;
225
+ TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2;
226
+ MemOp mop = finalize_memop(s, a->sz);
227
+
228
+ op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop);
229
+ tcg_rt = cpu_reg(s, a->rt);
230
+ tcg_rt2 = cpu_reg(s, a->rt2);
32
+ /*
231
+ /*
33
+ * Flags: If EL3 but not EL2...
232
+ * We built mop above for the single logical access -- rebuild it
34
+ * - UNDEF: discard the cpreg,
233
+ * now for the paired operation.
35
+ * - KEEP: retain the cpreg as is,
234
+ *
36
+ * - C_NZ: set const on the cpreg, but retain resetvalue,
235
+ * With LSE2, non-sign-extending pairs are treated atomically if
37
+ * - else: set const on the cpreg, zero resetvalue, aka RES0.
236
+ * aligned, and if unaligned one of the pair will be completely
38
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
237
+ * within a 16-byte block and that element will be atomic.
238
+ * Otherwise each element is separately atomic.
239
+ * In all cases, issue one operation with the correct atomicity.
39
+ */
240
+ */
40
+ ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16,
241
+ mop = a->sz + 1;
41
+ ARM_CP_EL3_NO_EL2_KEEP = 1 << 17,
242
+ if (s->align_mem) {
42
+ ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18,
243
+ mop |= (a->sz == 2 ? MO_ALIGN_4 : MO_ALIGN_8);
43
};
244
+ }
44
245
+ mop = finalize_memop_pair(s, mop);
45
/*
246
+ if (a->sz == 2) {
46
diff --git a/target/arm/helper.c b/target/arm/helper.c
247
+ TCGv_i64 tmp = tcg_temp_new_i64();
47
index XXXXXXX..XXXXXXX 100644
248
+
48
--- a/target/arm/helper.c
249
+ if (s->be_data == MO_LE) {
49
+++ b/target/arm/helper.c
250
+ tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2);
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
251
+ } else {
51
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
252
+ tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt);
52
{ .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
253
+ }
53
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
254
+ tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop);
54
- .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
255
+ } else {
55
+ .access = PL2_RW,
256
+ TCGv_i128 tmp = tcg_temp_new_i128();
56
+ .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
257
+
57
.fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
258
+ if (s->be_data == MO_LE) {
58
{ .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
259
+ tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2);
59
.opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
260
+ } else {
60
- .access = PL2_RW, .resetvalue = 0,
261
+ tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt);
61
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
262
+ }
62
.writefn = dacr_write, .raw_writefn = raw_write,
263
+ tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop);
63
.fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
264
+ }
64
{ .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
265
+ op_addr_ldstpair_post(s, a, dirty_addr, offset);
65
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
266
+ return true;
66
- .access = PL2_RW, .resetvalue = 0,
267
+}
67
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
268
+
68
.fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
269
+static bool trans_LDP(DisasContext *s, arg_ldstpair *a)
69
{ .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
270
+{
70
.type = ARM_CP_ALIAS,
271
+ uint64_t offset = a->imm << a->sz;
71
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
272
+ TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2;
72
.writefn = tlbimva_hyp_is_write },
273
+ MemOp mop = finalize_memop(s, a->sz);
73
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
274
+
74
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
275
+ op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false, mop);
75
- .type = ARM_CP_NO_RAW, .access = PL2_W,
276
+ tcg_rt = cpu_reg(s, a->rt);
76
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
277
+ tcg_rt2 = cpu_reg(s, a->rt2);
77
.writefn = tlbi_aa64_alle2_write },
278
+
78
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
79
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
80
- .type = ARM_CP_NO_RAW, .access = PL2_W,
81
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
82
.writefn = tlbi_aa64_vae2_write },
83
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
84
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
85
- .access = PL2_W, .type = ARM_CP_NO_RAW,
86
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
87
.writefn = tlbi_aa64_vae2_write },
88
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
89
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
90
- .access = PL2_W, .type = ARM_CP_NO_RAW,
91
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
92
.writefn = tlbi_aa64_alle2is_write },
93
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
94
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
95
- .type = ARM_CP_NO_RAW, .access = PL2_W,
96
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
97
.writefn = tlbi_aa64_vae2is_write },
98
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
99
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
100
- .access = PL2_W, .type = ARM_CP_NO_RAW,
101
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
102
.writefn = tlbi_aa64_vae2is_write },
103
#ifndef CONFIG_USER_ONLY
104
/* Unlike the other EL2-related AT operations, these must
105
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
106
{ .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
107
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
108
.access = PL2_W, .accessfn = at_s1e2_access,
109
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
110
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
111
+ .writefn = ats_write64 },
112
{ .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
113
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
114
.access = PL2_W, .accessfn = at_s1e2_access,
115
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
116
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
117
+ .writefn = ats_write64 },
118
/* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
119
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
120
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
121
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
122
{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
123
.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
124
.access = PL2_RW, .accessfn = access_tda,
125
- .type = ARM_CP_NOP },
126
+ .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
127
/* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
128
* Channel but Linux may try to access this register. The 32-bit
129
* alias is DBGDCCINT.
130
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
131
.access = PL2_W, .type = ARM_CP_NOP },
132
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
134
- .access = PL2_W, .type = ARM_CP_NO_RAW,
135
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
136
.writefn = tlbi_aa64_rvae2is_write },
137
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
138
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
139
- .access = PL2_W, .type = ARM_CP_NO_RAW,
140
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
141
.writefn = tlbi_aa64_rvae2is_write },
142
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
143
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
145
.access = PL2_W, .type = ARM_CP_NOP },
146
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
147
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
148
- .access = PL2_W, .type = ARM_CP_NO_RAW,
149
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
150
.writefn = tlbi_aa64_rvae2is_write },
151
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
152
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
153
- .access = PL2_W, .type = ARM_CP_NO_RAW,
154
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
155
.writefn = tlbi_aa64_rvae2is_write },
156
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
157
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
158
- .access = PL2_W, .type = ARM_CP_NO_RAW,
159
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
160
.writefn = tlbi_aa64_rvae2_write },
161
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
162
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
163
- .access = PL2_W, .type = ARM_CP_NO_RAW,
164
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
165
.writefn = tlbi_aa64_rvae2_write },
166
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
167
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
168
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
169
.writefn = tlbi_aa64_vae1is_write },
170
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
172
- .access = PL2_W, .type = ARM_CP_NO_RAW,
173
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
174
.writefn = tlbi_aa64_alle2is_write },
175
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
176
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
177
- .access = PL2_W, .type = ARM_CP_NO_RAW,
178
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
179
.writefn = tlbi_aa64_vae2is_write },
180
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
181
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
182
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
183
.writefn = tlbi_aa64_alle1is_write },
184
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
185
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
186
- .access = PL2_W, .type = ARM_CP_NO_RAW,
187
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
188
.writefn = tlbi_aa64_vae2is_write },
189
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
190
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
191
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
192
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
193
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
194
.access = PL2_RW, .accessfn = access_el3_aa32ns,
195
- .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
196
+ .resetvalue = cpu->midr,
197
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
198
.fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
199
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
200
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
201
.access = PL2_RW, .resetvalue = cpu->midr,
202
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
203
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
204
{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
205
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
206
.access = PL2_RW, .accessfn = access_el3_aa32ns,
207
- .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
208
+ .resetvalue = vmpidr_def,
209
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
210
.fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
211
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
212
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
213
- .access = PL2_RW,
214
- .resetvalue = vmpidr_def,
215
+ .access = PL2_RW, .resetvalue = vmpidr_def,
216
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
217
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
218
};
219
define_arm_cp_regs(cpu, vpidr_regs);
220
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
221
int crm, int opc1, int opc2,
222
const char *name)
223
{
224
+ CPUARMState *env = &cpu->env;
225
uint32_t key;
226
ARMCPRegInfo *r2;
227
bool is64 = r->type & ARM_CP_64BIT;
228
bool ns = secstate & ARM_CP_SECSTATE_NS;
229
int cp = r->cp;
230
- bool isbanked;
231
size_t name_len;
232
+ bool make_const;
233
234
switch (state) {
235
case ARM_CP_STATE_AA32:
236
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
237
}
238
}
239
240
+ /*
279
+ /*
241
+ * Eliminate registers that are not present because the EL is missing.
280
+ * We built mop above for the single logical access -- rebuild it
242
+ * Doing this here makes it easier to put all registers for a given
281
+ * now for the paired operation.
243
+ * feature into the same ARMCPRegInfo array and define them all at once.
282
+ *
283
+ * With LSE2, non-sign-extending pairs are treated atomically if
284
+ * aligned, and if unaligned one of the pair will be completely
285
+ * within a 16-byte block and that element will be atomic.
286
+ * Otherwise each element is separately atomic.
287
+ * In all cases, issue one operation with the correct atomicity.
288
+ *
289
+ * This treats sign-extending loads like zero-extending loads,
290
+ * since that reuses the most code below.
244
+ */
291
+ */
245
+ make_const = false;
292
+ mop = a->sz + 1;
246
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
293
+ if (s->align_mem) {
247
+ /*
294
+ mop |= (a->sz == 2 ? MO_ALIGN_4 : MO_ALIGN_8);
248
+ * An EL2 register without EL2 but with EL3 is (usually) RES0.
295
+ }
249
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
296
+ mop = finalize_memop_pair(s, mop);
250
+ */
297
+ if (a->sz == 2) {
251
+ int min_el = ctz32(r->access) / 2;
298
+ int o2 = s->be_data == MO_LE ? 32 : 0;
252
+ if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
299
+ int o1 = o2 ^ 32;
253
+ if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
300
+
254
+ return;
301
+ tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), mop);
255
+ }
302
+ if (a->sign) {
256
+ make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
303
+ tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32);
304
+ tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32);
305
+ } else {
306
+ tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32);
307
+ tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32);
257
+ }
308
+ }
258
+ } else {
309
+ } else {
259
+ CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
310
+ TCGv_i128 tmp = tcg_temp_new_i128();
260
+ ? PL2_RW : PL1_RW);
311
+
261
+ if ((r->access & max_el) == 0) {
312
+ tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mop);
262
+ return;
313
+ if (s->be_data == MO_LE) {
314
+ tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp);
315
+ } else {
316
+ tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp);
263
+ }
317
+ }
264
+ }
318
+ }
265
+
319
+ op_addr_ldstpair_post(s, a, dirty_addr, offset);
266
/* Combine cpreg and name into one allocation. */
320
+ return true;
267
name_len = strlen(name) + 1;
321
+}
268
r2 = g_malloc(sizeof(*r2) + name_len);
322
+
269
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
323
+static bool trans_STP_v(DisasContext *s, arg_ldstpair *a)
270
r2->opaque = opaque;
324
+{
325
+ uint64_t offset = a->imm << a->sz;
326
+ TCGv_i64 clean_addr, dirty_addr;
327
+ MemOp mop;
328
+
329
+ if (!fp_access_check(s)) {
330
+ return true;
331
+ }
332
+
333
+ /* LSE2 does not merge FP pairs; leave these as separate operations. */
334
+ mop = finalize_memop_asimd(s, a->sz);
335
+ op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop);
336
+ do_fp_st(s, a->rt, clean_addr, mop);
337
+ tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz);
338
+ do_fp_st(s, a->rt2, clean_addr, mop);
339
+ op_addr_ldstpair_post(s, a, dirty_addr, offset);
340
+ return true;
341
+}
342
+
343
+static bool trans_LDP_v(DisasContext *s, arg_ldstpair *a)
344
+{
345
+ uint64_t offset = a->imm << a->sz;
346
+ TCGv_i64 clean_addr, dirty_addr;
347
+ MemOp mop;
348
+
349
+ if (!fp_access_check(s)) {
350
+ return true;
351
+ }
352
+
353
+ /* LSE2 does not merge FP pairs; leave these as separate operations. */
354
+ mop = finalize_memop_asimd(s, a->sz);
355
+ op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false, mop);
356
+ do_fp_ld(s, a->rt, clean_addr, mop);
357
+ tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz);
358
+ do_fp_ld(s, a->rt2, clean_addr, mop);
359
+ op_addr_ldstpair_post(s, a, dirty_addr, offset);
360
+ return true;
361
+}
362
+
363
+static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
364
+{
365
+ TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2;
366
+ uint64_t offset = a->imm << LOG2_TAG_GRANULE;
367
+ MemOp mop;
368
+ TCGv_i128 tmp;
369
+
370
+ if (!dc_isar_feature(aa64_mte_insn_reg, s)) {
371
+ return false;
372
+ }
373
+
374
+ if (a->rn == 31) {
375
+ gen_check_sp_alignment(s);
376
+ }
377
+
378
+ dirty_addr = read_cpu_reg_sp(s, a->rn, 1);
379
+ if (!a->p) {
380
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
271
}
381
}
272
382
273
- isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
383
- if (set_tag) {
274
- if (isbanked) {
384
- if (!s->ata) {
275
+ if (make_const) {
385
- /*
276
+ /* This should not have been a very special register to begin. */
386
- * TODO: We could rely on the stores below, at least for
277
+ int old_special = r2->type & ARM_CP_SPECIAL_MASK;
387
- * system mode, if we arrange to add MO_ALIGN_16.
278
+ assert(old_special == 0 || old_special == ARM_CP_NOP);
388
- */
389
- gen_helper_stg_stub(cpu_env, dirty_addr);
390
- } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
391
- gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
392
- } else {
393
- gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
394
- }
395
- }
396
-
397
- if (is_vector) {
398
- mop = finalize_memop_asimd(s, size);
399
- } else {
400
- mop = finalize_memop(s, size);
401
- }
402
- clean_addr = gen_mte_checkN(s, dirty_addr, !is_load,
403
- (wback || rn != 31) && !set_tag,
404
- 2 << size, mop);
405
-
406
- if (is_vector) {
407
- /* LSE2 does not merge FP pairs; leave these as separate operations. */
408
- if (is_load) {
409
- do_fp_ld(s, rt, clean_addr, mop);
410
- } else {
411
- do_fp_st(s, rt, clean_addr, mop);
412
- }
413
- tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size);
414
- if (is_load) {
415
- do_fp_ld(s, rt2, clean_addr, mop);
416
- } else {
417
- do_fp_st(s, rt2, clean_addr, mop);
418
- }
419
- } else {
420
- TCGv_i64 tcg_rt = cpu_reg(s, rt);
421
- TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
422
-
423
+ if (!s->ata) {
279
/*
424
/*
280
- * Register is banked (using both entries in array).
425
- * We built mop above for the single logical access -- rebuild it
281
- * Overwriting fieldoffset as the array is only used to define
426
- * now for the paired operation.
282
- * banked registers but later only fieldoffset is used.
427
- *
283
+ * Set the special function to CONST, retaining the other flags.
428
- * With LSE2, non-sign-extending pairs are treated atomically if
284
+ * This is important for e.g. ARM_CP_SVE so that we still
429
- * aligned, and if unaligned one of the pair will be completely
285
+ * take the SVE trap if CPTR_EL3.EZ == 0.
430
- * within a 16-byte block and that element will be atomic.
431
- * Otherwise each element is separately atomic.
432
- * In all cases, issue one operation with the correct atomicity.
433
- *
434
- * This treats sign-extending loads like zero-extending loads,
435
- * since that reuses the most code below.
436
+ * TODO: We could rely on the stores below, at least for
437
+ * system mode, if we arrange to add MO_ALIGN_16.
286
*/
438
*/
287
- r2->fieldoffset = r->bank_fieldoffsets[ns];
439
- mop = size + 1;
288
- }
440
- if (s->align_mem) {
289
+ r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
441
- mop |= (size == 2 ? MO_ALIGN_4 : MO_ALIGN_8);
290
+ /*
442
- }
291
+ * Usually, these registers become RES0, but there are a few
443
- mop = finalize_memop_pair(s, mop);
292
+ * special cases like VPIDR_EL2 which have a constant non-zero
444
-
293
+ * value with writes ignored.
445
- if (is_load) {
294
+ */
446
- if (size == 2) {
295
+ if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
447
- int o2 = s->be_data == MO_LE ? 32 : 0;
296
+ r2->resetvalue = 0;
448
- int o1 = o2 ^ 32;
297
+ }
449
-
298
+ /*
450
- tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), mop);
299
+ * ARM_CP_CONST has precedence, so removing the callbacks and
451
- if (is_signed) {
300
+ * offsets are not strictly necessary, but it is potentially
452
- tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32);
301
+ * less confusing to debug later.
453
- tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32);
302
+ */
454
- } else {
303
+ r2->readfn = NULL;
455
- tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32);
304
+ r2->writefn = NULL;
456
- tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32);
305
+ r2->raw_readfn = NULL;
457
- }
306
+ r2->raw_writefn = NULL;
458
- } else {
307
+ r2->resetfn = NULL;
459
- TCGv_i128 tmp = tcg_temp_new_i128();
308
+ r2->fieldoffset = 0;
460
-
309
+ r2->bank_fieldoffsets[0] = 0;
461
- tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mop);
310
+ r2->bank_fieldoffsets[1] = 0;
462
- if (s->be_data == MO_LE) {
463
- tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp);
464
- } else {
465
- tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp);
466
- }
467
- }
468
- } else {
469
- if (size == 2) {
470
- TCGv_i64 tmp = tcg_temp_new_i64();
471
-
472
- if (s->be_data == MO_LE) {
473
- tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2);
474
- } else {
475
- tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt);
476
- }
477
- tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop);
478
- } else {
479
- TCGv_i128 tmp = tcg_temp_new_i128();
480
-
481
- if (s->be_data == MO_LE) {
482
- tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2);
483
- } else {
484
- tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt);
485
- }
486
- tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop);
487
- }
488
- }
489
+ gen_helper_stg_stub(cpu_env, dirty_addr);
490
+ } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
491
+ gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
311
+ } else {
492
+ } else {
312
+ bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
493
+ gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
313
314
- if (state == ARM_CP_STATE_AA32) {
315
if (isbanked) {
316
/*
317
- * If the register is banked then we don't need to migrate or
318
- * reset the 32-bit instance in certain cases:
319
- *
320
- * 1) If the register has both 32-bit and 64-bit instances then we
321
- * can count on the 64-bit instance taking care of the
322
- * non-secure bank.
323
- * 2) If ARMv8 is enabled then we can count on a 64-bit version
324
- * taking care of the secure bank. This requires that separate
325
- * 32 and 64-bit definitions are provided.
326
+ * Register is banked (using both entries in array).
327
+ * Overwriting fieldoffset as the array is only used to define
328
+ * banked registers but later only fieldoffset is used.
329
*/
330
- if ((r->state == ARM_CP_STATE_BOTH && ns) ||
331
- (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
332
+ r2->fieldoffset = r->bank_fieldoffsets[ns];
333
+ }
334
+ if (state == ARM_CP_STATE_AA32) {
335
+ if (isbanked) {
336
+ /*
337
+ * If the register is banked then we don't need to migrate or
338
+ * reset the 32-bit instance in certain cases:
339
+ *
340
+ * 1) If the register has both 32-bit and 64-bit instances
341
+ * then we can count on the 64-bit instance taking care
342
+ * of the non-secure bank.
343
+ * 2) If ARMv8 is enabled then we can count on a 64-bit
344
+ * version taking care of the secure bank. This requires
345
+ * that separate 32 and 64-bit definitions are provided.
346
+ */
347
+ if ((r->state == ARM_CP_STATE_BOTH && ns) ||
348
+ (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
349
+ r2->type |= ARM_CP_ALIAS;
350
+ }
351
+ } else if ((secstate != r->secure) && !ns) {
352
+ /*
353
+ * The register is not banked so we only want to allow
354
+ * migration of the non-secure instance.
355
+ */
356
r2->type |= ARM_CP_ALIAS;
357
}
358
- } else if ((secstate != r->secure) && !ns) {
359
- /*
360
- * The register is not banked so we only want to allow migration
361
- * of the non-secure instance.
362
- */
363
- r2->type |= ARM_CP_ALIAS;
364
- }
365
366
- if (HOST_BIG_ENDIAN &&
367
- r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
368
- r2->fieldoffset += sizeof(uint32_t);
369
+ if (HOST_BIG_ENDIAN &&
370
+ r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
371
+ r2->fieldoffset += sizeof(uint32_t);
372
+ }
373
}
374
}
494
}
375
495
376
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
496
- if (wback) {
377
* multiple times. Special registers (ie NOP/WFI) are
497
- if (postindex) {
378
* never migratable and not even raw-accessible.
498
- tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
379
*/
499
- }
380
- if (r->type & ARM_CP_SPECIAL_MASK) {
500
- tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr);
381
+ if (r2->type & ARM_CP_SPECIAL_MASK) {
501
+ mop = finalize_memop(s, a->sz);
382
r2->type |= ARM_CP_NO_RAW;
502
+ clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << a->sz, mop);
503
+
504
+ tcg_rt = cpu_reg(s, a->rt);
505
+ tcg_rt2 = cpu_reg(s, a->rt2);
506
+
507
+ assert(a->sz == 3);
508
+
509
+ tmp = tcg_temp_new_i128();
510
+ if (s->be_data == MO_LE) {
511
+ tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2);
512
+ } else {
513
+ tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt);
383
}
514
}
384
if (((r->crm == CP_ANY) && crm != 0) ||
515
+ tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop);
516
+
517
+ op_addr_ldstpair_post(s, a, dirty_addr, offset);
518
+ return true;
519
}
520
521
/*
522
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
523
static void disas_ldst(DisasContext *s, uint32_t insn)
524
{
525
switch (extract32(insn, 24, 6)) {
526
- case 0x28: case 0x29:
527
- case 0x2c: case 0x2d: /* Load/store pair (all forms) */
528
- disas_ldst_pair(s, insn);
529
- break;
530
case 0x38: case 0x39:
531
case 0x3c: case 0x3d: /* Load/store register (all forms) */
532
disas_ldst_reg(s, insn);
385
--
533
--
386
2.25.1
534
2.34.1
diff view generated by jsdifflib
[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
[PULL 15/33] target/arm: Convert ld/st reg+imm9 insns to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the load and store instructions which use a 9-bit
2
immediate offset to decodetree.
2
3
3
This register is present for either VHE or Debugv8p2.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230602155223.2040685-13-peter.maydell@linaro.org
7
---
8
target/arm/tcg/a64.decode | 69 +++++++++++
9
target/arm/tcg/translate-a64.c | 206 ++++++++++++++-------------------
10
2 files changed, 153 insertions(+), 122 deletions(-)
4
11
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 15 +++++++++++----
11
1 file changed, 11 insertions(+), 4 deletions(-)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
14
--- a/target/arm/tcg/a64.decode
16
+++ b/target/arm/helper.c
15
+++ b/target/arm/tcg/a64.decode
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
16
@@ -XXX,XX +XXX,XX @@ LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p
18
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
17
STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
19
};
18
STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
20
19
STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
21
+static const ARMCPRegInfo contextidr_el2 = {
20
+
22
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
21
+# Load/store register (unscaled immediate)
23
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
22
+&ldst_imm rt rn imm sz sign w p unpriv ext
24
+ .access = PL2_RW,
23
+@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0
25
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
24
+@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1
26
+};
25
+@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1
27
+
26
+@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0
28
static const ARMCPRegInfo vhe_reginfo[] = {
27
+
29
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
28
+STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
30
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
29
+LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0
31
- .access = PL2_RW,
30
+LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1
32
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
31
+LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2
33
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
32
+LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3
34
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
33
+LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0
35
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
34
+LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1
36
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
35
+LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2
37
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
36
+LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0
37
+LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1
38
+
39
+STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
40
+LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0
41
+LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1
42
+LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2
43
+LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3
44
+LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0
45
+LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1
46
+LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2
47
+LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0
48
+LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1
49
+
50
+STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0
51
+LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0
52
+LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1
53
+LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2
54
+LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3
55
+LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0
56
+LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1
57
+LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2
58
+LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0
59
+LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1
60
+
61
+STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
62
+LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0
63
+LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1
64
+LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2
65
+LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3
66
+LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0
67
+LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1
68
+LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2
69
+LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0
70
+LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1
71
+
72
+# PRFM : prefetch memory: a no-op for QEMU
73
+NOP 11 111 0 00 10 0 --------- 00 ----- -----
74
+
75
+STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
76
+STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
77
+LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
78
+LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
79
+
80
+STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
81
+STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
82
+LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
83
+LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
84
+
85
+STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
86
+STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
87
+LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
88
+LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
89
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/tcg/translate-a64.c
92
+++ b/target/arm/tcg/translate-a64.c
93
@@ -XXX,XX +XXX,XX @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
94
return true;
95
}
96
97
-/*
98
- * Load/store (immediate post-indexed)
99
- * Load/store (immediate pre-indexed)
100
- * Load/store (unscaled immediate)
101
- *
102
- * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
103
- * +----+-------+---+-----+-----+---+--------+-----+------+------+
104
- * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
105
- * +----+-------+---+-----+-----+---+--------+-----+------+------+
106
- *
107
- * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
108
- 10 -> unprivileged
109
- * V = 0 -> non-vector
110
- * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
111
- * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
112
- */
113
-static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
114
- int opc,
115
- int size,
116
- int rt,
117
- bool is_vector)
118
+static void op_addr_ldst_imm_pre(DisasContext *s, arg_ldst_imm *a,
119
+ TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr,
120
+ uint64_t offset, bool is_store, MemOp mop)
121
{
122
- int rn = extract32(insn, 5, 5);
123
- int imm9 = sextract32(insn, 12, 9);
124
- int idx = extract32(insn, 10, 2);
125
- bool is_signed = false;
126
- bool is_store = false;
127
- bool is_extended = false;
128
- bool is_unpriv = (idx == 2);
129
- bool iss_valid;
130
- bool post_index;
131
- bool writeback;
132
int memidx;
133
- MemOp memop;
134
- TCGv_i64 clean_addr, dirty_addr;
135
136
- if (is_vector) {
137
- size |= (opc & 2) << 1;
138
- if (size > 4 || is_unpriv) {
139
- unallocated_encoding(s);
140
- return;
141
- }
142
- is_store = ((opc & 1) == 0);
143
- if (!fp_access_check(s)) {
144
- return;
145
- }
146
- memop = finalize_memop_asimd(s, size);
147
- } else {
148
- if (size == 3 && opc == 2) {
149
- /* PRFM - prefetch */
150
- if (idx != 0) {
151
- unallocated_encoding(s);
152
- return;
153
- }
154
- return;
155
- }
156
- if (opc == 3 && size > 1) {
157
- unallocated_encoding(s);
158
- return;
159
- }
160
- is_store = (opc == 0);
161
- is_signed = !is_store && extract32(opc, 1, 1);
162
- is_extended = (size < 3) && extract32(opc, 0, 1);
163
- memop = finalize_memop(s, size + is_signed * MO_SIGN);
164
- }
165
-
166
- switch (idx) {
167
- case 0:
168
- case 2:
169
- post_index = false;
170
- writeback = false;
171
- break;
172
- case 1:
173
- post_index = true;
174
- writeback = true;
175
- break;
176
- case 3:
177
- post_index = false;
178
- writeback = true;
179
- break;
180
- default:
181
- g_assert_not_reached();
182
- }
183
-
184
- iss_valid = !is_vector && !writeback;
185
-
186
- if (rn == 31) {
187
+ if (a->rn == 31) {
188
gen_check_sp_alignment(s);
38
}
189
}
39
190
40
+ if (cpu_isar_feature(aa64_vh, cpu) ||
191
- dirty_addr = read_cpu_reg_sp(s, rn, 1);
41
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
192
- if (!post_index) {
42
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
193
- tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9);
194
+ *dirty_addr = read_cpu_reg_sp(s, a->rn, 1);
195
+ if (!a->p) {
196
+ tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset);
197
}
198
+ memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
199
+ *clean_addr = gen_mte_check1_mmuidx(s, *dirty_addr, is_store,
200
+ a->w || a->rn != 31,
201
+ mop, a->unpriv, memidx);
202
+}
203
204
- memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
205
-
206
- clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store,
207
- writeback || rn != 31,
208
- memop, is_unpriv, memidx);
209
-
210
- if (is_vector) {
211
- if (is_store) {
212
- do_fp_st(s, rt, clean_addr, memop);
213
- } else {
214
- do_fp_ld(s, rt, clean_addr, memop);
215
- }
216
- } else {
217
- TCGv_i64 tcg_rt = cpu_reg(s, rt);
218
- bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
219
-
220
- if (is_store) {
221
- do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx,
222
- iss_valid, rt, iss_sf, false);
223
- } else {
224
- do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop,
225
- is_extended, memidx,
226
- iss_valid, rt, iss_sf, false);
227
+static void op_addr_ldst_imm_post(DisasContext *s, arg_ldst_imm *a,
228
+ TCGv_i64 dirty_addr, uint64_t offset)
229
+{
230
+ if (a->w) {
231
+ if (a->p) {
232
+ tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
233
}
234
+ tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr);
235
}
236
+}
237
238
- if (writeback) {
239
- TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
240
- if (post_index) {
241
- tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9);
242
- }
243
- tcg_gen_mov_i64(tcg_rn, dirty_addr);
244
+static bool trans_STR_i(DisasContext *s, arg_ldst_imm *a)
245
+{
246
+ bool iss_sf, iss_valid = !a->w;
247
+ TCGv_i64 clean_addr, dirty_addr, tcg_rt;
248
+ int memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
249
+ MemOp mop = finalize_memop(s, a->sz + a->sign * MO_SIGN);
250
+
251
+ op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop);
252
+
253
+ tcg_rt = cpu_reg(s, a->rt);
254
+ iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext);
255
+
256
+ do_gpr_st_memidx(s, tcg_rt, clean_addr, mop, memidx,
257
+ iss_valid, a->rt, iss_sf, false);
258
+ op_addr_ldst_imm_post(s, a, dirty_addr, a->imm);
259
+ return true;
260
+}
261
+
262
+static bool trans_LDR_i(DisasContext *s, arg_ldst_imm *a)
263
+{
264
+ bool iss_sf, iss_valid = !a->w;
265
+ TCGv_i64 clean_addr, dirty_addr, tcg_rt;
266
+ int memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
267
+ MemOp mop = finalize_memop(s, a->sz + a->sign * MO_SIGN);
268
+
269
+ op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mop);
270
+
271
+ tcg_rt = cpu_reg(s, a->rt);
272
+ iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext);
273
+
274
+ do_gpr_ld_memidx(s, tcg_rt, clean_addr, mop,
275
+ a->ext, memidx, iss_valid, a->rt, iss_sf, false);
276
+ op_addr_ldst_imm_post(s, a, dirty_addr, a->imm);
277
+ return true;
278
+}
279
+
280
+static bool trans_STR_v_i(DisasContext *s, arg_ldst_imm *a)
281
+{
282
+ TCGv_i64 clean_addr, dirty_addr;
283
+ MemOp mop;
284
+
285
+ if (!fp_access_check(s)) {
286
+ return true;
287
}
288
+ mop = finalize_memop_asimd(s, a->sz);
289
+ op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop);
290
+ do_fp_st(s, a->rt, clean_addr, mop);
291
+ op_addr_ldst_imm_post(s, a, dirty_addr, a->imm);
292
+ return true;
293
+}
294
+
295
+static bool trans_LDR_v_i(DisasContext *s, arg_ldst_imm *a)
296
+{
297
+ TCGv_i64 clean_addr, dirty_addr;
298
+ MemOp mop;
299
+
300
+ if (!fp_access_check(s)) {
301
+ return true;
43
+ }
302
+ }
44
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
303
+ mop = finalize_memop_asimd(s, a->sz);
45
define_arm_cp_regs(cpu, vhe_reginfo);
304
+ op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mop);
46
}
305
+ do_fp_ld(s, a->rt, clean_addr, mop);
306
+ op_addr_ldst_imm_post(s, a, dirty_addr, a->imm);
307
+ return true;
308
}
309
310
/*
311
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
312
switch (extract32(insn, 24, 2)) {
313
case 0:
314
if (extract32(insn, 21, 1) == 0) {
315
- /* Load/store register (unscaled immediate)
316
- * Load/store immediate pre/post-indexed
317
- * Load/store register unprivileged
318
- */
319
- disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector);
320
- return;
321
+ break;
322
}
323
switch (extract32(insn, 10, 2)) {
324
case 0:
47
--
325
--
48
2.25.1
326
2.34.1
diff view generated by jsdifflib
[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
[PULL 16/33] target/arm: Convert LDR/STR with 12-bit immediate to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the LDR and STR instructions which use a 12-bit immediate
2
offset to decodetree. We can reuse the existing LDR and STR
3
trans functions for these.
2
4
3
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
is CONTEXTIDR_EL2, which is also conditionally implemented
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
with FEAT_VHE. The rest of the debug extension concerns the
7
Message-id: 20230602155223.2040685-14-peter.maydell@linaro.org
6
External debug interface, which is outside the scope of QEMU.
8
---
9
target/arm/tcg/a64.decode | 25 ++++++++
10
target/arm/tcg/translate-a64.c | 104 +++++----------------------------
11
2 files changed, 41 insertions(+), 88 deletions(-)
7
12
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/system/arm/emulation.rst | 1 +
14
target/arm/cpu.c | 1 +
15
target/arm/cpu64.c | 1 +
16
target/arm/cpu_tcg.c | 2 ++
17
4 files changed, 5 insertions(+)
18
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
15
--- a/target/arm/tcg/a64.decode
22
+++ b/docs/system/arm/emulation.rst
16
+++ b/target/arm/tcg/a64.decode
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
17
@@ -XXX,XX +XXX,XX @@ STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0
24
- FEAT_BTI (Branch Target Identification)
18
STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
25
- FEAT_DIT (Data Independent Timing instructions)
19
LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
26
- FEAT_DPB (DC CVAP instruction)
20
LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
27
+- FEAT_Debugv8p2 (Debug changes for v8.2)
21
+
28
- FEAT_DotProd (Advanced SIMD dot product instructions)
22
+# Load/store with an unsigned 12 bit immediate, which is scaled by the
29
- FEAT_FCMA (Floating-point complex number instructions)
23
+# element size. The function gets the sz:imm and returns the scaled immediate.
30
- FEAT_FHM (Floating-point half-precision multiplication instructions)
24
+%uimm_scaled 10:12 sz:3 !function=uimm_scaled
31
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
25
+
26
+@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled
27
+
28
+STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
29
+LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0
30
+LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1
31
+LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2
32
+LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3
33
+LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0
34
+LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1
35
+LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2
36
+LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0
37
+LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1
38
+
39
+# PRFM
40
+NOP 11 111 0 01 10 ------------ ----- -----
41
+
42
+STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
43
+STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
44
+LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0
45
+LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
46
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
32
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu.c
48
--- a/target/arm/tcg/translate-a64.c
34
+++ b/target/arm/cpu.c
49
+++ b/target/arm/tcg/translate-a64.c
35
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
50
@@ -XXX,XX +XXX,XX @@ enum a64_shift_type {
36
* feature registers as well.
51
A64_SHIFT_TYPE_ROR = 3
37
*/
52
};
38
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
53
39
+ cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
54
+/*
40
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
55
+ * Helpers for extracting complex instruction fields
41
ID_AA64PFR0, EL3, 0);
56
+ */
57
+
58
+/*
59
+ * For load/store with an unsigned 12 bit immediate scaled by the element
60
+ * size. The input has the immediate field in bits [14:3] and the element
61
+ * size in [2:0].
62
+ */
63
+static int uimm_scaled(DisasContext *s, int x)
64
+{
65
+ unsigned imm = x >> 3;
66
+ unsigned scale = extract32(x, 0, 3);
67
+ return imm << scale;
68
+}
69
+
70
/*
71
* Include the generated decoders.
72
*/
73
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
42
}
74
}
43
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
75
}
44
index XXXXXXX..XXXXXXX 100644
76
45
--- a/target/arm/cpu64.c
77
-/*
46
+++ b/target/arm/cpu64.c
78
- * Load/store (unsigned immediate)
47
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
79
- *
48
cpu->isar.id_aa64zfr0 = t;
80
- * 31 30 29 27 26 25 24 23 22 21 10 9 5
49
81
- * +----+-------+---+-----+-----+------------+-------+------+
50
t = cpu->isar.id_aa64dfr0;
82
- * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
51
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
83
- * +----+-------+---+-----+-----+------------+-------+------+
52
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
84
- *
53
cpu->isar.id_aa64dfr0 = t;
85
- * For non-vector:
54
86
- * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
55
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
87
- * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
56
index XXXXXXX..XXXXXXX 100644
88
- * For vector:
57
--- a/target/arm/cpu_tcg.c
89
- * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
58
+++ b/target/arm/cpu_tcg.c
90
- * opc<0>: 0 -> store, 1 -> load
59
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
91
- * Rn: base address register (inc SP)
60
cpu->isar.id_pfr2 = t;
92
- * Rt: target register
61
93
- */
62
t = cpu->isar.id_dfr0;
94
-static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
63
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
95
- int opc,
64
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
96
- int size,
65
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
97
- int rt,
66
cpu->isar.id_dfr0 = t;
98
- bool is_vector)
99
-{
100
- int rn = extract32(insn, 5, 5);
101
- unsigned int imm12 = extract32(insn, 10, 12);
102
- unsigned int offset;
103
- TCGv_i64 clean_addr, dirty_addr;
104
- bool is_store;
105
- bool is_signed = false;
106
- bool is_extended = false;
107
- MemOp memop;
108
-
109
- if (is_vector) {
110
- size |= (opc & 2) << 1;
111
- if (size > 4) {
112
- unallocated_encoding(s);
113
- return;
114
- }
115
- is_store = !extract32(opc, 0, 1);
116
- if (!fp_access_check(s)) {
117
- return;
118
- }
119
- memop = finalize_memop_asimd(s, size);
120
- } else {
121
- if (size == 3 && opc == 2) {
122
- /* PRFM - prefetch */
123
- return;
124
- }
125
- if (opc == 3 && size > 1) {
126
- unallocated_encoding(s);
127
- return;
128
- }
129
- is_store = (opc == 0);
130
- is_signed = !is_store && extract32(opc, 1, 1);
131
- is_extended = (size < 3) && extract32(opc, 0, 1);
132
- memop = finalize_memop(s, size + is_signed * MO_SIGN);
133
- }
134
-
135
- if (rn == 31) {
136
- gen_check_sp_alignment(s);
137
- }
138
- dirty_addr = read_cpu_reg_sp(s, rn, 1);
139
- offset = imm12 << size;
140
- tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
141
-
142
- clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, memop);
143
-
144
- if (is_vector) {
145
- if (is_store) {
146
- do_fp_st(s, rt, clean_addr, memop);
147
- } else {
148
- do_fp_ld(s, rt, clean_addr, memop);
149
- }
150
- } else {
151
- TCGv_i64 tcg_rt = cpu_reg(s, rt);
152
- bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
153
- if (is_store) {
154
- do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, false);
155
- } else {
156
- do_gpr_ld(s, tcg_rt, clean_addr, memop,
157
- is_extended, true, rt, iss_sf, false);
158
- }
159
- }
160
-}
161
-
162
/* Atomic memory operations
163
*
164
* 31 30 27 26 24 22 21 16 15 12 10 5 0
165
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
166
return;
167
}
168
break;
169
- case 1:
170
- disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector);
171
- return;
172
}
173
unallocated_encoding(s);
67
}
174
}
68
--
175
--
69
2.25.1
176
2.34.1
diff view generated by jsdifflib
[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
[PULL 17/33] target/arm: Convert LDR/STR reg+reg to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the LDR and STR instructions which take a register
2
plus register offset to decodetree.
2
3
3
This extension concerns not merging memory access, which TCG does
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
not implement. Thus we can trivially enable this feature.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Add a comment to handle_hint for the DGH instruction, but no code.
6
Message-id: 20230602155223.2040685-15-peter.maydell@linaro.org
7
---
8
target/arm/tcg/a64.decode | 22 +++++
9
target/arm/tcg/translate-a64.c | 173 +++++++++++++++------------------
10
2 files changed, 103 insertions(+), 92 deletions(-)
6
11
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 1 +
13
target/arm/cpu64.c | 1 +
14
target/arm/translate-a64.c | 1 +
15
3 files changed, 3 insertions(+)
16
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/arm/emulation.rst
14
--- a/target/arm/tcg/a64.decode
20
+++ b/docs/system/arm/emulation.rst
15
+++ b/target/arm/tcg/a64.decode
21
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
@@ -XXX,XX +XXX,XX @@ STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
17
STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
18
LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0
24
- FEAT_CSV3 (Cache speculation variant 3)
19
LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
25
+- FEAT_DGH (Data gathering hint)
20
+
26
- FEAT_DIT (Data Independent Timing instructions)
21
+# Load/store with register offset
27
- FEAT_DPB (DC CVAP instruction)
22
+&ldst rm rn rt sign ext sz opt s
28
- FEAT_Debugv8p2 (Debug changes for v8.2)
23
+@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst
29
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
24
+STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
25
+LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0
26
+LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1
27
+LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2
28
+LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3
29
+LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0
30
+LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1
31
+LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2
32
+LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0
33
+LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1
34
+
35
+# PRFM
36
+NOP 11 111 0 00 10 1 ----- -1- - 10 ----- -----
37
+
38
+STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
39
+STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
40
+LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
41
+LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
42
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
30
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu64.c
44
--- a/target/arm/tcg/translate-a64.c
32
+++ b/target/arm/cpu64.c
45
+++ b/target/arm/tcg/translate-a64.c
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
46
@@ -XXX,XX +XXX,XX @@ static bool trans_LDR_v_i(DisasContext *s, arg_ldst_imm *a)
34
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
47
return true;
35
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
48
}
36
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
49
37
+ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
50
-/*
38
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
51
- * Load/store (register offset)
39
cpu->isar.id_aa64isar1 = t;
52
- *
40
53
- * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
41
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
54
- * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
42
index XXXXXXX..XXXXXXX 100644
55
- * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
43
--- a/target/arm/translate-a64.c
56
- * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
44
+++ b/target/arm/translate-a64.c
57
- *
45
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
58
- * For non-vector:
46
break;
59
- * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
47
case 0b00100: /* SEV */
60
- * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
48
case 0b00101: /* SEVL */
61
- * For vector:
49
+ case 0b00110: /* DGH */
62
- * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
50
/* we treat all as NOP at least for now */
63
- * opc<0>: 0 -> store, 1 -> load
51
break;
64
- * V: 1 -> vector/simd
52
case 0b00111: /* XPACLRI */
65
- * opt: extend encoding (see DecodeRegExtend)
66
- * S: if S=1 then scale (essentially index by sizeof(size))
67
- * Rt: register to transfer into/out of
68
- * Rn: address register or SP for base
69
- * Rm: offset register or ZR for offset
70
- */
71
-static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
72
- int opc,
73
- int size,
74
- int rt,
75
- bool is_vector)
76
+static void op_addr_ldst_pre(DisasContext *s, arg_ldst *a,
77
+ TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr,
78
+ bool is_store, MemOp memop)
79
{
80
- int rn = extract32(insn, 5, 5);
81
- int shift = extract32(insn, 12, 1);
82
- int rm = extract32(insn, 16, 5);
83
- int opt = extract32(insn, 13, 3);
84
- bool is_signed = false;
85
- bool is_store = false;
86
- bool is_extended = false;
87
- TCGv_i64 tcg_rm, clean_addr, dirty_addr;
88
- MemOp memop;
89
+ TCGv_i64 tcg_rm;
90
91
- if (extract32(opt, 1, 1) == 0) {
92
- unallocated_encoding(s);
93
- return;
94
- }
95
-
96
- if (is_vector) {
97
- size |= (opc & 2) << 1;
98
- if (size > 4) {
99
- unallocated_encoding(s);
100
- return;
101
- }
102
- is_store = !extract32(opc, 0, 1);
103
- if (!fp_access_check(s)) {
104
- return;
105
- }
106
- memop = finalize_memop_asimd(s, size);
107
- } else {
108
- if (size == 3 && opc == 2) {
109
- /* PRFM - prefetch */
110
- return;
111
- }
112
- if (opc == 3 && size > 1) {
113
- unallocated_encoding(s);
114
- return;
115
- }
116
- is_store = (opc == 0);
117
- is_signed = !is_store && extract32(opc, 1, 1);
118
- is_extended = (size < 3) && extract32(opc, 0, 1);
119
- memop = finalize_memop(s, size + is_signed * MO_SIGN);
120
- }
121
-
122
- if (rn == 31) {
123
+ if (a->rn == 31) {
124
gen_check_sp_alignment(s);
125
}
126
- dirty_addr = read_cpu_reg_sp(s, rn, 1);
127
+ *dirty_addr = read_cpu_reg_sp(s, a->rn, 1);
128
129
- tcg_rm = read_cpu_reg(s, rm, 1);
130
- ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
131
+ tcg_rm = read_cpu_reg(s, a->rm, 1);
132
+ ext_and_shift_reg(tcg_rm, tcg_rm, a->opt, a->s ? a->sz : 0);
133
134
- tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
135
+ tcg_gen_add_i64(*dirty_addr, *dirty_addr, tcg_rm);
136
+ *clean_addr = gen_mte_check1(s, *dirty_addr, is_store, true, memop);
137
+}
138
139
- clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, memop);
140
+static bool trans_LDR(DisasContext *s, arg_ldst *a)
141
+{
142
+ TCGv_i64 clean_addr, dirty_addr, tcg_rt;
143
+ bool iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext);
144
+ MemOp memop;
145
146
- if (is_vector) {
147
- if (is_store) {
148
- do_fp_st(s, rt, clean_addr, memop);
149
- } else {
150
- do_fp_ld(s, rt, clean_addr, memop);
151
- }
152
- } else {
153
- TCGv_i64 tcg_rt = cpu_reg(s, rt);
154
- bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
155
-
156
- if (is_store) {
157
- do_gpr_st(s, tcg_rt, clean_addr, memop,
158
- true, rt, iss_sf, false);
159
- } else {
160
- do_gpr_ld(s, tcg_rt, clean_addr, memop,
161
- is_extended, true, rt, iss_sf, false);
162
- }
163
+ if (extract32(a->opt, 1, 1) == 0) {
164
+ return false;
165
}
166
+
167
+ memop = finalize_memop(s, a->sz + a->sign * MO_SIGN);
168
+ op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false, memop);
169
+ tcg_rt = cpu_reg(s, a->rt);
170
+ do_gpr_ld(s, tcg_rt, clean_addr, memop,
171
+ a->ext, true, a->rt, iss_sf, false);
172
+ return true;
173
+}
174
+
175
+static bool trans_STR(DisasContext *s, arg_ldst *a)
176
+{
177
+ TCGv_i64 clean_addr, dirty_addr, tcg_rt;
178
+ bool iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext);
179
+ MemOp memop;
180
+
181
+ if (extract32(a->opt, 1, 1) == 0) {
182
+ return false;
183
+ }
184
+
185
+ memop = finalize_memop(s, a->sz);
186
+ op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true, memop);
187
+ tcg_rt = cpu_reg(s, a->rt);
188
+ do_gpr_st(s, tcg_rt, clean_addr, memop, true, a->rt, iss_sf, false);
189
+ return true;
190
+}
191
+
192
+static bool trans_LDR_v(DisasContext *s, arg_ldst *a)
193
+{
194
+ TCGv_i64 clean_addr, dirty_addr;
195
+ MemOp memop;
196
+
197
+ if (extract32(a->opt, 1, 1) == 0) {
198
+ return false;
199
+ }
200
+
201
+ if (!fp_access_check(s)) {
202
+ return true;
203
+ }
204
+
205
+ memop = finalize_memop_asimd(s, a->sz);
206
+ op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false, memop);
207
+ do_fp_ld(s, a->rt, clean_addr, memop);
208
+ return true;
209
+}
210
+
211
+static bool trans_STR_v(DisasContext *s, arg_ldst *a)
212
+{
213
+ TCGv_i64 clean_addr, dirty_addr;
214
+ MemOp memop;
215
+
216
+ if (extract32(a->opt, 1, 1) == 0) {
217
+ return false;
218
+ }
219
+
220
+ if (!fp_access_check(s)) {
221
+ return true;
222
+ }
223
+
224
+ memop = finalize_memop_asimd(s, a->sz);
225
+ op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true, memop);
226
+ do_fp_st(s, a->rt, clean_addr, memop);
227
+ return true;
228
}
229
230
/* Atomic memory operations
231
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
232
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
233
{
234
int rt = extract32(insn, 0, 5);
235
- int opc = extract32(insn, 22, 2);
236
bool is_vector = extract32(insn, 26, 1);
237
int size = extract32(insn, 30, 2);
238
239
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
240
disas_ldst_atomic(s, insn, size, rt, is_vector);
241
return;
242
case 2:
243
- disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector);
244
- return;
245
+ break;
246
default:
247
disas_ldst_pac(s, insn, size, rt, is_vector);
248
return;
53
--
249
--
54
2.25.1
250
2.34.1
diff view generated by jsdifflib
[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
[PULL 18/33] target/arm: Convert atomic memory ops to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the insns in the atomic memory operations group to
2
decodetree.
2
3
3
This extension concerns branch speculation, which TCG does
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
not implement. Thus we can trivially enable this feature.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230602155223.2040685-16-peter.maydell@linaro.org
7
---
8
target/arm/tcg/a64.decode | 15 ++++
9
target/arm/tcg/translate-a64.c | 153 ++++++++++++---------------------
10
2 files changed, 70 insertions(+), 98 deletions(-)
5
11
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/emulation.rst | 1 +
12
target/arm/cpu64.c | 1 +
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
15
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
14
--- a/target/arm/tcg/a64.decode
19
+++ b/docs/system/arm/emulation.rst
15
+++ b/target/arm/tcg/a64.decode
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
@@ -XXX,XX +XXX,XX @@ STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
21
- FEAT_BBM at level 2 (Translation table break-before-make levels)
17
STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
22
- FEAT_BF16 (AArch64 BFloat16 instructions)
18
LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
23
- FEAT_BTI (Branch Target Identification)
19
LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
24
+- FEAT_CSV2 (Cache speculation variant 2)
20
+
25
- FEAT_DIT (Data Independent Timing instructions)
21
+# Atomic memory operations
26
- FEAT_DPB (DC CVAP instruction)
22
+&atomic rs rn rt a r sz
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
23
+@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
24
+LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic
25
+LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic
26
+LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic
27
+LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic
28
+LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic
29
+LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic
30
+LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic
31
+LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic
32
+SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic
33
+
34
+LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
35
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu64.c
37
--- a/target/arm/tcg/translate-a64.c
31
+++ b/target/arm/cpu64.c
38
+++ b/target/arm/tcg/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
39
@@ -XXX,XX +XXX,XX @@ static bool trans_STR_v(DisasContext *s, arg_ldst *a)
33
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
40
return true;
34
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
41
}
35
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
42
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
43
-/* Atomic memory operations
37
cpu->isar.id_aa64pfr0 = t;
44
- *
38
45
- * 31 30 27 26 24 22 21 16 15 12 10 5 0
39
t = cpu->isar.id_aa64pfr1;
46
- * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
47
- * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
41
index XXXXXXX..XXXXXXX 100644
48
- * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
42
--- a/target/arm/cpu_tcg.c
49
- *
43
+++ b/target/arm/cpu_tcg.c
50
- * Rt: the result register
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
51
- * Rn: base address or SP
45
cpu->isar.id_mmfr4 = t;
52
- * Rs: the source register for the operation
46
53
- * V: vector flag (always 0 as of v8.3)
47
t = cpu->isar.id_pfr0;
54
- * A: acquire flag
48
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
55
- * R: release flag
49
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
56
- */
50
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
57
-static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
51
cpu->isar.id_pfr0 = t;
58
- int size, int rt, bool is_vector)
59
+
60
+static bool do_atomic_ld(DisasContext *s, arg_atomic *a, AtomicThreeOpFn *fn,
61
+ int sign, bool invert)
62
{
63
- int rs = extract32(insn, 16, 5);
64
- int rn = extract32(insn, 5, 5);
65
- int o3_opc = extract32(insn, 12, 4);
66
- bool r = extract32(insn, 22, 1);
67
- bool a = extract32(insn, 23, 1);
68
- TCGv_i64 tcg_rs, tcg_rt, clean_addr;
69
- AtomicThreeOpFn *fn = NULL;
70
- MemOp mop = size;
71
+ MemOp mop = a->sz | sign;
72
+ TCGv_i64 clean_addr, tcg_rs, tcg_rt;
73
74
- if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
75
- unallocated_encoding(s);
76
- return;
77
- }
78
- switch (o3_opc) {
79
- case 000: /* LDADD */
80
- fn = tcg_gen_atomic_fetch_add_i64;
81
- break;
82
- case 001: /* LDCLR */
83
- fn = tcg_gen_atomic_fetch_and_i64;
84
- break;
85
- case 002: /* LDEOR */
86
- fn = tcg_gen_atomic_fetch_xor_i64;
87
- break;
88
- case 003: /* LDSET */
89
- fn = tcg_gen_atomic_fetch_or_i64;
90
- break;
91
- case 004: /* LDSMAX */
92
- fn = tcg_gen_atomic_fetch_smax_i64;
93
- mop |= MO_SIGN;
94
- break;
95
- case 005: /* LDSMIN */
96
- fn = tcg_gen_atomic_fetch_smin_i64;
97
- mop |= MO_SIGN;
98
- break;
99
- case 006: /* LDUMAX */
100
- fn = tcg_gen_atomic_fetch_umax_i64;
101
- break;
102
- case 007: /* LDUMIN */
103
- fn = tcg_gen_atomic_fetch_umin_i64;
104
- break;
105
- case 010: /* SWP */
106
- fn = tcg_gen_atomic_xchg_i64;
107
- break;
108
- case 014: /* LDAPR, LDAPRH, LDAPRB */
109
- if (!dc_isar_feature(aa64_rcpc_8_3, s) ||
110
- rs != 31 || a != 1 || r != 0) {
111
- unallocated_encoding(s);
112
- return;
113
- }
114
- break;
115
- default:
116
- unallocated_encoding(s);
117
- return;
118
- }
119
-
120
- if (rn == 31) {
121
+ if (a->rn == 31) {
122
gen_check_sp_alignment(s);
123
}
124
-
125
- mop = check_atomic_align(s, rn, mop);
126
- clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, mop);
127
-
128
- if (o3_opc == 014) {
129
- /*
130
- * LDAPR* are a special case because they are a simple load, not a
131
- * fetch-and-do-something op.
132
- * The architectural consistency requirements here are weaker than
133
- * full load-acquire (we only need "load-acquire processor consistent"),
134
- * but we choose to implement them as full LDAQ.
135
- */
136
- do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, false,
137
- true, rt, disas_ldst_compute_iss_sf(size, false, 0), true);
138
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
139
- return;
140
- }
141
-
142
- tcg_rs = read_cpu_reg(s, rs, true);
143
- tcg_rt = cpu_reg(s, rt);
144
-
145
- if (o3_opc == 1) { /* LDCLR */
146
+ mop = check_atomic_align(s, a->rn, mop);
147
+ clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), false,
148
+ a->rn != 31, mop);
149
+ tcg_rs = read_cpu_reg(s, a->rs, true);
150
+ tcg_rt = cpu_reg(s, a->rt);
151
+ if (invert) {
152
tcg_gen_not_i64(tcg_rs, tcg_rs);
153
}
154
-
155
- /* The tcg atomic primitives are all full barriers. Therefore we
156
+ /*
157
+ * The tcg atomic primitives are all full barriers. Therefore we
158
* can ignore the Acquire and Release bits of this instruction.
159
*/
160
fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop);
161
162
if (mop & MO_SIGN) {
163
- switch (size) {
164
+ switch (a->sz) {
165
case MO_8:
166
tcg_gen_ext8u_i64(tcg_rt, tcg_rt);
167
break;
168
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
169
g_assert_not_reached();
170
}
171
}
172
+ return true;
173
+}
174
+
175
+TRANS_FEAT(LDADD, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_add_i64, 0, false)
176
+TRANS_FEAT(LDCLR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_and_i64, 0, true)
177
+TRANS_FEAT(LDEOR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_xor_i64, 0, false)
178
+TRANS_FEAT(LDSET, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_or_i64, 0, false)
179
+TRANS_FEAT(LDSMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_smax_i64, MO_SIGN, false)
180
+TRANS_FEAT(LDSMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_smin_i64, MO_SIGN, false)
181
+TRANS_FEAT(LDUMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_umax_i64, 0, false)
182
+TRANS_FEAT(LDUMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_umin_i64, 0, false)
183
+TRANS_FEAT(SWP, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_xchg_i64, 0, false)
184
+
185
+static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a)
186
+{
187
+ bool iss_sf = ldst_iss_sf(a->sz, false, false);
188
+ TCGv_i64 clean_addr;
189
+ MemOp mop;
190
+
191
+ if (!dc_isar_feature(aa64_atomics, s) ||
192
+ !dc_isar_feature(aa64_rcpc_8_3, s)) {
193
+ return false;
194
+ }
195
+ if (a->rn == 31) {
196
+ gen_check_sp_alignment(s);
197
+ }
198
+ mop = check_atomic_align(s, a->rn, a->sz);
199
+ clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), false,
200
+ a->rn != 31, mop);
201
+ /*
202
+ * LDAPR* are a special case because they are a simple load, not a
203
+ * fetch-and-do-something op.
204
+ * The architectural consistency requirements here are weaker than
205
+ * full load-acquire (we only need "load-acquire processor consistent"),
206
+ * but we choose to implement them as full LDAQ.
207
+ */
208
+ do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, false,
209
+ true, a->rt, iss_sf, true);
210
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
211
+ return true;
212
}
213
214
/*
215
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
216
}
217
switch (extract32(insn, 10, 2)) {
218
case 0:
219
- disas_ldst_atomic(s, insn, size, rt, is_vector);
220
- return;
221
case 2:
222
break;
223
default:
52
--
224
--
53
2.25.1
225
2.34.1
diff view generated by jsdifflib
[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
[PULL 19/33] target/arm: Convert load (pointer auth) insns to decodetree
1
From: Gavin Shan <gshan@redhat.com>
1
Convert the instructions in the load/store register (pointer
2
authentication) group ot decodetree: LDRAA, LDRAB.
2
3
3
When the PPTT table is built, the CPU topology is re-calculated, but
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
it's unecessary because the CPU topology has been populated in
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
virt_possible_cpu_arch_ids() on arm/virt machine.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20230602155223.2040685-17-peter.maydell@linaro.org
8
---
9
target/arm/tcg/a64.decode | 7 +++
10
target/arm/tcg/translate-a64.c | 83 +++++++---------------------------
11
2 files changed, 23 insertions(+), 67 deletions(-)
6
12
7
This reworks build_pptt() to avoid by reusing the existing IDs in
13
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
8
ms->possible_cpus. Currently, the only user of build_pptt() is
9
arm/virt machine.
10
11
Signed-off-by: Gavin Shan <gshan@redhat.com>
12
Tested-by: Yanan Wang <wangyanan55@huawei.com>
13
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
14
Acked-by: Igor Mammedov <imammedo@redhat.com>
15
Acked-by: Michael S. Tsirkin <mst@redhat.com>
16
Message-id: 20220503140304.855514-7-gshan@redhat.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
20
1 file changed, 48 insertions(+), 63 deletions(-)
21
22
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
23
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/acpi/aml-build.c
15
--- a/target/arm/tcg/a64.decode
25
+++ b/hw/acpi/aml-build.c
16
+++ b/target/arm/tcg/a64.decode
26
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
17
@@ -XXX,XX +XXX,XX @@ LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic
27
const char *oem_id, const char *oem_table_id)
18
SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic
19
20
LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
21
+
22
+# Load/store register (pointer authentication)
23
+
24
+# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous
25
+%ldra_imm 22:s1 12:9 !function=times_2
26
+
27
+LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm
28
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/tcg/translate-a64.c
31
+++ b/target/arm/tcg/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a)
33
return true;
34
}
35
36
-/*
37
- * PAC memory operations
38
- *
39
- * 31 30 27 26 24 22 21 12 11 10 5 0
40
- * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
41
- * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
42
- * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
43
- *
44
- * Rt: the result register
45
- * Rn: base address or SP
46
- * V: vector flag (always 0 as of v8.3)
47
- * M: clear for key DA, set for key DB
48
- * W: pre-indexing flag
49
- * S: sign for imm9.
50
- */
51
-static void disas_ldst_pac(DisasContext *s, uint32_t insn,
52
- int size, int rt, bool is_vector)
53
+static bool trans_LDRA(DisasContext *s, arg_LDRA *a)
28
{
54
{
29
MachineClass *mc = MACHINE_GET_CLASS(ms);
55
- int rn = extract32(insn, 5, 5);
30
- GQueue *list = g_queue_new();
56
- bool is_wback = extract32(insn, 11, 1);
31
- guint pptt_start = table_data->len;
57
- bool use_key_a = !extract32(insn, 23, 1);
32
- guint parent_offset;
58
- int offset;
33
- guint length, i;
59
TCGv_i64 clean_addr, dirty_addr, tcg_rt;
34
- int uid = 0;
60
MemOp memop;
35
- int socket;
61
36
+ CPUArchIdList *cpus = ms->possible_cpus;
62
- if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) {
37
+ int64_t socket_id = -1, cluster_id = -1, core_id = -1;
63
- unallocated_encoding(s);
38
+ uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
64
- return;
39
+ uint32_t pptt_start = table_data->len;
65
+ /* Load with pointer authentication */
40
+ int n;
66
+ if (!dc_isar_feature(aa64_pauth, s)) {
41
AcpiTable table = { .sig = "PPTT", .rev = 2,
67
+ return false;
42
.oem_id = oem_id, .oem_table_id = oem_table_id };
68
}
43
69
44
acpi_table_begin(&table, table_data);
70
- if (rn == 31) {
45
71
+ if (a->rn == 31) {
46
- for (socket = 0; socket < ms->smp.sockets; socket++) {
72
gen_check_sp_alignment(s);
47
- g_queue_push_tail(list,
73
}
48
- GUINT_TO_POINTER(table_data->len - pptt_start));
74
- dirty_addr = read_cpu_reg_sp(s, rn, 1);
49
- build_processor_hierarchy_node(
75
+ dirty_addr = read_cpu_reg_sp(s, a->rn, 1);
50
- table_data,
76
51
- /*
77
if (s->pauth_active) {
52
- * Physical package - represents the boundary
78
- if (use_key_a) {
53
- * of a physical package
79
+ if (!a->m) {
54
- */
80
gen_helper_autda(dirty_addr, cpu_env, dirty_addr,
55
- (1 << 0),
81
tcg_constant_i64(0));
56
- 0, socket, NULL, 0);
82
} else {
57
- }
83
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
58
-
59
- if (mc->smp_props.clusters_supported) {
60
- length = g_queue_get_length(list);
61
- for (i = 0; i < length; i++) {
62
- int cluster;
63
-
64
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
65
- for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
66
- g_queue_push_tail(list,
67
- GUINT_TO_POINTER(table_data->len - pptt_start));
68
- build_processor_hierarchy_node(
69
- table_data,
70
- (0 << 0), /* not a physical package */
71
- parent_offset, cluster, NULL, 0);
72
- }
73
+ /*
74
+ * This works with the assumption that cpus[n].props.*_id has been
75
+ * sorted from top to down levels in mc->possible_cpu_arch_ids().
76
+ * Otherwise, the unexpected and duplicated containers will be
77
+ * created.
78
+ */
79
+ for (n = 0; n < cpus->len; n++) {
80
+ if (cpus->cpus[n].props.socket_id != socket_id) {
81
+ assert(cpus->cpus[n].props.socket_id > socket_id);
82
+ socket_id = cpus->cpus[n].props.socket_id;
83
+ cluster_id = -1;
84
+ core_id = -1;
85
+ socket_offset = table_data->len - pptt_start;
86
+ build_processor_hierarchy_node(table_data,
87
+ (1 << 0), /* Physical package */
88
+ 0, socket_id, NULL, 0);
89
}
90
- }
91
92
- length = g_queue_get_length(list);
93
- for (i = 0; i < length; i++) {
94
- int core;
95
-
96
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
97
- for (core = 0; core < ms->smp.cores; core++) {
98
- if (ms->smp.threads > 1) {
99
- g_queue_push_tail(list,
100
- GUINT_TO_POINTER(table_data->len - pptt_start));
101
- build_processor_hierarchy_node(
102
- table_data,
103
- (0 << 0), /* not a physical package */
104
- parent_offset, core, NULL, 0);
105
- } else {
106
- build_processor_hierarchy_node(
107
- table_data,
108
- (1 << 1) | /* ACPI Processor ID valid */
109
- (1 << 3), /* Node is a Leaf */
110
- parent_offset, uid++, NULL, 0);
111
+ if (mc->smp_props.clusters_supported) {
112
+ if (cpus->cpus[n].props.cluster_id != cluster_id) {
113
+ assert(cpus->cpus[n].props.cluster_id > cluster_id);
114
+ cluster_id = cpus->cpus[n].props.cluster_id;
115
+ core_id = -1;
116
+ cluster_offset = table_data->len - pptt_start;
117
+ build_processor_hierarchy_node(table_data,
118
+ (0 << 0), /* Not a physical package */
119
+ socket_offset, cluster_id, NULL, 0);
120
}
121
+ } else {
122
+ cluster_offset = socket_offset;
123
}
124
- }
125
126
- length = g_queue_get_length(list);
127
- for (i = 0; i < length; i++) {
128
- int thread;
129
+ if (ms->smp.threads == 1) {
130
+ build_processor_hierarchy_node(table_data,
131
+ (1 << 1) | /* ACPI Processor ID valid */
132
+ (1 << 3), /* Node is a Leaf */
133
+ cluster_offset, n, NULL, 0);
134
+ } else {
135
+ if (cpus->cpus[n].props.core_id != core_id) {
136
+ assert(cpus->cpus[n].props.core_id > core_id);
137
+ core_id = cpus->cpus[n].props.core_id;
138
+ core_offset = table_data->len - pptt_start;
139
+ build_processor_hierarchy_node(table_data,
140
+ (0 << 0), /* Not a physical package */
141
+ cluster_offset, core_id, NULL, 0);
142
+ }
143
144
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
145
- for (thread = 0; thread < ms->smp.threads; thread++) {
146
- build_processor_hierarchy_node(
147
- table_data,
148
+ build_processor_hierarchy_node(table_data,
149
(1 << 1) | /* ACPI Processor ID valid */
150
(1 << 2) | /* Processor is a Thread */
151
(1 << 3), /* Node is a Leaf */
152
- parent_offset, uid++, NULL, 0);
153
+ core_offset, n, NULL, 0);
154
}
84
}
155
}
85
}
156
86
157
- g_queue_free(list);
87
- /* Form the 10-bit signed, scaled offset. */
158
acpi_table_end(linker, &table);
88
- offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9);
89
- offset = sextract32(offset << size, 0, 10 + size);
90
- tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
91
+ tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm);
92
93
- memop = finalize_memop(s, size);
94
+ memop = finalize_memop(s, MO_64);
95
96
/* Note that "clean" and "dirty" here refer to TBI not PAC. */
97
clean_addr = gen_mte_check1(s, dirty_addr, false,
98
- is_wback || rn != 31, memop);
99
+ a->w || a->rn != 31, memop);
100
101
- tcg_rt = cpu_reg(s, rt);
102
+ tcg_rt = cpu_reg(s, a->rt);
103
do_gpr_ld(s, tcg_rt, clean_addr, memop,
104
- /* extend */ false, /* iss_valid */ !is_wback,
105
- /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);
106
+ /* extend */ false, /* iss_valid */ !a->w,
107
+ /* iss_srt */ a->rt, /* iss_sf */ true, /* iss_ar */ false);
108
109
- if (is_wback) {
110
- tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr);
111
+ if (a->w) {
112
+ tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr);
113
}
114
+ return true;
159
}
115
}
160
116
117
/*
118
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
119
}
120
}
121
122
-/* Load/store register (all forms) */
123
-static void disas_ldst_reg(DisasContext *s, uint32_t insn)
124
-{
125
- int rt = extract32(insn, 0, 5);
126
- bool is_vector = extract32(insn, 26, 1);
127
- int size = extract32(insn, 30, 2);
128
-
129
- switch (extract32(insn, 24, 2)) {
130
- case 0:
131
- if (extract32(insn, 21, 1) == 0) {
132
- break;
133
- }
134
- switch (extract32(insn, 10, 2)) {
135
- case 0:
136
- case 2:
137
- break;
138
- default:
139
- disas_ldst_pac(s, insn, size, rt, is_vector);
140
- return;
141
- }
142
- break;
143
- }
144
- unallocated_encoding(s);
145
-}
146
-
147
/* AdvSIMD load/store multiple structures
148
*
149
* 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
150
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
151
static void disas_ldst(DisasContext *s, uint32_t insn)
152
{
153
switch (extract32(insn, 24, 6)) {
154
- case 0x38: case 0x39:
155
- case 0x3c: case 0x3d: /* Load/store register (all forms) */
156
- disas_ldst_reg(s, insn);
157
- break;
158
case 0x0c: /* AdvSIMD load/store multiple structures */
159
disas_ldst_multiple_struct(s, insn);
160
break;
161
--
161
--
162
2.25.1
162
2.34.1
163
164
diff view generated by jsdifflib
[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
[PULL 20/33] target/arm: Convert LDAPR/STLR (imm) to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the instructions in the LDAPR/STLR (unscaled immediate)
2
group to decodetree.
2
3
3
Previously we were defining some of these in user-only mode,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
but none of them are accessible from user-only, therefore
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
define them only in system mode.
6
Message-id: 20230602155223.2040685-18-peter.maydell@linaro.org
7
---
8
target/arm/tcg/a64.decode | 10 +++
9
target/arm/tcg/translate-a64.c | 132 ++++++++++++---------------------
10
2 files changed, 56 insertions(+), 86 deletions(-)
6
11
7
This will shortly be used from cpu_tcg.c also.
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/internals.h | 6 ++++
15
target/arm/cpu64.c | 64 +++---------------------------------------
16
target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++
17
3 files changed, 69 insertions(+), 60 deletions(-)
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
14
--- a/target/arm/tcg/a64.decode
22
+++ b/target/arm/internals.h
15
+++ b/target/arm/tcg/a64.decode
23
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
16
@@ -XXX,XX +XXX,XX @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
24
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
17
%ldra_imm 22:s1 12:9 !function=times_2
25
#endif
18
26
19
LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm
27
+#ifdef CONFIG_USER_ONLY
20
+
28
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
21
+&ldapr_stlr_i rn rt imm sz sign ext
29
+#else
22
+@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i
30
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
23
+STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0
31
+#endif
24
+LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0
32
+
25
+LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0
33
#endif
26
+LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1
34
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
27
+LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2
28
+LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0
29
+LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1
30
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
35
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/cpu64.c
32
--- a/target/arm/tcg/translate-a64.c
37
+++ b/target/arm/cpu64.c
33
+++ b/target/arm/tcg/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
39
#include "hvf_arm.h"
35
}
40
#include "qapi/visitor.h"
36
}
41
#include "hw/qdev-properties.h"
37
42
-#include "cpregs.h"
38
-/* Update the Sixty-Four bit (SF) registersize. This logic is derived
43
+#include "internals.h"
39
+/*
44
40
+ * Compute the ISS.SF bit for syndrome information if an exception
45
41
+ * is taken on a load or store. This indicates whether the instruction
46
-#ifndef CONFIG_USER_ONLY
42
+ * is accessing a 32-bit or 64-bit register. This logic is derived
47
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
43
* from the ARMv8 specs for LDR (Shared decode for all encodings).
44
*/
45
-static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
48
-{
46
-{
49
- ARMCPU *cpu = env_archcpu(env);
47
- int opc0 = extract32(opc, 0, 1);
50
-
48
- int regsize;
51
- /* Number of cores is in [25:24]; otherwise we RAZ */
49
-
52
- return (cpu->core_count - 1) << 24;
50
- if (is_signed) {
51
- regsize = opc0 ? 32 : 64;
52
- } else {
53
- regsize = size == 3 ? 64 : 32;
54
- }
55
- return regsize == 64;
53
-}
56
-}
54
-#endif
57
-
55
-
58
static bool ldst_iss_sf(int size, bool sign, bool ext)
56
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
57
-#ifndef CONFIG_USER_ONLY
58
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
59
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
60
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
61
- .writefn = arm_cp_write_ignore },
62
- { .name = "L2CTLR",
63
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
64
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
65
- .writefn = arm_cp_write_ignore },
66
-#endif
67
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
68
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
69
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
70
- { .name = "L2ECTLR",
71
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
72
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
73
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
74
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
75
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
76
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
77
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
78
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
- { .name = "CPUACTLR",
80
- .cp = 15, .opc1 = 0, .crm = 15,
81
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
82
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
83
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
84
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
85
- { .name = "CPUECTLR",
86
- .cp = 15, .opc1 = 1, .crm = 15,
87
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
88
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
89
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
90
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
91
- { .name = "CPUMERRSR",
92
- .cp = 15, .opc1 = 2, .crm = 15,
93
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
94
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
95
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
96
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
97
- { .name = "L2MERRSR",
98
- .cp = 15, .opc1 = 3, .crm = 15,
99
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
100
-};
101
-
102
static void aarch64_a57_initfn(Object *obj)
103
{
59
{
104
ARMCPU *cpu = ARM_CPU(obj);
60
105
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
61
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRA(DisasContext *s, arg_LDRA *a)
106
cpu->gic_num_lrs = 4;
62
return true;
107
cpu->gic_vpribits = 5;
108
cpu->gic_vprebits = 5;
109
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
110
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
111
}
63
}
112
64
113
static void aarch64_a53_initfn(Object *obj)
65
-/*
114
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
66
- * LDAPR/STLR (unscaled immediate)
115
cpu->gic_num_lrs = 4;
67
- *
116
cpu->gic_vpribits = 5;
68
- * 31 30 24 22 21 12 10 5 0
117
cpu->gic_vprebits = 5;
69
- * +------+-------------+-----+---+--------+-----+----+-----+
118
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
70
- * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
119
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
71
- * +------+-------------+-----+---+--------+-----+----+-----+
72
- *
73
- * Rt: source or destination register
74
- * Rn: base register
75
- * imm9: unscaled immediate offset
76
- * opc: 00: STLUR*, 01/10/11: various LDAPUR*
77
- * size: size of load/store
78
- */
79
-static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
80
+static bool trans_LDAPR_i(DisasContext *s, arg_ldapr_stlr_i *a)
81
{
82
- int rt = extract32(insn, 0, 5);
83
- int rn = extract32(insn, 5, 5);
84
- int offset = sextract32(insn, 12, 9);
85
- int opc = extract32(insn, 22, 2);
86
- int size = extract32(insn, 30, 2);
87
TCGv_i64 clean_addr, dirty_addr;
88
- bool is_store = false;
89
- bool extend = false;
90
- bool iss_sf;
91
- MemOp mop = size;
92
+ MemOp mop = a->sz | (a->sign ? MO_SIGN : 0);
93
+ bool iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext);
94
95
if (!dc_isar_feature(aa64_rcpc_8_4, s)) {
96
- unallocated_encoding(s);
97
- return;
98
+ return false;
99
}
100
101
- switch (opc) {
102
- case 0: /* STLURB */
103
- is_store = true;
104
- break;
105
- case 1: /* LDAPUR* */
106
- break;
107
- case 2: /* LDAPURS* 64-bit variant */
108
- if (size == 3) {
109
- unallocated_encoding(s);
110
- return;
111
- }
112
- mop |= MO_SIGN;
113
- break;
114
- case 3: /* LDAPURS* 32-bit variant */
115
- if (size > 1) {
116
- unallocated_encoding(s);
117
- return;
118
- }
119
- mop |= MO_SIGN;
120
- extend = true; /* zero-extend 32->64 after signed load */
121
- break;
122
- default:
123
- g_assert_not_reached();
124
- }
125
-
126
- iss_sf = disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) != 0, opc);
127
-
128
- if (rn == 31) {
129
+ if (a->rn == 31) {
130
gen_check_sp_alignment(s);
131
}
132
133
- mop = check_ordered_align(s, rn, offset, is_store, mop);
134
-
135
- dirty_addr = read_cpu_reg_sp(s, rn, 1);
136
- tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
137
+ mop = check_ordered_align(s, a->rn, a->imm, false, mop);
138
+ dirty_addr = read_cpu_reg_sp(s, a->rn, 1);
139
+ tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm);
140
clean_addr = clean_data_tbi(s, dirty_addr);
141
142
- if (is_store) {
143
- /* Store-Release semantics */
144
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
145
- do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, true);
146
- } else {
147
- /*
148
- * Load-AcquirePC semantics; we implement as the slightly more
149
- * restrictive Load-Acquire.
150
- */
151
- do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop,
152
- extend, true, rt, iss_sf, true);
153
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
154
+ /*
155
+ * Load-AcquirePC semantics; we implement as the slightly more
156
+ * restrictive Load-Acquire.
157
+ */
158
+ do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, a->ext, true,
159
+ a->rt, iss_sf, true);
160
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
161
+ return true;
162
+}
163
+
164
+static bool trans_STLR_i(DisasContext *s, arg_ldapr_stlr_i *a)
165
+{
166
+ TCGv_i64 clean_addr, dirty_addr;
167
+ MemOp mop = a->sz;
168
+ bool iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext);
169
+
170
+ if (!dc_isar_feature(aa64_rcpc_8_4, s)) {
171
+ return false;
172
}
173
+
174
+ /* TODO: ARMv8.4-LSE SCTLR.nAA */
175
+
176
+ if (a->rn == 31) {
177
+ gen_check_sp_alignment(s);
178
+ }
179
+
180
+ mop = check_ordered_align(s, a->rn, a->imm, true, mop);
181
+ dirty_addr = read_cpu_reg_sp(s, a->rn, 1);
182
+ tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm);
183
+ clean_addr = clean_data_tbi(s, dirty_addr);
184
+
185
+ /* Store-Release semantics */
186
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
187
+ do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, mop, true, a->rt, iss_sf, true);
188
+ return true;
120
}
189
}
121
190
122
static void aarch64_a72_initfn(Object *obj)
191
/* AdvSIMD load/store multiple structures
123
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
192
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
124
cpu->gic_num_lrs = 4;
193
case 0x19:
125
cpu->gic_vpribits = 5;
194
if (extract32(insn, 21, 1) != 0) {
126
cpu->gic_vprebits = 5;
195
disas_ldst_tag(s, insn);
127
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
196
- } else if (extract32(insn, 10, 2) == 0) {
128
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
197
- disas_ldst_ldapr_stlr(s, insn);
129
}
198
} else {
130
199
unallocated_encoding(s);
131
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
200
}
132
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
133
index XXXXXXX..XXXXXXX 100644
134
--- a/target/arm/cpu_tcg.c
135
+++ b/target/arm/cpu_tcg.c
136
@@ -XXX,XX +XXX,XX @@
137
#endif
138
#include "cpregs.h"
139
140
+#ifndef CONFIG_USER_ONLY
141
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
142
+{
143
+ ARMCPU *cpu = env_archcpu(env);
144
+
145
+ /* Number of cores is in [25:24]; otherwise we RAZ */
146
+ return (cpu->core_count - 1) << 24;
147
+}
148
+
149
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
150
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
151
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
152
+ .access = PL1_RW, .readfn = l2ctlr_read,
153
+ .writefn = arm_cp_write_ignore },
154
+ { .name = "L2CTLR",
155
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
156
+ .access = PL1_RW, .readfn = l2ctlr_read,
157
+ .writefn = arm_cp_write_ignore },
158
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
159
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
160
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
161
+ { .name = "L2ECTLR",
162
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
163
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
164
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
165
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
166
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
167
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
168
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
169
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
170
+ { .name = "CPUACTLR",
171
+ .cp = 15, .opc1 = 0, .crm = 15,
172
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
173
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
174
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
175
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
176
+ { .name = "CPUECTLR",
177
+ .cp = 15, .opc1 = 1, .crm = 15,
178
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
179
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
180
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
181
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
182
+ { .name = "CPUMERRSR",
183
+ .cp = 15, .opc1 = 2, .crm = 15,
184
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
185
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
186
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
187
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
188
+ { .name = "L2MERRSR",
189
+ .cp = 15, .opc1 = 3, .crm = 15,
190
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
191
+};
192
+
193
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
194
+{
195
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
196
+}
197
+#endif /* !CONFIG_USER_ONLY */
198
+
199
/* CPU models. These are not needed for the AArch64 linux-user build. */
200
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
201
202
--
201
--
203
2.25.1
202
2.34.1
diff view generated by jsdifflib
[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
[PULL 21/33] target/arm: Convert load/store (multiple structures) to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the instructions in the ASIMD load/store multiple structures
2
instruction classes to decodetree.
2
3
3
This feature is AArch64 only, and applies to physical SErrors,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
which QEMU does not implement, thus the feature is a nop.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230602155223.2040685-19-peter.maydell@linaro.org
7
---
8
target/arm/tcg/a64.decode | 20 +++
9
target/arm/tcg/translate-a64.c | 222 ++++++++++++++++-----------------
10
2 files changed, 131 insertions(+), 111 deletions(-)
5
11
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/emulation.rst | 1 +
12
target/arm/cpu64.c | 1 +
13
2 files changed, 2 insertions(+)
14
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
14
--- a/target/arm/tcg/a64.decode
18
+++ b/docs/system/arm/emulation.rst
15
+++ b/target/arm/tcg/a64.decode
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
@@ -XXX,XX +XXX,XX @@ LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext
20
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
17
LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2
21
- FEAT_HPDS (Hierarchical permission disables)
18
LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0
22
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
19
LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1
23
+- FEAT_IESB (Implicit error synchronization event)
20
+
24
- FEAT_JSCVT (JavaScript conversion instructions)
21
+# Load/store multiple structures
25
- FEAT_LOR (Limited ordering regions)
22
+# The 4-bit opcode in [15:12] encodes repeat count and structure elements
26
- FEAT_LPA (Large Physical Address space)
23
+&ldst_mult rm rn rt sz q p rpt selem
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
24
+@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult
25
+ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4
26
+ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1
27
+ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3
28
+ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1
29
+ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
30
+ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
31
+ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
32
+
33
+LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4
34
+LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1
35
+LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3
36
+LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1
37
+LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
38
+LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
39
+LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
40
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
28
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu64.c
42
--- a/target/arm/tcg/translate-a64.c
30
+++ b/target/arm/cpu64.c
43
+++ b/target/arm/tcg/translate-a64.c
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
44
@@ -XXX,XX +XXX,XX @@ static bool trans_STLR_i(DisasContext *s, arg_ldapr_stlr_i *a)
32
t = cpu->isar.id_aa64mmfr2;
45
return true;
33
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
46
}
34
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
47
35
+ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
48
-/* AdvSIMD load/store multiple structures
36
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
49
- *
37
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
50
- * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
38
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
51
- * +---+---+---------------+---+-------------+--------+------+------+------+
52
- * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
53
- * +---+---+---------------+---+-------------+--------+------+------+------+
54
- *
55
- * AdvSIMD load/store multiple structures (post-indexed)
56
- *
57
- * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
58
- * +---+---+---------------+---+---+---------+--------+------+------+------+
59
- * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
60
- * +---+---+---------------+---+---+---------+--------+------+------+------+
61
- *
62
- * Rt: first (or only) SIMD&FP register to be transferred
63
- * Rn: base address or SP
64
- * Rm (post-index only): post-index register (when !31) or size dependent #imm
65
- */
66
-static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
67
+static bool trans_LD_mult(DisasContext *s, arg_ldst_mult *a)
68
{
69
- int rt = extract32(insn, 0, 5);
70
- int rn = extract32(insn, 5, 5);
71
- int rm = extract32(insn, 16, 5);
72
- int size = extract32(insn, 10, 2);
73
- int opcode = extract32(insn, 12, 4);
74
- bool is_store = !extract32(insn, 22, 1);
75
- bool is_postidx = extract32(insn, 23, 1);
76
- bool is_q = extract32(insn, 30, 1);
77
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
78
MemOp endian, align, mop;
79
80
int total; /* total bytes */
81
int elements; /* elements per vector */
82
- int rpt; /* num iterations */
83
- int selem; /* structure elements */
84
int r;
85
+ int size = a->sz;
86
87
- if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) {
88
- unallocated_encoding(s);
89
- return;
90
+ if (!a->p && a->rm != 0) {
91
+ /* For non-postindexed accesses the Rm field must be 0 */
92
+ return false;
93
}
94
-
95
- if (!is_postidx && rm != 0) {
96
- unallocated_encoding(s);
97
- return;
98
+ if (size == 3 && !a->q && a->selem != 1) {
99
+ return false;
100
}
101
-
102
- /* From the shared decode logic */
103
- switch (opcode) {
104
- case 0x0:
105
- rpt = 1;
106
- selem = 4;
107
- break;
108
- case 0x2:
109
- rpt = 4;
110
- selem = 1;
111
- break;
112
- case 0x4:
113
- rpt = 1;
114
- selem = 3;
115
- break;
116
- case 0x6:
117
- rpt = 3;
118
- selem = 1;
119
- break;
120
- case 0x7:
121
- rpt = 1;
122
- selem = 1;
123
- break;
124
- case 0x8:
125
- rpt = 1;
126
- selem = 2;
127
- break;
128
- case 0xa:
129
- rpt = 2;
130
- selem = 1;
131
- break;
132
- default:
133
- unallocated_encoding(s);
134
- return;
135
- }
136
-
137
- if (size == 3 && !is_q && selem != 1) {
138
- /* reserved */
139
- unallocated_encoding(s);
140
- return;
141
- }
142
-
143
if (!fp_access_check(s)) {
144
- return;
145
+ return true;
146
}
147
148
- if (rn == 31) {
149
+ if (a->rn == 31) {
150
gen_check_sp_alignment(s);
151
}
152
153
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
154
endian = MO_LE;
155
}
156
157
- total = rpt * selem * (is_q ? 16 : 8);
158
- tcg_rn = cpu_reg_sp(s, rn);
159
+ total = a->rpt * a->selem * (a->q ? 16 : 8);
160
+ tcg_rn = cpu_reg_sp(s, a->rn);
161
162
/*
163
* Issue the MTE check vs the logical repeat count, before we
164
* promote consecutive little-endian elements below.
165
*/
166
- clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31,
167
- total, finalize_memop_asimd(s, size));
168
+ clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31, total,
169
+ finalize_memop_asimd(s, size));
170
171
/*
172
* Consecutive little-endian elements from a single register
173
* can be promoted to a larger little-endian operation.
174
*/
175
align = MO_ALIGN;
176
- if (selem == 1 && endian == MO_LE) {
177
+ if (a->selem == 1 && endian == MO_LE) {
178
align = pow2_align(size);
179
size = 3;
180
}
181
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
182
}
183
mop = endian | size | align;
184
185
- elements = (is_q ? 16 : 8) >> size;
186
+ elements = (a->q ? 16 : 8) >> size;
187
tcg_ebytes = tcg_constant_i64(1 << size);
188
- for (r = 0; r < rpt; r++) {
189
+ for (r = 0; r < a->rpt; r++) {
190
int e;
191
for (e = 0; e < elements; e++) {
192
int xs;
193
- for (xs = 0; xs < selem; xs++) {
194
- int tt = (rt + r + xs) % 32;
195
- if (is_store) {
196
- do_vec_st(s, tt, e, clean_addr, mop);
197
- } else {
198
- do_vec_ld(s, tt, e, clean_addr, mop);
199
- }
200
+ for (xs = 0; xs < a->selem; xs++) {
201
+ int tt = (a->rt + r + xs) % 32;
202
+ do_vec_ld(s, tt, e, clean_addr, mop);
203
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
204
}
205
}
206
}
207
208
- if (!is_store) {
209
- /* For non-quad operations, setting a slice of the low
210
- * 64 bits of the register clears the high 64 bits (in
211
- * the ARM ARM pseudocode this is implicit in the fact
212
- * that 'rval' is a 64 bit wide variable).
213
- * For quad operations, we might still need to zero the
214
- * high bits of SVE.
215
- */
216
- for (r = 0; r < rpt * selem; r++) {
217
- int tt = (rt + r) % 32;
218
- clear_vec_high(s, is_q, tt);
219
+ /*
220
+ * For non-quad operations, setting a slice of the low 64 bits of
221
+ * the register clears the high 64 bits (in the ARM ARM pseudocode
222
+ * this is implicit in the fact that 'rval' is a 64 bit wide
223
+ * variable). For quad operations, we might still need to zero
224
+ * the high bits of SVE.
225
+ */
226
+ for (r = 0; r < a->rpt * a->selem; r++) {
227
+ int tt = (a->rt + r) % 32;
228
+ clear_vec_high(s, a->q, tt);
229
+ }
230
+
231
+ if (a->p) {
232
+ if (a->rm == 31) {
233
+ tcg_gen_addi_i64(tcg_rn, tcg_rn, total);
234
+ } else {
235
+ tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm));
236
+ }
237
+ }
238
+ return true;
239
+}
240
+
241
+static bool trans_ST_mult(DisasContext *s, arg_ldst_mult *a)
242
+{
243
+ TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
244
+ MemOp endian, align, mop;
245
+
246
+ int total; /* total bytes */
247
+ int elements; /* elements per vector */
248
+ int r;
249
+ int size = a->sz;
250
+
251
+ if (!a->p && a->rm != 0) {
252
+ /* For non-postindexed accesses the Rm field must be 0 */
253
+ return false;
254
+ }
255
+ if (size == 3 && !a->q && a->selem != 1) {
256
+ return false;
257
+ }
258
+ if (!fp_access_check(s)) {
259
+ return true;
260
+ }
261
+
262
+ if (a->rn == 31) {
263
+ gen_check_sp_alignment(s);
264
+ }
265
+
266
+ /* For our purposes, bytes are always little-endian. */
267
+ endian = s->be_data;
268
+ if (size == 0) {
269
+ endian = MO_LE;
270
+ }
271
+
272
+ total = a->rpt * a->selem * (a->q ? 16 : 8);
273
+ tcg_rn = cpu_reg_sp(s, a->rn);
274
+
275
+ /*
276
+ * Issue the MTE check vs the logical repeat count, before we
277
+ * promote consecutive little-endian elements below.
278
+ */
279
+ clean_addr = gen_mte_checkN(s, tcg_rn, true, a->p || a->rn != 31, total,
280
+ finalize_memop_asimd(s, size));
281
+
282
+ /*
283
+ * Consecutive little-endian elements from a single register
284
+ * can be promoted to a larger little-endian operation.
285
+ */
286
+ align = MO_ALIGN;
287
+ if (a->selem == 1 && endian == MO_LE) {
288
+ align = pow2_align(size);
289
+ size = 3;
290
+ }
291
+ if (!s->align_mem) {
292
+ align = 0;
293
+ }
294
+ mop = endian | size | align;
295
+
296
+ elements = (a->q ? 16 : 8) >> size;
297
+ tcg_ebytes = tcg_constant_i64(1 << size);
298
+ for (r = 0; r < a->rpt; r++) {
299
+ int e;
300
+ for (e = 0; e < elements; e++) {
301
+ int xs;
302
+ for (xs = 0; xs < a->selem; xs++) {
303
+ int tt = (a->rt + r + xs) % 32;
304
+ do_vec_st(s, tt, e, clean_addr, mop);
305
+ tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
306
+ }
307
}
308
}
309
310
- if (is_postidx) {
311
- if (rm == 31) {
312
+ if (a->p) {
313
+ if (a->rm == 31) {
314
tcg_gen_addi_i64(tcg_rn, tcg_rn, total);
315
} else {
316
- tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
317
+ tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm));
318
}
319
}
320
+ return true;
321
}
322
323
/* AdvSIMD load/store single structure
324
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
325
static void disas_ldst(DisasContext *s, uint32_t insn)
326
{
327
switch (extract32(insn, 24, 6)) {
328
- case 0x0c: /* AdvSIMD load/store multiple structures */
329
- disas_ldst_multiple_struct(s, insn);
330
- break;
331
case 0x0d: /* AdvSIMD load/store single structure */
332
disas_ldst_single_struct(s, insn);
333
break;
39
--
334
--
40
2.25.1
335
2.34.1
diff view generated by jsdifflib
[PULL 24/32] target/arm: Define cortex-a76
[PULL 22/33] target/arm: Convert load/store single structure to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the ASIMD load/store single structure insns to decodetree.
2
2
3
Enable the a76 for virt and sbsa board use.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Message-id: 20230602155223.2040685-20-peter.maydell@linaro.org
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/arm/tcg/a64.decode | 34 +++++
8
target/arm/tcg/translate-a64.c | 219 +++++++++++++++------------------
9
2 files changed, 136 insertions(+), 117 deletions(-)
4
10
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
docs/system/arm/virt.rst | 1 +
11
hw/arm/sbsa-ref.c | 1 +
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
15
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/virt.rst
13
--- a/target/arm/tcg/a64.decode
19
+++ b/docs/system/arm/virt.rst
14
+++ b/target/arm/tcg/a64.decode
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
15
@@ -XXX,XX +XXX,XX @@ LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 sele
21
- ``cortex-a53`` (64-bit)
16
LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
22
- ``cortex-a57`` (64-bit)
17
LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
23
- ``cortex-a72`` (64-bit)
18
LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
24
+- ``cortex-a76`` (64-bit)
19
+
25
- ``a64fx`` (64-bit)
20
+# Load/store single structure
26
- ``host`` (with KVM only)
21
+&ldst_single rm rn rt p selem index scale
27
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
22
+
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
23
+%ldst_single_selem 13:1 21:1 !function=plus_1
24
+
25
+%ldst_single_index_b 30:1 10:3
26
+%ldst_single_index_h 30:1 11:2
27
+%ldst_single_index_s 30:1 12:1
28
+
29
+@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
30
+ &ldst_single scale=0 selem=%ldst_single_selem \
31
+ index=%ldst_single_index_b
32
+@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
33
+ &ldst_single scale=1 selem=%ldst_single_selem \
34
+ index=%ldst_single_index_h
35
+@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
36
+ &ldst_single scale=2 selem=%ldst_single_selem \
37
+ index=%ldst_single_index_s
38
+@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \
39
+ &ldst_single scale=3 selem=%ldst_single_selem
40
+
41
+ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b
42
+ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h
43
+ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s
44
+ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d
45
+
46
+LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b
47
+LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h
48
+LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s
49
+LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d
50
+
51
+# Replicating load case
52
+LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem
53
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/sbsa-ref.c
55
--- a/target/arm/tcg/translate-a64.c
31
+++ b/hw/arm/sbsa-ref.c
56
+++ b/target/arm/tcg/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
57
@@ -XXX,XX +XXX,XX @@ static bool trans_ST_mult(DisasContext *s, arg_ldst_mult *a)
33
static const char * const valid_cpus[] = {
58
return true;
34
ARM_CPU_TYPE_NAME("cortex-a57"),
35
ARM_CPU_TYPE_NAME("cortex-a72"),
36
+ ARM_CPU_TYPE_NAME("cortex-a76"),
37
ARM_CPU_TYPE_NAME("max"),
38
};
39
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a53"),
46
ARM_CPU_TYPE_NAME("cortex-a57"),
47
ARM_CPU_TYPE_NAME("cortex-a72"),
48
+ ARM_CPU_TYPE_NAME("cortex-a76"),
49
ARM_CPU_TYPE_NAME("a64fx"),
50
ARM_CPU_TYPE_NAME("host"),
51
ARM_CPU_TYPE_NAME("max"),
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
57
define_cortex_a72_a57_a53_cp_reginfo(cpu);
58
}
59
}
59
60
60
+static void aarch64_a76_initfn(Object *obj)
61
-/* AdvSIMD load/store single structure
62
- *
63
- * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
64
- * +---+---+---------------+-----+-----------+-----+---+------+------+------+
65
- * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
66
- * +---+---+---------------+-----+-----------+-----+---+------+------+------+
67
- *
68
- * AdvSIMD load/store single structure (post-indexed)
69
- *
70
- * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
71
- * +---+---+---------------+-----+-----------+-----+---+------+------+------+
72
- * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
73
- * +---+---+---------------+-----+-----------+-----+---+------+------+------+
74
- *
75
- * Rt: first (or only) SIMD&FP register to be transferred
76
- * Rn: base address or SP
77
- * Rm (post-index only): post-index register (when !31) or size dependent #imm
78
- * index = encoded in Q:S:size dependent on size
79
- *
80
- * lane_size = encoded in R, opc
81
- * transfer width = encoded in opc, S, size
82
- */
83
-static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
84
+static bool trans_ST_single(DisasContext *s, arg_ldst_single *a)
85
{
86
- int rt = extract32(insn, 0, 5);
87
- int rn = extract32(insn, 5, 5);
88
- int rm = extract32(insn, 16, 5);
89
- int size = extract32(insn, 10, 2);
90
- int S = extract32(insn, 12, 1);
91
- int opc = extract32(insn, 13, 3);
92
- int R = extract32(insn, 21, 1);
93
- int is_load = extract32(insn, 22, 1);
94
- int is_postidx = extract32(insn, 23, 1);
95
- int is_q = extract32(insn, 30, 1);
96
-
97
- int scale = extract32(opc, 1, 2);
98
- int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
99
- bool replicate = false;
100
- int index = is_q << 3 | S << 2 | size;
101
- int xs, total;
102
+ int xs, total, rt;
103
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
104
MemOp mop;
105
106
- if (extract32(insn, 31, 1)) {
107
- unallocated_encoding(s);
108
- return;
109
+ if (!a->p && a->rm != 0) {
110
+ return false;
111
}
112
- if (!is_postidx && rm != 0) {
113
- unallocated_encoding(s);
114
- return;
115
- }
116
-
117
- switch (scale) {
118
- case 3:
119
- if (!is_load || S) {
120
- unallocated_encoding(s);
121
- return;
122
- }
123
- scale = size;
124
- replicate = true;
125
- break;
126
- case 0:
127
- break;
128
- case 1:
129
- if (extract32(size, 0, 1)) {
130
- unallocated_encoding(s);
131
- return;
132
- }
133
- index >>= 1;
134
- break;
135
- case 2:
136
- if (extract32(size, 1, 1)) {
137
- unallocated_encoding(s);
138
- return;
139
- }
140
- if (!extract32(size, 0, 1)) {
141
- index >>= 2;
142
- } else {
143
- if (S) {
144
- unallocated_encoding(s);
145
- return;
146
- }
147
- index >>= 3;
148
- scale = 3;
149
- }
150
- break;
151
- default:
152
- g_assert_not_reached();
153
- }
154
-
155
if (!fp_access_check(s)) {
156
- return;
157
+ return true;
158
}
159
160
- if (rn == 31) {
161
+ if (a->rn == 31) {
162
gen_check_sp_alignment(s);
163
}
164
165
- total = selem << scale;
166
- tcg_rn = cpu_reg_sp(s, rn);
167
+ total = a->selem << a->scale;
168
+ tcg_rn = cpu_reg_sp(s, a->rn);
169
170
- mop = finalize_memop_asimd(s, scale);
171
-
172
- clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
173
+ mop = finalize_memop_asimd(s, a->scale);
174
+ clean_addr = gen_mte_checkN(s, tcg_rn, true, a->p || a->rn != 31,
175
total, mop);
176
177
- tcg_ebytes = tcg_constant_i64(1 << scale);
178
- for (xs = 0; xs < selem; xs++) {
179
- if (replicate) {
180
- /* Load and replicate to all elements */
181
- TCGv_i64 tcg_tmp = tcg_temp_new_i64();
182
-
183
- tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop);
184
- tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
185
- (is_q + 1) * 8, vec_full_reg_size(s),
186
- tcg_tmp);
187
- } else {
188
- /* Load/store one element per register */
189
- if (is_load) {
190
- do_vec_ld(s, rt, index, clean_addr, mop);
191
- } else {
192
- do_vec_st(s, rt, index, clean_addr, mop);
193
- }
194
- }
195
+ tcg_ebytes = tcg_constant_i64(1 << a->scale);
196
+ for (xs = 0, rt = a->rt; xs < a->selem; xs++, rt = (rt + 1) % 32) {
197
+ do_vec_st(s, rt, a->index, clean_addr, mop);
198
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
199
- rt = (rt + 1) % 32;
200
}
201
202
- if (is_postidx) {
203
- if (rm == 31) {
204
+ if (a->p) {
205
+ if (a->rm == 31) {
206
tcg_gen_addi_i64(tcg_rn, tcg_rn, total);
207
} else {
208
- tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
209
+ tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm));
210
}
211
}
212
+ return true;
213
+}
214
+
215
+static bool trans_LD_single(DisasContext *s, arg_ldst_single *a)
61
+{
216
+{
62
+ ARMCPU *cpu = ARM_CPU(obj);
217
+ int xs, total, rt;
63
+
218
+ TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
64
+ cpu->dtb_compatible = "arm,cortex-a76";
219
+ MemOp mop;
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
220
+
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
221
+ if (!a->p && a->rm != 0) {
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
222
+ return false;
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
223
+ }
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
224
+ if (!fp_access_check(s)) {
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
225
+ return true;
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
226
+ }
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
227
+
73
+
228
+ if (a->rn == 31) {
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
229
+ gen_check_sp_alignment(s);
75
+ cpu->clidr = 0x82000023;
230
+ }
76
+ cpu->ctr = 0x8444C004;
231
+
77
+ cpu->dcz_blocksize = 4;
232
+ total = a->selem << a->scale;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
233
+ tcg_rn = cpu_reg_sp(s, a->rn);
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
234
+
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
235
+ mop = finalize_memop_asimd(s, a->scale);
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
236
+ clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31,
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
237
+ total, mop);
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
238
+
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
239
+ tcg_ebytes = tcg_constant_i64(1 << a->scale);
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
240
+ for (xs = 0, rt = a->rt; xs < a->selem; xs++, rt = (rt + 1) % 32) {
86
+ cpu->id_afr0 = 0x00000000;
241
+ do_vec_ld(s, rt, a->index, clean_addr, mop);
87
+ cpu->isar.id_dfr0 = 0x04010088;
242
+ tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
88
+ cpu->isar.id_isar0 = 0x02101110;
243
+ }
89
+ cpu->isar.id_isar1 = 0x13112111;
244
+
90
+ cpu->isar.id_isar2 = 0x21232042;
245
+ if (a->p) {
91
+ cpu->isar.id_isar3 = 0x01112131;
246
+ if (a->rm == 31) {
92
+ cpu->isar.id_isar4 = 0x00010142;
247
+ tcg_gen_addi_i64(tcg_rn, tcg_rn, total);
93
+ cpu->isar.id_isar5 = 0x01011121;
248
+ } else {
94
+ cpu->isar.id_isar6 = 0x00000010;
249
+ tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm));
95
+ cpu->isar.id_mmfr0 = 0x10201105;
250
+ }
96
+ cpu->isar.id_mmfr1 = 0x40000000;
251
+ }
97
+ cpu->isar.id_mmfr2 = 0x01260000;
252
+ return true;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0b1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.18 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
110
+
111
+ /* From B2.93 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
123
+}
253
+}
124
+
254
+
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
255
+static bool trans_LD_single_repl(DisasContext *s, arg_LD_single_repl *a)
256
+{
257
+ int xs, total, rt;
258
+ TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
259
+ MemOp mop;
260
+
261
+ if (!a->p && a->rm != 0) {
262
+ return false;
263
+ }
264
+ if (!fp_access_check(s)) {
265
+ return true;
266
+ }
267
+
268
+ if (a->rn == 31) {
269
+ gen_check_sp_alignment(s);
270
+ }
271
+
272
+ total = a->selem << a->scale;
273
+ tcg_rn = cpu_reg_sp(s, a->rn);
274
+
275
+ mop = finalize_memop_asimd(s, a->scale);
276
+ clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31,
277
+ total, mop);
278
+
279
+ tcg_ebytes = tcg_constant_i64(1 << a->scale);
280
+ for (xs = 0, rt = a->rt; xs < a->selem; xs++, rt = (rt + 1) % 32) {
281
+ /* Load and replicate to all elements */
282
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
283
+
284
+ tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop);
285
+ tcg_gen_gvec_dup_i64(a->scale, vec_full_reg_offset(s, rt),
286
+ (a->q + 1) * 8, vec_full_reg_size(s), tcg_tmp);
287
+ tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
288
+ }
289
+
290
+ if (a->p) {
291
+ if (a->rm == 31) {
292
+ tcg_gen_addi_i64(tcg_rn, tcg_rn, total);
293
+ } else {
294
+ tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm));
295
+ }
296
+ }
297
+ return true;
298
}
299
300
/*
301
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
302
static void disas_ldst(DisasContext *s, uint32_t insn)
126
{
303
{
127
/*
304
switch (extract32(insn, 24, 6)) {
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
305
- case 0x0d: /* AdvSIMD load/store single structure */
129
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
306
- disas_ldst_single_struct(s, insn);
130
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
307
- break;
131
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
308
case 0x19:
132
+ { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
309
if (extract32(insn, 21, 1) != 0) {
133
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
310
disas_ldst_tag(s, insn);
134
{ .name = "max", .initfn = aarch64_max_initfn },
135
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
136
--
311
--
137
2.25.1
312
2.34.1
diff view generated by jsdifflib
[PULL 14/32] target/arm: Add minimal RAS registers
[PULL 23/33] target/arm: Convert load/store tags insns to decodetree
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the instructions in the load/store memory tags instruction
2
group to decodetree.
2
3
3
Add only the system registers required to implement zero error
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
records. This means that all values for ERRSELR are out of range,
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
which means that it and all of the indexed error record registers
6
Message-id: 20230602155223.2040685-21-peter.maydell@linaro.org
6
need not be implemented.
7
---
8
target/arm/tcg/a64.decode | 25 +++
9
target/arm/tcg/translate-a64.c | 360 ++++++++++++++++-----------------
10
2 files changed, 199 insertions(+), 186 deletions(-)
7
11
8
Add the EL2 registers required for injecting virtual SError.
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/cpu.h | 5 +++
16
target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
17
2 files changed, 89 insertions(+)
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
14
--- a/target/arm/tcg/a64.decode
22
+++ b/target/arm/cpu.h
15
+++ b/target/arm/tcg/a64.decode
23
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
16
@@ -XXX,XX +XXX,XX @@ LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d
24
uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
17
25
uint64_t gcr_el1;
18
# Replicating load case
26
uint64_t rgsr_el1;
19
LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem
27
+
20
+
28
+ /* Minimal RAS registers */
21
+%tag_offset 12:s9 !function=scale_by_log2_tag_granule
29
+ uint64_t disr_el1;
22
+&ldst_tag rn rt imm p w
30
+ uint64_t vdisr_el2;
23
+@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset
31
+ uint64_t vsesr_el2;
24
+@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0
32
} cp15;
25
+
33
26
+STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
34
struct {
27
+STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
+STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
29
+STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
30
+
31
+LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0
32
+STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
33
+STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
34
+STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
35
+
36
+STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
37
+ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
38
+ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
39
+ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
40
+
41
+LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
42
+STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
43
+STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
44
+STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
45
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
36
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper.c
47
--- a/target/arm/tcg/translate-a64.c
38
+++ b/target/arm/helper.c
48
+++ b/target/arm/tcg/translate-a64.c
39
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
49
@@ -XXX,XX +XXX,XX @@ static int uimm_scaled(DisasContext *s, int x)
40
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
50
return imm << scale;
41
};
51
}
42
52
43
+/*
53
+/* For load/store memory tags: scale offset by LOG2_TAG_GRANULE */
44
+ * Check for traps to RAS registers, which are controlled
54
+static int scale_by_log2_tag_granule(DisasContext *s, int x)
45
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
46
+ */
47
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
48
+ bool isread)
49
+{
55
+{
50
+ int el = arm_current_el(env);
56
+ return x << LOG2_TAG_GRANULE;
51
+
52
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
53
+ return CP_ACCESS_TRAP_EL2;
54
+ }
55
+ if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
56
+ return CP_ACCESS_TRAP_EL3;
57
+ }
58
+ return CP_ACCESS_OK;
59
+}
57
+}
60
+
58
+
61
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
59
/*
60
* Include the generated decoders.
61
*/
62
@@ -XXX,XX +XXX,XX @@ static bool trans_LD_single_repl(DisasContext *s, arg_LD_single_repl *a)
63
return true;
64
}
65
66
-/*
67
- * Load/Store memory tags
68
- *
69
- * 31 30 29 24 22 21 12 10 5 0
70
- * +-----+-------------+-----+---+------+-----+------+------+
71
- * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
72
- * +-----+-------------+-----+---+------+-----+------+------+
73
- */
74
-static void disas_ldst_tag(DisasContext *s, uint32_t insn)
75
+static bool trans_STZGM(DisasContext *s, arg_ldst_tag *a)
76
{
77
- int rt = extract32(insn, 0, 5);
78
- int rn = extract32(insn, 5, 5);
79
- uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE;
80
- int op2 = extract32(insn, 10, 2);
81
- int op1 = extract32(insn, 22, 2);
82
- bool is_load = false, is_pair = false, is_zero = false, is_mult = false;
83
- int index = 0;
84
TCGv_i64 addr, clean_addr, tcg_rt;
85
+ int size = 4 << s->dcz_blocksize;
86
87
- /* We checked insn bits [29:24,21] in the caller. */
88
- if (extract32(insn, 30, 2) != 3) {
89
- goto do_unallocated;
90
+ if (!dc_isar_feature(aa64_mte, s)) {
91
+ return false;
92
+ }
93
+ if (s->current_el == 0) {
94
+ return false;
95
}
96
97
- /*
98
- * @index is a tri-state variable which has 3 states:
99
- * < 0 : post-index, writeback
100
- * = 0 : signed offset
101
- * > 0 : pre-index, writeback
102
- */
103
- switch (op1) {
104
- case 0:
105
- if (op2 != 0) {
106
- /* STG */
107
- index = op2 - 2;
108
- } else {
109
- /* STZGM */
110
- if (s->current_el == 0 || offset != 0) {
111
- goto do_unallocated;
112
- }
113
- is_mult = is_zero = true;
114
- }
115
- break;
116
- case 1:
117
- if (op2 != 0) {
118
- /* STZG */
119
- is_zero = true;
120
- index = op2 - 2;
121
- } else {
122
- /* LDG */
123
- is_load = true;
124
- }
125
- break;
126
- case 2:
127
- if (op2 != 0) {
128
- /* ST2G */
129
- is_pair = true;
130
- index = op2 - 2;
131
- } else {
132
- /* STGM */
133
- if (s->current_el == 0 || offset != 0) {
134
- goto do_unallocated;
135
- }
136
- is_mult = true;
137
- }
138
- break;
139
- case 3:
140
- if (op2 != 0) {
141
- /* STZ2G */
142
- is_pair = is_zero = true;
143
- index = op2 - 2;
144
- } else {
145
- /* LDGM */
146
- if (s->current_el == 0 || offset != 0) {
147
- goto do_unallocated;
148
- }
149
- is_mult = is_load = true;
150
- }
151
- break;
152
-
153
- default:
154
- do_unallocated:
155
- unallocated_encoding(s);
156
- return;
157
- }
158
-
159
- if (is_mult
160
- ? !dc_isar_feature(aa64_mte, s)
161
- : !dc_isar_feature(aa64_mte_insn_reg, s)) {
162
- goto do_unallocated;
163
- }
164
-
165
- if (rn == 31) {
166
+ if (a->rn == 31) {
167
gen_check_sp_alignment(s);
168
}
169
170
- addr = read_cpu_reg_sp(s, rn, true);
171
- if (index >= 0) {
172
+ addr = read_cpu_reg_sp(s, a->rn, true);
173
+ tcg_gen_addi_i64(addr, addr, a->imm);
174
+ tcg_rt = cpu_reg(s, a->rt);
175
+
176
+ if (s->ata) {
177
+ gen_helper_stzgm_tags(cpu_env, addr, tcg_rt);
178
+ }
179
+ /*
180
+ * The non-tags portion of STZGM is mostly like DC_ZVA,
181
+ * except the alignment happens before the access.
182
+ */
183
+ clean_addr = clean_data_tbi(s, addr);
184
+ tcg_gen_andi_i64(clean_addr, clean_addr, -size);
185
+ gen_helper_dc_zva(cpu_env, clean_addr);
186
+ return true;
187
+}
188
+
189
+static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
62
+{
190
+{
63
+ int el = arm_current_el(env);
191
+ TCGv_i64 addr, clean_addr, tcg_rt;
64
+
192
+
65
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
193
+ if (!dc_isar_feature(aa64_mte, s)) {
66
+ return env->cp15.vdisr_el2;
194
+ return false;
67
+ }
195
+ }
68
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
196
+ if (s->current_el == 0) {
69
+ return 0; /* RAZ/WI */
197
+ return false;
70
+ }
198
+ }
71
+ return env->cp15.disr_el1;
199
+
200
+ if (a->rn == 31) {
201
+ gen_check_sp_alignment(s);
202
+ }
203
+
204
+ addr = read_cpu_reg_sp(s, a->rn, true);
205
+ tcg_gen_addi_i64(addr, addr, a->imm);
206
+ tcg_rt = cpu_reg(s, a->rt);
207
+
208
+ if (s->ata) {
209
+ gen_helper_stgm(cpu_env, addr, tcg_rt);
210
+ } else {
211
+ MMUAccessType acc = MMU_DATA_STORE;
212
+ int size = 4 << GMID_EL1_BS;
213
+
214
+ clean_addr = clean_data_tbi(s, addr);
215
+ tcg_gen_andi_i64(clean_addr, clean_addr, -size);
216
+ gen_probe_access(s, clean_addr, acc, size);
217
+ }
218
+ return true;
72
+}
219
+}
73
+
220
+
74
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
221
+static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
75
+{
222
+{
76
+ int el = arm_current_el(env);
223
+ TCGv_i64 addr, clean_addr, tcg_rt;
77
+
224
+
78
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
225
+ if (!dc_isar_feature(aa64_mte, s)) {
79
+ env->cp15.vdisr_el2 = val;
226
+ return false;
80
+ return;
227
+ }
81
+ }
228
+ if (s->current_el == 0) {
82
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
229
+ return false;
83
+ return; /* RAZ/WI */
230
+ }
84
+ }
231
+
85
+ env->cp15.disr_el1 = val;
232
+ if (a->rn == 31) {
233
+ gen_check_sp_alignment(s);
234
+ }
235
+
236
+ addr = read_cpu_reg_sp(s, a->rn, true);
237
+ tcg_gen_addi_i64(addr, addr, a->imm);
238
+ tcg_rt = cpu_reg(s, a->rt);
239
+
240
+ if (s->ata) {
241
+ gen_helper_ldgm(tcg_rt, cpu_env, addr);
242
+ } else {
243
+ MMUAccessType acc = MMU_DATA_LOAD;
244
+ int size = 4 << GMID_EL1_BS;
245
+
246
+ clean_addr = clean_data_tbi(s, addr);
247
+ tcg_gen_andi_i64(clean_addr, clean_addr, -size);
248
+ gen_probe_access(s, clean_addr, acc, size);
249
+ /* The result tags are zeros. */
250
+ tcg_gen_movi_i64(tcg_rt, 0);
251
+ }
252
+ return true;
86
+}
253
+}
87
+
254
+
88
+/*
255
+static bool trans_LDG(DisasContext *s, arg_ldst_tag *a)
89
+ * Minimal RAS implementation with no Error Records.
256
+{
90
+ * Which means that all of the Error Record registers:
257
+ TCGv_i64 addr, clean_addr, tcg_rt;
91
+ * ERXADDR_EL1
258
+
92
+ * ERXCTLR_EL1
259
+ if (!dc_isar_feature(aa64_mte_insn_reg, s)) {
93
+ * ERXFR_EL1
260
+ return false;
94
+ * ERXMISC0_EL1
261
+ }
95
+ * ERXMISC1_EL1
262
+
96
+ * ERXMISC2_EL1
263
+ if (a->rn == 31) {
97
+ * ERXMISC3_EL1
264
+ gen_check_sp_alignment(s);
98
+ * ERXPFGCDN_EL1 (RASv1p1)
265
+ }
99
+ * ERXPFGCTL_EL1 (RASv1p1)
266
+
100
+ * ERXPFGF_EL1 (RASv1p1)
267
+ addr = read_cpu_reg_sp(s, a->rn, true);
101
+ * ERXSTATUS_EL1
268
+ if (!a->p) {
102
+ * and
269
/* pre-index or signed offset */
103
+ * ERRSELR_EL1
270
- tcg_gen_addi_i64(addr, addr, offset);
104
+ * may generate UNDEFINED, which is the effect we get by not
271
+ tcg_gen_addi_i64(addr, addr, a->imm);
105
+ * listing them at all.
272
}
106
+ */
273
107
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
274
- if (is_mult) {
108
+ { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
275
- tcg_rt = cpu_reg(s, rt);
109
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
276
+ tcg_gen_andi_i64(addr, addr, -TAG_GRANULE);
110
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
277
+ tcg_rt = cpu_reg(s, a->rt);
111
+ .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
278
+ if (s->ata) {
112
+ { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
279
+ gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt);
113
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
280
+ } else {
114
+ .access = PL1_R, .accessfn = access_terr,
281
+ /*
115
+ .type = ARM_CP_CONST, .resetvalue = 0 },
282
+ * Tag access disabled: we must check for aborts on the load
116
+ { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
283
+ * load from [rn+offset], and then insert a 0 tag into rt.
117
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
284
+ */
118
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
285
+ clean_addr = clean_data_tbi(s, addr);
119
+ { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
286
+ gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8);
120
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
287
+ gen_address_with_allocation_tag0(tcg_rt, tcg_rt);
121
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
288
+ }
122
+};
289
123
+
290
- if (is_zero) {
124
/* Return the exception level to which exceptions should be taken
291
- int size = 4 << s->dcz_blocksize;
125
* via SVEAccessTrap. If an exception should be routed through
292
-
126
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
293
- if (s->ata) {
127
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
294
- gen_helper_stzgm_tags(cpu_env, addr, tcg_rt);
128
if (cpu_isar_feature(aa64_ssbs, cpu)) {
295
- }
129
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
296
- /*
130
}
297
- * The non-tags portion of STZGM is mostly like DC_ZVA,
131
+ if (cpu_isar_feature(any_ras, cpu)) {
298
- * except the alignment happens before the access.
132
+ define_arm_cp_regs(cpu, minimal_ras_reginfo);
299
- */
133
+ }
300
- clean_addr = clean_data_tbi(s, addr);
134
301
- tcg_gen_andi_i64(clean_addr, clean_addr, -size);
135
if (cpu_isar_feature(aa64_vh, cpu) ||
302
- gen_helper_dc_zva(cpu_env, clean_addr);
136
cpu_isar_feature(aa64_debugv8p2, cpu)) {
303
- } else if (s->ata) {
304
- if (is_load) {
305
- gen_helper_ldgm(tcg_rt, cpu_env, addr);
306
- } else {
307
- gen_helper_stgm(cpu_env, addr, tcg_rt);
308
- }
309
- } else {
310
- MMUAccessType acc = is_load ? MMU_DATA_LOAD : MMU_DATA_STORE;
311
- int size = 4 << GMID_EL1_BS;
312
-
313
- clean_addr = clean_data_tbi(s, addr);
314
- tcg_gen_andi_i64(clean_addr, clean_addr, -size);
315
- gen_probe_access(s, clean_addr, acc, size);
316
-
317
- if (is_load) {
318
- /* The result tags are zeros. */
319
- tcg_gen_movi_i64(tcg_rt, 0);
320
- }
321
+ if (a->w) {
322
+ /* pre-index or post-index */
323
+ if (a->p) {
324
+ /* post-index */
325
+ tcg_gen_addi_i64(addr, addr, a->imm);
326
}
327
- return;
328
+ tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr);
329
+ }
330
+ return true;
331
+}
332
+
333
+static bool do_STG(DisasContext *s, arg_ldst_tag *a, bool is_zero, bool is_pair)
334
+{
335
+ TCGv_i64 addr, tcg_rt;
336
+
337
+ if (a->rn == 31) {
338
+ gen_check_sp_alignment(s);
339
}
340
341
- if (is_load) {
342
- tcg_gen_andi_i64(addr, addr, -TAG_GRANULE);
343
- tcg_rt = cpu_reg(s, rt);
344
- if (s->ata) {
345
- gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt);
346
+ addr = read_cpu_reg_sp(s, a->rn, true);
347
+ if (!a->p) {
348
+ /* pre-index or signed offset */
349
+ tcg_gen_addi_i64(addr, addr, a->imm);
350
+ }
351
+ tcg_rt = cpu_reg_sp(s, a->rt);
352
+ if (!s->ata) {
353
+ /*
354
+ * For STG and ST2G, we need to check alignment and probe memory.
355
+ * TODO: For STZG and STZ2G, we could rely on the stores below,
356
+ * at least for system mode; user-only won't enforce alignment.
357
+ */
358
+ if (is_pair) {
359
+ gen_helper_st2g_stub(cpu_env, addr);
360
} else {
361
- /*
362
- * Tag access disabled: we must check for aborts on the load
363
- * load from [rn+offset], and then insert a 0 tag into rt.
364
- */
365
- clean_addr = clean_data_tbi(s, addr);
366
- gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8);
367
- gen_address_with_allocation_tag0(tcg_rt, tcg_rt);
368
+ gen_helper_stg_stub(cpu_env, addr);
369
+ }
370
+ } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
371
+ if (is_pair) {
372
+ gen_helper_st2g_parallel(cpu_env, addr, tcg_rt);
373
+ } else {
374
+ gen_helper_stg_parallel(cpu_env, addr, tcg_rt);
375
}
376
} else {
377
- tcg_rt = cpu_reg_sp(s, rt);
378
- if (!s->ata) {
379
- /*
380
- * For STG and ST2G, we need to check alignment and probe memory.
381
- * TODO: For STZG and STZ2G, we could rely on the stores below,
382
- * at least for system mode; user-only won't enforce alignment.
383
- */
384
- if (is_pair) {
385
- gen_helper_st2g_stub(cpu_env, addr);
386
- } else {
387
- gen_helper_stg_stub(cpu_env, addr);
388
- }
389
- } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
390
- if (is_pair) {
391
- gen_helper_st2g_parallel(cpu_env, addr, tcg_rt);
392
- } else {
393
- gen_helper_stg_parallel(cpu_env, addr, tcg_rt);
394
- }
395
+ if (is_pair) {
396
+ gen_helper_st2g(cpu_env, addr, tcg_rt);
397
} else {
398
- if (is_pair) {
399
- gen_helper_st2g(cpu_env, addr, tcg_rt);
400
- } else {
401
- gen_helper_stg(cpu_env, addr, tcg_rt);
402
- }
403
+ gen_helper_stg(cpu_env, addr, tcg_rt);
404
}
405
}
406
407
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
408
}
409
}
410
411
- if (index != 0) {
412
+ if (a->w) {
413
/* pre-index or post-index */
414
- if (index < 0) {
415
+ if (a->p) {
416
/* post-index */
417
- tcg_gen_addi_i64(addr, addr, offset);
418
+ tcg_gen_addi_i64(addr, addr, a->imm);
419
}
420
- tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr);
421
+ tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr);
422
}
423
+ return true;
424
}
425
426
-/* Loads and stores */
427
-static void disas_ldst(DisasContext *s, uint32_t insn)
428
-{
429
- switch (extract32(insn, 24, 6)) {
430
- case 0x19:
431
- if (extract32(insn, 21, 1) != 0) {
432
- disas_ldst_tag(s, insn);
433
- } else {
434
- unallocated_encoding(s);
435
- }
436
- break;
437
- default:
438
- unallocated_encoding(s);
439
- break;
440
- }
441
-}
442
+TRANS_FEAT(STG, aa64_mte_insn_reg, do_STG, a, false, false)
443
+TRANS_FEAT(STZG, aa64_mte_insn_reg, do_STG, a, true, false)
444
+TRANS_FEAT(ST2G, aa64_mte_insn_reg, do_STG, a, false, true)
445
+TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, true, true)
446
447
typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64);
448
449
@@ -XXX,XX +XXX,XX @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype)
450
static void disas_a64_legacy(DisasContext *s, uint32_t insn)
451
{
452
switch (extract32(insn, 25, 4)) {
453
- case 0x4:
454
- case 0x6:
455
- case 0xc:
456
- case 0xe: /* Loads and stores */
457
- disas_ldst(s, insn);
458
- break;
459
case 0x5:
460
case 0xd: /* Data processing - register */
461
disas_data_proc_reg(s, insn);
137
--
462
--
138
2.25.1
463
2.34.1
diff view generated by jsdifflib
[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
[PULL 24/33] hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner
2
A10 PIC model; however in the process we introduced a regression.
3
This is because the old code was robust against the incoming 'level'
4
argument being something other than 0 or 1, whereas the new code was
5
not.
2
6
3
This extension concerns cache speculation, which TCG does
7
In particular, the allwinner-sdhost code treats its IRQ line
4
not implement. Thus we can trivially enable this feature.
8
as 0-vs-non-0 rather than 0-vs-1, so when the SD controller
9
set its IRQ line for any reason other than transmit the
10
interrupt controller would ignore it. The observed effect
11
was a guest timeout when rebooting the guest kernel.
5
12
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Handle level values other than 0 or 1, to restore the old
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
behaviour.
8
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
15
16
Fixes: 2c5fa0778c3b430 ("hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()")
17
Cc: qemu-stable@nongnu.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
20
Tested-by: Guenter Roeck <linux@roeck-us.net>
21
Message-id: 20230606104609.3692557-2-peter.maydell@linaro.org
10
---
22
---
11
docs/system/arm/emulation.rst | 1 +
23
hw/intc/allwinner-a10-pic.c | 2 +-
12
target/arm/cpu64.c | 1 +
24
1 file changed, 1 insertion(+), 1 deletion(-)
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
15
25
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
26
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
17
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
28
--- a/hw/intc/allwinner-a10-pic.c
19
+++ b/docs/system/arm/emulation.rst
29
+++ b/hw/intc/allwinner-a10-pic.c
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
30
@@ -XXX,XX +XXX,XX @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
21
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
31
AwA10PICState *s = opaque;
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
32
uint32_t *pending_reg = &s->irq_pending[irq / 32];
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
33
24
+- FEAT_CSV3 (Cache speculation variant 3)
34
- *pending_reg = deposit32(*pending_reg, irq % 32, 1, level);
25
- FEAT_DIT (Data Independent Timing instructions)
35
+ *pending_reg = deposit32(*pending_reg, irq % 32, 1, !!level);
26
- FEAT_DPB (DC CVAP instruction)
36
aw_a10_pic_update(s);
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
37
}
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu64.c
31
+++ b/target/arm/cpu64.c
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
33
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
34
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
35
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
37
cpu->isar.id_aa64pfr0 = t;
38
39
t = cpu->isar.id_aa64pfr1;
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu_tcg.c
43
+++ b/target/arm/cpu_tcg.c
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
45
cpu->isar.id_pfr0 = t;
46
47
t = cpu->isar.id_pfr2;
48
+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
49
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
50
cpu->isar.id_pfr2 = t;
51
38
52
--
39
--
53
2.25.1
40
2.34.1
41
42
diff view generated by jsdifflib
[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
[PULL 25/33] hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
1
From: Richard Henderson <richard.henderson@linaro.org>
1
QEMU allows qemu_irq lines to transfer arbitrary integers. However
2
the convention is that for a simple IRQ line the values transferred
3
are always 0 and 1. The A10 SD controller device instead assumes a
4
0-vs-non-0 convention, which happens to work with the interrupt
5
controller it is wired up to.
2
6
3
Enable writes to the TERR and TEA bits when RAS is enabled.
7
Coerce the value to boolean to follow our usual convention.
4
These bits are otherwise RES0.
5
8
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Tested-by: Guenter Roeck <linux@roeck-us.net>
12
Message-id: 20230606104609.3692557-3-peter.maydell@linaro.org
10
---
13
---
11
target/arm/helper.c | 9 +++++++++
14
hw/sd/allwinner-sdhost.c | 2 +-
12
1 file changed, 9 insertions(+)
15
1 file changed, 1 insertion(+), 1 deletion(-)
13
16
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
19
--- a/hw/sd/allwinner-sdhost.c
17
+++ b/target/arm/helper.c
20
+++ b/hw/sd/allwinner-sdhost.c
18
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
21
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_update_irq(AwSdHostState *s)
19
}
20
valid_mask &= ~SCR_NET;
21
22
+ if (cpu_isar_feature(aa64_ras, cpu)) {
23
+ valid_mask |= SCR_TERR;
24
+ }
25
if (cpu_isar_feature(aa64_lor, cpu)) {
26
valid_mask |= SCR_TLOR;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
29
}
30
} else {
31
valid_mask &= ~(SCR_RW | SCR_ST);
32
+ if (cpu_isar_feature(aa32_ras, cpu)) {
33
+ valid_mask |= SCR_TERR;
34
+ }
35
}
22
}
36
23
37
if (!arm_feature(env, ARM_FEATURE_EL2)) {
24
trace_allwinner_sdhost_update_irq(irq);
38
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
25
- qemu_set_irq(s->irq, irq);
39
if (cpu_isar_feature(aa64_vh, cpu)) {
26
+ qemu_set_irq(s->irq, !!irq);
40
valid_mask |= HCR_E2H;
27
}
41
}
28
42
+ if (cpu_isar_feature(aa64_ras, cpu)) {
29
static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
43
+ valid_mask |= HCR_TERR | HCR_TEA;
44
+ }
45
if (cpu_isar_feature(aa64_lor, cpu)) {
46
valid_mask |= HCR_TLOR;
47
}
48
--
30
--
49
2.25.1
31
2.34.1
32
33
diff view generated by jsdifflib
[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
[PULL 26/33] hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The nrf51_timer has a free-running counter which we implement using
2
the pattern of using two fields (update_counter_ns, counter) to track
3
the last point at which we calculated the counter value, and the
4
counter value at that time. Then we can find the current counter
5
value by converting the difference in wall-clock time between then
6
and now to a tick count that we need to add to the counter value.
2
7
3
Instead of starting with cortex-a15 and adding v8 features to
8
Unfortunately the nrf51_timer's implementation of this has a bug
4
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
9
which means it loses time every time update_counter() is called.
5
This fixes the long-standing to-do where we only enabled v8
10
After updating s->counter it always sets s->update_counter_ns to
6
features for user-only.
11
'now', even though the actual point when s->counter hit the new value
12
will be some point in the past (half a tick, say). In the worst case
13
(guest code in a tight loop reading the counter, icount mode) the
14
counter is continually queried less than a tick after it was last
15
read, so s->counter never advances but s->update_counter_ns does, and
16
the guest never makes forward progress.
7
17
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
The fix for this is to only advance update_counter_ns to the
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
19
timestamp of the last tick, not all the way to 'now'. (This is the
10
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
20
pattern used in hw/misc/mps2-fpgaio.c's counter.)
21
22
Cc: qemu-stable@nongnu.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Joel Stanley <joel@jms.id.au>
25
Message-id: 20230606134917.3782215-1-peter.maydell@linaro.org
12
---
26
---
13
target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
27
hw/timer/nrf51_timer.c | 7 ++++++-
14
1 file changed, 92 insertions(+), 59 deletions(-)
28
1 file changed, 6 insertions(+), 1 deletion(-)
15
29
16
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
30
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
17
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu_tcg.c
32
--- a/hw/timer/nrf51_timer.c
19
+++ b/target/arm/cpu_tcg.c
33
+++ b/hw/timer/nrf51_timer.c
20
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
34
@@ -XXX,XX +XXX,XX @@ static uint32_t update_counter(NRF51TimerState *s, int64_t now)
21
static void arm_max_initfn(Object *obj)
35
uint32_t ticks = ns_to_ticks(s, now - s->update_counter_ns);
22
{
36
23
ARMCPU *cpu = ARM_CPU(obj);
37
s->counter = (s->counter + ticks) % BIT(bitwidths[s->bitmode]);
24
+ uint32_t t;
38
- s->update_counter_ns = now;
25
39
+ /*
26
- cortex_a15_initfn(obj);
40
+ * Only advance the sync time to the timestamp of the last tick,
27
+ /* aarch64_a57_initfn, advertising none of the aarch64 features */
41
+ * not all the way to 'now', so we don't lose time if we do
28
+ cpu->dtb_compatible = "arm,cortex-a57";
42
+ * multiple resyncs in a single tick.
29
+ set_feature(&cpu->env, ARM_FEATURE_V8);
43
+ */
30
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
44
+ s->update_counter_ns += ticks_to_ns(s, ticks);
31
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
45
return ticks;
32
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
33
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
34
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
35
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
36
+ cpu->midr = 0x411fd070;
37
+ cpu->revidr = 0x00000000;
38
+ cpu->reset_fpsid = 0x41034070;
39
+ cpu->isar.mvfr0 = 0x10110222;
40
+ cpu->isar.mvfr1 = 0x12111111;
41
+ cpu->isar.mvfr2 = 0x00000043;
42
+ cpu->ctr = 0x8444c004;
43
+ cpu->reset_sctlr = 0x00c50838;
44
+ cpu->isar.id_pfr0 = 0x00000131;
45
+ cpu->isar.id_pfr1 = 0x00011011;
46
+ cpu->isar.id_dfr0 = 0x03010066;
47
+ cpu->id_afr0 = 0x00000000;
48
+ cpu->isar.id_mmfr0 = 0x10101105;
49
+ cpu->isar.id_mmfr1 = 0x40000000;
50
+ cpu->isar.id_mmfr2 = 0x01260000;
51
+ cpu->isar.id_mmfr3 = 0x02102211;
52
+ cpu->isar.id_isar0 = 0x02101110;
53
+ cpu->isar.id_isar1 = 0x13112111;
54
+ cpu->isar.id_isar2 = 0x21232042;
55
+ cpu->isar.id_isar3 = 0x01112131;
56
+ cpu->isar.id_isar4 = 0x00011142;
57
+ cpu->isar.id_isar5 = 0x00011121;
58
+ cpu->isar.id_isar6 = 0;
59
+ cpu->isar.dbgdidr = 0x3516d000;
60
+ cpu->clidr = 0x0a200023;
61
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
62
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
63
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
64
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
65
66
- /* old-style VFP short-vector support */
67
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
68
+ /* Add additional features supported by QEMU */
69
+ t = cpu->isar.id_isar5;
70
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
71
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
72
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
73
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
74
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
75
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
76
+ cpu->isar.id_isar5 = t;
77
+
78
+ t = cpu->isar.id_isar6;
79
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
80
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
81
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
82
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
83
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
84
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
85
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
86
+ cpu->isar.id_isar6 = t;
87
+
88
+ t = cpu->isar.mvfr1;
89
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
90
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
91
+ cpu->isar.mvfr1 = t;
92
+
93
+ t = cpu->isar.mvfr2;
94
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
95
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
96
+ cpu->isar.mvfr2 = t;
97
+
98
+ t = cpu->isar.id_mmfr3;
99
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
100
+ cpu->isar.id_mmfr3 = t;
101
+
102
+ t = cpu->isar.id_mmfr4;
103
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
104
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
105
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
106
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
107
+ cpu->isar.id_mmfr4 = t;
108
+
109
+ t = cpu->isar.id_pfr0;
110
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
111
+ cpu->isar.id_pfr0 = t;
112
+
113
+ t = cpu->isar.id_pfr2;
114
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
115
+ cpu->isar.id_pfr2 = t;
116
117
#ifdef CONFIG_USER_ONLY
118
/*
119
- * We don't set these in system emulation mode for the moment,
120
- * since we don't correctly set (all of) the ID registers to
121
- * advertise them.
122
+ * Break with true ARMv8 and add back old-style VFP short-vector support.
123
+ * Only do this for user-mode, where -cpu max is the default, so that
124
+ * older v6 and v7 programs are more likely to work without adjustment.
125
*/
126
- set_feature(&cpu->env, ARM_FEATURE_V8);
127
- {
128
- uint32_t t;
129
-
130
- t = cpu->isar.id_isar5;
131
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
132
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
133
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
134
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
135
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
136
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
137
- cpu->isar.id_isar5 = t;
138
-
139
- t = cpu->isar.id_isar6;
140
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
141
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
142
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
143
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
144
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
145
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
146
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
147
- cpu->isar.id_isar6 = t;
148
-
149
- t = cpu->isar.mvfr1;
150
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
151
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
152
- cpu->isar.mvfr1 = t;
153
-
154
- t = cpu->isar.mvfr2;
155
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
156
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
157
- cpu->isar.mvfr2 = t;
158
-
159
- t = cpu->isar.id_mmfr3;
160
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
161
- cpu->isar.id_mmfr3 = t;
162
-
163
- t = cpu->isar.id_mmfr4;
164
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
165
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
166
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
167
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
168
- cpu->isar.id_mmfr4 = t;
169
-
170
- t = cpu->isar.id_pfr0;
171
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
172
- cpu->isar.id_pfr0 = t;
173
-
174
- t = cpu->isar.id_pfr2;
175
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
176
- cpu->isar.id_pfr2 = t;
177
- }
178
-#endif /* CONFIG_USER_ONLY */
179
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
180
+#endif
181
}
46
}
182
#endif /* !TARGET_AARCH64 */
183
47
184
--
48
--
185
2.25.1
49
2.34.1
diff view generated by jsdifflib
[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
[PULL 27/33] hw/arm/Kconfig: sbsa-ref uses Bochs display
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Thomas Huth <thuth@redhat.com>
5
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
5
Message-id: 20230607092112.655098-1-marcin.juszkiewicz@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
7
---
8
docs/system/arm/emulation.rst | 1 +
8
hw/arm/Kconfig | 1 +
9
target/arm/cpu64.c | 1 +
9
1 file changed, 1 insertion(+)
10
target/arm/cpu_tcg.c | 1 +
11
3 files changed, 3 insertions(+)
12
10
13
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
11
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/arm/emulation.rst
13
--- a/hw/arm/Kconfig
16
+++ b/docs/system/arm/emulation.rst
14
+++ b/hw/arm/Kconfig
17
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
15
@@ -XXX,XX +XXX,XX @@ config SBSA_REF
18
- FEAT_PMULL (PMULL, PMULL2 instructions)
16
select PL061 # GPIO
19
- FEAT_PMUv3p1 (PMU Extensions v3.1)
17
select USB_EHCI_SYSBUS
20
- FEAT_PMUv3p4 (PMU Extensions v3.4)
18
select WDT_SBSA
21
+- FEAT_RAS (Reliability, availability, and serviceability)
19
+ select BOCHS_DISPLAY
22
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
20
23
- FEAT_RNG (Random number generator)
21
config SABRELITE
24
- FEAT_SB (Speculation Barrier)
22
bool
25
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/cpu64.c
28
+++ b/target/arm/cpu64.c
29
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
30
t = cpu->isar.id_aa64pfr0;
31
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
32
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
33
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */
34
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
35
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
36
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
37
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu_tcg.c
40
+++ b/target/arm/cpu_tcg.c
41
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
42
43
t = cpu->isar.id_pfr0;
44
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
45
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
46
cpu->isar.id_pfr0 = t;
47
48
t = cpu->isar.id_pfr2;
49
--
23
--
50
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
[PULL 28/33] imx_serial: set wake bit when we receive a data byte
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Martin Kaiser <martin@kaiser.cx>
2
2
3
Update the legacy feature names to the current names.
3
The Linux kernel added a flood check for RX data recently in commit
4
Provide feature names for id changes that were not marked.
4
496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This
5
Sort the field updates into increasing bitfield order.
5
check uses the wake bit in the UART status register 2. The wake bit
6
indicates that the receiver detected a start bit on the RX line. If the
7
kernel sees a number of RX interrupts without the wake bit being set, it
8
treats this as spurious data and resets the UART port. imx_serial does
9
never set the wake bit and triggers the kernel's flood check.
6
10
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
This patch adds support for the wake bit. wake is set when we receive a
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
new character (it's not set for break events). It seems that wake is
9
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
13
cleared by the kernel driver, the hardware does not have to clear it
14
automatically after data was read.
15
16
The wake bit can be configured as an interrupt source. Support this
17
mechanism as well.
18
19
Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
21
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
22
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
24
---
12
target/arm/cpu64.c | 100 +++++++++++++++++++++----------------------
25
include/hw/char/imx_serial.h | 1 +
13
target/arm/cpu_tcg.c | 48 ++++++++++-----------
26
hw/char/imx_serial.c | 5 ++++-
14
2 files changed, 74 insertions(+), 74 deletions(-)
27
2 files changed, 5 insertions(+), 1 deletion(-)
15
28
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
29
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
17
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu64.c
31
--- a/include/hw/char/imx_serial.h
19
+++ b/target/arm/cpu64.c
32
+++ b/include/hw/char/imx_serial.h
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
33
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
21
cpu->midr = t;
34
22
35
#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
23
t = cpu->isar.id_aa64isar0;
36
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
24
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
37
+#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */
25
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
38
26
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
39
#define UTS1_TXEMPTY (1<<6)
27
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
40
#define UTS1_RXEMPTY (1<<5)
28
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
41
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
29
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
42
index XXXXXXX..XXXXXXX 100644
30
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
43
--- a/hw/char/imx_serial.c
31
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
44
+++ b/hw/char/imx_serial.c
32
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
45
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
33
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
46
* TCEN and TXDC are both bit 3
34
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
47
* RDR and DREN are both bit 0
35
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
36
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
37
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
38
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
39
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
40
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
41
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
42
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
43
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
44
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
45
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
46
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
47
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
48
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
49
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
50
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
51
cpu->isar.id_aa64isar0 = t;
52
53
t = cpu->isar.id_aa64isar1;
54
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
55
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
56
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
57
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
58
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
59
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
60
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
61
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
62
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
63
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
64
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
65
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
66
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
67
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
68
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
69
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
70
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
71
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
72
cpu->isar.id_aa64isar1 = t;
73
74
t = cpu->isar.id_aa64pfr0;
75
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
76
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
77
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
78
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
79
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
80
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
81
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
82
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
83
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
84
cpu->isar.id_aa64pfr0 = t;
85
86
t = cpu->isar.id_aa64pfr1;
87
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
88
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
89
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
90
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
91
/*
92
* Begin with full support for MTE. This will be downgraded to MTE=0
93
* during realize if the board provides no tag memory, much like
94
* we do for EL2 with the virtualization=on property.
95
*/
48
*/
96
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
49
- mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);
97
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
50
+ mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN);
98
cpu->isar.id_aa64pfr1 = t;
51
99
52
usr2 = s->usr2 & mask;
100
t = cpu->isar.id_aa64mmfr0;
53
101
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
54
@@ -XXX,XX +XXX,XX @@ static void imx_put_data(void *opaque, uint32_t value)
102
cpu->isar.id_aa64mmfr0 = t;
55
103
56
static void imx_receive(void *opaque, const uint8_t *buf, int size)
104
t = cpu->isar.id_aa64mmfr1;
57
{
105
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
58
+ IMXSerialState *s = (IMXSerialState *)opaque;
106
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
59
+
107
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
60
+ s->usr2 |= USR2_WAKE;
108
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
61
imx_put_data(opaque, *buf);
109
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
110
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
111
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
112
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
113
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
114
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
115
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
116
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
117
cpu->isar.id_aa64mmfr1 = t;
118
119
t = cpu->isar.id_aa64mmfr2;
120
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
121
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
122
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
123
- t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
124
- t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
125
- t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
126
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
127
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
128
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
129
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
130
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
131
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
132
cpu->isar.id_aa64mmfr2 = t;
133
134
t = cpu->isar.id_aa64zfr0;
135
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
136
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
137
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
138
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
139
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
140
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
141
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
142
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
143
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
144
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
145
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
146
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
147
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
148
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
149
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
150
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
151
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
152
cpu->isar.id_aa64zfr0 = t;
153
154
t = cpu->isar.id_aa64dfr0;
155
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
156
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
157
cpu->isar.id_aa64dfr0 = t;
158
159
/* Replicate the same data to the 32-bit id registers. */
160
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/arm/cpu_tcg.c
163
+++ b/target/arm/cpu_tcg.c
164
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
165
166
/* Add additional features supported by QEMU */
167
t = cpu->isar.id_isar5;
168
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
169
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
170
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
171
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
172
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
173
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
174
t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
175
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
176
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
177
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
178
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
179
cpu->isar.id_isar5 = t;
180
181
t = cpu->isar.id_isar6;
182
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
183
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
184
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
185
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
186
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
187
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
188
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
189
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
190
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
191
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
192
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
193
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
194
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
195
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
196
cpu->isar.id_isar6 = t;
197
198
t = cpu->isar.mvfr1;
199
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
200
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
201
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
202
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
203
cpu->isar.mvfr1 = t;
204
205
t = cpu->isar.mvfr2;
206
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
207
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
208
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
cpu->isar.mvfr2 = t;
211
212
t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
215
cpu->isar.id_mmfr3 = t;
216
217
t = cpu->isar.id_mmfr4;
218
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
219
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
220
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
221
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
222
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
223
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
224
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
225
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/
226
cpu->isar.id_mmfr4 = t;
227
228
t = cpu->isar.id_pfr0;
229
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
230
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
231
cpu->isar.id_pfr0 = t;
232
233
t = cpu->isar.id_pfr2;
234
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
235
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
236
cpu->isar.id_pfr2 = t;
237
238
t = cpu->isar.id_dfr0;
239
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
240
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
241
cpu->isar.id_dfr0 = t;
242
}
62
}
243
63
244
--
64
--
245
2.25.1
65
2.34.1
66
67
diff view generated by jsdifflib
[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
[PULL 29/33] docs: sbsa: document board to firmware interface
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
We set this for qemu-system-aarch64, but failed to do so
3
We plan to add more hardware information into DeviceTree to limit amount
4
for the strictly 32-bit emulation.
4
of hardcoded values in firmware.
5
5
6
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
7
Message-id: 20230531171834.236569-1-marcin.juszkiewicz@linaro.org
8
[PMM: fix format nits, add text about platform version fields from
9
a comment in the C source file]
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/cpu_tcg.c | 4 ++++
13
docs/system/arm/sbsa.rst | 38 +++++++++++++++++++++++++++++++-------
13
1 file changed, 4 insertions(+)
14
1 file changed, 31 insertions(+), 7 deletions(-)
14
15
15
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
16
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu_tcg.c
18
--- a/docs/system/arm/sbsa.rst
18
+++ b/target/arm/cpu_tcg.c
19
+++ b/docs/system/arm/sbsa.rst
19
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
20
@@ -XXX,XX +XXX,XX @@ any real hardware the ``sbsa-ref`` board intends to look like real
20
t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
21
hardware. The `Server Base System Architecture
21
cpu->isar.id_pfr2 = t;
22
<https://developer.arm.com/documentation/den0029/latest>`_ defines a
22
23
minimum base line of hardware support and importantly how the firmware
23
+ t = cpu->isar.id_dfr0;
24
-reports that to any operating system. It is a static system that
24
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
25
-reports a very minimal DT to the firmware for non-discoverable
25
+ cpu->isar.id_dfr0 = t;
26
-information about components affected by the qemu command line (i.e.
27
-cpus and memory). As a result it must have a firmware specifically
28
-built to expect a certain hardware layout (as you would in a real
29
-machine).
30
+reports that to any operating system.
31
32
It is intended to be a machine for developing firmware and testing
33
standards compliance with operating systems.
34
@@ -XXX,XX +XXX,XX @@ standards compliance with operating systems.
35
Supported devices
36
"""""""""""""""""
37
38
-The sbsa-ref board supports:
39
+The ``sbsa-ref`` board supports:
40
41
- A configurable number of AArch64 CPUs
42
- GIC version 3
43
@@ -XXX,XX +XXX,XX @@ The sbsa-ref board supports:
44
- Bochs display adapter on PCIe bus
45
- A generic SBSA watchdog device
46
26
+
47
+
27
#ifdef CONFIG_USER_ONLY
48
+Board to firmware interface
28
/*
49
+"""""""""""""""""""""""""""
29
* Break with true ARMv8 and add back old-style VFP short-vector support.
50
+
51
+``sbsa-ref`` is a static system that reports a very minimal devicetree to the
52
+firmware for non-discoverable information about system components. This
53
+includes both internal hardware and parts affected by the qemu command line
54
+(i.e. CPUs and memory). As a result it must have a firmware specifically built
55
+to expect a certain hardware layout (as you would in a real machine).
56
+
57
+DeviceTree information
58
+''''''''''''''''''''''
59
+
60
+The devicetree provided by the board model to the firmware is not intended
61
+to be a complete compliant DT. It currently reports:
62
+
63
+ - CPUs
64
+ - memory
65
+ - platform version
66
+ - GIC addresses
67
+
68
+The platform version is only for informing platform firmware about
69
+what kind of ``sbsa-ref`` board it is running on. It is neither
70
+a QEMU versioned machine type nor a reflection of the level of the
71
+SBSA/SystemReady SR support provided.
72
+
73
+The ``machine-version-major`` value is updated when changes breaking
74
+fw compatibility are introduced. The ``machine-version-minor`` value
75
+is updated when features are added that don't break fw compatibility.
30
--
76
--
31
2.25.1
77
2.34.1
diff view generated by jsdifflib
[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
[PULL 30/33] hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h'
1
From: Gavin Shan <gshan@redhat.com>
1
From: Sergey Kambalin <sergey.kambalin@auriga.com>
2
2
3
The CPU topology isn't enabled on arm/virt machine yet, but we're
3
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
4
going to do it in next patch. After the CPU topology is enabled by
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
next patch, "thread-id=1" becomes invalid because the CPU core is
5
Acked-by: Richard Henderson <richard.henderson@linaro.org>
6
preferred on arm/virt machine. It means these two CPUs have 0/1
6
Message-id: 20230612223456.33824-2-philmd@linaro.org
7
as their core IDs, but their thread IDs are all 0. It will trigger
7
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
8
test failure as the following message indicates:
8
[PMD: Split from bigger patch: 1/4]
9
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR
11
1.48s killed by signal 6 SIGABRT
12
>>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
13
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \
14
QTEST_QEMU_BINARY=./qemu-system-aarch64 \
15
QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \
16
/home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
17
――――――――――――――――――――――――――――――――――――――――――――――
18
stderr:
19
qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
20
21
This fixes the issue by providing comprehensive SMP configurations
22
in aarch64_numa_cpu(). The SMP configurations aren't used before
23
the CPU topology is enabled in next patch.
24
25
Signed-off-by: Gavin Shan <gshan@redhat.com>
26
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
27
Message-id: 20220503140304.855514-3-gshan@redhat.com
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
---
11
---
30
tests/qtest/numa-test.c | 3 ++-
12
include/hw/misc/raspberrypi-fw-defs.h | 163 ++++++++++++++++++++++++++
31
1 file changed, 2 insertions(+), 1 deletion(-)
13
1 file changed, 163 insertions(+)
14
create mode 100644 include/hw/misc/raspberrypi-fw-defs.h
32
15
33
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
16
diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/misc/raspberrypi-fw-defs.h
34
index XXXXXXX..XXXXXXX 100644
17
new file mode 100644
35
--- a/tests/qtest/numa-test.c
18
index XXXXXXX..XXXXXXX
36
+++ b/tests/qtest/numa-test.c
19
--- /dev/null
37
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
20
+++ b/include/hw/misc/raspberrypi-fw-defs.h
38
QTestState *qts;
21
@@ -XXX,XX +XXX,XX @@
39
g_autofree char *cli = NULL;
22
+/*
40
23
+ * Raspberry Pi firmware definitions
41
- cli = make_cli(data, "-machine smp.cpus=2 "
24
+ *
42
+ cli = make_cli(data, "-machine "
25
+ * Copyright (C) 2022 Auriga LLC, based on Linux kernel
43
+ "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
26
+ * `include/soc/bcm2835/raspberrypi-firmware.h` (Copyright © 2015 Broadcom)
44
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
27
+ *
45
"-numa cpu,node-id=1,thread-id=0 "
28
+ * SPDX-License-Identifier: GPL-2.0-or-later
46
"-numa cpu,node-id=0,thread-id=1");
29
+ */
30
+
31
+#ifndef INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_
32
+#define INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_
33
+
34
+#include "qemu/osdep.h"
35
+
36
+enum rpi_firmware_property_tag {
37
+ RPI_FWREQ_PROPERTY_END = 0,
38
+ RPI_FWREQ_GET_FIRMWARE_REVISION = 0x00000001,
39
+ RPI_FWREQ_GET_FIRMWARE_VARIANT = 0x00000002,
40
+ RPI_FWREQ_GET_FIRMWARE_HASH = 0x00000003,
41
+
42
+ RPI_FWREQ_SET_CURSOR_INFO = 0x00008010,
43
+ RPI_FWREQ_SET_CURSOR_STATE = 0x00008011,
44
+
45
+ RPI_FWREQ_GET_BOARD_MODEL = 0x00010001,
46
+ RPI_FWREQ_GET_BOARD_REVISION = 0x00010002,
47
+ RPI_FWREQ_GET_BOARD_MAC_ADDRESS = 0x00010003,
48
+ RPI_FWREQ_GET_BOARD_SERIAL = 0x00010004,
49
+ RPI_FWREQ_GET_ARM_MEMORY = 0x00010005,
50
+ RPI_FWREQ_GET_VC_MEMORY = 0x00010006,
51
+ RPI_FWREQ_GET_CLOCKS = 0x00010007,
52
+ RPI_FWREQ_GET_POWER_STATE = 0x00020001,
53
+ RPI_FWREQ_GET_TIMING = 0x00020002,
54
+ RPI_FWREQ_SET_POWER_STATE = 0x00028001,
55
+ RPI_FWREQ_GET_CLOCK_STATE = 0x00030001,
56
+ RPI_FWREQ_GET_CLOCK_RATE = 0x00030002,
57
+ RPI_FWREQ_GET_VOLTAGE = 0x00030003,
58
+ RPI_FWREQ_GET_MAX_CLOCK_RATE = 0x00030004,
59
+ RPI_FWREQ_GET_MAX_VOLTAGE = 0x00030005,
60
+ RPI_FWREQ_GET_TEMPERATURE = 0x00030006,
61
+ RPI_FWREQ_GET_MIN_CLOCK_RATE = 0x00030007,
62
+ RPI_FWREQ_GET_MIN_VOLTAGE = 0x00030008,
63
+ RPI_FWREQ_GET_TURBO = 0x00030009,
64
+ RPI_FWREQ_GET_MAX_TEMPERATURE = 0x0003000a,
65
+ RPI_FWREQ_GET_STC = 0x0003000b,
66
+ RPI_FWREQ_ALLOCATE_MEMORY = 0x0003000c,
67
+ RPI_FWREQ_LOCK_MEMORY = 0x0003000d,
68
+ RPI_FWREQ_UNLOCK_MEMORY = 0x0003000e,
69
+ RPI_FWREQ_RELEASE_MEMORY = 0x0003000f,
70
+ RPI_FWREQ_EXECUTE_CODE = 0x00030010,
71
+ RPI_FWREQ_EXECUTE_QPU = 0x00030011,
72
+ RPI_FWREQ_SET_ENABLE_QPU = 0x00030012,
73
+ RPI_FWREQ_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014,
74
+ RPI_FWREQ_GET_EDID_BLOCK = 0x00030020,
75
+ RPI_FWREQ_GET_CUSTOMER_OTP = 0x00030021,
76
+ RPI_FWREQ_GET_EDID_BLOCK_DISPLAY = 0x00030023,
77
+ RPI_FWREQ_GET_DOMAIN_STATE = 0x00030030,
78
+ RPI_FWREQ_GET_THROTTLED = 0x00030046,
79
+ RPI_FWREQ_GET_CLOCK_MEASURED = 0x00030047,
80
+ RPI_FWREQ_NOTIFY_REBOOT = 0x00030048,
81
+ RPI_FWREQ_SET_CLOCK_STATE = 0x00038001,
82
+ RPI_FWREQ_SET_CLOCK_RATE = 0x00038002,
83
+ RPI_FWREQ_SET_VOLTAGE = 0x00038003,
84
+ RPI_FWREQ_SET_MAX_CLOCK_RATE = 0x00038004,
85
+ RPI_FWREQ_SET_MIN_CLOCK_RATE = 0x00038007,
86
+ RPI_FWREQ_SET_TURBO = 0x00038009,
87
+ RPI_FWREQ_SET_CUSTOMER_OTP = 0x00038021,
88
+ RPI_FWREQ_SET_DOMAIN_STATE = 0x00038030,
89
+ RPI_FWREQ_GET_GPIO_STATE = 0x00030041,
90
+ RPI_FWREQ_SET_GPIO_STATE = 0x00038041,
91
+ RPI_FWREQ_SET_SDHOST_CLOCK = 0x00038042,
92
+ RPI_FWREQ_GET_GPIO_CONFIG = 0x00030043,
93
+ RPI_FWREQ_SET_GPIO_CONFIG = 0x00038043,
94
+ RPI_FWREQ_GET_PERIPH_REG = 0x00030045,
95
+ RPI_FWREQ_SET_PERIPH_REG = 0x00038045,
96
+ RPI_FWREQ_GET_POE_HAT_VAL = 0x00030049,
97
+ RPI_FWREQ_SET_POE_HAT_VAL = 0x00038049,
98
+ RPI_FWREQ_SET_POE_HAT_VAL_OLD = 0x00030050,
99
+ RPI_FWREQ_NOTIFY_XHCI_RESET = 0x00030058,
100
+ RPI_FWREQ_GET_REBOOT_FLAGS = 0x00030064,
101
+ RPI_FWREQ_SET_REBOOT_FLAGS = 0x00038064,
102
+ RPI_FWREQ_NOTIFY_DISPLAY_DONE = 0x00030066,
103
+
104
+ /* Dispmanx TAGS */
105
+ RPI_FWREQ_FRAMEBUFFER_ALLOCATE = 0x00040001,
106
+ RPI_FWREQ_FRAMEBUFFER_BLANK = 0x00040002,
107
+ RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
108
+ RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
109
+ RPI_FWREQ_FRAMEBUFFER_GET_DEPTH = 0x00040005,
110
+ RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER = 0x00040006,
111
+ RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE = 0x00040007,
112
+ RPI_FWREQ_FRAMEBUFFER_GET_PITCH = 0x00040008,
113
+ RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 0x00040009,
114
+ RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN = 0x0004000a,
115
+ RPI_FWREQ_FRAMEBUFFER_GET_PALETTE = 0x0004000b,
116
+ RPI_FWREQ_FRAMEBUFFER_GET_LAYER = 0x0004000c,
117
+ RPI_FWREQ_FRAMEBUFFER_GET_TRANSFORM = 0x0004000d,
118
+ RPI_FWREQ_FRAMEBUFFER_GET_VSYNC = 0x0004000e,
119
+ RPI_FWREQ_FRAMEBUFFER_GET_TOUCHBUF = 0x0004000f,
120
+ RPI_FWREQ_FRAMEBUFFER_GET_GPIOVIRTBUF = 0x00040010,
121
+ RPI_FWREQ_FRAMEBUFFER_RELEASE = 0x00048001,
122
+ RPI_FWREQ_FRAMEBUFFER_GET_DISPLAY_ID = 0x00040016,
123
+ RPI_FWREQ_FRAMEBUFFER_SET_DISPLAY_NUM = 0x00048013,
124
+ RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS = 0x00040013,
125
+ RPI_FWREQ_FRAMEBUFFER_GET_DISPLAY_SETTINGS = 0x00040014,
126
+ RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
127
+ RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
128
+ RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH = 0x00044005,
129
+ RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER = 0x00044006,
130
+ RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE = 0x00044007,
131
+ RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 0x00044009,
132
+ RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN = 0x0004400a,
133
+ RPI_FWREQ_FRAMEBUFFER_TEST_PALETTE = 0x0004400b,
134
+ RPI_FWREQ_FRAMEBUFFER_TEST_LAYER = 0x0004400c,
135
+ RPI_FWREQ_FRAMEBUFFER_TEST_TRANSFORM = 0x0004400d,
136
+ RPI_FWREQ_FRAMEBUFFER_TEST_VSYNC = 0x0004400e,
137
+ RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
138
+ RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
139
+ RPI_FWREQ_FRAMEBUFFER_SET_DEPTH = 0x00048005,
140
+ RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER = 0x00048006,
141
+ RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE = 0x00048007,
142
+ RPI_FWREQ_FRAMEBUFFER_SET_PITCH = 0x00048008,
143
+ RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 0x00048009,
144
+ RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a,
145
+ RPI_FWREQ_FRAMEBUFFER_SET_PALETTE = 0x0004800b,
146
+
147
+ RPI_FWREQ_FRAMEBUFFER_SET_TOUCHBUF = 0x0004801f,
148
+ RPI_FWREQ_FRAMEBUFFER_SET_GPIOVIRTBUF = 0x00048020,
149
+ RPI_FWREQ_FRAMEBUFFER_SET_VSYNC = 0x0004800e,
150
+ RPI_FWREQ_FRAMEBUFFER_SET_LAYER = 0x0004800c,
151
+ RPI_FWREQ_FRAMEBUFFER_SET_TRANSFORM = 0x0004800d,
152
+ RPI_FWREQ_FRAMEBUFFER_SET_BACKLIGHT = 0x0004800f,
153
+
154
+ RPI_FWREQ_VCHIQ_INIT = 0x00048010,
155
+
156
+ RPI_FWREQ_SET_PLANE = 0x00048015,
157
+ RPI_FWREQ_GET_DISPLAY_TIMING = 0x00040017,
158
+ RPI_FWREQ_SET_TIMING = 0x00048017,
159
+ RPI_FWREQ_GET_DISPLAY_CFG = 0x00040018,
160
+ RPI_FWREQ_SET_DISPLAY_POWER = 0x00048019,
161
+ RPI_FWREQ_GET_COMMAND_LINE = 0x00050001,
162
+ RPI_FWREQ_GET_DMA_CHANNELS = 0x00060001,
163
+};
164
+
165
+enum rpi_firmware_clk_id {
166
+ RPI_FIRMWARE_EMMC_CLK_ID = 1,
167
+ RPI_FIRMWARE_UART_CLK_ID,
168
+ RPI_FIRMWARE_ARM_CLK_ID,
169
+ RPI_FIRMWARE_CORE_CLK_ID,
170
+ RPI_FIRMWARE_V3D_CLK_ID,
171
+ RPI_FIRMWARE_H264_CLK_ID,
172
+ RPI_FIRMWARE_ISP_CLK_ID,
173
+ RPI_FIRMWARE_SDRAM_CLK_ID,
174
+ RPI_FIRMWARE_PIXEL_CLK_ID,
175
+ RPI_FIRMWARE_PWM_CLK_ID,
176
+ RPI_FIRMWARE_HEVC_CLK_ID,
177
+ RPI_FIRMWARE_EMMC2_CLK_ID,
178
+ RPI_FIRMWARE_M2MC_CLK_ID,
179
+ RPI_FIRMWARE_PIXEL_BVB_CLK_ID,
180
+ RPI_FIRMWARE_VEC_CLK_ID,
181
+ RPI_FIRMWARE_NUM_CLK_ID,
182
+};
183
+
184
+#endif /* INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_ */
47
--
185
--
48
2.25.1
186
2.34.1
49
187
50
188
diff view generated by jsdifflib
[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
[PULL 31/33] hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitions
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Sergey Kambalin <sergey.kambalin@auriga.com>
2
2
3
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
3
Replace magic property values by a proper definition,
4
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
4
removing redundant comments.
5
while registering for v8.
5
6
6
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
7
This is a behavior change for v7 cpus with Security Extensions and
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
without Virtualization Extensions, in that the virtualization cpregs
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
are now correctly not present. This would be a migration compatibility
9
Message-id: 20230612223456.33824-3-philmd@linaro.org
10
break, except that we have an existing bug in which migration of 32-bit
10
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
11
cpus with Security Extensions enabled does not work.
11
[PMD: Split from bigger patch: 2/4]
12
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
14
---
18
target/arm/helper.c | 158 ++++----------------------------------------
15
hw/misc/bcm2835_property.c | 101 +++++++++++++++++++------------------
19
1 file changed, 13 insertions(+), 145 deletions(-)
16
1 file changed, 51 insertions(+), 50 deletions(-)
20
17
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
22
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
20
--- a/hw/misc/bcm2835_property.c
24
+++ b/target/arm/helper.c
21
+++ b/hw/misc/bcm2835_property.c
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
22
@@ -XXX,XX +XXX,XX @@
26
.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
23
#include "migration/vmstate.h"
27
};
24
#include "hw/irq.h"
28
25
#include "hw/misc/bcm2835_mbox_defs.h"
29
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
26
+#include "hw/misc/raspberrypi-fw-defs.h"
30
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
27
#include "sysemu/dma.h"
31
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
28
#include "qemu/log.h"
32
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
29
#include "qemu/module.h"
33
- .access = PL2_RW,
30
@@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
34
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
31
/* @(value + 8) : Request/response indicator */
35
- { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
32
resplen = 0;
36
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
33
switch (tag) {
37
- .access = PL2_RW,
34
- case 0x00000000: /* End tag */
38
- .type = ARM_CP_CONST, .resetvalue = 0 },
35
+ case RPI_FWREQ_PROPERTY_END:
39
- { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
36
break;
40
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
37
- case 0x00000001: /* Get firmware revision */
41
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
38
+ case RPI_FWREQ_GET_FIRMWARE_REVISION:
42
- { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
39
stl_le_phys(&s->dma_as, value + 12, 346337);
43
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
40
resplen = 4;
44
- .access = PL2_RW,
41
break;
45
- .type = ARM_CP_CONST, .resetvalue = 0 },
42
- case 0x00010001: /* Get board model */
46
- { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
43
+ case RPI_FWREQ_GET_BOARD_MODEL:
47
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
44
qemu_log_mask(LOG_UNIMP,
48
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
"bcm2835_property: 0x%08x get board model NYI\n",
49
- { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
46
tag);
50
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
47
resplen = 4;
51
- .access = PL2_RW, .type = ARM_CP_CONST,
48
break;
52
- .resetvalue = 0 },
49
- case 0x00010002: /* Get board revision */
53
- { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
50
+ case RPI_FWREQ_GET_BOARD_REVISION:
54
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
51
stl_le_phys(&s->dma_as, value + 12, s->board_rev);
55
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
52
resplen = 4;
56
- { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
53
break;
57
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
54
- case 0x00010003: /* Get board MAC address */
58
- .access = PL2_RW, .type = ARM_CP_CONST,
55
+ case RPI_FWREQ_GET_BOARD_MAC_ADDRESS:
59
- .resetvalue = 0 },
56
resplen = sizeof(s->macaddr.a);
60
- { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
57
dma_memory_write(&s->dma_as, value + 12, s->macaddr.a, resplen,
61
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
58
MEMTXATTRS_UNSPECIFIED);
62
- .access = PL2_RW, .type = ARM_CP_CONST,
59
break;
63
- .resetvalue = 0 },
60
- case 0x00010004: /* Get board serial */
64
- { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
61
+ case RPI_FWREQ_GET_BOARD_SERIAL:
65
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
62
qemu_log_mask(LOG_UNIMP,
66
- .access = PL2_RW, .type = ARM_CP_CONST,
63
"bcm2835_property: 0x%08x get board serial NYI\n",
67
- .resetvalue = 0 },
64
tag);
68
- { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
65
resplen = 8;
69
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
66
break;
70
- .access = PL2_RW, .type = ARM_CP_CONST,
67
- case 0x00010005: /* Get ARM memory */
71
- .resetvalue = 0 },
68
+ case RPI_FWREQ_GET_ARM_MEMORY:
72
- { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
69
/* base */
73
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
70
stl_le_phys(&s->dma_as, value + 12, 0);
74
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
71
/* size */
75
- { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
72
stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_base);
76
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
73
resplen = 8;
77
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
74
break;
78
- .type = ARM_CP_CONST, .resetvalue = 0 },
75
- case 0x00010006: /* Get VC memory */
79
- { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
76
+ case RPI_FWREQ_GET_VC_MEMORY:
80
- .cp = 15, .opc1 = 6, .crm = 2,
77
/* base */
81
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
78
stl_le_phys(&s->dma_as, value + 12, s->fbdev->vcram_base);
82
- .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
79
/* size */
83
- { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
80
stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_size);
84
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
81
resplen = 8;
85
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
82
break;
86
- { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
83
- case 0x00028001: /* Set power state */
87
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
84
+ case RPI_FWREQ_SET_POWER_STATE:
88
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
85
/* Assume that whatever device they asked for exists,
89
- { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
86
* and we'll just claim we set it to the desired state
90
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
87
*/
91
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
92
- { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
89
93
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
90
/* Clocks */
94
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
91
95
- { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
92
- case 0x00030001: /* Get clock state */
96
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
93
+ case RPI_FWREQ_GET_CLOCK_STATE:
97
- .resetvalue = 0 },
94
stl_le_phys(&s->dma_as, value + 16, 0x1);
98
- { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
95
resplen = 8;
99
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
96
break;
100
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
97
101
- { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
98
- case 0x00038001: /* Set clock state */
102
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
99
+ case RPI_FWREQ_SET_CLOCK_STATE:
103
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
100
qemu_log_mask(LOG_UNIMP,
104
- { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
101
"bcm2835_property: 0x%08x set clock state NYI\n",
105
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
102
tag);
106
- .resetvalue = 0 },
103
resplen = 8;
107
- { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
104
break;
108
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
105
109
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
106
- case 0x00030002: /* Get clock rate */
110
- { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
107
- case 0x00030004: /* Get max clock rate */
111
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
108
- case 0x00030007: /* Get min clock rate */
112
- .resetvalue = 0 },
109
+ case RPI_FWREQ_GET_CLOCK_RATE:
113
- { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
110
+ case RPI_FWREQ_GET_MAX_CLOCK_RATE:
114
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
111
+ case RPI_FWREQ_GET_MIN_CLOCK_RATE:
115
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
112
switch (ldl_le_phys(&s->dma_as, value + 12)) {
116
- { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
113
- case 1: /* EMMC */
117
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
114
+ case RPI_FIRMWARE_EMMC_CLK_ID:
118
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
115
stl_le_phys(&s->dma_as, value + 16, 50000000);
119
- { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
116
break;
120
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
117
- case 2: /* UART */
121
- .access = PL2_RW, .accessfn = access_tda,
118
+ case RPI_FIRMWARE_UART_CLK_ID:
122
- .type = ARM_CP_CONST, .resetvalue = 0 },
119
stl_le_phys(&s->dma_as, value + 16, 3000000);
123
- { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
120
break;
124
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
121
default:
125
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
122
@@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
126
- .type = ARM_CP_CONST, .resetvalue = 0 },
123
resplen = 8;
127
- { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
124
break;
128
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
125
129
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
126
- case 0x00038002: /* Set clock rate */
130
- { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
127
- case 0x00038004: /* Set max clock rate */
131
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
128
- case 0x00038007: /* Set min clock rate */
132
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
129
+ case RPI_FWREQ_SET_CLOCK_RATE:
133
- { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
130
+ case RPI_FWREQ_SET_MAX_CLOCK_RATE:
134
- .type = ARM_CP_CONST,
131
+ case RPI_FWREQ_SET_MIN_CLOCK_RATE:
135
- .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
132
qemu_log_mask(LOG_UNIMP,
136
- .access = PL2_RW, .resetvalue = 0 },
133
"bcm2835_property: 0x%08x set clock rate NYI\n",
137
-};
134
tag);
138
-
135
@@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
139
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
136
140
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
137
/* Temperature */
141
- { .name = "HCR2", .state = ARM_CP_STATE_AA32,
138
142
- .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
139
- case 0x00030006: /* Get temperature */
143
- .access = PL2_RW,
140
+ case RPI_FWREQ_GET_TEMPERATURE:
144
- .type = ARM_CP_CONST, .resetvalue = 0 },
141
stl_le_phys(&s->dma_as, value + 16, 25000);
145
-};
142
resplen = 8;
146
-
143
break;
147
static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
144
148
{
145
- case 0x0003000A: /* Get max temperature */
149
ARMCPU *cpu = env_archcpu(env);
146
+ case RPI_FWREQ_GET_MAX_TEMPERATURE:
150
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
147
stl_le_phys(&s->dma_as, value + 16, 99000);
151
define_arm_cp_regs(cpu, v8_idregs);
148
resplen = 8;
152
define_arm_cp_regs(cpu, v8_cp_reginfo);
149
break;
153
}
150
154
- if (arm_feature(env, ARM_FEATURE_EL2)) {
151
/* Frame buffer */
155
+
152
156
+ /*
153
- case 0x00040001: /* Allocate buffer */
157
+ * Register the base EL2 cpregs.
154
+ case RPI_FWREQ_FRAMEBUFFER_ALLOCATE:
158
+ * Pre v8, these registers are implemented only as part of the
155
stl_le_phys(&s->dma_as, value + 12, fbconfig.base);
159
+ * Virtualization Extensions (EL2 present). Beginning with v8,
156
stl_le_phys(&s->dma_as, value + 16,
160
+ * if EL2 is missing but EL3 is enabled, mostly these become
157
bcm2835_fb_get_size(&fbconfig));
161
+ * RES0 from EL3, with some specific exceptions.
158
resplen = 8;
162
+ */
159
break;
163
+ if (arm_feature(env, ARM_FEATURE_EL2)
160
- case 0x00048001: /* Release buffer */
164
+ || (arm_feature(env, ARM_FEATURE_EL3)
161
+ case RPI_FWREQ_FRAMEBUFFER_RELEASE:
165
+ && arm_feature(env, ARM_FEATURE_V8))) {
162
resplen = 0;
166
uint64_t vmpidr_def = mpidr_read_val(env);
163
break;
167
ARMCPRegInfo vpidr_regs[] = {
164
- case 0x00040002: /* Blank screen */
168
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
165
+ case RPI_FWREQ_FRAMEBUFFER_BLANK:
169
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
166
resplen = 4;
170
};
167
break;
171
define_one_arm_cp_reg(cpu, &rvbar);
168
- case 0x00044003: /* Test physical display width/height */
172
}
169
- case 0x00044004: /* Test virtual display width/height */
173
- } else {
170
+ case RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT:
174
- /* If EL2 is missing but higher ELs are enabled, we need to
171
+ case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT:
175
- * register the no_el2 reginfos.
172
resplen = 8;
176
- */
173
break;
177
- if (arm_feature(env, ARM_FEATURE_EL3)) {
174
- case 0x00048003: /* Set physical display width/height */
178
- /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
175
+ case RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT:
179
- * of MIDR_EL1 and MPIDR_EL1.
176
fbconfig.xres = ldl_le_phys(&s->dma_as, value + 12);
180
- */
177
fbconfig.yres = ldl_le_phys(&s->dma_as, value + 16);
181
- ARMCPRegInfo vpidr_regs[] = {
178
bcm2835_fb_validate_config(&fbconfig);
182
- { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
179
fbconfig_updated = true;
183
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
180
/* fall through */
184
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
181
- case 0x00040003: /* Get physical display width/height */
185
- .type = ARM_CP_CONST, .resetvalue = cpu->midr,
182
+ case RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT:
186
- .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
183
stl_le_phys(&s->dma_as, value + 12, fbconfig.xres);
187
- { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
184
stl_le_phys(&s->dma_as, value + 16, fbconfig.yres);
188
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
185
resplen = 8;
189
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
186
break;
190
- .type = ARM_CP_NO_RAW,
187
- case 0x00048004: /* Set virtual display width/height */
191
- .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
188
+ case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT:
192
- };
189
fbconfig.xres_virtual = ldl_le_phys(&s->dma_as, value + 12);
193
- define_arm_cp_regs(cpu, vpidr_regs);
190
fbconfig.yres_virtual = ldl_le_phys(&s->dma_as, value + 16);
194
- define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
191
bcm2835_fb_validate_config(&fbconfig);
195
- if (arm_feature(env, ARM_FEATURE_V8)) {
192
fbconfig_updated = true;
196
- define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
193
/* fall through */
197
- }
194
- case 0x00040004: /* Get virtual display width/height */
198
- }
195
+ case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT:
199
}
196
stl_le_phys(&s->dma_as, value + 12, fbconfig.xres_virtual);
200
+
197
stl_le_phys(&s->dma_as, value + 16, fbconfig.yres_virtual);
201
+ /* Register the base EL3 cpregs. */
198
resplen = 8;
202
if (arm_feature(env, ARM_FEATURE_EL3)) {
199
break;
203
define_arm_cp_regs(cpu, el3_cp_reginfo);
200
- case 0x00044005: /* Test depth */
204
ARMCPRegInfo el3_regs[] = {
201
+ case RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH:
202
resplen = 4;
203
break;
204
- case 0x00048005: /* Set depth */
205
+ case RPI_FWREQ_FRAMEBUFFER_SET_DEPTH:
206
fbconfig.bpp = ldl_le_phys(&s->dma_as, value + 12);
207
bcm2835_fb_validate_config(&fbconfig);
208
fbconfig_updated = true;
209
/* fall through */
210
- case 0x00040005: /* Get depth */
211
+ case RPI_FWREQ_FRAMEBUFFER_GET_DEPTH:
212
stl_le_phys(&s->dma_as, value + 12, fbconfig.bpp);
213
resplen = 4;
214
break;
215
- case 0x00044006: /* Test pixel order */
216
+ case RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER:
217
resplen = 4;
218
break;
219
- case 0x00048006: /* Set pixel order */
220
+ case RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER:
221
fbconfig.pixo = ldl_le_phys(&s->dma_as, value + 12);
222
bcm2835_fb_validate_config(&fbconfig);
223
fbconfig_updated = true;
224
/* fall through */
225
- case 0x00040006: /* Get pixel order */
226
+ case RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER:
227
stl_le_phys(&s->dma_as, value + 12, fbconfig.pixo);
228
resplen = 4;
229
break;
230
- case 0x00044007: /* Test pixel alpha */
231
+ case RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE:
232
resplen = 4;
233
break;
234
- case 0x00048007: /* Set alpha */
235
+ case RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE:
236
fbconfig.alpha = ldl_le_phys(&s->dma_as, value + 12);
237
bcm2835_fb_validate_config(&fbconfig);
238
fbconfig_updated = true;
239
/* fall through */
240
- case 0x00040007: /* Get alpha */
241
+ case RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE:
242
stl_le_phys(&s->dma_as, value + 12, fbconfig.alpha);
243
resplen = 4;
244
break;
245
- case 0x00040008: /* Get pitch */
246
+ case RPI_FWREQ_FRAMEBUFFER_GET_PITCH:
247
stl_le_phys(&s->dma_as, value + 12,
248
bcm2835_fb_get_pitch(&fbconfig));
249
resplen = 4;
250
break;
251
- case 0x00044009: /* Test virtual offset */
252
+ case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET:
253
resplen = 8;
254
break;
255
- case 0x00048009: /* Set virtual offset */
256
+ case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET:
257
fbconfig.xoffset = ldl_le_phys(&s->dma_as, value + 12);
258
fbconfig.yoffset = ldl_le_phys(&s->dma_as, value + 16);
259
bcm2835_fb_validate_config(&fbconfig);
260
fbconfig_updated = true;
261
/* fall through */
262
- case 0x00040009: /* Get virtual offset */
263
+ case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET:
264
stl_le_phys(&s->dma_as, value + 12, fbconfig.xoffset);
265
stl_le_phys(&s->dma_as, value + 16, fbconfig.yoffset);
266
resplen = 8;
267
break;
268
- case 0x0004000a: /* Get/Test/Set overscan */
269
- case 0x0004400a:
270
- case 0x0004800a:
271
+ case RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN:
272
+ case RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN:
273
+ case RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN:
274
stl_le_phys(&s->dma_as, value + 12, 0);
275
stl_le_phys(&s->dma_as, value + 16, 0);
276
stl_le_phys(&s->dma_as, value + 20, 0);
277
stl_le_phys(&s->dma_as, value + 24, 0);
278
resplen = 16;
279
break;
280
- case 0x0004800b: /* Set palette */
281
+ case RPI_FWREQ_FRAMEBUFFER_SET_PALETTE:
282
offset = ldl_le_phys(&s->dma_as, value + 12);
283
length = ldl_le_phys(&s->dma_as, value + 16);
284
n = 0;
285
@@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
286
stl_le_phys(&s->dma_as, value + 12, 0);
287
resplen = 4;
288
break;
289
- case 0x00040013: /* Get number of displays */
290
+ case RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS:
291
stl_le_phys(&s->dma_as, value + 12, 1);
292
resplen = 4;
293
break;
294
295
- case 0x00060001: /* Get DMA channels */
296
+ case RPI_FWREQ_GET_DMA_CHANNELS:
297
/* channels 2-5 */
298
stl_le_phys(&s->dma_as, value + 12, 0x003C);
299
resplen = 4;
300
break;
301
302
- case 0x00050001: /* Get command line */
303
+ case RPI_FWREQ_GET_COMMAND_LINE:
304
/*
305
* We follow the firmware behaviour: no NUL terminator is
306
* written to the buffer, and if the buffer is too short
205
--
307
--
206
2.25.1
308
2.34.1
309
310
diff view generated by jsdifflib
[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
[PULL 32/33] hw/misc/bcm2835_property: Replace magic frequency values by definitions
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
From: Sergey Kambalin <sergey.kambalin@auriga.com>
2
2
3
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
3
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
4
separate infrastructure for a transitional period. We've now switched
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
over to contributing as Qualcomm Innovation Center (quicinc), so update
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
my email address to reflect this.
6
Message-id: 20230612223456.33824-4-philmd@linaro.org
7
7
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
8
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
8
[PMD: Split from bigger patch: 4/4]
9
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Cc: Leif Lindholm <leif@nuviainc.com>
11
Cc: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
[Fixed commit message typo]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
11
---
16
.mailmap | 3 ++-
12
include/hw/arm/raspi_platform.h | 5 +++++
17
MAINTAINERS | 2 +-
13
hw/misc/bcm2835_property.c | 8 +++++---
18
2 files changed, 3 insertions(+), 2 deletions(-)
14
2 files changed, 10 insertions(+), 3 deletions(-)
19
15
20
diff --git a/.mailmap b/.mailmap
16
diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/.mailmap
18
--- a/include/hw/arm/raspi_platform.h
23
+++ b/.mailmap
19
+++ b/include/hw/arm/raspi_platform.h
24
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
20
@@ -XXX,XX +XXX,XX @@
25
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
21
#define INTERRUPT_ILLEGAL_TYPE0 6
26
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
22
#define INTERRUPT_ILLEGAL_TYPE1 7
27
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
23
28
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
24
+/* Clock rates */
29
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
25
+#define RPI_FIRMWARE_EMMC_CLK_RATE 50000000
30
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
26
+#define RPI_FIRMWARE_UART_CLK_RATE 3000000
31
Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
27
+#define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000
32
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
28
+
33
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
29
#endif
34
diff --git a/MAINTAINERS b/MAINTAINERS
30
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
35
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
36
--- a/MAINTAINERS
32
--- a/hw/misc/bcm2835_property.c
37
+++ b/MAINTAINERS
33
+++ b/hw/misc/bcm2835_property.c
38
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
34
@@ -XXX,XX +XXX,XX @@
39
SBSA-REF
35
#include "qemu/log.h"
40
M: Radoslaw Biernacki <rad@semihalf.com>
36
#include "qemu/module.h"
41
M: Peter Maydell <peter.maydell@linaro.org>
37
#include "trace.h"
42
-R: Leif Lindholm <leif@nuviainc.com>
38
+#include "hw/arm/raspi_platform.h"
43
+R: Leif Lindholm <quic_llindhol@quicinc.com>
39
44
L: qemu-arm@nongnu.org
40
/* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface */
45
S: Maintained
41
46
F: hw/arm/sbsa-ref.c
42
@@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
43
case RPI_FWREQ_GET_MIN_CLOCK_RATE:
44
switch (ldl_le_phys(&s->dma_as, value + 12)) {
45
case RPI_FIRMWARE_EMMC_CLK_ID:
46
- stl_le_phys(&s->dma_as, value + 16, 50000000);
47
+ stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_EMMC_CLK_RATE);
48
break;
49
case RPI_FIRMWARE_UART_CLK_ID:
50
- stl_le_phys(&s->dma_as, value + 16, 3000000);
51
+ stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_RATE);
52
break;
53
default:
54
- stl_le_phys(&s->dma_as, value + 16, 700000000);
55
+ stl_le_phys(&s->dma_as, value + 16,
56
+ RPI_FIRMWARE_DEFAULT_CLK_RATE);
57
break;
58
}
59
resplen = 8;
47
--
60
--
48
2.25.1
61
2.34.1
49
62
50
63
diff view generated by jsdifflib
[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
[PULL 33/33] hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
From: Sergey Kambalin <sergey.kambalin@auriga.com>
2
2
3
The sbsa-ref machine is continuously evolving. Some of the changes we
3
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
4
want to make in the near future, to align with real components (e.g.
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
the GIC-700), will break compatibility for existing firmware.
5
Message-id: 20230612223456.33824-5-philmd@linaro.org
6
6
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
7
Introduce two new properties to the DT generated on machine generation:
7
[PMD: Split from bigger patch: 3/4]
8
- machine-version-major
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
To be incremented when a platform change makes the machine
9
[PMM: added a comment about RPI_FIRMWARE_CORE_CLK_RATE
10
incompatible with existing firmware.
10
really being SoC-specific]
11
- machine-version-minor
12
To be incremented when functionality is added to the machine
13
without causing incompatibility with existing firmware.
14
to be reset to 0 when machine-version-major is incremented.
15
16
This versioning scheme is *neither*:
17
- A QEMU versioned machine type; a given version of QEMU will emulate
18
a given version of the platform.
19
- A reflection of level of SBSA (now SystemReady SR) support provided.
20
21
The version will increment on guest-visible functional changes only,
22
akin to a revision ID register found on a physical platform.
23
24
These properties are both introduced with the value 0.
25
(Hence, a machine where the DT is lacking these nodes is equivalent
26
to version 0.0.)
27
28
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
29
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
30
Cc: Peter Maydell <peter.maydell@linaro.org>
31
Cc: Radoslaw Biernacki <rad@semihalf.com>
32
Cc: Cédric Le Goater <clg@kaod.org>
33
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
---
13
---
36
hw/arm/sbsa-ref.c | 14 ++++++++++++++
14
include/hw/arm/raspi_platform.h | 5 +++++
37
1 file changed, 14 insertions(+)
15
hw/misc/bcm2835_property.c | 3 +++
16
2 files changed, 8 insertions(+)
38
17
39
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
18
diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
40
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/sbsa-ref.c
20
--- a/include/hw/arm/raspi_platform.h
42
+++ b/hw/arm/sbsa-ref.c
21
+++ b/include/hw/arm/raspi_platform.h
43
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
22
@@ -XXX,XX +XXX,XX @@
44
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
23
/* Clock rates */
45
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
24
#define RPI_FIRMWARE_EMMC_CLK_RATE 50000000
46
25
#define RPI_FIRMWARE_UART_CLK_RATE 3000000
47
+ /*
26
+/*
48
+ * This versioning scheme is for informing platform fw only. It is neither:
27
+ * TODO: this is really SoC-specific; we might want to
49
+ * - A QEMU versioned machine type; a given version of QEMU will emulate
28
+ * set it per-SoC if it turns out any guests care.
50
+ * a given version of the platform.
29
+ */
51
+ * - A reflection of level of SBSA (now SystemReady SR) support provided.
30
+#define RPI_FIRMWARE_CORE_CLK_RATE 350000000
52
+ *
31
#define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000
53
+ * machine-version-major: updated when changes breaking fw compatibility
32
54
+ * are introduced.
33
#endif
55
+ * machine-version-minor: updated when features are added that don't break
34
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
56
+ * fw compatibility.
35
index XXXXXXX..XXXXXXX 100644
57
+ */
36
--- a/hw/misc/bcm2835_property.c
58
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
37
+++ b/hw/misc/bcm2835_property.c
59
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
38
@@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
60
+
39
case RPI_FIRMWARE_UART_CLK_ID:
61
if (ms->numa_state->have_numa_distance) {
40
stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_RATE);
62
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
41
break;
63
uint32_t *matrix = g_malloc0(size);
42
+ case RPI_FIRMWARE_CORE_CLK_ID:
43
+ stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_CORE_CLK_RATE);
44
+ break;
45
default:
46
stl_le_phys(&s->dma_as, value + 16,
47
RPI_FIRMWARE_DEFAULT_CLK_RATE);
64
--
48
--
65
2.25.1
49
2.34.1
66
50
67
51
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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