| 1 | target-arm queue: the big stuff here is the final part of | 1 | The following changes since commit aa9e7fa4689d1becb2faf67f65aafcbcf664f1ce: |
|---|---|---|---|
| 2 | rth's patches for Cortex-A76 and Neoverse-N1 support; | ||
| 3 | also present are Gavin's NUMA series and a few other things. | ||
| 4 | 2 | ||
| 5 | thanks | 3 | Merge tag 'edk2-stable202302-20230320-pull-request' of https://gitlab.com/kraxel/qemu into staging (2023-03-20 13:43:35 +0000) |
| 6 | -- PMM | ||
| 7 | |||
| 8 | The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b: | ||
| 9 | |||
| 10 | Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500) | ||
| 11 | 4 | ||
| 12 | are available in the Git repository at: | 5 | are available in the Git repository at: |
| 13 | 6 | ||
| 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230321 |
| 15 | 8 | ||
| 16 | for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34: | 9 | for you to fetch changes up to 5787d17a42f7af4bd117e5d6bfa54b1fdf93c255: |
| 17 | 10 | ||
| 18 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100) | 11 | target/arm: Don't advertise aarch64-pauth.xml to gdb (2023-03-21 13:19:08 +0000) |
| 19 | 12 | ||
| 20 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
| 21 | target-arm queue: | 14 | target-arm queue: |
| 22 | * MAINTAINERS/.mailmap: update email for Leif Lindholm | 15 | * contrib/elf2dmp: Support Windows Server 2022 |
| 23 | * hw/arm: add version information to sbsa-ref machine DT | 16 | * hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings |
| 24 | * Enable new features for -cpu max: | 17 | * target/arm: Add Neoverse-N1 IMPDEF registers |
| 25 | FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only), | 18 | * hw/usb/imx: Fix out of bounds access in imx_usbphy_read() |
| 26 | FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH | 19 | * docs/system/arm/cpu-features.rst: Fix formatting |
| 27 | * Emulate Cortex-A76 | 20 | * target/arm: Don't advertise aarch64-pauth.xml to gdb |
| 28 | * Emulate Neoverse-N1 | ||
| 29 | * Fix the virt board default NUMA topology | ||
| 30 | 21 | ||
| 31 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
| 32 | Gavin Shan (6): | 23 | Chen Baozi (1): |
| 33 | qapi/machine.json: Add cluster-id | 24 | target/arm: Add Neoverse-N1 registers |
| 34 | qtest/numa-test: Specify CPU topology in aarch64_numa_cpu() | ||
| 35 | hw/arm/virt: Consider SMP configuration in CPU topology | ||
| 36 | qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu() | ||
| 37 | hw/arm/virt: Fix CPU's default NUMA node ID | ||
| 38 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table | ||
| 39 | 25 | ||
| 40 | Leif Lindholm (2): | 26 | Guenter Roeck (1): |
| 41 | MAINTAINERS/.mailmap: update email for Leif Lindholm | 27 | hw/usb/imx: Fix out of bounds access in imx_usbphy_read() |
| 42 | hw/arm: add versioning to sbsa-ref machine DT | ||
| 43 | 28 | ||
| 44 | Richard Henderson (24): | 29 | Peter Maydell (3): |
| 45 | target/arm: Handle cpreg registration for missing EL | 30 | hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings |
| 46 | target/arm: Drop EL3 no EL2 fallbacks | 31 | docs/system/arm/cpu-features.rst: Fix formatting |
| 47 | target/arm: Merge zcr reginfo | 32 | target/arm: Don't advertise aarch64-pauth.xml to gdb |
| 48 | target/arm: Adjust definition of CONTEXTIDR_EL2 | ||
| 49 | target/arm: Move cortex impdef sysregs to cpu_tcg.c | ||
| 50 | target/arm: Update qemu-system-arm -cpu max to cortex-a57 | ||
| 51 | target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max | ||
| 52 | target/arm: Split out aa32_max_features | ||
| 53 | target/arm: Annotate arm_max_initfn with FEAT identifiers | ||
| 54 | target/arm: Use field names for manipulating EL2 and EL3 modes | ||
| 55 | target/arm: Enable FEAT_Debugv8p2 for -cpu max | ||
| 56 | target/arm: Enable FEAT_Debugv8p4 for -cpu max | ||
| 57 | target/arm: Add minimal RAS registers | ||
| 58 | target/arm: Enable SCR and HCR bits for RAS | ||
| 59 | target/arm: Implement virtual SError exceptions | ||
| 60 | target/arm: Implement ESB instruction | ||
| 61 | target/arm: Enable FEAT_RAS for -cpu max | ||
| 62 | target/arm: Enable FEAT_IESB for -cpu max | ||
| 63 | target/arm: Enable FEAT_CSV2 for -cpu max | ||
| 64 | target/arm: Enable FEAT_CSV2_2 for -cpu max | ||
| 65 | target/arm: Enable FEAT_CSV3 for -cpu max | ||
| 66 | target/arm: Enable FEAT_DGH for -cpu max | ||
| 67 | target/arm: Define cortex-a76 | ||
| 68 | target/arm: Define neoverse-n1 | ||
| 69 | 33 | ||
| 70 | docs/system/arm/emulation.rst | 10 + | 34 | Viktor Prutyanov (3): |
| 71 | docs/system/arm/virt.rst | 2 + | 35 | contrib/elf2dmp: fix code style |
| 72 | qapi/machine.json | 6 +- | 36 | contrib/elf2dmp: move PE dir search to pe_get_data_dir_entry |
| 73 | target/arm/cpregs.h | 11 + | 37 | contrib/elf2dmp: add PE name check and Windows Server 2022 support |
| 74 | target/arm/cpu.h | 23 ++ | 38 | |
| 75 | target/arm/helper.h | 1 + | 39 | docs/system/arm/cpu-features.rst | 68 ++++++++++------------- |
| 76 | target/arm/internals.h | 16 ++ | 40 | contrib/elf2dmp/pe.h | 115 ++++++++++++++++++++++----------------- |
| 77 | target/arm/syndrome.h | 5 + | 41 | contrib/elf2dmp/addrspace.c | 1 + |
| 78 | target/arm/a32.decode | 16 +- | 42 | contrib/elf2dmp/main.c | 108 ++++++++++++++++++++++++------------ |
| 79 | target/arm/t32.decode | 18 +- | 43 | hw/char/cadence_uart.c | 6 +- |
| 80 | hw/acpi/aml-build.c | 111 ++++---- | 44 | hw/usb/imx-usb-phy.c | 19 ++++++- |
| 81 | hw/arm/sbsa-ref.c | 16 ++ | 45 | target/arm/cpu64.c | 69 +++++++++++++++++++++++ |
| 82 | hw/arm/virt.c | 21 +- | 46 | target/arm/gdbstub.c | 7 +++ |
| 83 | hw/core/machine-hmp-cmds.c | 4 + | 47 | 8 files changed, 267 insertions(+), 126 deletions(-) |
| 84 | hw/core/machine.c | 16 ++ | ||
| 85 | target/arm/cpu.c | 66 ++++- | ||
| 86 | target/arm/cpu64.c | 353 ++++++++++++++----------- | ||
| 87 | target/arm/cpu_tcg.c | 227 +++++++++++----- | ||
| 88 | target/arm/helper.c | 600 +++++++++++++++++++++++++----------------- | ||
| 89 | target/arm/op_helper.c | 43 +++ | ||
| 90 | target/arm/translate-a64.c | 18 ++ | ||
| 91 | target/arm/translate.c | 23 ++ | ||
| 92 | tests/qtest/numa-test.c | 19 +- | ||
| 93 | .mailmap | 3 +- | ||
| 94 | MAINTAINERS | 2 +- | ||
| 95 | 25 files changed, 1068 insertions(+), 562 deletions(-) | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> | ||
| 2 | 1 | ||
| 3 | NUVIA was acquired by Qualcomm in March 2021, but kept functioning on | ||
| 4 | separate infrastructure for a transitional period. We've now switched | ||
| 5 | over to contributing as Qualcomm Innovation Center (quicinc), so update | ||
| 6 | my email address to reflect this. | ||
| 7 | |||
| 8 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
| 9 | Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com | ||
| 10 | Cc: Leif Lindholm <leif@nuviainc.com> | ||
| 11 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 13 | [Fixed commit message typo] | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | --- | ||
| 16 | .mailmap | 3 ++- | ||
| 17 | MAINTAINERS | 2 +- | ||
| 18 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/.mailmap b/.mailmap | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/.mailmap | ||
| 23 | +++ b/.mailmap | ||
| 24 | @@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com> | ||
| 25 | Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> | ||
| 26 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> | ||
| 27 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> | ||
| 28 | -Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org> | ||
| 29 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> | ||
| 30 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> | ||
| 31 | Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org> | ||
| 32 | Paul Burton <paulburton@kernel.org> <paul.burton@mips.com> | ||
| 33 | Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com> | ||
| 34 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 35 | index XXXXXXX..XXXXXXX 100644 | ||
| 36 | --- a/MAINTAINERS | ||
| 37 | +++ b/MAINTAINERS | ||
| 38 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h | ||
| 39 | SBSA-REF | ||
| 40 | M: Radoslaw Biernacki <rad@semihalf.com> | ||
| 41 | M: Peter Maydell <peter.maydell@linaro.org> | ||
| 42 | -R: Leif Lindholm <leif@nuviainc.com> | ||
| 43 | +R: Leif Lindholm <quic_llindhol@quicinc.com> | ||
| 44 | L: qemu-arm@nongnu.org | ||
| 45 | S: Maintained | ||
| 46 | F: hw/arm/sbsa-ref.c | ||
| 47 | -- | ||
| 48 | 2.25.1 | ||
| 49 | |||
| 50 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Chen Baozi <chenbaozi@phytium.com.cn> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Previously we were defining some of these in user-only mode, | 3 | Add implementation defined registers for neoverse-n1 which |
| 4 | but none of them are accessible from user-only, therefore | 4 | would be accessed by TF-A. Since there is no DSU in Qemu, |
| 5 | define them only in system mode. | 5 | CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. |
| 6 | 6 | ||
| 7 | This will shortly be used from cpu_tcg.c also. | 7 | Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> |
| 8 | |||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
| 11 | Message-id: 20220506180242.216785-6-richard.henderson@linaro.org | 10 | Message-id: 20230313033936.585669-1-chenbaozi@phytium.com.cn |
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | --- | 12 | --- |
| 14 | target/arm/internals.h | 6 ++++ | 13 | target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++ |
| 15 | target/arm/cpu64.c | 64 +++--------------------------------------- | 14 | 1 file changed, 69 insertions(+) |
| 16 | target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ | ||
| 17 | 3 files changed, 69 insertions(+), 60 deletions(-) | ||
| 18 | 15 | ||
| 19 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/target/arm/internals.h | ||
| 22 | +++ b/target/arm/internals.h | ||
| 23 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
| 24 | int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
| 25 | #endif | ||
| 26 | |||
| 27 | +#ifdef CONFIG_USER_ONLY | ||
| 28 | +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | ||
| 29 | +#else | ||
| 30 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | ||
| 31 | +#endif | ||
| 32 | + | ||
| 33 | #endif | ||
| 34 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 16 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
| 35 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 36 | --- a/target/arm/cpu64.c | 18 | --- a/target/arm/cpu64.c |
| 37 | +++ b/target/arm/cpu64.c | 19 | +++ b/target/arm/cpu64.c |
| 38 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
| 39 | #include "hvf_arm.h" | 21 | #include "qemu/osdep.h" |
| 40 | #include "qapi/visitor.h" | 22 | #include "qapi/error.h" |
| 41 | #include "hw/qdev-properties.h" | 23 | #include "cpu.h" |
| 42 | -#include "cpregs.h" | 24 | +#include "cpregs.h" |
| 43 | +#include "internals.h" | 25 | #include "qemu/module.h" |
| 44 | 26 | #include "sysemu/kvm.h" | |
| 45 | 27 | #include "sysemu/hvf.h" | |
| 46 | -#ifndef CONFIG_USER_ONLY | 28 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj) |
| 47 | -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 29 | /* TODO: Add A64FX specific HPC extension registers */ |
| 48 | -{ | 30 | } |
| 49 | - ARMCPU *cpu = env_archcpu(env); | 31 | |
| 50 | - | 32 | +static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { |
| 51 | - /* Number of cores is in [25:24]; otherwise we RAZ */ | 33 | + { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, |
| 52 | - return (cpu->core_count - 1) << 24; | 34 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, |
| 53 | -} | 35 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 54 | -#endif | 36 | + { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, |
| 55 | - | 37 | + .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, |
| 56 | -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | 38 | + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 57 | -#ifndef CONFIG_USER_ONLY | 39 | + { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, |
| 58 | - { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | 40 | + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, |
| 59 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | 41 | + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 60 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | 42 | + { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64, |
| 61 | - .writefn = arm_cp_write_ignore }, | 43 | + .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0, |
| 62 | - { .name = "L2CTLR", | 44 | + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 63 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | 45 | + { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, |
| 64 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | 46 | + .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, |
| 65 | - .writefn = arm_cp_write_ignore }, | 47 | + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 66 | -#endif | 48 | + { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 67 | - { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | 49 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, |
| 68 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | 50 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 69 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 51 | + { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, |
| 70 | - { .name = "L2ECTLR", | 52 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, |
| 71 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | 53 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 54 | + { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, |
| 73 | - { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | 55 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, |
| 74 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | 56 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 75 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 57 | + /* |
| 76 | - { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | 58 | + * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU |
| 77 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | 59 | + * (and in particular its system registers). |
| 78 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 60 | + */ |
| 79 | - { .name = "CPUACTLR", | 61 | + { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, |
| 80 | - .cp = 15, .opc1 = 0, .crm = 15, | 62 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, |
| 81 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | 63 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, |
| 82 | - { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | 64 | + { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 83 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | 65 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, |
| 84 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 66 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 }, |
| 85 | - { .name = "CPUECTLR", | 67 | + { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, |
| 86 | - .cp = 15, .opc1 = 1, .crm = 15, | 68 | + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, |
| 87 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | 69 | + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 88 | - { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | 70 | + { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, |
| 89 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | 71 | + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, |
| 90 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 72 | + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 91 | - { .name = "CPUMERRSR", | 73 | + { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, |
| 92 | - .cp = 15, .opc1 = 2, .crm = 15, | 74 | + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, |
| 93 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | 75 | + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 94 | - { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | 76 | + { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, |
| 95 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | 77 | + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, |
| 96 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 78 | + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 97 | - { .name = "L2MERRSR", | 79 | + { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, |
| 98 | - .cp = 15, .opc1 = 3, .crm = 15, | 80 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, |
| 99 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | 81 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 100 | -}; | 82 | + { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, |
| 101 | - | 83 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, |
| 102 | static void aarch64_a57_initfn(Object *obj) | 84 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
| 85 | + { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, | ||
| 86 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, | ||
| 87 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 88 | + { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, | ||
| 89 | + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, | ||
| 90 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 91 | +}; | ||
| 92 | + | ||
| 93 | +static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) | ||
| 94 | +{ | ||
| 95 | + define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); | ||
| 96 | +} | ||
| 97 | + | ||
| 98 | static void aarch64_neoverse_n1_initfn(Object *obj) | ||
| 103 | { | 99 | { |
| 104 | ARMCPU *cpu = ARM_CPU(obj); | 100 | ARMCPU *cpu = ARM_CPU(obj); |
| 105 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | 101 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj) |
| 106 | cpu->gic_num_lrs = 4; | 102 | |
| 107 | cpu->gic_vpribits = 5; | 103 | /* From D5.1 AArch64 PMU register summary */ |
| 108 | cpu->gic_vprebits = 5; | 104 | cpu->isar.reset_pmcr_el0 = 0x410c3000; |
| 109 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 105 | + |
| 110 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | 106 | + define_neoverse_n1_cp_reginfo(cpu); |
| 111 | } | 107 | } |
| 112 | 108 | ||
| 113 | static void aarch64_a53_initfn(Object *obj) | 109 | static void aarch64_host_initfn(Object *obj) |
| 114 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
| 115 | cpu->gic_num_lrs = 4; | ||
| 116 | cpu->gic_vpribits = 5; | ||
| 117 | cpu->gic_vprebits = 5; | ||
| 118 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
| 119 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
| 120 | } | ||
| 121 | |||
| 122 | static void aarch64_a72_initfn(Object *obj) | ||
| 123 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
| 124 | cpu->gic_num_lrs = 4; | ||
| 125 | cpu->gic_vpribits = 5; | ||
| 126 | cpu->gic_vprebits = 5; | ||
| 127 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
| 128 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
| 129 | } | ||
| 130 | |||
| 131 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | ||
| 132 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 133 | index XXXXXXX..XXXXXXX 100644 | ||
| 134 | --- a/target/arm/cpu_tcg.c | ||
| 135 | +++ b/target/arm/cpu_tcg.c | ||
| 136 | @@ -XXX,XX +XXX,XX @@ | ||
| 137 | #endif | ||
| 138 | #include "cpregs.h" | ||
| 139 | |||
| 140 | +#ifndef CONFIG_USER_ONLY | ||
| 141 | +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 142 | +{ | ||
| 143 | + ARMCPU *cpu = env_archcpu(env); | ||
| 144 | + | ||
| 145 | + /* Number of cores is in [25:24]; otherwise we RAZ */ | ||
| 146 | + return (cpu->core_count - 1) << 24; | ||
| 147 | +} | ||
| 148 | + | ||
| 149 | +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
| 150 | + { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 151 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | ||
| 152 | + .access = PL1_RW, .readfn = l2ctlr_read, | ||
| 153 | + .writefn = arm_cp_write_ignore }, | ||
| 154 | + { .name = "L2CTLR", | ||
| 155 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | ||
| 156 | + .access = PL1_RW, .readfn = l2ctlr_read, | ||
| 157 | + .writefn = arm_cp_write_ignore }, | ||
| 158 | + { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 159 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | ||
| 160 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 161 | + { .name = "L2ECTLR", | ||
| 162 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | ||
| 163 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 164 | + { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | ||
| 165 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | ||
| 166 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 167 | + { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 168 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | ||
| 169 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 170 | + { .name = "CPUACTLR", | ||
| 171 | + .cp = 15, .opc1 = 0, .crm = 15, | ||
| 172 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 173 | + { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 174 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | ||
| 175 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 176 | + { .name = "CPUECTLR", | ||
| 177 | + .cp = 15, .opc1 = 1, .crm = 15, | ||
| 178 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 179 | + { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 180 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | ||
| 181 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 182 | + { .name = "CPUMERRSR", | ||
| 183 | + .cp = 15, .opc1 = 2, .crm = 15, | ||
| 184 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 185 | + { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 186 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | ||
| 187 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 188 | + { .name = "L2MERRSR", | ||
| 189 | + .cp = 15, .opc1 = 3, .crm = 15, | ||
| 190 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 191 | +}; | ||
| 192 | + | ||
| 193 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) | ||
| 194 | +{ | ||
| 195 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
| 196 | +} | ||
| 197 | +#endif /* !CONFIG_USER_ONLY */ | ||
| 198 | + | ||
| 199 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | ||
| 200 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | ||
| 201 | |||
| 202 | -- | 110 | -- |
| 203 | 2.25.1 | 111 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Gavin Shan <gshan@redhat.com> | 1 | The cadence UART attempts to avoid allowing the guest to set invalid |
|---|---|---|---|
| 2 | baud rate register values in the uart_write() function. However it | ||
| 3 | does the "mask to the size of the register field" and "check for | ||
| 4 | invalid values" in the wrong order, which means that a malicious | ||
| 5 | guest can get a bogus value into the register by setting also some | ||
| 6 | high bits in the value, and cause QEMU to crash by division-by-zero. | ||
| 2 | 7 | ||
| 3 | The CPU topology isn't enabled on arm/virt machine yet, but we're | 8 | Do the mask before the bounds check instead of afterwards. |
| 4 | going to do it in next patch. After the CPU topology is enabled by | ||
| 5 | next patch, "thread-id=1" becomes invalid because the CPU core is | ||
| 6 | preferred on arm/virt machine. It means these two CPUs have 0/1 | ||
| 7 | as their core IDs, but their thread IDs are all 0. It will trigger | ||
| 8 | test failure as the following message indicates: | ||
| 9 | 9 | ||
| 10 | [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR | 10 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1493 |
| 11 | 1.48s killed by signal 6 SIGABRT | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \ | 12 | Reviewed-by: Thomas Huth <thuth@redhat.com> |
| 13 | QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \ | 13 | Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> |
| 14 | QTEST_QEMU_BINARY=./qemu-system-aarch64 \ | 14 | Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> |
| 15 | QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \ | 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 16 | /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k | 16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 17 | ―――――――――――――――――――――――――――――――――――――――――――――― | 17 | Tested-by: Qiang Liu <cyruscyliu@gmail.com> |
| 18 | stderr: | 18 | Message-id: 20230314170804.1196232-1-peter.maydell@linaro.org |
| 19 | qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found | 19 | --- |
| 20 | hw/char/cadence_uart.c | 6 ++++-- | ||
| 21 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
| 20 | 22 | ||
| 21 | This fixes the issue by providing comprehensive SMP configurations | 23 | diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c |
| 22 | in aarch64_numa_cpu(). The SMP configurations aren't used before | ||
| 23 | the CPU topology is enabled in next patch. | ||
| 24 | |||
| 25 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
| 26 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
| 27 | Message-id: 20220503140304.855514-3-gshan@redhat.com | ||
| 28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 29 | --- | ||
| 30 | tests/qtest/numa-test.c | 3 ++- | ||
| 31 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
| 32 | |||
| 33 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 35 | --- a/tests/qtest/numa-test.c | 25 | --- a/hw/char/cadence_uart.c |
| 36 | +++ b/tests/qtest/numa-test.c | 26 | +++ b/hw/char/cadence_uart.c |
| 37 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | 27 | @@ -XXX,XX +XXX,XX @@ static MemTxResult uart_write(void *opaque, hwaddr offset, |
| 38 | QTestState *qts; | 28 | } |
| 39 | g_autofree char *cli = NULL; | 29 | break; |
| 40 | 30 | case R_BRGR: /* Baud rate generator */ | |
| 41 | - cli = make_cli(data, "-machine smp.cpus=2 " | 31 | + value &= 0xffff; |
| 42 | + cli = make_cli(data, "-machine " | 32 | if (value >= 0x01) { |
| 43 | + "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " | 33 | - s->r[offset] = value & 0xFFFF; |
| 44 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " | 34 | + s->r[offset] = value; |
| 45 | "-numa cpu,node-id=1,thread-id=0 " | 35 | } |
| 46 | "-numa cpu,node-id=0,thread-id=1"); | 36 | break; |
| 37 | case R_BDIV: /* Baud rate divider */ | ||
| 38 | + value &= 0xff; | ||
| 39 | if (value >= 0x04) { | ||
| 40 | - s->r[offset] = value & 0xFF; | ||
| 41 | + s->r[offset] = value; | ||
| 42 | } | ||
| 43 | break; | ||
| 44 | default: | ||
| 47 | -- | 45 | -- |
| 48 | 2.25.1 | 46 | 2.34.1 |
| 49 | 47 | ||
| 50 | 48 | diff view generated by jsdifflib |
| 1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Viktor Prutyanov <viktor@daynix.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | When the PPTT table is built, the CPU topology is re-calculated, but | 3 | Originally elf2dmp were added with some code style issues, |
| 4 | it's unecessary because the CPU topology has been populated in | 4 | especially in pe.h header, and some were introduced by |
| 5 | virt_possible_cpu_arch_ids() on arm/virt machine. | 5 | 2d0fc797faaa73fbc1d30f5f9e90407bf3dd93f0. Fix them now. |
| 6 | 6 | ||
| 7 | This reworks build_pptt() to avoid by reusing the existing IDs in | 7 | Signed-off-by: Viktor Prutyanov <viktor@daynix.com> |
| 8 | ms->possible_cpus. Currently, the only user of build_pptt() is | 8 | Reviewed-by: Annie Li <annie.li@oracle.com> |
| 9 | arm/virt machine. | 9 | Message-id: 20230222211246.883679-2-viktor@daynix.com |
| 10 | |||
| 11 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
| 12 | Tested-by: Yanan Wang <wangyanan55@huawei.com> | ||
| 13 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
| 14 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
| 15 | Acked-by: Michael S. Tsirkin <mst@redhat.com> | ||
| 16 | Message-id: 20220503140304.855514-7-gshan@redhat.com | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 18 | --- | 11 | --- |
| 19 | hw/acpi/aml-build.c | 111 +++++++++++++++++++------------------------- | 12 | contrib/elf2dmp/pe.h | 100 ++++++++++++++++++------------------ |
| 20 | 1 file changed, 48 insertions(+), 63 deletions(-) | 13 | contrib/elf2dmp/addrspace.c | 1 + |
| 14 | contrib/elf2dmp/main.c | 9 ++-- | ||
| 15 | 3 files changed, 57 insertions(+), 53 deletions(-) | ||
| 21 | 16 | ||
| 22 | diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c | 17 | diff --git a/contrib/elf2dmp/pe.h b/contrib/elf2dmp/pe.h |
| 23 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/hw/acpi/aml-build.c | 19 | --- a/contrib/elf2dmp/pe.h |
| 25 | +++ b/hw/acpi/aml-build.c | 20 | +++ b/contrib/elf2dmp/pe.h |
| 26 | @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, | 21 | @@ -XXX,XX +XXX,XX @@ typedef struct IMAGE_DOS_HEADER { |
| 27 | const char *oem_id, const char *oem_table_id) | 22 | } __attribute__ ((packed)) IMAGE_DOS_HEADER; |
| 23 | |||
| 24 | typedef struct IMAGE_FILE_HEADER { | ||
| 25 | - uint16_t Machine; | ||
| 26 | - uint16_t NumberOfSections; | ||
| 27 | - uint32_t TimeDateStamp; | ||
| 28 | - uint32_t PointerToSymbolTable; | ||
| 29 | - uint32_t NumberOfSymbols; | ||
| 30 | - uint16_t SizeOfOptionalHeader; | ||
| 31 | - uint16_t Characteristics; | ||
| 32 | + uint16_t Machine; | ||
| 33 | + uint16_t NumberOfSections; | ||
| 34 | + uint32_t TimeDateStamp; | ||
| 35 | + uint32_t PointerToSymbolTable; | ||
| 36 | + uint32_t NumberOfSymbols; | ||
| 37 | + uint16_t SizeOfOptionalHeader; | ||
| 38 | + uint16_t Characteristics; | ||
| 39 | } __attribute__ ((packed)) IMAGE_FILE_HEADER; | ||
| 40 | |||
| 41 | typedef struct IMAGE_DATA_DIRECTORY { | ||
| 42 | - uint32_t VirtualAddress; | ||
| 43 | - uint32_t Size; | ||
| 44 | + uint32_t VirtualAddress; | ||
| 45 | + uint32_t Size; | ||
| 46 | } __attribute__ ((packed)) IMAGE_DATA_DIRECTORY; | ||
| 47 | |||
| 48 | #define IMAGE_NUMBEROF_DIRECTORY_ENTRIES 16 | ||
| 49 | |||
| 50 | typedef struct IMAGE_OPTIONAL_HEADER64 { | ||
| 51 | - uint16_t Magic; /* 0x20b */ | ||
| 52 | - uint8_t MajorLinkerVersion; | ||
| 53 | - uint8_t MinorLinkerVersion; | ||
| 54 | - uint32_t SizeOfCode; | ||
| 55 | - uint32_t SizeOfInitializedData; | ||
| 56 | - uint32_t SizeOfUninitializedData; | ||
| 57 | - uint32_t AddressOfEntryPoint; | ||
| 58 | - uint32_t BaseOfCode; | ||
| 59 | - uint64_t ImageBase; | ||
| 60 | - uint32_t SectionAlignment; | ||
| 61 | - uint32_t FileAlignment; | ||
| 62 | - uint16_t MajorOperatingSystemVersion; | ||
| 63 | - uint16_t MinorOperatingSystemVersion; | ||
| 64 | - uint16_t MajorImageVersion; | ||
| 65 | - uint16_t MinorImageVersion; | ||
| 66 | - uint16_t MajorSubsystemVersion; | ||
| 67 | - uint16_t MinorSubsystemVersion; | ||
| 68 | - uint32_t Win32VersionValue; | ||
| 69 | - uint32_t SizeOfImage; | ||
| 70 | - uint32_t SizeOfHeaders; | ||
| 71 | - uint32_t CheckSum; | ||
| 72 | - uint16_t Subsystem; | ||
| 73 | - uint16_t DllCharacteristics; | ||
| 74 | - uint64_t SizeOfStackReserve; | ||
| 75 | - uint64_t SizeOfStackCommit; | ||
| 76 | - uint64_t SizeOfHeapReserve; | ||
| 77 | - uint64_t SizeOfHeapCommit; | ||
| 78 | - uint32_t LoaderFlags; | ||
| 79 | - uint32_t NumberOfRvaAndSizes; | ||
| 80 | - IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; | ||
| 81 | + uint16_t Magic; /* 0x20b */ | ||
| 82 | + uint8_t MajorLinkerVersion; | ||
| 83 | + uint8_t MinorLinkerVersion; | ||
| 84 | + uint32_t SizeOfCode; | ||
| 85 | + uint32_t SizeOfInitializedData; | ||
| 86 | + uint32_t SizeOfUninitializedData; | ||
| 87 | + uint32_t AddressOfEntryPoint; | ||
| 88 | + uint32_t BaseOfCode; | ||
| 89 | + uint64_t ImageBase; | ||
| 90 | + uint32_t SectionAlignment; | ||
| 91 | + uint32_t FileAlignment; | ||
| 92 | + uint16_t MajorOperatingSystemVersion; | ||
| 93 | + uint16_t MinorOperatingSystemVersion; | ||
| 94 | + uint16_t MajorImageVersion; | ||
| 95 | + uint16_t MinorImageVersion; | ||
| 96 | + uint16_t MajorSubsystemVersion; | ||
| 97 | + uint16_t MinorSubsystemVersion; | ||
| 98 | + uint32_t Win32VersionValue; | ||
| 99 | + uint32_t SizeOfImage; | ||
| 100 | + uint32_t SizeOfHeaders; | ||
| 101 | + uint32_t CheckSum; | ||
| 102 | + uint16_t Subsystem; | ||
| 103 | + uint16_t DllCharacteristics; | ||
| 104 | + uint64_t SizeOfStackReserve; | ||
| 105 | + uint64_t SizeOfStackCommit; | ||
| 106 | + uint64_t SizeOfHeapReserve; | ||
| 107 | + uint64_t SizeOfHeapCommit; | ||
| 108 | + uint32_t LoaderFlags; | ||
| 109 | + uint32_t NumberOfRvaAndSizes; | ||
| 110 | + IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; | ||
| 111 | } __attribute__ ((packed)) IMAGE_OPTIONAL_HEADER64; | ||
| 112 | |||
| 113 | typedef struct IMAGE_NT_HEADERS64 { | ||
| 114 | - uint32_t Signature; | ||
| 115 | - IMAGE_FILE_HEADER FileHeader; | ||
| 116 | - IMAGE_OPTIONAL_HEADER64 OptionalHeader; | ||
| 117 | + uint32_t Signature; | ||
| 118 | + IMAGE_FILE_HEADER FileHeader; | ||
| 119 | + IMAGE_OPTIONAL_HEADER64 OptionalHeader; | ||
| 120 | } __attribute__ ((packed)) IMAGE_NT_HEADERS64; | ||
| 121 | |||
| 122 | typedef struct IMAGE_DEBUG_DIRECTORY { | ||
| 123 | - uint32_t Characteristics; | ||
| 124 | - uint32_t TimeDateStamp; | ||
| 125 | - uint16_t MajorVersion; | ||
| 126 | - uint16_t MinorVersion; | ||
| 127 | - uint32_t Type; | ||
| 128 | - uint32_t SizeOfData; | ||
| 129 | - uint32_t AddressOfRawData; | ||
| 130 | - uint32_t PointerToRawData; | ||
| 131 | + uint32_t Characteristics; | ||
| 132 | + uint32_t TimeDateStamp; | ||
| 133 | + uint16_t MajorVersion; | ||
| 134 | + uint16_t MinorVersion; | ||
| 135 | + uint32_t Type; | ||
| 136 | + uint32_t SizeOfData; | ||
| 137 | + uint32_t AddressOfRawData; | ||
| 138 | + uint32_t PointerToRawData; | ||
| 139 | } __attribute__ ((packed)) IMAGE_DEBUG_DIRECTORY; | ||
| 140 | |||
| 141 | #define IMAGE_DEBUG_TYPE_CODEVIEW 2 | ||
| 142 | diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c | ||
| 143 | index XXXXXXX..XXXXXXX 100644 | ||
| 144 | --- a/contrib/elf2dmp/addrspace.c | ||
| 145 | +++ b/contrib/elf2dmp/addrspace.c | ||
| 146 | @@ -XXX,XX +XXX,XX @@ | ||
| 147 | static struct pa_block *pa_space_find_block(struct pa_space *ps, uint64_t pa) | ||
| 28 | { | 148 | { |
| 29 | MachineClass *mc = MACHINE_GET_CLASS(ms); | 149 | size_t i; |
| 30 | - GQueue *list = g_queue_new(); | 150 | + |
| 31 | - guint pptt_start = table_data->len; | 151 | for (i = 0; i < ps->block_nr; i++) { |
| 32 | - guint parent_offset; | 152 | if (ps->block[i].paddr <= pa && |
| 33 | - guint length, i; | 153 | pa <= ps->block[i].paddr + ps->block[i].size) { |
| 34 | - int uid = 0; | 154 | diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c |
| 35 | - int socket; | 155 | index XXXXXXX..XXXXXXX 100644 |
| 36 | + CPUArchIdList *cpus = ms->possible_cpus; | 156 | --- a/contrib/elf2dmp/main.c |
| 37 | + int64_t socket_id = -1, cluster_id = -1, core_id = -1; | 157 | +++ b/contrib/elf2dmp/main.c |
| 38 | + uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0; | 158 | @@ -XXX,XX +XXX,XX @@ static int fill_header(WinDumpHeader64 *hdr, struct pa_space *ps, |
| 39 | + uint32_t pptt_start = table_data->len; | 159 | }; |
| 40 | + int n; | 160 | |
| 41 | AcpiTable table = { .sig = "PPTT", .rev = 2, | 161 | for (i = 0; i < ps->block_nr; i++) { |
| 42 | .oem_id = oem_id, .oem_table_id = oem_table_id }; | 162 | - h.PhysicalMemoryBlock.NumberOfPages += ps->block[i].size / ELF2DMP_PAGE_SIZE; |
| 43 | 163 | + h.PhysicalMemoryBlock.NumberOfPages += | |
| 44 | acpi_table_begin(&table, table_data); | 164 | + ps->block[i].size / ELF2DMP_PAGE_SIZE; |
| 45 | 165 | h.PhysicalMemoryBlock.Run[i] = (WinDumpPhyMemRun64) { | |
| 46 | - for (socket = 0; socket < ms->smp.sockets; socket++) { | 166 | .BasePage = ps->block[i].paddr / ELF2DMP_PAGE_SIZE, |
| 47 | - g_queue_push_tail(list, | 167 | .PageCount = ps->block[i].size / ELF2DMP_PAGE_SIZE, |
| 48 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | 168 | }; |
| 49 | - build_processor_hierarchy_node( | ||
| 50 | - table_data, | ||
| 51 | - /* | ||
| 52 | - * Physical package - represents the boundary | ||
| 53 | - * of a physical package | ||
| 54 | - */ | ||
| 55 | - (1 << 0), | ||
| 56 | - 0, socket, NULL, 0); | ||
| 57 | - } | ||
| 58 | - | ||
| 59 | - if (mc->smp_props.clusters_supported) { | ||
| 60 | - length = g_queue_get_length(list); | ||
| 61 | - for (i = 0; i < length; i++) { | ||
| 62 | - int cluster; | ||
| 63 | - | ||
| 64 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
| 65 | - for (cluster = 0; cluster < ms->smp.clusters; cluster++) { | ||
| 66 | - g_queue_push_tail(list, | ||
| 67 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
| 68 | - build_processor_hierarchy_node( | ||
| 69 | - table_data, | ||
| 70 | - (0 << 0), /* not a physical package */ | ||
| 71 | - parent_offset, cluster, NULL, 0); | ||
| 72 | - } | ||
| 73 | + /* | ||
| 74 | + * This works with the assumption that cpus[n].props.*_id has been | ||
| 75 | + * sorted from top to down levels in mc->possible_cpu_arch_ids(). | ||
| 76 | + * Otherwise, the unexpected and duplicated containers will be | ||
| 77 | + * created. | ||
| 78 | + */ | ||
| 79 | + for (n = 0; n < cpus->len; n++) { | ||
| 80 | + if (cpus->cpus[n].props.socket_id != socket_id) { | ||
| 81 | + assert(cpus->cpus[n].props.socket_id > socket_id); | ||
| 82 | + socket_id = cpus->cpus[n].props.socket_id; | ||
| 83 | + cluster_id = -1; | ||
| 84 | + core_id = -1; | ||
| 85 | + socket_offset = table_data->len - pptt_start; | ||
| 86 | + build_processor_hierarchy_node(table_data, | ||
| 87 | + (1 << 0), /* Physical package */ | ||
| 88 | + 0, socket_id, NULL, 0); | ||
| 89 | } | ||
| 90 | - } | ||
| 91 | |||
| 92 | - length = g_queue_get_length(list); | ||
| 93 | - for (i = 0; i < length; i++) { | ||
| 94 | - int core; | ||
| 95 | - | ||
| 96 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
| 97 | - for (core = 0; core < ms->smp.cores; core++) { | ||
| 98 | - if (ms->smp.threads > 1) { | ||
| 99 | - g_queue_push_tail(list, | ||
| 100 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
| 101 | - build_processor_hierarchy_node( | ||
| 102 | - table_data, | ||
| 103 | - (0 << 0), /* not a physical package */ | ||
| 104 | - parent_offset, core, NULL, 0); | ||
| 105 | - } else { | ||
| 106 | - build_processor_hierarchy_node( | ||
| 107 | - table_data, | ||
| 108 | - (1 << 1) | /* ACPI Processor ID valid */ | ||
| 109 | - (1 << 3), /* Node is a Leaf */ | ||
| 110 | - parent_offset, uid++, NULL, 0); | ||
| 111 | + if (mc->smp_props.clusters_supported) { | ||
| 112 | + if (cpus->cpus[n].props.cluster_id != cluster_id) { | ||
| 113 | + assert(cpus->cpus[n].props.cluster_id > cluster_id); | ||
| 114 | + cluster_id = cpus->cpus[n].props.cluster_id; | ||
| 115 | + core_id = -1; | ||
| 116 | + cluster_offset = table_data->len - pptt_start; | ||
| 117 | + build_processor_hierarchy_node(table_data, | ||
| 118 | + (0 << 0), /* Not a physical package */ | ||
| 119 | + socket_offset, cluster_id, NULL, 0); | ||
| 120 | } | ||
| 121 | + } else { | ||
| 122 | + cluster_offset = socket_offset; | ||
| 123 | } | ||
| 124 | - } | ||
| 125 | |||
| 126 | - length = g_queue_get_length(list); | ||
| 127 | - for (i = 0; i < length; i++) { | ||
| 128 | - int thread; | ||
| 129 | + if (ms->smp.threads == 1) { | ||
| 130 | + build_processor_hierarchy_node(table_data, | ||
| 131 | + (1 << 1) | /* ACPI Processor ID valid */ | ||
| 132 | + (1 << 3), /* Node is a Leaf */ | ||
| 133 | + cluster_offset, n, NULL, 0); | ||
| 134 | + } else { | ||
| 135 | + if (cpus->cpus[n].props.core_id != core_id) { | ||
| 136 | + assert(cpus->cpus[n].props.core_id > core_id); | ||
| 137 | + core_id = cpus->cpus[n].props.core_id; | ||
| 138 | + core_offset = table_data->len - pptt_start; | ||
| 139 | + build_processor_hierarchy_node(table_data, | ||
| 140 | + (0 << 0), /* Not a physical package */ | ||
| 141 | + cluster_offset, core_id, NULL, 0); | ||
| 142 | + } | ||
| 143 | |||
| 144 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
| 145 | - for (thread = 0; thread < ms->smp.threads; thread++) { | ||
| 146 | - build_processor_hierarchy_node( | ||
| 147 | - table_data, | ||
| 148 | + build_processor_hierarchy_node(table_data, | ||
| 149 | (1 << 1) | /* ACPI Processor ID valid */ | ||
| 150 | (1 << 2) | /* Processor is a Thread */ | ||
| 151 | (1 << 3), /* Node is a Leaf */ | ||
| 152 | - parent_offset, uid++, NULL, 0); | ||
| 153 | + core_offset, n, NULL, 0); | ||
| 154 | } | ||
| 155 | } | 169 | } |
| 156 | 170 | ||
| 157 | - g_queue_free(list); | 171 | - h.RequiredDumpSpace += h.PhysicalMemoryBlock.NumberOfPages << ELF2DMP_PAGE_BITS; |
| 158 | acpi_table_end(linker, &table); | 172 | + h.RequiredDumpSpace += |
| 159 | } | 173 | + h.PhysicalMemoryBlock.NumberOfPages << ELF2DMP_PAGE_BITS; |
| 160 | 174 | ||
| 175 | *hdr = h; | ||
| 176 | |||
| 177 | @@ -XXX,XX +XXX,XX @@ static int fill_header(WinDumpHeader64 *hdr, struct pa_space *ps, | ||
| 178 | static int fill_context(KDDEBUGGER_DATA64 *kdbg, | ||
| 179 | struct va_space *vs, QEMU_Elf *qe) | ||
| 180 | { | ||
| 181 | - int i; | ||
| 182 | + int i; | ||
| 183 | + | ||
| 184 | for (i = 0; i < qe->state_nr; i++) { | ||
| 185 | uint64_t Prcb; | ||
| 186 | uint64_t Context; | ||
| 161 | -- | 187 | -- |
| 162 | 2.25.1 | 188 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Viktor Prutyanov <viktor@daynix.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Enable the n1 for virt and sbsa board use. | 3 | Move out PE directory search functionality to be reused not only |
| 4 | for Debug Directory processing but for arbitrary PE directory. | ||
| 4 | 5 | ||
| 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Viktor Prutyanov <viktor@daynix.com> |
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Annie Li <annie.li@oracle.com> |
| 7 | Message-id: 20220506180242.216785-25-richard.henderson@linaro.org | 8 | Message-id: 20230222211246.883679-3-viktor@daynix.com |
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | --- | 10 | --- |
| 10 | docs/system/arm/virt.rst | 1 + | 11 | contrib/elf2dmp/main.c | 71 +++++++++++++++++++++++++----------------- |
| 11 | hw/arm/sbsa-ref.c | 1 + | 12 | 1 file changed, 42 insertions(+), 29 deletions(-) |
| 12 | hw/arm/virt.c | 1 + | ||
| 13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | ||
| 14 | 4 files changed, 69 insertions(+) | ||
| 15 | 13 | ||
| 16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 14 | diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/docs/system/arm/virt.rst | 16 | --- a/contrib/elf2dmp/main.c |
| 19 | +++ b/docs/system/arm/virt.rst | 17 | +++ b/contrib/elf2dmp/main.c |
| 20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | 18 | @@ -XXX,XX +XXX,XX @@ static int fill_context(KDDEBUGGER_DATA64 *kdbg, |
| 21 | - ``cortex-a76`` (64-bit) | 19 | return 0; |
| 22 | - ``a64fx`` (64-bit) | ||
| 23 | - ``host`` (with KVM only) | ||
| 24 | +- ``neoverse-n1`` (64-bit) | ||
| 25 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | ||
| 26 | |||
| 27 | Note that the default is ``cortex-a15``, so for an AArch64 guest you must | ||
| 28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/arm/sbsa-ref.c | ||
| 31 | +++ b/hw/arm/sbsa-ref.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = { | ||
| 33 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
| 34 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
| 35 | ARM_CPU_TYPE_NAME("cortex-a76"), | ||
| 36 | + ARM_CPU_TYPE_NAME("neoverse-n1"), | ||
| 37 | ARM_CPU_TYPE_NAME("max"), | ||
| 38 | }; | ||
| 39 | |||
| 40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/hw/arm/virt.c | ||
| 43 | +++ b/hw/arm/virt.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | ||
| 45 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
| 46 | ARM_CPU_TYPE_NAME("cortex-a76"), | ||
| 47 | ARM_CPU_TYPE_NAME("a64fx"), | ||
| 48 | + ARM_CPU_TYPE_NAME("neoverse-n1"), | ||
| 49 | ARM_CPU_TYPE_NAME("host"), | ||
| 50 | ARM_CPU_TYPE_NAME("max"), | ||
| 51 | }; | ||
| 52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/target/arm/cpu64.c | ||
| 55 | +++ b/target/arm/cpu64.c | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj) | ||
| 57 | cpu->isar.mvfr2 = 0x00000043; | ||
| 58 | } | 20 | } |
| 59 | 21 | ||
| 60 | +static void aarch64_neoverse_n1_initfn(Object *obj) | 22 | +static int pe_get_data_dir_entry(uint64_t base, void *start_addr, int idx, |
| 23 | + void *entry, size_t size, struct va_space *vs) | ||
| 61 | +{ | 24 | +{ |
| 62 | + ARMCPU *cpu = ARM_CPU(obj); | 25 | + const char e_magic[2] = "MZ"; |
| 26 | + const char Signature[4] = "PE\0\0"; | ||
| 27 | + IMAGE_DOS_HEADER *dos_hdr = start_addr; | ||
| 28 | + IMAGE_NT_HEADERS64 nt_hdrs; | ||
| 29 | + IMAGE_FILE_HEADER *file_hdr = &nt_hdrs.FileHeader; | ||
| 30 | + IMAGE_OPTIONAL_HEADER64 *opt_hdr = &nt_hdrs.OptionalHeader; | ||
| 31 | + IMAGE_DATA_DIRECTORY *data_dir = nt_hdrs.OptionalHeader.DataDirectory; | ||
| 63 | + | 32 | + |
| 64 | + cpu->dtb_compatible = "arm,neoverse-n1"; | 33 | + QEMU_BUILD_BUG_ON(sizeof(*dos_hdr) >= ELF2DMP_PAGE_SIZE); |
| 65 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
| 66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
| 67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
| 68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
| 69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
| 70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
| 71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
| 72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
| 73 | + | 34 | + |
| 74 | + /* Ordered by B2.4 AArch64 registers by functional group */ | 35 | + if (memcmp(&dos_hdr->e_magic, e_magic, sizeof(e_magic))) { |
| 75 | + cpu->clidr = 0x82000023; | 36 | + return 1; |
| 76 | + cpu->ctr = 0x8444c004; | 37 | + } |
| 77 | + cpu->dcz_blocksize = 4; | ||
| 78 | + cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; | ||
| 79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | ||
| 80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | ||
| 81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; | ||
| 82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | ||
| 83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | ||
| 84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | ||
| 85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; | ||
| 86 | + cpu->id_afr0 = 0x00000000; | ||
| 87 | + cpu->isar.id_dfr0 = 0x04010088; | ||
| 88 | + cpu->isar.id_isar0 = 0x02101110; | ||
| 89 | + cpu->isar.id_isar1 = 0x13112111; | ||
| 90 | + cpu->isar.id_isar2 = 0x21232042; | ||
| 91 | + cpu->isar.id_isar3 = 0x01112131; | ||
| 92 | + cpu->isar.id_isar4 = 0x00010142; | ||
| 93 | + cpu->isar.id_isar5 = 0x01011121; | ||
| 94 | + cpu->isar.id_isar6 = 0x00000010; | ||
| 95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
| 96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
| 97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
| 98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
| 99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
| 100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
| 101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
| 102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
| 103 | + cpu->midr = 0x414fd0c1; /* r4p1 */ | ||
| 104 | + cpu->revidr = 0; | ||
| 105 | + | 38 | + |
| 106 | + /* From B2.23 CCSIDR_EL1 */ | 39 | + if (va_space_rw(vs, base + dos_hdr->e_lfanew, |
| 107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | 40 | + &nt_hdrs, sizeof(nt_hdrs), 0)) { |
| 108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | 41 | + return 1; |
| 109 | + cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ | 42 | + } |
| 110 | + | 43 | + |
| 111 | + /* From B2.98 SCTLR_EL3 */ | 44 | + if (memcmp(&nt_hdrs.Signature, Signature, sizeof(Signature)) || |
| 112 | + cpu->reset_sctlr = 0x30c50838; | 45 | + file_hdr->Machine != 0x8664 || opt_hdr->Magic != 0x020b) { |
| 46 | + return 1; | ||
| 47 | + } | ||
| 113 | + | 48 | + |
| 114 | + /* From B4.23 ICH_VTR_EL2 */ | 49 | + if (va_space_rw(vs, |
| 115 | + cpu->gic_num_lrs = 4; | 50 | + base + data_dir[idx].VirtualAddress, |
| 116 | + cpu->gic_vpribits = 5; | 51 | + entry, size, 0)) { |
| 117 | + cpu->gic_vprebits = 5; | 52 | + return 1; |
| 53 | + } | ||
| 118 | + | 54 | + |
| 119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | 55 | + printf("Data directory entry #%d: RVA = 0x%08"PRIx32"\n", idx, |
| 120 | + cpu->isar.mvfr0 = 0x10110222; | 56 | + (uint32_t)data_dir[idx].VirtualAddress); |
| 121 | + cpu->isar.mvfr1 = 0x13211111; | 57 | + |
| 122 | + cpu->isar.mvfr2 = 0x00000043; | 58 | + return 0; |
| 123 | +} | 59 | +} |
| 124 | + | 60 | + |
| 125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | 61 | static int write_dump(struct pa_space *ps, |
| 62 | WinDumpHeader64 *hdr, const char *name) | ||
| 126 | { | 63 | { |
| 127 | /* | 64 | @@ -XXX,XX +XXX,XX @@ static int write_dump(struct pa_space *ps, |
| 128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | 65 | static int pe_get_pdb_symstore_hash(uint64_t base, void *start_addr, |
| 129 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | 66 | char *hash, struct va_space *vs) |
| 130 | { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | 67 | { |
| 131 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | 68 | - const char e_magic[2] = "MZ"; |
| 132 | + { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, | 69 | - const char Signature[4] = "PE\0\0"; |
| 133 | { .name = "max", .initfn = aarch64_max_initfn }, | 70 | const char sign_rsds[4] = "RSDS"; |
| 134 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | 71 | - IMAGE_DOS_HEADER *dos_hdr = start_addr; |
| 135 | { .name = "host", .initfn = aarch64_host_initfn }, | 72 | - IMAGE_NT_HEADERS64 nt_hdrs; |
| 73 | - IMAGE_FILE_HEADER *file_hdr = &nt_hdrs.FileHeader; | ||
| 74 | - IMAGE_OPTIONAL_HEADER64 *opt_hdr = &nt_hdrs.OptionalHeader; | ||
| 75 | - IMAGE_DATA_DIRECTORY *data_dir = nt_hdrs.OptionalHeader.DataDirectory; | ||
| 76 | IMAGE_DEBUG_DIRECTORY debug_dir; | ||
| 77 | OMFSignatureRSDS rsds; | ||
| 78 | char *pdb_name; | ||
| 79 | size_t pdb_name_sz; | ||
| 80 | size_t i; | ||
| 81 | |||
| 82 | - QEMU_BUILD_BUG_ON(sizeof(*dos_hdr) >= ELF2DMP_PAGE_SIZE); | ||
| 83 | - | ||
| 84 | - if (memcmp(&dos_hdr->e_magic, e_magic, sizeof(e_magic))) { | ||
| 85 | - return 1; | ||
| 86 | - } | ||
| 87 | - | ||
| 88 | - if (va_space_rw(vs, base + dos_hdr->e_lfanew, | ||
| 89 | - &nt_hdrs, sizeof(nt_hdrs), 0)) { | ||
| 90 | - return 1; | ||
| 91 | - } | ||
| 92 | - | ||
| 93 | - if (memcmp(&nt_hdrs.Signature, Signature, sizeof(Signature)) || | ||
| 94 | - file_hdr->Machine != 0x8664 || opt_hdr->Magic != 0x020b) { | ||
| 95 | - return 1; | ||
| 96 | - } | ||
| 97 | - | ||
| 98 | - printf("Debug Directory RVA = 0x%08"PRIx32"\n", | ||
| 99 | - (uint32_t)data_dir[IMAGE_FILE_DEBUG_DIRECTORY].VirtualAddress); | ||
| 100 | - | ||
| 101 | - if (va_space_rw(vs, | ||
| 102 | - base + data_dir[IMAGE_FILE_DEBUG_DIRECTORY].VirtualAddress, | ||
| 103 | - &debug_dir, sizeof(debug_dir), 0)) { | ||
| 104 | + if (pe_get_data_dir_entry(base, start_addr, IMAGE_FILE_DEBUG_DIRECTORY, | ||
| 105 | + &debug_dir, sizeof(debug_dir), vs)) { | ||
| 106 | + eprintf("Failed to get Debug Directory\n"); | ||
| 107 | return 1; | ||
| 108 | } | ||
| 109 | |||
| 136 | -- | 110 | -- |
| 137 | 2.25.1 | 111 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Viktor Prutyanov <viktor@daynix.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | More gracefully handle cpregs when EL2 and/or EL3 are missing. | 3 | Since its inception elf2dmp has checked MZ signatures within an |
| 4 | If the reg is entirely inaccessible, do not register it at all. | 4 | address space above IDT[0] interrupt vector and took first PE image |
| 5 | If the reg is for EL2, and EL3 is present but EL2 is not, | 5 | found as Windows Kernel. |
| 6 | either discard, squash to res0, const, or keep unchanged. | 6 | But in Windows Server 2022 memory dump this address space range is |
| 7 | full of invalid PE fragments and the tool must check that PE image | ||
| 8 | is 'ntoskrnl.exe' actually. | ||
| 9 | So, introduce additional validation by checking image name from | ||
| 10 | Export Directory against 'ntoskrnl.exe'. | ||
| 7 | 11 | ||
| 8 | Per rule RJFFP, mark the 4 aarch32 hypervisor access registers | 12 | Signed-off-by: Viktor Prutyanov <viktor@daynix.com> |
| 9 | with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address | 13 | Tested-by: Yuri Benditovich <yuri.benditovich@daynix.com> |
| 10 | translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. | 14 | Reviewed-by: Annie Li <annie.li@oracle.com> |
| 11 | Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ. | 15 | Message-id: 20230222211246.883679-4-viktor@daynix.com |
| 12 | |||
| 13 | This will simplify cpreg registration for conditional arm features. | ||
| 14 | |||
| 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 17 | Message-id: 20220506180242.216785-2-richard.henderson@linaro.org | ||
| 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 19 | --- | 17 | --- |
| 20 | target/arm/cpregs.h | 11 +++ | 18 | contrib/elf2dmp/pe.h | 15 +++++++++++++++ |
| 21 | target/arm/helper.c | 178 ++++++++++++++++++++++++++++++-------------- | 19 | contrib/elf2dmp/main.c | 28 ++++++++++++++++++++++++++-- |
| 22 | 2 files changed, 133 insertions(+), 56 deletions(-) | 20 | 2 files changed, 41 insertions(+), 2 deletions(-) |
| 23 | 21 | ||
| 24 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 22 | diff --git a/contrib/elf2dmp/pe.h b/contrib/elf2dmp/pe.h |
| 25 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/target/arm/cpregs.h | 24 | --- a/contrib/elf2dmp/pe.h |
| 27 | +++ b/target/arm/cpregs.h | 25 | +++ b/contrib/elf2dmp/pe.h |
| 28 | @@ -XXX,XX +XXX,XX @@ enum { | 26 | @@ -XXX,XX +XXX,XX @@ typedef struct IMAGE_NT_HEADERS64 { |
| 29 | ARM_CP_SVE = 1 << 14, | 27 | IMAGE_OPTIONAL_HEADER64 OptionalHeader; |
| 30 | /* Flag: Do not expose in gdb sysreg xml. */ | 28 | } __attribute__ ((packed)) IMAGE_NT_HEADERS64; |
| 31 | ARM_CP_NO_GDB = 1 << 15, | 29 | |
| 32 | + /* | 30 | +typedef struct IMAGE_EXPORT_DIRECTORY { |
| 33 | + * Flags: If EL3 but not EL2... | 31 | + uint32_t Characteristics; |
| 34 | + * - UNDEF: discard the cpreg, | 32 | + uint32_t TimeDateStamp; |
| 35 | + * - KEEP: retain the cpreg as is, | 33 | + uint16_t MajorVersion; |
| 36 | + * - C_NZ: set const on the cpreg, but retain resetvalue, | 34 | + uint16_t MinorVersion; |
| 37 | + * - else: set const on the cpreg, zero resetvalue, aka RES0. | 35 | + uint32_t Name; |
| 38 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | 36 | + uint32_t Base; |
| 39 | + */ | 37 | + uint32_t NumberOfFunctions; |
| 40 | + ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, | 38 | + uint32_t NumberOfNames; |
| 41 | + ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, | 39 | + uint32_t AddressOfFunctions; |
| 42 | + ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, | 40 | + uint32_t AddressOfNames; |
| 43 | }; | 41 | + uint32_t AddressOfNameOrdinals; |
| 44 | 42 | +} __attribute__ ((packed)) IMAGE_EXPORT_DIRECTORY; | |
| 45 | /* | 43 | + |
| 46 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 44 | typedef struct IMAGE_DEBUG_DIRECTORY { |
| 45 | uint32_t Characteristics; | ||
| 46 | uint32_t TimeDateStamp; | ||
| 47 | @@ -XXX,XX +XXX,XX @@ typedef struct IMAGE_DEBUG_DIRECTORY { | ||
| 48 | #define IMAGE_DEBUG_TYPE_CODEVIEW 2 | ||
| 49 | #endif | ||
| 50 | |||
| 51 | +#define IMAGE_FILE_EXPORT_DIRECTORY 0 | ||
| 52 | #define IMAGE_FILE_DEBUG_DIRECTORY 6 | ||
| 53 | |||
| 54 | typedef struct guid_t { | ||
| 55 | diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | 56 | index XXXXXXX..XXXXXXX 100644 |
| 48 | --- a/target/arm/helper.c | 57 | --- a/contrib/elf2dmp/main.c |
| 49 | +++ b/target/arm/helper.c | 58 | +++ b/contrib/elf2dmp/main.c |
| 50 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 59 | @@ -XXX,XX +XXX,XX @@ |
| 51 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, | 60 | |
| 52 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, | 61 | #define SYM_URL_BASE "https://msdl.microsoft.com/download/symbols/" |
| 53 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | 62 | #define PDB_NAME "ntkrnlmp.pdb" |
| 54 | - .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU, | 63 | +#define PE_NAME "ntoskrnl.exe" |
| 55 | + .access = PL2_RW, | 64 | |
| 56 | + .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | 65 | #define INITIAL_MXCSR 0x1f80 |
| 57 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, | 66 | |
| 58 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, | 67 | @@ -XXX,XX +XXX,XX @@ static int write_dump(struct pa_space *ps, |
| 59 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | 68 | return fclose(dmp_file); |
| 60 | - .access = PL2_RW, .resetvalue = 0, | 69 | } |
| 61 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | 70 | |
| 62 | .writefn = dacr_write, .raw_writefn = raw_write, | 71 | +static bool pe_check_export_name(uint64_t base, void *start_addr, |
| 63 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | 72 | + struct va_space *vs) |
| 64 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | 73 | +{ |
| 65 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | 74 | + IMAGE_EXPORT_DIRECTORY export_dir; |
| 66 | - .access = PL2_RW, .resetvalue = 0, | 75 | + const char *pe_name; |
| 67 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | 76 | + |
| 68 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | 77 | + if (pe_get_data_dir_entry(base, start_addr, IMAGE_FILE_EXPORT_DIRECTORY, |
| 69 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | 78 | + &export_dir, sizeof(export_dir), vs)) { |
| 70 | .type = ARM_CP_ALIAS, | 79 | + return false; |
| 71 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
| 72 | .writefn = tlbimva_hyp_is_write }, | ||
| 73 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, | ||
| 74 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | ||
| 75 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
| 76 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 77 | .writefn = tlbi_aa64_alle2_write }, | ||
| 78 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, | ||
| 79 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | ||
| 80 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
| 81 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 82 | .writefn = tlbi_aa64_vae2_write }, | ||
| 83 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, | ||
| 84 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | ||
| 85 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 86 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 87 | .writefn = tlbi_aa64_vae2_write }, | ||
| 88 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | ||
| 89 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | ||
| 90 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 91 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 92 | .writefn = tlbi_aa64_alle2is_write }, | ||
| 93 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, | ||
| 94 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | ||
| 95 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
| 96 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 97 | .writefn = tlbi_aa64_vae2is_write }, | ||
| 98 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, | ||
| 99 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | ||
| 100 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 101 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 102 | .writefn = tlbi_aa64_vae2is_write }, | ||
| 103 | #ifndef CONFIG_USER_ONLY | ||
| 104 | /* Unlike the other EL2-related AT operations, these must | ||
| 105 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
| 106 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | ||
| 107 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | ||
| 108 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
| 109 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
| 110 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 111 | + .writefn = ats_write64 }, | ||
| 112 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | ||
| 113 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | ||
| 114 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
| 115 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
| 116 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 117 | + .writefn = ats_write64 }, | ||
| 118 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE | ||
| 119 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | ||
| 120 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | ||
| 121 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
| 122 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | ||
| 123 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | ||
| 124 | .access = PL2_RW, .accessfn = access_tda, | ||
| 125 | - .type = ARM_CP_NOP }, | ||
| 126 | + .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, | ||
| 127 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
| 128 | * Channel but Linux may try to access this register. The 32-bit | ||
| 129 | * alias is DBGDCCINT. | ||
| 130 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
| 131 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
| 132 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, | ||
| 133 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | ||
| 134 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 135 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 136 | .writefn = tlbi_aa64_rvae2is_write }, | ||
| 137 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | ||
| 138 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | ||
| 139 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 140 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 141 | .writefn = tlbi_aa64_rvae2is_write }, | ||
| 142 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | ||
| 143 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | ||
| 144 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
| 145 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
| 146 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, | ||
| 147 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | ||
| 148 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 149 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 150 | .writefn = tlbi_aa64_rvae2is_write }, | ||
| 151 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | ||
| 152 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | ||
| 153 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 154 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 155 | .writefn = tlbi_aa64_rvae2is_write }, | ||
| 156 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | ||
| 157 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | ||
| 158 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 159 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 160 | .writefn = tlbi_aa64_rvae2_write }, | ||
| 161 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | ||
| 162 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | ||
| 163 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 164 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 165 | .writefn = tlbi_aa64_rvae2_write }, | ||
| 166 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | ||
| 167 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | ||
| 168 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
| 169 | .writefn = tlbi_aa64_vae1is_write }, | ||
| 170 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, | ||
| 171 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | ||
| 172 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 173 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 174 | .writefn = tlbi_aa64_alle2is_write }, | ||
| 175 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, | ||
| 176 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | ||
| 177 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 178 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 179 | .writefn = tlbi_aa64_vae2is_write }, | ||
| 180 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, | ||
| 181 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | ||
| 182 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
| 183 | .writefn = tlbi_aa64_alle1is_write }, | ||
| 184 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, | ||
| 185 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | ||
| 186 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 187 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
| 188 | .writefn = tlbi_aa64_vae2is_write }, | ||
| 189 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, | ||
| 190 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | ||
| 191 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 192 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
| 193 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
| 194 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
| 195 | - .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, | ||
| 196 | + .resetvalue = cpu->midr, | ||
| 197 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
| 198 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | ||
| 199 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
| 200 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
| 201 | .access = PL2_RW, .resetvalue = cpu->midr, | ||
| 202 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
| 203 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
| 204 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, | ||
| 205 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
| 206 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
| 207 | - .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, | ||
| 208 | + .resetvalue = vmpidr_def, | ||
| 209 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
| 210 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | ||
| 211 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
| 212 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
| 213 | - .access = PL2_RW, | ||
| 214 | - .resetvalue = vmpidr_def, | ||
| 215 | + .access = PL2_RW, .resetvalue = vmpidr_def, | ||
| 216 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
| 217 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | ||
| 218 | }; | ||
| 219 | define_arm_cp_regs(cpu, vpidr_regs); | ||
| 220 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 221 | int crm, int opc1, int opc2, | ||
| 222 | const char *name) | ||
| 223 | { | ||
| 224 | + CPUARMState *env = &cpu->env; | ||
| 225 | uint32_t key; | ||
| 226 | ARMCPRegInfo *r2; | ||
| 227 | bool is64 = r->type & ARM_CP_64BIT; | ||
| 228 | bool ns = secstate & ARM_CP_SECSTATE_NS; | ||
| 229 | int cp = r->cp; | ||
| 230 | - bool isbanked; | ||
| 231 | size_t name_len; | ||
| 232 | + bool make_const; | ||
| 233 | |||
| 234 | switch (state) { | ||
| 235 | case ARM_CP_STATE_AA32: | ||
| 236 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
| 237 | } | ||
| 238 | } | ||
| 239 | |||
| 240 | + /* | ||
| 241 | + * Eliminate registers that are not present because the EL is missing. | ||
| 242 | + * Doing this here makes it easier to put all registers for a given | ||
| 243 | + * feature into the same ARMCPRegInfo array and define them all at once. | ||
| 244 | + */ | ||
| 245 | + make_const = false; | ||
| 246 | + if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
| 247 | + /* | ||
| 248 | + * An EL2 register without EL2 but with EL3 is (usually) RES0. | ||
| 249 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | ||
| 250 | + */ | ||
| 251 | + int min_el = ctz32(r->access) / 2; | ||
| 252 | + if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | ||
| 253 | + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | ||
| 254 | + return; | ||
| 255 | + } | ||
| 256 | + make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | ||
| 257 | + } | ||
| 258 | + } else { | ||
| 259 | + CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | ||
| 260 | + ? PL2_RW : PL1_RW); | ||
| 261 | + if ((r->access & max_el) == 0) { | ||
| 262 | + return; | ||
| 263 | + } | ||
| 264 | + } | 80 | + } |
| 265 | + | 81 | + |
| 266 | /* Combine cpreg and name into one allocation. */ | 82 | + pe_name = va_space_resolve(vs, base + export_dir.Name); |
| 267 | name_len = strlen(name) + 1; | 83 | + if (!pe_name) { |
| 268 | r2 = g_malloc(sizeof(*r2) + name_len); | 84 | + return false; |
| 269 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 85 | + } |
| 270 | r2->opaque = opaque; | 86 | + |
| 271 | } | 87 | + return !strcmp(pe_name, PE_NAME); |
| 272 | 88 | +} | |
| 273 | - isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | 89 | + |
| 274 | - if (isbanked) { | 90 | static int pe_get_pdb_symstore_hash(uint64_t base, void *start_addr, |
| 275 | + if (make_const) { | 91 | char *hash, struct va_space *vs) |
| 276 | + /* This should not have been a very special register to begin. */ | 92 | { |
| 277 | + int old_special = r2->type & ARM_CP_SPECIAL_MASK; | 93 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[]) |
| 278 | + assert(old_special == 0 || old_special == ARM_CP_NOP); | 94 | uint64_t KdDebuggerDataBlock; |
| 279 | /* | 95 | KDDEBUGGER_DATA64 *kdbg; |
| 280 | - * Register is banked (using both entries in array). | 96 | uint64_t KdVersionBlock; |
| 281 | - * Overwriting fieldoffset as the array is only used to define | 97 | + bool kernel_found = false; |
| 282 | - * banked registers but later only fieldoffset is used. | 98 | |
| 283 | + * Set the special function to CONST, retaining the other flags. | 99 | if (argc != 3) { |
| 284 | + * This is important for e.g. ARM_CP_SVE so that we still | 100 | eprintf("usage:\n\t%s elf_file dmp_file\n", argv[0]); |
| 285 | + * take the SVE trap if CPTR_EL3.EZ == 0. | 101 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[]) |
| 286 | */ | 102 | } |
| 287 | - r2->fieldoffset = r->bank_fieldoffsets[ns]; | 103 | |
| 288 | - } | 104 | if (*(uint16_t *)nt_start_addr == 0x5a4d) { /* MZ */ |
| 289 | + r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; | 105 | - break; |
| 290 | + /* | 106 | + if (pe_check_export_name(KernBase, nt_start_addr, &vs)) { |
| 291 | + * Usually, these registers become RES0, but there are a few | 107 | + kernel_found = true; |
| 292 | + * special cases like VPIDR_EL2 which have a constant non-zero | 108 | + break; |
| 293 | + * value with writes ignored. | ||
| 294 | + */ | ||
| 295 | + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | ||
| 296 | + r2->resetvalue = 0; | ||
| 297 | + } | ||
| 298 | + /* | ||
| 299 | + * ARM_CP_CONST has precedence, so removing the callbacks and | ||
| 300 | + * offsets are not strictly necessary, but it is potentially | ||
| 301 | + * less confusing to debug later. | ||
| 302 | + */ | ||
| 303 | + r2->readfn = NULL; | ||
| 304 | + r2->writefn = NULL; | ||
| 305 | + r2->raw_readfn = NULL; | ||
| 306 | + r2->raw_writefn = NULL; | ||
| 307 | + r2->resetfn = NULL; | ||
| 308 | + r2->fieldoffset = 0; | ||
| 309 | + r2->bank_fieldoffsets[0] = 0; | ||
| 310 | + r2->bank_fieldoffsets[1] = 0; | ||
| 311 | + } else { | ||
| 312 | + bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | ||
| 313 | |||
| 314 | - if (state == ARM_CP_STATE_AA32) { | ||
| 315 | if (isbanked) { | ||
| 316 | /* | ||
| 317 | - * If the register is banked then we don't need to migrate or | ||
| 318 | - * reset the 32-bit instance in certain cases: | ||
| 319 | - * | ||
| 320 | - * 1) If the register has both 32-bit and 64-bit instances then we | ||
| 321 | - * can count on the 64-bit instance taking care of the | ||
| 322 | - * non-secure bank. | ||
| 323 | - * 2) If ARMv8 is enabled then we can count on a 64-bit version | ||
| 324 | - * taking care of the secure bank. This requires that separate | ||
| 325 | - * 32 and 64-bit definitions are provided. | ||
| 326 | + * Register is banked (using both entries in array). | ||
| 327 | + * Overwriting fieldoffset as the array is only used to define | ||
| 328 | + * banked registers but later only fieldoffset is used. | ||
| 329 | */ | ||
| 330 | - if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
| 331 | - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | ||
| 332 | + r2->fieldoffset = r->bank_fieldoffsets[ns]; | ||
| 333 | + } | ||
| 334 | + if (state == ARM_CP_STATE_AA32) { | ||
| 335 | + if (isbanked) { | ||
| 336 | + /* | ||
| 337 | + * If the register is banked then we don't need to migrate or | ||
| 338 | + * reset the 32-bit instance in certain cases: | ||
| 339 | + * | ||
| 340 | + * 1) If the register has both 32-bit and 64-bit instances | ||
| 341 | + * then we can count on the 64-bit instance taking care | ||
| 342 | + * of the non-secure bank. | ||
| 343 | + * 2) If ARMv8 is enabled then we can count on a 64-bit | ||
| 344 | + * version taking care of the secure bank. This requires | ||
| 345 | + * that separate 32 and 64-bit definitions are provided. | ||
| 346 | + */ | ||
| 347 | + if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
| 348 | + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | ||
| 349 | + r2->type |= ARM_CP_ALIAS; | ||
| 350 | + } | ||
| 351 | + } else if ((secstate != r->secure) && !ns) { | ||
| 352 | + /* | ||
| 353 | + * The register is not banked so we only want to allow | ||
| 354 | + * migration of the non-secure instance. | ||
| 355 | + */ | ||
| 356 | r2->type |= ARM_CP_ALIAS; | ||
| 357 | } | ||
| 358 | - } else if ((secstate != r->secure) && !ns) { | ||
| 359 | - /* | ||
| 360 | - * The register is not banked so we only want to allow migration | ||
| 361 | - * of the non-secure instance. | ||
| 362 | - */ | ||
| 363 | - r2->type |= ARM_CP_ALIAS; | ||
| 364 | - } | ||
| 365 | |||
| 366 | - if (HOST_BIG_ENDIAN && | ||
| 367 | - r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
| 368 | - r2->fieldoffset += sizeof(uint32_t); | ||
| 369 | + if (HOST_BIG_ENDIAN && | ||
| 370 | + r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
| 371 | + r2->fieldoffset += sizeof(uint32_t); | ||
| 372 | + } | 109 | + } |
| 373 | } | 110 | } |
| 374 | } | 111 | } |
| 375 | 112 | ||
| 376 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 113 | - if (!nt_start_addr) { |
| 377 | * multiple times. Special registers (ie NOP/WFI) are | 114 | + if (!kernel_found) { |
| 378 | * never migratable and not even raw-accessible. | 115 | eprintf("Failed to find NT kernel image\n"); |
| 379 | */ | 116 | err = 1; |
| 380 | - if (r->type & ARM_CP_SPECIAL_MASK) { | 117 | goto out_ps; |
| 381 | + if (r2->type & ARM_CP_SPECIAL_MASK) { | ||
| 382 | r2->type |= ARM_CP_NO_RAW; | ||
| 383 | } | ||
| 384 | if (((r->crm == CP_ANY) && crm != 0) || | ||
| 385 | -- | 118 | -- |
| 386 | 2.25.1 | 119 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local | ||
| 4 | vpidr_regs definition, and rely on the squashing to ARM_CP_CONST | ||
| 5 | while registering for v8. | ||
| 6 | |||
| 7 | This is a behavior change for v7 cpus with Security Extensions and | ||
| 8 | without Virtualization Extensions, in that the virtualization cpregs | ||
| 9 | are now correctly not present. This would be a migration compatibility | ||
| 10 | break, except that we have an existing bug in which migration of 32-bit | ||
| 11 | cpus with Security Extensions enabled does not work. | ||
| 12 | |||
| 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 15 | Message-id: 20220506180242.216785-3-richard.henderson@linaro.org | ||
| 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 17 | --- | ||
| 18 | target/arm/helper.c | 158 ++++---------------------------------------- | ||
| 19 | 1 file changed, 13 insertions(+), 145 deletions(-) | ||
| 20 | |||
| 21 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/target/arm/helper.c | ||
| 24 | +++ b/target/arm/helper.c | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
| 26 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | ||
| 27 | }; | ||
| 28 | |||
| 29 | -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ | ||
| 30 | -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | ||
| 31 | - { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 32 | - .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | ||
| 33 | - .access = PL2_RW, | ||
| 34 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | ||
| 35 | - { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 36 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | ||
| 37 | - .access = PL2_RW, | ||
| 38 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 39 | - { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 40 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | ||
| 41 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 42 | - { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 43 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | ||
| 44 | - .access = PL2_RW, | ||
| 45 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 46 | - { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 47 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | ||
| 48 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 49 | - { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 50 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | ||
| 51 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
| 52 | - .resetvalue = 0 }, | ||
| 53 | - { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | ||
| 54 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | ||
| 55 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 56 | - { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 57 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | ||
| 58 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
| 59 | - .resetvalue = 0 }, | ||
| 60 | - { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, | ||
| 61 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | ||
| 62 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
| 63 | - .resetvalue = 0 }, | ||
| 64 | - { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 65 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | ||
| 66 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
| 67 | - .resetvalue = 0 }, | ||
| 68 | - { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 69 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | ||
| 70 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
| 71 | - .resetvalue = 0 }, | ||
| 72 | - { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 73 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | ||
| 74 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 75 | - { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 76 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | ||
| 77 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
| 78 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 79 | - { .name = "VTTBR", .state = ARM_CP_STATE_AA32, | ||
| 80 | - .cp = 15, .opc1 = 6, .crm = 2, | ||
| 81 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
| 82 | - .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 83 | - { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | ||
| 84 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | ||
| 85 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 86 | - { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 87 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | ||
| 88 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 89 | - { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 90 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | ||
| 91 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 92 | - { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, | ||
| 93 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | ||
| 94 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 95 | - { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | ||
| 96 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
| 97 | - .resetvalue = 0 }, | ||
| 98 | - { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 99 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | ||
| 100 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 101 | - { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, | ||
| 102 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | ||
| 103 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 104 | - { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | ||
| 105 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
| 106 | - .resetvalue = 0 }, | ||
| 107 | - { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, | ||
| 108 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | ||
| 109 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 110 | - { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | ||
| 111 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
| 112 | - .resetvalue = 0 }, | ||
| 113 | - { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 114 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | ||
| 115 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 116 | - { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 117 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | ||
| 118 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 119 | - { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 120 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | ||
| 121 | - .access = PL2_RW, .accessfn = access_tda, | ||
| 122 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 123 | - { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 124 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | ||
| 125 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
| 126 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 127 | - { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 128 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | ||
| 129 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 130 | - { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 131 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | ||
| 132 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 133 | - { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | ||
| 134 | - .type = ARM_CP_CONST, | ||
| 135 | - .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | ||
| 136 | - .access = PL2_RW, .resetvalue = 0 }, | ||
| 137 | -}; | ||
| 138 | - | ||
| 139 | -/* Ditto, but for registers which exist in ARMv8 but not v7 */ | ||
| 140 | -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | ||
| 141 | - { .name = "HCR2", .state = ARM_CP_STATE_AA32, | ||
| 142 | - .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | ||
| 143 | - .access = PL2_RW, | ||
| 144 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 145 | -}; | ||
| 146 | - | ||
| 147 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
| 148 | { | ||
| 149 | ARMCPU *cpu = env_archcpu(env); | ||
| 150 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 151 | define_arm_cp_regs(cpu, v8_idregs); | ||
| 152 | define_arm_cp_regs(cpu, v8_cp_reginfo); | ||
| 153 | } | ||
| 154 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | ||
| 155 | + | ||
| 156 | + /* | ||
| 157 | + * Register the base EL2 cpregs. | ||
| 158 | + * Pre v8, these registers are implemented only as part of the | ||
| 159 | + * Virtualization Extensions (EL2 present). Beginning with v8, | ||
| 160 | + * if EL2 is missing but EL3 is enabled, mostly these become | ||
| 161 | + * RES0 from EL3, with some specific exceptions. | ||
| 162 | + */ | ||
| 163 | + if (arm_feature(env, ARM_FEATURE_EL2) | ||
| 164 | + || (arm_feature(env, ARM_FEATURE_EL3) | ||
| 165 | + && arm_feature(env, ARM_FEATURE_V8))) { | ||
| 166 | uint64_t vmpidr_def = mpidr_read_val(env); | ||
| 167 | ARMCPRegInfo vpidr_regs[] = { | ||
| 168 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
| 169 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 170 | }; | ||
| 171 | define_one_arm_cp_reg(cpu, &rvbar); | ||
| 172 | } | ||
| 173 | - } else { | ||
| 174 | - /* If EL2 is missing but higher ELs are enabled, we need to | ||
| 175 | - * register the no_el2 reginfos. | ||
| 176 | - */ | ||
| 177 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
| 178 | - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value | ||
| 179 | - * of MIDR_EL1 and MPIDR_EL1. | ||
| 180 | - */ | ||
| 181 | - ARMCPRegInfo vpidr_regs[] = { | ||
| 182 | - { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 183 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
| 184 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
| 185 | - .type = ARM_CP_CONST, .resetvalue = cpu->midr, | ||
| 186 | - .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
| 187 | - { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 188 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
| 189 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
| 190 | - .type = ARM_CP_NO_RAW, | ||
| 191 | - .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | ||
| 192 | - }; | ||
| 193 | - define_arm_cp_regs(cpu, vpidr_regs); | ||
| 194 | - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); | ||
| 195 | - if (arm_feature(env, ARM_FEATURE_V8)) { | ||
| 196 | - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | ||
| 197 | - } | ||
| 198 | - } | ||
| 199 | } | ||
| 200 | + | ||
| 201 | + /* Register the base EL3 cpregs. */ | ||
| 202 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
| 203 | define_arm_cp_regs(cpu, el3_cp_reginfo); | ||
| 204 | ARMCPRegInfo el3_regs[] = { | ||
| 205 | -- | ||
| 206 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Drop zcr_no_el2_reginfo and merge the 3 registers into one array, | ||
| 4 | now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped | ||
| 5 | while registering. | ||
| 6 | |||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220506180242.216785-4-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/helper.c | 55 ++++++++++++++------------------------------- | ||
| 13 | 1 file changed, 17 insertions(+), 38 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/helper.c | ||
| 18 | +++ b/target/arm/helper.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 20 | } | ||
| 21 | } | ||
| 22 | |||
| 23 | -static const ARMCPRegInfo zcr_el1_reginfo = { | ||
| 24 | - .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 25 | - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | ||
| 26 | - .access = PL1_RW, .type = ARM_CP_SVE, | ||
| 27 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | ||
| 28 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
| 29 | -}; | ||
| 30 | - | ||
| 31 | -static const ARMCPRegInfo zcr_el2_reginfo = { | ||
| 32 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
| 33 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
| 34 | - .access = PL2_RW, .type = ARM_CP_SVE, | ||
| 35 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | ||
| 36 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
| 37 | -}; | ||
| 38 | - | ||
| 39 | -static const ARMCPRegInfo zcr_no_el2_reginfo = { | ||
| 40 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
| 41 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
| 42 | - .access = PL2_RW, .type = ARM_CP_SVE, | ||
| 43 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore | ||
| 44 | -}; | ||
| 45 | - | ||
| 46 | -static const ARMCPRegInfo zcr_el3_reginfo = { | ||
| 47 | - .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
| 48 | - .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
| 49 | - .access = PL3_RW, .type = ARM_CP_SVE, | ||
| 50 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
| 51 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
| 52 | +static const ARMCPRegInfo zcr_reginfo[] = { | ||
| 53 | + { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 54 | + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | ||
| 55 | + .access = PL1_RW, .type = ARM_CP_SVE, | ||
| 56 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | ||
| 57 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
| 58 | + { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
| 59 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
| 60 | + .access = PL2_RW, .type = ARM_CP_SVE, | ||
| 61 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | ||
| 62 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
| 63 | + { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
| 64 | + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
| 65 | + .access = PL3_RW, .type = ARM_CP_SVE, | ||
| 66 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
| 67 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
| 68 | }; | ||
| 69 | |||
| 70 | void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
| 71 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 72 | } | ||
| 73 | |||
| 74 | if (cpu_isar_feature(aa64_sve, cpu)) { | ||
| 75 | - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); | ||
| 76 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | ||
| 77 | - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | ||
| 78 | - } else { | ||
| 79 | - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | ||
| 80 | - } | ||
| 81 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
| 82 | - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | ||
| 83 | - } | ||
| 84 | + define_arm_cp_regs(cpu, zcr_reginfo); | ||
| 85 | } | ||
| 86 | |||
| 87 | #ifdef TARGET_AARCH64 | ||
| 88 | -- | ||
| 89 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | This register is present for either VHE or Debugv8p2. | ||
| 4 | |||
| 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220506180242.216785-5-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/helper.c | 15 +++++++++++---- | ||
| 11 | 1 file changed, 11 insertions(+), 4 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/helper.c | ||
| 16 | +++ b/target/arm/helper.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = { | ||
| 18 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 19 | }; | ||
| 20 | |||
| 21 | +static const ARMCPRegInfo contextidr_el2 = { | ||
| 22 | + .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
| 23 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | ||
| 24 | + .access = PL2_RW, | ||
| 25 | + .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) | ||
| 26 | +}; | ||
| 27 | + | ||
| 28 | static const ARMCPRegInfo vhe_reginfo[] = { | ||
| 29 | - { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
| 30 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | ||
| 31 | - .access = PL2_RW, | ||
| 32 | - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, | ||
| 33 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, | ||
| 34 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | ||
| 35 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | ||
| 36 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 37 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | ||
| 38 | } | ||
| 39 | |||
| 40 | + if (cpu_isar_feature(aa64_vh, cpu) || | ||
| 41 | + cpu_isar_feature(aa64_debugv8p2, cpu)) { | ||
| 42 | + define_one_arm_cp_reg(cpu, &contextidr_el2); | ||
| 43 | + } | ||
| 44 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | ||
| 45 | define_arm_cp_regs(cpu, vhe_reginfo); | ||
| 46 | } | ||
| 47 | -- | ||
| 48 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Instead of starting with cortex-a15 and adding v8 features to | ||
| 4 | a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. | ||
| 5 | This fixes the long-standing to-do where we only enabled v8 | ||
| 6 | features for user-only. | ||
| 7 | |||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20220506180242.216785-7-richard.henderson@linaro.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- | ||
| 14 | 1 file changed, 92 insertions(+), 59 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/cpu_tcg.c | ||
| 19 | +++ b/target/arm/cpu_tcg.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
| 21 | static void arm_max_initfn(Object *obj) | ||
| 22 | { | ||
| 23 | ARMCPU *cpu = ARM_CPU(obj); | ||
| 24 | + uint32_t t; | ||
| 25 | |||
| 26 | - cortex_a15_initfn(obj); | ||
| 27 | + /* aarch64_a57_initfn, advertising none of the aarch64 features */ | ||
| 28 | + cpu->dtb_compatible = "arm,cortex-a57"; | ||
| 29 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
| 30 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
| 31 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
| 32 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
| 33 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
| 34 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
| 35 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
| 36 | + cpu->midr = 0x411fd070; | ||
| 37 | + cpu->revidr = 0x00000000; | ||
| 38 | + cpu->reset_fpsid = 0x41034070; | ||
| 39 | + cpu->isar.mvfr0 = 0x10110222; | ||
| 40 | + cpu->isar.mvfr1 = 0x12111111; | ||
| 41 | + cpu->isar.mvfr2 = 0x00000043; | ||
| 42 | + cpu->ctr = 0x8444c004; | ||
| 43 | + cpu->reset_sctlr = 0x00c50838; | ||
| 44 | + cpu->isar.id_pfr0 = 0x00000131; | ||
| 45 | + cpu->isar.id_pfr1 = 0x00011011; | ||
| 46 | + cpu->isar.id_dfr0 = 0x03010066; | ||
| 47 | + cpu->id_afr0 = 0x00000000; | ||
| 48 | + cpu->isar.id_mmfr0 = 0x10101105; | ||
| 49 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
| 50 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
| 51 | + cpu->isar.id_mmfr3 = 0x02102211; | ||
| 52 | + cpu->isar.id_isar0 = 0x02101110; | ||
| 53 | + cpu->isar.id_isar1 = 0x13112111; | ||
| 54 | + cpu->isar.id_isar2 = 0x21232042; | ||
| 55 | + cpu->isar.id_isar3 = 0x01112131; | ||
| 56 | + cpu->isar.id_isar4 = 0x00011142; | ||
| 57 | + cpu->isar.id_isar5 = 0x00011121; | ||
| 58 | + cpu->isar.id_isar6 = 0; | ||
| 59 | + cpu->isar.dbgdidr = 0x3516d000; | ||
| 60 | + cpu->clidr = 0x0a200023; | ||
| 61 | + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
| 62 | + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | ||
| 63 | + cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
| 64 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
| 65 | |||
| 66 | - /* old-style VFP short-vector support */ | ||
| 67 | - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
| 68 | + /* Add additional features supported by QEMU */ | ||
| 69 | + t = cpu->isar.id_isar5; | ||
| 70 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
| 71 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
| 72 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
| 73 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
| 74 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
| 75 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
| 76 | + cpu->isar.id_isar5 = t; | ||
| 77 | + | ||
| 78 | + t = cpu->isar.id_isar6; | ||
| 79 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
| 80 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
| 81 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
| 82 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
| 83 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
| 84 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
| 85 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
| 86 | + cpu->isar.id_isar6 = t; | ||
| 87 | + | ||
| 88 | + t = cpu->isar.mvfr1; | ||
| 89 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
| 90 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
| 91 | + cpu->isar.mvfr1 = t; | ||
| 92 | + | ||
| 93 | + t = cpu->isar.mvfr2; | ||
| 94 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
| 95 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
| 96 | + cpu->isar.mvfr2 = t; | ||
| 97 | + | ||
| 98 | + t = cpu->isar.id_mmfr3; | ||
| 99 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
| 100 | + cpu->isar.id_mmfr3 = t; | ||
| 101 | + | ||
| 102 | + t = cpu->isar.id_mmfr4; | ||
| 103 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
| 104 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
| 105 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
| 106 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
| 107 | + cpu->isar.id_mmfr4 = t; | ||
| 108 | + | ||
| 109 | + t = cpu->isar.id_pfr0; | ||
| 110 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
| 111 | + cpu->isar.id_pfr0 = t; | ||
| 112 | + | ||
| 113 | + t = cpu->isar.id_pfr2; | ||
| 114 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
| 115 | + cpu->isar.id_pfr2 = t; | ||
| 116 | |||
| 117 | #ifdef CONFIG_USER_ONLY | ||
| 118 | /* | ||
| 119 | - * We don't set these in system emulation mode for the moment, | ||
| 120 | - * since we don't correctly set (all of) the ID registers to | ||
| 121 | - * advertise them. | ||
| 122 | + * Break with true ARMv8 and add back old-style VFP short-vector support. | ||
| 123 | + * Only do this for user-mode, where -cpu max is the default, so that | ||
| 124 | + * older v6 and v7 programs are more likely to work without adjustment. | ||
| 125 | */ | ||
| 126 | - set_feature(&cpu->env, ARM_FEATURE_V8); | ||
| 127 | - { | ||
| 128 | - uint32_t t; | ||
| 129 | - | ||
| 130 | - t = cpu->isar.id_isar5; | ||
| 131 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
| 132 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
| 133 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
| 134 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
| 135 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
| 136 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
| 137 | - cpu->isar.id_isar5 = t; | ||
| 138 | - | ||
| 139 | - t = cpu->isar.id_isar6; | ||
| 140 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
| 141 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
| 142 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
| 143 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
| 144 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
| 145 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
| 146 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
| 147 | - cpu->isar.id_isar6 = t; | ||
| 148 | - | ||
| 149 | - t = cpu->isar.mvfr1; | ||
| 150 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
| 151 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
| 152 | - cpu->isar.mvfr1 = t; | ||
| 153 | - | ||
| 154 | - t = cpu->isar.mvfr2; | ||
| 155 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
| 156 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
| 157 | - cpu->isar.mvfr2 = t; | ||
| 158 | - | ||
| 159 | - t = cpu->isar.id_mmfr3; | ||
| 160 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
| 161 | - cpu->isar.id_mmfr3 = t; | ||
| 162 | - | ||
| 163 | - t = cpu->isar.id_mmfr4; | ||
| 164 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
| 165 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
| 166 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
| 167 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
| 168 | - cpu->isar.id_mmfr4 = t; | ||
| 169 | - | ||
| 170 | - t = cpu->isar.id_pfr0; | ||
| 171 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
| 172 | - cpu->isar.id_pfr0 = t; | ||
| 173 | - | ||
| 174 | - t = cpu->isar.id_pfr2; | ||
| 175 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
| 176 | - cpu->isar.id_pfr2 = t; | ||
| 177 | - } | ||
| 178 | -#endif /* CONFIG_USER_ONLY */ | ||
| 179 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
| 180 | +#endif | ||
| 181 | } | ||
| 182 | #endif /* !TARGET_AARCH64 */ | ||
| 183 | |||
| 184 | -- | ||
| 185 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | We set this for qemu-system-aarch64, but failed to do so | ||
| 4 | for the strictly 32-bit emulation. | ||
| 5 | |||
| 6 | Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220506180242.216785-8-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/cpu_tcg.c | 4 ++++ | ||
| 13 | 1 file changed, 4 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/cpu_tcg.c | ||
| 18 | +++ b/target/arm/cpu_tcg.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
| 20 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
| 21 | cpu->isar.id_pfr2 = t; | ||
| 22 | |||
| 23 | + t = cpu->isar.id_dfr0; | ||
| 24 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
| 25 | + cpu->isar.id_dfr0 = t; | ||
| 26 | + | ||
| 27 | #ifdef CONFIG_USER_ONLY | ||
| 28 | /* | ||
| 29 | * Break with true ARMv8 and add back old-style VFP short-vector support. | ||
| 30 | -- | ||
| 31 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Share the code to set AArch32 max features so that we no | ||
| 4 | longer have code drift between qemu{-system,}-{arm,aarch64}. | ||
| 5 | |||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20220506180242.216785-9-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/internals.h | 2 + | ||
| 12 | target/arm/cpu64.c | 50 +----------------- | ||
| 13 | target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- | ||
| 14 | 3 files changed, 65 insertions(+), 101 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/internals.h | ||
| 19 | +++ b/target/arm/internals.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | ||
| 21 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | ||
| 22 | #endif | ||
| 23 | |||
| 24 | +void aa32_max_features(ARMCPU *cpu); | ||
| 25 | + | ||
| 26 | #endif | ||
| 27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | ||
| 29 | --- a/target/arm/cpu64.c | ||
| 30 | +++ b/target/arm/cpu64.c | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 32 | { | ||
| 33 | ARMCPU *cpu = ARM_CPU(obj); | ||
| 34 | uint64_t t; | ||
| 35 | - uint32_t u; | ||
| 36 | |||
| 37 | if (kvm_enabled() || hvf_enabled()) { | ||
| 38 | /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 40 | t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
| 41 | cpu->isar.id_aa64zfr0 = t; | ||
| 42 | |||
| 43 | - /* Replicate the same data to the 32-bit id registers. */ | ||
| 44 | - u = cpu->isar.id_isar5; | ||
| 45 | - u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ | ||
| 46 | - u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); | ||
| 47 | - u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); | ||
| 48 | - u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); | ||
| 49 | - u = FIELD_DP32(u, ID_ISAR5, RDM, 1); | ||
| 50 | - u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); | ||
| 51 | - cpu->isar.id_isar5 = u; | ||
| 52 | - | ||
| 53 | - u = cpu->isar.id_isar6; | ||
| 54 | - u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); | ||
| 55 | - u = FIELD_DP32(u, ID_ISAR6, DP, 1); | ||
| 56 | - u = FIELD_DP32(u, ID_ISAR6, FHM, 1); | ||
| 57 | - u = FIELD_DP32(u, ID_ISAR6, SB, 1); | ||
| 58 | - u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); | ||
| 59 | - u = FIELD_DP32(u, ID_ISAR6, BF16, 1); | ||
| 60 | - u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); | ||
| 61 | - cpu->isar.id_isar6 = u; | ||
| 62 | - | ||
| 63 | - u = cpu->isar.id_pfr0; | ||
| 64 | - u = FIELD_DP32(u, ID_PFR0, DIT, 1); | ||
| 65 | - cpu->isar.id_pfr0 = u; | ||
| 66 | - | ||
| 67 | - u = cpu->isar.id_pfr2; | ||
| 68 | - u = FIELD_DP32(u, ID_PFR2, SSBS, 1); | ||
| 69 | - cpu->isar.id_pfr2 = u; | ||
| 70 | - | ||
| 71 | - u = cpu->isar.id_mmfr3; | ||
| 72 | - u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
| 73 | - cpu->isar.id_mmfr3 = u; | ||
| 74 | - | ||
| 75 | - u = cpu->isar.id_mmfr4; | ||
| 76 | - u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
| 77 | - u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
| 78 | - u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
| 79 | - u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
| 80 | - cpu->isar.id_mmfr4 = u; | ||
| 81 | - | ||
| 82 | t = cpu->isar.id_aa64dfr0; | ||
| 83 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
| 84 | cpu->isar.id_aa64dfr0 = t; | ||
| 85 | |||
| 86 | - u = cpu->isar.id_dfr0; | ||
| 87 | - u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
| 88 | - cpu->isar.id_dfr0 = u; | ||
| 89 | - | ||
| 90 | - u = cpu->isar.mvfr1; | ||
| 91 | - u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
| 92 | - u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
| 93 | - cpu->isar.mvfr1 = u; | ||
| 94 | + /* Replicate the same data to the 32-bit id registers. */ | ||
| 95 | + aa32_max_features(cpu); | ||
| 96 | |||
| 97 | #ifdef CONFIG_USER_ONLY | ||
| 98 | /* | ||
| 99 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 100 | index XXXXXXX..XXXXXXX 100644 | ||
| 101 | --- a/target/arm/cpu_tcg.c | ||
| 102 | +++ b/target/arm/cpu_tcg.c | ||
| 103 | @@ -XXX,XX +XXX,XX @@ | ||
| 104 | #endif | ||
| 105 | #include "cpregs.h" | ||
| 106 | |||
| 107 | + | ||
| 108 | +/* Share AArch32 -cpu max features with AArch64. */ | ||
| 109 | +void aa32_max_features(ARMCPU *cpu) | ||
| 110 | +{ | ||
| 111 | + uint32_t t; | ||
| 112 | + | ||
| 113 | + /* Add additional features supported by QEMU */ | ||
| 114 | + t = cpu->isar.id_isar5; | ||
| 115 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
| 116 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
| 117 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
| 118 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
| 119 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
| 120 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
| 121 | + cpu->isar.id_isar5 = t; | ||
| 122 | + | ||
| 123 | + t = cpu->isar.id_isar6; | ||
| 124 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
| 125 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
| 126 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
| 127 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
| 128 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
| 129 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
| 130 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
| 131 | + cpu->isar.id_isar6 = t; | ||
| 132 | + | ||
| 133 | + t = cpu->isar.mvfr1; | ||
| 134 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
| 135 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
| 136 | + cpu->isar.mvfr1 = t; | ||
| 137 | + | ||
| 138 | + t = cpu->isar.mvfr2; | ||
| 139 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
| 140 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
| 141 | + cpu->isar.mvfr2 = t; | ||
| 142 | + | ||
| 143 | + t = cpu->isar.id_mmfr3; | ||
| 144 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
| 145 | + cpu->isar.id_mmfr3 = t; | ||
| 146 | + | ||
| 147 | + t = cpu->isar.id_mmfr4; | ||
| 148 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
| 149 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
| 150 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
| 151 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
| 152 | + cpu->isar.id_mmfr4 = t; | ||
| 153 | + | ||
| 154 | + t = cpu->isar.id_pfr0; | ||
| 155 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
| 156 | + cpu->isar.id_pfr0 = t; | ||
| 157 | + | ||
| 158 | + t = cpu->isar.id_pfr2; | ||
| 159 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
| 160 | + cpu->isar.id_pfr2 = t; | ||
| 161 | + | ||
| 162 | + t = cpu->isar.id_dfr0; | ||
| 163 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
| 164 | + cpu->isar.id_dfr0 = t; | ||
| 165 | +} | ||
| 166 | + | ||
| 167 | #ifndef CONFIG_USER_ONLY | ||
| 168 | static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 169 | { | ||
| 170 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
| 171 | static void arm_max_initfn(Object *obj) | ||
| 172 | { | ||
| 173 | ARMCPU *cpu = ARM_CPU(obj); | ||
| 174 | - uint32_t t; | ||
| 175 | |||
| 176 | /* aarch64_a57_initfn, advertising none of the aarch64 features */ | ||
| 177 | cpu->dtb_compatible = "arm,cortex-a57"; | ||
| 178 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
| 179 | cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
| 180 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
| 181 | |||
| 182 | - /* Add additional features supported by QEMU */ | ||
| 183 | - t = cpu->isar.id_isar5; | ||
| 184 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
| 185 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
| 186 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
| 187 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
| 188 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
| 189 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
| 190 | - cpu->isar.id_isar5 = t; | ||
| 191 | - | ||
| 192 | - t = cpu->isar.id_isar6; | ||
| 193 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
| 194 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
| 195 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
| 196 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
| 197 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
| 198 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
| 199 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
| 200 | - cpu->isar.id_isar6 = t; | ||
| 201 | - | ||
| 202 | - t = cpu->isar.mvfr1; | ||
| 203 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
| 204 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
| 205 | - cpu->isar.mvfr1 = t; | ||
| 206 | - | ||
| 207 | - t = cpu->isar.mvfr2; | ||
| 208 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
| 209 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
| 210 | - cpu->isar.mvfr2 = t; | ||
| 211 | - | ||
| 212 | - t = cpu->isar.id_mmfr3; | ||
| 213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
| 214 | - cpu->isar.id_mmfr3 = t; | ||
| 215 | - | ||
| 216 | - t = cpu->isar.id_mmfr4; | ||
| 217 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
| 218 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
| 219 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
| 220 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
| 221 | - cpu->isar.id_mmfr4 = t; | ||
| 222 | - | ||
| 223 | - t = cpu->isar.id_pfr0; | ||
| 224 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
| 225 | - cpu->isar.id_pfr0 = t; | ||
| 226 | - | ||
| 227 | - t = cpu->isar.id_pfr2; | ||
| 228 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
| 229 | - cpu->isar.id_pfr2 = t; | ||
| 230 | - | ||
| 231 | - t = cpu->isar.id_dfr0; | ||
| 232 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
| 233 | - cpu->isar.id_dfr0 = t; | ||
| 234 | + aa32_max_features(cpu); | ||
| 235 | |||
| 236 | #ifdef CONFIG_USER_ONLY | ||
| 237 | /* | ||
| 238 | -- | ||
| 239 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Update the legacy feature names to the current names. | ||
| 4 | Provide feature names for id changes that were not marked. | ||
| 5 | Sort the field updates into increasing bitfield order. | ||
| 6 | |||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220506180242.216785-10-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/cpu64.c | 100 +++++++++++++++++++++---------------------- | ||
| 13 | target/arm/cpu_tcg.c | 48 ++++++++++----------- | ||
| 14 | 2 files changed, 74 insertions(+), 74 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/cpu64.c | ||
| 19 | +++ b/target/arm/cpu64.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 21 | cpu->midr = t; | ||
| 22 | |||
| 23 | t = cpu->isar.id_aa64isar0; | ||
| 24 | - t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ | ||
| 25 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); | ||
| 26 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ | ||
| 27 | + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ | ||
| 28 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ | ||
| 29 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ | ||
| 30 | t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | ||
| 31 | - t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); | ||
| 32 | - t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); | ||
| 33 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); | ||
| 34 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); | ||
| 35 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); | ||
| 36 | - t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); | ||
| 37 | - t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); | ||
| 38 | - t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ | ||
| 39 | - t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | ||
| 40 | - t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); | ||
| 41 | + t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ | ||
| 42 | + t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | ||
| 43 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | ||
| 44 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ | ||
| 45 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ | ||
| 46 | + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ | ||
| 47 | + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ | ||
| 48 | + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ | ||
| 49 | + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | ||
| 50 | + t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ | ||
| 51 | cpu->isar.id_aa64isar0 = t; | ||
| 52 | |||
| 53 | t = cpu->isar.id_aa64isar1; | ||
| 54 | - t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); | ||
| 55 | - t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); | ||
| 56 | - t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); | ||
| 57 | - t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | ||
| 58 | - t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | ||
| 59 | - t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); | ||
| 60 | - t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); | ||
| 61 | - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ | ||
| 62 | - t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); | ||
| 63 | + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ | ||
| 64 | + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ | ||
| 65 | + t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ | ||
| 66 | + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ | ||
| 67 | + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ | ||
| 68 | + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | ||
| 69 | + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | ||
| 70 | + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | ||
| 71 | + t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | ||
| 72 | cpu->isar.id_aa64isar1 = t; | ||
| 73 | |||
| 74 | t = cpu->isar.id_aa64pfr0; | ||
| 75 | + t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | ||
| 76 | + t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | ||
| 77 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 78 | - t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); | ||
| 79 | - t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); | ||
| 80 | - t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); | ||
| 81 | - t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); | ||
| 82 | + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
| 83 | + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
| 84 | cpu->isar.id_aa64pfr0 = t; | ||
| 85 | |||
| 86 | t = cpu->isar.id_aa64pfr1; | ||
| 87 | - t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | ||
| 88 | - t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); | ||
| 89 | + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ | ||
| 90 | + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ | ||
| 91 | /* | ||
| 92 | * Begin with full support for MTE. This will be downgraded to MTE=0 | ||
| 93 | * during realize if the board provides no tag memory, much like | ||
| 94 | * we do for EL2 with the virtualization=on property. | ||
| 95 | */ | ||
| 96 | - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); | ||
| 97 | + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
| 98 | cpu->isar.id_aa64pfr1 = t; | ||
| 99 | |||
| 100 | t = cpu->isar.id_aa64mmfr0; | ||
| 101 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 102 | cpu->isar.id_aa64mmfr0 = t; | ||
| 103 | |||
| 104 | t = cpu->isar.id_aa64mmfr1; | ||
| 105 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | ||
| 106 | - t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); | ||
| 107 | - t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); | ||
| 108 | - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ | ||
| 109 | - t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ | ||
| 110 | - t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ | ||
| 111 | + t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | ||
| 112 | + t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | ||
| 113 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | ||
| 114 | + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | ||
| 115 | + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ | ||
| 116 | + t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | ||
| 117 | cpu->isar.id_aa64mmfr1 = t; | ||
| 118 | |||
| 119 | t = cpu->isar.id_aa64mmfr2; | ||
| 120 | - t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | ||
| 121 | - t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | ||
| 122 | - t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | ||
| 123 | - t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
| 124 | - t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
| 125 | - t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
| 126 | + t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | ||
| 127 | + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | ||
| 128 | + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
| 129 | + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | ||
| 130 | + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
| 131 | + t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
| 132 | cpu->isar.id_aa64mmfr2 = t; | ||
| 133 | |||
| 134 | t = cpu->isar.id_aa64zfr0; | ||
| 135 | t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); | ||
| 136 | - t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ | ||
| 137 | - t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); | ||
| 138 | - t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); | ||
| 139 | - t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); | ||
| 140 | - t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); | ||
| 141 | - t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); | ||
| 142 | - t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); | ||
| 143 | - t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
| 144 | + t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ | ||
| 145 | + t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ | ||
| 146 | + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ | ||
| 147 | + t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ | ||
| 148 | + t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ | ||
| 149 | + t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ | ||
| 150 | + t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ | ||
| 151 | + t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ | ||
| 152 | cpu->isar.id_aa64zfr0 = t; | ||
| 153 | |||
| 154 | t = cpu->isar.id_aa64dfr0; | ||
| 155 | - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
| 156 | + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | ||
| 157 | cpu->isar.id_aa64dfr0 = t; | ||
| 158 | |||
| 159 | /* Replicate the same data to the 32-bit id registers. */ | ||
| 160 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 161 | index XXXXXXX..XXXXXXX 100644 | ||
| 162 | --- a/target/arm/cpu_tcg.c | ||
| 163 | +++ b/target/arm/cpu_tcg.c | ||
| 164 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
| 165 | |||
| 166 | /* Add additional features supported by QEMU */ | ||
| 167 | t = cpu->isar.id_isar5; | ||
| 168 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
| 169 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
| 170 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
| 171 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ | ||
| 172 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ | ||
| 173 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ | ||
| 174 | t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
| 175 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
| 176 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
| 177 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ | ||
| 178 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ | ||
| 179 | cpu->isar.id_isar5 = t; | ||
| 180 | |||
| 181 | t = cpu->isar.id_isar6; | ||
| 182 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
| 183 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
| 184 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
| 185 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
| 186 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
| 187 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
| 188 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
| 189 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ | ||
| 190 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ | ||
| 191 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ | ||
| 192 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ | ||
| 193 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ | ||
| 194 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ | ||
| 195 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ | ||
| 196 | cpu->isar.id_isar6 = t; | ||
| 197 | |||
| 198 | t = cpu->isar.mvfr1; | ||
| 199 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
| 200 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
| 201 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ | ||
| 202 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ | ||
| 203 | cpu->isar.mvfr1 = t; | ||
| 204 | |||
| 205 | t = cpu->isar.mvfr2; | ||
| 206 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
| 207 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
| 208 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
| 209 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
| 210 | cpu->isar.mvfr2 = t; | ||
| 211 | |||
| 212 | t = cpu->isar.id_mmfr3; | ||
| 213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
| 214 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ | ||
| 215 | cpu->isar.id_mmfr3 = t; | ||
| 216 | |||
| 217 | t = cpu->isar.id_mmfr4; | ||
| 218 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
| 219 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
| 220 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
| 221 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
| 222 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ | ||
| 223 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
| 224 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ | ||
| 225 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ | ||
| 226 | cpu->isar.id_mmfr4 = t; | ||
| 227 | |||
| 228 | t = cpu->isar.id_pfr0; | ||
| 229 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
| 230 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
| 231 | cpu->isar.id_pfr0 = t; | ||
| 232 | |||
| 233 | t = cpu->isar.id_pfr2; | ||
| 234 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
| 235 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | ||
| 236 | cpu->isar.id_pfr2 = t; | ||
| 237 | |||
| 238 | t = cpu->isar.id_dfr0; | ||
| 239 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
| 240 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
| 241 | cpu->isar.id_dfr0 = t; | ||
| 242 | } | ||
| 243 | |||
| 244 | -- | ||
| 245 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 | ||
| 4 | during arm_cpu_realizefn. | ||
| 5 | |||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20220506180242.216785-11-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/cpu.c | 22 +++++++++++++--------- | ||
| 12 | 1 file changed, 13 insertions(+), 9 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/cpu.c | ||
| 17 | +++ b/target/arm/cpu.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 19 | */ | ||
| 20 | unset_feature(env, ARM_FEATURE_EL3); | ||
| 21 | |||
| 22 | - /* Disable the security extension feature bits in the processor feature | ||
| 23 | - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. | ||
| 24 | + /* | ||
| 25 | + * Disable the security extension feature bits in the processor | ||
| 26 | + * feature registers as well. | ||
| 27 | */ | ||
| 28 | - cpu->isar.id_pfr1 &= ~0xf0; | ||
| 29 | - cpu->isar.id_aa64pfr0 &= ~0xf000; | ||
| 30 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | ||
| 31 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
| 32 | + ID_AA64PFR0, EL3, 0); | ||
| 33 | } | ||
| 34 | |||
| 35 | if (!cpu->has_el2) { | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 37 | } | ||
| 38 | |||
| 39 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | ||
| 40 | - /* Disable the hypervisor feature bits in the processor feature | ||
| 41 | - * registers if we don't have EL2. These are id_pfr1[15:12] and | ||
| 42 | - * id_aa64pfr0_el1[11:8]. | ||
| 43 | + /* | ||
| 44 | + * Disable the hypervisor feature bits in the processor feature | ||
| 45 | + * registers if we don't have EL2. | ||
| 46 | */ | ||
| 47 | - cpu->isar.id_aa64pfr0 &= ~0xf00; | ||
| 48 | - cpu->isar.id_pfr1 &= ~0xf000; | ||
| 49 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
| 50 | + ID_AA64PFR0, EL2, 0); | ||
| 51 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, | ||
| 52 | + ID_PFR1, VIRTUALIZATION, 0); | ||
| 53 | } | ||
| 54 | |||
| 55 | #ifndef CONFIG_USER_ONLY | ||
| 56 | -- | ||
| 57 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The only portion of FEAT_Debugv8p2 that is relevant to QEMU | ||
| 4 | is CONTEXTIDR_EL2, which is also conditionally implemented | ||
| 5 | with FEAT_VHE. The rest of the debug extension concerns the | ||
| 6 | External debug interface, which is outside the scope of QEMU. | ||
| 7 | |||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20220506180242.216785-12-richard.henderson@linaro.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | docs/system/arm/emulation.rst | 1 + | ||
| 14 | target/arm/cpu.c | 1 + | ||
| 15 | target/arm/cpu64.c | 1 + | ||
| 16 | target/arm/cpu_tcg.c | 2 ++ | ||
| 17 | 4 files changed, 5 insertions(+) | ||
| 18 | |||
| 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/docs/system/arm/emulation.rst | ||
| 22 | +++ b/docs/system/arm/emulation.rst | ||
| 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 24 | - FEAT_BTI (Branch Target Identification) | ||
| 25 | - FEAT_DIT (Data Independent Timing instructions) | ||
| 26 | - FEAT_DPB (DC CVAP instruction) | ||
| 27 | +- FEAT_Debugv8p2 (Debug changes for v8.2) | ||
| 28 | - FEAT_DotProd (Advanced SIMD dot product instructions) | ||
| 29 | - FEAT_FCMA (Floating-point complex number instructions) | ||
| 30 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | ||
| 31 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/target/arm/cpu.c | ||
| 34 | +++ b/target/arm/cpu.c | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 36 | * feature registers as well. | ||
| 37 | */ | ||
| 38 | cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | ||
| 39 | + cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); | ||
| 40 | cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
| 41 | ID_AA64PFR0, EL3, 0); | ||
| 42 | } | ||
| 43 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 44 | index XXXXXXX..XXXXXXX 100644 | ||
| 45 | --- a/target/arm/cpu64.c | ||
| 46 | +++ b/target/arm/cpu64.c | ||
| 47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 48 | cpu->isar.id_aa64zfr0 = t; | ||
| 49 | |||
| 50 | t = cpu->isar.id_aa64dfr0; | ||
| 51 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ | ||
| 52 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | ||
| 53 | cpu->isar.id_aa64dfr0 = t; | ||
| 54 | |||
| 55 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 56 | index XXXXXXX..XXXXXXX 100644 | ||
| 57 | --- a/target/arm/cpu_tcg.c | ||
| 58 | +++ b/target/arm/cpu_tcg.c | ||
| 59 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
| 60 | cpu->isar.id_pfr2 = t; | ||
| 61 | |||
| 62 | t = cpu->isar.id_dfr0; | ||
| 63 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | ||
| 64 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | ||
| 65 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
| 66 | cpu->isar.id_dfr0 = t; | ||
| 67 | } | ||
| 68 | -- | ||
| 69 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | This extension concerns changes to the External Debug interface, | ||
| 4 | with Secure and Non-secure access to the debug registers, and all | ||
| 5 | of it is outside the scope of QEMU. Indicating support for this | ||
| 6 | is mandatory with FEAT_SEL2, which we do implement. | ||
| 7 | |||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20220506180242.216785-13-richard.henderson@linaro.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | docs/system/arm/emulation.rst | 1 + | ||
| 14 | target/arm/cpu64.c | 2 +- | ||
| 15 | target/arm/cpu_tcg.c | 4 ++-- | ||
| 16 | 3 files changed, 4 insertions(+), 3 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/docs/system/arm/emulation.rst | ||
| 21 | +++ b/docs/system/arm/emulation.rst | ||
| 22 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 23 | - FEAT_DIT (Data Independent Timing instructions) | ||
| 24 | - FEAT_DPB (DC CVAP instruction) | ||
| 25 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
| 26 | +- FEAT_Debugv8p4 (Debug changes for v8.4) | ||
| 27 | - FEAT_DotProd (Advanced SIMD dot product instructions) | ||
| 28 | - FEAT_FCMA (Floating-point complex number instructions) | ||
| 29 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | ||
| 30 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 31 | index XXXXXXX..XXXXXXX 100644 | ||
| 32 | --- a/target/arm/cpu64.c | ||
| 33 | +++ b/target/arm/cpu64.c | ||
| 34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 35 | cpu->isar.id_aa64zfr0 = t; | ||
| 36 | |||
| 37 | t = cpu->isar.id_aa64dfr0; | ||
| 38 | - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ | ||
| 39 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ | ||
| 40 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | ||
| 41 | cpu->isar.id_aa64dfr0 = t; | ||
| 42 | |||
| 43 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 44 | index XXXXXXX..XXXXXXX 100644 | ||
| 45 | --- a/target/arm/cpu_tcg.c | ||
| 46 | +++ b/target/arm/cpu_tcg.c | ||
| 47 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
| 48 | cpu->isar.id_pfr2 = t; | ||
| 49 | |||
| 50 | t = cpu->isar.id_dfr0; | ||
| 51 | - t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | ||
| 52 | - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | ||
| 53 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ | ||
| 54 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ | ||
| 55 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
| 56 | cpu->isar.id_dfr0 = t; | ||
| 57 | } | ||
| 58 | -- | ||
| 59 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Add only the system registers required to implement zero error | ||
| 4 | records. This means that all values for ERRSELR are out of range, | ||
| 5 | which means that it and all of the indexed error record registers | ||
| 6 | need not be implemented. | ||
| 7 | |||
| 8 | Add the EL2 registers required for injecting virtual SError. | ||
| 9 | |||
| 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 20220506180242.216785-14-richard.henderson@linaro.org | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | target/arm/cpu.h | 5 +++ | ||
| 16 | target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ | ||
| 17 | 2 files changed, 89 insertions(+) | ||
| 18 | |||
| 19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/target/arm/cpu.h | ||
| 22 | +++ b/target/arm/cpu.h | ||
| 23 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
| 24 | uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ | ||
| 25 | uint64_t gcr_el1; | ||
| 26 | uint64_t rgsr_el1; | ||
| 27 | + | ||
| 28 | + /* Minimal RAS registers */ | ||
| 29 | + uint64_t disr_el1; | ||
| 30 | + uint64_t vdisr_el2; | ||
| 31 | + uint64_t vsesr_el2; | ||
| 32 | } cp15; | ||
| 33 | |||
| 34 | struct { | ||
| 35 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/arm/helper.c | ||
| 38 | +++ b/target/arm/helper.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
| 40 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 41 | }; | ||
| 42 | |||
| 43 | +/* | ||
| 44 | + * Check for traps to RAS registers, which are controlled | ||
| 45 | + * by HCR_EL2.TERR and SCR_EL3.TERR. | ||
| 46 | + */ | ||
| 47 | +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 48 | + bool isread) | ||
| 49 | +{ | ||
| 50 | + int el = arm_current_el(env); | ||
| 51 | + | ||
| 52 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { | ||
| 53 | + return CP_ACCESS_TRAP_EL2; | ||
| 54 | + } | ||
| 55 | + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { | ||
| 56 | + return CP_ACCESS_TRAP_EL3; | ||
| 57 | + } | ||
| 58 | + return CP_ACCESS_OK; | ||
| 59 | +} | ||
| 60 | + | ||
| 61 | +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 62 | +{ | ||
| 63 | + int el = arm_current_el(env); | ||
| 64 | + | ||
| 65 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | ||
| 66 | + return env->cp15.vdisr_el2; | ||
| 67 | + } | ||
| 68 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | ||
| 69 | + return 0; /* RAZ/WI */ | ||
| 70 | + } | ||
| 71 | + return env->cp15.disr_el1; | ||
| 72 | +} | ||
| 73 | + | ||
| 74 | +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | ||
| 75 | +{ | ||
| 76 | + int el = arm_current_el(env); | ||
| 77 | + | ||
| 78 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | ||
| 79 | + env->cp15.vdisr_el2 = val; | ||
| 80 | + return; | ||
| 81 | + } | ||
| 82 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | ||
| 83 | + return; /* RAZ/WI */ | ||
| 84 | + } | ||
| 85 | + env->cp15.disr_el1 = val; | ||
| 86 | +} | ||
| 87 | + | ||
| 88 | +/* | ||
| 89 | + * Minimal RAS implementation with no Error Records. | ||
| 90 | + * Which means that all of the Error Record registers: | ||
| 91 | + * ERXADDR_EL1 | ||
| 92 | + * ERXCTLR_EL1 | ||
| 93 | + * ERXFR_EL1 | ||
| 94 | + * ERXMISC0_EL1 | ||
| 95 | + * ERXMISC1_EL1 | ||
| 96 | + * ERXMISC2_EL1 | ||
| 97 | + * ERXMISC3_EL1 | ||
| 98 | + * ERXPFGCDN_EL1 (RASv1p1) | ||
| 99 | + * ERXPFGCTL_EL1 (RASv1p1) | ||
| 100 | + * ERXPFGF_EL1 (RASv1p1) | ||
| 101 | + * ERXSTATUS_EL1 | ||
| 102 | + * and | ||
| 103 | + * ERRSELR_EL1 | ||
| 104 | + * may generate UNDEFINED, which is the effect we get by not | ||
| 105 | + * listing them at all. | ||
| 106 | + */ | ||
| 107 | +static const ARMCPRegInfo minimal_ras_reginfo[] = { | ||
| 108 | + { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 109 | + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | ||
| 110 | + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | ||
| 111 | + .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | ||
| 112 | + { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 113 | + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | ||
| 114 | + .access = PL1_R, .accessfn = access_terr, | ||
| 115 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 116 | + { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 117 | + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | ||
| 118 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | ||
| 119 | + { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | ||
| 120 | + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | ||
| 121 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | ||
| 122 | +}; | ||
| 123 | + | ||
| 124 | /* Return the exception level to which exceptions should be taken | ||
| 125 | * via SVEAccessTrap. If an exception should be routed through | ||
| 126 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | ||
| 127 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 128 | if (cpu_isar_feature(aa64_ssbs, cpu)) { | ||
| 129 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | ||
| 130 | } | ||
| 131 | + if (cpu_isar_feature(any_ras, cpu)) { | ||
| 132 | + define_arm_cp_regs(cpu, minimal_ras_reginfo); | ||
| 133 | + } | ||
| 134 | |||
| 135 | if (cpu_isar_feature(aa64_vh, cpu) || | ||
| 136 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | ||
| 137 | -- | ||
| 138 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Enable writes to the TERR and TEA bits when RAS is enabled. | ||
| 4 | These bits are otherwise RES0. | ||
| 5 | |||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20220506180242.216785-15-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/helper.c | 9 +++++++++ | ||
| 12 | 1 file changed, 9 insertions(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/helper.c | ||
| 17 | +++ b/target/arm/helper.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
| 19 | } | ||
| 20 | valid_mask &= ~SCR_NET; | ||
| 21 | |||
| 22 | + if (cpu_isar_feature(aa64_ras, cpu)) { | ||
| 23 | + valid_mask |= SCR_TERR; | ||
| 24 | + } | ||
| 25 | if (cpu_isar_feature(aa64_lor, cpu)) { | ||
| 26 | valid_mask |= SCR_TLOR; | ||
| 27 | } | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
| 29 | } | ||
| 30 | } else { | ||
| 31 | valid_mask &= ~(SCR_RW | SCR_ST); | ||
| 32 | + if (cpu_isar_feature(aa32_ras, cpu)) { | ||
| 33 | + valid_mask |= SCR_TERR; | ||
| 34 | + } | ||
| 35 | } | ||
| 36 | |||
| 37 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | ||
| 38 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
| 39 | if (cpu_isar_feature(aa64_vh, cpu)) { | ||
| 40 | valid_mask |= HCR_E2H; | ||
| 41 | } | ||
| 42 | + if (cpu_isar_feature(aa64_ras, cpu)) { | ||
| 43 | + valid_mask |= HCR_TERR | HCR_TEA; | ||
| 44 | + } | ||
| 45 | if (cpu_isar_feature(aa64_lor, cpu)) { | ||
| 46 | valid_mask |= HCR_TLOR; | ||
| 47 | } | ||
| 48 | -- | ||
| 49 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Virtual SError exceptions are raised by setting HCR_EL2.VSE, | ||
| 4 | and are routed to EL1 just like other virtual exceptions. | ||
| 5 | |||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20220506180242.216785-16-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/cpu.h | 2 ++ | ||
| 12 | target/arm/internals.h | 8 ++++++++ | ||
| 13 | target/arm/syndrome.h | 5 +++++ | ||
| 14 | target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- | ||
| 15 | target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- | ||
| 16 | 5 files changed, 91 insertions(+), 2 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/arm/cpu.h | ||
| 21 | +++ b/target/arm/cpu.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ | ||
| 23 | #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ | ||
| 24 | #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ | ||
| 25 | #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ | ||
| 26 | +#define EXCP_VSERR 24 | ||
| 27 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ | ||
| 28 | |||
| 29 | #define ARMV7M_EXCP_RESET 1 | ||
| 30 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 31 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | ||
| 32 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 | ||
| 33 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 | ||
| 34 | +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 | ||
| 35 | |||
| 36 | /* The usual mapping for an AArch64 system register to its AArch32 | ||
| 37 | * counterpart is for the 32 bit world to have access to the lower | ||
| 38 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/target/arm/internals.h | ||
| 41 | +++ b/target/arm/internals.h | ||
| 42 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu); | ||
| 43 | */ | ||
| 44 | void arm_cpu_update_vfiq(ARMCPU *cpu); | ||
| 45 | |||
| 46 | +/** | ||
| 47 | + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit | ||
| 48 | + * | ||
| 49 | + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, | ||
| 50 | + * following a change to the HCR_EL2.VSE bit. | ||
| 51 | + */ | ||
| 52 | +void arm_cpu_update_vserr(ARMCPU *cpu); | ||
| 53 | + | ||
| 54 | /** | ||
| 55 | * arm_mmu_idx_el: | ||
| 56 | * @env: The cpu environment | ||
| 57 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h | ||
| 58 | index XXXXXXX..XXXXXXX 100644 | ||
| 59 | --- a/target/arm/syndrome.h | ||
| 60 | +++ b/target/arm/syndrome.h | ||
| 61 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void) | ||
| 62 | return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; | ||
| 63 | } | ||
| 64 | |||
| 65 | +static inline uint32_t syn_serror(uint32_t extra) | ||
| 66 | +{ | ||
| 67 | + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; | ||
| 68 | +} | ||
| 69 | + | ||
| 70 | #endif /* TARGET_ARM_SYNDROME_H */ | ||
| 71 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 72 | index XXXXXXX..XXXXXXX 100644 | ||
| 73 | --- a/target/arm/cpu.c | ||
| 74 | +++ b/target/arm/cpu.c | ||
| 75 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs) | ||
| 76 | return (cpu->power_state != PSCI_OFF) | ||
| 77 | && cs->interrupt_request & | ||
| 78 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | ||
| 79 | - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | ||
| 80 | + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | ||
| 81 | | CPU_INTERRUPT_EXITTB); | ||
| 82 | } | ||
| 83 | |||
| 84 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | ||
| 85 | return false; | ||
| 86 | } | ||
| 87 | return !(env->daif & PSTATE_I); | ||
| 88 | + case EXCP_VSERR: | ||
| 89 | + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { | ||
| 90 | + /* VIRQs are only taken when hypervized. */ | ||
| 91 | + return false; | ||
| 92 | + } | ||
| 93 | + return !(env->daif & PSTATE_A); | ||
| 94 | default: | ||
| 95 | g_assert_not_reached(); | ||
| 96 | } | ||
| 97 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | ||
| 98 | goto found; | ||
| 99 | } | ||
| 100 | } | ||
| 101 | + if (interrupt_request & CPU_INTERRUPT_VSERR) { | ||
| 102 | + excp_idx = EXCP_VSERR; | ||
| 103 | + target_el = 1; | ||
| 104 | + if (arm_excp_unmasked(cs, excp_idx, target_el, | ||
| 105 | + cur_el, secure, hcr_el2)) { | ||
| 106 | + /* Taking a virtual abort clears HCR_EL2.VSE */ | ||
| 107 | + env->cp15.hcr_el2 &= ~HCR_VSE; | ||
| 108 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
| 109 | + goto found; | ||
| 110 | + } | ||
| 111 | + } | ||
| 112 | return false; | ||
| 113 | |||
| 114 | found: | ||
| 115 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu) | ||
| 116 | } | ||
| 117 | } | ||
| 118 | |||
| 119 | +void arm_cpu_update_vserr(ARMCPU *cpu) | ||
| 120 | +{ | ||
| 121 | + /* | ||
| 122 | + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. | ||
| 123 | + */ | ||
| 124 | + CPUARMState *env = &cpu->env; | ||
| 125 | + CPUState *cs = CPU(cpu); | ||
| 126 | + | ||
| 127 | + bool new_state = env->cp15.hcr_el2 & HCR_VSE; | ||
| 128 | + | ||
| 129 | + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { | ||
| 130 | + if (new_state) { | ||
| 131 | + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
| 132 | + } else { | ||
| 133 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
| 134 | + } | ||
| 135 | + } | ||
| 136 | +} | ||
| 137 | + | ||
| 138 | #ifndef CONFIG_USER_ONLY | ||
| 139 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | ||
| 140 | { | ||
| 141 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 142 | index XXXXXXX..XXXXXXX 100644 | ||
| 143 | --- a/target/arm/helper.c | ||
| 144 | +++ b/target/arm/helper.c | ||
| 145 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 146 | } | ||
| 147 | } | ||
| 148 | |||
| 149 | - /* External aborts are not possible in QEMU so A bit is always clear */ | ||
| 150 | + if (hcr_el2 & HCR_AMO) { | ||
| 151 | + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { | ||
| 152 | + ret |= CPSR_A; | ||
| 153 | + } | ||
| 154 | + } | ||
| 155 | + | ||
| 156 | return ret; | ||
| 157 | } | ||
| 158 | |||
| 159 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
| 160 | g_assert(qemu_mutex_iothread_locked()); | ||
| 161 | arm_cpu_update_virq(cpu); | ||
| 162 | arm_cpu_update_vfiq(cpu); | ||
| 163 | + arm_cpu_update_vserr(cpu); | ||
| 164 | } | ||
| 165 | |||
| 166 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
| 167 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs) | ||
| 168 | [EXCP_LSERR] = "v8M LSERR UsageFault", | ||
| 169 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | ||
| 170 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", | ||
| 171 | + [EXCP_VSERR] = "Virtual SERR", | ||
| 172 | }; | ||
| 173 | |||
| 174 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | ||
| 175 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) | ||
| 176 | mask = CPSR_A | CPSR_I | CPSR_F; | ||
| 177 | offset = 4; | ||
| 178 | break; | ||
| 179 | + case EXCP_VSERR: | ||
| 180 | + { | ||
| 181 | + /* | ||
| 182 | + * Note that this is reported as a data abort, but the DFAR | ||
| 183 | + * has an UNKNOWN value. Construct the SError syndrome from | ||
| 184 | + * AET and ExT fields. | ||
| 185 | + */ | ||
| 186 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; | ||
| 187 | + | ||
| 188 | + if (extended_addresses_enabled(env)) { | ||
| 189 | + env->exception.fsr = arm_fi_to_lfsc(&fi); | ||
| 190 | + } else { | ||
| 191 | + env->exception.fsr = arm_fi_to_sfsc(&fi); | ||
| 192 | + } | ||
| 193 | + env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; | ||
| 194 | + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); | ||
| 195 | + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", | ||
| 196 | + env->exception.fsr); | ||
| 197 | + | ||
| 198 | + new_mode = ARM_CPU_MODE_ABT; | ||
| 199 | + addr = 0x10; | ||
| 200 | + mask = CPSR_A | CPSR_I; | ||
| 201 | + offset = 8; | ||
| 202 | + } | ||
| 203 | + break; | ||
| 204 | case EXCP_SMC: | ||
| 205 | new_mode = ARM_CPU_MODE_MON; | ||
| 206 | addr = 0x08; | ||
| 207 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
| 208 | case EXCP_VFIQ: | ||
| 209 | addr += 0x100; | ||
| 210 | break; | ||
| 211 | + case EXCP_VSERR: | ||
| 212 | + addr += 0x180; | ||
| 213 | + /* Construct the SError syndrome from IDS and ISS fields. */ | ||
| 214 | + env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | ||
| 215 | + env->cp15.esr_el[new_el] = env->exception.syndrome; | ||
| 216 | + break; | ||
| 217 | default: | ||
| 218 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | ||
| 219 | } | ||
| 220 | -- | ||
| 221 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Check for and defer any pending virtual SError. | ||
| 4 | |||
| 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220506180242.216785-17-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/helper.h | 1 + | ||
| 11 | target/arm/a32.decode | 16 ++++++++------ | ||
| 12 | target/arm/t32.decode | 18 ++++++++-------- | ||
| 13 | target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ | ||
| 14 | target/arm/translate-a64.c | 17 +++++++++++++++ | ||
| 15 | target/arm/translate.c | 23 ++++++++++++++++++++ | ||
| 16 | 6 files changed, 103 insertions(+), 15 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/arm/helper.h | ||
| 21 | +++ b/target/arm/helper.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env) | ||
| 23 | DEF_HELPER_1(yield, void, env) | ||
| 24 | DEF_HELPER_1(pre_hvc, void, env) | ||
| 25 | DEF_HELPER_2(pre_smc, void, env, i32) | ||
| 26 | +DEF_HELPER_1(vesb, void, env) | ||
| 27 | |||
| 28 | DEF_HELPER_3(cpsr_write, void, env, i32, i32) | ||
| 29 | DEF_HELPER_2(cpsr_write_eret, void, env, i32) | ||
| 30 | diff --git a/target/arm/a32.decode b/target/arm/a32.decode | ||
| 31 | index XXXXXXX..XXXXXXX 100644 | ||
| 32 | --- a/target/arm/a32.decode | ||
| 33 | +++ b/target/arm/a32.decode | ||
| 34 | @@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn | ||
| 35 | |||
| 36 | { | ||
| 37 | { | ||
| 38 | - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 | ||
| 39 | - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 | ||
| 40 | - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 | ||
| 41 | + [ | ||
| 42 | + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 | ||
| 43 | + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 | ||
| 44 | + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 | ||
| 45 | |||
| 46 | - # TODO: Implement SEV, SEVL; may help SMP performance. | ||
| 47 | - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 | ||
| 48 | - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 | ||
| 49 | + # TODO: Implement SEV, SEVL; may help SMP performance. | ||
| 50 | + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 | ||
| 51 | + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 | ||
| 52 | + | ||
| 53 | + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 | ||
| 54 | + ] | ||
| 55 | |||
| 56 | # The canonical nop ends in 00000000, but the whole of the | ||
| 57 | # rest of the space executes as nop if otherwise unsupported. | ||
| 58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
| 59 | index XXXXXXX..XXXXXXX 100644 | ||
| 60 | --- a/target/arm/t32.decode | ||
| 61 | +++ b/target/arm/t32.decode | ||
| 62 | @@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm | ||
| 63 | [ | ||
| 64 | # Hints, and CPS | ||
| 65 | { | ||
| 66 | - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | ||
| 67 | - WFE 1111 0011 1010 1111 1000 0000 0000 0010 | ||
| 68 | - WFI 1111 0011 1010 1111 1000 0000 0000 0011 | ||
| 69 | + [ | ||
| 70 | + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | ||
| 71 | + WFE 1111 0011 1010 1111 1000 0000 0000 0010 | ||
| 72 | + WFI 1111 0011 1010 1111 1000 0000 0000 0011 | ||
| 73 | |||
| 74 | - # TODO: Implement SEV, SEVL; may help SMP performance. | ||
| 75 | - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
| 76 | - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
| 77 | + # TODO: Implement SEV, SEVL; may help SMP performance. | ||
| 78 | + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
| 79 | + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
| 80 | |||
| 81 | - # For M-profile minimal-RAS ESB can be a NOP, which is the | ||
| 82 | - # default behaviour since it is in the hint space. | ||
| 83 | - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
| 84 | + ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
| 85 | + ] | ||
| 86 | |||
| 87 | # The canonical nop ends in 0000 0000, but the whole rest | ||
| 88 | # of the space is "reserved hint, behaves as nop". | ||
| 89 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
| 90 | index XXXXXXX..XXXXXXX 100644 | ||
| 91 | --- a/target/arm/op_helper.c | ||
| 92 | +++ b/target/arm/op_helper.c | ||
| 93 | @@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, | ||
| 94 | access_type, mmu_idx, ra); | ||
| 95 | } | ||
| 96 | } | ||
| 97 | + | ||
| 98 | +/* | ||
| 99 | + * This function corresponds to AArch64.vESBOperation(). | ||
| 100 | + * Note that the AArch32 version is not functionally different. | ||
| 101 | + */ | ||
| 102 | +void HELPER(vesb)(CPUARMState *env) | ||
| 103 | +{ | ||
| 104 | + /* | ||
| 105 | + * The EL2Enabled() check is done inside arm_hcr_el2_eff, | ||
| 106 | + * and will return HCR_EL2.VSE == 0, so nothing happens. | ||
| 107 | + */ | ||
| 108 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
| 109 | + bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO); | ||
| 110 | + bool pending = enabled && (hcr & HCR_VSE); | ||
| 111 | + bool masked = (env->daif & PSTATE_A); | ||
| 112 | + | ||
| 113 | + /* If VSE pending and masked, defer the exception. */ | ||
| 114 | + if (pending && masked) { | ||
| 115 | + uint32_t syndrome; | ||
| 116 | + | ||
| 117 | + if (arm_el_is_aa64(env, 1)) { | ||
| 118 | + /* Copy across IDS and ISS from VSESR. */ | ||
| 119 | + syndrome = env->cp15.vsesr_el2 & 0x1ffffff; | ||
| 120 | + } else { | ||
| 121 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal }; | ||
| 122 | + | ||
| 123 | + if (extended_addresses_enabled(env)) { | ||
| 124 | + syndrome = arm_fi_to_lfsc(&fi); | ||
| 125 | + } else { | ||
| 126 | + syndrome = arm_fi_to_sfsc(&fi); | ||
| 127 | + } | ||
| 128 | + /* Copy across AET and ExT from VSESR. */ | ||
| 129 | + syndrome |= env->cp15.vsesr_el2 & 0xd000; | ||
| 130 | + } | ||
| 131 | + | ||
| 132 | + /* Set VDISR_EL2.A along with the syndrome. */ | ||
| 133 | + env->cp15.vdisr_el2 = syndrome | (1u << 31); | ||
| 134 | + | ||
| 135 | + /* Clear pending virtual SError */ | ||
| 136 | + env->cp15.hcr_el2 &= ~HCR_VSE; | ||
| 137 | + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); | ||
| 138 | + } | ||
| 139 | +} | ||
| 140 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 141 | index XXXXXXX..XXXXXXX 100644 | ||
| 142 | --- a/target/arm/translate-a64.c | ||
| 143 | +++ b/target/arm/translate-a64.c | ||
| 144 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, | ||
| 145 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
| 146 | } | ||
| 147 | break; | ||
| 148 | + case 0b10000: /* ESB */ | ||
| 149 | + /* Without RAS, we must implement this as NOP. */ | ||
| 150 | + if (dc_isar_feature(aa64_ras, s)) { | ||
| 151 | + /* | ||
| 152 | + * QEMU does not have a source of physical SErrors, | ||
| 153 | + * so we are only concerned with virtual SErrors. | ||
| 154 | + * The pseudocode in the ARM for this case is | ||
| 155 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
| 156 | + * AArch64.vESBOperation(); | ||
| 157 | + * Most of the condition can be evaluated at translation time. | ||
| 158 | + * Test for EL2 present, and defer test for SEL2 to runtime. | ||
| 159 | + */ | ||
| 160 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
| 161 | + gen_helper_vesb(cpu_env); | ||
| 162 | + } | ||
| 163 | + } | ||
| 164 | + break; | ||
| 165 | case 0b11000: /* PACIAZ */ | ||
| 166 | if (s->pauth_active) { | ||
| 167 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | ||
| 168 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 169 | index XXXXXXX..XXXXXXX 100644 | ||
| 170 | --- a/target/arm/translate.c | ||
| 171 | +++ b/target/arm/translate.c | ||
| 172 | @@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) | ||
| 173 | return true; | ||
| 174 | } | ||
| 175 | |||
| 176 | +static bool trans_ESB(DisasContext *s, arg_ESB *a) | ||
| 177 | +{ | ||
| 178 | + /* | ||
| 179 | + * For M-profile, minimal-RAS ESB can be a NOP. | ||
| 180 | + * Without RAS, we must implement this as NOP. | ||
| 181 | + */ | ||
| 182 | + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) { | ||
| 183 | + /* | ||
| 184 | + * QEMU does not have a source of physical SErrors, | ||
| 185 | + * so we are only concerned with virtual SErrors. | ||
| 186 | + * The pseudocode in the ARM for this case is | ||
| 187 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
| 188 | + * AArch32.vESBOperation(); | ||
| 189 | + * Most of the condition can be evaluated at translation time. | ||
| 190 | + * Test for EL2 present, and defer test for SEL2 to runtime. | ||
| 191 | + */ | ||
| 192 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
| 193 | + gen_helper_vesb(cpu_env); | ||
| 194 | + } | ||
| 195 | + } | ||
| 196 | + return true; | ||
| 197 | +} | ||
| 198 | + | ||
| 199 | static bool trans_NOP(DisasContext *s, arg_NOP *a) | ||
| 200 | { | ||
| 201 | return true; | ||
| 202 | -- | ||
| 203 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20220506180242.216785-18-richard.henderson@linaro.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | --- | ||
| 8 | docs/system/arm/emulation.rst | 1 + | ||
| 9 | target/arm/cpu64.c | 1 + | ||
| 10 | target/arm/cpu_tcg.c | 1 + | ||
| 11 | 3 files changed, 3 insertions(+) | ||
| 12 | |||
| 13 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/docs/system/arm/emulation.rst | ||
| 16 | +++ b/docs/system/arm/emulation.rst | ||
| 17 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 18 | - FEAT_PMULL (PMULL, PMULL2 instructions) | ||
| 19 | - FEAT_PMUv3p1 (PMU Extensions v3.1) | ||
| 20 | - FEAT_PMUv3p4 (PMU Extensions v3.4) | ||
| 21 | +- FEAT_RAS (Reliability, availability, and serviceability) | ||
| 22 | - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) | ||
| 23 | - FEAT_RNG (Random number generator) | ||
| 24 | - FEAT_SB (Speculation Barrier) | ||
| 25 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/target/arm/cpu64.c | ||
| 28 | +++ b/target/arm/cpu64.c | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 30 | t = cpu->isar.id_aa64pfr0; | ||
| 31 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | ||
| 32 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | ||
| 33 | + t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ | ||
| 34 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 35 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
| 36 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
| 37 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 38 | index XXXXXXX..XXXXXXX 100644 | ||
| 39 | --- a/target/arm/cpu_tcg.c | ||
| 40 | +++ b/target/arm/cpu_tcg.c | ||
| 41 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
| 42 | |||
| 43 | t = cpu->isar.id_pfr0; | ||
| 44 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
| 45 | + t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ | ||
| 46 | cpu->isar.id_pfr0 = t; | ||
| 47 | |||
| 48 | t = cpu->isar.id_pfr2; | ||
| 49 | -- | ||
| 50 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | This feature is AArch64 only, and applies to physical SErrors, | ||
| 4 | which QEMU does not implement, thus the feature is a nop. | ||
| 5 | |||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20220506180242.216785-19-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | docs/system/arm/emulation.rst | 1 + | ||
| 12 | target/arm/cpu64.c | 1 + | ||
| 13 | 2 files changed, 2 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/docs/system/arm/emulation.rst | ||
| 18 | +++ b/docs/system/arm/emulation.rst | ||
| 19 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 20 | - FEAT_FlagM2 (Enhancements to flag manipulation instructions) | ||
| 21 | - FEAT_HPDS (Hierarchical permission disables) | ||
| 22 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) | ||
| 23 | +- FEAT_IESB (Implicit error synchronization event) | ||
| 24 | - FEAT_JSCVT (JavaScript conversion instructions) | ||
| 25 | - FEAT_LOR (Limited ordering regions) | ||
| 26 | - FEAT_LPA (Large Physical Address space) | ||
| 27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | ||
| 29 | --- a/target/arm/cpu64.c | ||
| 30 | +++ b/target/arm/cpu64.c | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 32 | t = cpu->isar.id_aa64mmfr2; | ||
| 33 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | ||
| 34 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | ||
| 35 | + t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ | ||
| 36 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
| 37 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | ||
| 38 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
| 39 | -- | ||
| 40 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | This extension concerns branch speculation, which TCG does | ||
| 4 | not implement. Thus we can trivially enable this feature. | ||
| 5 | |||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20220506180242.216785-20-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | docs/system/arm/emulation.rst | 1 + | ||
| 12 | target/arm/cpu64.c | 1 + | ||
| 13 | target/arm/cpu_tcg.c | 1 + | ||
| 14 | 3 files changed, 3 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/docs/system/arm/emulation.rst | ||
| 19 | +++ b/docs/system/arm/emulation.rst | ||
| 20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 21 | - FEAT_BBM at level 2 (Translation table break-before-make levels) | ||
| 22 | - FEAT_BF16 (AArch64 BFloat16 instructions) | ||
| 23 | - FEAT_BTI (Branch Target Identification) | ||
| 24 | +- FEAT_CSV2 (Cache speculation variant 2) | ||
| 25 | - FEAT_DIT (Data Independent Timing instructions) | ||
| 26 | - FEAT_DPB (DC CVAP instruction) | ||
| 27 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
| 28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/target/arm/cpu64.c | ||
| 31 | +++ b/target/arm/cpu64.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 33 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 34 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
| 35 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
| 36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ | ||
| 37 | cpu->isar.id_aa64pfr0 = t; | ||
| 38 | |||
| 39 | t = cpu->isar.id_aa64pfr1; | ||
| 40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/target/arm/cpu_tcg.c | ||
| 43 | +++ b/target/arm/cpu_tcg.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
| 45 | cpu->isar.id_mmfr4 = t; | ||
| 46 | |||
| 47 | t = cpu->isar.id_pfr0; | ||
| 48 | + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ | ||
| 49 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
| 50 | t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ | ||
| 51 | cpu->isar.id_pfr0 = t; | ||
| 52 | -- | ||
| 53 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | There is no branch prediction in TCG, therefore there is no | ||
| 4 | need to actually include the context number into the predictor. | ||
| 5 | Therefore all we need to do is add the state for SCXTNUM_ELx. | ||
| 6 | |||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220506180242.216785-21-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | docs/system/arm/emulation.rst | 3 ++ | ||
| 13 | target/arm/cpu.h | 16 +++++++++ | ||
| 14 | target/arm/cpu.c | 5 +++ | ||
| 15 | target/arm/cpu64.c | 3 +- | ||
| 16 | target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- | ||
| 17 | 5 files changed, 86 insertions(+), 2 deletions(-) | ||
| 18 | |||
| 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/docs/system/arm/emulation.rst | ||
| 22 | +++ b/docs/system/arm/emulation.rst | ||
| 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 24 | - FEAT_BF16 (AArch64 BFloat16 instructions) | ||
| 25 | - FEAT_BTI (Branch Target Identification) | ||
| 26 | - FEAT_CSV2 (Cache speculation variant 2) | ||
| 27 | +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | ||
| 28 | +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | ||
| 29 | +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) | ||
| 30 | - FEAT_DIT (Data Independent Timing instructions) | ||
| 31 | - FEAT_DPB (DC CVAP instruction) | ||
| 32 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
| 33 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/target/arm/cpu.h | ||
| 36 | +++ b/target/arm/cpu.h | ||
| 37 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
| 38 | ARMPACKey apdb; | ||
| 39 | ARMPACKey apga; | ||
| 40 | } keys; | ||
| 41 | + | ||
| 42 | + uint64_t scxtnum_el[4]; | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #if defined(CONFIG_USER_ONLY) | ||
| 46 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | ||
| 47 | #define SCTLR_WXN (1U << 19) | ||
| 48 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | ||
| 49 | #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ | ||
| 50 | +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ | ||
| 51 | #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ | ||
| 52 | #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ | ||
| 53 | #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ | ||
| 54 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) | ||
| 55 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; | ||
| 56 | } | ||
| 57 | |||
| 58 | +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) | ||
| 59 | +{ | ||
| 60 | + int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); | ||
| 61 | + if (key >= 2) { | ||
| 62 | + return true; /* FEAT_CSV2_2 */ | ||
| 63 | + } | ||
| 64 | + if (key == 1) { | ||
| 65 | + key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); | ||
| 66 | + return key >= 2; /* FEAT_CSV2_1p2 */ | ||
| 67 | + } | ||
| 68 | + return false; | ||
| 69 | +} | ||
| 70 | + | ||
| 71 | static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) | ||
| 72 | { | ||
| 73 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; | ||
| 74 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 75 | index XXXXXXX..XXXXXXX 100644 | ||
| 76 | --- a/target/arm/cpu.c | ||
| 77 | +++ b/target/arm/cpu.c | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | ||
| 79 | */ | ||
| 80 | env->cp15.gcr_el1 = 0x1ffff; | ||
| 81 | } | ||
| 82 | + /* | ||
| 83 | + * Disable access to SCXTNUM_EL0 from CSV2_1p2. | ||
| 84 | + * This is not yet exposed from the Linux kernel in any way. | ||
| 85 | + */ | ||
| 86 | + env->cp15.sctlr_el[1] |= SCTLR_TSCXT; | ||
| 87 | #else | ||
| 88 | /* Reset into the highest available EL */ | ||
| 89 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
| 90 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 91 | index XXXXXXX..XXXXXXX 100644 | ||
| 92 | --- a/target/arm/cpu64.c | ||
| 93 | +++ b/target/arm/cpu64.c | ||
| 94 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 95 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
| 96 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
| 97 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
| 98 | - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ | ||
| 99 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | ||
| 100 | cpu->isar.id_aa64pfr0 = t; | ||
| 101 | |||
| 102 | t = cpu->isar.id_aa64pfr1; | ||
| 103 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 104 | * we do for EL2 with the virtualization=on property. | ||
| 105 | */ | ||
| 106 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
| 107 | + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ | ||
| 108 | cpu->isar.id_aa64pfr1 = t; | ||
| 109 | |||
| 110 | t = cpu->isar.id_aa64mmfr0; | ||
| 111 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 112 | index XXXXXXX..XXXXXXX 100644 | ||
| 113 | --- a/target/arm/helper.c | ||
| 114 | +++ b/target/arm/helper.c | ||
| 115 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
| 116 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
| 117 | valid_mask |= SCR_ATA; | ||
| 118 | } | ||
| 119 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
| 120 | + valid_mask |= SCR_ENSCXT; | ||
| 121 | + } | ||
| 122 | } else { | ||
| 123 | valid_mask &= ~(SCR_RW | SCR_ST); | ||
| 124 | if (cpu_isar_feature(aa32_ras, cpu)) { | ||
| 125 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
| 126 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
| 127 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | ||
| 128 | } | ||
| 129 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
| 130 | + valid_mask |= HCR_ENSCXT; | ||
| 131 | + } | ||
| 132 | } | ||
| 133 | |||
| 134 | /* Clear RES0 bits. */ | ||
| 135 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
| 136 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), | ||
| 137 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | ||
| 138 | |||
| 139 | + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), | ||
| 140 | + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", | ||
| 141 | + isar_feature_aa64_scxtnum }, | ||
| 142 | + | ||
| 143 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ | ||
| 144 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | ||
| 145 | }; | ||
| 146 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
| 147 | }, | ||
| 148 | }; | ||
| 149 | |||
| 150 | -#endif | ||
| 151 | +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 152 | + bool isread) | ||
| 153 | +{ | ||
| 154 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
| 155 | + int el = arm_current_el(env); | ||
| 156 | + | ||
| 157 | + if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { | ||
| 158 | + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { | ||
| 159 | + if (hcr & HCR_TGE) { | ||
| 160 | + return CP_ACCESS_TRAP_EL2; | ||
| 161 | + } | ||
| 162 | + return CP_ACCESS_TRAP; | ||
| 163 | + } | ||
| 164 | + } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | ||
| 165 | + return CP_ACCESS_TRAP_EL2; | ||
| 166 | + } | ||
| 167 | + if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | ||
| 168 | + return CP_ACCESS_TRAP_EL2; | ||
| 169 | + } | ||
| 170 | + if (el < 3 | ||
| 171 | + && arm_feature(env, ARM_FEATURE_EL3) | ||
| 172 | + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | ||
| 173 | + return CP_ACCESS_TRAP_EL3; | ||
| 174 | + } | ||
| 175 | + return CP_ACCESS_OK; | ||
| 176 | +} | ||
| 177 | + | ||
| 178 | +static const ARMCPRegInfo scxtnum_reginfo[] = { | ||
| 179 | + { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | ||
| 180 | + .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | ||
| 181 | + .access = PL0_RW, .accessfn = access_scxtnum, | ||
| 182 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, | ||
| 183 | + { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | ||
| 184 | + .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | ||
| 185 | + .access = PL1_RW, .accessfn = access_scxtnum, | ||
| 186 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, | ||
| 187 | + { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | ||
| 188 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | ||
| 189 | + .access = PL2_RW, .accessfn = access_scxtnum, | ||
| 190 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | ||
| 191 | + { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | ||
| 192 | + .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | ||
| 193 | + .access = PL3_RW, | ||
| 194 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | ||
| 195 | +}; | ||
| 196 | +#endif /* TARGET_AARCH64 */ | ||
| 197 | |||
| 198 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 199 | bool isread) | ||
| 200 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 201 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | ||
| 202 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
| 203 | } | ||
| 204 | + | ||
| 205 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
| 206 | + define_arm_cp_regs(cpu, scxtnum_reginfo); | ||
| 207 | + } | ||
| 208 | #endif | ||
| 209 | |||
| 210 | if (cpu_isar_feature(any_predinv, cpu)) { | ||
| 211 | -- | ||
| 212 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | This extension concerns cache speculation, which TCG does | ||
| 4 | not implement. Thus we can trivially enable this feature. | ||
| 5 | |||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20220506180242.216785-22-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | docs/system/arm/emulation.rst | 1 + | ||
| 12 | target/arm/cpu64.c | 1 + | ||
| 13 | target/arm/cpu_tcg.c | 1 + | ||
| 14 | 3 files changed, 3 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/docs/system/arm/emulation.rst | ||
| 19 | +++ b/docs/system/arm/emulation.rst | ||
| 20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 21 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | ||
| 22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | ||
| 23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | ||
| 24 | +- FEAT_CSV3 (Cache speculation variant 3) | ||
| 25 | - FEAT_DIT (Data Independent Timing instructions) | ||
| 26 | - FEAT_DPB (DC CVAP instruction) | ||
| 27 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
| 28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/target/arm/cpu64.c | ||
| 31 | +++ b/target/arm/cpu64.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 33 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
| 34 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
| 35 | t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | ||
| 36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ | ||
| 37 | cpu->isar.id_aa64pfr0 = t; | ||
| 38 | |||
| 39 | t = cpu->isar.id_aa64pfr1; | ||
| 40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/target/arm/cpu_tcg.c | ||
| 43 | +++ b/target/arm/cpu_tcg.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
| 45 | cpu->isar.id_pfr0 = t; | ||
| 46 | |||
| 47 | t = cpu->isar.id_pfr2; | ||
| 48 | + t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ | ||
| 49 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | ||
| 50 | cpu->isar.id_pfr2 = t; | ||
| 51 | |||
| 52 | -- | ||
| 53 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | This extension concerns not merging memory access, which TCG does | ||
| 4 | not implement. Thus we can trivially enable this feature. | ||
| 5 | Add a comment to handle_hint for the DGH instruction, but no code. | ||
| 6 | |||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20220506180242.216785-23-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | docs/system/arm/emulation.rst | 1 + | ||
| 13 | target/arm/cpu64.c | 1 + | ||
| 14 | target/arm/translate-a64.c | 1 + | ||
| 15 | 3 files changed, 3 insertions(+) | ||
| 16 | |||
| 17 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/docs/system/arm/emulation.rst | ||
| 20 | +++ b/docs/system/arm/emulation.rst | ||
| 21 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | ||
| 23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | ||
| 24 | - FEAT_CSV3 (Cache speculation variant 3) | ||
| 25 | +- FEAT_DGH (Data gathering hint) | ||
| 26 | - FEAT_DIT (Data Independent Timing instructions) | ||
| 27 | - FEAT_DPB (DC CVAP instruction) | ||
| 28 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
| 29 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/target/arm/cpu64.c | ||
| 32 | +++ b/target/arm/cpu64.c | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 34 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | ||
| 35 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | ||
| 36 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | ||
| 37 | + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ | ||
| 38 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | ||
| 39 | cpu->isar.id_aa64isar1 = t; | ||
| 40 | |||
| 41 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 42 | index XXXXXXX..XXXXXXX 100644 | ||
| 43 | --- a/target/arm/translate-a64.c | ||
| 44 | +++ b/target/arm/translate-a64.c | ||
| 45 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, | ||
| 46 | break; | ||
| 47 | case 0b00100: /* SEV */ | ||
| 48 | case 0b00101: /* SEVL */ | ||
| 49 | + case 0b00110: /* DGH */ | ||
| 50 | /* we treat all as NOP at least for now */ | ||
| 51 | break; | ||
| 52 | case 0b00111: /* XPACLRI */ | ||
| 53 | -- | ||
| 54 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Enable the a76 for virt and sbsa board use. | ||
| 4 | |||
| 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20220506180242.216785-24-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | docs/system/arm/virt.rst | 1 + | ||
| 11 | hw/arm/sbsa-ref.c | 1 + | ||
| 12 | hw/arm/virt.c | 1 + | ||
| 13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | ||
| 14 | 4 files changed, 69 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/docs/system/arm/virt.rst | ||
| 19 | +++ b/docs/system/arm/virt.rst | ||
| 20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | ||
| 21 | - ``cortex-a53`` (64-bit) | ||
| 22 | - ``cortex-a57`` (64-bit) | ||
| 23 | - ``cortex-a72`` (64-bit) | ||
| 24 | +- ``cortex-a76`` (64-bit) | ||
| 25 | - ``a64fx`` (64-bit) | ||
| 26 | - ``host`` (with KVM only) | ||
| 27 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | ||
| 28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/arm/sbsa-ref.c | ||
| 31 | +++ b/hw/arm/sbsa-ref.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { | ||
| 33 | static const char * const valid_cpus[] = { | ||
| 34 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
| 35 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
| 36 | + ARM_CPU_TYPE_NAME("cortex-a76"), | ||
| 37 | ARM_CPU_TYPE_NAME("max"), | ||
| 38 | }; | ||
| 39 | |||
| 40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/hw/arm/virt.c | ||
| 43 | +++ b/hw/arm/virt.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | ||
| 45 | ARM_CPU_TYPE_NAME("cortex-a53"), | ||
| 46 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
| 47 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
| 48 | + ARM_CPU_TYPE_NAME("cortex-a76"), | ||
| 49 | ARM_CPU_TYPE_NAME("a64fx"), | ||
| 50 | ARM_CPU_TYPE_NAME("host"), | ||
| 51 | ARM_CPU_TYPE_NAME("max"), | ||
| 52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/target/arm/cpu64.c | ||
| 55 | +++ b/target/arm/cpu64.c | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
| 57 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
| 58 | } | ||
| 59 | |||
| 60 | +static void aarch64_a76_initfn(Object *obj) | ||
| 61 | +{ | ||
| 62 | + ARMCPU *cpu = ARM_CPU(obj); | ||
| 63 | + | ||
| 64 | + cpu->dtb_compatible = "arm,cortex-a76"; | ||
| 65 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
| 66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
| 67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
| 68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
| 69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
| 70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
| 71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
| 72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
| 73 | + | ||
| 74 | + /* Ordered by B2.4 AArch64 registers by functional group */ | ||
| 75 | + cpu->clidr = 0x82000023; | ||
| 76 | + cpu->ctr = 0x8444C004; | ||
| 77 | + cpu->dcz_blocksize = 4; | ||
| 78 | + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; | ||
| 79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | ||
| 80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | ||
| 81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; | ||
| 82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | ||
| 83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | ||
| 84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | ||
| 85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; | ||
| 86 | + cpu->id_afr0 = 0x00000000; | ||
| 87 | + cpu->isar.id_dfr0 = 0x04010088; | ||
| 88 | + cpu->isar.id_isar0 = 0x02101110; | ||
| 89 | + cpu->isar.id_isar1 = 0x13112111; | ||
| 90 | + cpu->isar.id_isar2 = 0x21232042; | ||
| 91 | + cpu->isar.id_isar3 = 0x01112131; | ||
| 92 | + cpu->isar.id_isar4 = 0x00010142; | ||
| 93 | + cpu->isar.id_isar5 = 0x01011121; | ||
| 94 | + cpu->isar.id_isar6 = 0x00000010; | ||
| 95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
| 96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
| 97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
| 98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
| 99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
| 100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
| 101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
| 102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
| 103 | + cpu->midr = 0x414fd0b1; /* r4p1 */ | ||
| 104 | + cpu->revidr = 0; | ||
| 105 | + | ||
| 106 | + /* From B2.18 CCSIDR_EL1 */ | ||
| 107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | ||
| 108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | ||
| 109 | + cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ | ||
| 110 | + | ||
| 111 | + /* From B2.93 SCTLR_EL3 */ | ||
| 112 | + cpu->reset_sctlr = 0x30c50838; | ||
| 113 | + | ||
| 114 | + /* From B4.23 ICH_VTR_EL2 */ | ||
| 115 | + cpu->gic_num_lrs = 4; | ||
| 116 | + cpu->gic_vpribits = 5; | ||
| 117 | + cpu->gic_vprebits = 5; | ||
| 118 | + | ||
| 119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | ||
| 120 | + cpu->isar.mvfr0 = 0x10110222; | ||
| 121 | + cpu->isar.mvfr1 = 0x13211111; | ||
| 122 | + cpu->isar.mvfr2 = 0x00000043; | ||
| 123 | +} | ||
| 124 | + | ||
| 125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | ||
| 126 | { | ||
| 127 | /* | ||
| 128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | ||
| 129 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, | ||
| 130 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, | ||
| 131 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | ||
| 132 | + { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | ||
| 133 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | ||
| 134 | { .name = "max", .initfn = aarch64_max_initfn }, | ||
| 135 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | ||
| 136 | -- | ||
| 137 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> | ||
| 2 | 1 | ||
| 3 | The sbsa-ref machine is continuously evolving. Some of the changes we | ||
| 4 | want to make in the near future, to align with real components (e.g. | ||
| 5 | the GIC-700), will break compatibility for existing firmware. | ||
| 6 | |||
| 7 | Introduce two new properties to the DT generated on machine generation: | ||
| 8 | - machine-version-major | ||
| 9 | To be incremented when a platform change makes the machine | ||
| 10 | incompatible with existing firmware. | ||
| 11 | - machine-version-minor | ||
| 12 | To be incremented when functionality is added to the machine | ||
| 13 | without causing incompatibility with existing firmware. | ||
| 14 | to be reset to 0 when machine-version-major is incremented. | ||
| 15 | |||
| 16 | This versioning scheme is *neither*: | ||
| 17 | - A QEMU versioned machine type; a given version of QEMU will emulate | ||
| 18 | a given version of the platform. | ||
| 19 | - A reflection of level of SBSA (now SystemReady SR) support provided. | ||
| 20 | |||
| 21 | The version will increment on guest-visible functional changes only, | ||
| 22 | akin to a revision ID register found on a physical platform. | ||
| 23 | |||
| 24 | These properties are both introduced with the value 0. | ||
| 25 | (Hence, a machine where the DT is lacking these nodes is equivalent | ||
| 26 | to version 0.0.) | ||
| 27 | |||
| 28 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
| 29 | Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com | ||
| 30 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
| 31 | Cc: Radoslaw Biernacki <rad@semihalf.com> | ||
| 32 | Cc: Cédric Le Goater <clg@kaod.org> | ||
| 33 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 35 | --- | ||
| 36 | hw/arm/sbsa-ref.c | 14 ++++++++++++++ | ||
| 37 | 1 file changed, 14 insertions(+) | ||
| 38 | |||
| 39 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/hw/arm/sbsa-ref.c | ||
| 42 | +++ b/hw/arm/sbsa-ref.c | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms) | ||
| 44 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | ||
| 45 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | ||
| 46 | |||
| 47 | + /* | ||
| 48 | + * This versioning scheme is for informing platform fw only. It is neither: | ||
| 49 | + * - A QEMU versioned machine type; a given version of QEMU will emulate | ||
| 50 | + * a given version of the platform. | ||
| 51 | + * - A reflection of level of SBSA (now SystemReady SR) support provided. | ||
| 52 | + * | ||
| 53 | + * machine-version-major: updated when changes breaking fw compatibility | ||
| 54 | + * are introduced. | ||
| 55 | + * machine-version-minor: updated when features are added that don't break | ||
| 56 | + * fw compatibility. | ||
| 57 | + */ | ||
| 58 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); | ||
| 59 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0); | ||
| 60 | + | ||
| 61 | if (ms->numa_state->have_numa_distance) { | ||
| 62 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); | ||
| 63 | uint32_t *matrix = g_malloc0(size); | ||
| 64 | -- | ||
| 65 | 2.25.1 | ||
| 66 | |||
| 67 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Gavin Shan <gshan@redhat.com> | ||
| 2 | 1 | ||
| 3 | This adds cluster-id in CPU instance properties, which will be used | ||
| 4 | by arm/virt machine. Besides, the cluster-id is also verified or | ||
| 5 | dumped in various spots: | ||
| 6 | |||
| 7 | * hw/core/machine.c::machine_set_cpu_numa_node() to associate | ||
| 8 | CPU with its NUMA node. | ||
| 9 | |||
| 10 | * hw/core/machine.c::machine_numa_finish_cpu_init() to record | ||
| 11 | CPU slots with no NUMA mapping set. | ||
| 12 | |||
| 13 | * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump | ||
| 14 | cluster-id. | ||
| 15 | |||
| 16 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
| 17 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
| 18 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
| 19 | Message-id: 20220503140304.855514-2-gshan@redhat.com | ||
| 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 21 | --- | ||
| 22 | qapi/machine.json | 6 ++++-- | ||
| 23 | hw/core/machine-hmp-cmds.c | 4 ++++ | ||
| 24 | hw/core/machine.c | 16 ++++++++++++++++ | ||
| 25 | 3 files changed, 24 insertions(+), 2 deletions(-) | ||
| 26 | |||
| 27 | diff --git a/qapi/machine.json b/qapi/machine.json | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | ||
| 29 | --- a/qapi/machine.json | ||
| 30 | +++ b/qapi/machine.json | ||
| 31 | @@ -XXX,XX +XXX,XX @@ | ||
| 32 | # @node-id: NUMA node ID the CPU belongs to | ||
| 33 | # @socket-id: socket number within node/board the CPU belongs to | ||
| 34 | # @die-id: die number within socket the CPU belongs to (since 4.1) | ||
| 35 | -# @core-id: core number within die the CPU belongs to | ||
| 36 | +# @cluster-id: cluster number within die the CPU belongs to (since 7.1) | ||
| 37 | +# @core-id: core number within cluster the CPU belongs to | ||
| 38 | # @thread-id: thread number within core the CPU belongs to | ||
| 39 | # | ||
| 40 | -# Note: currently there are 5 properties that could be present | ||
| 41 | +# Note: currently there are 6 properties that could be present | ||
| 42 | # but management should be prepared to pass through other | ||
| 43 | # properties with device_add command to allow for future | ||
| 44 | # interface extension. This also requires the filed names to be kept in | ||
| 45 | @@ -XXX,XX +XXX,XX @@ | ||
| 46 | 'data': { '*node-id': 'int', | ||
| 47 | '*socket-id': 'int', | ||
| 48 | '*die-id': 'int', | ||
| 49 | + '*cluster-id': 'int', | ||
| 50 | '*core-id': 'int', | ||
| 51 | '*thread-id': 'int' | ||
| 52 | } | ||
| 53 | diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c | ||
| 54 | index XXXXXXX..XXXXXXX 100644 | ||
| 55 | --- a/hw/core/machine-hmp-cmds.c | ||
| 56 | +++ b/hw/core/machine-hmp-cmds.c | ||
| 57 | @@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) | ||
| 58 | if (c->has_die_id) { | ||
| 59 | monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); | ||
| 60 | } | ||
| 61 | + if (c->has_cluster_id) { | ||
| 62 | + monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n", | ||
| 63 | + c->cluster_id); | ||
| 64 | + } | ||
| 65 | if (c->has_core_id) { | ||
| 66 | monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); | ||
| 67 | } | ||
| 68 | diff --git a/hw/core/machine.c b/hw/core/machine.c | ||
| 69 | index XXXXXXX..XXXXXXX 100644 | ||
| 70 | --- a/hw/core/machine.c | ||
| 71 | +++ b/hw/core/machine.c | ||
| 72 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | ||
| 73 | return; | ||
| 74 | } | ||
| 75 | |||
| 76 | + if (props->has_cluster_id && !slot->props.has_cluster_id) { | ||
| 77 | + error_setg(errp, "cluster-id is not supported"); | ||
| 78 | + return; | ||
| 79 | + } | ||
| 80 | + | ||
| 81 | if (props->has_socket_id && !slot->props.has_socket_id) { | ||
| 82 | error_setg(errp, "socket-id is not supported"); | ||
| 83 | return; | ||
| 84 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | ||
| 85 | continue; | ||
| 86 | } | ||
| 87 | |||
| 88 | + if (props->has_cluster_id && | ||
| 89 | + props->cluster_id != slot->props.cluster_id) { | ||
| 90 | + continue; | ||
| 91 | + } | ||
| 92 | + | ||
| 93 | if (props->has_die_id && props->die_id != slot->props.die_id) { | ||
| 94 | continue; | ||
| 95 | } | ||
| 96 | @@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu) | ||
| 97 | } | ||
| 98 | g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); | ||
| 99 | } | ||
| 100 | + if (cpu->props.has_cluster_id) { | ||
| 101 | + if (s->len) { | ||
| 102 | + g_string_append_printf(s, ", "); | ||
| 103 | + } | ||
| 104 | + g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); | ||
| 105 | + } | ||
| 106 | if (cpu->props.has_core_id) { | ||
| 107 | if (s->len) { | ||
| 108 | g_string_append_printf(s, ", "); | ||
| 109 | -- | ||
| 110 | 2.25.1 | diff view generated by jsdifflib |
| 1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Guenter Roeck <linux@roeck-us.net> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Currently, the SMP configuration isn't considered when the CPU | 3 | The i.MX USB Phy driver does not check register ranges, resulting in out of |
| 4 | topology is populated. In this case, it's impossible to provide | 4 | bounds accesses if an attempt is made to access non-existing PHY registers. |
| 5 | the default CPU-to-NUMA mapping or association based on the socket | 5 | Add range check and conditionally report bad accesses to fix the problem. |
| 6 | ID of the given CPU. | ||
| 7 | 6 | ||
| 8 | This takes account of SMP configuration when the CPU topology | 7 | While at it, also conditionally log attempted writes to non-existing or |
| 9 | is populated. The die ID for the given CPU isn't assigned since | 8 | read-only registers. |
| 10 | it's not supported on arm/virt machine. Besides, the used SMP | ||
| 11 | configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted | ||
| 12 | to avoid testing failure | ||
| 13 | 9 | ||
| 14 | Signed-off-by: Gavin Shan <gshan@redhat.com> | 10 | Reported-by: Qiang Liu <cyruscyliu@gmail.com> |
| 15 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | 11 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> |
| 16 | Acked-by: Igor Mammedov <imammedo@redhat.com> | 12 | Tested-by: Qiang Liu <cyruscyliu@gmail.com> |
| 17 | Message-id: 20220503140304.855514-4-gshan@redhat.com | 13 | Message-id: 20230316234926.208874-1-linux@roeck-us.net |
| 14 | Link: https://gitlab.com/qemu-project/qemu/-/issues/1408 | ||
| 15 | Fixes: 0701a5efa015 ("hw/usb: Add basic i.MX USB Phy support") | ||
| 16 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
| 17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 19 | --- | 19 | --- |
| 20 | hw/arm/virt.c | 15 ++++++++++++++- | 20 | hw/usb/imx-usb-phy.c | 19 +++++++++++++++++-- |
| 21 | 1 file changed, 14 insertions(+), 1 deletion(-) | 21 | 1 file changed, 17 insertions(+), 2 deletions(-) |
| 22 | 22 | ||
| 23 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 23 | diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c |
| 24 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/hw/arm/virt.c | 25 | --- a/hw/usb/imx-usb-phy.c |
| 26 | +++ b/hw/arm/virt.c | 26 | +++ b/hw/usb/imx-usb-phy.c |
| 27 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 27 | @@ -XXX,XX +XXX,XX @@ |
| 28 | int n; | 28 | #include "qemu/osdep.h" |
| 29 | unsigned int max_cpus = ms->smp.max_cpus; | 29 | #include "hw/usb/imx-usb-phy.h" |
| 30 | VirtMachineState *vms = VIRT_MACHINE(ms); | 30 | #include "migration/vmstate.h" |
| 31 | + MachineClass *mc = MACHINE_GET_CLASS(vms); | 31 | +#include "qemu/log.h" |
| 32 | 32 | #include "qemu/module.h" | |
| 33 | if (ms->possible_cpus) { | 33 | |
| 34 | assert(ms->possible_cpus->len == max_cpus); | 34 | static const VMStateDescription vmstate_imx_usbphy = { |
| 35 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 35 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size) |
| 36 | ms->possible_cpus->cpus[n].type = ms->cpu_type; | 36 | value = s->usbphy[index - 3]; |
| 37 | ms->possible_cpus->cpus[n].arch_id = | 37 | break; |
| 38 | virt_cpu_mp_affinity(vms, n); | 38 | default: |
| 39 | + | 39 | - value = s->usbphy[index]; |
| 40 | + assert(!mc->smp_props.dies_supported); | 40 | + if (index < USBPHY_MAX) { |
| 41 | + ms->possible_cpus->cpus[n].props.has_socket_id = true; | 41 | + value = s->usbphy[index]; |
| 42 | + ms->possible_cpus->cpus[n].props.socket_id = | 42 | + } else { |
| 43 | + n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); | 43 | + qemu_log_mask(LOG_GUEST_ERROR, |
| 44 | + ms->possible_cpus->cpus[n].props.has_cluster_id = true; | 44 | + "%s: Read from non-existing USB PHY register 0x%" |
| 45 | + ms->possible_cpus->cpus[n].props.cluster_id = | 45 | + HWADDR_PRIx "\n", |
| 46 | + (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; | 46 | + __func__, offset); |
| 47 | + ms->possible_cpus->cpus[n].props.has_core_id = true; | 47 | + value = 0; |
| 48 | + ms->possible_cpus->cpus[n].props.core_id = | 48 | + } |
| 49 | + (n / ms->smp.threads) % ms->smp.cores; | 49 | break; |
| 50 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | ||
| 51 | - ms->possible_cpus->cpus[n].props.thread_id = n; | ||
| 52 | + ms->possible_cpus->cpus[n].props.thread_id = | ||
| 53 | + n % ms->smp.threads; | ||
| 54 | } | 50 | } |
| 55 | return ms->possible_cpus; | 51 | return (uint64_t)value; |
| 52 | @@ -XXX,XX +XXX,XX @@ static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 53 | s->usbphy[index - 3] ^= value; | ||
| 54 | break; | ||
| 55 | default: | ||
| 56 | - /* Other registers are read-only */ | ||
| 57 | + /* Other registers are read-only or do not exist */ | ||
| 58 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 59 | + "%s: Write to %s USB PHY register 0x%" | ||
| 60 | + HWADDR_PRIx "\n", | ||
| 61 | + __func__, | ||
| 62 | + index >= USBPHY_MAX ? "non-existing" : "read-only", | ||
| 63 | + offset); | ||
| 64 | break; | ||
| 65 | } | ||
| 56 | } | 66 | } |
| 57 | -- | 67 | -- |
| 58 | 2.25.1 | 68 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Gavin Shan <gshan@redhat.com> | 1 | The markup for the Arm CPU feature documentation is incorrect, |
|---|---|---|---|
| 2 | and results in the HTML not rendering correctly -- the first | ||
| 3 | line of each description is rendered in boldface as if it | ||
| 4 | were part of the option name. | ||
| 2 | 5 | ||
| 3 | When CPU-to-NUMA association isn't explicitly provided by users, | 6 | Reformat to match the styling used in cpu-models-x86.rst.inc. |
| 4 | the default one is given by mc->get_default_cpu_node_id(). However, | ||
| 5 | the CPU topology isn't fully considered in the default association | ||
| 6 | and this causes CPU topology broken warnings on booting Linux guest. | ||
| 7 | 7 | ||
| 8 | For example, the following warning messages are observed when the | 8 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1479 |
| 9 | Linux guest is booted with the following command lines. | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Message-id: 20230316105808.1414003-1-peter.maydell@linaro.org | ||
| 11 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
| 12 | --- | ||
| 13 | docs/system/arm/cpu-features.rst | 68 ++++++++++++++------------------ | ||
| 14 | 1 file changed, 30 insertions(+), 38 deletions(-) | ||
| 10 | 15 | ||
| 11 | /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ | 16 | diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst |
| 12 | -accel kvm -machine virt,gic-version=host \ | ||
| 13 | -cpu host \ | ||
| 14 | -smp 6,sockets=2,cores=3,threads=1 \ | ||
| 15 | -m 1024M,slots=16,maxmem=64G \ | ||
| 16 | -object memory-backend-ram,id=mem0,size=128M \ | ||
| 17 | -object memory-backend-ram,id=mem1,size=128M \ | ||
| 18 | -object memory-backend-ram,id=mem2,size=128M \ | ||
| 19 | -object memory-backend-ram,id=mem3,size=128M \ | ||
| 20 | -object memory-backend-ram,id=mem4,size=128M \ | ||
| 21 | -object memory-backend-ram,id=mem4,size=384M \ | ||
| 22 | -numa node,nodeid=0,memdev=mem0 \ | ||
| 23 | -numa node,nodeid=1,memdev=mem1 \ | ||
| 24 | -numa node,nodeid=2,memdev=mem2 \ | ||
| 25 | -numa node,nodeid=3,memdev=mem3 \ | ||
| 26 | -numa node,nodeid=4,memdev=mem4 \ | ||
| 27 | -numa node,nodeid=5,memdev=mem5 | ||
| 28 | : | ||
| 29 | alternatives: patching kernel code | ||
| 30 | BUG: arch topology borken | ||
| 31 | the CLS domain not a subset of the MC domain | ||
| 32 | <the above error log repeats> | ||
| 33 | BUG: arch topology borken | ||
| 34 | the DIE domain not a subset of the NODE domain | ||
| 35 | |||
| 36 | With current implementation of mc->get_default_cpu_node_id(), | ||
| 37 | CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately. | ||
| 38 | That's incorrect because CPU#0/1/2 should be associated with same | ||
| 39 | NUMA node because they're seated in same socket. | ||
| 40 | |||
| 41 | This fixes the issue by considering the socket ID when the default | ||
| 42 | CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids(). | ||
| 43 | With this applied, no more CPU topology broken warnings are seen | ||
| 44 | from the Linux guest. The 6 CPUs are associated with NODE#0/1, but | ||
| 45 | there are no CPUs associated with NODE#2/3/4/5. | ||
| 46 | |||
| 47 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
| 48 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
| 49 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
| 50 | Message-id: 20220503140304.855514-6-gshan@redhat.com | ||
| 51 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 52 | --- | ||
| 53 | hw/arm/virt.c | 4 +++- | ||
| 54 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
| 55 | |||
| 56 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 57 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 58 | --- a/hw/arm/virt.c | 18 | --- a/docs/system/arm/cpu-features.rst |
| 59 | +++ b/hw/arm/virt.c | 19 | +++ b/docs/system/arm/cpu-features.rst |
| 60 | @@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | 20 | @@ -XXX,XX +XXX,XX @@ are named with the prefix "kvm-". KVM VCPU features may be probed, |
| 61 | 21 | enabled, and disabled in the same way as other CPU features. Below is | |
| 62 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) | 22 | the list of KVM VCPU features and their descriptions. |
| 63 | { | 23 | |
| 64 | - return idx % ms->numa_state->num_nodes; | 24 | - kvm-no-adjvtime By default kvm-no-adjvtime is disabled. This |
| 65 | + int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; | 25 | - means that by default the virtual time |
| 66 | + | 26 | - adjustment is enabled (vtime is not *not* |
| 67 | + return socket_id % ms->numa_state->num_nodes; | 27 | - adjusted). |
| 68 | } | 28 | +``kvm-no-adjvtime`` |
| 69 | 29 | + By default kvm-no-adjvtime is disabled. This means that by default | |
| 70 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 30 | + the virtual time adjustment is enabled (vtime is not *not* adjusted). |
| 31 | |||
| 32 | - When virtual time adjustment is enabled each | ||
| 33 | - time the VM transitions back to running state | ||
| 34 | - the VCPU's virtual counter is updated to ensure | ||
| 35 | - stopped time is not counted. This avoids time | ||
| 36 | - jumps surprising guest OSes and applications, | ||
| 37 | - as long as they use the virtual counter for | ||
| 38 | - timekeeping. However it has the side effect of | ||
| 39 | - the virtual and physical counters diverging. | ||
| 40 | - All timekeeping based on the virtual counter | ||
| 41 | - will appear to lag behind any timekeeping that | ||
| 42 | - does not subtract VM stopped time. The guest | ||
| 43 | - may resynchronize its virtual counter with | ||
| 44 | - other time sources as needed. | ||
| 45 | + When virtual time adjustment is enabled each time the VM transitions | ||
| 46 | + back to running state the VCPU's virtual counter is updated to | ||
| 47 | + ensure stopped time is not counted. This avoids time jumps | ||
| 48 | + surprising guest OSes and applications, as long as they use the | ||
| 49 | + virtual counter for timekeeping. However it has the side effect of | ||
| 50 | + the virtual and physical counters diverging. All timekeeping based | ||
| 51 | + on the virtual counter will appear to lag behind any timekeeping | ||
| 52 | + that does not subtract VM stopped time. The guest may resynchronize | ||
| 53 | + its virtual counter with other time sources as needed. | ||
| 54 | |||
| 55 | - Enable kvm-no-adjvtime to disable virtual time | ||
| 56 | - adjustment, also restoring the legacy (pre-5.0) | ||
| 57 | - behavior. | ||
| 58 | + Enable kvm-no-adjvtime to disable virtual time adjustment, also | ||
| 59 | + restoring the legacy (pre-5.0) behavior. | ||
| 60 | |||
| 61 | - kvm-steal-time Since v5.2, kvm-steal-time is enabled by | ||
| 62 | - default when KVM is enabled, the feature is | ||
| 63 | - supported, and the guest is 64-bit. | ||
| 64 | +``kvm-steal-time`` | ||
| 65 | + Since v5.2, kvm-steal-time is enabled by default when KVM is | ||
| 66 | + enabled, the feature is supported, and the guest is 64-bit. | ||
| 67 | |||
| 68 | - When kvm-steal-time is enabled a 64-bit guest | ||
| 69 | - can account for time its CPUs were not running | ||
| 70 | - due to the host not scheduling the corresponding | ||
| 71 | - VCPU threads. The accounting statistics may | ||
| 72 | - influence the guest scheduler behavior and/or be | ||
| 73 | - exposed to the guest userspace. | ||
| 74 | + When kvm-steal-time is enabled a 64-bit guest can account for time | ||
| 75 | + its CPUs were not running due to the host not scheduling the | ||
| 76 | + corresponding VCPU threads. The accounting statistics may influence | ||
| 77 | + the guest scheduler behavior and/or be exposed to the guest | ||
| 78 | + userspace. | ||
| 79 | |||
| 80 | TCG VCPU Features | ||
| 81 | ================= | ||
| 82 | @@ -XXX,XX +XXX,XX @@ TCG VCPU Features | ||
| 83 | TCG VCPU features are CPU features that are specific to TCG. | ||
| 84 | Below is the list of TCG VCPU features and their descriptions. | ||
| 85 | |||
| 86 | - pauth-impdef When ``FEAT_Pauth`` is enabled, either the | ||
| 87 | - *impdef* (Implementation Defined) algorithm | ||
| 88 | - is enabled or the *architected* QARMA algorithm | ||
| 89 | - is enabled. By default the impdef algorithm | ||
| 90 | - is disabled, and QARMA is enabled. | ||
| 91 | +``pauth-impdef`` | ||
| 92 | + When ``FEAT_Pauth`` is enabled, either the *impdef* (Implementation | ||
| 93 | + Defined) algorithm is enabled or the *architected* QARMA algorithm | ||
| 94 | + is enabled. By default the impdef algorithm is disabled, and QARMA | ||
| 95 | + is enabled. | ||
| 96 | |||
| 97 | - The architected QARMA algorithm has good | ||
| 98 | - cryptographic properties, but can be quite slow | ||
| 99 | - to emulate. The impdef algorithm used by QEMU | ||
| 100 | - is non-cryptographic but significantly faster. | ||
| 101 | + The architected QARMA algorithm has good cryptographic properties, | ||
| 102 | + but can be quite slow to emulate. The impdef algorithm used by QEMU | ||
| 103 | + is non-cryptographic but significantly faster. | ||
| 104 | |||
| 105 | SVE CPU Properties | ||
| 106 | ================== | ||
| 71 | -- | 107 | -- |
| 72 | 2.25.1 | 108 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Gavin Shan <gshan@redhat.com> | 1 | Unfortunately a bug in older versions of gdb means that they will |
|---|---|---|---|
| 2 | crash if QEMU sends them the aarch64-pauth.xml. This bug is fixed in | ||
| 3 | gdb commit 1ba3a3222039eb25, and there are plans to backport that to | ||
| 4 | affected gdb release branches, but since the bug affects gdb 9 | ||
| 5 | through 12 it is very widely deployed (for instance by distros). | ||
| 2 | 6 | ||
| 3 | In aarch64_numa_cpu(), the CPU and NUMA association is something | 7 | It is not currently clear what the best way to deal with this is; it |
| 4 | like below. Two threads in the same core/cluster/socket are | 8 | has been proposed to define a new XML feature name that old gdb will |
| 5 | associated with two individual NUMA nodes, which is unreal as | 9 | ignore but newer gdb can handle. Since QEMU's 8.0 release is |
| 6 | Igor Mammedov mentioned. We don't expect the association to break | 10 | imminent and at least one of our CI runners is now falling over this, |
| 7 | NUMA-to-socket boundary, which matches with the real world. | 11 | disable the pauth XML for the moment. We can follow up with a more |
| 12 | considered fix either in time for 8.0 or else for the 8.1 release. | ||
| 8 | 13 | ||
| 9 | NUMA-node socket cluster core thread | ||
| 10 | ------------------------------------------ | ||
| 11 | 0 0 0 0 0 | ||
| 12 | 1 0 0 0 1 | ||
| 13 | |||
| 14 | This corrects the topology for CPUs and their association with | ||
| 15 | NUMA nodes. After this patch is applied, the CPU and NUMA | ||
| 16 | association becomes something like below, which looks real. | ||
| 17 | Besides, socket/cluster/core/thread IDs are all checked when | ||
| 18 | the NUMA node IDs are verified. It helps to check if the CPU | ||
| 19 | topology is properly populated or not. | ||
| 20 | |||
| 21 | NUMA-node socket cluster core thread | ||
| 22 | ------------------------------------------ | ||
| 23 | 0 1 0 0 0 | ||
| 24 | 1 0 0 0 0 | ||
| 25 | |||
| 26 | Suggested-by: Igor Mammedov <imammedo@redhat.com> | ||
| 27 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
| 28 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
| 29 | Message-id: 20220503140304.855514-5-gshan@redhat.com | ||
| 30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 31 | --- | 15 | --- |
| 32 | tests/qtest/numa-test.c | 18 ++++++++++++------ | 16 | target/arm/gdbstub.c | 7 +++++++ |
| 33 | 1 file changed, 12 insertions(+), 6 deletions(-) | 17 | 1 file changed, 7 insertions(+) |
| 34 | 18 | ||
| 35 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c | 19 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
| 36 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 37 | --- a/tests/qtest/numa-test.c | 21 | --- a/target/arm/gdbstub.c |
| 38 | +++ b/tests/qtest/numa-test.c | 22 | +++ b/target/arm/gdbstub.c |
| 39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | 23 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) |
| 40 | g_autofree char *cli = NULL; | 24 | aarch64_gdb_set_fpu_reg, |
| 41 | 25 | 34, "aarch64-fpu.xml", 0); | |
| 42 | cli = make_cli(data, "-machine " | 26 | } |
| 43 | - "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " | 27 | +#if 0 |
| 44 | + "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 " | 28 | + /* |
| 45 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " | 29 | + * GDB versions 9 through 12 have a bug which means they will |
| 46 | - "-numa cpu,node-id=1,thread-id=0 " | 30 | + * crash if they see this XML from QEMU; disable it for the 8.0 |
| 47 | - "-numa cpu,node-id=0,thread-id=1"); | 31 | + * release, pending a better solution. |
| 48 | + "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 " | 32 | + */ |
| 49 | + "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0"); | 33 | if (isar_feature_aa64_pauth(&cpu->isar)) { |
| 50 | qts = qtest_init(cli); | 34 | gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, |
| 51 | cpus = get_cpus(qts, &resp); | 35 | aarch64_gdb_set_pauth_reg, |
| 52 | g_assert(cpus); | 36 | 4, "aarch64-pauth.xml", 0); |
| 53 | 37 | } | |
| 54 | while ((e = qlist_pop(cpus))) { | 38 | +#endif |
| 55 | QDict *cpu, *props; | 39 | #endif |
| 56 | - int64_t thread, node; | 40 | } else { |
| 57 | + int64_t socket, cluster, core, thread, node; | 41 | if (arm_feature(env, ARM_FEATURE_NEON)) { |
| 58 | |||
| 59 | cpu = qobject_to(QDict, e); | ||
| 60 | g_assert(qdict_haskey(cpu, "props")); | ||
| 61 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | ||
| 62 | |||
| 63 | g_assert(qdict_haskey(props, "node-id")); | ||
| 64 | node = qdict_get_int(props, "node-id"); | ||
| 65 | + g_assert(qdict_haskey(props, "socket-id")); | ||
| 66 | + socket = qdict_get_int(props, "socket-id"); | ||
| 67 | + g_assert(qdict_haskey(props, "cluster-id")); | ||
| 68 | + cluster = qdict_get_int(props, "cluster-id"); | ||
| 69 | + g_assert(qdict_haskey(props, "core-id")); | ||
| 70 | + core = qdict_get_int(props, "core-id"); | ||
| 71 | g_assert(qdict_haskey(props, "thread-id")); | ||
| 72 | thread = qdict_get_int(props, "thread-id"); | ||
| 73 | |||
| 74 | - if (thread == 0) { | ||
| 75 | + if (socket == 0 && cluster == 0 && core == 0 && thread == 0) { | ||
| 76 | g_assert_cmpint(node, ==, 1); | ||
| 77 | - } else if (thread == 1) { | ||
| 78 | + } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) { | ||
| 79 | g_assert_cmpint(node, ==, 0); | ||
| 80 | } else { | ||
| 81 | g_assert(false); | ||
| 82 | -- | 42 | -- |
| 83 | 2.25.1 | 43 | 2.34.1 | diff view generated by jsdifflib |