[PULL 00/32] target-arm queue
[PULL 00/33] target-arm queue
1
target-arm queue: the big stuff here is the final part of
1
The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:
2
rth's patches for Cortex-A76 and Neoverse-N1 support;
3
also present are Gavin's NUMA series and a few other things.
4
2
5
thanks
3
Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)
6
-- PMM
7
8
The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
9
10
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
11
4
12
are available in the Git repository at:
5
are available in the Git repository at:
13
6
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203
15
8
16
for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
9
for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:
17
10
18
hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
11
target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)
19
12
20
----------------------------------------------------------------
13
----------------------------------------------------------------
21
target-arm queue:
14
target-arm queue:
22
* MAINTAINERS/.mailmap: update email for Leif Lindholm
15
* Fix physical address resolution for Stage2
23
* hw/arm: add version information to sbsa-ref machine DT
16
* pl011: refactoring, implement reset method
24
* Enable new features for -cpu max:
17
* Support GICv3 with hvf acceleration
25
FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
18
* sbsa-ref: remove cortex-a76 from list of supported cpus
26
FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
19
* Correct syndrome for ATS12NSO* traps at Secure EL1
27
* Emulate Cortex-A76
20
* Fix priority of HSTR_EL2 traps vs UNDEFs
28
* Emulate Neoverse-N1
21
* Implement FEAT_FGT for '-cpu max'
29
* Fix the virt board default NUMA topology
30
22
31
----------------------------------------------------------------
23
----------------------------------------------------------------
32
Gavin Shan (6):
24
Alexander Graf (3):
33
qapi/machine.json: Add cluster-id
25
hvf: arm: Add support for GICv3
34
qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
26
hw/arm/virt: Consolidate GIC finalize logic
35
hw/arm/virt: Consider SMP configuration in CPU topology
27
hw/arm/virt: Make accels in GIC finalize logic explicit
36
qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
37
hw/arm/virt: Fix CPU's default NUMA node ID
38
hw/acpi/aml-build: Use existing CPU topology to build PPTT table
39
28
40
Leif Lindholm (2):
29
Evgeny Iakovlev (4):
41
MAINTAINERS/.mailmap: update email for Leif Lindholm
30
hw/char/pl011: refactor FIFO depth handling code
42
hw/arm: add versioning to sbsa-ref machine DT
31
hw/char/pl011: add post_load hook for backwards-compatibility
32
hw/char/pl011: implement a reset method
33
hw/char/pl011: better handling of FIFO flags on LCR reset
43
34
44
Richard Henderson (24):
35
Marcin Juszkiewicz (1):
45
target/arm: Handle cpreg registration for missing EL
36
sbsa-ref: remove cortex-a76 from list of supported cpus
46
target/arm: Drop EL3 no EL2 fallbacks
47
target/arm: Merge zcr reginfo
48
target/arm: Adjust definition of CONTEXTIDR_EL2
49
target/arm: Move cortex impdef sysregs to cpu_tcg.c
50
target/arm: Update qemu-system-arm -cpu max to cortex-a57
51
target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
52
target/arm: Split out aa32_max_features
53
target/arm: Annotate arm_max_initfn with FEAT identifiers
54
target/arm: Use field names for manipulating EL2 and EL3 modes
55
target/arm: Enable FEAT_Debugv8p2 for -cpu max
56
target/arm: Enable FEAT_Debugv8p4 for -cpu max
57
target/arm: Add minimal RAS registers
58
target/arm: Enable SCR and HCR bits for RAS
59
target/arm: Implement virtual SError exceptions
60
target/arm: Implement ESB instruction
61
target/arm: Enable FEAT_RAS for -cpu max
62
target/arm: Enable FEAT_IESB for -cpu max
63
target/arm: Enable FEAT_CSV2 for -cpu max
64
target/arm: Enable FEAT_CSV2_2 for -cpu max
65
target/arm: Enable FEAT_CSV3 for -cpu max
66
target/arm: Enable FEAT_DGH for -cpu max
67
target/arm: Define cortex-a76
68
target/arm: Define neoverse-n1
69
37
70
docs/system/arm/emulation.rst | 10 +
38
Peter Maydell (23):
71
docs/system/arm/virt.rst | 2 +
39
target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
72
qapi/machine.json | 6 +-
40
target/arm: Correct syndrome for ATS12NSO* at Secure EL1
73
target/arm/cpregs.h | 11 +
41
target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
74
target/arm/cpu.h | 23 ++
42
target/arm: Move do_coproc_insn() syndrome calculation earlier
75
target/arm/helper.h | 1 +
43
target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
76
target/arm/internals.h | 16 ++
44
target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
77
target/arm/syndrome.h | 5 +
45
target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
78
target/arm/a32.decode | 16 +-
46
target/arm: Define the FEAT_FGT registers
79
target/arm/t32.decode | 18 +-
47
target/arm: Implement FGT trapping infrastructure
80
hw/acpi/aml-build.c | 111 ++++----
48
target/arm: Mark up sysregs for HFGRTR bits 0..11
81
hw/arm/sbsa-ref.c | 16 ++
49
target/arm: Mark up sysregs for HFGRTR bits 12..23
82
hw/arm/virt.c | 21 +-
50
target/arm: Mark up sysregs for HFGRTR bits 24..35
83
hw/core/machine-hmp-cmds.c | 4 +
51
target/arm: Mark up sysregs for HFGRTR bits 36..63
84
hw/core/machine.c | 16 ++
52
target/arm: Mark up sysregs for HDFGRTR bits 0..11
85
target/arm/cpu.c | 66 ++++-
53
target/arm: Mark up sysregs for HDFGRTR bits 12..63
86
target/arm/cpu64.c | 353 ++++++++++++++-----------
54
target/arm: Mark up sysregs for HFGITR bits 0..11
87
target/arm/cpu_tcg.c | 227 +++++++++++-----
55
target/arm: Mark up sysregs for HFGITR bits 12..17
88
target/arm/helper.c | 600 +++++++++++++++++++++++++-----------------
56
target/arm: Mark up sysregs for HFGITR bits 18..47
89
target/arm/op_helper.c | 43 +++
57
target/arm: Mark up sysregs for HFGITR bits 48..63
90
target/arm/translate-a64.c | 18 ++
58
target/arm: Implement the HFGITR_EL2.ERET trap
91
target/arm/translate.c | 23 ++
59
target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
92
tests/qtest/numa-test.c | 19 +-
60
target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
93
.mailmap | 3 +-
61
target/arm: Enable FEAT_FGT on '-cpu max'
94
MAINTAINERS | 2 +-
62
95
25 files changed, 1068 insertions(+), 562 deletions(-)
63
Richard Henderson (2):
64
hw/arm: Use TYPE_ARM_SMMUV3
65
target/arm: Fix physical address resolution for Stage2
66
67
docs/system/arm/emulation.rst | 1 +
68
include/hw/arm/virt.h | 15 +-
69
include/hw/char/pl011.h | 5 +-
70
target/arm/cpregs.h | 484 +++++++++++++++++++++++++++++++++++++++++-
71
target/arm/cpu.h | 18 ++
72
target/arm/internals.h | 20 ++
73
target/arm/syndrome.h | 10 +
74
target/arm/translate.h | 6 +
75
hw/arm/sbsa-ref.c | 4 +-
76
hw/arm/virt.c | 203 +++++++++---------
77
hw/char/pl011.c | 93 ++++++--
78
hw/intc/arm_gicv3_cpuif.c | 18 +-
79
target/arm/cpu64.c | 1 +
80
target/arm/debug_helper.c | 46 +++-
81
target/arm/helper.c | 245 ++++++++++++++++++++-
82
target/arm/hvf/hvf.c | 151 +++++++++++++
83
target/arm/op_helper.c | 58 ++++-
84
target/arm/ptw.c | 2 +-
85
target/arm/translate-a64.c | 22 +-
86
target/arm/translate.c | 125 +++++++----
87
target/arm/hvf/trace-events | 2 +
88
21 files changed, 1340 insertions(+), 189 deletions(-)
diff view generated by jsdifflib
[PULL 25/32] target/arm: Define neoverse-n1
[PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Enable the n1 for virt and sbsa board use.
3
Use the macro instead of two explicit string literals.
4
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
docs/system/arm/virt.rst | 1 +
11
hw/arm/sbsa-ref.c | 3 ++-
11
hw/arm/sbsa-ref.c | 1 +
12
hw/arm/virt.c | 2 +-
12
hw/arm/virt.c | 1 +
13
2 files changed, 3 insertions(+), 2 deletions(-)
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
15
14
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/virt.rst
19
+++ b/docs/system/arm/virt.rst
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
21
- ``cortex-a76`` (64-bit)
22
- ``a64fx`` (64-bit)
23
- ``host`` (with KVM only)
24
+- ``neoverse-n1`` (64-bit)
25
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
26
27
Note that the default is ``cortex-a15``, so for an AArch64 guest you must
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
15
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
29
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/sbsa-ref.c
17
--- a/hw/arm/sbsa-ref.c
31
+++ b/hw/arm/sbsa-ref.c
18
+++ b/hw/arm/sbsa-ref.c
32
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
19
@@ -XXX,XX +XXX,XX @@
33
ARM_CPU_TYPE_NAME("cortex-a57"),
20
#include "exec/hwaddr.h"
34
ARM_CPU_TYPE_NAME("cortex-a72"),
21
#include "kvm_arm.h"
35
ARM_CPU_TYPE_NAME("cortex-a76"),
22
#include "hw/arm/boot.h"
36
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
23
+#include "hw/arm/smmuv3.h"
37
ARM_CPU_TYPE_NAME("max"),
24
#include "hw/block/flash.h"
38
};
25
#include "hw/boards.h"
39
26
#include "hw/ide/internal.h"
27
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
28
DeviceState *dev;
29
int i;
30
31
- dev = qdev_new("arm-smmuv3");
32
+ dev = qdev_new(TYPE_ARM_SMMUV3);
33
34
object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
35
&error_abort);
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
36
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
38
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
39
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
40
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
45
ARM_CPU_TYPE_NAME("cortex-a72"),
41
return;
46
ARM_CPU_TYPE_NAME("cortex-a76"),
42
}
47
ARM_CPU_TYPE_NAME("a64fx"),
43
48
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
44
- dev = qdev_new("arm-smmuv3");
49
ARM_CPU_TYPE_NAME("host"),
45
+ dev = qdev_new(TYPE_ARM_SMMUV3);
50
ARM_CPU_TYPE_NAME("max"),
46
51
};
47
object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
48
&error_abort);
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
57
cpu->isar.mvfr2 = 0x00000043;
58
}
59
60
+static void aarch64_neoverse_n1_initfn(Object *obj)
61
+{
62
+ ARMCPU *cpu = ARM_CPU(obj);
63
+
64
+ cpu->dtb_compatible = "arm,neoverse-n1";
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
73
+
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
75
+ cpu->clidr = 0x82000023;
76
+ cpu->ctr = 0x8444c004;
77
+ cpu->dcz_blocksize = 4;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0c1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.23 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
110
+
111
+ /* From B2.98 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
123
+}
124
+
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
126
{
127
/*
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
129
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
130
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
131
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
132
+ { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
133
{ .name = "max", .initfn = aarch64_max_initfn },
134
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
135
{ .name = "host", .initfn = aarch64_host_initfn },
136
--
49
--
137
2.25.1
50
2.34.1
51
52
diff view generated by jsdifflib
[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
[PULL 02/33] target/arm: Fix physical address resolution for Stage2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This extension concerns cache speculation, which TCG does
3
Conversion to probe_access_full missed applying the page offset.
4
not implement. Thus we can trivially enable this feature.
5
4
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Cc: qemu-stable@nongnu.org
6
Reported-by: Sid Manning <sidneym@quicinc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20230126233134.103193-1-richard.henderson@linaro.org
10
Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking")
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
docs/system/arm/emulation.rst | 1 +
14
target/arm/ptw.c | 2 +-
12
target/arm/cpu64.c | 1 +
15
1 file changed, 1 insertion(+), 1 deletion(-)
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
15
16
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
19
--- a/target/arm/ptw.c
19
+++ b/docs/system/arm/emulation.rst
20
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
21
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
22
if (unlikely(flags & TLB_INVALID_MASK)) {
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
23
goto fail;
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
24
}
24
+- FEAT_CSV3 (Cache speculation variant 3)
25
- ptw->out_phys = full->phys_addr;
25
- FEAT_DIT (Data Independent Timing instructions)
26
+ ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
26
- FEAT_DPB (DC CVAP instruction)
27
ptw->out_rw = full->prot & PAGE_WRITE;
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
28
pte_attrs = full->pte_attrs;
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
29
pte_secure = full->attrs.secure;
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu64.c
31
+++ b/target/arm/cpu64.c
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
33
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
34
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
35
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
37
cpu->isar.id_aa64pfr0 = t;
38
39
t = cpu->isar.id_aa64pfr1;
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu_tcg.c
43
+++ b/target/arm/cpu_tcg.c
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
45
cpu->isar.id_pfr0 = t;
46
47
t = cpu->isar.id_pfr2;
48
+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
49
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
50
cpu->isar.id_pfr2 = t;
51
52
--
30
--
53
2.25.1
31
2.34.1
32
33
diff view generated by jsdifflib
[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
[PULL 03/33] hw/char/pl011: refactor FIFO depth handling code
1
From: Gavin Shan <gshan@redhat.com>
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
2
3
The CPU topology isn't enabled on arm/virt machine yet, but we're
3
PL011 can be in either of 2 modes depending guest config: FIFO and
4
going to do it in next patch. After the CPU topology is enabled by
4
single register. The last mode could be viewed as a 1-element-deep FIFO.
5
next patch, "thread-id=1" becomes invalid because the CPU core is
6
preferred on arm/virt machine. It means these two CPUs have 0/1
7
as their core IDs, but their thread IDs are all 0. It will trigger
8
test failure as the following message indicates:
9
5
10
[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR
6
Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
11
1.48s killed by signal 6 SIGABRT
7
depth handling code to isolate calculating current FIFO depth.
12
>>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
13
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \
14
QTEST_QEMU_BINARY=./qemu-system-aarch64 \
15
QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \
16
/home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
17
――――――――――――――――――――――――――――――――――――――――――――――
18
stderr:
19
qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
20
8
21
This fixes the issue by providing comprehensive SMP configurations
9
One functional (albeit guest-invisible) side-effect of this change is
22
in aarch64_numa_cpu(). The SMP configurations aren't used before
10
that previously we would always increment s->read_pos in UARTDR read
23
the CPU topology is enabled in next patch.
11
handler even if FIFO was disabled, now we are limiting read_pos to not
12
exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
24
13
25
Signed-off-by: Gavin Shan <gshan@redhat.com>
14
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
26
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Message-id: 20220503140304.855514-3-gshan@redhat.com
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
---
19
---
30
tests/qtest/numa-test.c | 3 ++-
20
include/hw/char/pl011.h | 5 ++++-
31
1 file changed, 2 insertions(+), 1 deletion(-)
21
hw/char/pl011.c | 30 ++++++++++++++++++------------
22
2 files changed, 22 insertions(+), 13 deletions(-)
32
23
33
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
24
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
34
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
35
--- a/tests/qtest/numa-test.c
26
--- a/include/hw/char/pl011.h
36
+++ b/tests/qtest/numa-test.c
27
+++ b/include/hw/char/pl011.h
37
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
28
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
38
QTestState *qts;
29
/* This shares the same struct (and cast macro) as the base pl011 device */
39
g_autofree char *cli = NULL;
30
#define TYPE_PL011_LUMINARY "pl011_luminary"
40
31
41
- cli = make_cli(data, "-machine smp.cpus=2 "
32
+/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
42
+ cli = make_cli(data, "-machine "
33
+#define PL011_FIFO_DEPTH 16
43
+ "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
34
+
44
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
35
struct PL011State {
45
"-numa cpu,node-id=1,thread-id=0 "
36
SysBusDevice parent_obj;
46
"-numa cpu,node-id=0,thread-id=1");
37
38
@@ -XXX,XX +XXX,XX @@ struct PL011State {
39
uint32_t dmacr;
40
uint32_t int_enabled;
41
uint32_t int_level;
42
- uint32_t read_fifo[16];
43
+ uint32_t read_fifo[PL011_FIFO_DEPTH];
44
uint32_t ilpr;
45
uint32_t ibrd;
46
uint32_t fbrd;
47
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/char/pl011.c
50
+++ b/hw/char/pl011.c
51
@@ -XXX,XX +XXX,XX @@ static void pl011_update(PL011State *s)
52
}
53
}
54
55
+static bool pl011_is_fifo_enabled(PL011State *s)
56
+{
57
+ return (s->lcr & 0x10) != 0;
58
+}
59
+
60
+static inline unsigned pl011_get_fifo_depth(PL011State *s)
61
+{
62
+ /* Note: FIFO depth is expected to be power-of-2 */
63
+ return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
64
+}
65
+
66
static uint64_t pl011_read(void *opaque, hwaddr offset,
67
unsigned size)
68
{
69
@@ -XXX,XX +XXX,XX @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
70
c = s->read_fifo[s->read_pos];
71
if (s->read_count > 0) {
72
s->read_count--;
73
- if (++s->read_pos == 16)
74
- s->read_pos = 0;
75
+ s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
76
}
77
if (s->read_count == 0) {
78
s->flags |= PL011_FLAG_RXFE;
79
@@ -XXX,XX +XXX,XX @@ static int pl011_can_receive(void *opaque)
80
PL011State *s = (PL011State *)opaque;
81
int r;
82
83
- if (s->lcr & 0x10) {
84
- r = s->read_count < 16;
85
- } else {
86
- r = s->read_count < 1;
87
- }
88
+ r = s->read_count < pl011_get_fifo_depth(s);
89
trace_pl011_can_receive(s->lcr, s->read_count, r);
90
return r;
91
}
92
@@ -XXX,XX +XXX,XX @@ static void pl011_put_fifo(void *opaque, uint32_t value)
93
{
94
PL011State *s = (PL011State *)opaque;
95
int slot;
96
+ unsigned pipe_depth;
97
98
- slot = s->read_pos + s->read_count;
99
- if (slot >= 16)
100
- slot -= 16;
101
+ pipe_depth = pl011_get_fifo_depth(s);
102
+ slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
103
s->read_fifo[slot] = value;
104
s->read_count++;
105
s->flags &= ~PL011_FLAG_RXFE;
106
trace_pl011_put_fifo(value, s->read_count);
107
- if (!(s->lcr & 0x10) || s->read_count == 16) {
108
+ if (s->read_count == pipe_depth) {
109
trace_pl011_put_fifo_full();
110
s->flags |= PL011_FLAG_RXFF;
111
}
112
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011 = {
113
VMSTATE_UINT32(dmacr, PL011State),
114
VMSTATE_UINT32(int_enabled, PL011State),
115
VMSTATE_UINT32(int_level, PL011State),
116
- VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
117
+ VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH),
118
VMSTATE_UINT32(ilpr, PL011State),
119
VMSTATE_UINT32(ibrd, PL011State),
120
VMSTATE_UINT32(fbrd, PL011State),
47
--
121
--
48
2.25.1
122
2.34.1
49
123
50
124
diff view generated by jsdifflib
[PULL 09/32] target/arm: Split out aa32_max_features
[PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
2
3
Share the code to set AArch32 max features so that we no
3
Previous change slightly modified the way we handle data writes when
4
longer have code drift between qemu{-system,}-{arm,aarch64}.
4
FIFO is disabled. Previously we kept incrementing read_pos and were
5
storing data at that position, although we only have a
6
single-register-deep FIFO now. Then we changed it to always store data
7
at pos 0.
5
8
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
If guest disables FIFO and the proceeds to read data, it will work out
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
fine, because we still read from current read_pos before setting it to
8
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
11
0.
12
13
However, to make code less fragile, introduce a post_load hook for
14
PL011State and move fixup read FIFO state when FIFO is disabled. Since
15
we are introducing a post_load hook, also do some sanity checking on
16
untrusted incoming input state.
17
18
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
19
Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
21
---
11
target/arm/internals.h | 2 +
22
hw/char/pl011.c | 25 +++++++++++++++++++++++++
12
target/arm/cpu64.c | 50 +-----------------
23
1 file changed, 25 insertions(+)
13
target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++-------------------
14
3 files changed, 65 insertions(+), 101 deletions(-)
15
24
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
25
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
17
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
27
--- a/hw/char/pl011.c
19
+++ b/target/arm/internals.h
28
+++ b/hw/char/pl011.c
20
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
29
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011_clock = {
21
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
30
}
22
#endif
31
};
23
32
24
+void aa32_max_features(ARMCPU *cpu);
33
+static int pl011_post_load(void *opaque, int version_id)
34
+{
35
+ PL011State* s = opaque;
25
+
36
+
26
#endif
37
+ /* Sanity-check input state */
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
38
+ if (s->read_pos >= ARRAY_SIZE(s->read_fifo) ||
28
index XXXXXXX..XXXXXXX 100644
39
+ s->read_count > ARRAY_SIZE(s->read_fifo)) {
29
--- a/target/arm/cpu64.c
40
+ return -1;
30
+++ b/target/arm/cpu64.c
41
+ }
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
32
{
33
ARMCPU *cpu = ARM_CPU(obj);
34
uint64_t t;
35
- uint32_t u;
36
37
if (kvm_enabled() || hvf_enabled()) {
38
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
40
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
41
cpu->isar.id_aa64zfr0 = t;
42
43
- /* Replicate the same data to the 32-bit id registers. */
44
- u = cpu->isar.id_isar5;
45
- u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
46
- u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
47
- u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
48
- u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
49
- u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
50
- u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
51
- cpu->isar.id_isar5 = u;
52
-
53
- u = cpu->isar.id_isar6;
54
- u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
55
- u = FIELD_DP32(u, ID_ISAR6, DP, 1);
56
- u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
57
- u = FIELD_DP32(u, ID_ISAR6, SB, 1);
58
- u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
59
- u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
60
- u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
61
- cpu->isar.id_isar6 = u;
62
-
63
- u = cpu->isar.id_pfr0;
64
- u = FIELD_DP32(u, ID_PFR0, DIT, 1);
65
- cpu->isar.id_pfr0 = u;
66
-
67
- u = cpu->isar.id_pfr2;
68
- u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
69
- cpu->isar.id_pfr2 = u;
70
-
71
- u = cpu->isar.id_mmfr3;
72
- u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
73
- cpu->isar.id_mmfr3 = u;
74
-
75
- u = cpu->isar.id_mmfr4;
76
- u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
77
- u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
78
- u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
79
- u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
80
- cpu->isar.id_mmfr4 = u;
81
-
82
t = cpu->isar.id_aa64dfr0;
83
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
84
cpu->isar.id_aa64dfr0 = t;
85
86
- u = cpu->isar.id_dfr0;
87
- u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
88
- cpu->isar.id_dfr0 = u;
89
-
90
- u = cpu->isar.mvfr1;
91
- u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
92
- u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
93
- cpu->isar.mvfr1 = u;
94
+ /* Replicate the same data to the 32-bit id registers. */
95
+ aa32_max_features(cpu);
96
97
#ifdef CONFIG_USER_ONLY
98
/*
99
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/cpu_tcg.c
102
+++ b/target/arm/cpu_tcg.c
103
@@ -XXX,XX +XXX,XX @@
104
#endif
105
#include "cpregs.h"
106
107
+
42
+
108
+/* Share AArch32 -cpu max features with AArch64. */
43
+ if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) {
109
+void aa32_max_features(ARMCPU *cpu)
44
+ /*
110
+{
45
+ * Older versions of PL011 didn't ensure that the single
111
+ uint32_t t;
46
+ * character in the FIFO in FIFO-disabled mode is in
47
+ * element 0 of the array; convert to follow the current
48
+ * code's assumptions.
49
+ */
50
+ s->read_fifo[0] = s->read_fifo[s->read_pos];
51
+ s->read_pos = 0;
52
+ }
112
+
53
+
113
+ /* Add additional features supported by QEMU */
54
+ return 0;
114
+ t = cpu->isar.id_isar5;
115
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
116
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
117
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
118
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
119
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
120
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
121
+ cpu->isar.id_isar5 = t;
122
+
123
+ t = cpu->isar.id_isar6;
124
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
125
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
126
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
127
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
128
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
129
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
130
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
131
+ cpu->isar.id_isar6 = t;
132
+
133
+ t = cpu->isar.mvfr1;
134
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
135
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
136
+ cpu->isar.mvfr1 = t;
137
+
138
+ t = cpu->isar.mvfr2;
139
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
140
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
141
+ cpu->isar.mvfr2 = t;
142
+
143
+ t = cpu->isar.id_mmfr3;
144
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
145
+ cpu->isar.id_mmfr3 = t;
146
+
147
+ t = cpu->isar.id_mmfr4;
148
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
149
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
150
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
151
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
152
+ cpu->isar.id_mmfr4 = t;
153
+
154
+ t = cpu->isar.id_pfr0;
155
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
156
+ cpu->isar.id_pfr0 = t;
157
+
158
+ t = cpu->isar.id_pfr2;
159
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
160
+ cpu->isar.id_pfr2 = t;
161
+
162
+ t = cpu->isar.id_dfr0;
163
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
164
+ cpu->isar.id_dfr0 = t;
165
+}
55
+}
166
+
56
+
167
#ifndef CONFIG_USER_ONLY
57
static const VMStateDescription vmstate_pl011 = {
168
static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
58
.name = "pl011",
169
{
59
.version_id = 2,
170
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
60
.minimum_version_id = 2,
171
static void arm_max_initfn(Object *obj)
61
+ .post_load = pl011_post_load,
172
{
62
.fields = (VMStateField[]) {
173
ARMCPU *cpu = ARM_CPU(obj);
63
VMSTATE_UINT32(readbuff, PL011State),
174
- uint32_t t;
64
VMSTATE_UINT32(flags, PL011State),
175
176
/* aarch64_a57_initfn, advertising none of the aarch64 features */
177
cpu->dtb_compatible = "arm,cortex-a57";
178
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
179
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
180
define_cortex_a72_a57_a53_cp_reginfo(cpu);
181
182
- /* Add additional features supported by QEMU */
183
- t = cpu->isar.id_isar5;
184
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
185
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
186
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
187
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
188
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
189
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
190
- cpu->isar.id_isar5 = t;
191
-
192
- t = cpu->isar.id_isar6;
193
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
194
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
195
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
196
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
197
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
198
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
199
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
200
- cpu->isar.id_isar6 = t;
201
-
202
- t = cpu->isar.mvfr1;
203
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
204
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
205
- cpu->isar.mvfr1 = t;
206
-
207
- t = cpu->isar.mvfr2;
208
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
- cpu->isar.mvfr2 = t;
211
-
212
- t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
- cpu->isar.id_mmfr3 = t;
215
-
216
- t = cpu->isar.id_mmfr4;
217
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
218
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
219
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
220
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
221
- cpu->isar.id_mmfr4 = t;
222
-
223
- t = cpu->isar.id_pfr0;
224
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
225
- cpu->isar.id_pfr0 = t;
226
-
227
- t = cpu->isar.id_pfr2;
228
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
229
- cpu->isar.id_pfr2 = t;
230
-
231
- t = cpu->isar.id_dfr0;
232
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
233
- cpu->isar.id_dfr0 = t;
234
+ aa32_max_features(cpu);
235
236
#ifdef CONFIG_USER_ONLY
237
/*
238
--
65
--
239
2.25.1
66
2.34.1
diff view generated by jsdifflib
[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
[PULL 05/33] hw/char/pl011: implement a reset method
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
2
3
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
3
PL011 currently lacks a reset method. Implement it.
4
separate infrastructure for a transitional period. We've now switched
5
over to contributing as Qualcomm Innovation Center (quicinc), so update
6
my email address to reflect this.
7
4
8
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
5
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
9
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Cc: Leif Lindholm <leif@nuviainc.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
[Fixed commit message typo]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
.mailmap | 3 ++-
11
hw/char/pl011.c | 26 +++++++++++++++++++++-----
17
MAINTAINERS | 2 +-
12
1 file changed, 21 insertions(+), 5 deletions(-)
18
2 files changed, 3 insertions(+), 2 deletions(-)
19
13
20
diff --git a/.mailmap b/.mailmap
14
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/.mailmap
16
--- a/hw/char/pl011.c
23
+++ b/.mailmap
17
+++ b/hw/char/pl011.c
24
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
18
@@ -XXX,XX +XXX,XX @@ static void pl011_init(Object *obj)
25
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
19
s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s,
26
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
20
ClockUpdate);
27
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
21
28
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
22
- s->read_trigger = 1;
29
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
23
- s->ifl = 0x12;
30
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
24
- s->cr = 0x300;
31
Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
25
- s->flags = 0x90;
32
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
26
-
33
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
27
s->id = pl011_id_arm;
34
diff --git a/MAINTAINERS b/MAINTAINERS
28
}
35
index XXXXXXX..XXXXXXX 100644
29
36
--- a/MAINTAINERS
30
@@ -XXX,XX +XXX,XX @@ static void pl011_realize(DeviceState *dev, Error **errp)
37
+++ b/MAINTAINERS
31
pl011_event, NULL, s, NULL, true);
38
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
32
}
39
SBSA-REF
33
40
M: Radoslaw Biernacki <rad@semihalf.com>
34
+static void pl011_reset(DeviceState *dev)
41
M: Peter Maydell <peter.maydell@linaro.org>
35
+{
42
-R: Leif Lindholm <leif@nuviainc.com>
36
+ PL011State *s = PL011(dev);
43
+R: Leif Lindholm <quic_llindhol@quicinc.com>
37
+
44
L: qemu-arm@nongnu.org
38
+ s->lcr = 0;
45
S: Maintained
39
+ s->rsr = 0;
46
F: hw/arm/sbsa-ref.c
40
+ s->dmacr = 0;
41
+ s->int_enabled = 0;
42
+ s->int_level = 0;
43
+ s->ilpr = 0;
44
+ s->ibrd = 0;
45
+ s->fbrd = 0;
46
+ s->read_pos = 0;
47
+ s->read_count = 0;
48
+ s->read_trigger = 1;
49
+ s->ifl = 0x12;
50
+ s->cr = 0x300;
51
+ s->flags = 0x90;
52
+}
53
+
54
static void pl011_class_init(ObjectClass *oc, void *data)
55
{
56
DeviceClass *dc = DEVICE_CLASS(oc);
57
58
dc->realize = pl011_realize;
59
+ dc->reset = pl011_reset;
60
dc->vmsd = &vmstate_pl011;
61
device_class_set_props(dc, pl011_properties);
62
}
47
--
63
--
48
2.25.1
64
2.34.1
49
65
50
66
diff view generated by jsdifflib
[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
[PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
2
3
Update the legacy feature names to the current names.
3
Current FIFO handling code does not reset RXFE/RXFF flags when guest
4
Provide feature names for id changes that were not marked.
4
resets FIFO by writing to UARTLCR register, although internal FIFO state
5
Sort the field updates into increasing bitfield order.
5
is reset to 0 read count. Actual guest-visible flag update will happen
6
only on next data read or write attempt. As a result of that any guest
7
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
8
FIFO will never see that happen.
6
9
10
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
9
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
target/arm/cpu64.c | 100 +++++++++++++++++++++----------------------
15
hw/char/pl011.c | 18 +++++++++++++-----
13
target/arm/cpu_tcg.c | 48 ++++++++++-----------
16
1 file changed, 13 insertions(+), 5 deletions(-)
14
2 files changed, 74 insertions(+), 74 deletions(-)
15
17
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
18
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu64.c
20
--- a/hw/char/pl011.c
19
+++ b/target/arm/cpu64.c
21
+++ b/hw/char/pl011.c
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
22
@@ -XXX,XX +XXX,XX @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
21
cpu->midr = t;
23
return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
22
23
t = cpu->isar.id_aa64isar0;
24
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
25
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
26
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
27
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
28
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
29
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
30
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
31
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
32
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
33
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
34
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
35
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
36
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
37
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
38
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
39
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
40
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
41
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
42
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
43
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
44
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
45
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
46
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
47
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
48
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
49
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
50
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
51
cpu->isar.id_aa64isar0 = t;
52
53
t = cpu->isar.id_aa64isar1;
54
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
55
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
56
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
57
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
58
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
59
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
60
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
61
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
62
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
63
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
64
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
65
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
66
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
67
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
68
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
69
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
70
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
71
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
72
cpu->isar.id_aa64isar1 = t;
73
74
t = cpu->isar.id_aa64pfr0;
75
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
76
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
77
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
78
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
79
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
80
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
81
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
82
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
83
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
84
cpu->isar.id_aa64pfr0 = t;
85
86
t = cpu->isar.id_aa64pfr1;
87
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
88
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
89
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
90
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
91
/*
92
* Begin with full support for MTE. This will be downgraded to MTE=0
93
* during realize if the board provides no tag memory, much like
94
* we do for EL2 with the virtualization=on property.
95
*/
96
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
97
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
98
cpu->isar.id_aa64pfr1 = t;
99
100
t = cpu->isar.id_aa64mmfr0;
101
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
102
cpu->isar.id_aa64mmfr0 = t;
103
104
t = cpu->isar.id_aa64mmfr1;
105
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
106
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
107
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
108
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
109
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
110
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
111
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
112
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
113
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
114
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
115
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
116
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
117
cpu->isar.id_aa64mmfr1 = t;
118
119
t = cpu->isar.id_aa64mmfr2;
120
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
121
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
122
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
123
- t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
124
- t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
125
- t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
126
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
127
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
128
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
129
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
130
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
131
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
132
cpu->isar.id_aa64mmfr2 = t;
133
134
t = cpu->isar.id_aa64zfr0;
135
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
136
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
137
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
138
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
139
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
140
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
141
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
142
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
143
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
144
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
145
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
146
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
147
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
148
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
149
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
150
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
151
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
152
cpu->isar.id_aa64zfr0 = t;
153
154
t = cpu->isar.id_aa64dfr0;
155
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
156
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
157
cpu->isar.id_aa64dfr0 = t;
158
159
/* Replicate the same data to the 32-bit id registers. */
160
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/arm/cpu_tcg.c
163
+++ b/target/arm/cpu_tcg.c
164
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
165
166
/* Add additional features supported by QEMU */
167
t = cpu->isar.id_isar5;
168
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
169
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
170
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
171
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
172
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
173
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
174
t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
175
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
176
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
177
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
178
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
179
cpu->isar.id_isar5 = t;
180
181
t = cpu->isar.id_isar6;
182
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
183
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
184
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
185
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
186
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
187
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
188
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
189
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
190
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
191
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
192
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
193
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
194
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
195
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
196
cpu->isar.id_isar6 = t;
197
198
t = cpu->isar.mvfr1;
199
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
200
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
201
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
202
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
203
cpu->isar.mvfr1 = t;
204
205
t = cpu->isar.mvfr2;
206
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
207
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
208
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
cpu->isar.mvfr2 = t;
211
212
t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
215
cpu->isar.id_mmfr3 = t;
216
217
t = cpu->isar.id_mmfr4;
218
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
219
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
220
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
221
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
222
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
223
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
224
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
225
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/
226
cpu->isar.id_mmfr4 = t;
227
228
t = cpu->isar.id_pfr0;
229
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
230
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
231
cpu->isar.id_pfr0 = t;
232
233
t = cpu->isar.id_pfr2;
234
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
235
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
236
cpu->isar.id_pfr2 = t;
237
238
t = cpu->isar.id_dfr0;
239
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
240
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
241
cpu->isar.id_dfr0 = t;
242
}
24
}
243
25
26
+static inline void pl011_reset_fifo(PL011State *s)
27
+{
28
+ s->read_count = 0;
29
+ s->read_pos = 0;
30
+
31
+ /* Reset FIFO flags */
32
+ s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
33
+ s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
34
+}
35
+
36
static uint64_t pl011_read(void *opaque, hwaddr offset,
37
unsigned size)
38
{
39
@@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset,
40
case 11: /* UARTLCR_H */
41
/* Reset the FIFO state on FIFO enable or disable */
42
if ((s->lcr ^ value) & 0x10) {
43
- s->read_count = 0;
44
- s->read_pos = 0;
45
+ pl011_reset_fifo(s);
46
}
47
if ((s->lcr ^ value) & 0x1) {
48
int break_enable = value & 0x1;
49
@@ -XXX,XX +XXX,XX @@ static void pl011_reset(DeviceState *dev)
50
s->ilpr = 0;
51
s->ibrd = 0;
52
s->fbrd = 0;
53
- s->read_pos = 0;
54
- s->read_count = 0;
55
s->read_trigger = 1;
56
s->ifl = 0x12;
57
s->cr = 0x300;
58
- s->flags = 0x90;
59
+ s->flags = 0;
60
+ pl011_reset_fifo(s);
61
}
62
63
static void pl011_class_init(ObjectClass *oc, void *data)
244
--
64
--
245
2.25.1
65
2.34.1
diff view generated by jsdifflib
[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
[PULL 07/33] hvf: arm: Add support for GICv3
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
The sbsa-ref machine is continuously evolving. Some of the changes we
3
We currently only support GICv2 emulation. To also support GICv3, we will
4
want to make in the near future, to align with real components (e.g.
4
need to pass a few system registers into their respective handler functions.
5
the GIC-700), will break compatibility for existing firmware.
5
6
6
This patch adds support for HVF to call into the TCG callbacks for GICv3
7
Introduce two new properties to the DT generated on machine generation:
7
system register handlers. This is safe because the GICv3 TCG code is generic
8
- machine-version-major
8
as long as we limit ourselves to EL0 and EL1 - which are the only modes
9
To be incremented when a platform change makes the machine
9
supported by HVF.
10
incompatible with existing firmware.
10
11
- machine-version-minor
11
To make sure nobody trips over that, we also annotate callbacks that don't
12
To be incremented when functionality is added to the machine
12
work in HVF mode, such as EL state change hooks.
13
without causing incompatibility with existing firmware.
13
14
to be reset to 0 when machine-version-major is incremented.
14
With GICv3 support in place, we can run with more than 8 vCPUs.
15
15
16
This versioning scheme is *neither*:
16
Signed-off-by: Alexander Graf <agraf@csgraf.de>
17
- A QEMU versioned machine type; a given version of QEMU will emulate
17
Message-id: 20230128224459.70676-1-agraf@csgraf.de
18
a given version of the platform.
19
- A reflection of level of SBSA (now SystemReady SR) support provided.
20
21
The version will increment on guest-visible functional changes only,
22
akin to a revision ID register found on a physical platform.
23
24
These properties are both introduced with the value 0.
25
(Hence, a machine where the DT is lacking these nodes is equivalent
26
to version 0.0.)
27
28
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
29
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
30
Cc: Peter Maydell <peter.maydell@linaro.org>
31
Cc: Radoslaw Biernacki <rad@semihalf.com>
32
Cc: Cédric Le Goater <clg@kaod.org>
33
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
---
20
---
36
hw/arm/sbsa-ref.c | 14 ++++++++++++++
21
hw/intc/arm_gicv3_cpuif.c | 16 +++-
37
1 file changed, 14 insertions(+)
22
target/arm/hvf/hvf.c | 151 ++++++++++++++++++++++++++++++++++++
38
23
target/arm/hvf/trace-events | 2 +
39
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
24
3 files changed, 168 insertions(+), 1 deletion(-)
25
26
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
40
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/sbsa-ref.c
28
--- a/hw/intc/arm_gicv3_cpuif.c
42
+++ b/hw/arm/sbsa-ref.c
29
+++ b/hw/intc/arm_gicv3_cpuif.c
43
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
30
@@ -XXX,XX +XXX,XX @@
44
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
31
#include "hw/irq.h"
45
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
32
#include "cpu.h"
46
33
#include "target/arm/cpregs.h"
47
+ /*
34
+#include "sysemu/tcg.h"
48
+ * This versioning scheme is for informing platform fw only. It is neither:
35
+#include "sysemu/qtest.h"
49
+ * - A QEMU versioned machine type; a given version of QEMU will emulate
36
50
+ * a given version of the platform.
37
/*
51
+ * - A reflection of level of SBSA (now SystemReady SR) support provided.
38
* Special case return value from hppvi_index(); must be larger than
52
+ *
39
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
53
+ * machine-version-major: updated when changes breaking fw compatibility
40
* which case we'd get the wrong value.
54
+ * are introduced.
41
* So instead we define the regs with no ri->opaque info, and
55
+ * machine-version-minor: updated when features are added that don't break
42
* get back to the GICv3CPUState from the CPUARMState.
56
+ * fw compatibility.
43
+ *
57
+ */
44
+ * These CP regs callbacks can be called from either TCG or HVF code.
58
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
45
*/
59
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
46
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
60
+
47
61
if (ms->numa_state->have_numa_distance) {
48
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
62
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
49
define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo);
63
uint32_t *matrix = g_malloc0(size);
50
}
51
}
52
- arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
53
+ if (tcg_enabled() || qtest_enabled()) {
54
+ /*
55
+ * We can only trap EL changes with TCG. However the GIC interrupt
56
+ * state only changes on EL changes involving EL2 or EL3, so for
57
+ * the non-TCG case this is OK, as EL2 and EL3 can't exist.
58
+ */
59
+ arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
60
+ } else {
61
+ assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2));
62
+ assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3));
63
+ }
64
}
65
}
66
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/hvf/hvf.c
69
+++ b/target/arm/hvf/hvf.c
70
@@ -XXX,XX +XXX,XX @@
71
#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)
72
#define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)
73
74
+#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4)
75
+#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5)
76
+#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6)
77
+#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7)
78
+#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0)
79
+#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1)
80
+#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2)
81
+#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3)
82
+#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6)
83
+#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3)
84
+#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3)
85
+#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4)
86
+#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1)
87
+#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1)
88
+#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1)
89
+#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2)
90
+#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2)
91
+#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0)
92
+#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0)
93
+#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6)
94
+#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7)
95
+#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0)
96
+#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3)
97
+#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7)
98
+#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5)
99
+#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5)
100
+
101
#define WFX_IS_WFE (1 << 0)
102
103
#define TMR_CTL_ENABLE (1 << 0)
104
@@ -XXX,XX +XXX,XX @@ static bool is_id_sysreg(uint32_t reg)
105
SYSREG_CRM(reg) < 8;
106
}
107
108
+static uint32_t hvf_reg2cp_reg(uint32_t reg)
109
+{
110
+ return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
111
+ (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
112
+ (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
113
+ (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
114
+ (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
115
+ (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
116
+}
117
+
118
+static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
119
+{
120
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
121
+ CPUARMState *env = &arm_cpu->env;
122
+ const ARMCPRegInfo *ri;
123
+
124
+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
125
+ if (ri) {
126
+ if (ri->accessfn) {
127
+ if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) {
128
+ return false;
129
+ }
130
+ }
131
+ if (ri->type & ARM_CP_CONST) {
132
+ *val = ri->resetvalue;
133
+ } else if (ri->readfn) {
134
+ *val = ri->readfn(env, ri);
135
+ } else {
136
+ *val = CPREG_FIELD64(env, ri);
137
+ }
138
+ trace_hvf_vgic_read(ri->name, *val);
139
+ return true;
140
+ }
141
+
142
+ return false;
143
+}
144
+
145
static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
146
{
147
ARMCPU *arm_cpu = ARM_CPU(cpu);
148
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
149
case SYSREG_OSDLR_EL1:
150
/* Dummy register */
151
break;
152
+ case SYSREG_ICC_AP0R0_EL1:
153
+ case SYSREG_ICC_AP0R1_EL1:
154
+ case SYSREG_ICC_AP0R2_EL1:
155
+ case SYSREG_ICC_AP0R3_EL1:
156
+ case SYSREG_ICC_AP1R0_EL1:
157
+ case SYSREG_ICC_AP1R1_EL1:
158
+ case SYSREG_ICC_AP1R2_EL1:
159
+ case SYSREG_ICC_AP1R3_EL1:
160
+ case SYSREG_ICC_ASGI1R_EL1:
161
+ case SYSREG_ICC_BPR0_EL1:
162
+ case SYSREG_ICC_BPR1_EL1:
163
+ case SYSREG_ICC_DIR_EL1:
164
+ case SYSREG_ICC_EOIR0_EL1:
165
+ case SYSREG_ICC_EOIR1_EL1:
166
+ case SYSREG_ICC_HPPIR0_EL1:
167
+ case SYSREG_ICC_HPPIR1_EL1:
168
+ case SYSREG_ICC_IAR0_EL1:
169
+ case SYSREG_ICC_IAR1_EL1:
170
+ case SYSREG_ICC_IGRPEN0_EL1:
171
+ case SYSREG_ICC_IGRPEN1_EL1:
172
+ case SYSREG_ICC_PMR_EL1:
173
+ case SYSREG_ICC_SGI0R_EL1:
174
+ case SYSREG_ICC_SGI1R_EL1:
175
+ case SYSREG_ICC_SRE_EL1:
176
+ case SYSREG_ICC_CTLR_EL1:
177
+ /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
178
+ if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
179
+ hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
180
+ }
181
+ break;
182
default:
183
if (is_id_sysreg(reg)) {
184
/* ID system registers read as RES0 */
185
@@ -XXX,XX +XXX,XX @@ static void pmswinc_write(CPUARMState *env, uint64_t value)
186
}
187
}
188
189
+static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
190
+{
191
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
192
+ CPUARMState *env = &arm_cpu->env;
193
+ const ARMCPRegInfo *ri;
194
+
195
+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
196
+
197
+ if (ri) {
198
+ if (ri->accessfn) {
199
+ if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) {
200
+ return false;
201
+ }
202
+ }
203
+ if (ri->writefn) {
204
+ ri->writefn(env, ri, val);
205
+ } else {
206
+ CPREG_FIELD64(env, ri) = val;
207
+ }
208
+
209
+ trace_hvf_vgic_write(ri->name, val);
210
+ return true;
211
+ }
212
+
213
+ return false;
214
+}
215
+
216
static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
217
{
218
ARMCPU *arm_cpu = ARM_CPU(cpu);
219
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
220
case SYSREG_OSDLR_EL1:
221
/* Dummy register */
222
break;
223
+ case SYSREG_ICC_AP0R0_EL1:
224
+ case SYSREG_ICC_AP0R1_EL1:
225
+ case SYSREG_ICC_AP0R2_EL1:
226
+ case SYSREG_ICC_AP0R3_EL1:
227
+ case SYSREG_ICC_AP1R0_EL1:
228
+ case SYSREG_ICC_AP1R1_EL1:
229
+ case SYSREG_ICC_AP1R2_EL1:
230
+ case SYSREG_ICC_AP1R3_EL1:
231
+ case SYSREG_ICC_ASGI1R_EL1:
232
+ case SYSREG_ICC_BPR0_EL1:
233
+ case SYSREG_ICC_BPR1_EL1:
234
+ case SYSREG_ICC_CTLR_EL1:
235
+ case SYSREG_ICC_DIR_EL1:
236
+ case SYSREG_ICC_EOIR0_EL1:
237
+ case SYSREG_ICC_EOIR1_EL1:
238
+ case SYSREG_ICC_HPPIR0_EL1:
239
+ case SYSREG_ICC_HPPIR1_EL1:
240
+ case SYSREG_ICC_IAR0_EL1:
241
+ case SYSREG_ICC_IAR1_EL1:
242
+ case SYSREG_ICC_IGRPEN0_EL1:
243
+ case SYSREG_ICC_IGRPEN1_EL1:
244
+ case SYSREG_ICC_PMR_EL1:
245
+ case SYSREG_ICC_SGI0R_EL1:
246
+ case SYSREG_ICC_SGI1R_EL1:
247
+ case SYSREG_ICC_SRE_EL1:
248
+ /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
249
+ if (!hvf_sysreg_write_cp(cpu, reg, val)) {
250
+ hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
251
+ }
252
+ break;
253
default:
254
cpu_synchronize_state(cpu);
255
trace_hvf_unhandled_sysreg_write(env->pc, reg,
256
diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
257
index XXXXXXX..XXXXXXX 100644
258
--- a/target/arm/hvf/trace-events
259
+++ b/target/arm/hvf/trace-events
260
@@ -XXX,XX +XXX,XX @@ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
261
hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
262
hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
263
hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
264
+hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]"
265
+hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]"
64
--
266
--
65
2.25.1
267
2.34.1
66
67
diff view generated by jsdifflib
[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
[PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic
1
From: Gavin Shan <gshan@redhat.com>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
When CPU-to-NUMA association isn't explicitly provided by users,
3
Up to now, the finalize_gic_version() code open coded what is essentially
4
the default one is given by mc->get_default_cpu_node_id(). However,
4
a support bitmap match between host/emulation environment and desired
5
the CPU topology isn't fully considered in the default association
5
target GIC type.
6
and this causes CPU topology broken warnings on booting Linux guest.
6
7
7
This open coding leads to undesirable side effects. For example, a VM with
8
For example, the following warning messages are observed when the
8
KVM and -smp 10 will automatically choose GICv3 while the same command
9
Linux guest is booted with the following command lines.
9
line with TCG will stay on GICv2 and fail the launch.
10
10
11
/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
11
This patch combines the TCG and KVM matching code paths by making
12
-accel kvm -machine virt,gic-version=host \
12
everything a 2 pass process. First, we determine which GIC versions the
13
-cpu host \
13
current environment is able to support, then we go through a single
14
-smp 6,sockets=2,cores=3,threads=1 \
14
state machine to determine which target GIC mode that means for us.
15
-m 1024M,slots=16,maxmem=64G \
15
16
-object memory-backend-ram,id=mem0,size=128M \
16
After this patch, the only user noticable changes should be consolidated
17
-object memory-backend-ram,id=mem1,size=128M \
17
error messages as well as TCG -M virt supporting -smp > 8 automatically.
18
-object memory-backend-ram,id=mem2,size=128M \
18
19
-object memory-backend-ram,id=mem3,size=128M \
19
Signed-off-by: Alexander Graf <agraf@csgraf.de>
20
-object memory-backend-ram,id=mem4,size=128M \
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
-object memory-backend-ram,id=mem4,size=384M \
21
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
22
-numa node,nodeid=0,memdev=mem0 \
22
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
23
-numa node,nodeid=1,memdev=mem1 \
23
Message-id: 20221223090107.98888-2-agraf@csgraf.de
24
-numa node,nodeid=2,memdev=mem2 \
25
-numa node,nodeid=3,memdev=mem3 \
26
-numa node,nodeid=4,memdev=mem4 \
27
-numa node,nodeid=5,memdev=mem5
28
:
29
alternatives: patching kernel code
30
BUG: arch topology borken
31
the CLS domain not a subset of the MC domain
32
<the above error log repeats>
33
BUG: arch topology borken
34
the DIE domain not a subset of the NODE domain
35
36
With current implementation of mc->get_default_cpu_node_id(),
37
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
38
That's incorrect because CPU#0/1/2 should be associated with same
39
NUMA node because they're seated in same socket.
40
41
This fixes the issue by considering the socket ID when the default
42
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
43
With this applied, no more CPU topology broken warnings are seen
44
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
45
there are no CPUs associated with NODE#2/3/4/5.
46
47
Signed-off-by: Gavin Shan <gshan@redhat.com>
48
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
49
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
50
Message-id: 20220503140304.855514-6-gshan@redhat.com
51
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
52
---
25
---
53
hw/arm/virt.c | 4 +++-
26
include/hw/arm/virt.h | 15 ++--
54
1 file changed, 3 insertions(+), 1 deletion(-)
27
hw/arm/virt.c | 198 ++++++++++++++++++++++--------------------
55
28
2 files changed, 112 insertions(+), 101 deletions(-)
29
30
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/arm/virt.h
33
+++ b/include/hw/arm/virt.h
34
@@ -XXX,XX +XXX,XX @@ typedef enum VirtMSIControllerType {
35
} VirtMSIControllerType;
36
37
typedef enum VirtGICType {
38
- VIRT_GIC_VERSION_MAX,
39
- VIRT_GIC_VERSION_HOST,
40
- VIRT_GIC_VERSION_2,
41
- VIRT_GIC_VERSION_3,
42
- VIRT_GIC_VERSION_4,
43
+ VIRT_GIC_VERSION_MAX = 0,
44
+ VIRT_GIC_VERSION_HOST = 1,
45
+ /* The concrete GIC values have to match the GIC version number */
46
+ VIRT_GIC_VERSION_2 = 2,
47
+ VIRT_GIC_VERSION_3 = 3,
48
+ VIRT_GIC_VERSION_4 = 4,
49
VIRT_GIC_VERSION_NOSEL,
50
} VirtGICType;
51
52
+#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)
53
+#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)
54
+#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)
55
+
56
struct VirtMachineClass {
57
MachineClass parent;
58
bool disallow_affinity_adjustment;
56
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
59
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
57
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/arm/virt.c
61
--- a/hw/arm/virt.c
59
+++ b/hw/arm/virt.c
62
+++ b/hw/arm/virt.c
60
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
63
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
61
64
}
62
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
65
}
66
67
+static VirtGICType finalize_gic_version_do(const char *accel_name,
68
+ VirtGICType gic_version,
69
+ int gics_supported,
70
+ unsigned int max_cpus)
71
+{
72
+ /* Convert host/max/nosel to GIC version number */
73
+ switch (gic_version) {
74
+ case VIRT_GIC_VERSION_HOST:
75
+ if (!kvm_enabled()) {
76
+ error_report("gic-version=host requires KVM");
77
+ exit(1);
78
+ }
79
+
80
+ /* For KVM, gic-version=host means gic-version=max */
81
+ return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
82
+ gics_supported, max_cpus);
83
+ case VIRT_GIC_VERSION_MAX:
84
+ if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
85
+ gic_version = VIRT_GIC_VERSION_4;
86
+ } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
87
+ gic_version = VIRT_GIC_VERSION_3;
88
+ } else {
89
+ gic_version = VIRT_GIC_VERSION_2;
90
+ }
91
+ break;
92
+ case VIRT_GIC_VERSION_NOSEL:
93
+ if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
94
+ max_cpus <= GIC_NCPU) {
95
+ gic_version = VIRT_GIC_VERSION_2;
96
+ } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
97
+ /*
98
+ * in case the host does not support v2 emulation or
99
+ * the end-user requested more than 8 VCPUs we now default
100
+ * to v3. In any case defaulting to v2 would be broken.
101
+ */
102
+ gic_version = VIRT_GIC_VERSION_3;
103
+ } else if (max_cpus > GIC_NCPU) {
104
+ error_report("%s only supports GICv2 emulation but more than 8 "
105
+ "vcpus are requested", accel_name);
106
+ exit(1);
107
+ }
108
+ break;
109
+ case VIRT_GIC_VERSION_2:
110
+ case VIRT_GIC_VERSION_3:
111
+ case VIRT_GIC_VERSION_4:
112
+ break;
113
+ }
114
+
115
+ /* Check chosen version is effectively supported */
116
+ switch (gic_version) {
117
+ case VIRT_GIC_VERSION_2:
118
+ if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
119
+ error_report("%s does not support GICv2 emulation", accel_name);
120
+ exit(1);
121
+ }
122
+ break;
123
+ case VIRT_GIC_VERSION_3:
124
+ if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
125
+ error_report("%s does not support GICv3 emulation", accel_name);
126
+ exit(1);
127
+ }
128
+ break;
129
+ case VIRT_GIC_VERSION_4:
130
+ if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
131
+ error_report("%s does not support GICv4 emulation, is virtualization=on?",
132
+ accel_name);
133
+ exit(1);
134
+ }
135
+ break;
136
+ default:
137
+ error_report("logic error in finalize_gic_version");
138
+ exit(1);
139
+ break;
140
+ }
141
+
142
+ return gic_version;
143
+}
144
+
145
/*
146
* finalize_gic_version - Determines the final gic_version
147
* according to the gic-version property
148
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
149
*/
150
static void finalize_gic_version(VirtMachineState *vms)
63
{
151
{
64
- return idx % ms->numa_state->num_nodes;
152
+ const char *accel_name = current_accel_name();
65
+ int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
153
unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
66
+
154
+ int gics_supported = 0;
67
+ return socket_id % ms->numa_state->num_nodes;
155
156
- if (kvm_enabled()) {
157
- int probe_bitmap;
158
+ /* Determine which GIC versions the current environment supports */
159
+ if (kvm_enabled() && kvm_irqchip_in_kernel()) {
160
+ int probe_bitmap = kvm_arm_vgic_probe();
161
162
- if (!kvm_irqchip_in_kernel()) {
163
- switch (vms->gic_version) {
164
- case VIRT_GIC_VERSION_HOST:
165
- warn_report(
166
- "gic-version=host not relevant with kernel-irqchip=off "
167
- "as only userspace GICv2 is supported. Using v2 ...");
168
- return;
169
- case VIRT_GIC_VERSION_MAX:
170
- case VIRT_GIC_VERSION_NOSEL:
171
- vms->gic_version = VIRT_GIC_VERSION_2;
172
- return;
173
- case VIRT_GIC_VERSION_2:
174
- return;
175
- case VIRT_GIC_VERSION_3:
176
- error_report(
177
- "gic-version=3 is not supported with kernel-irqchip=off");
178
- exit(1);
179
- case VIRT_GIC_VERSION_4:
180
- error_report(
181
- "gic-version=4 is not supported with kernel-irqchip=off");
182
- exit(1);
183
- }
184
- }
185
-
186
- probe_bitmap = kvm_arm_vgic_probe();
187
if (!probe_bitmap) {
188
error_report("Unable to determine GIC version supported by host");
189
exit(1);
190
}
191
192
- switch (vms->gic_version) {
193
- case VIRT_GIC_VERSION_HOST:
194
- case VIRT_GIC_VERSION_MAX:
195
- if (probe_bitmap & KVM_ARM_VGIC_V3) {
196
- vms->gic_version = VIRT_GIC_VERSION_3;
197
- } else {
198
- vms->gic_version = VIRT_GIC_VERSION_2;
199
- }
200
- return;
201
- case VIRT_GIC_VERSION_NOSEL:
202
- if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
203
- vms->gic_version = VIRT_GIC_VERSION_2;
204
- } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
205
- /*
206
- * in case the host does not support v2 in-kernel emulation or
207
- * the end-user requested more than 8 VCPUs we now default
208
- * to v3. In any case defaulting to v2 would be broken.
209
- */
210
- vms->gic_version = VIRT_GIC_VERSION_3;
211
- } else if (max_cpus > GIC_NCPU) {
212
- error_report("host only supports in-kernel GICv2 emulation "
213
- "but more than 8 vcpus are requested");
214
- exit(1);
215
- }
216
- break;
217
- case VIRT_GIC_VERSION_2:
218
- case VIRT_GIC_VERSION_3:
219
- break;
220
- case VIRT_GIC_VERSION_4:
221
- error_report("gic-version=4 is not supported with KVM");
222
- exit(1);
223
+ if (probe_bitmap & KVM_ARM_VGIC_V2) {
224
+ gics_supported |= VIRT_GIC_VERSION_2_MASK;
225
}
226
-
227
- /* Check chosen version is effectively supported by the host */
228
- if (vms->gic_version == VIRT_GIC_VERSION_2 &&
229
- !(probe_bitmap & KVM_ARM_VGIC_V2)) {
230
- error_report("host does not support in-kernel GICv2 emulation");
231
- exit(1);
232
- } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
233
- !(probe_bitmap & KVM_ARM_VGIC_V3)) {
234
- error_report("host does not support in-kernel GICv3 emulation");
235
- exit(1);
236
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
237
+ gics_supported |= VIRT_GIC_VERSION_3_MASK;
238
}
239
- return;
240
- }
241
-
242
- /* TCG mode */
243
- switch (vms->gic_version) {
244
- case VIRT_GIC_VERSION_NOSEL:
245
- vms->gic_version = VIRT_GIC_VERSION_2;
246
- break;
247
- case VIRT_GIC_VERSION_MAX:
248
+ } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
249
+ /* KVM w/o kernel irqchip can only deal with GICv2 */
250
+ gics_supported |= VIRT_GIC_VERSION_2_MASK;
251
+ accel_name = "KVM with kernel-irqchip=off";
252
+ } else {
253
+ gics_supported |= VIRT_GIC_VERSION_2_MASK;
254
if (module_object_class_by_name("arm-gicv3")) {
255
- /* CONFIG_ARM_GICV3_TCG was set */
256
+ gics_supported |= VIRT_GIC_VERSION_3_MASK;
257
if (vms->virt) {
258
/* GICv4 only makes sense if CPU has EL2 */
259
- vms->gic_version = VIRT_GIC_VERSION_4;
260
- } else {
261
- vms->gic_version = VIRT_GIC_VERSION_3;
262
+ gics_supported |= VIRT_GIC_VERSION_4_MASK;
263
}
264
- } else {
265
- vms->gic_version = VIRT_GIC_VERSION_2;
266
}
267
- break;
268
- case VIRT_GIC_VERSION_HOST:
269
- error_report("gic-version=host requires KVM");
270
- exit(1);
271
- case VIRT_GIC_VERSION_4:
272
- if (!vms->virt) {
273
- error_report("gic-version=4 requires virtualization enabled");
274
- exit(1);
275
- }
276
- break;
277
- case VIRT_GIC_VERSION_2:
278
- case VIRT_GIC_VERSION_3:
279
- break;
280
}
281
+
282
+ /*
283
+ * Then convert helpers like host/max to concrete GIC versions and ensure
284
+ * the desired version is supported
285
+ */
286
+ vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
287
+ gics_supported, max_cpus);
68
}
288
}
69
289
70
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
290
/*
71
--
291
--
72
2.25.1
292
2.34.1
diff view generated by jsdifflib
[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
[PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit
1
From: Gavin Shan <gshan@redhat.com>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
Currently, the SMP configuration isn't considered when the CPU
3
Let's explicitly list out all accelerators that we support when trying to
4
topology is populated. In this case, it's impossible to provide
4
determine the supported set of GIC versions. KVM was already separate, so
5
the default CPU-to-NUMA mapping or association based on the socket
5
the only missing one is HVF which simply reuses all of TCG's emulation
6
ID of the given CPU.
6
code and thus has the same compatibility matrix.
7
7
8
This takes account of SMP configuration when the CPU topology
8
Signed-off-by: Alexander Graf <agraf@csgraf.de>
9
is populated. The die ID for the given CPU isn't assigned since
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
it's not supported on arm/virt machine. Besides, the used SMP
10
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
11
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
11
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
12
to avoid testing failure
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
13
Message-id: 20221223090107.98888-3-agraf@csgraf.de
14
Signed-off-by: Gavin Shan <gshan@redhat.com>
14
[PMM: Added qtest to the list of accelerators]
15
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
16
Acked-by: Igor Mammedov <imammedo@redhat.com>
17
Message-id: 20220503140304.855514-4-gshan@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
16
---
20
hw/arm/virt.c | 15 ++++++++++++++-
17
hw/arm/virt.c | 7 ++++++-
21
1 file changed, 14 insertions(+), 1 deletion(-)
18
1 file changed, 6 insertions(+), 1 deletion(-)
22
19
23
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
24
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/virt.c
22
--- a/hw/arm/virt.c
26
+++ b/hw/arm/virt.c
23
+++ b/hw/arm/virt.c
27
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
24
@@ -XXX,XX +XXX,XX @@
28
int n;
25
#include "sysemu/numa.h"
29
unsigned int max_cpus = ms->smp.max_cpus;
26
#include "sysemu/runstate.h"
30
VirtMachineState *vms = VIRT_MACHINE(ms);
27
#include "sysemu/tpm.h"
31
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
28
+#include "sysemu/tcg.h"
32
29
#include "sysemu/kvm.h"
33
if (ms->possible_cpus) {
30
#include "sysemu/hvf.h"
34
assert(ms->possible_cpus->len == max_cpus);
31
+#include "sysemu/qtest.h"
35
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
32
#include "hw/loader.h"
36
ms->possible_cpus->cpus[n].type = ms->cpu_type;
33
#include "qapi/error.h"
37
ms->possible_cpus->cpus[n].arch_id =
34
#include "qemu/bitops.h"
38
virt_cpu_mp_affinity(vms, n);
35
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
39
+
36
/* KVM w/o kernel irqchip can only deal with GICv2 */
40
+ assert(!mc->smp_props.dies_supported);
37
gics_supported |= VIRT_GIC_VERSION_2_MASK;
41
+ ms->possible_cpus->cpus[n].props.has_socket_id = true;
38
accel_name = "KVM with kernel-irqchip=off";
42
+ ms->possible_cpus->cpus[n].props.socket_id =
39
- } else {
43
+ n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
40
+ } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
44
+ ms->possible_cpus->cpus[n].props.has_cluster_id = true;
41
gics_supported |= VIRT_GIC_VERSION_2_MASK;
45
+ ms->possible_cpus->cpus[n].props.cluster_id =
42
if (module_object_class_by_name("arm-gicv3")) {
46
+ (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
43
gics_supported |= VIRT_GIC_VERSION_3_MASK;
47
+ ms->possible_cpus->cpus[n].props.has_core_id = true;
44
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
48
+ ms->possible_cpus->cpus[n].props.core_id =
45
gics_supported |= VIRT_GIC_VERSION_4_MASK;
49
+ (n / ms->smp.threads) % ms->smp.cores;
46
}
50
ms->possible_cpus->cpus[n].props.has_thread_id = true;
47
}
51
- ms->possible_cpus->cpus[n].props.thread_id = n;
48
+ } else {
52
+ ms->possible_cpus->cpus[n].props.thread_id =
49
+ error_report("Unsupported accelerator, can not determine GIC support");
53
+ n % ms->smp.threads;
50
+ exit(1);
54
}
51
}
55
return ms->possible_cpus;
52
56
}
53
/*
57
--
54
--
58
2.25.1
55
2.34.1
56
57
diff view generated by jsdifflib
[PULL 24/32] target/arm: Define cortex-a76
[PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
Enable the a76 for virt and sbsa board use.
3
Cortex-A76 supports 40bits of address space. sbsa-ref's memory
4
starts above this limit.
4
5
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230126114416.2447685-1-marcin.juszkiewicz@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
docs/system/arm/virt.rst | 1 +
12
hw/arm/sbsa-ref.c | 1 -
11
hw/arm/sbsa-ref.c | 1 +
13
1 file changed, 1 deletion(-)
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
15
14
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/virt.rst
19
+++ b/docs/system/arm/virt.rst
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
21
- ``cortex-a53`` (64-bit)
22
- ``cortex-a57`` (64-bit)
23
- ``cortex-a72`` (64-bit)
24
+- ``cortex-a76`` (64-bit)
25
- ``a64fx`` (64-bit)
26
- ``host`` (with KVM only)
27
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
15
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
29
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/sbsa-ref.c
17
--- a/hw/arm/sbsa-ref.c
31
+++ b/hw/arm/sbsa-ref.c
18
+++ b/hw/arm/sbsa-ref.c
32
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
19
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
33
static const char * const valid_cpus[] = {
20
static const char * const valid_cpus[] = {
34
ARM_CPU_TYPE_NAME("cortex-a57"),
21
ARM_CPU_TYPE_NAME("cortex-a57"),
35
ARM_CPU_TYPE_NAME("cortex-a72"),
22
ARM_CPU_TYPE_NAME("cortex-a72"),
36
+ ARM_CPU_TYPE_NAME("cortex-a76"),
23
- ARM_CPU_TYPE_NAME("cortex-a76"),
24
ARM_CPU_TYPE_NAME("neoverse-n1"),
37
ARM_CPU_TYPE_NAME("max"),
25
ARM_CPU_TYPE_NAME("max"),
38
};
26
};
39
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a53"),
46
ARM_CPU_TYPE_NAME("cortex-a57"),
47
ARM_CPU_TYPE_NAME("cortex-a72"),
48
+ ARM_CPU_TYPE_NAME("cortex-a76"),
49
ARM_CPU_TYPE_NAME("a64fx"),
50
ARM_CPU_TYPE_NAME("host"),
51
ARM_CPU_TYPE_NAME("max"),
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
57
define_cortex_a72_a57_a53_cp_reginfo(cpu);
58
}
59
60
+static void aarch64_a76_initfn(Object *obj)
61
+{
62
+ ARMCPU *cpu = ARM_CPU(obj);
63
+
64
+ cpu->dtb_compatible = "arm,cortex-a76";
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
73
+
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
75
+ cpu->clidr = 0x82000023;
76
+ cpu->ctr = 0x8444C004;
77
+ cpu->dcz_blocksize = 4;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0b1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.18 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
110
+
111
+ /* From B2.93 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
123
+}
124
+
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
126
{
127
/*
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
129
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
130
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
131
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
132
+ { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
133
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
134
{ .name = "max", .initfn = aarch64_max_initfn },
135
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
136
--
27
--
137
2.25.1
28
2.34.1
29
30
diff view generated by jsdifflib
[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
[PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
2
S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
3
them AT S1E1R and AT S1E1W (which are entirely different
4
instructions). Fix the names.
2
5
3
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
6
(This has no guest-visible effect as the names are for debug purposes
4
during arm_cpu_realizefn.
7
only.)
5
8
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Fuad Tabba <tabba@google.com>
12
Message-id: 20230130182459.3309057-2-peter.maydell@linaro.org
13
Message-id: 20230127175507.2895013-2-peter.maydell@linaro.org
10
---
14
---
11
target/arm/cpu.c | 22 +++++++++++++---------
15
target/arm/helper.c | 4 ++--
12
1 file changed, 13 insertions(+), 9 deletions(-)
16
1 file changed, 2 insertions(+), 2 deletions(-)
13
17
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
20
--- a/target/arm/helper.c
17
+++ b/target/arm/cpu.c
21
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
22
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
19
*/
20
unset_feature(env, ARM_FEATURE_EL3);
21
22
- /* Disable the security extension feature bits in the processor feature
23
- * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
24
+ /*
25
+ * Disable the security extension feature bits in the processor
26
+ * feature registers as well.
27
*/
28
- cpu->isar.id_pfr1 &= ~0xf0;
29
- cpu->isar.id_aa64pfr0 &= ~0xf000;
30
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
31
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
32
+ ID_AA64PFR0, EL3, 0);
33
}
34
35
if (!cpu->has_el2) {
36
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
37
}
38
39
if (!arm_feature(env, ARM_FEATURE_EL2)) {
40
- /* Disable the hypervisor feature bits in the processor feature
41
- * registers if we don't have EL2. These are id_pfr1[15:12] and
42
- * id_aa64pfr0_el1[11:8].
43
+ /*
44
+ * Disable the hypervisor feature bits in the processor feature
45
+ * registers if we don't have EL2.
46
*/
47
- cpu->isar.id_aa64pfr0 &= ~0xf00;
48
- cpu->isar.id_pfr1 &= ~0xf000;
49
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
50
+ ID_AA64PFR0, EL2, 0);
51
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
52
+ ID_PFR1, VIRTUALIZATION, 0);
53
}
54
23
55
#ifndef CONFIG_USER_ONLY
24
#ifndef CONFIG_USER_ONLY
25
static const ARMCPRegInfo ats1e1_reginfo[] = {
26
- { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
27
+ { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
28
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
29
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
30
.writefn = ats_write64 },
31
- { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
32
+ { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
33
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
34
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
35
.writefn = ats_write64 },
56
--
36
--
57
2.25.1
37
2.34.1
diff view generated by jsdifflib
[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
[PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The AArch32 ATS12NSO* address translation operations are supposed to
2
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
3
can only happen if EL3 is AArch64). We implement this, but we got
4
the syndrome value wrong: like other traps to EL2 or EL3 on an
5
AArch32 cpreg access, they should report the 0x3 syndrome, not the
6
0x0 'uncategorized' syndrome. This is clear in the access pseudocode
7
for these instructions.
2
8
3
Enable writes to the TERR and TEA bits when RAS is enabled.
9
Fix the syndrome value for these operations by correcting the
4
These bits are otherwise RES0.
10
returned value from the ats_access() function.
5
11
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Fuad Tabba <tabba@google.com>
15
Message-id: 20230130182459.3309057-3-peter.maydell@linaro.org
16
Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org
10
---
17
---
11
target/arm/helper.c | 9 +++++++++
18
target/arm/helper.c | 4 ++--
12
1 file changed, 9 insertions(+)
19
1 file changed, 2 insertions(+), 2 deletions(-)
13
20
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
23
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
24
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
25
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
19
}
26
if (arm_current_el(env) == 1) {
20
valid_mask &= ~SCR_NET;
27
if (arm_is_secure_below_el3(env)) {
21
28
if (env->cp15.scr_el3 & SCR_EEL2) {
22
+ if (cpu_isar_feature(aa64_ras, cpu)) {
29
- return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
23
+ valid_mask |= SCR_TERR;
30
+ return CP_ACCESS_TRAP_EL2;
24
+ }
31
}
25
if (cpu_isar_feature(aa64_lor, cpu)) {
32
- return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
26
valid_mask |= SCR_TLOR;
33
+ return CP_ACCESS_TRAP_EL3;
27
}
34
}
28
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
35
return CP_ACCESS_TRAP_UNCATEGORIZED;
29
}
30
} else {
31
valid_mask &= ~(SCR_RW | SCR_ST);
32
+ if (cpu_isar_feature(aa32_ras, cpu)) {
33
+ valid_mask |= SCR_TERR;
34
+ }
35
}
36
37
if (!arm_feature(env, ARM_FEATURE_EL2)) {
38
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
39
if (cpu_isar_feature(aa64_vh, cpu)) {
40
valid_mask |= HCR_E2H;
41
}
42
+ if (cpu_isar_feature(aa64_ras, cpu)) {
43
+ valid_mask |= HCR_TERR | HCR_TEA;
44
+ }
45
if (cpu_isar_feature(aa64_lor, cpu)) {
46
valid_mask |= HCR_TLOR;
47
}
36
}
48
--
37
--
49
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
[PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
1
From: Richard Henderson <richard.henderson@linaro.org>
1
We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
2
and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
3
the ats_access() function, but doing so was incorrect (a bug fixed in
4
a previous commit). There aren't any cases where we want an access
5
function to be able to request a trap to EL2 or EL3 with a zero
6
syndrome value, so remove these enum values.
2
7
3
This extension concerns branch speculation, which TCG does
8
As well as cleaning up dead code, the motivation here is that
4
not implement. Thus we can trivially enable this feature.
9
we'd like to implement fine-grained-trap handling in
10
helper_access_check_cp_reg(). Although the fine-grained traps
11
to EL2 are always lower priority than trap-to-same-EL and
12
higher priority than trap-to-EL3, they are in the middle of
13
various other kinds of trap-to-EL2. Knowing that a trap-to-EL2
14
must always for us have the same syndrome (ie that an access
15
function will return CP_ACCESS_TRAP_EL2 and there is no other
16
kind of trap-to-EL2 enum value) means we don't have to try
17
to choose which of the two syndrome values to report if the
18
access would trap to EL2 both for the fine-grained-trap and
19
because the access function requires it.
5
20
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Tested-by: Fuad Tabba <tabba@google.com>
24
Message-id: 20230130182459.3309057-4-peter.maydell@linaro.org
25
Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org
10
---
26
---
11
docs/system/arm/emulation.rst | 1 +
27
target/arm/cpregs.h | 4 ++--
12
target/arm/cpu64.c | 1 +
28
target/arm/op_helper.c | 2 ++
13
target/arm/cpu_tcg.c | 1 +
29
2 files changed, 4 insertions(+), 2 deletions(-)
14
3 files changed, 3 insertions(+)
15
30
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
31
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
17
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
33
--- a/target/arm/cpregs.h
19
+++ b/docs/system/arm/emulation.rst
34
+++ b/target/arm/cpregs.h
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
35
@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
21
- FEAT_BBM at level 2 (Translation table break-before-make levels)
36
* Access fails and results in an exception syndrome 0x0 ("uncategorized").
22
- FEAT_BF16 (AArch64 BFloat16 instructions)
37
* Note that this is not a catch-all case -- the set of cases which may
23
- FEAT_BTI (Branch Target Identification)
38
* result in this failure is specifically defined by the architecture.
24
+- FEAT_CSV2 (Cache speculation variant 2)
39
+ * This trap is always to the usual target EL, never directly to a
25
- FEAT_DIT (Data Independent Timing instructions)
40
+ * specified target EL.
26
- FEAT_DPB (DC CVAP instruction)
41
*/
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
42
CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
43
- CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
44
- CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
45
} CPAccessResult;
46
47
typedef struct ARMCPRegInfo ARMCPRegInfo;
48
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
29
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu64.c
50
--- a/target/arm/op_helper.c
31
+++ b/target/arm/cpu64.c
51
+++ b/target/arm/op_helper.c
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
52
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
33
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
53
case CP_ACCESS_TRAP:
34
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
54
break;
35
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
55
case CP_ACCESS_TRAP_UNCATEGORIZED:
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
56
+ /* Only CP_ACCESS_TRAP traps are direct to a specified EL */
37
cpu->isar.id_aa64pfr0 = t;
57
+ assert((res & CP_ACCESS_EL_MASK) == 0);
38
58
if (cpu_isar_feature(aa64_ids, cpu) && isread &&
39
t = cpu->isar.id_aa64pfr1;
59
arm_cpreg_in_idspace(ri)) {
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
60
/*
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu_tcg.c
43
+++ b/target/arm/cpu_tcg.c
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
45
cpu->isar.id_mmfr4 = t;
46
47
t = cpu->isar.id_pfr0;
48
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
49
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
50
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
51
cpu->isar.id_pfr0 = t;
52
--
61
--
53
2.25.1
62
2.34.1
diff view generated by jsdifflib
[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
[PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Rearrange the code in do_coproc_insn() so that we calculate the
2
syndrome value for a potential trap early; we're about to add a
3
second check that wants this value earlier than where it is currently
4
determined.
2
5
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
(Specifically, a trap to EL2 because of HSTR_EL2 should take
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
priority over an UNDEF to EL1, even when the UNDEF is because
5
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
8
the register does not exist at all or because its ri->access
9
bits non-configurably fail the access. So the check we put in
10
for HSTR_EL2 trapping at EL1 (which needs the syndrome) is
11
going to have to be done before the check "is the ARMCPRegInfo
12
pointer NULL".)
13
14
This commit is just code motion; the change to HSTR_EL2
15
handling that will use the 'syndrome' variable is in a
16
subsequent commit.
17
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Tested-by: Fuad Tabba <tabba@google.com>
21
Message-id: 20230130182459.3309057-5-peter.maydell@linaro.org
22
Message-id: 20230127175507.2895013-5-peter.maydell@linaro.org
7
---
23
---
8
docs/system/arm/emulation.rst | 1 +
24
target/arm/translate.c | 83 +++++++++++++++++++++---------------------
9
target/arm/cpu64.c | 1 +
25
1 file changed, 41 insertions(+), 42 deletions(-)
10
target/arm/cpu_tcg.c | 1 +
11
3 files changed, 3 insertions(+)
12
26
13
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
27
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/arm/emulation.rst
29
--- a/target/arm/translate.c
16
+++ b/docs/system/arm/emulation.rst
30
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
31
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
18
- FEAT_PMULL (PMULL, PMULL2 instructions)
32
const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
19
- FEAT_PMUv3p1 (PMU Extensions v3.1)
33
TCGv_ptr tcg_ri = NULL;
20
- FEAT_PMUv3p4 (PMU Extensions v3.4)
34
bool need_exit_tb;
21
+- FEAT_RAS (Reliability, availability, and serviceability)
35
+ uint32_t syndrome;
22
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
36
+
23
- FEAT_RNG (Random number generator)
37
+ /*
24
- FEAT_SB (Speculation Barrier)
38
+ * Note that since we are an implementation which takes an
25
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
39
+ * exception on a trapped conditional instruction only if the
26
index XXXXXXX..XXXXXXX 100644
40
+ * instruction passes its condition code check, we can take
27
--- a/target/arm/cpu64.c
41
+ * advantage of the clause in the ARM ARM that allows us to set
28
+++ b/target/arm/cpu64.c
42
+ * the COND field in the instruction to 0xE in all cases.
29
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
43
+ * We could fish the actual condition out of the insn (ARM)
30
t = cpu->isar.id_aa64pfr0;
44
+ * or the condexec bits (Thumb) but it isn't necessary.
31
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
45
+ */
32
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
46
+ switch (cpnum) {
33
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */
47
+ case 14:
34
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
48
+ if (is64) {
35
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
49
+ syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
36
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
50
+ isread, false);
37
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
51
+ } else {
38
index XXXXXXX..XXXXXXX 100644
52
+ syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
39
--- a/target/arm/cpu_tcg.c
53
+ rt, isread, false);
40
+++ b/target/arm/cpu_tcg.c
54
+ }
41
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
55
+ break;
42
56
+ case 15:
43
t = cpu->isar.id_pfr0;
57
+ if (is64) {
44
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
58
+ syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
45
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
59
+ isread, false);
46
cpu->isar.id_pfr0 = t;
60
+ } else {
47
61
+ syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
48
t = cpu->isar.id_pfr2;
62
+ rt, isread, false);
63
+ }
64
+ break;
65
+ default:
66
+ /*
67
+ * ARMv8 defines that only coprocessors 14 and 15 exist,
68
+ * so this can only happen if this is an ARMv7 or earlier CPU,
69
+ * in which case the syndrome information won't actually be
70
+ * guest visible.
71
+ */
72
+ assert(!arm_dc_feature(s, ARM_FEATURE_V8));
73
+ syndrome = syn_uncategorized();
74
+ break;
75
+ }
76
77
if (!ri) {
78
/*
79
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
80
* Note that on XScale all cp0..c13 registers do an access check
81
* call in order to handle c15_cpar.
82
*/
83
- uint32_t syndrome;
84
-
85
- /*
86
- * Note that since we are an implementation which takes an
87
- * exception on a trapped conditional instruction only if the
88
- * instruction passes its condition code check, we can take
89
- * advantage of the clause in the ARM ARM that allows us to set
90
- * the COND field in the instruction to 0xE in all cases.
91
- * We could fish the actual condition out of the insn (ARM)
92
- * or the condexec bits (Thumb) but it isn't necessary.
93
- */
94
- switch (cpnum) {
95
- case 14:
96
- if (is64) {
97
- syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
98
- isread, false);
99
- } else {
100
- syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
101
- rt, isread, false);
102
- }
103
- break;
104
- case 15:
105
- if (is64) {
106
- syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
107
- isread, false);
108
- } else {
109
- syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
110
- rt, isread, false);
111
- }
112
- break;
113
- default:
114
- /*
115
- * ARMv8 defines that only coprocessors 14 and 15 exist,
116
- * so this can only happen if this is an ARMv7 or earlier CPU,
117
- * in which case the syndrome information won't actually be
118
- * guest visible.
119
- */
120
- assert(!arm_dc_feature(s, ARM_FEATURE_V8));
121
- syndrome = syn_uncategorized();
122
- break;
123
- }
124
-
125
gen_set_condexec(s);
126
gen_update_pc(s, 0);
127
tcg_ri = tcg_temp_new_ptr();
49
--
128
--
50
2.25.1
129
2.34.1
diff view generated by jsdifflib
[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
[PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
1
From: Gavin Shan <gshan@redhat.com>
1
The HSTR_EL2 register has a collection of trap bits which allow
2
trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor
3
registers. The specification of these bits is that when the bit is
4
set we should trap
5
* EL1 accesses
6
* EL0 accesses, if the access is not UNDEFINED when the
7
trap bit is 0
2
8
3
When the PPTT table is built, the CPU topology is re-calculated, but
9
In other words, all UNDEF traps from EL0 to EL1 take precedence over
4
it's unecessary because the CPU topology has been populated in
10
the HSTR_EL2 trap to EL2. (Since this is all AArch32, the only kind
5
virt_possible_cpu_arch_ids() on arm/virt machine.
11
of trap-to-EL1 is the UNDEF.)
6
12
7
This reworks build_pptt() to avoid by reusing the existing IDs in
13
Our implementation doesn't quite get this right -- we check for traps
8
ms->possible_cpus. Currently, the only user of build_pptt() is
14
in the order:
9
arm/virt machine.
15
* no such register
16
* ARMCPRegInfo::access bits
17
* HSTR_EL2 trap bits
18
* ARMCPRegInfo::accessfn
10
19
11
Signed-off-by: Gavin Shan <gshan@redhat.com>
20
So UNDEFs that happen because of the access bits or because the
12
Tested-by: Yanan Wang <wangyanan55@huawei.com>
21
register doesn't exist at all correctly take priority over the
13
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
22
HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the
14
Acked-by: Igor Mammedov <imammedo@redhat.com>
23
accessfn we are incorrectly always taking the HSTR_EL2 trap. There
15
Acked-by: Michael S. Tsirkin <mst@redhat.com>
24
aren't many of these, but one example is the PMCR; if you look at the
16
Message-id: 20220503140304.855514-7-gshan@redhat.com
25
access pseudocode for this register you can see that UNDEFs taken
26
because of the value of PMUSERENR.EN are checked before the HSTR_EL2
27
bit.
28
29
Rearrange helper_access_check_cp_reg() so that we always call the
30
accessfn, and use its return value if it indicates that the access
31
traps to EL0 rather than continuing to do the HSTR_EL2 check.
32
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
35
Tested-by: Fuad Tabba <tabba@google.com>
36
Message-id: 20230130182459.3309057-6-peter.maydell@linaro.org
37
Message-id: 20230127175507.2895013-6-peter.maydell@linaro.org
18
---
38
---
19
hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
39
target/arm/op_helper.c | 21 ++++++++++++++++-----
20
1 file changed, 48 insertions(+), 63 deletions(-)
40
1 file changed, 16 insertions(+), 5 deletions(-)
21
41
22
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
42
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
23
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/acpi/aml-build.c
44
--- a/target/arm/op_helper.c
25
+++ b/hw/acpi/aml-build.c
45
+++ b/target/arm/op_helper.c
26
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
46
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
27
const char *oem_id, const char *oem_table_id)
47
goto fail;
28
{
48
}
29
MachineClass *mc = MACHINE_GET_CLASS(ms);
49
30
- GQueue *list = g_queue_new();
50
+ if (ri->accessfn) {
31
- guint pptt_start = table_data->len;
51
+ res = ri->accessfn(env, ri, isread);
32
- guint parent_offset;
52
+ }
33
- guint length, i;
53
+
34
- int uid = 0;
54
/*
35
- int socket;
55
- * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
36
+ CPUArchIdList *cpus = ms->possible_cpus;
56
- * to sysregs non accessible at EL0 to have UNDEF-ed already.
37
+ int64_t socket_id = -1, cluster_id = -1, core_id = -1;
57
+ * If the access function indicates a trap from EL0 to EL1 then
38
+ uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
58
+ * that always takes priority over the HSTR_EL2 trap. (If it indicates
39
+ uint32_t pptt_start = table_data->len;
59
+ * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicates
40
+ int n;
60
+ * a trap to EL2, then the syndrome is the same either way so we don't
41
AcpiTable table = { .sig = "PPTT", .rev = 2,
61
+ * care whether technically the architecture says that HSTR_EL2 trap or
42
.oem_id = oem_id, .oem_table_id = oem_table_id };
62
+ * the other trap takes priority. So we take the "check HSTR_EL2" path
43
63
+ * for all of those cases.)
44
acpi_table_begin(&table, table_data);
64
*/
45
65
+ if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) &&
46
- for (socket = 0; socket < ms->smp.sockets; socket++) {
66
+ arm_current_el(env) == 0) {
47
- g_queue_push_tail(list,
67
+ goto fail;
48
- GUINT_TO_POINTER(table_data->len - pptt_start));
68
+ }
49
- build_processor_hierarchy_node(
69
+
50
- table_data,
70
if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
51
- /*
71
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
52
- * Physical package - represents the boundary
72
uint32_t mask = 1 << ri->crn;
53
- * of a physical package
73
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
54
- */
55
- (1 << 0),
56
- 0, socket, NULL, 0);
57
- }
58
-
59
- if (mc->smp_props.clusters_supported) {
60
- length = g_queue_get_length(list);
61
- for (i = 0; i < length; i++) {
62
- int cluster;
63
-
64
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
65
- for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
66
- g_queue_push_tail(list,
67
- GUINT_TO_POINTER(table_data->len - pptt_start));
68
- build_processor_hierarchy_node(
69
- table_data,
70
- (0 << 0), /* not a physical package */
71
- parent_offset, cluster, NULL, 0);
72
- }
73
+ /*
74
+ * This works with the assumption that cpus[n].props.*_id has been
75
+ * sorted from top to down levels in mc->possible_cpu_arch_ids().
76
+ * Otherwise, the unexpected and duplicated containers will be
77
+ * created.
78
+ */
79
+ for (n = 0; n < cpus->len; n++) {
80
+ if (cpus->cpus[n].props.socket_id != socket_id) {
81
+ assert(cpus->cpus[n].props.socket_id > socket_id);
82
+ socket_id = cpus->cpus[n].props.socket_id;
83
+ cluster_id = -1;
84
+ core_id = -1;
85
+ socket_offset = table_data->len - pptt_start;
86
+ build_processor_hierarchy_node(table_data,
87
+ (1 << 0), /* Physical package */
88
+ 0, socket_id, NULL, 0);
89
}
90
- }
91
92
- length = g_queue_get_length(list);
93
- for (i = 0; i < length; i++) {
94
- int core;
95
-
96
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
97
- for (core = 0; core < ms->smp.cores; core++) {
98
- if (ms->smp.threads > 1) {
99
- g_queue_push_tail(list,
100
- GUINT_TO_POINTER(table_data->len - pptt_start));
101
- build_processor_hierarchy_node(
102
- table_data,
103
- (0 << 0), /* not a physical package */
104
- parent_offset, core, NULL, 0);
105
- } else {
106
- build_processor_hierarchy_node(
107
- table_data,
108
- (1 << 1) | /* ACPI Processor ID valid */
109
- (1 << 3), /* Node is a Leaf */
110
- parent_offset, uid++, NULL, 0);
111
+ if (mc->smp_props.clusters_supported) {
112
+ if (cpus->cpus[n].props.cluster_id != cluster_id) {
113
+ assert(cpus->cpus[n].props.cluster_id > cluster_id);
114
+ cluster_id = cpus->cpus[n].props.cluster_id;
115
+ core_id = -1;
116
+ cluster_offset = table_data->len - pptt_start;
117
+ build_processor_hierarchy_node(table_data,
118
+ (0 << 0), /* Not a physical package */
119
+ socket_offset, cluster_id, NULL, 0);
120
}
121
+ } else {
122
+ cluster_offset = socket_offset;
123
}
124
- }
125
126
- length = g_queue_get_length(list);
127
- for (i = 0; i < length; i++) {
128
- int thread;
129
+ if (ms->smp.threads == 1) {
130
+ build_processor_hierarchy_node(table_data,
131
+ (1 << 1) | /* ACPI Processor ID valid */
132
+ (1 << 3), /* Node is a Leaf */
133
+ cluster_offset, n, NULL, 0);
134
+ } else {
135
+ if (cpus->cpus[n].props.core_id != core_id) {
136
+ assert(cpus->cpus[n].props.core_id > core_id);
137
+ core_id = cpus->cpus[n].props.core_id;
138
+ core_offset = table_data->len - pptt_start;
139
+ build_processor_hierarchy_node(table_data,
140
+ (0 << 0), /* Not a physical package */
141
+ cluster_offset, core_id, NULL, 0);
142
+ }
143
144
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
145
- for (thread = 0; thread < ms->smp.threads; thread++) {
146
- build_processor_hierarchy_node(
147
- table_data,
148
+ build_processor_hierarchy_node(table_data,
149
(1 << 1) | /* ACPI Processor ID valid */
150
(1 << 2) | /* Processor is a Thread */
151
(1 << 3), /* Node is a Leaf */
152
- parent_offset, uid++, NULL, 0);
153
+ core_offset, n, NULL, 0);
154
}
74
}
155
}
75
}
156
76
157
- g_queue_free(list);
77
- if (ri->accessfn) {
158
acpi_table_end(linker, &table);
78
- res = ri->accessfn(env, ri, isread);
159
}
79
- }
160
80
if (likely(res == CP_ACCESS_OK)) {
81
return ri;
82
}
161
--
83
--
162
2.25.1
84
2.34.1
diff view generated by jsdifflib
[PULL 17/32] target/arm: Implement ESB instruction
[PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The semantics of HSTR_EL2 require that it traps cpreg accesses
2
to EL2 for:
3
* EL1 accesses
4
* EL0 accesses, if the access is not UNDEFINED when the
5
trap bit is 0
2
6
3
Check for and defer any pending virtual SError.
7
(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
8
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
9
HSTR_EL2 traps from EL0 are priority 15.)
4
10
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
However, we don't get this right for EL1 accesses which UNDEF because
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
the register doesn't exist at all or because its ri->access bits
7
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
13
non-configurably forbid the access. At EL1, check for the HSTR_EL2
14
trap early, before either of these UNDEF reasons.
15
16
We have to retain the HSTR_EL2 check in access_check_cp_reg(),
17
because at EL0 any kind of UNDEF-to-EL1 (including "no such
18
register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'")
19
takes precedence over the trap to EL2. But we only need to do that
20
check for EL0 now.
21
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Tested-by: Fuad Tabba <tabba@google.com>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org
26
Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org
9
---
27
---
10
target/arm/helper.h | 1 +
28
target/arm/op_helper.c | 6 +++++-
11
target/arm/a32.decode | 16 ++++++++------
29
target/arm/translate.c | 28 +++++++++++++++++++++++++++-
12
target/arm/t32.decode | 18 ++++++++--------
30
2 files changed, 32 insertions(+), 2 deletions(-)
13
target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-a64.c | 17 +++++++++++++++
15
target/arm/translate.c | 23 ++++++++++++++++++++
16
6 files changed, 103 insertions(+), 15 deletions(-)
17
31
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
21
+++ b/target/arm/helper.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
23
DEF_HELPER_1(yield, void, env)
24
DEF_HELPER_1(pre_hvc, void, env)
25
DEF_HELPER_2(pre_smc, void, env, i32)
26
+DEF_HELPER_1(vesb, void, env)
27
28
DEF_HELPER_3(cpsr_write, void, env, i32, i32)
29
DEF_HELPER_2(cpsr_write_eret, void, env, i32)
30
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/a32.decode
33
+++ b/target/arm/a32.decode
34
@@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
35
36
{
37
{
38
- YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
39
- WFE ---- 0011 0010 0000 1111 ---- 0000 0010
40
- WFI ---- 0011 0010 0000 1111 ---- 0000 0011
41
+ [
42
+ YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
43
+ WFE ---- 0011 0010 0000 1111 ---- 0000 0010
44
+ WFI ---- 0011 0010 0000 1111 ---- 0000 0011
45
46
- # TODO: Implement SEV, SEVL; may help SMP performance.
47
- # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
48
- # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
49
+ # TODO: Implement SEV, SEVL; may help SMP performance.
50
+ # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
51
+ # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
52
+
53
+ ESB ---- 0011 0010 0000 1111 ---- 0001 0000
54
+ ]
55
56
# The canonical nop ends in 00000000, but the whole of the
57
# rest of the space executes as nop if otherwise unsupported.
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
63
[
64
# Hints, and CPS
65
{
66
- YIELD 1111 0011 1010 1111 1000 0000 0000 0001
67
- WFE 1111 0011 1010 1111 1000 0000 0000 0010
68
- WFI 1111 0011 1010 1111 1000 0000 0000 0011
69
+ [
70
+ YIELD 1111 0011 1010 1111 1000 0000 0000 0001
71
+ WFE 1111 0011 1010 1111 1000 0000 0000 0010
72
+ WFI 1111 0011 1010 1111 1000 0000 0000 0011
73
74
- # TODO: Implement SEV, SEVL; may help SMP performance.
75
- # SEV 1111 0011 1010 1111 1000 0000 0000 0100
76
- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
77
+ # TODO: Implement SEV, SEVL; may help SMP performance.
78
+ # SEV 1111 0011 1010 1111 1000 0000 0000 0100
79
+ # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
80
81
- # For M-profile minimal-RAS ESB can be a NOP, which is the
82
- # default behaviour since it is in the hint space.
83
- # ESB 1111 0011 1010 1111 1000 0000 0001 0000
84
+ ESB 1111 0011 1010 1111 1000 0000 0001 0000
85
+ ]
86
87
# The canonical nop ends in 0000 0000, but the whole rest
88
# of the space is "reserved hint, behaves as nop".
89
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
32
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
90
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/op_helper.c
34
--- a/target/arm/op_helper.c
92
+++ b/target/arm/op_helper.c
35
+++ b/target/arm/op_helper.c
93
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
36
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
94
access_type, mmu_idx, ra);
37
goto fail;
95
}
38
}
96
}
39
97
+
40
- if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
98
+/*
99
+ * This function corresponds to AArch64.vESBOperation().
100
+ * Note that the AArch32 version is not functionally different.
101
+ */
102
+void HELPER(vesb)(CPUARMState *env)
103
+{
104
+ /*
41
+ /*
105
+ * The EL2Enabled() check is done inside arm_hcr_el2_eff,
42
+ * HSTR_EL2 traps from EL1 are checked earlier, in generated code;
106
+ * and will return HCR_EL2.VSE == 0, so nothing happens.
43
+ * we only need to check here for traps from EL0.
107
+ */
44
+ */
108
+ uint64_t hcr = arm_hcr_el2_eff(env);
45
+ if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
109
+ bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
46
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
110
+ bool pending = enabled && (hcr & HCR_VSE);
47
uint32_t mask = 1 << ri->crn;
111
+ bool masked = (env->daif & PSTATE_A);
48
112
+
113
+ /* If VSE pending and masked, defer the exception. */
114
+ if (pending && masked) {
115
+ uint32_t syndrome;
116
+
117
+ if (arm_el_is_aa64(env, 1)) {
118
+ /* Copy across IDS and ISS from VSESR. */
119
+ syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
120
+ } else {
121
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
122
+
123
+ if (extended_addresses_enabled(env)) {
124
+ syndrome = arm_fi_to_lfsc(&fi);
125
+ } else {
126
+ syndrome = arm_fi_to_sfsc(&fi);
127
+ }
128
+ /* Copy across AET and ExT from VSESR. */
129
+ syndrome |= env->cp15.vsesr_el2 & 0xd000;
130
+ }
131
+
132
+ /* Set VDISR_EL2.A along with the syndrome. */
133
+ env->cp15.vdisr_el2 = syndrome | (1u << 31);
134
+
135
+ /* Clear pending virtual SError */
136
+ env->cp15.hcr_el2 &= ~HCR_VSE;
137
+ cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
138
+ }
139
+}
140
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
141
index XXXXXXX..XXXXXXX 100644
142
--- a/target/arm/translate-a64.c
143
+++ b/target/arm/translate-a64.c
144
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
145
gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
146
}
147
break;
148
+ case 0b10000: /* ESB */
149
+ /* Without RAS, we must implement this as NOP. */
150
+ if (dc_isar_feature(aa64_ras, s)) {
151
+ /*
152
+ * QEMU does not have a source of physical SErrors,
153
+ * so we are only concerned with virtual SErrors.
154
+ * The pseudocode in the ARM for this case is
155
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
156
+ * AArch64.vESBOperation();
157
+ * Most of the condition can be evaluated at translation time.
158
+ * Test for EL2 present, and defer test for SEL2 to runtime.
159
+ */
160
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
161
+ gen_helper_vesb(cpu_env);
162
+ }
163
+ }
164
+ break;
165
case 0b11000: /* PACIAZ */
166
if (s->pauth_active) {
167
gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
168
diff --git a/target/arm/translate.c b/target/arm/translate.c
49
diff --git a/target/arm/translate.c b/target/arm/translate.c
169
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
170
--- a/target/arm/translate.c
51
--- a/target/arm/translate.c
171
+++ b/target/arm/translate.c
52
+++ b/target/arm/translate.c
172
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
53
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
173
return true;
54
break;
174
}
55
}
175
56
176
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
57
+ if (s->hstr_active && cpnum == 15 && s->current_el == 1) {
177
+{
178
+ /*
179
+ * For M-profile, minimal-RAS ESB can be a NOP.
180
+ * Without RAS, we must implement this as NOP.
181
+ */
182
+ if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
183
+ /*
58
+ /*
184
+ * QEMU does not have a source of physical SErrors,
59
+ * At EL1, check for a HSTR_EL2 trap, which must take precedence
185
+ * so we are only concerned with virtual SErrors.
60
+ * over the UNDEF for "no such register" or the UNDEF for "access
186
+ * The pseudocode in the ARM for this case is
61
+ * permissions forbid this EL1 access". HSTR_EL2 traps from EL0
187
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
62
+ * only happen if the cpreg doesn't UNDEF at EL0, so we do those in
188
+ * AArch32.vESBOperation();
63
+ * access_check_cp_reg(), after the checks for whether the access
189
+ * Most of the condition can be evaluated at translation time.
64
+ * configurably trapped to EL1.
190
+ * Test for EL2 present, and defer test for SEL2 to runtime.
191
+ */
65
+ */
192
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
66
+ uint32_t maskbit = is64 ? crm : crn;
193
+ gen_helper_vesb(cpu_env);
67
+
68
+ if (maskbit != 4 && maskbit != 14) {
69
+ /* T4 and T14 are RES0 so never cause traps */
70
+ TCGv_i32 t;
71
+ DisasLabel over = gen_disas_label(s);
72
+
73
+ t = load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2));
74
+ tcg_gen_andi_i32(t, t, 1u << maskbit);
75
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
76
+ tcg_temp_free_i32(t);
77
+
78
+ gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
79
+ set_disas_label(s, over);
194
+ }
80
+ }
195
+ }
81
+ }
196
+ return true;
197
+}
198
+
82
+
199
static bool trans_NOP(DisasContext *s, arg_NOP *a)
83
if (!ri) {
200
{
84
/*
201
return true;
85
* Unknown register; this might be a guest error or a QEMU
86
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
87
return;
88
}
89
90
- if (s->hstr_active || ri->accessfn ||
91
+ if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
92
(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
93
/*
94
* Emit code to perform further access permissions checks at
202
--
95
--
203
2.25.1
96
2.34.1
diff view generated by jsdifflib
[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
[PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
2
enabled in the current security state. We weren't checking for this,
3
which meant that if the guest set up the HSTR_EL2 register we would
4
incorrectly trap even for accesses from Secure EL0 and EL1.
2
5
3
This register is present for either VHE or Debugv8p2.
6
Add the missing checks. (Other places where we look at HSTR_EL2
7
for the not-in-v8A bits TTEE and TJDBX are already checking that
8
we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)
4
9
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Tested-by: Fuad Tabba <tabba@google.com>
13
Message-id: 20230130182459.3309057-8-peter.maydell@linaro.org
14
Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org
9
---
15
---
10
target/arm/helper.c | 15 +++++++++++----
16
target/arm/helper.c | 2 +-
11
1 file changed, 11 insertions(+), 4 deletions(-)
17
target/arm/op_helper.c | 1 +
18
2 files changed, 2 insertions(+), 1 deletion(-)
12
19
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
22
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
23
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
24
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
18
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
25
DP_TBFLAG_A32(flags, VFPEN, 1);
19
};
20
21
+static const ARMCPRegInfo contextidr_el2 = {
22
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
23
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
24
+ .access = PL2_RW,
25
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
26
+};
27
+
28
static const ARMCPRegInfo vhe_reginfo[] = {
29
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
30
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
31
- .access = PL2_RW,
32
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
33
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
34
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
35
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
36
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
37
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
38
}
26
}
39
27
40
+ if (cpu_isar_feature(aa64_vh, cpu) ||
28
- if (el < 2 && env->cp15.hstr_el2 &&
41
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
29
+ if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
42
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
30
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
43
+ }
31
DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
44
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
45
define_arm_cp_regs(cpu, vhe_reginfo);
46
}
32
}
33
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/op_helper.c
36
+++ b/target/arm/op_helper.c
37
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
38
* we only need to check here for traps from EL0.
39
*/
40
if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
41
+ arm_is_el2_enabled(env) &&
42
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
43
uint32_t mask = 1 << ri->crn;
44
47
--
45
--
48
2.25.1
46
2.34.1
diff view generated by jsdifflib
[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
[PULL 18/33] target/arm: Define the FEAT_FGT registers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Define the system registers which are provided by the
2
2
FEAT_FGT fine-grained trap architectural feature:
3
There is no branch prediction in TCG, therefore there is no
3
HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2
4
need to actually include the context number into the predictor.
4
5
Therefore all we need to do is add the state for SCXTNUM_ELx.
5
All these registers are a set of bit fields, where each bit is set
6
6
for a trap and clear to not trap on a particular system register
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
access. The R and W register pairs are for system registers,
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
allowing trapping to be done separately for reads and writes; the I
9
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
9
register is for system instructions where trapping is on instruction
10
execution.
11
12
The data storage in the CPU state struct is arranged as a set of
13
arrays rather than separate fields so that when we're looking up the
14
bits for a system register access we can just index into the array
15
rather than having to use a switch to select a named struct member.
16
The later FEAT_FGT2 will add extra elements to these arrays.
17
18
The field definitions for the new registers are in cpregs.h because
19
in practice the code that needs them is code that also needs
20
the cpregs information; cpu.h is included in a lot more files.
21
We're also going to add some FGT-specific definitions to cpregs.h
22
in the next commit.
23
24
We do not implement HAFGRTR_EL2, because we don't implement
25
FEAT_AMUv1.
26
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
29
Tested-by: Fuad Tabba <tabba@google.com>
30
Message-id: 20230130182459.3309057-9-peter.maydell@linaro.org
31
Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org
11
---
32
---
12
docs/system/arm/emulation.rst | 3 ++
33
target/arm/cpregs.h | 285 ++++++++++++++++++++++++++++++++++++++++++++
13
target/arm/cpu.h | 16 +++++++++
34
target/arm/cpu.h | 15 +++
14
target/arm/cpu.c | 5 +++
35
target/arm/helper.c | 40 +++++++
15
target/arm/cpu64.c | 3 +-
36
3 files changed, 340 insertions(+)
16
target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++-
37
17
5 files changed, 86 insertions(+), 2 deletions(-)
38
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
18
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
40
--- a/target/arm/cpregs.h
22
+++ b/docs/system/arm/emulation.rst
41
+++ b/target/arm/cpregs.h
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
42
@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
24
- FEAT_BF16 (AArch64 BFloat16 instructions)
43
CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
25
- FEAT_BTI (Branch Target Identification)
44
} CPAccessResult;
26
- FEAT_CSV2 (Cache speculation variant 2)
45
27
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
46
+/* Indexes into fgt_read[] */
28
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
47
+#define FGTREG_HFGRTR 0
29
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
48
+#define FGTREG_HDFGRTR 1
30
- FEAT_DIT (Data Independent Timing instructions)
49
+/* Indexes into fgt_write[] */
31
- FEAT_DPB (DC CVAP instruction)
50
+#define FGTREG_HFGWTR 0
32
- FEAT_Debugv8p2 (Debug changes for v8.2)
51
+#define FGTREG_HDFGWTR 1
52
+/* Indexes into fgt_exec[] */
53
+#define FGTREG_HFGITR 0
54
+
55
+FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
56
+FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1)
57
+FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1)
58
+FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1)
59
+FIELD(HFGRTR_EL2, APDAKEY, 4, 1)
60
+FIELD(HFGRTR_EL2, APDBKEY, 5, 1)
61
+FIELD(HFGRTR_EL2, APGAKEY, 6, 1)
62
+FIELD(HFGRTR_EL2, APIAKEY, 7, 1)
63
+FIELD(HFGRTR_EL2, APIBKEY, 8, 1)
64
+FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1)
65
+FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1)
66
+FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1)
67
+FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1)
68
+FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1)
69
+FIELD(HFGRTR_EL2, CTR_EL0, 14, 1)
70
+FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1)
71
+FIELD(HFGRTR_EL2, ESR_EL1, 16, 1)
72
+FIELD(HFGRTR_EL2, FAR_EL1, 17, 1)
73
+FIELD(HFGRTR_EL2, ISR_EL1, 18, 1)
74
+FIELD(HFGRTR_EL2, LORC_EL1, 19, 1)
75
+FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1)
76
+FIELD(HFGRTR_EL2, LORID_EL1, 21, 1)
77
+FIELD(HFGRTR_EL2, LORN_EL1, 22, 1)
78
+FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1)
79
+FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1)
80
+FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1)
81
+FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1)
82
+FIELD(HFGRTR_EL2, PAR_EL1, 27, 1)
83
+FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1)
84
+FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1)
85
+FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1)
86
+FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1)
87
+FIELD(HFGRTR_EL2, TCR_EL1, 32, 1)
88
+FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1)
89
+FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1)
90
+FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1)
91
+FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1)
92
+FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1)
93
+FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1)
94
+FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1)
95
+FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1)
96
+FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1)
97
+FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1)
98
+FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1)
99
+FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1)
100
+FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1)
101
+FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1)
102
+FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1)
103
+FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1)
104
+FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1)
105
+FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1)
106
+/* 51-53: RES0 */
107
+FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1)
108
+FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1)
109
+/* 56-63: RES0 */
110
+
111
+/* These match HFGRTR but bits for RO registers are RES0 */
112
+FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1)
113
+FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1)
114
+FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1)
115
+FIELD(HFGWTR_EL2, APDAKEY, 4, 1)
116
+FIELD(HFGWTR_EL2, APDBKEY, 5, 1)
117
+FIELD(HFGWTR_EL2, APGAKEY, 6, 1)
118
+FIELD(HFGWTR_EL2, APIAKEY, 7, 1)
119
+FIELD(HFGWTR_EL2, APIBKEY, 8, 1)
120
+FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1)
121
+FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1)
122
+FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1)
123
+FIELD(HFGWTR_EL2, ESR_EL1, 16, 1)
124
+FIELD(HFGWTR_EL2, FAR_EL1, 17, 1)
125
+FIELD(HFGWTR_EL2, LORC_EL1, 19, 1)
126
+FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1)
127
+FIELD(HFGWTR_EL2, LORN_EL1, 22, 1)
128
+FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1)
129
+FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1)
130
+FIELD(HFGWTR_EL2, PAR_EL1, 27, 1)
131
+FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1)
132
+FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1)
133
+FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1)
134
+FIELD(HFGWTR_EL2, TCR_EL1, 32, 1)
135
+FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1)
136
+FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1)
137
+FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1)
138
+FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1)
139
+FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1)
140
+FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1)
141
+FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1)
142
+FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1)
143
+FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1)
144
+FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1)
145
+FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1)
146
+FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1)
147
+FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1)
148
+FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1)
149
+FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1)
150
+FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1)
151
+FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1)
152
+
153
+FIELD(HFGITR_EL2, ICIALLUIS, 0, 1)
154
+FIELD(HFGITR_EL2, ICIALLU, 1, 1)
155
+FIELD(HFGITR_EL2, ICIVAU, 2, 1)
156
+FIELD(HFGITR_EL2, DCIVAC, 3, 1)
157
+FIELD(HFGITR_EL2, DCISW, 4, 1)
158
+FIELD(HFGITR_EL2, DCCSW, 5, 1)
159
+FIELD(HFGITR_EL2, DCCISW, 6, 1)
160
+FIELD(HFGITR_EL2, DCCVAU, 7, 1)
161
+FIELD(HFGITR_EL2, DCCVAP, 8, 1)
162
+FIELD(HFGITR_EL2, DCCVADP, 9, 1)
163
+FIELD(HFGITR_EL2, DCCIVAC, 10, 1)
164
+FIELD(HFGITR_EL2, DCZVA, 11, 1)
165
+FIELD(HFGITR_EL2, ATS1E1R, 12, 1)
166
+FIELD(HFGITR_EL2, ATS1E1W, 13, 1)
167
+FIELD(HFGITR_EL2, ATS1E0R, 14, 1)
168
+FIELD(HFGITR_EL2, ATS1E0W, 15, 1)
169
+FIELD(HFGITR_EL2, ATS1E1RP, 16, 1)
170
+FIELD(HFGITR_EL2, ATS1E1WP, 17, 1)
171
+FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1)
172
+FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1)
173
+FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1)
174
+FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1)
175
+FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1)
176
+FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1)
177
+FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1)
178
+FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1)
179
+FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1)
180
+FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1)
181
+FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1)
182
+FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1)
183
+FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1)
184
+FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1)
185
+FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1)
186
+FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1)
187
+FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1)
188
+FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1)
189
+FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1)
190
+FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1)
191
+FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1)
192
+FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1)
193
+FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1)
194
+FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1)
195
+FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1)
196
+FIELD(HFGITR_EL2, TLBIVAE1, 43, 1)
197
+FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1)
198
+FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1)
199
+FIELD(HFGITR_EL2, TLBIVALE1, 46, 1)
200
+FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1)
201
+FIELD(HFGITR_EL2, CFPRCTX, 48, 1)
202
+FIELD(HFGITR_EL2, DVPRCTX, 49, 1)
203
+FIELD(HFGITR_EL2, CPPRCTX, 50, 1)
204
+FIELD(HFGITR_EL2, ERET, 51, 1)
205
+FIELD(HFGITR_EL2, SVC_EL0, 52, 1)
206
+FIELD(HFGITR_EL2, SVC_EL1, 53, 1)
207
+FIELD(HFGITR_EL2, DCCVAC, 54, 1)
208
+FIELD(HFGITR_EL2, NBRBINJ, 55, 1)
209
+FIELD(HFGITR_EL2, NBRBIALL, 56, 1)
210
+
211
+FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1)
212
+FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1)
213
+FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1)
214
+FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1)
215
+FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1)
216
+FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1)
217
+FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1)
218
+FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1)
219
+/* 8: RES0: OSLAR_EL1 is WO */
220
+FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1)
221
+FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1)
222
+FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1)
223
+FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1)
224
+FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1)
225
+FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1)
226
+FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1)
227
+FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1)
228
+FIELD(HDFGRTR_EL2, PMINTEN, 17, 1)
229
+FIELD(HDFGRTR_EL2, PMOVS, 18, 1)
230
+FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1)
231
+/* 20: RES0: PMSWINC_EL0 is WO */
232
+/* 21: RES0: PMCR_EL0 is WO */
233
+FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1)
234
+FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1)
235
+FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1)
236
+FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1)
237
+FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1)
238
+FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1)
239
+FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1)
240
+FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1)
241
+FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1)
242
+FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1)
243
+FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1)
244
+FIELD(HDFGRTR_EL2, TRC, 33, 1)
245
+FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1)
246
+FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1)
247
+FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1)
248
+FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1)
249
+/* 38, 39: RES0 */
250
+FIELD(HDFGRTR_EL2, TRCID, 40, 1)
251
+FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1)
252
+/* 42: RES0: TRCOSLAR is WO */
253
+FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1)
254
+FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1)
255
+FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1)
256
+FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1)
257
+FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1)
258
+FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1)
259
+/* 49: RES0: TRFCR_EL1 is WO */
260
+FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1)
261
+FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1)
262
+FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1)
263
+FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1)
264
+FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1)
265
+FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1)
266
+FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1)
267
+FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1)
268
+FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1)
269
+FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1)
270
+FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1)
271
+FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1)
272
+FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1)
273
+FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1)
274
+
275
+/*
276
+ * These match HDFGRTR_EL2, but bits for RO registers are RES0.
277
+ * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0.
278
+ */
279
+FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1)
280
+FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1)
281
+FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1)
282
+FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1)
283
+FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1)
284
+FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1)
285
+FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1)
286
+FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1)
287
+FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1)
288
+FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1)
289
+FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1)
290
+FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1)
291
+FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1)
292
+FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1)
293
+FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1)
294
+FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1)
295
+FIELD(HDFGWTR_EL2, PMINTEN, 17, 1)
296
+FIELD(HDFGWTR_EL2, PMOVS, 18, 1)
297
+FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1)
298
+FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1)
299
+FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1)
300
+FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1)
301
+FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1)
302
+FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1)
303
+FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1)
304
+FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1)
305
+FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1)
306
+FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1)
307
+FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1)
308
+FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1)
309
+FIELD(HDFGWTR_EL2, TRC, 33, 1)
310
+FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1)
311
+FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1)
312
+FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1)
313
+FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1)
314
+FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1)
315
+FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1)
316
+FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1)
317
+FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1)
318
+FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1)
319
+FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1)
320
+FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1)
321
+FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1)
322
+FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1)
323
+FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1)
324
+FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1)
325
+FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1)
326
+FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1)
327
+FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
328
+FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
329
+FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
330
+
331
typedef struct ARMCPRegInfo ARMCPRegInfo;
332
333
/*
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
334
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
index XXXXXXX..XXXXXXX 100644
335
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
336
--- a/target/arm/cpu.h
36
+++ b/target/arm/cpu.h
337
+++ b/target/arm/cpu.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
338
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
38
ARMPACKey apdb;
339
uint64_t disr_el1;
39
ARMPACKey apga;
340
uint64_t vdisr_el2;
40
} keys;
341
uint64_t vsesr_el2;
41
+
342
+
42
+ uint64_t scxtnum_el[4];
343
+ /*
43
#endif
344
+ * Fine-Grained Trap registers. We store these as arrays so the
44
345
+ * access checking code doesn't have to manually select
45
#if defined(CONFIG_USER_ONLY)
346
+ * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
46
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
347
+ * FEAT_FGT2 will add more elements to these arrays.
47
#define SCTLR_WXN (1U << 19)
348
+ */
48
#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
349
+ uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
49
#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
350
+ uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
50
+#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
351
+ uint64_t fgt_exec[1]; /* HFGITR */
51
#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
352
} cp15;
52
#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
353
53
#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
354
struct {
54
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
355
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
55
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
356
return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
56
}
357
}
57
358
58
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
359
+static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
59
+{
360
+{
60
+ int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
361
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
61
+ if (key >= 2) {
62
+ return true; /* FEAT_CSV2_2 */
63
+ }
64
+ if (key == 1) {
65
+ key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
66
+ return key >= 2; /* FEAT_CSV2_1p2 */
67
+ }
68
+ return false;
69
+}
362
+}
70
+
363
+
71
static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
364
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
72
{
365
{
73
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
366
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
74
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/cpu.c
77
+++ b/target/arm/cpu.c
78
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
79
*/
80
env->cp15.gcr_el1 = 0x1ffff;
81
}
82
+ /*
83
+ * Disable access to SCXTNUM_EL0 from CSV2_1p2.
84
+ * This is not yet exposed from the Linux kernel in any way.
85
+ */
86
+ env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
87
#else
88
/* Reset into the highest available EL */
89
if (arm_feature(env, ARM_FEATURE_EL3)) {
90
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/cpu64.c
93
+++ b/target/arm/cpu64.c
94
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
95
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
96
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
97
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
98
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
99
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
100
cpu->isar.id_aa64pfr0 = t;
101
102
t = cpu->isar.id_aa64pfr1;
103
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
104
* we do for EL2 with the virtualization=on property.
105
*/
106
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
107
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
108
cpu->isar.id_aa64pfr1 = t;
109
110
t = cpu->isar.id_aa64mmfr0;
111
diff --git a/target/arm/helper.c b/target/arm/helper.c
367
diff --git a/target/arm/helper.c b/target/arm/helper.c
112
index XXXXXXX..XXXXXXX 100644
368
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/helper.c
369
--- a/target/arm/helper.c
114
+++ b/target/arm/helper.c
370
+++ b/target/arm/helper.c
115
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
371
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
116
if (cpu_isar_feature(aa64_mte, cpu)) {
372
if (cpu_isar_feature(aa64_hcx, cpu)) {
117
valid_mask |= SCR_ATA;
373
valid_mask |= SCR_HXEN;
118
}
374
}
119
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
375
+ if (cpu_isar_feature(aa64_fgt, cpu)) {
120
+ valid_mask |= SCR_ENSCXT;
376
+ valid_mask |= SCR_FGTEN;
121
+ }
377
+ }
122
} else {
378
} else {
123
valid_mask &= ~(SCR_RW | SCR_ST);
379
valid_mask &= ~(SCR_RW | SCR_ST);
124
if (cpu_isar_feature(aa32_ras, cpu)) {
380
if (cpu_isar_feature(aa32_ras, cpu)) {
125
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
381
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
126
if (cpu_isar_feature(aa64_mte, cpu)) {
382
.access = PL3_RW,
127
valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
383
.fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
128
}
129
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
130
+ valid_mask |= HCR_ENSCXT;
131
+ }
132
}
133
134
/* Clear RES0 bits. */
135
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
136
{ K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
137
"TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
138
139
+ { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
140
+ "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
141
+ isar_feature_aa64_scxtnum },
142
+
143
/* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
144
/* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
145
};
146
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
147
},
148
};
384
};
149
385
+
150
-#endif
386
+static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri,
151
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
387
+ bool isread)
152
+ bool isread)
153
+{
388
+{
154
+ uint64_t hcr = arm_hcr_el2_eff(env);
389
+ if (arm_current_el(env) == 2 &&
155
+ int el = arm_current_el(env);
390
+ arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) {
156
+
157
+ if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
158
+ if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
159
+ if (hcr & HCR_TGE) {
160
+ return CP_ACCESS_TRAP_EL2;
161
+ }
162
+ return CP_ACCESS_TRAP;
163
+ }
164
+ } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
165
+ return CP_ACCESS_TRAP_EL2;
166
+ }
167
+ if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
168
+ return CP_ACCESS_TRAP_EL2;
169
+ }
170
+ if (el < 3
171
+ && arm_feature(env, ARM_FEATURE_EL3)
172
+ && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
173
+ return CP_ACCESS_TRAP_EL3;
391
+ return CP_ACCESS_TRAP_EL3;
174
+ }
392
+ }
175
+ return CP_ACCESS_OK;
393
+ return CP_ACCESS_OK;
176
+}
394
+}
177
+
395
+
178
+static const ARMCPRegInfo scxtnum_reginfo[] = {
396
+static const ARMCPRegInfo fgt_reginfo[] = {
179
+ { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
397
+ { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64,
180
+ .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
398
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
181
+ .access = PL0_RW, .accessfn = access_scxtnum,
399
+ .access = PL2_RW, .accessfn = access_fgt,
182
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
400
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) },
183
+ { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
401
+ { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64,
184
+ .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
402
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5,
185
+ .access = PL1_RW, .accessfn = access_scxtnum,
403
+ .access = PL2_RW, .accessfn = access_fgt,
186
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
404
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) },
187
+ { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
405
+ { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64,
188
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
406
+ .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4,
189
+ .access = PL2_RW, .accessfn = access_scxtnum,
407
+ .access = PL2_RW, .accessfn = access_fgt,
190
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
408
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) },
191
+ { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
409
+ { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64,
192
+ .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
410
+ .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5,
193
+ .access = PL3_RW,
411
+ .access = PL2_RW, .accessfn = access_fgt,
194
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
412
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) },
413
+ { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64,
414
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6,
415
+ .access = PL2_RW, .accessfn = access_fgt,
416
+ .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) },
195
+};
417
+};
196
+#endif /* TARGET_AARCH64 */
418
#endif /* TARGET_AARCH64 */
197
419
198
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
420
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
199
bool isread)
200
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
421
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
201
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
422
if (cpu_isar_feature(aa64_scxtnum, cpu)) {
202
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
423
define_arm_cp_regs(cpu, scxtnum_reginfo);
203
}
424
}
204
+
425
+
205
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
426
+ if (cpu_isar_feature(aa64_fgt, cpu)) {
206
+ define_arm_cp_regs(cpu, scxtnum_reginfo);
427
+ define_arm_cp_regs(cpu, fgt_reginfo);
207
+ }
428
+ }
208
#endif
429
#endif
209
430
210
if (cpu_isar_feature(any_predinv, cpu)) {
431
if (cpu_isar_feature(any_predinv, cpu)) {
211
--
432
--
212
2.25.1
433
2.34.1
diff view generated by jsdifflib
[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
[PULL 19/33] target/arm: Implement FGT trapping infrastructure
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the machinery for fine-grained traps on normal sysregs.
2
2
Any sysreg with a fine-grained trap will set the new field to
3
Previously we were defining some of these in user-only mode,
3
indicate which FGT register bit it should trap on.
4
but none of them are accessible from user-only, therefore
4
5
define them only in system mode.
5
FGT traps only happen when an AArch64 EL2 enables them for
6
6
an AArch64 EL1. They therefore are only relevant for AArch32
7
This will shortly be used from cpu_tcg.c also.
7
cpregs when the cpreg can be accessed from EL0. The logic
8
8
in access_check_cp_reg() will check this, so it is safe to
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo.
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
11
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
11
The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname
12
which can be used to specify the FGT bit, eg
13
.fgt = FGT_AFSR0_EL1
14
(We assume that there is no bit name duplication across the FGT
15
registers, for brevity's sake.)
16
17
Subsequent commits will add the .fgt fields to the relevant register
18
definitions and define the FGT_nnn values for them.
19
20
Note that some of the FGT traps are for instructions that we don't
21
handle via the cpregs mechanisms (mostly these are instruction traps).
22
Those we will have to handle separately.
23
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Tested-by: Fuad Tabba <tabba@google.com>
27
Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org
28
Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
13
---
29
---
14
target/arm/internals.h | 6 ++++
30
target/arm/cpregs.h | 72 ++++++++++++++++++++++++++++++++++++++
15
target/arm/cpu64.c | 64 +++---------------------------------------
31
target/arm/cpu.h | 1 +
16
target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++
32
target/arm/internals.h | 20 +++++++++++
17
3 files changed, 69 insertions(+), 60 deletions(-)
33
target/arm/translate.h | 2 ++
18
34
target/arm/helper.c | 9 +++++
35
target/arm/op_helper.c | 30 ++++++++++++++++
36
target/arm/translate-a64.c | 3 +-
37
target/arm/translate.c | 2 ++
38
8 files changed, 138 insertions(+), 1 deletion(-)
39
40
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpregs.h
43
+++ b/target/arm/cpregs.h
44
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
45
FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
46
FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
47
48
+/* Which fine-grained trap bit register to check, if any */
49
+FIELD(FGT, TYPE, 10, 3)
50
+FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
51
+FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */
52
+FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
53
+
54
+/*
55
+ * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt
56
+ * fields. We assume for brevity's sake that there are no duplicated
57
+ * bit names across the various FGT registers.
58
+ */
59
+#define DO_BIT(REG, BITNAME) \
60
+ FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
61
+
62
+/* Some bits have reversed sense, so 0 means trap and 1 means not */
63
+#define DO_REV_BIT(REG, BITNAME) \
64
+ FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
65
+
66
+typedef enum FGTBit {
67
+ /*
68
+ * These bits tell us which register arrays to use:
69
+ * if FGT_R is set then reads are checked against fgt_read[];
70
+ * if FGT_W is set then writes are checked against fgt_write[];
71
+ * if FGT_EXEC is set then all accesses are checked against fgt_exec[].
72
+ *
73
+ * For almost all bits in the R/W register pairs, the bit exists in
74
+ * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register
75
+ * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
76
+ * for a WO register. There are unfortunately a couple of exceptions
77
+ * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but
78
+ * the FGT system only allows trapping of writes, not reads.
79
+ *
80
+ * Note that we arrange these bits so that a 0 FGTBit means "no trap".
81
+ */
82
+ FGT_R = 1 << R_FGT_TYPE_SHIFT,
83
+ FGT_W = 2 << R_FGT_TYPE_SHIFT,
84
+ FGT_EXEC = 4 << R_FGT_TYPE_SHIFT,
85
+ FGT_RW = FGT_R | FGT_W,
86
+ /* Bit to identify whether trap bit is reversed sense */
87
+ FGT_REV = R_FGT_REV_MASK,
88
+
89
+ /*
90
+ * If a bit exists in HFGRTR/HDFGRTR then either the register being
91
+ * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either
92
+ * want to trap for both reads and writes or else it's harmless to mark
93
+ * it as trap-on-writes.
94
+ * If a bit exists only in HFGWTR/HDFGWTR then either the register being
95
+ * trapped is WO, or else it is one of the two oddball special cases
96
+ * which are RW but have only a write trap. We mark these as only
97
+ * FGT_W so we get the right behaviour for those special cases.
98
+ * (If a bit was added in future that provided only a read trap for an
99
+ * RW register we'd need to do something special to get the FGT_R bit
100
+ * only. But this seems unlikely to happen.)
101
+ *
102
+ * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if
103
+ * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR.
104
+ */
105
+ FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT),
106
+ FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT),
107
+ FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
108
+ FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
109
+ FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
110
+} FGTBit;
111
+
112
+#undef DO_BIT
113
+#undef DO_REV_BIT
114
+
115
typedef struct ARMCPRegInfo ARMCPRegInfo;
116
117
/*
118
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
119
CPAccessRights access;
120
/* Security state: ARM_CP_SECSTATE_* bits/values */
121
CPSecureState secure;
122
+ /*
123
+ * Which fine-grained trap register bit to check, if any. This
124
+ * value encodes both the trap register and bit within it.
125
+ */
126
+ FGTBit fgt;
127
/*
128
* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
129
* this register was defined: can be used to hand data through to the
130
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
131
index XXXXXXX..XXXXXXX 100644
132
--- a/target/arm/cpu.h
133
+++ b/target/arm/cpu.h
134
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
135
/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
136
FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
137
FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
138
+FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
139
140
/*
141
* Bit usage when in AArch32 state, both A- and M-profile.
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
142
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
143
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
144
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
145
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
146
@@ -XXX,XX +XXX,XX @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
24
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
147
((1 << (1 - 1)) | (1 << (2 - 1)) | \
148
(1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
149
150
+/*
151
+ * Return true if it is possible to take a fine-grained-trap to EL2.
152
+ */
153
+static inline bool arm_fgt_active(CPUARMState *env, int el)
154
+{
155
+ /*
156
+ * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
157
+ * that can affect EL0, but it is harmless to do the test also for
158
+ * traps on registers that are only accessible at EL1 because if the test
159
+ * returns true then we can't be executing at EL1 anyway.
160
+ * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
161
+ * traps from AArch32 only happen for the EL0 is AArch32 case.
162
+ */
163
+ return cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
164
+ el < 2 && arm_is_el2_enabled(env) &&
165
+ arm_el_is_aa64(env, 1) &&
166
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
167
+ (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
168
+}
169
+
25
#endif
170
#endif
26
171
diff --git a/target/arm/translate.h b/target/arm/translate.h
27
+#ifdef CONFIG_USER_ONLY
172
index XXXXXXX..XXXXXXX 100644
28
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
173
--- a/target/arm/translate.h
29
+#else
174
+++ b/target/arm/translate.h
30
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
175
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
31
+#endif
176
bool is_nonstreaming;
32
+
177
/* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
33
#endif
178
bool mve_no_pred;
34
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
179
+ /* True if fine-grained traps are active */
35
index XXXXXXX..XXXXXXX 100644
180
+ bool fgt_active;
36
--- a/target/arm/cpu64.c
181
/*
37
+++ b/target/arm/cpu64.c
182
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
38
@@ -XXX,XX +XXX,XX @@
183
* < 0, set by the current instruction.
39
#include "hvf_arm.h"
184
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
#include "qapi/visitor.h"
185
index XXXXXXX..XXXXXXX 100644
41
#include "hw/qdev-properties.h"
186
--- a/target/arm/helper.c
42
-#include "cpregs.h"
187
+++ b/target/arm/helper.c
43
+#include "internals.h"
188
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
44
189
if (arm_singlestep_active(env)) {
45
190
DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
46
-#ifndef CONFIG_USER_ONLY
191
}
47
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
192
+
48
-{
193
return flags;
49
- ARMCPU *cpu = env_archcpu(env);
50
-
51
- /* Number of cores is in [25:24]; otherwise we RAZ */
52
- return (cpu->core_count - 1) << 24;
53
-}
54
-#endif
55
-
56
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
57
-#ifndef CONFIG_USER_ONLY
58
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
59
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
60
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
61
- .writefn = arm_cp_write_ignore },
62
- { .name = "L2CTLR",
63
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
64
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
65
- .writefn = arm_cp_write_ignore },
66
-#endif
67
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
68
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
69
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
70
- { .name = "L2ECTLR",
71
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
72
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
73
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
74
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
75
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
76
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
77
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
78
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
- { .name = "CPUACTLR",
80
- .cp = 15, .opc1 = 0, .crm = 15,
81
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
82
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
83
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
84
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
85
- { .name = "CPUECTLR",
86
- .cp = 15, .opc1 = 1, .crm = 15,
87
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
88
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
89
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
90
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
91
- { .name = "CPUMERRSR",
92
- .cp = 15, .opc1 = 2, .crm = 15,
93
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
94
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
95
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
96
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
97
- { .name = "L2MERRSR",
98
- .cp = 15, .opc1 = 3, .crm = 15,
99
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
100
-};
101
-
102
static void aarch64_a57_initfn(Object *obj)
103
{
104
ARMCPU *cpu = ARM_CPU(obj);
105
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
106
cpu->gic_num_lrs = 4;
107
cpu->gic_vpribits = 5;
108
cpu->gic_vprebits = 5;
109
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
110
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
111
}
194
}
112
195
113
static void aarch64_a53_initfn(Object *obj)
196
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
114
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
197
DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
115
cpu->gic_num_lrs = 4;
198
}
116
cpu->gic_vpribits = 5;
199
117
cpu->gic_vprebits = 5;
200
+ if (arm_fgt_active(env, el)) {
118
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
201
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
119
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
202
+ }
120
}
203
+
121
204
if (env->uncached_cpsr & CPSR_IL) {
122
static void aarch64_a72_initfn(Object *obj)
205
DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
123
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
206
}
124
cpu->gic_num_lrs = 4;
207
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
125
cpu->gic_vpribits = 5;
208
DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
126
cpu->gic_vprebits = 5;
209
}
127
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
210
128
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
211
+ if (arm_fgt_active(env, el)) {
129
}
212
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
130
213
+ }
131
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
214
+
132
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
215
if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
133
index XXXXXXX..XXXXXXX 100644
216
/*
134
--- a/target/arm/cpu_tcg.c
217
* Set MTE_ACTIVE if any access may be Checked, and leave clear
135
+++ b/target/arm/cpu_tcg.c
218
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
136
@@ -XXX,XX +XXX,XX @@
219
index XXXXXXX..XXXXXXX 100644
137
#endif
220
--- a/target/arm/op_helper.c
138
#include "cpregs.h"
221
+++ b/target/arm/op_helper.c
139
222
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
140
+#ifndef CONFIG_USER_ONLY
223
}
141
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
224
}
142
+{
225
143
+ ARMCPU *cpu = env_archcpu(env);
226
+ /*
144
+
227
+ * Fine-grained traps also are lower priority than undef-to-EL1,
145
+ /* Number of cores is in [25:24]; otherwise we RAZ */
228
+ * higher priority than trap-to-EL3, and we don't care about priority
146
+ return (cpu->core_count - 1) << 24;
229
+ * order with other EL2 traps because the syndrome value is the same.
147
+}
230
+ */
148
+
231
+ if (arm_fgt_active(env, arm_current_el(env))) {
149
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
232
+ uint64_t trapword = 0;
150
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
233
+ unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
151
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
234
+ unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
152
+ .access = PL1_RW, .readfn = l2ctlr_read,
235
+ bool rev = FIELD_EX32(ri->fgt, FGT, REV);
153
+ .writefn = arm_cp_write_ignore },
236
+ bool trapbit;
154
+ { .name = "L2CTLR",
237
+
155
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
238
+ if (ri->fgt & FGT_EXEC) {
156
+ .access = PL1_RW, .readfn = l2ctlr_read,
239
+ assert(idx < ARRAY_SIZE(env->cp15.fgt_exec));
157
+ .writefn = arm_cp_write_ignore },
240
+ trapword = env->cp15.fgt_exec[idx];
158
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
241
+ } else if (isread && (ri->fgt & FGT_R)) {
159
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
242
+ assert(idx < ARRAY_SIZE(env->cp15.fgt_read));
160
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
243
+ trapword = env->cp15.fgt_read[idx];
161
+ { .name = "L2ECTLR",
244
+ } else if (!isread && (ri->fgt & FGT_W)) {
162
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
245
+ assert(idx < ARRAY_SIZE(env->cp15.fgt_write));
163
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
246
+ trapword = env->cp15.fgt_write[idx];
164
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
247
+ }
165
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
248
+
166
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
249
+ trapbit = extract64(trapword, bitpos, 1);
167
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
250
+ if (trapbit != rev) {
168
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
251
+ res = CP_ACCESS_TRAP_EL2;
169
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
252
+ goto fail;
170
+ { .name = "CPUACTLR",
253
+ }
171
+ .cp = 15, .opc1 = 0, .crm = 15,
254
+ }
172
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
255
+
173
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
256
if (likely(res == CP_ACCESS_OK)) {
174
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
257
return ri;
175
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
258
}
176
+ { .name = "CPUECTLR",
259
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
177
+ .cp = 15, .opc1 = 1, .crm = 15,
260
index XXXXXXX..XXXXXXX 100644
178
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
261
--- a/target/arm/translate-a64.c
179
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
262
+++ b/target/arm/translate-a64.c
180
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
263
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
181
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
264
return;
182
+ { .name = "CPUMERRSR",
265
}
183
+ .cp = 15, .opc1 = 2, .crm = 15,
266
184
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
267
- if (ri->accessfn) {
185
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
268
+ if (ri->accessfn || (ri->fgt && s->fgt_active)) {
186
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
269
/* Emit code to perform further access permissions checks at
187
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
270
* runtime; this may result in an exception.
188
+ { .name = "L2MERRSR",
271
*/
189
+ .cp = 15, .opc1 = 3, .crm = 15,
272
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
190
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
273
dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
191
+};
274
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
192
+
275
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
193
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
276
+ dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
194
+{
277
dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
195
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
278
dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
196
+}
279
dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
197
+#endif /* !CONFIG_USER_ONLY */
280
diff --git a/target/arm/translate.c b/target/arm/translate.c
198
+
281
index XXXXXXX..XXXXXXX 100644
199
/* CPU models. These are not needed for the AArch64 linux-user build. */
282
--- a/target/arm/translate.c
200
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
283
+++ b/target/arm/translate.c
201
284
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
285
}
286
287
if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
288
+ (ri->fgt && s->fgt_active) ||
289
(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
290
/*
291
* Emit code to perform further access permissions checks at
292
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
293
dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
294
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
295
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
296
+ dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
297
298
if (arm_feature(env, ARM_FEATURE_M)) {
299
dc->vfp_enabled = 1;
202
--
300
--
203
2.25.1
301
2.34.1
diff view generated by jsdifflib
[PULL 04/32] target/arm: Merge zcr reginfo
[PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Mark up the sysreg definitions for the registers trapped
2
by HFGRTR/HFGWTR bits 0..11.
2
3
3
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
while registering.
6
Tested-by: Fuad Tabba <tabba@google.com>
7
Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org
8
Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org
9
---
10
target/arm/cpregs.h | 14 ++++++++++++++
11
target/arm/helper.c | 17 +++++++++++++++++
12
2 files changed, 31 insertions(+)
6
13
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
index XXXXXXX..XXXXXXX 100644
9
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
16
--- a/target/arm/cpregs.h
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
+++ b/target/arm/cpregs.h
11
---
18
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
12
target/arm/helper.c | 55 ++++++++++++++-------------------------------
19
FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
13
1 file changed, 17 insertions(+), 38 deletions(-)
20
FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
14
21
FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
22
+
23
+ /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
24
+ DO_BIT(HFGRTR, AFSR0_EL1),
25
+ DO_BIT(HFGRTR, AFSR1_EL1),
26
+ DO_BIT(HFGRTR, AIDR_EL1),
27
+ DO_BIT(HFGRTR, AMAIR_EL1),
28
+ DO_BIT(HFGRTR, APDAKEY),
29
+ DO_BIT(HFGRTR, APDBKEY),
30
+ DO_BIT(HFGRTR, APGAKEY),
31
+ DO_BIT(HFGRTR, APIAKEY),
32
+ DO_BIT(HFGRTR, APIBKEY),
33
+ DO_BIT(HFGRTR, CCSIDR_EL1),
34
+ DO_BIT(HFGRTR, CLIDR_EL1),
35
+ DO_BIT(HFGRTR, CONTEXTIDR_EL1),
36
} FGTBit;
37
38
#undef DO_BIT
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
20
}
44
{ .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
21
}
45
.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
22
46
.access = PL1_RW, .accessfn = access_tvm_trvm,
23
-static const ARMCPRegInfo zcr_el1_reginfo = {
47
+ .fgt = FGT_CONTEXTIDR_EL1,
24
- .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
48
.secure = ARM_CP_SECSTATE_NS,
25
- .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
49
.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
26
- .access = PL1_RW, .type = ARM_CP_SVE,
50
.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
27
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
51
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
28
- .writefn = zcr_write, .raw_writefn = raw_write
52
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
29
-};
53
.access = PL1_R,
30
-
54
.accessfn = access_tid4,
31
-static const ARMCPRegInfo zcr_el2_reginfo = {
55
+ .fgt = FGT_CCSIDR_EL1,
32
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
56
.readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
33
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
57
{ .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
34
- .access = PL2_RW, .type = ARM_CP_SVE,
58
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
35
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
59
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
36
- .writefn = zcr_write, .raw_writefn = raw_write
60
.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
37
-};
61
.access = PL1_R, .type = ARM_CP_CONST,
38
-
62
.accessfn = access_aa64_tid1,
39
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
63
+ .fgt = FGT_AIDR_EL1,
40
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
64
.resetvalue = 0 },
41
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
65
/*
42
- .access = PL2_RW, .type = ARM_CP_SVE,
66
* Auxiliary fault status registers: these also are IMPDEF, and we
43
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
44
-};
68
{ .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
45
-
69
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
46
-static const ARMCPRegInfo zcr_el3_reginfo = {
70
.access = PL1_RW, .accessfn = access_tvm_trvm,
47
- .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
71
+ .fgt = FGT_AFSR0_EL1,
48
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
72
.type = ARM_CP_CONST, .resetvalue = 0 },
49
- .access = PL3_RW, .type = ARM_CP_SVE,
73
{ .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
50
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
74
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
51
- .writefn = zcr_write, .raw_writefn = raw_write
75
.access = PL1_RW, .accessfn = access_tvm_trvm,
52
+static const ARMCPRegInfo zcr_reginfo[] = {
76
+ .fgt = FGT_AFSR1_EL1,
53
+ { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
77
.type = ARM_CP_CONST, .resetvalue = 0 },
54
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
78
/*
55
+ .access = PL1_RW, .type = ARM_CP_SVE,
79
* MAIR can just read-as-written because we don't implement caches
56
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
80
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
57
+ .writefn = zcr_write, .raw_writefn = raw_write },
81
{ .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
58
+ { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
82
.opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
59
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
83
.access = PL1_RW, .accessfn = access_tvm_trvm,
60
+ .access = PL2_RW, .type = ARM_CP_SVE,
84
+ .fgt = FGT_AMAIR_EL1,
61
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
85
.type = ARM_CP_CONST, .resetvalue = 0 },
62
+ .writefn = zcr_write, .raw_writefn = raw_write },
86
/* AMAIR1 is mapped to AMAIR_EL1[63:32] */
63
+ { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
87
{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
64
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
88
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
65
+ .access = PL3_RW, .type = ARM_CP_SVE,
89
{ .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
66
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
90
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
67
+ .writefn = zcr_write, .raw_writefn = raw_write },
91
.access = PL1_RW, .accessfn = access_pauth,
92
+ .fgt = FGT_APDAKEY,
93
.fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
94
{ .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
95
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
96
.access = PL1_RW, .accessfn = access_pauth,
97
+ .fgt = FGT_APDAKEY,
98
.fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
99
{ .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
100
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
101
.access = PL1_RW, .accessfn = access_pauth,
102
+ .fgt = FGT_APDBKEY,
103
.fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
104
{ .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
105
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
106
.access = PL1_RW, .accessfn = access_pauth,
107
+ .fgt = FGT_APDBKEY,
108
.fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
109
{ .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
110
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
111
.access = PL1_RW, .accessfn = access_pauth,
112
+ .fgt = FGT_APGAKEY,
113
.fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
114
{ .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
115
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
116
.access = PL1_RW, .accessfn = access_pauth,
117
+ .fgt = FGT_APGAKEY,
118
.fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
119
{ .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
120
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
121
.access = PL1_RW, .accessfn = access_pauth,
122
+ .fgt = FGT_APIAKEY,
123
.fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
124
{ .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
125
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
126
.access = PL1_RW, .accessfn = access_pauth,
127
+ .fgt = FGT_APIAKEY,
128
.fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
129
{ .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
130
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
131
.access = PL1_RW, .accessfn = access_pauth,
132
+ .fgt = FGT_APIBKEY,
133
.fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
134
{ .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
135
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
136
.access = PL1_RW, .accessfn = access_pauth,
137
+ .fgt = FGT_APIBKEY,
138
.fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
68
};
139
};
69
140
70
void hw_watchpoint_update(ARMCPU *cpu, int n)
71
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
141
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
72
}
142
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
73
143
.access = PL1_R, .type = ARM_CP_CONST,
74
if (cpu_isar_feature(aa64_sve, cpu)) {
144
.accessfn = access_tid4,
75
- define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
145
+ .fgt = FGT_CLIDR_EL1,
76
- if (arm_feature(env, ARM_FEATURE_EL2)) {
146
.resetvalue = cpu->clidr
77
- define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
147
};
78
- } else {
148
define_one_arm_cp_reg(cpu, &clidr);
79
- define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
80
- }
81
- if (arm_feature(env, ARM_FEATURE_EL3)) {
82
- define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
83
- }
84
+ define_arm_cp_regs(cpu, zcr_reginfo);
85
}
86
87
#ifdef TARGET_AARCH64
88
--
149
--
89
2.25.1
150
2.34.1
diff view generated by jsdifflib
[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
[PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23
1
From: Gavin Shan <gshan@redhat.com>
1
Mark up the sysreg definitions for the registers trapped
2
by HFGRTR/HFGWTR bits 12..23.
2
3
3
In aarch64_numa_cpu(), the CPU and NUMA association is something
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
like below. Two threads in the same core/cluster/socket are
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
associated with two individual NUMA nodes, which is unreal as
6
Tested-by: Fuad Tabba <tabba@google.com>
6
Igor Mammedov mentioned. We don't expect the association to break
7
Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org
7
NUMA-to-socket boundary, which matches with the real world.
8
Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org
9
---
10
target/arm/cpregs.h | 12 ++++++++++++
11
target/arm/helper.c | 12 ++++++++++++
12
2 files changed, 24 insertions(+)
8
13
9
NUMA-node socket cluster core thread
14
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
10
------------------------------------------
11
0 0 0 0 0
12
1 0 0 0 1
13
14
This corrects the topology for CPUs and their association with
15
NUMA nodes. After this patch is applied, the CPU and NUMA
16
association becomes something like below, which looks real.
17
Besides, socket/cluster/core/thread IDs are all checked when
18
the NUMA node IDs are verified. It helps to check if the CPU
19
topology is properly populated or not.
20
21
NUMA-node socket cluster core thread
22
------------------------------------------
23
0 1 0 0 0
24
1 0 0 0 0
25
26
Suggested-by: Igor Mammedov <imammedo@redhat.com>
27
Signed-off-by: Gavin Shan <gshan@redhat.com>
28
Acked-by: Igor Mammedov <imammedo@redhat.com>
29
Message-id: 20220503140304.855514-5-gshan@redhat.com
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
32
tests/qtest/numa-test.c | 18 ++++++++++++------
33
1 file changed, 12 insertions(+), 6 deletions(-)
34
35
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
36
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
37
--- a/tests/qtest/numa-test.c
16
--- a/target/arm/cpregs.h
38
+++ b/tests/qtest/numa-test.c
17
+++ b/target/arm/cpregs.h
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
18
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
40
g_autofree char *cli = NULL;
19
DO_BIT(HFGRTR, CCSIDR_EL1),
41
20
DO_BIT(HFGRTR, CLIDR_EL1),
42
cli = make_cli(data, "-machine "
21
DO_BIT(HFGRTR, CONTEXTIDR_EL1),
43
- "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
22
+ DO_BIT(HFGRTR, CPACR_EL1),
44
+ "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
23
+ DO_BIT(HFGRTR, CSSELR_EL1),
45
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
24
+ DO_BIT(HFGRTR, CTR_EL0),
46
- "-numa cpu,node-id=1,thread-id=0 "
25
+ DO_BIT(HFGRTR, DCZID_EL0),
47
- "-numa cpu,node-id=0,thread-id=1");
26
+ DO_BIT(HFGRTR, ESR_EL1),
48
+ "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
27
+ DO_BIT(HFGRTR, FAR_EL1),
49
+ "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
28
+ DO_BIT(HFGRTR, ISR_EL1),
50
qts = qtest_init(cli);
29
+ DO_BIT(HFGRTR, LORC_EL1),
51
cpus = get_cpus(qts, &resp);
30
+ DO_BIT(HFGRTR, LOREA_EL1),
52
g_assert(cpus);
31
+ DO_BIT(HFGRTR, LORID_EL1),
53
32
+ DO_BIT(HFGRTR, LORN_EL1),
54
while ((e = qlist_pop(cpus))) {
33
+ DO_BIT(HFGRTR, LORSA_EL1),
55
QDict *cpu, *props;
34
} FGTBit;
56
- int64_t thread, node;
35
57
+ int64_t socket, cluster, core, thread, node;
36
#undef DO_BIT
58
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
59
cpu = qobject_to(QDict, e);
38
index XXXXXXX..XXXXXXX 100644
60
g_assert(qdict_haskey(cpu, "props"));
39
--- a/target/arm/helper.c
61
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
40
+++ b/target/arm/helper.c
62
41
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
63
g_assert(qdict_haskey(props, "node-id"));
42
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
64
node = qdict_get_int(props, "node-id");
43
{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
65
+ g_assert(qdict_haskey(props, "socket-id"));
44
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
66
+ socket = qdict_get_int(props, "socket-id");
45
+ .fgt = FGT_CPACR_EL1,
67
+ g_assert(qdict_haskey(props, "cluster-id"));
46
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
68
+ cluster = qdict_get_int(props, "cluster-id");
47
.resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
69
+ g_assert(qdict_haskey(props, "core-id"));
48
};
70
+ core = qdict_get_int(props, "core-id");
49
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
71
g_assert(qdict_haskey(props, "thread-id"));
50
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
72
thread = qdict_get_int(props, "thread-id");
51
.access = PL1_RW,
73
52
.accessfn = access_tid4,
74
- if (thread == 0) {
53
+ .fgt = FGT_CSSELR_EL1,
75
+ if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
54
.writefn = csselr_write, .resetvalue = 0,
76
g_assert_cmpint(node, ==, 1);
55
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
77
- } else if (thread == 1) {
56
offsetof(CPUARMState, cp15.csselr_ns) } },
78
+ } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
57
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
79
g_assert_cmpint(node, ==, 0);
58
.resetfn = arm_cp_reset_ignore },
80
} else {
59
{ .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
81
g_assert(false);
60
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
61
+ .fgt = FGT_ISR_EL1,
62
.type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
63
/* 32 bit ITLB invalidates */
64
{ .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
66
{ .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
67
.opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
68
.access = PL1_RW, .accessfn = access_tvm_trvm,
69
+ .fgt = FGT_FAR_EL1,
70
.fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
71
.resetvalue = 0, },
72
};
73
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
74
{ .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
75
.opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
76
.access = PL1_RW, .accessfn = access_tvm_trvm,
77
+ .fgt = FGT_ESR_EL1,
78
.fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
79
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
80
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
81
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
82
{ .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
83
.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
84
.access = PL0_R, .type = ARM_CP_NO_RAW,
85
+ .fgt = FGT_DCZID_EL0,
86
.readfn = aa64_dczid_read },
87
{ .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
88
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
89
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
90
{ .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
91
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
92
.access = PL1_RW, .accessfn = access_lor_other,
93
+ .fgt = FGT_LORSA_EL1,
94
.type = ARM_CP_CONST, .resetvalue = 0 },
95
{ .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
96
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
97
.access = PL1_RW, .accessfn = access_lor_other,
98
+ .fgt = FGT_LOREA_EL1,
99
.type = ARM_CP_CONST, .resetvalue = 0 },
100
{ .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
101
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
102
.access = PL1_RW, .accessfn = access_lor_other,
103
+ .fgt = FGT_LORN_EL1,
104
.type = ARM_CP_CONST, .resetvalue = 0 },
105
{ .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
106
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
107
.access = PL1_RW, .accessfn = access_lor_other,
108
+ .fgt = FGT_LORC_EL1,
109
.type = ARM_CP_CONST, .resetvalue = 0 },
110
{ .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
111
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
112
.access = PL1_R, .accessfn = access_lor_ns,
113
+ .fgt = FGT_LORID_EL1,
114
.type = ARM_CP_CONST, .resetvalue = 0 },
115
};
116
117
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
118
{ .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
119
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
120
.access = PL0_R, .accessfn = ctr_el0_access,
121
+ .fgt = FGT_CTR_EL0,
122
.type = ARM_CP_CONST, .resetvalue = cpu->ctr },
123
/* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
124
{ .name = "TCMTR",
82
--
125
--
83
2.25.1
126
2.34.1
diff view generated by jsdifflib
[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
[PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Mark up the sysreg definitions for the registers trapped
2
by HFGRTR/HFGWTR bits 24..35.
2
3
3
This extension concerns changes to the External Debug interface,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
with Secure and Non-secure access to the debug registers, and all
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
of it is outside the scope of QEMU. Indicating support for this
6
Tested-by: Fuad Tabba <tabba@google.com>
6
is mandatory with FEAT_SEL2, which we do implement.
7
Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org
8
Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org
9
---
10
target/arm/cpregs.h | 12 ++++++++++++
11
target/arm/helper.c | 14 ++++++++++++++
12
2 files changed, 26 insertions(+)
7
13
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/system/arm/emulation.rst | 1 +
14
target/arm/cpu64.c | 2 +-
15
target/arm/cpu_tcg.c | 4 ++--
16
3 files changed, 4 insertions(+), 3 deletions(-)
17
18
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/emulation.rst
16
--- a/target/arm/cpregs.h
21
+++ b/docs/system/arm/emulation.rst
17
+++ b/target/arm/cpregs.h
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
23
- FEAT_DIT (Data Independent Timing instructions)
19
DO_BIT(HFGRTR, LORID_EL1),
24
- FEAT_DPB (DC CVAP instruction)
20
DO_BIT(HFGRTR, LORN_EL1),
25
- FEAT_Debugv8p2 (Debug changes for v8.2)
21
DO_BIT(HFGRTR, LORSA_EL1),
26
+- FEAT_Debugv8p4 (Debug changes for v8.4)
22
+ DO_BIT(HFGRTR, MAIR_EL1),
27
- FEAT_DotProd (Advanced SIMD dot product instructions)
23
+ DO_BIT(HFGRTR, MIDR_EL1),
28
- FEAT_FCMA (Floating-point complex number instructions)
24
+ DO_BIT(HFGRTR, MPIDR_EL1),
29
- FEAT_FHM (Floating-point half-precision multiplication instructions)
25
+ DO_BIT(HFGRTR, PAR_EL1),
30
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
+ DO_BIT(HFGRTR, REVIDR_EL1),
27
+ DO_BIT(HFGRTR, SCTLR_EL1),
28
+ DO_BIT(HFGRTR, SCXTNUM_EL1),
29
+ DO_BIT(HFGRTR, SCXTNUM_EL0),
30
+ DO_BIT(HFGRTR, TCR_EL1),
31
+ DO_BIT(HFGRTR, TPIDR_EL1),
32
+ DO_BIT(HFGRTR, TPIDRRO_EL0),
33
+ DO_BIT(HFGRTR, TPIDR_EL0),
34
} FGTBit;
35
36
#undef DO_BIT
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu64.c
39
--- a/target/arm/helper.c
33
+++ b/target/arm/cpu64.c
40
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
41
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
35
cpu->isar.id_aa64zfr0 = t;
42
{ .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
36
43
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
37
t = cpu->isar.id_aa64dfr0;
44
.access = PL1_RW, .accessfn = access_tvm_trvm,
38
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
45
+ .fgt = FGT_MAIR_EL1,
39
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
46
.fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
40
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
47
.resetvalue = 0 },
41
cpu->isar.id_aa64dfr0 = t;
48
{ .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
42
49
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
43
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
50
{ .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
44
index XXXXXXX..XXXXXXX 100644
51
.opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
45
--- a/target/arm/cpu_tcg.c
52
.access = PL0_RW,
46
+++ b/target/arm/cpu_tcg.c
53
+ .fgt = FGT_TPIDR_EL0,
47
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
54
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
48
cpu->isar.id_pfr2 = t;
55
{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
49
56
.access = PL0_RW,
50
t = cpu->isar.id_dfr0;
57
+ .fgt = FGT_TPIDR_EL0,
51
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
58
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
52
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
59
offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
53
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
60
.resetfn = arm_cp_reset_ignore },
54
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
61
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
55
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
62
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
56
cpu->isar.id_dfr0 = t;
63
.access = PL0_R | PL1_W,
57
}
64
+ .fgt = FGT_TPIDRRO_EL0,
65
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
66
.resetvalue = 0},
67
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
68
.access = PL0_R | PL1_W,
69
+ .fgt = FGT_TPIDRRO_EL0,
70
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
71
offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
72
.resetfn = arm_cp_reset_ignore },
73
{ .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
74
.opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
75
.access = PL1_RW,
76
+ .fgt = FGT_TPIDR_EL1,
77
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
78
{ .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
79
.access = PL1_RW,
80
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
81
{ .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
82
.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
83
.access = PL1_RW, .accessfn = access_tvm_trvm,
84
+ .fgt = FGT_TCR_EL1,
85
.writefn = vmsa_tcr_el12_write,
86
.raw_writefn = raw_write,
87
.resetvalue = 0,
88
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
89
.type = ARM_CP_ALIAS,
90
.opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
91
.access = PL1_RW, .resetvalue = 0,
92
+ .fgt = FGT_PAR_EL1,
93
.fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
94
.writefn = par_write },
95
#endif
96
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
97
{ .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
98
.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
99
.access = PL0_RW, .accessfn = access_scxtnum,
100
+ .fgt = FGT_SCXTNUM_EL0,
101
.fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
102
{ .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
103
.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
104
.access = PL1_RW, .accessfn = access_scxtnum,
105
+ .fgt = FGT_SCXTNUM_EL1,
106
.fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
107
{ .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
108
.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
109
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
110
{ .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
112
.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
113
+ .fgt = FGT_MIDR_EL1,
114
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
115
.readfn = midr_read },
116
/* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
117
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
118
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
119
.access = PL1_R,
120
.accessfn = access_aa64_tid1,
121
+ .fgt = FGT_REVIDR_EL1,
122
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
123
};
124
ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
125
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
126
ARMCPRegInfo mpidr_cp_reginfo[] = {
127
{ .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
128
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
129
+ .fgt = FGT_MPIDR_EL1,
130
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
131
};
132
#ifdef CONFIG_USER_ONLY
133
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
134
.name = "SCTLR", .state = ARM_CP_STATE_BOTH,
135
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
136
.access = PL1_RW, .accessfn = access_tvm_trvm,
137
+ .fgt = FGT_SCTLR_EL1,
138
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
139
offsetof(CPUARMState, cp15.sctlr_ns) },
140
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
58
--
141
--
59
2.25.1
142
2.34.1
diff view generated by jsdifflib
[PULL 27/32] qapi/machine.json: Add cluster-id
[PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63
1
From: Gavin Shan <gshan@redhat.com>
1
Mark up the sysreg definitions for the registers trapped
2
by HFGRTR/HFGWTR bits 36..63.
2
3
3
This adds cluster-id in CPU instance properties, which will be used
4
Of these, some correspond to RAS registers which we implement as
4
by arm/virt machine. Besides, the cluster-id is also verified or
5
always-UNDEF: these don't need any extra handling for FGT because the
5
dumped in various spots:
6
UNDEF-to-EL1 always takes priority over any theoretical
7
FGT-trap-to-EL2.
6
8
7
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
9
Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part
8
CPU with its NUMA node.
10
of the FEAT_LS64_ACCDATA feature which we don't yet implement.
9
11
10
* hw/core/machine.c::machine_numa_finish_cpu_init() to record
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
CPU slots with no NUMA mapping set.
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Fuad Tabba <tabba@google.com>
15
Message-id: 20230130182459.3309057-14-peter.maydell@linaro.org
16
Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org
17
---
18
target/arm/cpregs.h | 7 +++++++
19
hw/intc/arm_gicv3_cpuif.c | 2 ++
20
target/arm/helper.c | 10 ++++++++++
21
3 files changed, 19 insertions(+)
12
22
13
* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
23
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
14
cluster-id.
15
16
Signed-off-by: Gavin Shan <gshan@redhat.com>
17
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
18
Acked-by: Igor Mammedov <imammedo@redhat.com>
19
Message-id: 20220503140304.855514-2-gshan@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
qapi/machine.json | 6 ++++--
23
hw/core/machine-hmp-cmds.c | 4 ++++
24
hw/core/machine.c | 16 ++++++++++++++++
25
3 files changed, 24 insertions(+), 2 deletions(-)
26
27
diff --git a/qapi/machine.json b/qapi/machine.json
28
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
29
--- a/qapi/machine.json
25
--- a/target/arm/cpregs.h
30
+++ b/qapi/machine.json
26
+++ b/target/arm/cpregs.h
31
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
32
# @node-id: NUMA node ID the CPU belongs to
28
DO_BIT(HFGRTR, TPIDR_EL1),
33
# @socket-id: socket number within node/board the CPU belongs to
29
DO_BIT(HFGRTR, TPIDRRO_EL0),
34
# @die-id: die number within socket the CPU belongs to (since 4.1)
30
DO_BIT(HFGRTR, TPIDR_EL0),
35
-# @core-id: core number within die the CPU belongs to
31
+ DO_BIT(HFGRTR, TTBR0_EL1),
36
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
32
+ DO_BIT(HFGRTR, TTBR1_EL1),
37
+# @core-id: core number within cluster the CPU belongs to
33
+ DO_BIT(HFGRTR, VBAR_EL1),
38
# @thread-id: thread number within core the CPU belongs to
34
+ DO_BIT(HFGRTR, ICC_IGRPENN_EL1),
39
#
35
+ DO_BIT(HFGRTR, ERRIDR_EL1),
40
-# Note: currently there are 5 properties that could be present
36
+ DO_REV_BIT(HFGRTR, NSMPRI_EL1),
41
+# Note: currently there are 6 properties that could be present
37
+ DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
42
# but management should be prepared to pass through other
38
} FGTBit;
43
# properties with device_add command to allow for future
39
44
# interface extension. This also requires the filed names to be kept in
40
#undef DO_BIT
45
@@ -XXX,XX +XXX,XX @@
41
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
46
'data': { '*node-id': 'int',
47
'*socket-id': 'int',
48
'*die-id': 'int',
49
+ '*cluster-id': 'int',
50
'*core-id': 'int',
51
'*thread-id': 'int'
52
}
53
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
54
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/core/machine-hmp-cmds.c
43
--- a/hw/intc/arm_gicv3_cpuif.c
56
+++ b/hw/core/machine-hmp-cmds.c
44
+++ b/hw/intc/arm_gicv3_cpuif.c
57
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
45
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
58
if (c->has_die_id) {
46
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
59
monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
47
.type = ARM_CP_IO | ARM_CP_NO_RAW,
60
}
48
.access = PL1_RW, .accessfn = gicv3_fiq_access,
61
+ if (c->has_cluster_id) {
49
+ .fgt = FGT_ICC_IGRPENN_EL1,
62
+ monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n",
50
.readfn = icc_igrpen_read,
63
+ c->cluster_id);
51
.writefn = icc_igrpen_write,
64
+ }
52
},
65
if (c->has_core_id) {
53
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
66
monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
54
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
67
}
55
.type = ARM_CP_IO | ARM_CP_NO_RAW,
68
diff --git a/hw/core/machine.c b/hw/core/machine.c
56
.access = PL1_RW, .accessfn = gicv3_irq_access,
57
+ .fgt = FGT_ICC_IGRPENN_EL1,
58
.readfn = icc_igrpen_read,
59
.writefn = icc_igrpen_write,
60
},
61
diff --git a/target/arm/helper.c b/target/arm/helper.c
69
index XXXXXXX..XXXXXXX 100644
62
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/core/machine.c
63
--- a/target/arm/helper.c
71
+++ b/hw/core/machine.c
64
+++ b/target/arm/helper.c
72
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
73
return;
66
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
74
}
67
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
75
68
.access = PL1_RW, .accessfn = access_tvm_trvm,
76
+ if (props->has_cluster_id && !slot->props.has_cluster_id) {
69
+ .fgt = FGT_TTBR0_EL1,
77
+ error_setg(errp, "cluster-id is not supported");
70
.writefn = vmsa_ttbr_write, .resetvalue = 0,
78
+ return;
71
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
79
+ }
72
offsetof(CPUARMState, cp15.ttbr0_ns) } },
80
+
73
{ .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
81
if (props->has_socket_id && !slot->props.has_socket_id) {
74
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
82
error_setg(errp, "socket-id is not supported");
75
.access = PL1_RW, .accessfn = access_tvm_trvm,
83
return;
76
+ .fgt = FGT_TTBR1_EL1,
84
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
77
.writefn = vmsa_ttbr_write, .resetvalue = 0,
85
continue;
78
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
86
}
79
offsetof(CPUARMState, cp15.ttbr1_ns) } },
87
80
@@ -XXX,XX +XXX,XX @@ static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
88
+ if (props->has_cluster_id &&
81
* ERRSELR_EL1
89
+ props->cluster_id != slot->props.cluster_id) {
82
* may generate UNDEFINED, which is the effect we get by not
90
+ continue;
83
* listing them at all.
91
+ }
84
+ *
92
+
85
+ * These registers have fine-grained trap bits, but UNDEF-to-EL1
93
if (props->has_die_id && props->die_id != slot->props.die_id) {
86
+ * is higher priority than FGT-to-EL2 so we do not need to list them
94
continue;
87
+ * in order to check for an FGT.
95
}
88
*/
96
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
89
static const ARMCPRegInfo minimal_ras_reginfo[] = {
97
}
90
{ .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
98
g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
91
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
99
}
92
{ .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
100
+ if (cpu->props.has_cluster_id) {
93
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
101
+ if (s->len) {
94
.access = PL1_R, .accessfn = access_terr,
102
+ g_string_append_printf(s, ", ");
95
+ .fgt = FGT_ERRIDR_EL1,
103
+ }
96
.type = ARM_CP_CONST, .resetvalue = 0 },
104
+ g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
97
{ .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
105
+ }
98
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
106
if (cpu->props.has_core_id) {
99
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
107
if (s->len) {
100
{ .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,
108
g_string_append_printf(s, ", ");
101
.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,
102
.access = PL0_RW, .accessfn = access_tpidr2,
103
+ .fgt = FGT_NTPIDR2_EL0,
104
.fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },
105
{ .name = "SVCR", .state = ARM_CP_STATE_AA64,
106
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,
107
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
108
{ .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64,
109
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,
110
.access = PL1_RW, .accessfn = access_esm,
111
+ .fgt = FGT_NSMPRI_EL1,
112
.type = ARM_CP_CONST, .resetvalue = 0 },
113
{ .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,
114
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
115
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
116
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
117
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
118
.access = PL1_RW, .writefn = vbar_write,
119
+ .fgt = FGT_VBAR_EL1,
120
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
121
offsetof(CPUARMState, cp15.vbar_ns) },
122
.resetvalue = 0 },
109
--
123
--
110
2.25.1
124
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11
1
Mark up the sysreg definitons for the registers trapped
2
by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
3
related registers.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Fuad Tabba <tabba@google.com>
8
Message-id: 20230130182459.3309057-15-peter.maydell@linaro.org
9
Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org
10
---
11
target/arm/cpregs.h | 12 ++++++++++++
12
target/arm/debug_helper.c | 11 +++++++++++
13
2 files changed, 23 insertions(+)
14
15
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpregs.h
18
+++ b/target/arm/cpregs.h
19
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
20
DO_BIT(HFGRTR, ERRIDR_EL1),
21
DO_REV_BIT(HFGRTR, NSMPRI_EL1),
22
DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
23
+
24
+ /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */
25
+ DO_BIT(HDFGRTR, DBGBCRN_EL1),
26
+ DO_BIT(HDFGRTR, DBGBVRN_EL1),
27
+ DO_BIT(HDFGRTR, DBGWCRN_EL1),
28
+ DO_BIT(HDFGRTR, DBGWVRN_EL1),
29
+ DO_BIT(HDFGRTR, MDSCR_EL1),
30
+ DO_BIT(HDFGRTR, DBGCLAIM),
31
+ DO_BIT(HDFGWTR, OSLAR_EL1),
32
+ DO_BIT(HDFGRTR, OSLSR_EL1),
33
+ DO_BIT(HDFGRTR, OSECCR_EL1),
34
+ DO_BIT(HDFGRTR, OSDLR_EL1),
35
} FGTBit;
36
37
#undef DO_BIT
38
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/debug_helper.c
41
+++ b/target/arm/debug_helper.c
42
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
43
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
44
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
45
.access = PL1_RW, .accessfn = access_tda,
46
+ .fgt = FGT_MDSCR_EL1,
47
.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
48
.resetvalue = 0 },
49
/*
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
51
{ .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
52
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
53
.access = PL1_RW, .accessfn = access_tda,
54
+ .fgt = FGT_OSECCR_EL1,
55
.type = ARM_CP_CONST, .resetvalue = 0 },
56
/*
57
* DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
58
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
59
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
60
.access = PL1_W, .type = ARM_CP_NO_RAW,
61
.accessfn = access_tdosa,
62
+ .fgt = FGT_OSLAR_EL1,
63
.writefn = oslar_write },
64
{ .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
65
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
66
.access = PL1_R, .resetvalue = 10,
67
.accessfn = access_tdosa,
68
+ .fgt = FGT_OSLSR_EL1,
69
.fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
70
/* Dummy OSDLR_EL1: 32-bit Linux will read this */
71
{ .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
72
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
73
.access = PL1_RW, .accessfn = access_tdosa,
74
+ .fgt = FGT_OSDLR_EL1,
75
.writefn = osdlr_write,
76
.fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) },
77
/*
78
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
79
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
80
.type = ARM_CP_ALIAS,
81
.access = PL1_RW, .accessfn = access_tda,
82
+ .fgt = FGT_DBGCLAIM,
83
.writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
84
{ .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
85
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
86
.access = PL1_RW, .accessfn = access_tda,
87
+ .fgt = FGT_DBGCLAIM,
88
.writefn = dbgclaimclr_write, .raw_writefn = raw_write,
89
.fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
90
};
91
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
92
{ .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
93
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
94
.access = PL1_RW, .accessfn = access_tda,
95
+ .fgt = FGT_DBGBVRN_EL1,
96
.fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
97
.writefn = dbgbvr_write, .raw_writefn = raw_write
98
},
99
{ .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
100
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
101
.access = PL1_RW, .accessfn = access_tda,
102
+ .fgt = FGT_DBGBCRN_EL1,
103
.fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
104
.writefn = dbgbcr_write, .raw_writefn = raw_write
105
},
106
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
107
{ .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
108
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
109
.access = PL1_RW, .accessfn = access_tda,
110
+ .fgt = FGT_DBGWVRN_EL1,
111
.fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
112
.writefn = dbgwvr_write, .raw_writefn = raw_write
113
},
114
{ .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
115
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
116
.access = PL1_RW, .accessfn = access_tda,
117
+ .fgt = FGT_DBGWCRN_EL1,
118
.fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
119
.writefn = dbgwcr_write, .raw_writefn = raw_write
120
},
121
--
122
2.34.1
diff view generated by jsdifflib
[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
[PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Mark up the sysreg definitions for the registers trapped
2
2
by HDFGRTR/HDFGWTR bits 12..x.
3
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
3
4
is CONTEXTIDR_EL2, which is also conditionally implemented
4
Bits 12..22 and bit 58 are for PMU registers.
5
with FEAT_VHE. The rest of the debug extension concerns the
5
6
External debug interface, which is outside the scope of QEMU.
6
The remaining bits in HDFGRTR/HDFGWTR are for traps on
7
7
registers that are part of features we don't implement:
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Bits 23..32 and 63 : FEAT_SPE
10
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
10
Bits 33..48 : FEAT_ETE
11
Bits 50..56 : FEAT_TRBE
12
Bits 59..61 : FEAT_BRBE
13
Bit 62 : FEAT_SPEv1p2.
14
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Tested-by: Fuad Tabba <tabba@google.com>
18
Message-id: 20230130182459.3309057-16-peter.maydell@linaro.org
19
Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org
12
---
20
---
13
docs/system/arm/emulation.rst | 1 +
21
target/arm/cpregs.h | 12 ++++++++++++
14
target/arm/cpu.c | 1 +
22
target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++
15
target/arm/cpu64.c | 1 +
23
2 files changed, 49 insertions(+)
16
target/arm/cpu_tcg.c | 2 ++
24
17
4 files changed, 5 insertions(+)
25
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
18
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
27
--- a/target/arm/cpregs.h
22
+++ b/docs/system/arm/emulation.rst
28
+++ b/target/arm/cpregs.h
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
29
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
24
- FEAT_BTI (Branch Target Identification)
30
DO_BIT(HDFGRTR, OSLSR_EL1),
25
- FEAT_DIT (Data Independent Timing instructions)
31
DO_BIT(HDFGRTR, OSECCR_EL1),
26
- FEAT_DPB (DC CVAP instruction)
32
DO_BIT(HDFGRTR, OSDLR_EL1),
27
+- FEAT_Debugv8p2 (Debug changes for v8.2)
33
+ DO_BIT(HDFGRTR, PMEVCNTRN_EL0),
28
- FEAT_DotProd (Advanced SIMD dot product instructions)
34
+ DO_BIT(HDFGRTR, PMEVTYPERN_EL0),
29
- FEAT_FCMA (Floating-point complex number instructions)
35
+ DO_BIT(HDFGRTR, PMCCFILTR_EL0),
30
- FEAT_FHM (Floating-point half-precision multiplication instructions)
36
+ DO_BIT(HDFGRTR, PMCCNTR_EL0),
31
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
37
+ DO_BIT(HDFGRTR, PMCNTEN),
38
+ DO_BIT(HDFGRTR, PMINTEN),
39
+ DO_BIT(HDFGRTR, PMOVS),
40
+ DO_BIT(HDFGRTR, PMSELR_EL0),
41
+ DO_BIT(HDFGWTR, PMSWINC_EL0),
42
+ DO_BIT(HDFGWTR, PMCR_EL0),
43
+ DO_BIT(HDFGRTR, PMMIR_EL1),
44
+ DO_BIT(HDFGRTR, PMCEIDN_EL0),
45
} FGTBit;
46
47
#undef DO_BIT
48
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu.c
50
--- a/target/arm/helper.c
34
+++ b/target/arm/cpu.c
51
+++ b/target/arm/helper.c
35
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
52
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
36
* feature registers as well.
53
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
37
*/
54
.writefn = pmcntenset_write,
38
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
55
.accessfn = pmreg_access,
39
+ cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
56
+ .fgt = FGT_PMCNTEN,
40
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
57
.raw_writefn = raw_write },
41
ID_AA64PFR0, EL3, 0);
58
{ .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
42
}
59
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
43
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
60
.access = PL0_RW, .accessfn = pmreg_access,
44
index XXXXXXX..XXXXXXX 100644
61
+ .fgt = FGT_PMCNTEN,
45
--- a/target/arm/cpu64.c
62
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
46
+++ b/target/arm/cpu64.c
63
.writefn = pmcntenset_write, .raw_writefn = raw_write },
47
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
64
{ .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
48
cpu->isar.id_aa64zfr0 = t;
65
.access = PL0_RW,
49
66
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
50
t = cpu->isar.id_aa64dfr0;
67
.accessfn = pmreg_access,
51
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
68
+ .fgt = FGT_PMCNTEN,
52
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
69
.writefn = pmcntenclr_write,
53
cpu->isar.id_aa64dfr0 = t;
70
.type = ARM_CP_ALIAS | ARM_CP_IO },
54
71
{ .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
55
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
72
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
56
index XXXXXXX..XXXXXXX 100644
73
.access = PL0_RW, .accessfn = pmreg_access,
57
--- a/target/arm/cpu_tcg.c
74
+ .fgt = FGT_PMCNTEN,
58
+++ b/target/arm/cpu_tcg.c
75
.type = ARM_CP_ALIAS | ARM_CP_IO,
59
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
76
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
60
cpu->isar.id_pfr2 = t;
77
.writefn = pmcntenclr_write },
61
78
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
62
t = cpu->isar.id_dfr0;
79
.access = PL0_RW, .type = ARM_CP_IO,
63
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
80
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
64
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
81
.accessfn = pmreg_access,
65
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
82
+ .fgt = FGT_PMOVS,
66
cpu->isar.id_dfr0 = t;
83
.writefn = pmovsr_write,
67
}
84
.raw_writefn = raw_write },
85
{ .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
86
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
87
.access = PL0_RW, .accessfn = pmreg_access,
88
+ .fgt = FGT_PMOVS,
89
.type = ARM_CP_ALIAS | ARM_CP_IO,
90
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
91
.writefn = pmovsr_write,
92
.raw_writefn = raw_write },
93
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
94
.access = PL0_W, .accessfn = pmreg_access_swinc,
95
+ .fgt = FGT_PMSWINC_EL0,
96
.type = ARM_CP_NO_RAW | ARM_CP_IO,
97
.writefn = pmswinc_write },
98
{ .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
99
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
100
.access = PL0_W, .accessfn = pmreg_access_swinc,
101
+ .fgt = FGT_PMSWINC_EL0,
102
.type = ARM_CP_NO_RAW | ARM_CP_IO,
103
.writefn = pmswinc_write },
104
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
105
.access = PL0_RW, .type = ARM_CP_ALIAS,
106
+ .fgt = FGT_PMSELR_EL0,
107
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
108
.accessfn = pmreg_access_selr, .writefn = pmselr_write,
109
.raw_writefn = raw_write},
110
{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
111
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
112
.access = PL0_RW, .accessfn = pmreg_access_selr,
113
+ .fgt = FGT_PMSELR_EL0,
114
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
115
.writefn = pmselr_write, .raw_writefn = raw_write, },
116
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
117
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
118
+ .fgt = FGT_PMCCNTR_EL0,
119
.readfn = pmccntr_read, .writefn = pmccntr_write32,
120
.accessfn = pmreg_access_ccntr },
121
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
122
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
123
.access = PL0_RW, .accessfn = pmreg_access_ccntr,
124
+ .fgt = FGT_PMCCNTR_EL0,
125
.type = ARM_CP_IO,
126
.fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
127
.readfn = pmccntr_read, .writefn = pmccntr_write,
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
129
{ .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
130
.writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
131
.access = PL0_RW, .accessfn = pmreg_access,
132
+ .fgt = FGT_PMCCFILTR_EL0,
133
.type = ARM_CP_ALIAS | ARM_CP_IO,
134
.resetvalue = 0, },
135
{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
136
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
137
.writefn = pmccfiltr_write, .raw_writefn = raw_write,
138
.access = PL0_RW, .accessfn = pmreg_access,
139
+ .fgt = FGT_PMCCFILTR_EL0,
140
.type = ARM_CP_IO,
141
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
142
.resetvalue = 0, },
143
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
144
.access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
145
.accessfn = pmreg_access,
146
+ .fgt = FGT_PMEVTYPERN_EL0,
147
.writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
148
{ .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
149
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
150
.access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
151
.accessfn = pmreg_access,
152
+ .fgt = FGT_PMEVTYPERN_EL0,
153
.writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
154
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
155
.access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
156
.accessfn = pmreg_access_xevcntr,
157
+ .fgt = FGT_PMEVCNTRN_EL0,
158
.writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
159
{ .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
161
.access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
162
.accessfn = pmreg_access_xevcntr,
163
+ .fgt = FGT_PMEVCNTRN_EL0,
164
.writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
165
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
166
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
167
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
168
.writefn = pmuserenr_write, .raw_writefn = raw_write },
169
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
170
.access = PL1_RW, .accessfn = access_tpm,
171
+ .fgt = FGT_PMINTEN,
172
.type = ARM_CP_ALIAS | ARM_CP_IO,
173
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
174
.resetvalue = 0,
175
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
176
{ .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
177
.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
178
.access = PL1_RW, .accessfn = access_tpm,
179
+ .fgt = FGT_PMINTEN,
180
.type = ARM_CP_IO,
181
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
182
.writefn = pmintenset_write, .raw_writefn = raw_write,
183
.resetvalue = 0x0 },
184
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
185
.access = PL1_RW, .accessfn = access_tpm,
186
+ .fgt = FGT_PMINTEN,
187
.type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
188
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
189
.writefn = pmintenclr_write, },
190
{ .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
192
.access = PL1_RW, .accessfn = access_tpm,
193
+ .fgt = FGT_PMINTEN,
194
.type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
195
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
196
.writefn = pmintenclr_write },
197
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
198
/* PMOVSSET is not implemented in v7 before v7ve */
199
{ .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
200
.access = PL0_RW, .accessfn = pmreg_access,
201
+ .fgt = FGT_PMOVS,
202
.type = ARM_CP_ALIAS | ARM_CP_IO,
203
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
204
.writefn = pmovsset_write,
205
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
206
{ .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
207
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
208
.access = PL0_RW, .accessfn = pmreg_access,
209
+ .fgt = FGT_PMOVS,
210
.type = ARM_CP_ALIAS | ARM_CP_IO,
211
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
212
.writefn = pmovsset_write,
213
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
214
ARMCPRegInfo pmcr = {
215
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
216
.access = PL0_RW,
217
+ .fgt = FGT_PMCR_EL0,
218
.type = ARM_CP_IO | ARM_CP_ALIAS,
219
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
220
.accessfn = pmreg_access, .writefn = pmcr_write,
221
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
222
.name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
223
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
224
.access = PL0_RW, .accessfn = pmreg_access,
225
+ .fgt = FGT_PMCR_EL0,
226
.type = ARM_CP_IO,
227
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
228
.resetvalue = cpu->isar.reset_pmcr_el0,
229
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
230
{ .name = pmevcntr_name, .cp = 15, .crn = 14,
231
.crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
232
.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
233
+ .fgt = FGT_PMEVCNTRN_EL0,
234
.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
235
.accessfn = pmreg_access_xevcntr },
236
{ .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
237
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
238
.opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
239
.type = ARM_CP_IO,
240
+ .fgt = FGT_PMEVCNTRN_EL0,
241
.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
242
.raw_readfn = pmevcntr_rawread,
243
.raw_writefn = pmevcntr_rawwrite },
244
{ .name = pmevtyper_name, .cp = 15, .crn = 14,
245
.crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
246
.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
247
+ .fgt = FGT_PMEVTYPERN_EL0,
248
.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
249
.accessfn = pmreg_access },
250
{ .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
252
.opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
253
+ .fgt = FGT_PMEVTYPERN_EL0,
254
.type = ARM_CP_IO,
255
.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
256
.raw_writefn = pmevtyper_rawwrite },
257
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
258
{ .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
259
.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
260
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
261
+ .fgt = FGT_PMCEIDN_EL0,
262
.resetvalue = extract64(cpu->pmceid0, 32, 32) },
263
{ .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
264
.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
265
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
266
+ .fgt = FGT_PMCEIDN_EL0,
267
.resetvalue = extract64(cpu->pmceid1, 32, 32) },
268
};
269
define_arm_cp_regs(cpu, v81_pmu_regs);
270
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
271
.name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
272
.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
273
.access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
274
+ .fgt = FGT_PMMIR_EL1,
275
.resetvalue = 0
276
};
277
define_one_arm_cp_reg(cpu, &v84_pmmir);
278
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
279
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
280
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
281
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
282
+ .fgt = FGT_PMCEIDN_EL0,
283
.resetvalue = extract64(cpu->pmceid0, 0, 32) },
284
{ .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
285
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
286
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
287
+ .fgt = FGT_PMCEIDN_EL0,
288
.resetvalue = cpu->pmceid0 },
289
{ .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
290
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
291
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
292
+ .fgt = FGT_PMCEIDN_EL0,
293
.resetvalue = extract64(cpu->pmceid1, 0, 32) },
294
{ .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
295
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
296
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
297
+ .fgt = FGT_PMCEIDN_EL0,
298
.resetvalue = cpu->pmceid1 },
299
};
300
#ifdef CONFIG_USER_ONLY
68
--
301
--
69
2.25.1
302
2.34.1
diff view generated by jsdifflib
[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
[PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Mark up the sysreg definitions for the system instructions
2
trapped by HFGITR bits 0..11. These bits cover various
3
cache maintenance operations.
2
4
3
We set this for qemu-system-aarch64, but failed to do so
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
for the strictly 32-bit emulation.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Fuad Tabba <tabba@google.com>
8
Message-id: 20230130182459.3309057-17-peter.maydell@linaro.org
9
Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org
10
---
11
target/arm/cpregs.h | 14 ++++++++++++++
12
target/arm/helper.c | 28 ++++++++++++++++++++++++++++
13
2 files changed, 42 insertions(+)
5
14
6
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
15
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu_tcg.c | 4 ++++
13
1 file changed, 4 insertions(+)
14
15
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu_tcg.c
17
--- a/target/arm/cpregs.h
18
+++ b/target/arm/cpu_tcg.c
18
+++ b/target/arm/cpregs.h
19
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
19
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
20
t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
20
DO_BIT(HDFGWTR, PMCR_EL0),
21
cpu->isar.id_pfr2 = t;
21
DO_BIT(HDFGRTR, PMMIR_EL1),
22
22
DO_BIT(HDFGRTR, PMCEIDN_EL0),
23
+ t = cpu->isar.id_dfr0;
24
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
25
+ cpu->isar.id_dfr0 = t;
26
+
23
+
27
#ifdef CONFIG_USER_ONLY
24
+ /* Trap bits in HFGITR_EL2, starting from bit 0 */
28
/*
25
+ DO_BIT(HFGITR, ICIALLUIS),
29
* Break with true ARMv8 and add back old-style VFP short-vector support.
26
+ DO_BIT(HFGITR, ICIALLU),
27
+ DO_BIT(HFGITR, ICIVAU),
28
+ DO_BIT(HFGITR, DCIVAC),
29
+ DO_BIT(HFGITR, DCISW),
30
+ DO_BIT(HFGITR, DCCSW),
31
+ DO_BIT(HFGITR, DCCISW),
32
+ DO_BIT(HFGITR, DCCVAU),
33
+ DO_BIT(HFGITR, DCCVAP),
34
+ DO_BIT(HFGITR, DCCVADP),
35
+ DO_BIT(HFGITR, DCCIVAC),
36
+ DO_BIT(HFGITR, DCZVA),
37
} FGTBit;
38
39
#undef DO_BIT
40
diff --git a/target/arm/helper.c b/target/arm/helper.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/helper.c
43
+++ b/target/arm/helper.c
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
45
#ifndef CONFIG_USER_ONLY
46
/* Avoid overhead of an access check that always passes in user-mode */
47
.accessfn = aa64_zva_access,
48
+ .fgt = FGT_DCZVA,
49
#endif
50
},
51
{ .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
52
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
53
{ .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
54
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
55
.access = PL1_W, .type = ARM_CP_NOP,
56
+ .fgt = FGT_ICIALLUIS,
57
.accessfn = access_ticab },
58
{ .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
59
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
60
.access = PL1_W, .type = ARM_CP_NOP,
61
+ .fgt = FGT_ICIALLU,
62
.accessfn = access_tocu },
63
{ .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
64
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
65
.access = PL0_W, .type = ARM_CP_NOP,
66
+ .fgt = FGT_ICIVAU,
67
.accessfn = access_tocu },
68
{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
69
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
70
.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
71
+ .fgt = FGT_DCIVAC,
72
.type = ARM_CP_NOP },
73
{ .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
74
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
75
+ .fgt = FGT_DCISW,
76
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
77
{ .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
78
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
79
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
80
.accessfn = aa64_cacheop_poc_access },
81
{ .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
82
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
83
+ .fgt = FGT_DCCSW,
84
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
85
{ .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
86
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
87
.access = PL0_W, .type = ARM_CP_NOP,
88
+ .fgt = FGT_DCCVAU,
89
.accessfn = access_tocu },
90
{ .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
91
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
92
.access = PL0_W, .type = ARM_CP_NOP,
93
+ .fgt = FGT_DCCIVAC,
94
.accessfn = aa64_cacheop_poc_access },
95
{ .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
96
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
97
+ .fgt = FGT_DCCISW,
98
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
99
/* TLBI operations */
100
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
101
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
102
{ .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
103
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
104
.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
105
+ .fgt = FGT_DCCVAP,
106
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
107
};
108
109
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
110
{ .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
111
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
112
.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
113
+ .fgt = FGT_DCCVADP,
114
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
115
};
116
#endif /*CONFIG_USER_ONLY*/
117
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
118
{ .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
119
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
120
.type = ARM_CP_NOP, .access = PL1_W,
121
+ .fgt = FGT_DCIVAC,
122
.accessfn = aa64_cacheop_poc_access },
123
{ .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
124
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
125
+ .fgt = FGT_DCISW,
126
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
127
{ .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
128
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
129
.type = ARM_CP_NOP, .access = PL1_W,
130
+ .fgt = FGT_DCIVAC,
131
.accessfn = aa64_cacheop_poc_access },
132
{ .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
134
+ .fgt = FGT_DCISW,
135
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
136
{ .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
137
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
138
+ .fgt = FGT_DCCSW,
139
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
140
{ .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
141
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
142
+ .fgt = FGT_DCCSW,
143
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
144
{ .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
145
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
146
+ .fgt = FGT_DCCISW,
147
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
148
{ .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
149
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
150
+ .fgt = FGT_DCCISW,
151
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
152
};
153
154
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
155
{ .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
156
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
157
.type = ARM_CP_NOP, .access = PL0_W,
158
+ .fgt = FGT_DCCVAP,
159
.accessfn = aa64_cacheop_poc_access },
160
{ .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
161
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
162
.type = ARM_CP_NOP, .access = PL0_W,
163
+ .fgt = FGT_DCCVAP,
164
.accessfn = aa64_cacheop_poc_access },
165
{ .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
166
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
167
.type = ARM_CP_NOP, .access = PL0_W,
168
+ .fgt = FGT_DCCVADP,
169
.accessfn = aa64_cacheop_poc_access },
170
{ .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
172
.type = ARM_CP_NOP, .access = PL0_W,
173
+ .fgt = FGT_DCCVADP,
174
.accessfn = aa64_cacheop_poc_access },
175
{ .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
176
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
177
.type = ARM_CP_NOP, .access = PL0_W,
178
+ .fgt = FGT_DCCIVAC,
179
.accessfn = aa64_cacheop_poc_access },
180
{ .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
181
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
182
.type = ARM_CP_NOP, .access = PL0_W,
183
+ .fgt = FGT_DCCIVAC,
184
.accessfn = aa64_cacheop_poc_access },
185
{ .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
186
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
187
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
188
#ifndef CONFIG_USER_ONLY
189
/* Avoid overhead of an access check that always passes in user-mode */
190
.accessfn = aa64_zva_access,
191
+ .fgt = FGT_DCZVA,
192
#endif
193
},
194
{ .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
195
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
196
#ifndef CONFIG_USER_ONLY
197
/* Avoid overhead of an access check that always passes in user-mode */
198
.accessfn = aa64_zva_access,
199
+ .fgt = FGT_DCZVA,
200
#endif
201
},
202
};
30
--
203
--
31
2.25.1
204
2.34.1
diff view generated by jsdifflib
[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
[PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Mark up the sysreg definitions for the system instructions
2
trapped by HFGITR bits 12..17. These bits cover AT address
3
translation instructions.
2
4
3
Instead of starting with cortex-a15 and adding v8 features to
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
This fixes the long-standing to-do where we only enabled v8
7
Tested-by: Fuad Tabba <tabba@google.com>
6
features for user-only.
8
Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org
9
Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org
10
---
11
target/arm/cpregs.h | 6 ++++++
12
target/arm/helper.c | 6 ++++++
13
2 files changed, 12 insertions(+)
7
14
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
14
1 file changed, 92 insertions(+), 59 deletions(-)
15
16
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu_tcg.c
17
--- a/target/arm/cpregs.h
19
+++ b/target/arm/cpu_tcg.c
18
+++ b/target/arm/cpregs.h
20
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
19
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
21
static void arm_max_initfn(Object *obj)
20
DO_BIT(HFGITR, DCCVADP),
22
{
21
DO_BIT(HFGITR, DCCIVAC),
23
ARMCPU *cpu = ARM_CPU(obj);
22
DO_BIT(HFGITR, DCZVA),
24
+ uint32_t t;
23
+ DO_BIT(HFGITR, ATS1E1R),
25
24
+ DO_BIT(HFGITR, ATS1E1W),
26
- cortex_a15_initfn(obj);
25
+ DO_BIT(HFGITR, ATS1E0R),
27
+ /* aarch64_a57_initfn, advertising none of the aarch64 features */
26
+ DO_BIT(HFGITR, ATS1E0W),
28
+ cpu->dtb_compatible = "arm,cortex-a57";
27
+ DO_BIT(HFGITR, ATS1E1RP),
29
+ set_feature(&cpu->env, ARM_FEATURE_V8);
28
+ DO_BIT(HFGITR, ATS1E1WP),
30
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
29
} FGTBit;
31
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
30
32
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
31
#undef DO_BIT
33
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
32
diff --git a/target/arm/helper.c b/target/arm/helper.c
34
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
33
index XXXXXXX..XXXXXXX 100644
35
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
34
--- a/target/arm/helper.c
36
+ cpu->midr = 0x411fd070;
35
+++ b/target/arm/helper.c
37
+ cpu->revidr = 0x00000000;
36
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
38
+ cpu->reset_fpsid = 0x41034070;
37
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
39
+ cpu->isar.mvfr0 = 0x10110222;
38
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
40
+ cpu->isar.mvfr1 = 0x12111111;
39
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
41
+ cpu->isar.mvfr2 = 0x00000043;
40
+ .fgt = FGT_ATS1E1R,
42
+ cpu->ctr = 0x8444c004;
41
.writefn = ats_write64 },
43
+ cpu->reset_sctlr = 0x00c50838;
42
{ .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
44
+ cpu->isar.id_pfr0 = 0x00000131;
43
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
45
+ cpu->isar.id_pfr1 = 0x00011011;
44
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
46
+ cpu->isar.id_dfr0 = 0x03010066;
45
+ .fgt = FGT_ATS1E1W,
47
+ cpu->id_afr0 = 0x00000000;
46
.writefn = ats_write64 },
48
+ cpu->isar.id_mmfr0 = 0x10101105;
47
{ .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
49
+ cpu->isar.id_mmfr1 = 0x40000000;
48
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
50
+ cpu->isar.id_mmfr2 = 0x01260000;
49
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
51
+ cpu->isar.id_mmfr3 = 0x02102211;
50
+ .fgt = FGT_ATS1E0R,
52
+ cpu->isar.id_isar0 = 0x02101110;
51
.writefn = ats_write64 },
53
+ cpu->isar.id_isar1 = 0x13112111;
52
{ .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
54
+ cpu->isar.id_isar2 = 0x21232042;
53
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
55
+ cpu->isar.id_isar3 = 0x01112131;
54
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
56
+ cpu->isar.id_isar4 = 0x00011142;
55
+ .fgt = FGT_ATS1E0W,
57
+ cpu->isar.id_isar5 = 0x00011121;
56
.writefn = ats_write64 },
58
+ cpu->isar.id_isar6 = 0;
57
{ .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
59
+ cpu->isar.dbgdidr = 0x3516d000;
58
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
60
+ cpu->clidr = 0x0a200023;
59
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
61
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
60
{ .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
62
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
61
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
63
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
62
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
64
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
63
+ .fgt = FGT_ATS1E1RP,
65
64
.writefn = ats_write64 },
66
- /* old-style VFP short-vector support */
65
{ .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
67
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
66
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
68
+ /* Add additional features supported by QEMU */
67
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
69
+ t = cpu->isar.id_isar5;
68
+ .fgt = FGT_ATS1E1WP,
70
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
69
.writefn = ats_write64 },
71
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
70
};
72
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
73
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
74
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
75
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
76
+ cpu->isar.id_isar5 = t;
77
+
78
+ t = cpu->isar.id_isar6;
79
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
80
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
81
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
82
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
83
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
84
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
85
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
86
+ cpu->isar.id_isar6 = t;
87
+
88
+ t = cpu->isar.mvfr1;
89
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
90
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
91
+ cpu->isar.mvfr1 = t;
92
+
93
+ t = cpu->isar.mvfr2;
94
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
95
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
96
+ cpu->isar.mvfr2 = t;
97
+
98
+ t = cpu->isar.id_mmfr3;
99
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
100
+ cpu->isar.id_mmfr3 = t;
101
+
102
+ t = cpu->isar.id_mmfr4;
103
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
104
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
105
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
106
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
107
+ cpu->isar.id_mmfr4 = t;
108
+
109
+ t = cpu->isar.id_pfr0;
110
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
111
+ cpu->isar.id_pfr0 = t;
112
+
113
+ t = cpu->isar.id_pfr2;
114
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
115
+ cpu->isar.id_pfr2 = t;
116
117
#ifdef CONFIG_USER_ONLY
118
/*
119
- * We don't set these in system emulation mode for the moment,
120
- * since we don't correctly set (all of) the ID registers to
121
- * advertise them.
122
+ * Break with true ARMv8 and add back old-style VFP short-vector support.
123
+ * Only do this for user-mode, where -cpu max is the default, so that
124
+ * older v6 and v7 programs are more likely to work without adjustment.
125
*/
126
- set_feature(&cpu->env, ARM_FEATURE_V8);
127
- {
128
- uint32_t t;
129
-
130
- t = cpu->isar.id_isar5;
131
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
132
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
133
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
134
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
135
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
136
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
137
- cpu->isar.id_isar5 = t;
138
-
139
- t = cpu->isar.id_isar6;
140
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
141
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
142
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
143
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
144
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
145
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
146
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
147
- cpu->isar.id_isar6 = t;
148
-
149
- t = cpu->isar.mvfr1;
150
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
151
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
152
- cpu->isar.mvfr1 = t;
153
-
154
- t = cpu->isar.mvfr2;
155
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
156
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
157
- cpu->isar.mvfr2 = t;
158
-
159
- t = cpu->isar.id_mmfr3;
160
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
161
- cpu->isar.id_mmfr3 = t;
162
-
163
- t = cpu->isar.id_mmfr4;
164
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
165
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
166
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
167
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
168
- cpu->isar.id_mmfr4 = t;
169
-
170
- t = cpu->isar.id_pfr0;
171
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
172
- cpu->isar.id_pfr0 = t;
173
-
174
- t = cpu->isar.id_pfr2;
175
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
176
- cpu->isar.id_pfr2 = t;
177
- }
178
-#endif /* CONFIG_USER_ONLY */
179
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
180
+#endif
181
}
182
#endif /* !TARGET_AARCH64 */
183
71
184
--
72
--
185
2.25.1
73
2.34.1
diff view generated by jsdifflib
[PULL 02/32] target/arm: Handle cpreg registration for missing EL
[PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Mark up the sysreg definitions for the system instructions
2
trapped by HFGITR bits 18..47. These bits cover TLBI
3
TLB maintenance instructions.
2
4
3
More gracefully handle cpregs when EL2 and/or EL3 are missing.
5
(If we implemented FEAT_XS we would need to trap some of the
4
If the reg is entirely inaccessible, do not register it at all.
6
instructions added by that feature using these bits; but we don't
5
If the reg is for EL2, and EL3 is present but EL2 is not,
7
yet, so will need to add the .fgt markup when we do.)
6
either discard, squash to res0, const, or keep unchanged.
7
8
8
Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
9
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
10
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
11
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
12
13
This will simplify cpreg registration for conditional arm features.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Fuad Tabba <tabba@google.com>
12
Message-id: 20230130182459.3309057-19-peter.maydell@linaro.org
13
Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org
19
---
14
---
20
target/arm/cpregs.h | 11 +++
15
target/arm/cpregs.h | 30 ++++++++++++++++++++++++++++++
21
target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
16
target/arm/helper.c | 30 ++++++++++++++++++++++++++++++
22
2 files changed, 133 insertions(+), 56 deletions(-)
17
2 files changed, 60 insertions(+)
23
18
24
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
19
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
25
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpregs.h
21
--- a/target/arm/cpregs.h
27
+++ b/target/arm/cpregs.h
22
+++ b/target/arm/cpregs.h
28
@@ -XXX,XX +XXX,XX @@ enum {
23
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
29
ARM_CP_SVE = 1 << 14,
24
DO_BIT(HFGITR, ATS1E0W),
30
/* Flag: Do not expose in gdb sysreg xml. */
25
DO_BIT(HFGITR, ATS1E1RP),
31
ARM_CP_NO_GDB = 1 << 15,
26
DO_BIT(HFGITR, ATS1E1WP),
32
+ /*
27
+ DO_BIT(HFGITR, TLBIVMALLE1OS),
33
+ * Flags: If EL3 but not EL2...
28
+ DO_BIT(HFGITR, TLBIVAE1OS),
34
+ * - UNDEF: discard the cpreg,
29
+ DO_BIT(HFGITR, TLBIASIDE1OS),
35
+ * - KEEP: retain the cpreg as is,
30
+ DO_BIT(HFGITR, TLBIVAAE1OS),
36
+ * - C_NZ: set const on the cpreg, but retain resetvalue,
31
+ DO_BIT(HFGITR, TLBIVALE1OS),
37
+ * - else: set const on the cpreg, zero resetvalue, aka RES0.
32
+ DO_BIT(HFGITR, TLBIVAALE1OS),
38
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
33
+ DO_BIT(HFGITR, TLBIRVAE1OS),
39
+ */
34
+ DO_BIT(HFGITR, TLBIRVAAE1OS),
40
+ ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16,
35
+ DO_BIT(HFGITR, TLBIRVALE1OS),
41
+ ARM_CP_EL3_NO_EL2_KEEP = 1 << 17,
36
+ DO_BIT(HFGITR, TLBIRVAALE1OS),
42
+ ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18,
37
+ DO_BIT(HFGITR, TLBIVMALLE1IS),
43
};
38
+ DO_BIT(HFGITR, TLBIVAE1IS),
44
39
+ DO_BIT(HFGITR, TLBIASIDE1IS),
45
/*
40
+ DO_BIT(HFGITR, TLBIVAAE1IS),
41
+ DO_BIT(HFGITR, TLBIVALE1IS),
42
+ DO_BIT(HFGITR, TLBIVAALE1IS),
43
+ DO_BIT(HFGITR, TLBIRVAE1IS),
44
+ DO_BIT(HFGITR, TLBIRVAAE1IS),
45
+ DO_BIT(HFGITR, TLBIRVALE1IS),
46
+ DO_BIT(HFGITR, TLBIRVAALE1IS),
47
+ DO_BIT(HFGITR, TLBIRVAE1),
48
+ DO_BIT(HFGITR, TLBIRVAAE1),
49
+ DO_BIT(HFGITR, TLBIRVALE1),
50
+ DO_BIT(HFGITR, TLBIRVAALE1),
51
+ DO_BIT(HFGITR, TLBIVMALLE1),
52
+ DO_BIT(HFGITR, TLBIVAE1),
53
+ DO_BIT(HFGITR, TLBIASIDE1),
54
+ DO_BIT(HFGITR, TLBIVAAE1),
55
+ DO_BIT(HFGITR, TLBIVALE1),
56
+ DO_BIT(HFGITR, TLBIVAALE1),
57
} FGTBit;
58
59
#undef DO_BIT
46
diff --git a/target/arm/helper.c b/target/arm/helper.c
60
diff --git a/target/arm/helper.c b/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
61
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/helper.c
62
--- a/target/arm/helper.c
49
+++ b/target/arm/helper.c
63
+++ b/target/arm/helper.c
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
64
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
51
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
65
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
52
{ .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
66
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
53
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
67
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
54
- .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
68
+ .fgt = FGT_TLBIVMALLE1IS,
55
+ .access = PL2_RW,
69
.writefn = tlbi_aa64_vmalle1is_write },
56
+ .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
70
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
57
.fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
71
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
58
{ .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
72
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
59
.opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
73
+ .fgt = FGT_TLBIVAE1IS,
60
- .access = PL2_RW, .resetvalue = 0,
74
.writefn = tlbi_aa64_vae1is_write },
61
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
75
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
62
.writefn = dacr_write, .raw_writefn = raw_write,
76
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
63
.fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
77
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
64
{ .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
78
+ .fgt = FGT_TLBIASIDE1IS,
65
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
79
.writefn = tlbi_aa64_vmalle1is_write },
66
- .access = PL2_RW, .resetvalue = 0,
80
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
67
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
81
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
68
.fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
82
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
69
{ .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
83
+ .fgt = FGT_TLBIVAAE1IS,
70
.type = ARM_CP_ALIAS,
84
.writefn = tlbi_aa64_vae1is_write },
71
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
85
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
72
.writefn = tlbimva_hyp_is_write },
86
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
73
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
87
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
74
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
88
+ .fgt = FGT_TLBIVALE1IS,
75
- .type = ARM_CP_NO_RAW, .access = PL2_W,
89
.writefn = tlbi_aa64_vae1is_write },
76
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
90
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
77
.writefn = tlbi_aa64_alle2_write },
91
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
78
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
92
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
79
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
93
+ .fgt = FGT_TLBIVAALE1IS,
80
- .type = ARM_CP_NO_RAW, .access = PL2_W,
94
.writefn = tlbi_aa64_vae1is_write },
81
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
95
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
82
.writefn = tlbi_aa64_vae2_write },
96
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
83
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
97
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
84
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
98
+ .fgt = FGT_TLBIVMALLE1,
85
- .access = PL2_W, .type = ARM_CP_NO_RAW,
99
.writefn = tlbi_aa64_vmalle1_write },
86
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
100
{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
87
.writefn = tlbi_aa64_vae2_write },
101
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
88
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
102
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
89
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
103
+ .fgt = FGT_TLBIVAE1,
90
- .access = PL2_W, .type = ARM_CP_NO_RAW,
104
.writefn = tlbi_aa64_vae1_write },
91
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
105
{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
92
.writefn = tlbi_aa64_alle2is_write },
106
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
93
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
107
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
94
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
108
+ .fgt = FGT_TLBIASIDE1,
95
- .type = ARM_CP_NO_RAW, .access = PL2_W,
109
.writefn = tlbi_aa64_vmalle1_write },
96
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
110
{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
97
.writefn = tlbi_aa64_vae2is_write },
111
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
98
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
112
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
99
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
113
+ .fgt = FGT_TLBIVAAE1,
100
- .access = PL2_W, .type = ARM_CP_NO_RAW,
114
.writefn = tlbi_aa64_vae1_write },
101
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
115
{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
102
.writefn = tlbi_aa64_vae2is_write },
116
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
103
#ifndef CONFIG_USER_ONLY
117
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
104
/* Unlike the other EL2-related AT operations, these must
118
+ .fgt = FGT_TLBIVALE1,
105
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
119
.writefn = tlbi_aa64_vae1_write },
106
{ .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
120
{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
107
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
121
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
108
.access = PL2_W, .accessfn = at_s1e2_access,
122
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
109
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
123
+ .fgt = FGT_TLBIVAALE1,
110
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
124
.writefn = tlbi_aa64_vae1_write },
111
+ .writefn = ats_write64 },
125
{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
112
{ .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
126
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
113
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
114
.access = PL2_W, .accessfn = at_s1e2_access,
115
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
116
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
117
+ .writefn = ats_write64 },
118
/* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
119
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
120
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
121
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
122
{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
123
.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
124
.access = PL2_RW, .accessfn = access_tda,
125
- .type = ARM_CP_NOP },
126
+ .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
127
/* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
128
* Channel but Linux may try to access this register. The 32-bit
129
* alias is DBGDCCINT.
130
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
127
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
131
.access = PL2_W, .type = ARM_CP_NOP },
128
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
132
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
129
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
133
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
130
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
134
- .access = PL2_W, .type = ARM_CP_NO_RAW,
131
+ .fgt = FGT_TLBIRVAE1IS,
135
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
132
.writefn = tlbi_aa64_rvae1is_write },
136
.writefn = tlbi_aa64_rvae2is_write },
133
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
137
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
134
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
138
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
135
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
139
- .access = PL2_W, .type = ARM_CP_NO_RAW,
136
+ .fgt = FGT_TLBIRVAAE1IS,
140
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
137
.writefn = tlbi_aa64_rvae1is_write },
141
.writefn = tlbi_aa64_rvae2is_write },
138
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
142
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
139
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
143
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
140
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
141
+ .fgt = FGT_TLBIRVALE1IS,
145
.access = PL2_W, .type = ARM_CP_NOP },
142
.writefn = tlbi_aa64_rvae1is_write },
146
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
143
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
147
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
144
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
148
- .access = PL2_W, .type = ARM_CP_NO_RAW,
145
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
149
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
146
+ .fgt = FGT_TLBIRVAALE1IS,
150
.writefn = tlbi_aa64_rvae2is_write },
147
.writefn = tlbi_aa64_rvae1is_write },
151
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
148
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
152
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
149
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
153
- .access = PL2_W, .type = ARM_CP_NO_RAW,
150
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
154
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
151
+ .fgt = FGT_TLBIRVAE1OS,
155
.writefn = tlbi_aa64_rvae2is_write },
152
.writefn = tlbi_aa64_rvae1is_write },
156
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
153
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
157
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
154
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
158
- .access = PL2_W, .type = ARM_CP_NO_RAW,
155
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
159
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
156
+ .fgt = FGT_TLBIRVAAE1OS,
160
.writefn = tlbi_aa64_rvae2_write },
157
.writefn = tlbi_aa64_rvae1is_write },
161
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
158
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
162
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
159
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
163
- .access = PL2_W, .type = ARM_CP_NO_RAW,
160
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
164
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
161
+ .fgt = FGT_TLBIRVALE1OS,
165
.writefn = tlbi_aa64_rvae2_write },
162
.writefn = tlbi_aa64_rvae1is_write },
166
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
163
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
167
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
164
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
165
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
166
+ .fgt = FGT_TLBIRVAALE1OS,
167
.writefn = tlbi_aa64_rvae1is_write },
168
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
169
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
170
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
171
+ .fgt = FGT_TLBIRVAE1,
172
.writefn = tlbi_aa64_rvae1_write },
173
{ .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
174
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
175
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
176
+ .fgt = FGT_TLBIRVAAE1,
177
.writefn = tlbi_aa64_rvae1_write },
178
{ .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
179
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
180
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
181
+ .fgt = FGT_TLBIRVALE1,
182
.writefn = tlbi_aa64_rvae1_write },
183
{ .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
184
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
185
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
186
+ .fgt = FGT_TLBIRVAALE1,
187
.writefn = tlbi_aa64_rvae1_write },
188
{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
189
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
168
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
190
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
191
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
192
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
193
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
194
+ .fgt = FGT_TLBIVMALLE1OS,
195
.writefn = tlbi_aa64_vmalle1is_write },
196
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
197
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
198
+ .fgt = FGT_TLBIVAE1OS,
199
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
200
.writefn = tlbi_aa64_vae1is_write },
201
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
202
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
203
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
204
+ .fgt = FGT_TLBIASIDE1OS,
205
.writefn = tlbi_aa64_vmalle1is_write },
206
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
207
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
208
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
209
+ .fgt = FGT_TLBIVAAE1OS,
210
.writefn = tlbi_aa64_vae1is_write },
211
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
212
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
213
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
214
+ .fgt = FGT_TLBIVALE1OS,
215
.writefn = tlbi_aa64_vae1is_write },
216
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
217
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
218
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
219
+ .fgt = FGT_TLBIVAALE1OS,
169
.writefn = tlbi_aa64_vae1is_write },
220
.writefn = tlbi_aa64_vae1is_write },
170
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
221
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
222
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
172
- .access = PL2_W, .type = ARM_CP_NO_RAW,
173
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
174
.writefn = tlbi_aa64_alle2is_write },
175
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
176
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
177
- .access = PL2_W, .type = ARM_CP_NO_RAW,
178
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
179
.writefn = tlbi_aa64_vae2is_write },
180
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
181
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
182
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
183
.writefn = tlbi_aa64_alle1is_write },
184
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
185
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
186
- .access = PL2_W, .type = ARM_CP_NO_RAW,
187
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
188
.writefn = tlbi_aa64_vae2is_write },
189
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
190
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
191
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
192
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
193
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
194
.access = PL2_RW, .accessfn = access_el3_aa32ns,
195
- .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
196
+ .resetvalue = cpu->midr,
197
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
198
.fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
199
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
200
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
201
.access = PL2_RW, .resetvalue = cpu->midr,
202
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
203
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
204
{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
205
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
206
.access = PL2_RW, .accessfn = access_el3_aa32ns,
207
- .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
208
+ .resetvalue = vmpidr_def,
209
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
210
.fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
211
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
212
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
213
- .access = PL2_RW,
214
- .resetvalue = vmpidr_def,
215
+ .access = PL2_RW, .resetvalue = vmpidr_def,
216
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
217
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
218
};
219
define_arm_cp_regs(cpu, vpidr_regs);
220
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
221
int crm, int opc1, int opc2,
222
const char *name)
223
{
224
+ CPUARMState *env = &cpu->env;
225
uint32_t key;
226
ARMCPRegInfo *r2;
227
bool is64 = r->type & ARM_CP_64BIT;
228
bool ns = secstate & ARM_CP_SECSTATE_NS;
229
int cp = r->cp;
230
- bool isbanked;
231
size_t name_len;
232
+ bool make_const;
233
234
switch (state) {
235
case ARM_CP_STATE_AA32:
236
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
237
}
238
}
239
240
+ /*
241
+ * Eliminate registers that are not present because the EL is missing.
242
+ * Doing this here makes it easier to put all registers for a given
243
+ * feature into the same ARMCPRegInfo array and define them all at once.
244
+ */
245
+ make_const = false;
246
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
247
+ /*
248
+ * An EL2 register without EL2 but with EL3 is (usually) RES0.
249
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
250
+ */
251
+ int min_el = ctz32(r->access) / 2;
252
+ if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
253
+ if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
254
+ return;
255
+ }
256
+ make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
257
+ }
258
+ } else {
259
+ CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
260
+ ? PL2_RW : PL1_RW);
261
+ if ((r->access & max_el) == 0) {
262
+ return;
263
+ }
264
+ }
265
+
266
/* Combine cpreg and name into one allocation. */
267
name_len = strlen(name) + 1;
268
r2 = g_malloc(sizeof(*r2) + name_len);
269
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
270
r2->opaque = opaque;
271
}
272
273
- isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
274
- if (isbanked) {
275
+ if (make_const) {
276
+ /* This should not have been a very special register to begin. */
277
+ int old_special = r2->type & ARM_CP_SPECIAL_MASK;
278
+ assert(old_special == 0 || old_special == ARM_CP_NOP);
279
/*
280
- * Register is banked (using both entries in array).
281
- * Overwriting fieldoffset as the array is only used to define
282
- * banked registers but later only fieldoffset is used.
283
+ * Set the special function to CONST, retaining the other flags.
284
+ * This is important for e.g. ARM_CP_SVE so that we still
285
+ * take the SVE trap if CPTR_EL3.EZ == 0.
286
*/
287
- r2->fieldoffset = r->bank_fieldoffsets[ns];
288
- }
289
+ r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
290
+ /*
291
+ * Usually, these registers become RES0, but there are a few
292
+ * special cases like VPIDR_EL2 which have a constant non-zero
293
+ * value with writes ignored.
294
+ */
295
+ if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
296
+ r2->resetvalue = 0;
297
+ }
298
+ /*
299
+ * ARM_CP_CONST has precedence, so removing the callbacks and
300
+ * offsets are not strictly necessary, but it is potentially
301
+ * less confusing to debug later.
302
+ */
303
+ r2->readfn = NULL;
304
+ r2->writefn = NULL;
305
+ r2->raw_readfn = NULL;
306
+ r2->raw_writefn = NULL;
307
+ r2->resetfn = NULL;
308
+ r2->fieldoffset = 0;
309
+ r2->bank_fieldoffsets[0] = 0;
310
+ r2->bank_fieldoffsets[1] = 0;
311
+ } else {
312
+ bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
313
314
- if (state == ARM_CP_STATE_AA32) {
315
if (isbanked) {
316
/*
317
- * If the register is banked then we don't need to migrate or
318
- * reset the 32-bit instance in certain cases:
319
- *
320
- * 1) If the register has both 32-bit and 64-bit instances then we
321
- * can count on the 64-bit instance taking care of the
322
- * non-secure bank.
323
- * 2) If ARMv8 is enabled then we can count on a 64-bit version
324
- * taking care of the secure bank. This requires that separate
325
- * 32 and 64-bit definitions are provided.
326
+ * Register is banked (using both entries in array).
327
+ * Overwriting fieldoffset as the array is only used to define
328
+ * banked registers but later only fieldoffset is used.
329
*/
330
- if ((r->state == ARM_CP_STATE_BOTH && ns) ||
331
- (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
332
+ r2->fieldoffset = r->bank_fieldoffsets[ns];
333
+ }
334
+ if (state == ARM_CP_STATE_AA32) {
335
+ if (isbanked) {
336
+ /*
337
+ * If the register is banked then we don't need to migrate or
338
+ * reset the 32-bit instance in certain cases:
339
+ *
340
+ * 1) If the register has both 32-bit and 64-bit instances
341
+ * then we can count on the 64-bit instance taking care
342
+ * of the non-secure bank.
343
+ * 2) If ARMv8 is enabled then we can count on a 64-bit
344
+ * version taking care of the secure bank. This requires
345
+ * that separate 32 and 64-bit definitions are provided.
346
+ */
347
+ if ((r->state == ARM_CP_STATE_BOTH && ns) ||
348
+ (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
349
+ r2->type |= ARM_CP_ALIAS;
350
+ }
351
+ } else if ((secstate != r->secure) && !ns) {
352
+ /*
353
+ * The register is not banked so we only want to allow
354
+ * migration of the non-secure instance.
355
+ */
356
r2->type |= ARM_CP_ALIAS;
357
}
358
- } else if ((secstate != r->secure) && !ns) {
359
- /*
360
- * The register is not banked so we only want to allow migration
361
- * of the non-secure instance.
362
- */
363
- r2->type |= ARM_CP_ALIAS;
364
- }
365
366
- if (HOST_BIG_ENDIAN &&
367
- r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
368
- r2->fieldoffset += sizeof(uint32_t);
369
+ if (HOST_BIG_ENDIAN &&
370
+ r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
371
+ r2->fieldoffset += sizeof(uint32_t);
372
+ }
373
}
374
}
375
376
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
377
* multiple times. Special registers (ie NOP/WFI) are
378
* never migratable and not even raw-accessible.
379
*/
380
- if (r->type & ARM_CP_SPECIAL_MASK) {
381
+ if (r2->type & ARM_CP_SPECIAL_MASK) {
382
r2->type |= ARM_CP_NO_RAW;
383
}
384
if (((r->crm == CP_ANY) && crm != 0) ||
385
--
223
--
386
2.25.1
224
2.34.1
diff view generated by jsdifflib
[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
[PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Mark up the sysreg definitions for the system instructions
2
trapped by HFGITR bits 48..63.
2
3
3
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
4
Some of these bits are for trapping instructions which are
4
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
5
not in the system instruction encoding (i.e. which are
5
while registering for v8.
6
not handled by the ARMCPRegInfo mechanism):
7
* ERET, ERETAA, ERETAB
8
* SVC
6
9
7
This is a behavior change for v7 cpus with Security Extensions and
10
We will have to handle those separately and manually.
8
without Virtualization Extensions, in that the virtualization cpregs
9
are now correctly not present. This would be a migration compatibility
10
break, except that we have an existing bug in which migration of 32-bit
11
cpus with Security Extensions enabled does not work.
12
11
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Fuad Tabba <tabba@google.com>
15
Message-id: 20230130182459.3309057-20-peter.maydell@linaro.org
16
Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org
17
---
17
---
18
target/arm/helper.c | 158 ++++----------------------------------------
18
target/arm/cpregs.h | 4 ++++
19
1 file changed, 13 insertions(+), 145 deletions(-)
19
target/arm/helper.c | 9 +++++++++
20
2 files changed, 13 insertions(+)
20
21
22
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpregs.h
25
+++ b/target/arm/cpregs.h
26
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
27
DO_BIT(HFGITR, TLBIVAAE1),
28
DO_BIT(HFGITR, TLBIVALE1),
29
DO_BIT(HFGITR, TLBIVAALE1),
30
+ DO_BIT(HFGITR, CFPRCTX),
31
+ DO_BIT(HFGITR, DVPRCTX),
32
+ DO_BIT(HFGITR, CPPRCTX),
33
+ DO_BIT(HFGITR, DCCVAC),
34
} FGTBit;
35
36
#undef DO_BIT
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
39
--- a/target/arm/helper.c
24
+++ b/target/arm/helper.c
40
+++ b/target/arm/helper.c
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
41
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
26
.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
42
{ .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
43
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
44
.access = PL0_W, .type = ARM_CP_NOP,
45
+ .fgt = FGT_DCCVAC,
46
.accessfn = aa64_cacheop_poc_access },
47
{ .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
48
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
49
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
50
{ .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
51
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
52
.type = ARM_CP_NOP, .access = PL0_W,
53
+ .fgt = FGT_DCCVAC,
54
.accessfn = aa64_cacheop_poc_access },
55
{ .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
56
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
57
.type = ARM_CP_NOP, .access = PL0_W,
58
+ .fgt = FGT_DCCVAC,
59
.accessfn = aa64_cacheop_poc_access },
60
{ .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
61
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
62
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
63
static const ARMCPRegInfo predinv_reginfo[] = {
64
{ .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
65
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
66
+ .fgt = FGT_CFPRCTX,
67
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
68
{ .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
69
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
70
+ .fgt = FGT_DVPRCTX,
71
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
72
{ .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
73
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
74
+ .fgt = FGT_CPPRCTX,
75
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
76
/*
77
* Note the AArch32 opcodes have a different OPC1.
78
*/
79
{ .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
80
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
81
+ .fgt = FGT_CFPRCTX,
82
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
83
{ .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
84
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
85
+ .fgt = FGT_DVPRCTX,
86
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
87
{ .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
88
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
89
+ .fgt = FGT_CPPRCTX,
90
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
27
};
91
};
28
92
29
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
30
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
31
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
32
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
33
- .access = PL2_RW,
34
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
35
- { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
36
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
37
- .access = PL2_RW,
38
- .type = ARM_CP_CONST, .resetvalue = 0 },
39
- { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
40
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
41
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
- { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
43
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
44
- .access = PL2_RW,
45
- .type = ARM_CP_CONST, .resetvalue = 0 },
46
- { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
47
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
48
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49
- { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
50
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
51
- .access = PL2_RW, .type = ARM_CP_CONST,
52
- .resetvalue = 0 },
53
- { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
54
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
55
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
56
- { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
57
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
58
- .access = PL2_RW, .type = ARM_CP_CONST,
59
- .resetvalue = 0 },
60
- { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
61
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
62
- .access = PL2_RW, .type = ARM_CP_CONST,
63
- .resetvalue = 0 },
64
- { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
65
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
66
- .access = PL2_RW, .type = ARM_CP_CONST,
67
- .resetvalue = 0 },
68
- { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
69
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
70
- .access = PL2_RW, .type = ARM_CP_CONST,
71
- .resetvalue = 0 },
72
- { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
73
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
74
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
- { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
76
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
77
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
78
- .type = ARM_CP_CONST, .resetvalue = 0 },
79
- { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
80
- .cp = 15, .opc1 = 6, .crm = 2,
81
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
82
- .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
83
- { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
84
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
85
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
86
- { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
87
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
88
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
89
- { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
90
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
91
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
92
- { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
93
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
94
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
95
- { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
96
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
97
- .resetvalue = 0 },
98
- { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
99
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
100
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
101
- { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
102
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
103
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
104
- { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
105
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
106
- .resetvalue = 0 },
107
- { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
108
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
109
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
110
- { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
111
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
112
- .resetvalue = 0 },
113
- { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
114
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
115
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
116
- { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
117
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
118
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
119
- { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
120
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
121
- .access = PL2_RW, .accessfn = access_tda,
122
- .type = ARM_CP_CONST, .resetvalue = 0 },
123
- { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
124
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
125
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
126
- .type = ARM_CP_CONST, .resetvalue = 0 },
127
- { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
128
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
129
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
130
- { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
131
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
132
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
133
- { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
134
- .type = ARM_CP_CONST,
135
- .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
136
- .access = PL2_RW, .resetvalue = 0 },
137
-};
138
-
139
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
140
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
141
- { .name = "HCR2", .state = ARM_CP_STATE_AA32,
142
- .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
143
- .access = PL2_RW,
144
- .type = ARM_CP_CONST, .resetvalue = 0 },
145
-};
146
-
147
static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
148
{
149
ARMCPU *cpu = env_archcpu(env);
150
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
151
define_arm_cp_regs(cpu, v8_idregs);
152
define_arm_cp_regs(cpu, v8_cp_reginfo);
153
}
154
- if (arm_feature(env, ARM_FEATURE_EL2)) {
155
+
156
+ /*
157
+ * Register the base EL2 cpregs.
158
+ * Pre v8, these registers are implemented only as part of the
159
+ * Virtualization Extensions (EL2 present). Beginning with v8,
160
+ * if EL2 is missing but EL3 is enabled, mostly these become
161
+ * RES0 from EL3, with some specific exceptions.
162
+ */
163
+ if (arm_feature(env, ARM_FEATURE_EL2)
164
+ || (arm_feature(env, ARM_FEATURE_EL3)
165
+ && arm_feature(env, ARM_FEATURE_V8))) {
166
uint64_t vmpidr_def = mpidr_read_val(env);
167
ARMCPRegInfo vpidr_regs[] = {
168
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
169
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
170
};
171
define_one_arm_cp_reg(cpu, &rvbar);
172
}
173
- } else {
174
- /* If EL2 is missing but higher ELs are enabled, we need to
175
- * register the no_el2 reginfos.
176
- */
177
- if (arm_feature(env, ARM_FEATURE_EL3)) {
178
- /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
179
- * of MIDR_EL1 and MPIDR_EL1.
180
- */
181
- ARMCPRegInfo vpidr_regs[] = {
182
- { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
183
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
184
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
185
- .type = ARM_CP_CONST, .resetvalue = cpu->midr,
186
- .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
187
- { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
188
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
189
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
190
- .type = ARM_CP_NO_RAW,
191
- .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
192
- };
193
- define_arm_cp_regs(cpu, vpidr_regs);
194
- define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
195
- if (arm_feature(env, ARM_FEATURE_V8)) {
196
- define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
197
- }
198
- }
199
}
200
+
201
+ /* Register the base EL3 cpregs. */
202
if (arm_feature(env, ARM_FEATURE_EL3)) {
203
define_arm_cp_regs(cpu, el3_cp_reginfo);
204
ARMCPRegInfo el3_regs[] = {
205
--
93
--
206
2.25.1
94
2.34.1
diff view generated by jsdifflib
[PULL 16/32] target/arm: Implement virtual SError exceptions
[PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the HFGITR_EL2.ERET fine-grained trap. This traps
2
execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is
3
reported with a syndrome value of 0x1a.
2
4
3
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
5
The trap must take precedence over a possible pointer-authentication
4
and are routed to EL1 just like other virtual exceptions.
6
trap for ERETAA and ERETAB.
5
7
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Fuad Tabba <tabba@google.com>
11
Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org
12
Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org
10
---
13
---
11
target/arm/cpu.h | 2 ++
14
target/arm/cpu.h | 1 +
12
target/arm/internals.h | 8 ++++++++
15
target/arm/syndrome.h | 10 ++++++++++
13
target/arm/syndrome.h | 5 +++++
16
target/arm/translate.h | 2 ++
14
target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++-
17
target/arm/helper.c | 3 +++
15
target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++-
18
target/arm/translate-a64.c | 10 ++++++++++
16
5 files changed, 91 insertions(+), 2 deletions(-)
19
5 files changed, 26 insertions(+)
17
20
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
23
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
23
#define EXCP_LSERR 21 /* v8M LSERR SecureFault */
26
FIELD(TBFLAG_A64, SVL, 24, 4)
24
#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
27
/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
25
#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
28
FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
26
+#define EXCP_VSERR 24
29
+FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
27
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
30
28
31
/*
29
#define ARMV7M_EXCP_RESET 1
32
* Helpers for using the above.
30
@@ -XXX,XX +XXX,XX @@ enum {
31
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
32
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
33
#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
34
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
35
36
/* The usual mapping for an AArch64 system register to its AArch32
37
* counterpart is for the 32 bit world to have access to the lower
38
diff --git a/target/arm/internals.h b/target/arm/internals.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/internals.h
41
+++ b/target/arm/internals.h
42
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
43
*/
44
void arm_cpu_update_vfiq(ARMCPU *cpu);
45
46
+/**
47
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
48
+ *
49
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
50
+ * following a change to the HCR_EL2.VSE bit.
51
+ */
52
+void arm_cpu_update_vserr(ARMCPU *cpu);
53
+
54
/**
55
* arm_mmu_idx_el:
56
* @env: The cpu environment
57
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
33
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
58
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/syndrome.h
35
--- a/target/arm/syndrome.h
60
+++ b/target/arm/syndrome.h
36
+++ b/target/arm/syndrome.h
61
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
37
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
62
return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
38
EC_AA64_SMC = 0x17,
39
EC_SYSTEMREGISTERTRAP = 0x18,
40
EC_SVEACCESSTRAP = 0x19,
41
+ EC_ERETTRAP = 0x1a,
42
EC_SMETRAP = 0x1d,
43
EC_INSNABORT = 0x20,
44
EC_INSNABORT_SAME_EL = 0x21,
45
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void)
46
return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
63
}
47
}
64
48
65
+static inline uint32_t syn_serror(uint32_t extra)
49
+/*
50
+ * eret_op is bits [1:0] of the ERET instruction, so:
51
+ * 0 for ERET, 2 for ERETAA, 3 for ERETAB.
52
+ */
53
+static inline uint32_t syn_erettrap(int eret_op)
66
+{
54
+{
67
+ return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
55
+ return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op;
68
+}
56
+}
69
+
57
+
70
#endif /* TARGET_ARM_SYNDROME_H */
58
static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
71
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
59
{
60
return (EC_SMETRAP << ARM_EL_EC_SHIFT)
61
diff --git a/target/arm/translate.h b/target/arm/translate.h
72
index XXXXXXX..XXXXXXX 100644
62
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/cpu.c
63
--- a/target/arm/translate.h
74
+++ b/target/arm/cpu.c
64
+++ b/target/arm/translate.h
75
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
65
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
76
return (cpu->power_state != PSCI_OFF)
66
bool mve_no_pred;
77
&& cs->interrupt_request &
67
/* True if fine-grained traps are active */
78
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
68
bool fgt_active;
79
- | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
69
+ /* True if fine-grained trap on ERET is enabled */
80
+ | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
70
+ bool fgt_eret;
81
| CPU_INTERRUPT_EXITTB);
71
/*
82
}
72
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
83
73
* < 0, set by the current instruction.
84
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
85
return false;
86
}
87
return !(env->daif & PSTATE_I);
88
+ case EXCP_VSERR:
89
+ if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
90
+ /* VIRQs are only taken when hypervized. */
91
+ return false;
92
+ }
93
+ return !(env->daif & PSTATE_A);
94
default:
95
g_assert_not_reached();
96
}
97
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
98
goto found;
99
}
100
}
101
+ if (interrupt_request & CPU_INTERRUPT_VSERR) {
102
+ excp_idx = EXCP_VSERR;
103
+ target_el = 1;
104
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
105
+ cur_el, secure, hcr_el2)) {
106
+ /* Taking a virtual abort clears HCR_EL2.VSE */
107
+ env->cp15.hcr_el2 &= ~HCR_VSE;
108
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
109
+ goto found;
110
+ }
111
+ }
112
return false;
113
114
found:
115
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
116
}
117
}
118
119
+void arm_cpu_update_vserr(ARMCPU *cpu)
120
+{
121
+ /*
122
+ * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
123
+ */
124
+ CPUARMState *env = &cpu->env;
125
+ CPUState *cs = CPU(cpu);
126
+
127
+ bool new_state = env->cp15.hcr_el2 & HCR_VSE;
128
+
129
+ if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
130
+ if (new_state) {
131
+ cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
132
+ } else {
133
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
134
+ }
135
+ }
136
+}
137
+
138
#ifndef CONFIG_USER_ONLY
139
static void arm_cpu_set_irq(void *opaque, int irq, int level)
140
{
141
diff --git a/target/arm/helper.c b/target/arm/helper.c
74
diff --git a/target/arm/helper.c b/target/arm/helper.c
142
index XXXXXXX..XXXXXXX 100644
75
index XXXXXXX..XXXXXXX 100644
143
--- a/target/arm/helper.c
76
--- a/target/arm/helper.c
144
+++ b/target/arm/helper.c
77
+++ b/target/arm/helper.c
145
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
78
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
146
}
79
80
if (arm_fgt_active(env, el)) {
81
DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
82
+ if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
83
+ DP_TBFLAG_A64(flags, FGT_ERET, 1);
84
+ }
147
}
85
}
148
86
149
- /* External aborts are not possible in QEMU so A bit is always clear */
87
if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
150
+ if (hcr_el2 & HCR_AMO) {
88
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
151
+ if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
89
index XXXXXXX..XXXXXXX 100644
152
+ ret |= CPSR_A;
90
--- a/target/arm/translate-a64.c
153
+ }
91
+++ b/target/arm/translate-a64.c
154
+ }
92
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
155
+
93
if (op4 != 0) {
156
return ret;
94
goto do_unallocated;
157
}
95
}
158
96
+ if (s->fgt_eret) {
159
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
97
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
160
g_assert(qemu_mutex_iothread_locked());
98
+ return;
161
arm_cpu_update_virq(cpu);
162
arm_cpu_update_vfiq(cpu);
163
+ arm_cpu_update_vserr(cpu);
164
}
165
166
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
167
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
168
[EXCP_LSERR] = "v8M LSERR UsageFault",
169
[EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
170
[EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
171
+ [EXCP_VSERR] = "Virtual SERR",
172
};
173
174
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
175
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
176
mask = CPSR_A | CPSR_I | CPSR_F;
177
offset = 4;
178
break;
179
+ case EXCP_VSERR:
180
+ {
181
+ /*
182
+ * Note that this is reported as a data abort, but the DFAR
183
+ * has an UNKNOWN value. Construct the SError syndrome from
184
+ * AET and ExT fields.
185
+ */
186
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
187
+
188
+ if (extended_addresses_enabled(env)) {
189
+ env->exception.fsr = arm_fi_to_lfsc(&fi);
190
+ } else {
191
+ env->exception.fsr = arm_fi_to_sfsc(&fi);
192
+ }
99
+ }
193
+ env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
100
dst = tcg_temp_new_i64();
194
+ A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
101
tcg_gen_ld_i64(dst, cpu_env,
195
+ qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
102
offsetof(CPUARMState, elr_el[s->current_el]));
196
+ env->exception.fsr);
103
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
197
+
104
if (rn != 0x1f || op4 != 0x1f) {
198
+ new_mode = ARM_CPU_MODE_ABT;
105
goto do_unallocated;
199
+ addr = 0x10;
106
}
200
+ mask = CPSR_A | CPSR_I;
107
+ /* The FGT trap takes precedence over an auth trap. */
201
+ offset = 8;
108
+ if (s->fgt_eret) {
202
+ }
109
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
203
+ break;
110
+ return;
204
case EXCP_SMC:
111
+ }
205
new_mode = ARM_CPU_MODE_MON;
112
dst = tcg_temp_new_i64();
206
addr = 0x08;
113
tcg_gen_ld_i64(dst, cpu_env,
207
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
114
offsetof(CPUARMState, elr_el[s->current_el]));
208
case EXCP_VFIQ:
115
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
209
addr += 0x100;
116
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
210
break;
117
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
211
+ case EXCP_VSERR:
118
dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
212
+ addr += 0x180;
119
+ dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
213
+ /* Construct the SError syndrome from IDS and ISS fields. */
120
dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
214
+ env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
121
dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
215
+ env->cp15.esr_el[new_el] = env->exception.syndrome;
122
dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
216
+ break;
217
default:
218
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
219
}
220
--
123
--
221
2.25.1
124
2.34.1
diff view generated by jsdifflib
[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
[PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
2
These trap execution of the SVC instruction from AArch32 and AArch64.
3
(As usual, AArch32 can only trap from EL0, as fine grained traps are
4
disabled with an AArch32 EL1.)
2
5
3
This extension concerns not merging memory access, which TCG does
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
not implement. Thus we can trivially enable this feature.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Add a comment to handle_hint for the DGH instruction, but no code.
8
Tested-by: Fuad Tabba <tabba@google.com>
9
Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
10
Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
11
---
12
target/arm/cpu.h | 1 +
13
target/arm/translate.h | 2 ++
14
target/arm/helper.c | 20 ++++++++++++++++++++
15
target/arm/translate-a64.c | 9 ++++++++-
16
target/arm/translate.c | 12 +++++++++---
17
5 files changed, 40 insertions(+), 4 deletions(-)
6
18
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 1 +
13
target/arm/cpu64.c | 1 +
14
target/arm/translate-a64.c | 1 +
15
3 files changed, 3 insertions(+)
16
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/arm/emulation.rst
21
--- a/target/arm/cpu.h
20
+++ b/docs/system/arm/emulation.rst
22
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
23
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
24
FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
25
FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
24
- FEAT_CSV3 (Cache speculation variant 3)
26
FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
25
+- FEAT_DGH (Data gathering hint)
27
+FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
26
- FEAT_DIT (Data Independent Timing instructions)
28
27
- FEAT_DPB (DC CVAP instruction)
29
/*
28
- FEAT_Debugv8p2 (Debug changes for v8.2)
30
* Bit usage when in AArch32 state, both A- and M-profile.
29
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
31
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu64.c
33
--- a/target/arm/translate.h
32
+++ b/target/arm/cpu64.c
34
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
35
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
34
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
36
bool fgt_active;
35
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
37
/* True if fine-grained trap on ERET is enabled */
36
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
38
bool fgt_eret;
37
+ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
39
+ /* True if fine-grained trap on SVC is enabled */
38
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
40
+ bool fgt_svc;
39
cpu->isar.id_aa64isar1 = t;
41
/*
40
42
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
43
* < 0, set by the current instruction.
44
diff --git a/target/arm/helper.c b/target/arm/helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/helper.c
47
+++ b/target/arm/helper.c
48
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
49
return arm_mmu_idx_el(env, arm_current_el(env));
50
}
51
52
+static inline bool fgt_svc(CPUARMState *env, int el)
53
+{
54
+ /*
55
+ * Assuming fine-grained-traps are active, return true if we
56
+ * should be trapping on SVC instructions. Only AArch64 can
57
+ * trap on an SVC at EL1, but we don't need to special-case this
58
+ * because if this is AArch32 EL1 then arm_fgt_active() is false.
59
+ * We also know el is 0 or 1.
60
+ */
61
+ return el == 0 ?
62
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
63
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
64
+}
65
+
66
static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
67
ARMMMUIdx mmu_idx,
68
CPUARMTBFlags flags)
69
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
70
71
if (arm_fgt_active(env, el)) {
72
DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
73
+ if (fgt_svc(env, el)) {
74
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
75
+ }
76
}
77
78
if (env->uncached_cpsr & CPSR_IL) {
79
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
80
if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
81
DP_TBFLAG_A64(flags, FGT_ERET, 1);
82
}
83
+ if (fgt_svc(env, el)) {
84
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
85
+ }
86
}
87
88
if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
41
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
89
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
42
index XXXXXXX..XXXXXXX 100644
90
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/translate-a64.c
91
--- a/target/arm/translate-a64.c
44
+++ b/target/arm/translate-a64.c
92
+++ b/target/arm/translate-a64.c
45
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
93
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
46
break;
94
int opc = extract32(insn, 21, 3);
47
case 0b00100: /* SEV */
95
int op2_ll = extract32(insn, 0, 5);
48
case 0b00101: /* SEVL */
96
int imm16 = extract32(insn, 5, 16);
49
+ case 0b00110: /* DGH */
97
+ uint32_t syndrome;
50
/* we treat all as NOP at least for now */
98
51
break;
99
switch (opc) {
52
case 0b00111: /* XPACLRI */
100
case 0:
101
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
102
*/
103
switch (op2_ll) {
104
case 1: /* SVC */
105
+ syndrome = syn_aa64_svc(imm16);
106
+ if (s->fgt_svc) {
107
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
108
+ break;
109
+ }
110
gen_ss_advance(s);
111
- gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16));
112
+ gen_exception_insn(s, 4, EXCP_SWI, syndrome);
113
break;
114
case 2: /* HVC */
115
if (s->current_el == 0) {
116
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
117
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
118
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
119
dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
120
+ dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
121
dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
122
dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
123
dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
124
diff --git a/target/arm/translate.c b/target/arm/translate.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/target/arm/translate.c
127
+++ b/target/arm/translate.c
128
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
129
(a->imm == semihost_imm)) {
130
gen_exception_internal_insn(s, EXCP_SEMIHOST);
131
} else {
132
- gen_update_pc(s, curr_insn_len(s));
133
- s->svc_imm = a->imm;
134
- s->base.is_jmp = DISAS_SWI;
135
+ if (s->fgt_svc) {
136
+ uint32_t syndrome = syn_aa32_svc(a->imm, s->thumb);
137
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
138
+ } else {
139
+ gen_update_pc(s, curr_insn_len(s));
140
+ s->svc_imm = a->imm;
141
+ s->base.is_jmp = DISAS_SWI;
142
+ }
143
}
144
return true;
145
}
146
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
147
dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
148
dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
149
dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
150
+ dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
151
152
if (arm_feature(env, ARM_FEATURE_M)) {
153
dc->vfp_enabled = 1;
53
--
154
--
54
2.25.1
155
2.34.1
diff view generated by jsdifflib
[PULL 14/32] target/arm: Add minimal RAS registers
[PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
1
From: Richard Henderson <richard.henderson@linaro.org>
1
FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
2
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
3
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
4
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
5
AArch32 equivalents). This trapping is independent of whether
6
fine-grained traps are enabled or not.
2
7
3
Add only the system registers required to implement zero error
8
Implement these extra traps. (We don't implement DBGDTR_EL0,
4
records. This means that all values for ERRSELR are out of range,
9
DBGDTRRX_EL0 and DBGDTRTX_EL0.)
5
which means that it and all of the indexed error record registers
6
need not be implemented.
7
10
8
Add the EL2 registers required for injecting virtual SError.
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Fuad Tabba <tabba@google.com>
14
Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org
15
Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org
16
---
17
target/arm/debug_helper.c | 35 +++++++++++++++++++++++++++++++----
18
1 file changed, 31 insertions(+), 4 deletions(-)
9
19
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/cpu.h | 5 +++
16
target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
17
2 files changed, 89 insertions(+)
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
22
--- a/target/arm/debug_helper.c
22
+++ b/target/arm/cpu.h
23
+++ b/target/arm/debug_helper.c
23
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
24
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
24
uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
25
return CP_ACCESS_OK;
25
uint64_t gcr_el1;
26
}
26
uint64_t rgsr_el1;
27
+
28
+ /* Minimal RAS registers */
29
+ uint64_t disr_el1;
30
+ uint64_t vdisr_el2;
31
+ uint64_t vsesr_el2;
32
} cp15;
33
34
struct {
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper.c
38
+++ b/target/arm/helper.c
39
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
40
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
41
};
42
27
43
+/*
28
+/*
44
+ * Check for traps to RAS registers, which are controlled
29
+ * Check for traps to Debug Comms Channel registers. If FEAT_FGT
45
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
30
+ * is implemented then these are controlled by MDCR_EL2.TDCC for
31
+ * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
32
+ * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
46
+ */
33
+ */
47
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
34
+static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
48
+ bool isread)
35
+ bool isread)
49
+{
36
+{
50
+ int el = arm_current_el(env);
37
+ int el = arm_current_el(env);
38
+ uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
39
+ bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
40
+ (arm_hcr_el2_eff(env) & HCR_TGE);
41
+ bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
42
+ (mdcr_el2 & MDCR_TDCC);
43
+ bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
44
+ (env->cp15.mdcr_el3 & MDCR_TDCC);
51
+
45
+
52
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
46
+ if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
53
+ return CP_ACCESS_TRAP_EL2;
47
+ return CP_ACCESS_TRAP_EL2;
54
+ }
48
+ }
55
+ if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
49
+ if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
56
+ return CP_ACCESS_TRAP_EL3;
50
+ return CP_ACCESS_TRAP_EL3;
57
+ }
51
+ }
58
+ return CP_ACCESS_OK;
52
+ return CP_ACCESS_OK;
59
+}
53
+}
60
+
54
+
61
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
55
static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
62
+{
56
uint64_t value)
63
+ int el = arm_current_el(env);
57
{
64
+
58
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
65
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
59
*/
66
+ return env->cp15.vdisr_el2;
60
{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
67
+ }
61
.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
68
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
62
- .access = PL0_R, .accessfn = access_tda,
69
+ return 0; /* RAZ/WI */
63
+ .access = PL0_R, .accessfn = access_tdcc,
70
+ }
64
.type = ARM_CP_CONST, .resetvalue = 0 },
71
+ return env->cp15.disr_el1;
65
/*
72
+}
66
* OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
73
+
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
74
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
68
*/
75
+{
69
{ .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
76
+ int el = arm_current_el(env);
70
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
77
+
71
- .access = PL1_RW, .accessfn = access_tda,
78
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
72
+ .access = PL1_RW, .accessfn = access_tdcc,
79
+ env->cp15.vdisr_el2 = val;
73
.type = ARM_CP_CONST, .resetvalue = 0 },
80
+ return;
74
{ .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
81
+ }
75
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
82
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
76
- .access = PL1_RW, .accessfn = access_tda,
83
+ return; /* RAZ/WI */
77
+ .access = PL1_RW, .accessfn = access_tdcc,
84
+ }
78
.type = ARM_CP_CONST, .resetvalue = 0 },
85
+ env->cp15.disr_el1 = val;
79
/*
86
+}
80
* OSECCR_EL1 provides a mechanism for an operating system
87
+
81
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
88
+/*
82
*/
89
+ * Minimal RAS implementation with no Error Records.
83
{ .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
90
+ * Which means that all of the Error Record registers:
84
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
91
+ * ERXADDR_EL1
85
- .access = PL1_RW, .accessfn = access_tda,
92
+ * ERXCTLR_EL1
86
+ .access = PL1_RW, .accessfn = access_tdcc,
93
+ * ERXFR_EL1
87
.type = ARM_CP_NOP },
94
+ * ERXMISC0_EL1
88
/*
95
+ * ERXMISC1_EL1
89
* Dummy DBGCLAIM registers.
96
+ * ERXMISC2_EL1
97
+ * ERXMISC3_EL1
98
+ * ERXPFGCDN_EL1 (RASv1p1)
99
+ * ERXPFGCTL_EL1 (RASv1p1)
100
+ * ERXPFGF_EL1 (RASv1p1)
101
+ * ERXSTATUS_EL1
102
+ * and
103
+ * ERRSELR_EL1
104
+ * may generate UNDEFINED, which is the effect we get by not
105
+ * listing them at all.
106
+ */
107
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
108
+ { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
109
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
110
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
111
+ .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
112
+ { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
113
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
114
+ .access = PL1_R, .accessfn = access_terr,
115
+ .type = ARM_CP_CONST, .resetvalue = 0 },
116
+ { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
117
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
118
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
119
+ { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
120
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
121
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
122
+};
123
+
124
/* Return the exception level to which exceptions should be taken
125
* via SVEAccessTrap. If an exception should be routed through
126
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
127
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
128
if (cpu_isar_feature(aa64_ssbs, cpu)) {
129
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
130
}
131
+ if (cpu_isar_feature(any_ras, cpu)) {
132
+ define_arm_cp_regs(cpu, minimal_ras_reginfo);
133
+ }
134
135
if (cpu_isar_feature(aa64_vh, cpu) ||
136
cpu_isar_feature(aa64_debugv8p2, cpu)) {
137
--
90
--
138
2.25.1
91
2.34.1
diff view generated by jsdifflib
[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
[PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max'
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Update the ID registers for TCG's '-cpu max' to report the
2
presence of FEAT_FGT Fine-Grained Traps support.
2
3
3
This feature is AArch64 only, and applies to physical SErrors,
4
which QEMU does not implement, thus the feature is a nop.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Fuad Tabba <tabba@google.com>
7
Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org
8
Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org
10
---
9
---
11
docs/system/arm/emulation.rst | 1 +
10
docs/system/arm/emulation.rst | 1 +
12
target/arm/cpu64.c | 1 +
11
target/arm/cpu64.c | 1 +
13
2 files changed, 2 insertions(+)
12
2 files changed, 2 insertions(+)
14
13
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
16
--- a/docs/system/arm/emulation.rst
18
+++ b/docs/system/arm/emulation.rst
17
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
19
- FEAT_ETS (Enhanced Translation Synchronization)
21
- FEAT_HPDS (Hierarchical permission disables)
20
- FEAT_EVT (Enhanced Virtualization Traps)
22
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
21
- FEAT_FCMA (Floating-point complex number instructions)
23
+- FEAT_IESB (Implicit error synchronization event)
22
+- FEAT_FGT (Fine-Grained Traps)
24
- FEAT_JSCVT (JavaScript conversion instructions)
23
- FEAT_FHM (Floating-point half-precision multiplication instructions)
25
- FEAT_LOR (Limited ordering regions)
24
- FEAT_FP16 (Half-precision floating-point data processing)
26
- FEAT_LPA (Large Physical Address space)
25
- FEAT_FRINTTS (Floating-point to integer instructions)
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
28
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu64.c
28
--- a/target/arm/cpu64.c
30
+++ b/target/arm/cpu64.c
29
+++ b/target/arm/cpu64.c
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
30
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
32
t = cpu->isar.id_aa64mmfr2;
31
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
33
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
32
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
34
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
33
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
35
+ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
34
+ t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
36
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
35
cpu->isar.id_aa64mmfr0 = t;
37
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
36
38
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
37
t = cpu->isar.id_aa64mmfr1;
39
--
38
--
40
2.25.1
39
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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