1 | target-arm queue: the big stuff here is the final part of | 1 | I don't have anything else queued up at the moment, so this is just |
---|---|---|---|
2 | rth's patches for Cortex-A76 and Neoverse-N1 support; | 2 | Richard's SME patches. |
3 | also present are Gavin's NUMA series and a few other things. | ||
4 | 3 | ||
5 | thanks | ||
6 | -- PMM | 4 | -- PMM |
7 | 5 | ||
8 | The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b: | 6 | The following changes since commit 63b38f6c85acd312c2cab68554abf33adf4ee2b3: |
9 | 7 | ||
10 | Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500) | 8 | Merge tag 'pull-target-arm-20220707' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-07-08 06:17:11 +0530) |
11 | 9 | ||
12 | are available in the Git repository at: | 10 | are available in the Git repository at: |
13 | 11 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220711 |
15 | 13 | ||
16 | for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34: | 14 | for you to fetch changes up to f9982ceaf26df27d15547a3a7990a95019e9e3a8: |
17 | 15 | ||
18 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100) | 16 | linux-user/aarch64: Add SME related hwcap entries (2022-07-11 13:43:52 +0100) |
19 | 17 | ||
20 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
21 | target-arm queue: | 19 | target-arm: |
22 | * MAINTAINERS/.mailmap: update email for Leif Lindholm | 20 | * Implement SME emulation, for both system and linux-user |
23 | * hw/arm: add version information to sbsa-ref machine DT | ||
24 | * Enable new features for -cpu max: | ||
25 | FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only), | ||
26 | FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH | ||
27 | * Emulate Cortex-A76 | ||
28 | * Emulate Neoverse-N1 | ||
29 | * Fix the virt board default NUMA topology | ||
30 | 21 | ||
31 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
32 | Gavin Shan (6): | 23 | Richard Henderson (45): |
33 | qapi/machine.json: Add cluster-id | 24 | target/arm: Handle SME in aarch64_cpu_dump_state |
34 | qtest/numa-test: Specify CPU topology in aarch64_numa_cpu() | 25 | target/arm: Add infrastructure for disas_sme |
35 | hw/arm/virt: Consider SMP configuration in CPU topology | 26 | target/arm: Trap non-streaming usage when Streaming SVE is active |
36 | qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu() | 27 | target/arm: Mark ADR as non-streaming |
37 | hw/arm/virt: Fix CPU's default NUMA node ID | 28 | target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming |
38 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table | 29 | target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming |
30 | target/arm: Mark PMULL, FMMLA as non-streaming | ||
31 | target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming | ||
32 | target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming | ||
33 | target/arm: Mark string/histo/crypto as non-streaming | ||
34 | target/arm: Mark gather/scatter load/store as non-streaming | ||
35 | target/arm: Mark gather prefetch as non-streaming | ||
36 | target/arm: Mark LDFF1 and LDNF1 as non-streaming | ||
37 | target/arm: Mark LD1RO as non-streaming | ||
38 | target/arm: Add SME enablement checks | ||
39 | target/arm: Handle SME in sve_access_check | ||
40 | target/arm: Implement SME RDSVL, ADDSVL, ADDSPL | ||
41 | target/arm: Implement SME ZERO | ||
42 | target/arm: Implement SME MOVA | ||
43 | target/arm: Implement SME LD1, ST1 | ||
44 | target/arm: Export unpredicated ld/st from translate-sve.c | ||
45 | target/arm: Implement SME LDR, STR | ||
46 | target/arm: Implement SME ADDHA, ADDVA | ||
47 | target/arm: Implement FMOPA, FMOPS (non-widening) | ||
48 | target/arm: Implement BFMOPA, BFMOPS | ||
49 | target/arm: Implement FMOPA, FMOPS (widening) | ||
50 | target/arm: Implement SME integer outer product | ||
51 | target/arm: Implement PSEL | ||
52 | target/arm: Implement REVD | ||
53 | target/arm: Implement SCLAMP, UCLAMP | ||
54 | target/arm: Reset streaming sve state on exception boundaries | ||
55 | target/arm: Enable SME for -cpu max | ||
56 | linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS | ||
57 | linux-user/aarch64: Reset PSTATE.SM on syscalls | ||
58 | linux-user/aarch64: Add SM bit to SVE signal context | ||
59 | linux-user/aarch64: Tidy target_restore_sigframe error return | ||
60 | linux-user/aarch64: Do not allow duplicate or short sve records | ||
61 | linux-user/aarch64: Verify extra record lock succeeded | ||
62 | linux-user/aarch64: Move sve record checks into restore | ||
63 | linux-user/aarch64: Implement SME signal handling | ||
64 | linux-user: Rename sve prctls | ||
65 | linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL | ||
66 | target/arm: Only set ZEN in reset if SVE present | ||
67 | target/arm: Enable SME for user-only | ||
68 | linux-user/aarch64: Add SME related hwcap entries | ||
39 | 69 | ||
40 | Leif Lindholm (2): | 70 | docs/system/arm/emulation.rst | 4 + |
41 | MAINTAINERS/.mailmap: update email for Leif Lindholm | 71 | linux-user/aarch64/target_cpu.h | 5 +- |
42 | hw/arm: add versioning to sbsa-ref machine DT | 72 | linux-user/aarch64/target_prctl.h | 62 +- |
43 | 73 | target/arm/cpu.h | 7 + | |
44 | Richard Henderson (24): | 74 | target/arm/helper-sme.h | 126 ++++ |
45 | target/arm: Handle cpreg registration for missing EL | 75 | target/arm/helper-sve.h | 4 + |
46 | target/arm: Drop EL3 no EL2 fallbacks | 76 | target/arm/helper.h | 18 + |
47 | target/arm: Merge zcr reginfo | 77 | target/arm/translate-a64.h | 45 ++ |
48 | target/arm: Adjust definition of CONTEXTIDR_EL2 | 78 | target/arm/translate.h | 16 + |
49 | target/arm: Move cortex impdef sysregs to cpu_tcg.c | 79 | target/arm/sme-fa64.decode | 60 ++ |
50 | target/arm: Update qemu-system-arm -cpu max to cortex-a57 | 80 | target/arm/sme.decode | 88 +++ |
51 | target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max | 81 | target/arm/sve.decode | 41 +- |
52 | target/arm: Split out aa32_max_features | 82 | linux-user/aarch64/cpu_loop.c | 9 + |
53 | target/arm: Annotate arm_max_initfn with FEAT identifiers | 83 | linux-user/aarch64/signal.c | 243 ++++++-- |
54 | target/arm: Use field names for manipulating EL2 and EL3 modes | 84 | linux-user/elfload.c | 20 + |
55 | target/arm: Enable FEAT_Debugv8p2 for -cpu max | 85 | linux-user/syscall.c | 28 +- |
56 | target/arm: Enable FEAT_Debugv8p4 for -cpu max | 86 | target/arm/cpu.c | 35 +- |
57 | target/arm: Add minimal RAS registers | 87 | target/arm/cpu64.c | 11 + |
58 | target/arm: Enable SCR and HCR bits for RAS | 88 | target/arm/helper.c | 56 +- |
59 | target/arm: Implement virtual SError exceptions | 89 | target/arm/sme_helper.c | 1140 +++++++++++++++++++++++++++++++++++++ |
60 | target/arm: Implement ESB instruction | 90 | target/arm/sve_helper.c | 28 + |
61 | target/arm: Enable FEAT_RAS for -cpu max | 91 | target/arm/translate-a64.c | 103 +++- |
62 | target/arm: Enable FEAT_IESB for -cpu max | 92 | target/arm/translate-sme.c | 373 ++++++++++++ |
63 | target/arm: Enable FEAT_CSV2 for -cpu max | 93 | target/arm/translate-sve.c | 393 ++++++++++--- |
64 | target/arm: Enable FEAT_CSV2_2 for -cpu max | 94 | target/arm/translate-vfp.c | 12 + |
65 | target/arm: Enable FEAT_CSV3 for -cpu max | 95 | target/arm/translate.c | 2 + |
66 | target/arm: Enable FEAT_DGH for -cpu max | 96 | target/arm/vec_helper.c | 24 + |
67 | target/arm: Define cortex-a76 | 97 | target/arm/meson.build | 3 + |
68 | target/arm: Define neoverse-n1 | 98 | 28 files changed, 2821 insertions(+), 135 deletions(-) |
69 | 99 | create mode 100644 target/arm/sme-fa64.decode | |
70 | docs/system/arm/emulation.rst | 10 + | 100 | create mode 100644 target/arm/sme.decode |
71 | docs/system/arm/virt.rst | 2 + | 101 | create mode 100644 target/arm/translate-sme.c |
72 | qapi/machine.json | 6 +- | ||
73 | target/arm/cpregs.h | 11 + | ||
74 | target/arm/cpu.h | 23 ++ | ||
75 | target/arm/helper.h | 1 + | ||
76 | target/arm/internals.h | 16 ++ | ||
77 | target/arm/syndrome.h | 5 + | ||
78 | target/arm/a32.decode | 16 +- | ||
79 | target/arm/t32.decode | 18 +- | ||
80 | hw/acpi/aml-build.c | 111 ++++---- | ||
81 | hw/arm/sbsa-ref.c | 16 ++ | ||
82 | hw/arm/virt.c | 21 +- | ||
83 | hw/core/machine-hmp-cmds.c | 4 + | ||
84 | hw/core/machine.c | 16 ++ | ||
85 | target/arm/cpu.c | 66 ++++- | ||
86 | target/arm/cpu64.c | 353 ++++++++++++++----------- | ||
87 | target/arm/cpu_tcg.c | 227 +++++++++++----- | ||
88 | target/arm/helper.c | 600 +++++++++++++++++++++++++----------------- | ||
89 | target/arm/op_helper.c | 43 +++ | ||
90 | target/arm/translate-a64.c | 18 ++ | ||
91 | target/arm/translate.c | 23 ++ | ||
92 | tests/qtest/numa-test.c | 19 +- | ||
93 | .mailmap | 3 +- | ||
94 | MAINTAINERS | 2 +- | ||
95 | 25 files changed, 1068 insertions(+), 562 deletions(-) | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The only portion of FEAT_Debugv8p2 that is relevant to QEMU | 3 | Dump SVCR, plus use the correct access check for Streaming Mode. |
4 | is CONTEXTIDR_EL2, which is also conditionally implemented | ||
5 | with FEAT_VHE. The rest of the debug extension concerns the | ||
6 | External debug interface, which is outside the scope of QEMU. | ||
7 | 4 | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20220506180242.216785-12-richard.henderson@linaro.org | 7 | Message-id: 20220708151540.18136-2-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 9 | --- |
13 | docs/system/arm/emulation.rst | 1 + | 10 | target/arm/cpu.c | 17 ++++++++++++++++- |
14 | target/arm/cpu.c | 1 + | 11 | 1 file changed, 16 insertions(+), 1 deletion(-) |
15 | target/arm/cpu64.c | 1 + | ||
16 | target/arm/cpu_tcg.c | 2 ++ | ||
17 | 4 files changed, 5 insertions(+) | ||
18 | 12 | ||
19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/docs/system/arm/emulation.rst | ||
22 | +++ b/docs/system/arm/emulation.rst | ||
23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
24 | - FEAT_BTI (Branch Target Identification) | ||
25 | - FEAT_DIT (Data Independent Timing instructions) | ||
26 | - FEAT_DPB (DC CVAP instruction) | ||
27 | +- FEAT_Debugv8p2 (Debug changes for v8.2) | ||
28 | - FEAT_DotProd (Advanced SIMD dot product instructions) | ||
29 | - FEAT_FCMA (Floating-point complex number instructions) | ||
30 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | ||
31 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
32 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/target/arm/cpu.c | 15 | --- a/target/arm/cpu.c |
34 | +++ b/target/arm/cpu.c | 16 | +++ b/target/arm/cpu.c |
35 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 17 | @@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
36 | * feature registers as well. | 18 | int i; |
37 | */ | 19 | int el = arm_current_el(env); |
38 | cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | 20 | const char *ns_status; |
39 | + cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); | 21 | + bool sve; |
40 | cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | 22 | |
41 | ID_AA64PFR0, EL3, 0); | 23 | qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); |
24 | for (i = 0; i < 32; i++) { | ||
25 | @@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) | ||
26 | el, | ||
27 | psr & PSTATE_SP ? 'h' : 't'); | ||
28 | |||
29 | + if (cpu_isar_feature(aa64_sme, cpu)) { | ||
30 | + qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", | ||
31 | + env->svcr, | ||
32 | + (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), | ||
33 | + (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); | ||
34 | + } | ||
35 | if (cpu_isar_feature(aa64_bti, cpu)) { | ||
36 | qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); | ||
42 | } | 37 | } |
43 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 38 | @@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
44 | index XXXXXXX..XXXXXXX 100644 | 39 | qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", |
45 | --- a/target/arm/cpu64.c | 40 | vfp_get_fpcr(env), vfp_get_fpsr(env)); |
46 | +++ b/target/arm/cpu64.c | 41 | |
47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 42 | - if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { |
48 | cpu->isar.id_aa64zfr0 = t; | 43 | + if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { |
49 | 44 | + sve = sme_exception_el(env, el) == 0; | |
50 | t = cpu->isar.id_aa64dfr0; | 45 | + } else if (cpu_isar_feature(aa64_sve, cpu)) { |
51 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ | 46 | + sve = sve_exception_el(env, el) == 0; |
52 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | 47 | + } else { |
53 | cpu->isar.id_aa64dfr0 = t; | 48 | + sve = false; |
54 | 49 | + } | |
55 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 50 | + |
56 | index XXXXXXX..XXXXXXX 100644 | 51 | + if (sve) { |
57 | --- a/target/arm/cpu_tcg.c | 52 | int j, zcr_len = sve_vqm1_for_el(env, el); |
58 | +++ b/target/arm/cpu_tcg.c | 53 | |
59 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 54 | for (i = 0; i <= FFR_PRED_NUM; i++) { |
60 | cpu->isar.id_pfr2 = t; | ||
61 | |||
62 | t = cpu->isar.id_dfr0; | ||
63 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | ||
64 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | ||
65 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
66 | cpu->isar.id_dfr0 = t; | ||
67 | } | ||
68 | -- | 55 | -- |
69 | 2.25.1 | 56 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | This includes the build rules for the decoder, and the | ||
4 | new file for translation, but excludes any instructions. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-3-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate-a64.h | 1 + | ||
12 | target/arm/sme.decode | 20 ++++++++++++++++++++ | ||
13 | target/arm/translate-a64.c | 7 ++++++- | ||
14 | target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++ | ||
15 | target/arm/meson.build | 2 ++ | ||
16 | 5 files changed, 64 insertions(+), 1 deletion(-) | ||
17 | create mode 100644 target/arm/sme.decode | ||
18 | create mode 100644 target/arm/translate-sme.c | ||
19 | |||
20 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/target/arm/translate-a64.h | ||
23 | +++ b/target/arm/translate-a64.h | ||
24 | @@ -XXX,XX +XXX,XX @@ static inline int pred_gvec_reg_size(DisasContext *s) | ||
25 | } | ||
26 | |||
27 | bool disas_sve(DisasContext *, uint32_t); | ||
28 | +bool disas_sme(DisasContext *, uint32_t); | ||
29 | |||
30 | void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | ||
31 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); | ||
32 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode | ||
33 | new file mode 100644 | ||
34 | index XXXXXXX..XXXXXXX | ||
35 | --- /dev/null | ||
36 | +++ b/target/arm/sme.decode | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | +# AArch64 SME instruction descriptions | ||
39 | +# | ||
40 | +# Copyright (c) 2022 Linaro, Ltd | ||
41 | +# | ||
42 | +# This library is free software; you can redistribute it and/or | ||
43 | +# modify it under the terms of the GNU Lesser General Public | ||
44 | +# License as published by the Free Software Foundation; either | ||
45 | +# version 2.1 of the License, or (at your option) any later version. | ||
46 | +# | ||
47 | +# This library is distributed in the hope that it will be useful, | ||
48 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
49 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
50 | +# Lesser General Public License for more details. | ||
51 | +# | ||
52 | +# You should have received a copy of the GNU Lesser General Public | ||
53 | +# License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
54 | + | ||
55 | +# | ||
56 | +# This file is processed by scripts/decodetree.py | ||
57 | +# | ||
58 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/translate-a64.c | ||
61 | +++ b/target/arm/translate-a64.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
63 | } | ||
64 | |||
65 | switch (extract32(insn, 25, 4)) { | ||
66 | - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ | ||
67 | + case 0x0: | ||
68 | + if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { | ||
69 | + unallocated_encoding(s); | ||
70 | + } | ||
71 | + break; | ||
72 | + case 0x1: case 0x3: /* UNALLOCATED */ | ||
73 | unallocated_encoding(s); | ||
74 | break; | ||
75 | case 0x2: | ||
76 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
77 | new file mode 100644 | ||
78 | index XXXXXXX..XXXXXXX | ||
79 | --- /dev/null | ||
80 | +++ b/target/arm/translate-sme.c | ||
81 | @@ -XXX,XX +XXX,XX @@ | ||
82 | +/* | ||
83 | + * AArch64 SME translation | ||
84 | + * | ||
85 | + * Copyright (c) 2022 Linaro, Ltd | ||
86 | + * | ||
87 | + * This library is free software; you can redistribute it and/or | ||
88 | + * modify it under the terms of the GNU Lesser General Public | ||
89 | + * License as published by the Free Software Foundation; either | ||
90 | + * version 2.1 of the License, or (at your option) any later version. | ||
91 | + * | ||
92 | + * This library is distributed in the hope that it will be useful, | ||
93 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
94 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
95 | + * Lesser General Public License for more details. | ||
96 | + * | ||
97 | + * You should have received a copy of the GNU Lesser General Public | ||
98 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
99 | + */ | ||
100 | + | ||
101 | +#include "qemu/osdep.h" | ||
102 | +#include "cpu.h" | ||
103 | +#include "tcg/tcg-op.h" | ||
104 | +#include "tcg/tcg-op-gvec.h" | ||
105 | +#include "tcg/tcg-gvec-desc.h" | ||
106 | +#include "translate.h" | ||
107 | +#include "exec/helper-gen.h" | ||
108 | +#include "translate-a64.h" | ||
109 | +#include "fpu/softfloat.h" | ||
110 | + | ||
111 | + | ||
112 | +/* | ||
113 | + * Include the generated decoder. | ||
114 | + */ | ||
115 | + | ||
116 | +#include "decode-sme.c.inc" | ||
117 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/target/arm/meson.build | ||
120 | +++ b/target/arm/meson.build | ||
121 | @@ -XXX,XX +XXX,XX @@ | ||
122 | gen = [ | ||
123 | decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), | ||
124 | + decodetree.process('sme.decode', extra_args: '--decode=disas_sme'), | ||
125 | decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), | ||
126 | decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), | ||
127 | decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), | ||
128 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( | ||
129 | 'sme_helper.c', | ||
130 | 'translate-a64.c', | ||
131 | 'translate-sve.c', | ||
132 | + 'translate-sme.c', | ||
133 | )) | ||
134 | |||
135 | arm_softmmu_ss = ss.source_set() | ||
136 | -- | ||
137 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add only the system registers required to implement zero error | 3 | This new behaviour is in the ARM pseudocode function |
4 | records. This means that all values for ERRSELR are out of range, | 4 | AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 |
5 | which means that it and all of the indexed error record registers | 5 | via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which |
6 | need not be implemented. | 6 | the trap would be delivered is in AArch64 mode. |
7 | 7 | ||
8 | Add the EL2 registers required for injecting virtual SError. | 8 | Given that ARMv9 drops support for AArch32 outside EL0, the trap EL |
9 | detection ought to be trivially true, but the pseudocode still contains | ||
10 | a number of conditions, and QEMU has not yet committed to dropping A32 | ||
11 | support for EL[12] when v9 features are present. | ||
12 | |||
13 | Since the computation of SME_TRAP_NONSTREAMING is necessarily different | ||
14 | for the two modes, we might as well preserve bits within TBFLAG_ANY and | ||
15 | allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. | ||
16 | |||
17 | Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table | ||
18 | of instructions illegal in streaming mode. | ||
9 | 19 | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 21 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Message-id: 20220506180242.216785-14-richard.henderson@linaro.org | 22 | Message-id: 20220708151540.18136-4-richard.henderson@linaro.org |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 24 | --- |
15 | target/arm/cpu.h | 5 +++ | 25 | target/arm/cpu.h | 7 +++ |
16 | target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ | 26 | target/arm/translate.h | 4 ++ |
17 | 2 files changed, 89 insertions(+) | 27 | target/arm/sme-fa64.decode | 90 ++++++++++++++++++++++++++++++++++++++ |
28 | target/arm/helper.c | 41 +++++++++++++++++ | ||
29 | target/arm/translate-a64.c | 40 ++++++++++++++++- | ||
30 | target/arm/translate-vfp.c | 12 +++++ | ||
31 | target/arm/translate.c | 2 + | ||
32 | target/arm/meson.build | 1 + | ||
33 | 8 files changed, 195 insertions(+), 2 deletions(-) | ||
34 | create mode 100644 target/arm/sme-fa64.decode | ||
18 | 35 | ||
19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 36 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
20 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/cpu.h | 38 | --- a/target/arm/cpu.h |
22 | +++ b/target/arm/cpu.h | 39 | +++ b/target/arm/cpu.h |
23 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 40 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) |
24 | uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ | 41 | * the same thing as the current security state of the processor! |
25 | uint64_t gcr_el1; | 42 | */ |
26 | uint64_t rgsr_el1; | 43 | FIELD(TBFLAG_A32, NS, 10, 1) |
27 | + | 44 | +/* |
28 | + /* Minimal RAS registers */ | 45 | + * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. |
29 | + uint64_t disr_el1; | 46 | + * This requires an SME trap from AArch32 mode when using NEON. |
30 | + uint64_t vdisr_el2; | 47 | + */ |
31 | + uint64_t vsesr_el2; | 48 | +FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) |
32 | } cp15; | 49 | |
33 | 50 | /* | |
34 | struct { | 51 | * Bit usage when in AArch32 state, for M-profile only. |
52 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) | ||
53 | FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) | ||
54 | FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) | ||
55 | FIELD(TBFLAG_A64, SVL, 24, 4) | ||
56 | +/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ | ||
57 | +FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) | ||
58 | |||
59 | /* | ||
60 | * Helpers for using the above. | ||
61 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/target/arm/translate.h | ||
64 | +++ b/target/arm/translate.h | ||
65 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
66 | bool pstate_sm; | ||
67 | /* True if PSTATE.ZA is set. */ | ||
68 | bool pstate_za; | ||
69 | + /* True if non-streaming insns should raise an SME Streaming exception. */ | ||
70 | + bool sme_trap_nonstreaming; | ||
71 | + /* True if the current instruction is non-streaming. */ | ||
72 | + bool is_nonstreaming; | ||
73 | /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ | ||
74 | bool mve_no_pred; | ||
75 | /* | ||
76 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
77 | new file mode 100644 | ||
78 | index XXXXXXX..XXXXXXX | ||
79 | --- /dev/null | ||
80 | +++ b/target/arm/sme-fa64.decode | ||
81 | @@ -XXX,XX +XXX,XX @@ | ||
82 | +# AArch64 SME allowed instruction decoding | ||
83 | +# | ||
84 | +# Copyright (c) 2022 Linaro, Ltd | ||
85 | +# | ||
86 | +# This library is free software; you can redistribute it and/or | ||
87 | +# modify it under the terms of the GNU Lesser General Public | ||
88 | +# License as published by the Free Software Foundation; either | ||
89 | +# version 2.1 of the License, or (at your option) any later version. | ||
90 | +# | ||
91 | +# This library is distributed in the hope that it will be useful, | ||
92 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
93 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
94 | +# Lesser General Public License for more details. | ||
95 | +# | ||
96 | +# You should have received a copy of the GNU Lesser General Public | ||
97 | +# License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
98 | + | ||
99 | +# | ||
100 | +# This file is processed by scripts/decodetree.py | ||
101 | +# | ||
102 | + | ||
103 | +# These patterns are taken from Appendix E1.1 of DDI0616 A.a, | ||
104 | +# Arm Architecture Reference Manual Supplement, | ||
105 | +# The Scalable Matrix Extension (SME), for Armv9-A | ||
106 | + | ||
107 | +{ | ||
108 | + [ | ||
109 | + OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0] | ||
110 | + OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0] | ||
111 | + OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0] | ||
112 | + OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0] | ||
113 | + OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0] | ||
114 | + OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0] | ||
115 | + OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0] | ||
116 | + ] | ||
117 | + FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations | ||
118 | +} | ||
119 | + | ||
120 | +{ | ||
121 | + [ | ||
122 | + OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar) | ||
123 | + OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16) | ||
124 | + OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar) | ||
125 | + OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16) | ||
126 | + ] | ||
127 | + FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-element operations | ||
128 | +} | ||
129 | + | ||
130 | +FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store | ||
131 | +FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography extensions | ||
132 | +FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
133 | + | ||
134 | +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions | ||
135 | +# We don't actually need to include these, as the default is OK. | ||
136 | +# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point operations | ||
137 | +# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers | ||
138 | +# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal) | ||
139 | +# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) | ||
140 | +# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
141 | +# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
142 | + | ||
143 | +FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR | ||
144 | +FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA | ||
145 | +FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT | ||
146 | +FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS | ||
147 | +FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR | ||
148 | +FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP | ||
149 | +FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) | ||
150 | +FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA | ||
151 | +FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL | ||
152 | +FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD | ||
153 | +FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA | ||
154 | +FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA | ||
155 | +FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions | ||
156 | +FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) | ||
157 | +FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) | ||
158 | +FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) | ||
159 | +FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load (vector+imm) | ||
160 | +FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load byte (scalar+vector) | ||
161 | +FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load half (scalar+vector) | ||
162 | +FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load word (scalar+vector) | ||
163 | +FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) | ||
164 | +FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) | ||
165 | +FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) | ||
166 | +FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) | ||
167 | +FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch | ||
168 | +FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT store (vector+scalar) | ||
169 | +FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT store (vector+scalar) | ||
170 | +FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (scalar+32-bit vector) | ||
171 | +FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc) | ||
35 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 172 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
36 | index XXXXXXX..XXXXXXX 100644 | 173 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/target/arm/helper.c | 174 | --- a/target/arm/helper.c |
38 | +++ b/target/arm/helper.c | 175 | +++ b/target/arm/helper.c |
39 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | 176 | @@ -XXX,XX +XXX,XX @@ int sme_exception_el(CPUARMState *env, int el) |
40 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | 177 | return 0; |
41 | }; | 178 | } |
179 | |||
180 | +/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ | ||
181 | +static bool sme_fa64(CPUARMState *env, int el) | ||
182 | +{ | ||
183 | + if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { | ||
184 | + return false; | ||
185 | + } | ||
186 | + | ||
187 | + if (el <= 1 && !el_is_in_host(env, el)) { | ||
188 | + if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { | ||
189 | + return false; | ||
190 | + } | ||
191 | + } | ||
192 | + if (el <= 2 && arm_is_el2_enabled(env)) { | ||
193 | + if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { | ||
194 | + return false; | ||
195 | + } | ||
196 | + } | ||
197 | + if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
198 | + if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { | ||
199 | + return false; | ||
200 | + } | ||
201 | + } | ||
202 | + | ||
203 | + return true; | ||
204 | +} | ||
205 | + | ||
206 | /* | ||
207 | * Given that SVE is enabled, return the vector length for EL. | ||
208 | */ | ||
209 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, | ||
210 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | ||
211 | } | ||
212 | |||
213 | + /* | ||
214 | + * The SME exception we are testing for is raised via | ||
215 | + * AArch64.CheckFPAdvSIMDEnabled(), as called from | ||
216 | + * AArch32.CheckAdvSIMDOrFPEnabled(). | ||
217 | + */ | ||
218 | + if (el == 0 | ||
219 | + && FIELD_EX64(env->svcr, SVCR, SM) | ||
220 | + && (!arm_is_el2_enabled(env) | ||
221 | + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) | ||
222 | + && arm_el_is_aa64(env, 1) | ||
223 | + && !sme_fa64(env, el)) { | ||
224 | + DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); | ||
225 | + } | ||
226 | + | ||
227 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | ||
228 | } | ||
229 | |||
230 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, | ||
231 | } | ||
232 | if (FIELD_EX64(env->svcr, SVCR, SM)) { | ||
233 | DP_TBFLAG_A64(flags, PSTATE_SM, 1); | ||
234 | + DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); | ||
235 | } | ||
236 | DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); | ||
237 | } | ||
238 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
239 | index XXXXXXX..XXXXXXX 100644 | ||
240 | --- a/target/arm/translate-a64.c | ||
241 | +++ b/target/arm/translate-a64.c | ||
242 | @@ -XXX,XX +XXX,XX @@ static void do_vec_ld(DisasContext *s, int destidx, int element, | ||
243 | * unallocated-encoding checks (otherwise the syndrome information | ||
244 | * for the resulting exception will be incorrect). | ||
245 | */ | ||
246 | -static bool fp_access_check(DisasContext *s) | ||
247 | +static bool fp_access_check_only(DisasContext *s) | ||
248 | { | ||
249 | if (s->fp_excp_el) { | ||
250 | assert(!s->fp_access_checked); | ||
251 | @@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s) | ||
252 | return true; | ||
253 | } | ||
254 | |||
255 | +static bool fp_access_check(DisasContext *s) | ||
256 | +{ | ||
257 | + if (!fp_access_check_only(s)) { | ||
258 | + return false; | ||
259 | + } | ||
260 | + if (s->sme_trap_nonstreaming && s->is_nonstreaming) { | ||
261 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
262 | + syn_smetrap(SME_ET_Streaming, false)); | ||
263 | + return false; | ||
264 | + } | ||
265 | + return true; | ||
266 | +} | ||
267 | + | ||
268 | /* Check that SVE access is enabled. If it is, return true. | ||
269 | * If not, emit code to generate an appropriate exception and return false. | ||
270 | */ | ||
271 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
272 | default: | ||
273 | g_assert_not_reached(); | ||
274 | } | ||
275 | - if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { | ||
276 | + if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { | ||
277 | return; | ||
278 | } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { | ||
279 | return; | ||
280 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | ||
281 | } | ||
282 | } | ||
42 | 283 | ||
43 | +/* | 284 | +/* |
44 | + * Check for traps to RAS registers, which are controlled | 285 | + * Include the generated SME FA64 decoder. |
45 | + * by HCR_EL2.TERR and SCR_EL3.TERR. | ||
46 | + */ | 286 | + */ |
47 | +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, | 287 | + |
48 | + bool isread) | 288 | +#include "decode-sme-fa64.c.inc" |
49 | +{ | 289 | + |
50 | + int el = arm_current_el(env); | 290 | +static bool trans_OK(DisasContext *s, arg_OK *a) |
51 | + | 291 | +{ |
52 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { | 292 | + return true; |
53 | + return CP_ACCESS_TRAP_EL2; | 293 | +} |
54 | + } | 294 | + |
55 | + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { | 295 | +static bool trans_FAIL(DisasContext *s, arg_OK *a) |
56 | + return CP_ACCESS_TRAP_EL3; | 296 | +{ |
57 | + } | 297 | + s->is_nonstreaming = true; |
58 | + return CP_ACCESS_OK; | 298 | + return true; |
59 | +} | 299 | +} |
60 | + | 300 | + |
61 | +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 301 | /** |
62 | +{ | 302 | * is_guarded_page: |
63 | + int el = arm_current_el(env); | 303 | * @env: The cpu environment |
64 | + | 304 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
65 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | 305 | dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); |
66 | + return env->cp15.vdisr_el2; | 306 | dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM); |
67 | + } | 307 | dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA); |
68 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | 308 | + dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING); |
69 | + return 0; /* RAZ/WI */ | 309 | dc->vec_len = 0; |
70 | + } | 310 | dc->vec_stride = 0; |
71 | + return env->cp15.disr_el1; | 311 | dc->cp_regs = arm_cpu->cp_regs; |
72 | +} | 312 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
73 | + | 313 | } |
74 | +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | 314 | } |
75 | +{ | 315 | |
76 | + int el = arm_current_el(env); | 316 | + s->is_nonstreaming = false; |
77 | + | 317 | + if (s->sme_trap_nonstreaming) { |
78 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | 318 | + disas_sme_fa64(s, insn); |
79 | + env->cp15.vdisr_el2 = val; | 319 | + } |
80 | + return; | 320 | + |
81 | + } | 321 | switch (extract32(insn, 25, 4)) { |
82 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | 322 | case 0x0: |
83 | + return; /* RAZ/WI */ | 323 | if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { |
84 | + } | 324 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c |
85 | + env->cp15.disr_el1 = val; | 325 | index XXXXXXX..XXXXXXX 100644 |
86 | +} | 326 | --- a/target/arm/translate-vfp.c |
87 | + | 327 | +++ b/target/arm/translate-vfp.c |
88 | +/* | 328 | @@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) |
89 | + * Minimal RAS implementation with no Error Records. | 329 | return false; |
90 | + * Which means that all of the Error Record registers: | 330 | } |
91 | + * ERXADDR_EL1 | 331 | |
92 | + * ERXCTLR_EL1 | 332 | + /* |
93 | + * ERXFR_EL1 | 333 | + * Note that rebuild_hflags_a32 has already accounted for being in EL0 |
94 | + * ERXMISC0_EL1 | 334 | + * and the higher EL in A64 mode, etc. Unlike A64 mode, there do not |
95 | + * ERXMISC1_EL1 | 335 | + * appear to be any insns which touch VFP which are allowed. |
96 | + * ERXMISC2_EL1 | 336 | + */ |
97 | + * ERXMISC3_EL1 | 337 | + if (s->sme_trap_nonstreaming) { |
98 | + * ERXPFGCDN_EL1 (RASv1p1) | 338 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
99 | + * ERXPFGCTL_EL1 (RASv1p1) | 339 | + syn_smetrap(SME_ET_Streaming, |
100 | + * ERXPFGF_EL1 (RASv1p1) | 340 | + s->base.pc_next - s->pc_curr == 2)); |
101 | + * ERXSTATUS_EL1 | 341 | + return false; |
102 | + * and | 342 | + } |
103 | + * ERRSELR_EL1 | 343 | + |
104 | + * may generate UNDEFINED, which is the effect we get by not | 344 | if (!s->vfp_enabled && !ignore_vfp_enabled) { |
105 | + * listing them at all. | 345 | assert(!arm_dc_feature(s, ARM_FEATURE_M)); |
106 | + */ | 346 | unallocated_encoding(s); |
107 | +static const ARMCPRegInfo minimal_ras_reginfo[] = { | 347 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
108 | + { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | 348 | index XXXXXXX..XXXXXXX 100644 |
109 | + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | 349 | --- a/target/arm/translate.c |
110 | + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | 350 | +++ b/target/arm/translate.c |
111 | + .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | 351 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
112 | + { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | 352 | dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN); |
113 | + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | 353 | dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE); |
114 | + .access = PL1_R, .accessfn = access_terr, | 354 | } |
115 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | 355 | + dc->sme_trap_nonstreaming = |
116 | + { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | 356 | + EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); |
117 | + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | 357 | } |
118 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | 358 | dc->cp_regs = cpu->cp_regs; |
119 | + { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | 359 | dc->features = env->features; |
120 | + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | 360 | diff --git a/target/arm/meson.build b/target/arm/meson.build |
121 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | 361 | index XXXXXXX..XXXXXXX 100644 |
122 | +}; | 362 | --- a/target/arm/meson.build |
123 | + | 363 | +++ b/target/arm/meson.build |
124 | /* Return the exception level to which exceptions should be taken | 364 | @@ -XXX,XX +XXX,XX @@ |
125 | * via SVEAccessTrap. If an exception should be routed through | 365 | gen = [ |
126 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | 366 | decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), |
127 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 367 | decodetree.process('sme.decode', extra_args: '--decode=disas_sme'), |
128 | if (cpu_isar_feature(aa64_ssbs, cpu)) { | 368 | + decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'), |
129 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | 369 | decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), |
130 | } | 370 | decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), |
131 | + if (cpu_isar_feature(any_ras, cpu)) { | 371 | decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), |
132 | + define_arm_cp_regs(cpu, minimal_ras_reginfo); | ||
133 | + } | ||
134 | |||
135 | if (cpu_isar_feature(aa64_vh, cpu) || | ||
136 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | ||
137 | -- | 372 | -- |
138 | 2.25.1 | 373 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark ADR as a non-streaming instruction, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Removing entries from sme-fa64.decode is an easy way to see | ||
7 | what remains to be done. | ||
8 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220708151540.18136-5-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/translate.h | 7 +++++++ | ||
15 | target/arm/sme-fa64.decode | 1 - | ||
16 | target/arm/translate-sve.c | 8 ++++---- | ||
17 | 3 files changed, 11 insertions(+), 5 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/translate.h | ||
22 | +++ b/target/arm/translate.h | ||
23 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); | ||
24 | static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ | ||
25 | { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } | ||
26 | |||
27 | +#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ | ||
28 | + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ | ||
29 | + { \ | ||
30 | + s->is_nonstreaming = true; \ | ||
31 | + return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ | ||
32 | + } | ||
33 | + | ||
34 | #endif /* TARGET_ARM_TRANSLATE_H */ | ||
35 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/sme-fa64.decode | ||
38 | +++ b/target/arm/sme-fa64.decode | ||
39 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
40 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
41 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
42 | |||
43 | -FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR | ||
44 | FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA | ||
45 | FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT | ||
46 | FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS | ||
47 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/translate-sve.c | ||
50 | +++ b/target/arm/translate-sve.c | ||
51 | @@ -XXX,XX +XXX,XX @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn) | ||
52 | return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm); | ||
53 | } | ||
54 | |||
55 | -TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32) | ||
56 | -TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64) | ||
57 | -TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32) | ||
58 | -TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32) | ||
59 | +TRANS_FEAT_NONSTREAMING(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32) | ||
60 | +TRANS_FEAT_NONSTREAMING(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64) | ||
61 | +TRANS_FEAT_NONSTREAMING(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32) | ||
62 | +TRANS_FEAT_NONSTREAMING(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32) | ||
63 | |||
64 | /* | ||
65 | *** SVE Integer Misc - Unpredicated Group | ||
66 | -- | ||
67 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark these as a non-streaming instructions, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-6-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/sme-fa64.decode | 2 -- | ||
12 | target/arm/translate-sve.c | 9 ++++++--- | ||
13 | 2 files changed, 6 insertions(+), 5 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/sme-fa64.decode | ||
18 | +++ b/target/arm/sme-fa64.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
20 | |||
21 | FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA | ||
22 | FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT | ||
23 | -FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS | ||
24 | -FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR | ||
25 | FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP | ||
26 | FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) | ||
27 | FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA | ||
28 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/translate-sve.c | ||
31 | +++ b/target/arm/translate-sve.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) | ||
33 | TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s) | ||
34 | |||
35 | /* Note pat == 31 is #all, to set all elements. */ | ||
36 | -TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false) | ||
37 | +TRANS_FEAT_NONSTREAMING(SETFFR, aa64_sve, | ||
38 | + do_predset, 0, FFR_PRED_NUM, 31, false) | ||
39 | |||
40 | /* Note pat == 32 is #unimp, to set no elements. */ | ||
41 | TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false) | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a) | ||
43 | .rd = a->rd, .pg = a->pg, .s = a->s, | ||
44 | .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM, | ||
45 | }; | ||
46 | + | ||
47 | + s->is_nonstreaming = true; | ||
48 | return trans_AND_pppp(s, &alt_a); | ||
49 | } | ||
50 | |||
51 | -TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) | ||
52 | -TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) | ||
53 | +TRANS_FEAT_NONSTREAMING(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) | ||
54 | +TRANS_FEAT_NONSTREAMING(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) | ||
55 | |||
56 | static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, | ||
57 | void (*gen_fn)(TCGv_i32, TCGv_ptr, | ||
58 | -- | ||
59 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark these as a non-streaming instructions, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-7-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/sme-fa64.decode | 3 --- | ||
12 | target/arm/translate-sve.c | 22 ++++++++++++---------- | ||
13 | 2 files changed, 12 insertions(+), 13 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/sme-fa64.decode | ||
18 | +++ b/target/arm/sme-fa64.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
20 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
21 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
22 | |||
23 | -FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA | ||
24 | -FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT | ||
25 | -FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP | ||
26 | FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) | ||
27 | FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA | ||
28 | FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL | ||
29 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate-sve.c | ||
32 | +++ b/target/arm/translate-sve.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const fexpa_fns[4] = { | ||
34 | NULL, gen_helper_sve_fexpa_h, | ||
35 | gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d, | ||
36 | }; | ||
37 | -TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz, | ||
38 | - fexpa_fns[a->esz], a->rd, a->rn, 0) | ||
39 | +TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz, | ||
40 | + fexpa_fns[a->esz], a->rd, a->rn, 0) | ||
41 | |||
42 | static gen_helper_gvec_3 * const ftssel_fns[4] = { | ||
43 | NULL, gen_helper_sve_ftssel_h, | ||
44 | gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d, | ||
45 | }; | ||
46 | -TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0) | ||
47 | +TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, | ||
48 | + ftssel_fns[a->esz], a, 0) | ||
49 | |||
50 | /* | ||
51 | *** SVE Predicate Logical Operations Group | ||
52 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, | ||
53 | static gen_helper_gvec_3 * const compact_fns[4] = { | ||
54 | NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d | ||
55 | }; | ||
56 | -TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0) | ||
57 | +TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, | ||
58 | + compact_fns[a->esz], a, 0) | ||
59 | |||
60 | /* Call the helper that computes the ARM LastActiveElement pseudocode | ||
61 | * function, scaled by the element size. This includes the not found | ||
62 | @@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const bext_fns[4] = { | ||
63 | gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, | ||
64 | gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, | ||
65 | }; | ||
66 | -TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | ||
67 | - bext_fns[a->esz], a, 0) | ||
68 | +TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | ||
69 | + bext_fns[a->esz], a, 0) | ||
70 | |||
71 | static gen_helper_gvec_3 * const bdep_fns[4] = { | ||
72 | gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, | ||
73 | gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, | ||
74 | }; | ||
75 | -TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | ||
76 | - bdep_fns[a->esz], a, 0) | ||
77 | +TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | ||
78 | + bdep_fns[a->esz], a, 0) | ||
79 | |||
80 | static gen_helper_gvec_3 * const bgrp_fns[4] = { | ||
81 | gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, | ||
82 | gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, | ||
83 | }; | ||
84 | -TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | ||
85 | - bgrp_fns[a->esz], a, 0) | ||
86 | +TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | ||
87 | + bgrp_fns[a->esz], a, 0) | ||
88 | |||
89 | static gen_helper_gvec_3 * const cadd_fns[4] = { | ||
90 | gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, | ||
91 | -- | ||
92 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark these as a non-streaming instructions, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-8-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/sme-fa64.decode | 2 -- | ||
12 | target/arm/translate-sve.c | 24 +++++++++++++++--------- | ||
13 | 2 files changed, 15 insertions(+), 11 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/sme-fa64.decode | ||
18 | +++ b/target/arm/sme-fa64.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
20 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
21 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
22 | |||
23 | -FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) | ||
24 | -FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA | ||
25 | FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL | ||
26 | FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD | ||
27 | FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA | ||
28 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/translate-sve.c | ||
31 | +++ b/target/arm/translate-sve.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel) | ||
33 | gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h, | ||
34 | NULL, gen_helper_sve2_pmull_d, | ||
35 | }; | ||
36 | - if (a->esz == 0 | ||
37 | - ? !dc_isar_feature(aa64_sve2_pmull128, s) | ||
38 | - : !dc_isar_feature(aa64_sve, s)) { | ||
39 | + | ||
40 | + if (a->esz == 0) { | ||
41 | + if (!dc_isar_feature(aa64_sve2_pmull128, s)) { | ||
42 | + return false; | ||
43 | + } | ||
44 | + s->is_nonstreaming = true; | ||
45 | + } else if (!dc_isar_feature(aa64_sve, s)) { | ||
46 | return false; | ||
47 | } | ||
48 | return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); | ||
49 | @@ -XXX,XX +XXX,XX @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz) | ||
50 | * SVE Integer Multiply-Add (unpredicated) | ||
51 | */ | ||
52 | |||
53 | -TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s, | ||
54 | - a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) | ||
55 | -TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d, | ||
56 | - a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) | ||
57 | +TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, | ||
58 | + gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra, | ||
59 | + 0, FPST_FPCR) | ||
60 | +TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, | ||
61 | + gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra, | ||
62 | + 0, FPST_FPCR) | ||
63 | |||
64 | static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = { | ||
65 | NULL, gen_helper_sve2_sqdmlal_zzzw_h, | ||
66 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, | ||
67 | TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, | ||
68 | gen_helper_gvec_bfdot_idx, a) | ||
69 | |||
70 | -TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, | ||
71 | - gen_helper_gvec_bfmmla, a, 0) | ||
72 | +TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, | ||
73 | + gen_helper_gvec_bfmmla, a, 0) | ||
74 | |||
75 | static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) | ||
76 | { | ||
77 | -- | ||
78 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark these as a non-streaming instructions, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-9-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/sme-fa64.decode | 3 --- | ||
12 | target/arm/translate-sve.c | 15 +++++++++++---- | ||
13 | 2 files changed, 11 insertions(+), 7 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/sme-fa64.decode | ||
18 | +++ b/target/arm/sme-fa64.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
20 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
21 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
22 | |||
23 | -FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL | ||
24 | -FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD | ||
25 | -FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA | ||
26 | FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA | ||
27 | FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions | ||
28 | FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) | ||
29 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate-sve.c | ||
32 | +++ b/target/arm/translate-sve.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = { | ||
34 | NULL, gen_helper_sve_ftmad_h, | ||
35 | gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d, | ||
36 | }; | ||
37 | -TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz, | ||
38 | - ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, | ||
39 | - a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR) | ||
40 | +TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz, | ||
41 | + ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, | ||
42 | + a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR) | ||
43 | |||
44 | /* | ||
45 | *** SVE Floating Point Accumulating Reduction Group | ||
46 | @@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) | ||
47 | if (a->esz == 0 || !dc_isar_feature(aa64_sve, s)) { | ||
48 | return false; | ||
49 | } | ||
50 | + s->is_nonstreaming = true; | ||
51 | if (!sve_access_check(s)) { | ||
52 | return true; | ||
53 | } | ||
54 | @@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) | ||
55 | DO_FP3(FADD_zzz, fadd) | ||
56 | DO_FP3(FSUB_zzz, fsub) | ||
57 | DO_FP3(FMUL_zzz, fmul) | ||
58 | -DO_FP3(FTSMUL, ftsmul) | ||
59 | DO_FP3(FRECPS, recps) | ||
60 | DO_FP3(FRSQRTS, rsqrts) | ||
61 | |||
62 | #undef DO_FP3 | ||
63 | |||
64 | +static gen_helper_gvec_3_ptr * const ftsmul_fns[4] = { | ||
65 | + NULL, gen_helper_gvec_ftsmul_h, | ||
66 | + gen_helper_gvec_ftsmul_s, gen_helper_gvec_ftsmul_d | ||
67 | +}; | ||
68 | +TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_fpst_arg_zzz, | ||
69 | + ftsmul_fns[a->esz], a, 0) | ||
70 | + | ||
71 | /* | ||
72 | *** SVE Floating Point Arithmetic - Predicated Group | ||
73 | */ | ||
74 | -- | ||
75 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark these as a non-streaming instructions, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-10-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/sme-fa64.decode | 1 - | ||
12 | target/arm/translate-sve.c | 12 ++++++------ | ||
13 | 2 files changed, 6 insertions(+), 7 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/sme-fa64.decode | ||
18 | +++ b/target/arm/sme-fa64.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
20 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
21 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
22 | |||
23 | -FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA | ||
24 | FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions | ||
25 | FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) | ||
26 | FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) | ||
27 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/translate-sve.c | ||
30 | +++ b/target/arm/translate-sve.c | ||
31 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMLALT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, true) | ||
32 | TRANS_FEAT(FMLSLB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, false) | ||
33 | TRANS_FEAT(FMLSLT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, true) | ||
34 | |||
35 | -TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | ||
36 | - gen_helper_gvec_smmla_b, a, 0) | ||
37 | -TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | ||
38 | - gen_helper_gvec_usmmla_b, a, 0) | ||
39 | -TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | ||
40 | - gen_helper_gvec_ummla_b, a, 0) | ||
41 | +TRANS_FEAT_NONSTREAMING(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | ||
42 | + gen_helper_gvec_smmla_b, a, 0) | ||
43 | +TRANS_FEAT_NONSTREAMING(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | ||
44 | + gen_helper_gvec_usmmla_b, a, 0) | ||
45 | +TRANS_FEAT_NONSTREAMING(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | ||
46 | + gen_helper_gvec_ummla_b, a, 0) | ||
47 | |||
48 | TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, | ||
49 | gen_helper_gvec_bfdot, a, 0) | ||
50 | -- | ||
51 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark these as non-streaming instructions, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-11-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/sme-fa64.decode | 1 - | ||
12 | target/arm/translate-sve.c | 35 ++++++++++++++++++----------------- | ||
13 | 2 files changed, 18 insertions(+), 18 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/sme-fa64.decode | ||
18 | +++ b/target/arm/sme-fa64.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
20 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
21 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
22 | |||
23 | -FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions | ||
24 | FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) | ||
25 | FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) | ||
26 | FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) | ||
27 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/translate-sve.c | ||
30 | +++ b/target/arm/translate-sve.c | ||
31 | @@ -XXX,XX +XXX,XX @@ DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt) | ||
32 | static gen_helper_gvec_flags_4 * const match_fns[4] = { | ||
33 | gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL | ||
34 | }; | ||
35 | -TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz]) | ||
36 | +TRANS_FEAT_NONSTREAMING(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz]) | ||
37 | |||
38 | static gen_helper_gvec_flags_4 * const nmatch_fns[4] = { | ||
39 | gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL | ||
40 | }; | ||
41 | -TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz]) | ||
42 | +TRANS_FEAT_NONSTREAMING(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz]) | ||
43 | |||
44 | static gen_helper_gvec_4 * const histcnt_fns[4] = { | ||
45 | NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d | ||
46 | }; | ||
47 | -TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, | ||
48 | - histcnt_fns[a->esz], a, 0) | ||
49 | +TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, | ||
50 | + histcnt_fns[a->esz], a, 0) | ||
51 | |||
52 | -TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, | ||
53 | - a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0) | ||
54 | +TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, | ||
55 | + a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0) | ||
56 | |||
57 | DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz) | ||
58 | DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz) | ||
59 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz, | ||
60 | TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | ||
61 | a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0) | ||
62 | |||
63 | -TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, | ||
64 | - gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) | ||
65 | +TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, | ||
66 | + gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) | ||
67 | |||
68 | -TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, | ||
69 | - gen_helper_crypto_aese, a, false) | ||
70 | -TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, | ||
71 | - gen_helper_crypto_aese, a, true) | ||
72 | +TRANS_FEAT_NONSTREAMING(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, | ||
73 | + gen_helper_crypto_aese, a, false) | ||
74 | +TRANS_FEAT_NONSTREAMING(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, | ||
75 | + gen_helper_crypto_aese, a, true) | ||
76 | |||
77 | -TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, | ||
78 | - gen_helper_crypto_sm4e, a, 0) | ||
79 | -TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, | ||
80 | - gen_helper_crypto_sm4ekey, a, 0) | ||
81 | +TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, | ||
82 | + gen_helper_crypto_sm4e, a, 0) | ||
83 | +TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, | ||
84 | + gen_helper_crypto_sm4ekey, a, 0) | ||
85 | |||
86 | -TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) | ||
87 | +TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, | ||
88 | + gen_gvec_rax1, a) | ||
89 | |||
90 | TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, | ||
91 | gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR) | ||
92 | -- | ||
93 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This register is present for either VHE or Debugv8p2. | 3 | Mark these as a non-streaming instructions, which should trap |
4 | if full a64 support is not enabled in streaming mode. | ||
4 | 5 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-5-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-12-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/helper.c | 15 +++++++++++---- | 11 | target/arm/sme-fa64.decode | 9 --------- |
11 | 1 file changed, 11 insertions(+), 4 deletions(-) | 12 | target/arm/translate-sve.c | 6 ++++++ |
13 | 2 files changed, 6 insertions(+), 9 deletions(-) | ||
12 | 14 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 17 | --- a/target/arm/sme-fa64.decode |
16 | +++ b/target/arm/helper.c | 18 | +++ b/target/arm/sme-fa64.decode |
17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = { | 19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS |
18 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 20 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) |
19 | }; | 21 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) |
20 | 22 | ||
21 | +static const ARMCPRegInfo contextidr_el2 = { | 23 | -FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) |
22 | + .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | 24 | FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) |
23 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | 25 | FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) |
24 | + .access = PL2_RW, | 26 | -FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load (vector+imm) |
25 | + .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) | 27 | -FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load byte (scalar+vector) |
26 | +}; | 28 | -FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load half (scalar+vector) |
27 | + | 29 | -FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load word (scalar+vector) |
28 | static const ARMCPRegInfo vhe_reginfo[] = { | 30 | FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) |
29 | - { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | 31 | FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) |
30 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | 32 | FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) |
31 | - .access = PL2_RW, | 33 | FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) |
32 | - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, | 34 | FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch |
33 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, | 35 | -FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT store (vector+scalar) |
34 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | 36 | -FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT store (vector+scalar) |
35 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | 37 | -FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (scalar+32-bit vector) |
36 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 38 | -FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc) |
37 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | 39 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/translate-sve.c | ||
42 | +++ b/target/arm/translate-sve.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) | ||
44 | if (!dc_isar_feature(aa64_sve, s)) { | ||
45 | return false; | ||
38 | } | 46 | } |
39 | 47 | + s->is_nonstreaming = true; | |
40 | + if (cpu_isar_feature(aa64_vh, cpu) || | 48 | if (!sve_access_check(s)) { |
41 | + cpu_isar_feature(aa64_debugv8p2, cpu)) { | 49 | return true; |
42 | + define_one_arm_cp_reg(cpu, &contextidr_el2); | 50 | } |
43 | + } | 51 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) |
44 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | 52 | if (!dc_isar_feature(aa64_sve, s)) { |
45 | define_arm_cp_regs(cpu, vhe_reginfo); | 53 | return false; |
54 | } | ||
55 | + s->is_nonstreaming = true; | ||
56 | if (!sve_access_check(s)) { | ||
57 | return true; | ||
58 | } | ||
59 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) | ||
60 | if (!dc_isar_feature(aa64_sve2, s)) { | ||
61 | return false; | ||
62 | } | ||
63 | + s->is_nonstreaming = true; | ||
64 | if (!sve_access_check(s)) { | ||
65 | return true; | ||
66 | } | ||
67 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) | ||
68 | if (!dc_isar_feature(aa64_sve, s)) { | ||
69 | return false; | ||
70 | } | ||
71 | + s->is_nonstreaming = true; | ||
72 | if (!sve_access_check(s)) { | ||
73 | return true; | ||
74 | } | ||
75 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) | ||
76 | if (!dc_isar_feature(aa64_sve, s)) { | ||
77 | return false; | ||
78 | } | ||
79 | + s->is_nonstreaming = true; | ||
80 | if (!sve_access_check(s)) { | ||
81 | return true; | ||
82 | } | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) | ||
84 | if (!dc_isar_feature(aa64_sve2, s)) { | ||
85 | return false; | ||
86 | } | ||
87 | + s->is_nonstreaming = true; | ||
88 | if (!sve_access_check(s)) { | ||
89 | return true; | ||
46 | } | 90 | } |
47 | -- | 91 | -- |
48 | 2.25.1 | 92 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable the n1 for virt and sbsa board use. | 3 | Mark these as a non-streaming instructions, which should trap if full |
4 | a64 support is not enabled in streaming mode. In this case, introduce | ||
5 | PRF_ns (prefetch non-streaming) to handle the checks. | ||
4 | 6 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-25-richard.henderson@linaro.org | 9 | Message-id: 20220708151540.18136-13-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | docs/system/arm/virt.rst | 1 + | 12 | target/arm/sme-fa64.decode | 3 --- |
11 | hw/arm/sbsa-ref.c | 1 + | 13 | target/arm/sve.decode | 10 +++++----- |
12 | hw/arm/virt.c | 1 + | 14 | target/arm/translate-sve.c | 11 +++++++++++ |
13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | 15 | 3 files changed, 16 insertions(+), 8 deletions(-) |
14 | 4 files changed, 69 insertions(+) | ||
15 | 16 | ||
16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 17 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/virt.rst | 19 | --- a/target/arm/sme-fa64.decode |
19 | +++ b/docs/system/arm/virt.rst | 20 | +++ b/target/arm/sme-fa64.decode |
20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | 21 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS |
21 | - ``cortex-a76`` (64-bit) | 22 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) |
22 | - ``a64fx`` (64-bit) | 23 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) |
23 | - ``host`` (with KVM only) | 24 | |
24 | +- ``neoverse-n1`` (64-bit) | 25 | -FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) |
25 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | 26 | -FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) |
26 | 27 | FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) | |
27 | Note that the default is ``cortex-a15``, so for an AArch64 guest you must | 28 | FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) |
28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | 29 | FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) |
30 | FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) | ||
31 | -FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch | ||
32 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/arm/sbsa-ref.c | 34 | --- a/target/arm/sve.decode |
31 | +++ b/hw/arm/sbsa-ref.c | 35 | +++ b/target/arm/sve.decode |
32 | @@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = { | 36 | @@ -XXX,XX +XXX,XX @@ LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \ |
33 | ARM_CPU_TYPE_NAME("cortex-a57"), | 37 | @rpri_load_msz nreg=0 |
34 | ARM_CPU_TYPE_NAME("cortex-a72"), | 38 | |
35 | ARM_CPU_TYPE_NAME("cortex-a76"), | 39 | # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) |
36 | + ARM_CPU_TYPE_NAME("neoverse-n1"), | 40 | -PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- |
37 | ARM_CPU_TYPE_NAME("max"), | 41 | +PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ---- |
38 | }; | 42 | |
39 | 43 | # SVE 32-bit gather prefetch (vector plus immediate) | |
40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 44 | -PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- |
45 | +PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ---- | ||
46 | |||
47 | # SVE contiguous prefetch (scalar plus immediate) | ||
48 | PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- | ||
49 | @@ -XXX,XX +XXX,XX @@ LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ | ||
50 | @rpri_g_load esz=3 | ||
51 | |||
52 | # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) | ||
53 | -PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- | ||
54 | +PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ---- | ||
55 | |||
56 | # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) | ||
57 | -PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- | ||
58 | +PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ---- | ||
59 | |||
60 | # SVE 64-bit gather prefetch (vector plus immediate) | ||
61 | -PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- | ||
62 | +PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ---- | ||
63 | |||
64 | ### SVE Memory Store Group | ||
65 | |||
66 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | 67 | index XXXXXXX..XXXXXXX 100644 |
42 | --- a/hw/arm/virt.c | 68 | --- a/target/arm/translate-sve.c |
43 | +++ b/hw/arm/virt.c | 69 | +++ b/target/arm/translate-sve.c |
44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | 70 | @@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a) |
45 | ARM_CPU_TYPE_NAME("cortex-a72"), | 71 | return true; |
46 | ARM_CPU_TYPE_NAME("cortex-a76"), | ||
47 | ARM_CPU_TYPE_NAME("a64fx"), | ||
48 | + ARM_CPU_TYPE_NAME("neoverse-n1"), | ||
49 | ARM_CPU_TYPE_NAME("host"), | ||
50 | ARM_CPU_TYPE_NAME("max"), | ||
51 | }; | ||
52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/cpu64.c | ||
55 | +++ b/target/arm/cpu64.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj) | ||
57 | cpu->isar.mvfr2 = 0x00000043; | ||
58 | } | 72 | } |
59 | 73 | ||
60 | +static void aarch64_neoverse_n1_initfn(Object *obj) | 74 | +static bool trans_PRF_ns(DisasContext *s, arg_PRF_ns *a) |
61 | +{ | 75 | +{ |
62 | + ARMCPU *cpu = ARM_CPU(obj); | 76 | + if (!dc_isar_feature(aa64_sve, s)) { |
63 | + | 77 | + return false; |
64 | + cpu->dtb_compatible = "arm,neoverse-n1"; | 78 | + } |
65 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 79 | + /* Prefetch is a nop within QEMU. */ |
66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | 80 | + s->is_nonstreaming = true; |
67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | 81 | + (void)sve_access_check(s); |
68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | 82 | + return true; |
69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
73 | + | ||
74 | + /* Ordered by B2.4 AArch64 registers by functional group */ | ||
75 | + cpu->clidr = 0x82000023; | ||
76 | + cpu->ctr = 0x8444c004; | ||
77 | + cpu->dcz_blocksize = 4; | ||
78 | + cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; | ||
79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | ||
80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | ||
81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; | ||
82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | ||
83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | ||
84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | ||
85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; | ||
86 | + cpu->id_afr0 = 0x00000000; | ||
87 | + cpu->isar.id_dfr0 = 0x04010088; | ||
88 | + cpu->isar.id_isar0 = 0x02101110; | ||
89 | + cpu->isar.id_isar1 = 0x13112111; | ||
90 | + cpu->isar.id_isar2 = 0x21232042; | ||
91 | + cpu->isar.id_isar3 = 0x01112131; | ||
92 | + cpu->isar.id_isar4 = 0x00010142; | ||
93 | + cpu->isar.id_isar5 = 0x01011121; | ||
94 | + cpu->isar.id_isar6 = 0x00000010; | ||
95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
103 | + cpu->midr = 0x414fd0c1; /* r4p1 */ | ||
104 | + cpu->revidr = 0; | ||
105 | + | ||
106 | + /* From B2.23 CCSIDR_EL1 */ | ||
107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | ||
108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | ||
109 | + cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ | ||
110 | + | ||
111 | + /* From B2.98 SCTLR_EL3 */ | ||
112 | + cpu->reset_sctlr = 0x30c50838; | ||
113 | + | ||
114 | + /* From B4.23 ICH_VTR_EL2 */ | ||
115 | + cpu->gic_num_lrs = 4; | ||
116 | + cpu->gic_vpribits = 5; | ||
117 | + cpu->gic_vprebits = 5; | ||
118 | + | ||
119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | ||
120 | + cpu->isar.mvfr0 = 0x10110222; | ||
121 | + cpu->isar.mvfr1 = 0x13211111; | ||
122 | + cpu->isar.mvfr2 = 0x00000043; | ||
123 | +} | 83 | +} |
124 | + | 84 | + |
125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | 85 | /* |
126 | { | 86 | * Move Prefix |
127 | /* | 87 | * |
128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | ||
129 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | ||
130 | { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | ||
131 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | ||
132 | + { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, | ||
133 | { .name = "max", .initfn = aarch64_max_initfn }, | ||
134 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | ||
135 | { .name = "host", .initfn = aarch64_host_initfn }, | ||
136 | -- | 88 | -- |
137 | 2.25.1 | 89 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark these as a non-streaming instructions, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-14-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/sme-fa64.decode | 2 -- | ||
12 | target/arm/translate-sve.c | 2 ++ | ||
13 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/sme-fa64.decode | ||
18 | +++ b/target/arm/sme-fa64.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
20 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
21 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
22 | |||
23 | -FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) | ||
24 | -FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) | ||
25 | FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) | ||
26 | FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) | ||
27 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/translate-sve.c | ||
30 | +++ b/target/arm/translate-sve.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) | ||
32 | if (!dc_isar_feature(aa64_sve, s)) { | ||
33 | return false; | ||
34 | } | ||
35 | + s->is_nonstreaming = true; | ||
36 | if (sve_access_check(s)) { | ||
37 | TCGv_i64 addr = new_tmp_a64(s); | ||
38 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | ||
39 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) | ||
40 | if (!dc_isar_feature(aa64_sve, s)) { | ||
41 | return false; | ||
42 | } | ||
43 | + s->is_nonstreaming = true; | ||
44 | if (sve_access_check(s)) { | ||
45 | int vsz = vec_full_reg_size(s); | ||
46 | int elements = vsz >> dtype_esz[a->dtype]; | ||
47 | -- | ||
48 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Mark these as a non-streaming instructions, which should trap | ||
4 | if full a64 support is not enabled in streaming mode. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220708151540.18136-15-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/sme-fa64.decode | 3 --- | ||
12 | target/arm/translate-sve.c | 2 ++ | ||
13 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/sme-fa64.decode | ||
18 | +++ b/target/arm/sme-fa64.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS | ||
20 | # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) | ||
21 | # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) | ||
22 | # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) | ||
23 | - | ||
24 | -FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) | ||
25 | -FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) | ||
26 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/translate-sve.c | ||
29 | +++ b/target/arm/translate-sve.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a) | ||
31 | if (a->rm == 31) { | ||
32 | return false; | ||
33 | } | ||
34 | + s->is_nonstreaming = true; | ||
35 | if (sve_access_check(s)) { | ||
36 | TCGv_i64 addr = new_tmp_a64(s); | ||
37 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a) | ||
39 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | ||
40 | return false; | ||
41 | } | ||
42 | + s->is_nonstreaming = true; | ||
43 | if (sve_access_check(s)) { | ||
44 | TCGv_i64 addr = new_tmp_a64(s); | ||
45 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); | ||
46 | -- | ||
47 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Check for and defer any pending virtual SError. | 3 | These functions will be used to verify that the cpu |
4 | is in the correct state for a given instruction. | ||
4 | 5 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-17-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-16-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/helper.h | 1 + | 11 | target/arm/translate-a64.h | 21 +++++++++++++++++++++ |
11 | target/arm/a32.decode | 16 ++++++++------ | 12 | target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++ |
12 | target/arm/t32.decode | 18 ++++++++-------- | 13 | 2 files changed, 55 insertions(+) |
13 | target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-a64.c | 17 +++++++++++++++ | ||
15 | target/arm/translate.c | 23 ++++++++++++++++++++ | ||
16 | 6 files changed, 103 insertions(+), 15 deletions(-) | ||
17 | 14 | ||
18 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 15 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h |
19 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper.h | 17 | --- a/target/arm/translate-a64.h |
21 | +++ b/target/arm/helper.h | 18 | +++ b/target/arm/translate-a64.h |
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env) | 19 | @@ -XXX,XX +XXX,XX @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); |
23 | DEF_HELPER_1(yield, void, env) | 20 | bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
24 | DEF_HELPER_1(pre_hvc, void, env) | 21 | unsigned int imms, unsigned int immr); |
25 | DEF_HELPER_2(pre_smc, void, env, i32) | 22 | bool sve_access_check(DisasContext *s); |
26 | +DEF_HELPER_1(vesb, void, env) | 23 | +bool sme_enabled_check(DisasContext *s); |
27 | 24 | +bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); | |
28 | DEF_HELPER_3(cpsr_write, void, env, i32, i32) | ||
29 | DEF_HELPER_2(cpsr_write_eret, void, env, i32) | ||
30 | diff --git a/target/arm/a32.decode b/target/arm/a32.decode | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/a32.decode | ||
33 | +++ b/target/arm/a32.decode | ||
34 | @@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn | ||
35 | |||
36 | { | ||
37 | { | ||
38 | - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 | ||
39 | - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 | ||
40 | - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 | ||
41 | + [ | ||
42 | + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 | ||
43 | + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 | ||
44 | + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 | ||
45 | |||
46 | - # TODO: Implement SEV, SEVL; may help SMP performance. | ||
47 | - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 | ||
48 | - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 | ||
49 | + # TODO: Implement SEV, SEVL; may help SMP performance. | ||
50 | + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 | ||
51 | + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 | ||
52 | + | 25 | + |
53 | + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 | 26 | +/* This function corresponds to CheckStreamingSVEEnabled. */ |
54 | + ] | 27 | +static inline bool sme_sm_enabled_check(DisasContext *s) |
55 | 28 | +{ | |
56 | # The canonical nop ends in 00000000, but the whole of the | 29 | + return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK); |
57 | # rest of the space executes as nop if otherwise unsupported. | 30 | +} |
58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/t32.decode | ||
61 | +++ b/target/arm/t32.decode | ||
62 | @@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm | ||
63 | [ | ||
64 | # Hints, and CPS | ||
65 | { | ||
66 | - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | ||
67 | - WFE 1111 0011 1010 1111 1000 0000 0000 0010 | ||
68 | - WFI 1111 0011 1010 1111 1000 0000 0000 0011 | ||
69 | + [ | ||
70 | + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | ||
71 | + WFE 1111 0011 1010 1111 1000 0000 0000 0010 | ||
72 | + WFI 1111 0011 1010 1111 1000 0000 0000 0011 | ||
73 | |||
74 | - # TODO: Implement SEV, SEVL; may help SMP performance. | ||
75 | - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
76 | - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
77 | + # TODO: Implement SEV, SEVL; may help SMP performance. | ||
78 | + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
79 | + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
80 | |||
81 | - # For M-profile minimal-RAS ESB can be a NOP, which is the | ||
82 | - # default behaviour since it is in the hint space. | ||
83 | - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
84 | + ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
85 | + ] | ||
86 | |||
87 | # The canonical nop ends in 0000 0000, but the whole rest | ||
88 | # of the space is "reserved hint, behaves as nop". | ||
89 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
90 | index XXXXXXX..XXXXXXX 100644 | ||
91 | --- a/target/arm/op_helper.c | ||
92 | +++ b/target/arm/op_helper.c | ||
93 | @@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, | ||
94 | access_type, mmu_idx, ra); | ||
95 | } | ||
96 | } | ||
97 | + | 31 | + |
98 | +/* | 32 | +/* This function corresponds to CheckSMEAndZAEnabled. */ |
99 | + * This function corresponds to AArch64.vESBOperation(). | 33 | +static inline bool sme_za_enabled_check(DisasContext *s) |
100 | + * Note that the AArch32 version is not functionally different. | ||
101 | + */ | ||
102 | +void HELPER(vesb)(CPUARMState *env) | ||
103 | +{ | 34 | +{ |
104 | + /* | 35 | + return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK); |
105 | + * The EL2Enabled() check is done inside arm_hcr_el2_eff, | 36 | +} |
106 | + * and will return HCR_EL2.VSE == 0, so nothing happens. | ||
107 | + */ | ||
108 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
109 | + bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO); | ||
110 | + bool pending = enabled && (hcr & HCR_VSE); | ||
111 | + bool masked = (env->daif & PSTATE_A); | ||
112 | + | 37 | + |
113 | + /* If VSE pending and masked, defer the exception. */ | 38 | +/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */ |
114 | + if (pending && masked) { | 39 | +static inline bool sme_smza_enabled_check(DisasContext *s) |
115 | + uint32_t syndrome; | 40 | +{ |
41 | + return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); | ||
42 | +} | ||
116 | + | 43 | + |
117 | + if (arm_el_is_aa64(env, 1)) { | 44 | TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); |
118 | + /* Copy across IDS and ISS from VSESR. */ | 45 | TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, |
119 | + syndrome = env->cp15.vsesr_el2 & 0x1ffffff; | 46 | bool tag_checked, int log2_size); |
120 | + } else { | ||
121 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal }; | ||
122 | + | ||
123 | + if (extended_addresses_enabled(env)) { | ||
124 | + syndrome = arm_fi_to_lfsc(&fi); | ||
125 | + } else { | ||
126 | + syndrome = arm_fi_to_sfsc(&fi); | ||
127 | + } | ||
128 | + /* Copy across AET and ExT from VSESR. */ | ||
129 | + syndrome |= env->cp15.vsesr_el2 & 0xd000; | ||
130 | + } | ||
131 | + | ||
132 | + /* Set VDISR_EL2.A along with the syndrome. */ | ||
133 | + env->cp15.vdisr_el2 = syndrome | (1u << 31); | ||
134 | + | ||
135 | + /* Clear pending virtual SError */ | ||
136 | + env->cp15.hcr_el2 &= ~HCR_VSE; | ||
137 | + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); | ||
138 | + } | ||
139 | +} | ||
140 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 47 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
141 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
142 | --- a/target/arm/translate-a64.c | 49 | --- a/target/arm/translate-a64.c |
143 | +++ b/target/arm/translate-a64.c | 50 | +++ b/target/arm/translate-a64.c |
144 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, | 51 | @@ -XXX,XX +XXX,XX @@ static bool sme_access_check(DisasContext *s) |
145 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
146 | } | ||
147 | break; | ||
148 | + case 0b10000: /* ESB */ | ||
149 | + /* Without RAS, we must implement this as NOP. */ | ||
150 | + if (dc_isar_feature(aa64_ras, s)) { | ||
151 | + /* | ||
152 | + * QEMU does not have a source of physical SErrors, | ||
153 | + * so we are only concerned with virtual SErrors. | ||
154 | + * The pseudocode in the ARM for this case is | ||
155 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
156 | + * AArch64.vESBOperation(); | ||
157 | + * Most of the condition can be evaluated at translation time. | ||
158 | + * Test for EL2 present, and defer test for SEL2 to runtime. | ||
159 | + */ | ||
160 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
161 | + gen_helper_vesb(cpu_env); | ||
162 | + } | ||
163 | + } | ||
164 | + break; | ||
165 | case 0b11000: /* PACIAZ */ | ||
166 | if (s->pauth_active) { | ||
167 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | ||
168 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
169 | index XXXXXXX..XXXXXXX 100644 | ||
170 | --- a/target/arm/translate.c | ||
171 | +++ b/target/arm/translate.c | ||
172 | @@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) | ||
173 | return true; | 52 | return true; |
174 | } | 53 | } |
175 | 54 | ||
176 | +static bool trans_ESB(DisasContext *s, arg_ESB *a) | 55 | +/* This function corresponds to CheckSMEEnabled. */ |
56 | +bool sme_enabled_check(DisasContext *s) | ||
177 | +{ | 57 | +{ |
178 | + /* | 58 | + /* |
179 | + * For M-profile, minimal-RAS ESB can be a NOP. | 59 | + * Note that unlike sve_excp_el, we have not constrained sme_excp_el |
180 | + * Without RAS, we must implement this as NOP. | 60 | + * to be zero when fp_excp_el has priority. This is because we need |
61 | + * sme_excp_el by itself for cpregs access checks. | ||
181 | + */ | 62 | + */ |
182 | + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) { | 63 | + if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) { |
183 | + /* | 64 | + s->fp_access_checked = true; |
184 | + * QEMU does not have a source of physical SErrors, | 65 | + return sme_access_check(s); |
185 | + * so we are only concerned with virtual SErrors. | 66 | + } |
186 | + * The pseudocode in the ARM for this case is | 67 | + return fp_access_check_only(s); |
187 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | 68 | +} |
188 | + * AArch32.vESBOperation(); | 69 | + |
189 | + * Most of the condition can be evaluated at translation time. | 70 | +/* Common subroutine for CheckSMEAnd*Enabled. */ |
190 | + * Test for EL2 present, and defer test for SEL2 to runtime. | 71 | +bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req) |
191 | + */ | 72 | +{ |
192 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | 73 | + if (!sme_enabled_check(s)) { |
193 | + gen_helper_vesb(cpu_env); | 74 | + return false; |
194 | + } | 75 | + } |
76 | + if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) { | ||
77 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
78 | + syn_smetrap(SME_ET_NotStreaming, false)); | ||
79 | + return false; | ||
80 | + } | ||
81 | + if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) { | ||
82 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
83 | + syn_smetrap(SME_ET_InactiveZA, false)); | ||
84 | + return false; | ||
195 | + } | 85 | + } |
196 | + return true; | 86 | + return true; |
197 | +} | 87 | +} |
198 | + | 88 | + |
199 | static bool trans_NOP(DisasContext *s, arg_NOP *a) | 89 | /* |
200 | { | 90 | * This utility function is for doing register extension with an |
201 | return true; | 91 | * optional shift. You will likely want to pass a temporary for the |
202 | -- | 92 | -- |
203 | 2.25.1 | 93 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns not merging memory access, which TCG does | 3 | The pseudocode for CheckSVEEnabled gains a check for Streaming |
4 | not implement. Thus we can trivially enable this feature. | 4 | SVE mode, and for SME present but SVE absent. |
5 | Add a comment to handle_hint for the DGH instruction, but no code. | ||
6 | 5 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-23-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-17-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | docs/system/arm/emulation.rst | 1 + | 11 | target/arm/translate-a64.c | 22 ++++++++++++++++------ |
13 | target/arm/cpu64.c | 1 + | 12 | 1 file changed, 16 insertions(+), 6 deletions(-) |
14 | target/arm/translate-a64.c | 1 + | ||
15 | 3 files changed, 3 insertions(+) | ||
16 | 13 | ||
17 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/docs/system/arm/emulation.rst | ||
20 | +++ b/docs/system/arm/emulation.rst | ||
21 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | ||
23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | ||
24 | - FEAT_CSV3 (Cache speculation variant 3) | ||
25 | +- FEAT_DGH (Data gathering hint) | ||
26 | - FEAT_DIT (Data Independent Timing instructions) | ||
27 | - FEAT_DPB (DC CVAP instruction) | ||
28 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
29 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/cpu64.c | ||
32 | +++ b/target/arm/cpu64.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
34 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | ||
35 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | ||
36 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | ||
37 | + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ | ||
38 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | ||
39 | cpu->isar.id_aa64isar1 = t; | ||
40 | |||
41 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
42 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
43 | --- a/target/arm/translate-a64.c | 16 | --- a/target/arm/translate-a64.c |
44 | +++ b/target/arm/translate-a64.c | 17 | +++ b/target/arm/translate-a64.c |
45 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, | 18 | @@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s) |
46 | break; | 19 | return true; |
47 | case 0b00100: /* SEV */ | 20 | } |
48 | case 0b00101: /* SEVL */ | 21 | |
49 | + case 0b00110: /* DGH */ | 22 | -/* Check that SVE access is enabled. If it is, return true. |
50 | /* we treat all as NOP at least for now */ | 23 | +/* |
51 | break; | 24 | + * Check that SVE access is enabled. If it is, return true. |
52 | case 0b00111: /* XPACLRI */ | 25 | * If not, emit code to generate an appropriate exception and return false. |
26 | + * This function corresponds to CheckSVEEnabled(). | ||
27 | */ | ||
28 | bool sve_access_check(DisasContext *s) | ||
29 | { | ||
30 | - if (s->sve_excp_el) { | ||
31 | - assert(!s->sve_access_checked); | ||
32 | - s->sve_access_checked = true; | ||
33 | - | ||
34 | + if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) { | ||
35 | + assert(dc_isar_feature(aa64_sme, s)); | ||
36 | + if (!sme_sm_enabled_check(s)) { | ||
37 | + goto fail_exit; | ||
38 | + } | ||
39 | + } else if (s->sve_excp_el) { | ||
40 | gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
41 | syn_sve_access_trap(), s->sve_excp_el); | ||
42 | - return false; | ||
43 | + goto fail_exit; | ||
44 | } | ||
45 | s->sve_access_checked = true; | ||
46 | return fp_access_check(s); | ||
47 | + | ||
48 | + fail_exit: | ||
49 | + /* Assert that we only raise one exception per instruction. */ | ||
50 | + assert(!s->sve_access_checked); | ||
51 | + s->sve_access_checked = true; | ||
52 | + return false; | ||
53 | } | ||
54 | |||
55 | /* | ||
53 | -- | 56 | -- |
54 | 2.25.1 | 57 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Virtual SError exceptions are raised by setting HCR_EL2.VSE, | 3 | These SME instructions are nominally within the SVE decode space, |
4 | and are routed to EL1 just like other virtual exceptions. | 4 | so we add them to sve.decode and translate-sve.c. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-16-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-18-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/cpu.h | 2 ++ | 11 | target/arm/translate-a64.h | 12 ++++++++++++ |
12 | target/arm/internals.h | 8 ++++++++ | 12 | target/arm/sve.decode | 5 ++++- |
13 | target/arm/syndrome.h | 5 +++++ | 13 | target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++ |
14 | target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- | 14 | 3 files changed, 54 insertions(+), 1 deletion(-) |
15 | target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- | ||
16 | 5 files changed, 91 insertions(+), 2 deletions(-) | ||
17 | 15 | ||
18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h |
19 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/cpu.h | 18 | --- a/target/arm/translate-a64.h |
21 | +++ b/target/arm/cpu.h | 19 | +++ b/target/arm/translate-a64.h |
22 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s) |
23 | #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ | 21 | return s->vl; |
24 | #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ | ||
25 | #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ | ||
26 | +#define EXCP_VSERR 24 | ||
27 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ | ||
28 | |||
29 | #define ARMV7M_EXCP_RESET 1 | ||
30 | @@ -XXX,XX +XXX,XX @@ enum { | ||
31 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | ||
32 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 | ||
33 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 | ||
34 | +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 | ||
35 | |||
36 | /* The usual mapping for an AArch64 system register to its AArch32 | ||
37 | * counterpart is for the 32 bit world to have access to the lower | ||
38 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/internals.h | ||
41 | +++ b/target/arm/internals.h | ||
42 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu); | ||
43 | */ | ||
44 | void arm_cpu_update_vfiq(ARMCPU *cpu); | ||
45 | |||
46 | +/** | ||
47 | + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit | ||
48 | + * | ||
49 | + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, | ||
50 | + * following a change to the HCR_EL2.VSE bit. | ||
51 | + */ | ||
52 | +void arm_cpu_update_vserr(ARMCPU *cpu); | ||
53 | + | ||
54 | /** | ||
55 | * arm_mmu_idx_el: | ||
56 | * @env: The cpu environment | ||
57 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/target/arm/syndrome.h | ||
60 | +++ b/target/arm/syndrome.h | ||
61 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void) | ||
62 | return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; | ||
63 | } | 22 | } |
64 | 23 | ||
65 | +static inline uint32_t syn_serror(uint32_t extra) | 24 | +/* Return the byte size of the vector register, SVL / 8. */ |
25 | +static inline int streaming_vec_reg_size(DisasContext *s) | ||
66 | +{ | 26 | +{ |
67 | + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; | 27 | + return s->svl; |
68 | +} | 28 | +} |
69 | + | 29 | + |
70 | #endif /* TARGET_ARM_SYNDROME_H */ | 30 | /* |
71 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 31 | * Return the offset info CPUARMState of the predicate vector register Pn. |
72 | index XXXXXXX..XXXXXXX 100644 | 32 | * Note for this purpose, FFR is P16. |
73 | --- a/target/arm/cpu.c | 33 | @@ -XXX,XX +XXX,XX @@ static inline int pred_full_reg_size(DisasContext *s) |
74 | +++ b/target/arm/cpu.c | 34 | return s->vl >> 3; |
75 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs) | ||
76 | return (cpu->power_state != PSCI_OFF) | ||
77 | && cs->interrupt_request & | ||
78 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | ||
79 | - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | ||
80 | + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | ||
81 | | CPU_INTERRUPT_EXITTB); | ||
82 | } | 35 | } |
83 | 36 | ||
84 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | 37 | +/* Return the byte size of the predicate register, SVL / 64. */ |
85 | return false; | 38 | +static inline int streaming_pred_reg_size(DisasContext *s) |
86 | } | ||
87 | return !(env->daif & PSTATE_I); | ||
88 | + case EXCP_VSERR: | ||
89 | + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { | ||
90 | + /* VIRQs are only taken when hypervized. */ | ||
91 | + return false; | ||
92 | + } | ||
93 | + return !(env->daif & PSTATE_A); | ||
94 | default: | ||
95 | g_assert_not_reached(); | ||
96 | } | ||
97 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | ||
98 | goto found; | ||
99 | } | ||
100 | } | ||
101 | + if (interrupt_request & CPU_INTERRUPT_VSERR) { | ||
102 | + excp_idx = EXCP_VSERR; | ||
103 | + target_el = 1; | ||
104 | + if (arm_excp_unmasked(cs, excp_idx, target_el, | ||
105 | + cur_el, secure, hcr_el2)) { | ||
106 | + /* Taking a virtual abort clears HCR_EL2.VSE */ | ||
107 | + env->cp15.hcr_el2 &= ~HCR_VSE; | ||
108 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
109 | + goto found; | ||
110 | + } | ||
111 | + } | ||
112 | return false; | ||
113 | |||
114 | found: | ||
115 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu) | ||
116 | } | ||
117 | } | ||
118 | |||
119 | +void arm_cpu_update_vserr(ARMCPU *cpu) | ||
120 | +{ | 39 | +{ |
121 | + /* | 40 | + return s->svl >> 3; |
122 | + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. | ||
123 | + */ | ||
124 | + CPUARMState *env = &cpu->env; | ||
125 | + CPUState *cs = CPU(cpu); | ||
126 | + | ||
127 | + bool new_state = env->cp15.hcr_el2 & HCR_VSE; | ||
128 | + | ||
129 | + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { | ||
130 | + if (new_state) { | ||
131 | + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
132 | + } else { | ||
133 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
134 | + } | ||
135 | + } | ||
136 | +} | 41 | +} |
137 | + | 42 | + |
138 | #ifndef CONFIG_USER_ONLY | 43 | /* |
139 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | 44 | * Round up the size of a register to a size allowed by |
45 | * the tcg vector infrastructure. Any operation which uses this | ||
46 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/sve.decode | ||
49 | +++ b/target/arm/sve.decode | ||
50 | @@ -XXX,XX +XXX,XX @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | ||
51 | # SVE index generation (register start, register increment) | ||
52 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | ||
53 | |||
54 | -### SVE Stack Allocation Group | ||
55 | +### SVE / Streaming SVE Stack Allocation Group | ||
56 | |||
57 | # SVE stack frame adjustment | ||
58 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | ||
59 | +ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 | ||
60 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | ||
61 | +ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 | ||
62 | |||
63 | # SVE stack frame size | ||
64 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | ||
65 | +RDSVL 00000100 101 11111 01011 imm:s6 rd:5 | ||
66 | |||
67 | ### SVE Bitwise Shift - Unpredicated Group | ||
68 | |||
69 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/target/arm/translate-sve.c | ||
72 | +++ b/target/arm/translate-sve.c | ||
73 | @@ -XXX,XX +XXX,XX @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) | ||
74 | return true; | ||
75 | } | ||
76 | |||
77 | +static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a) | ||
78 | +{ | ||
79 | + if (!dc_isar_feature(aa64_sme, s)) { | ||
80 | + return false; | ||
81 | + } | ||
82 | + if (sme_enabled_check(s)) { | ||
83 | + TCGv_i64 rd = cpu_reg_sp(s, a->rd); | ||
84 | + TCGv_i64 rn = cpu_reg_sp(s, a->rn); | ||
85 | + tcg_gen_addi_i64(rd, rn, a->imm * streaming_vec_reg_size(s)); | ||
86 | + } | ||
87 | + return true; | ||
88 | +} | ||
89 | + | ||
90 | static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) | ||
140 | { | 91 | { |
141 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 92 | if (!dc_isar_feature(aa64_sve, s)) { |
142 | index XXXXXXX..XXXXXXX 100644 | 93 | @@ -XXX,XX +XXX,XX @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) |
143 | --- a/target/arm/helper.c | 94 | return true; |
144 | +++ b/target/arm/helper.c | 95 | } |
145 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 96 | |
146 | } | 97 | +static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a) |
147 | } | 98 | +{ |
148 | 99 | + if (!dc_isar_feature(aa64_sme, s)) { | |
149 | - /* External aborts are not possible in QEMU so A bit is always clear */ | 100 | + return false; |
150 | + if (hcr_el2 & HCR_AMO) { | ||
151 | + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { | ||
152 | + ret |= CPSR_A; | ||
153 | + } | ||
154 | + } | 101 | + } |
102 | + if (sme_enabled_check(s)) { | ||
103 | + TCGv_i64 rd = cpu_reg_sp(s, a->rd); | ||
104 | + TCGv_i64 rn = cpu_reg_sp(s, a->rn); | ||
105 | + tcg_gen_addi_i64(rd, rn, a->imm * streaming_pred_reg_size(s)); | ||
106 | + } | ||
107 | + return true; | ||
108 | +} | ||
155 | + | 109 | + |
156 | return ret; | 110 | static bool trans_RDVL(DisasContext *s, arg_RDVL *a) |
111 | { | ||
112 | if (!dc_isar_feature(aa64_sve, s)) { | ||
113 | @@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a) | ||
114 | return true; | ||
157 | } | 115 | } |
158 | 116 | ||
159 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | 117 | +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a) |
160 | g_assert(qemu_mutex_iothread_locked()); | 118 | +{ |
161 | arm_cpu_update_virq(cpu); | 119 | + if (!dc_isar_feature(aa64_sme, s)) { |
162 | arm_cpu_update_vfiq(cpu); | 120 | + return false; |
163 | + arm_cpu_update_vserr(cpu); | 121 | + } |
164 | } | 122 | + if (sme_enabled_check(s)) { |
165 | 123 | + TCGv_i64 reg = cpu_reg(s, a->rd); | |
166 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 124 | + tcg_gen_movi_i64(reg, a->imm * streaming_vec_reg_size(s)); |
167 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs) | 125 | + } |
168 | [EXCP_LSERR] = "v8M LSERR UsageFault", | 126 | + return true; |
169 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | 127 | +} |
170 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", | ||
171 | + [EXCP_VSERR] = "Virtual SERR", | ||
172 | }; | ||
173 | |||
174 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | ||
175 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) | ||
176 | mask = CPSR_A | CPSR_I | CPSR_F; | ||
177 | offset = 4; | ||
178 | break; | ||
179 | + case EXCP_VSERR: | ||
180 | + { | ||
181 | + /* | ||
182 | + * Note that this is reported as a data abort, but the DFAR | ||
183 | + * has an UNKNOWN value. Construct the SError syndrome from | ||
184 | + * AET and ExT fields. | ||
185 | + */ | ||
186 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; | ||
187 | + | 128 | + |
188 | + if (extended_addresses_enabled(env)) { | 129 | /* |
189 | + env->exception.fsr = arm_fi_to_lfsc(&fi); | 130 | *** SVE Compute Vector Address Group |
190 | + } else { | 131 | */ |
191 | + env->exception.fsr = arm_fi_to_sfsc(&fi); | ||
192 | + } | ||
193 | + env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; | ||
194 | + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); | ||
195 | + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", | ||
196 | + env->exception.fsr); | ||
197 | + | ||
198 | + new_mode = ARM_CPU_MODE_ABT; | ||
199 | + addr = 0x10; | ||
200 | + mask = CPSR_A | CPSR_I; | ||
201 | + offset = 8; | ||
202 | + } | ||
203 | + break; | ||
204 | case EXCP_SMC: | ||
205 | new_mode = ARM_CPU_MODE_MON; | ||
206 | addr = 0x08; | ||
207 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
208 | case EXCP_VFIQ: | ||
209 | addr += 0x100; | ||
210 | break; | ||
211 | + case EXCP_VSERR: | ||
212 | + addr += 0x180; | ||
213 | + /* Construct the SError syndrome from IDS and ISS fields. */ | ||
214 | + env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | ||
215 | + env->cp15.esr_el[new_el] = env->exception.syndrome; | ||
216 | + break; | ||
217 | default: | ||
218 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | ||
219 | } | ||
220 | -- | 132 | -- |
221 | 2.25.1 | 133 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | In aarch64_numa_cpu(), the CPU and NUMA association is something | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | like below. Two threads in the same core/cluster/socket are | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | associated with two individual NUMA nodes, which is unreal as | 5 | Message-id: 20220708151540.18136-19-richard.henderson@linaro.org |
6 | Igor Mammedov mentioned. We don't expect the association to break | ||
7 | NUMA-to-socket boundary, which matches with the real world. | ||
8 | |||
9 | NUMA-node socket cluster core thread | ||
10 | ------------------------------------------ | ||
11 | 0 0 0 0 0 | ||
12 | 1 0 0 0 1 | ||
13 | |||
14 | This corrects the topology for CPUs and their association with | ||
15 | NUMA nodes. After this patch is applied, the CPU and NUMA | ||
16 | association becomes something like below, which looks real. | ||
17 | Besides, socket/cluster/core/thread IDs are all checked when | ||
18 | the NUMA node IDs are verified. It helps to check if the CPU | ||
19 | topology is properly populated or not. | ||
20 | |||
21 | NUMA-node socket cluster core thread | ||
22 | ------------------------------------------ | ||
23 | 0 1 0 0 0 | ||
24 | 1 0 0 0 0 | ||
25 | |||
26 | Suggested-by: Igor Mammedov <imammedo@redhat.com> | ||
27 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
28 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
29 | Message-id: 20220503140304.855514-5-gshan@redhat.com | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | --- | 7 | --- |
32 | tests/qtest/numa-test.c | 18 ++++++++++++------ | 8 | target/arm/helper-sme.h | 2 ++ |
33 | 1 file changed, 12 insertions(+), 6 deletions(-) | 9 | target/arm/sme.decode | 4 ++++ |
10 | target/arm/sme_helper.c | 25 +++++++++++++++++++++++++ | ||
11 | target/arm/translate-sme.c | 13 +++++++++++++ | ||
12 | 4 files changed, 44 insertions(+) | ||
34 | 13 | ||
35 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c | 14 | diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h |
36 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/tests/qtest/numa-test.c | 16 | --- a/target/arm/helper-sme.h |
38 | +++ b/tests/qtest/numa-test.c | 17 | +++ b/target/arm/helper-sme.h |
39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | 18 | @@ -XXX,XX +XXX,XX @@ |
40 | g_autofree char *cli = NULL; | 19 | |
41 | 20 | DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) | |
42 | cli = make_cli(data, "-machine " | 21 | DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) |
43 | - "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " | 22 | + |
44 | + "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 " | 23 | +DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) |
45 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " | 24 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode |
46 | - "-numa cpu,node-id=1,thread-id=0 " | 25 | index XXXXXXX..XXXXXXX 100644 |
47 | - "-numa cpu,node-id=0,thread-id=1"); | 26 | --- a/target/arm/sme.decode |
48 | + "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 " | 27 | +++ b/target/arm/sme.decode |
49 | + "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0"); | 28 | @@ -XXX,XX +XXX,XX @@ |
50 | qts = qtest_init(cli); | 29 | # |
51 | cpus = get_cpus(qts, &resp); | 30 | # This file is processed by scripts/decodetree.py |
52 | g_assert(cpus); | 31 | # |
53 | 32 | + | |
54 | while ((e = qlist_pop(cpus))) { | 33 | +### SME Misc |
55 | QDict *cpu, *props; | 34 | + |
56 | - int64_t thread, node; | 35 | +ZERO 11000000 00 001 00000000000 imm:8 |
57 | + int64_t socket, cluster, core, thread, node; | 36 | diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c |
58 | 37 | index XXXXXXX..XXXXXXX 100644 | |
59 | cpu = qobject_to(QDict, e); | 38 | --- a/target/arm/sme_helper.c |
60 | g_assert(qdict_haskey(cpu, "props")); | 39 | +++ b/target/arm/sme_helper.c |
61 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | 40 | @@ -XXX,XX +XXX,XX @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) |
62 | 41 | memset(env->zarray, 0, sizeof(env->zarray)); | |
63 | g_assert(qdict_haskey(props, "node-id")); | 42 | } |
64 | node = qdict_get_int(props, "node-id"); | 43 | } |
65 | + g_assert(qdict_haskey(props, "socket-id")); | 44 | + |
66 | + socket = qdict_get_int(props, "socket-id"); | 45 | +void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) |
67 | + g_assert(qdict_haskey(props, "cluster-id")); | 46 | +{ |
68 | + cluster = qdict_get_int(props, "cluster-id"); | 47 | + uint32_t i; |
69 | + g_assert(qdict_haskey(props, "core-id")); | 48 | + |
70 | + core = qdict_get_int(props, "core-id"); | 49 | + /* |
71 | g_assert(qdict_haskey(props, "thread-id")); | 50 | + * Special case clearing the entire ZA space. |
72 | thread = qdict_get_int(props, "thread-id"); | 51 | + * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any |
73 | 52 | + * parts of the ZA storage outside of SVL. | |
74 | - if (thread == 0) { | 53 | + */ |
75 | + if (socket == 0 && cluster == 0 && core == 0 && thread == 0) { | 54 | + if (imm == 0xff) { |
76 | g_assert_cmpint(node, ==, 1); | 55 | + memset(env->zarray, 0, sizeof(env->zarray)); |
77 | - } else if (thread == 1) { | 56 | + return; |
78 | + } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) { | 57 | + } |
79 | g_assert_cmpint(node, ==, 0); | 58 | + |
80 | } else { | 59 | + /* |
81 | g_assert(false); | 60 | + * Recall that ZAnH.D[m] is spread across ZA[n+8*m], |
61 | + * so each row is discontiguous within ZA[]. | ||
62 | + */ | ||
63 | + for (i = 0; i < svl; i++) { | ||
64 | + if (imm & (1 << (i % 8))) { | ||
65 | + memset(&env->zarray[i], 0, svl); | ||
66 | + } | ||
67 | + } | ||
68 | +} | ||
69 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/target/arm/translate-sme.c | ||
72 | +++ b/target/arm/translate-sme.c | ||
73 | @@ -XXX,XX +XXX,XX @@ | ||
74 | */ | ||
75 | |||
76 | #include "decode-sme.c.inc" | ||
77 | + | ||
78 | + | ||
79 | +static bool trans_ZERO(DisasContext *s, arg_ZERO *a) | ||
80 | +{ | ||
81 | + if (!dc_isar_feature(aa64_sme, s)) { | ||
82 | + return false; | ||
83 | + } | ||
84 | + if (sme_za_enabled_check(s)) { | ||
85 | + gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm), | ||
86 | + tcg_constant_i32(streaming_vec_reg_size(s))); | ||
87 | + } | ||
88 | + return true; | ||
89 | +} | ||
82 | -- | 90 | -- |
83 | 2.25.1 | 91 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | More gracefully handle cpregs when EL2 and/or EL3 are missing. | 3 | We can reuse the SVE functions for implementing moves to/from |
4 | If the reg is entirely inaccessible, do not register it at all. | 4 | horizontal tile slices, but we need new ones for moves to/from |
5 | If the reg is for EL2, and EL3 is present but EL2 is not, | 5 | vertical tile slices. |
6 | either discard, squash to res0, const, or keep unchanged. | ||
7 | |||
8 | Per rule RJFFP, mark the 4 aarch32 hypervisor access registers | ||
9 | with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address | ||
10 | translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. | ||
11 | Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ. | ||
12 | |||
13 | This will simplify cpreg registration for conditional arm features. | ||
14 | 6 | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
17 | Message-id: 20220506180242.216785-2-richard.henderson@linaro.org | 9 | Message-id: 20220708151540.18136-20-richard.henderson@linaro.org |
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 11 | --- |
20 | target/arm/cpregs.h | 11 +++ | 12 | target/arm/helper-sme.h | 12 +++ |
21 | target/arm/helper.c | 178 ++++++++++++++++++++++++++++++-------------- | 13 | target/arm/helper-sve.h | 2 + |
22 | 2 files changed, 133 insertions(+), 56 deletions(-) | 14 | target/arm/translate-a64.h | 8 ++ |
15 | target/arm/translate.h | 5 ++ | ||
16 | target/arm/sme.decode | 15 ++++ | ||
17 | target/arm/sme_helper.c | 151 ++++++++++++++++++++++++++++++++++++- | ||
18 | target/arm/sve_helper.c | 12 +++ | ||
19 | target/arm/translate-sme.c | 127 +++++++++++++++++++++++++++++++ | ||
20 | 8 files changed, 331 insertions(+), 1 deletion(-) | ||
23 | 21 | ||
24 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 22 | diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h |
25 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpregs.h | 24 | --- a/target/arm/helper-sme.h |
27 | +++ b/target/arm/cpregs.h | 25 | +++ b/target/arm/helper-sme.h |
28 | @@ -XXX,XX +XXX,XX @@ enum { | 26 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) |
29 | ARM_CP_SVE = 1 << 14, | 27 | DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) |
30 | /* Flag: Do not expose in gdb sysreg xml. */ | 28 | |
31 | ARM_CP_NO_GDB = 1 << 15, | 29 | DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) |
32 | + /* | 30 | + |
33 | + * Flags: If EL3 but not EL2... | 31 | +/* Move to/from vertical array slices, i.e. columns, so 'c'. */ |
34 | + * - UNDEF: discard the cpreg, | 32 | +DEF_HELPER_FLAGS_4(sme_mova_cz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
35 | + * - KEEP: retain the cpreg as is, | 33 | +DEF_HELPER_FLAGS_4(sme_mova_zc_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
36 | + * - C_NZ: set const on the cpreg, but retain resetvalue, | 34 | +DEF_HELPER_FLAGS_4(sme_mova_cz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
37 | + * - else: set const on the cpreg, zero resetvalue, aka RES0. | 35 | +DEF_HELPER_FLAGS_4(sme_mova_zc_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
38 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | 36 | +DEF_HELPER_FLAGS_4(sme_mova_cz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
39 | + */ | 37 | +DEF_HELPER_FLAGS_4(sme_mova_zc_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
40 | + ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, | 38 | +DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
41 | + ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, | 39 | +DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
42 | + ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, | 40 | +DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
43 | }; | 41 | +DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
44 | 42 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | |
45 | /* | 43 | index XXXXXXX..XXXXXXX 100644 |
46 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 44 | --- a/target/arm/helper-sve.h |
47 | index XXXXXXX..XXXXXXX 100644 | 45 | +++ b/target/arm/helper-sve.h |
48 | --- a/target/arm/helper.c | 46 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG, |
49 | +++ b/target/arm/helper.c | 47 | void, ptr, ptr, ptr, ptr, i32) |
50 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 48 | DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG, |
51 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, | 49 | void, ptr, ptr, ptr, ptr, i32) |
52 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, | 50 | +DEF_HELPER_FLAGS_5(sve_sel_zpzz_q, TCG_CALL_NO_RWG, |
53 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | 51 | + void, ptr, ptr, ptr, ptr, i32) |
54 | - .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU, | 52 | |
55 | + .access = PL2_RW, | 53 | DEF_HELPER_FLAGS_5(sve2_addp_zpzz_b, TCG_CALL_NO_RWG, |
56 | + .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | 54 | void, ptr, ptr, ptr, ptr, i32) |
57 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, | 55 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h |
58 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, | 56 | index XXXXXXX..XXXXXXX 100644 |
59 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | 57 | --- a/target/arm/translate-a64.h |
60 | - .access = PL2_RW, .resetvalue = 0, | 58 | +++ b/target/arm/translate-a64.h |
61 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | 59 | @@ -XXX,XX +XXX,XX @@ static inline int pred_gvec_reg_size(DisasContext *s) |
62 | .writefn = dacr_write, .raw_writefn = raw_write, | 60 | return size_for_gvec(pred_full_reg_size(s)); |
63 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | 61 | } |
64 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | 62 | |
65 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | 63 | +/* Return a newly allocated pointer to the predicate register. */ |
66 | - .access = PL2_RW, .resetvalue = 0, | 64 | +static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) |
67 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | 65 | +{ |
68 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | 66 | + TCGv_ptr ret = tcg_temp_new_ptr(); |
69 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | 67 | + tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); |
70 | .type = ARM_CP_ALIAS, | 68 | + return ret; |
71 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | 69 | +} |
72 | .writefn = tlbimva_hyp_is_write }, | 70 | + |
73 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, | 71 | bool disas_sve(DisasContext *, uint32_t); |
74 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | 72 | bool disas_sme(DisasContext *, uint32_t); |
75 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | 73 | |
76 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | 74 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
77 | .writefn = tlbi_aa64_alle2_write }, | 75 | index XXXXXXX..XXXXXXX 100644 |
78 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, | 76 | --- a/target/arm/translate.h |
79 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | 77 | +++ b/target/arm/translate.h |
80 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | 78 | @@ -XXX,XX +XXX,XX @@ static inline int plus_2(DisasContext *s, int x) |
81 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | 79 | return x + 2; |
82 | .writefn = tlbi_aa64_vae2_write }, | 80 | } |
83 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, | 81 | |
84 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | 82 | +static inline int plus_12(DisasContext *s, int x) |
85 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | 83 | +{ |
86 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | 84 | + return x + 12; |
87 | .writefn = tlbi_aa64_vae2_write }, | 85 | +} |
88 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | 86 | + |
89 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | 87 | static inline int times_2(DisasContext *s, int x) |
90 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
91 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
92 | .writefn = tlbi_aa64_alle2is_write }, | ||
93 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, | ||
94 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | ||
95 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
96 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
97 | .writefn = tlbi_aa64_vae2is_write }, | ||
98 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, | ||
99 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | ||
100 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
101 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
102 | .writefn = tlbi_aa64_vae2is_write }, | ||
103 | #ifndef CONFIG_USER_ONLY | ||
104 | /* Unlike the other EL2-related AT operations, these must | ||
105 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
106 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | ||
108 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
109 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
110 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
111 | + .writefn = ats_write64 }, | ||
112 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | ||
113 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | ||
114 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
115 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
116 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
117 | + .writefn = ats_write64 }, | ||
118 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE | ||
119 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | ||
120 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | ||
121 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
122 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | ||
123 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | ||
124 | .access = PL2_RW, .accessfn = access_tda, | ||
125 | - .type = ARM_CP_NOP }, | ||
126 | + .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, | ||
127 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
128 | * Channel but Linux may try to access this register. The 32-bit | ||
129 | * alias is DBGDCCINT. | ||
130 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
131 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
132 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, | ||
133 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | ||
134 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
135 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
136 | .writefn = tlbi_aa64_rvae2is_write }, | ||
137 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | ||
138 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | ||
139 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
140 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
141 | .writefn = tlbi_aa64_rvae2is_write }, | ||
142 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | ||
143 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | ||
144 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
145 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
146 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, | ||
147 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | ||
148 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
149 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
150 | .writefn = tlbi_aa64_rvae2is_write }, | ||
151 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | ||
152 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | ||
153 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
154 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
155 | .writefn = tlbi_aa64_rvae2is_write }, | ||
156 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | ||
157 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | ||
158 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
159 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
160 | .writefn = tlbi_aa64_rvae2_write }, | ||
161 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | ||
162 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | ||
163 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
164 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
165 | .writefn = tlbi_aa64_rvae2_write }, | ||
166 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | ||
167 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | ||
168 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
169 | .writefn = tlbi_aa64_vae1is_write }, | ||
170 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, | ||
171 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | ||
172 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
173 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
174 | .writefn = tlbi_aa64_alle2is_write }, | ||
175 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, | ||
176 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | ||
177 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
178 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
179 | .writefn = tlbi_aa64_vae2is_write }, | ||
180 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, | ||
181 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | ||
182 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
183 | .writefn = tlbi_aa64_alle1is_write }, | ||
184 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, | ||
185 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | ||
186 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
187 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
188 | .writefn = tlbi_aa64_vae2is_write }, | ||
189 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, | ||
190 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | ||
191 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
192 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
193 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
194 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
195 | - .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, | ||
196 | + .resetvalue = cpu->midr, | ||
197 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
198 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | ||
199 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
200 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
201 | .access = PL2_RW, .resetvalue = cpu->midr, | ||
202 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
203 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
204 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, | ||
205 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
206 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
207 | - .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, | ||
208 | + .resetvalue = vmpidr_def, | ||
209 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
210 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | ||
211 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
212 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
213 | - .access = PL2_RW, | ||
214 | - .resetvalue = vmpidr_def, | ||
215 | + .access = PL2_RW, .resetvalue = vmpidr_def, | ||
216 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
217 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | ||
218 | }; | ||
219 | define_arm_cp_regs(cpu, vpidr_regs); | ||
220 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
221 | int crm, int opc1, int opc2, | ||
222 | const char *name) | ||
223 | { | 88 | { |
224 | + CPUARMState *env = &cpu->env; | 89 | return x * 2; |
225 | uint32_t key; | 90 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode |
226 | ARMCPRegInfo *r2; | 91 | index XXXXXXX..XXXXXXX 100644 |
227 | bool is64 = r->type & ARM_CP_64BIT; | 92 | --- a/target/arm/sme.decode |
228 | bool ns = secstate & ARM_CP_SECSTATE_NS; | 93 | +++ b/target/arm/sme.decode |
229 | int cp = r->cp; | 94 | @@ -XXX,XX +XXX,XX @@ |
230 | - bool isbanked; | 95 | ### SME Misc |
231 | size_t name_len; | 96 | |
232 | + bool make_const; | 97 | ZERO 11000000 00 001 00000000000 imm:8 |
233 | 98 | + | |
234 | switch (state) { | 99 | +### SME Move into/from Array |
235 | case ARM_CP_STATE_AA32: | 100 | + |
236 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 101 | +%mova_rs 13:2 !function=plus_12 |
102 | +&mova esz rs pg zr za_imm v:bool to_vec:bool | ||
103 | + | ||
104 | +MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \ | ||
105 | + &mova to_vec=0 rs=%mova_rs | ||
106 | +MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \ | ||
107 | + &mova to_vec=0 rs=%mova_rs esz=4 | ||
108 | + | ||
109 | +MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ | ||
110 | + &mova to_vec=1 rs=%mova_rs | ||
111 | +MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ | ||
112 | + &mova to_vec=1 rs=%mova_rs esz=4 | ||
113 | diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c | ||
114 | index XXXXXXX..XXXXXXX 100644 | ||
115 | --- a/target/arm/sme_helper.c | ||
116 | +++ b/target/arm/sme_helper.c | ||
117 | @@ -XXX,XX +XXX,XX @@ | ||
118 | |||
119 | #include "qemu/osdep.h" | ||
120 | #include "cpu.h" | ||
121 | -#include "internals.h" | ||
122 | +#include "tcg/tcg-gvec-desc.h" | ||
123 | #include "exec/helper-proto.h" | ||
124 | +#include "qemu/int128.h" | ||
125 | +#include "vec_internal.h" | ||
126 | |||
127 | /* ResetSVEState */ | ||
128 | void arm_reset_sve_state(CPUARMState *env) | ||
129 | @@ -XXX,XX +XXX,XX @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) | ||
237 | } | 130 | } |
238 | } | 131 | } |
239 | 132 | } | |
133 | + | ||
134 | + | ||
135 | +/* | ||
136 | + * When considering the ZA storage as an array of elements of | ||
137 | + * type T, the index within that array of the Nth element of | ||
138 | + * a vertical slice of a tile can be calculated like this, | ||
139 | + * regardless of the size of type T. This is because the tiles | ||
140 | + * are interleaved, so if type T is size N bytes then row 1 of | ||
141 | + * the tile is N rows away from row 0. The division by N to | ||
142 | + * convert a byte offset into an array index and the multiplication | ||
143 | + * by N to convert from vslice-index-within-the-tile to | ||
144 | + * the index within the ZA storage cancel out. | ||
145 | + */ | ||
146 | +#define tile_vslice_index(i) ((i) * sizeof(ARMVectorReg)) | ||
147 | + | ||
148 | +/* | ||
149 | + * When doing byte arithmetic on the ZA storage, the element | ||
150 | + * byteoff bytes away in a tile vertical slice is always this | ||
151 | + * many bytes away in the ZA storage, regardless of the | ||
152 | + * size of the tile element, assuming that byteoff is a multiple | ||
153 | + * of the element size. Again this is because of the interleaving | ||
154 | + * of the tiles. For instance if we have 1 byte per element then | ||
155 | + * each row of the ZA storage has one byte of the vslice data, | ||
156 | + * and (counting from 0) byte 8 goes in row 8 of the storage | ||
157 | + * at offset (8 * row-size-in-bytes). | ||
158 | + * If we have 8 bytes per element then each row of the ZA storage | ||
159 | + * has 8 bytes of the data, but there are 8 interleaved tiles and | ||
160 | + * so byte 8 of the data goes into row 1 of the tile, | ||
161 | + * which is again row 8 of the storage, so the offset is still | ||
162 | + * (8 * row-size-in-bytes). Similarly for other element sizes. | ||
163 | + */ | ||
164 | +#define tile_vslice_offset(byteoff) ((byteoff) * sizeof(ARMVectorReg)) | ||
165 | + | ||
166 | + | ||
167 | +/* | ||
168 | + * Move Zreg vector to ZArray column. | ||
169 | + */ | ||
170 | +#define DO_MOVA_C(NAME, TYPE, H) \ | ||
171 | +void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc) \ | ||
172 | +{ \ | ||
173 | + int i, oprsz = simd_oprsz(desc); \ | ||
174 | + for (i = 0; i < oprsz; ) { \ | ||
175 | + uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \ | ||
176 | + do { \ | ||
177 | + if (pg & 1) { \ | ||
178 | + *(TYPE *)(za + tile_vslice_offset(i)) = *(TYPE *)(vn + H(i)); \ | ||
179 | + } \ | ||
180 | + i += sizeof(TYPE); \ | ||
181 | + pg >>= sizeof(TYPE); \ | ||
182 | + } while (i & 15); \ | ||
183 | + } \ | ||
184 | +} | ||
185 | + | ||
186 | +DO_MOVA_C(sme_mova_cz_b, uint8_t, H1) | ||
187 | +DO_MOVA_C(sme_mova_cz_h, uint16_t, H1_2) | ||
188 | +DO_MOVA_C(sme_mova_cz_s, uint32_t, H1_4) | ||
189 | + | ||
190 | +void HELPER(sme_mova_cz_d)(void *za, void *vn, void *vg, uint32_t desc) | ||
191 | +{ | ||
192 | + int i, oprsz = simd_oprsz(desc) / 8; | ||
193 | + uint8_t *pg = vg; | ||
194 | + uint64_t *n = vn; | ||
195 | + uint64_t *a = za; | ||
196 | + | ||
197 | + for (i = 0; i < oprsz; i++) { | ||
198 | + if (pg[H1(i)] & 1) { | ||
199 | + a[tile_vslice_index(i)] = n[i]; | ||
200 | + } | ||
201 | + } | ||
202 | +} | ||
203 | + | ||
204 | +void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc) | ||
205 | +{ | ||
206 | + int i, oprsz = simd_oprsz(desc) / 16; | ||
207 | + uint16_t *pg = vg; | ||
208 | + Int128 *n = vn; | ||
209 | + Int128 *a = za; | ||
210 | + | ||
240 | + /* | 211 | + /* |
241 | + * Eliminate registers that are not present because the EL is missing. | 212 | + * Int128 is used here simply to copy 16 bytes, and to simplify |
242 | + * Doing this here makes it easier to put all registers for a given | 213 | + * the address arithmetic. |
243 | + * feature into the same ARMCPRegInfo array and define them all at once. | ||
244 | + */ | 214 | + */ |
245 | + make_const = false; | 215 | + for (i = 0; i < oprsz; i++) { |
246 | + if (arm_feature(env, ARM_FEATURE_EL3)) { | 216 | + if (pg[H2(i)] & 1) { |
217 | + a[tile_vslice_index(i)] = n[i]; | ||
218 | + } | ||
219 | + } | ||
220 | +} | ||
221 | + | ||
222 | +#undef DO_MOVA_C | ||
223 | + | ||
224 | +/* | ||
225 | + * Move ZArray column to Zreg vector. | ||
226 | + */ | ||
227 | +#define DO_MOVA_Z(NAME, TYPE, H) \ | ||
228 | +void HELPER(NAME)(void *vd, void *za, void *vg, uint32_t desc) \ | ||
229 | +{ \ | ||
230 | + int i, oprsz = simd_oprsz(desc); \ | ||
231 | + for (i = 0; i < oprsz; ) { \ | ||
232 | + uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \ | ||
233 | + do { \ | ||
234 | + if (pg & 1) { \ | ||
235 | + *(TYPE *)(vd + H(i)) = *(TYPE *)(za + tile_vslice_offset(i)); \ | ||
236 | + } \ | ||
237 | + i += sizeof(TYPE); \ | ||
238 | + pg >>= sizeof(TYPE); \ | ||
239 | + } while (i & 15); \ | ||
240 | + } \ | ||
241 | +} | ||
242 | + | ||
243 | +DO_MOVA_Z(sme_mova_zc_b, uint8_t, H1) | ||
244 | +DO_MOVA_Z(sme_mova_zc_h, uint16_t, H1_2) | ||
245 | +DO_MOVA_Z(sme_mova_zc_s, uint32_t, H1_4) | ||
246 | + | ||
247 | +void HELPER(sme_mova_zc_d)(void *vd, void *za, void *vg, uint32_t desc) | ||
248 | +{ | ||
249 | + int i, oprsz = simd_oprsz(desc) / 8; | ||
250 | + uint8_t *pg = vg; | ||
251 | + uint64_t *d = vd; | ||
252 | + uint64_t *a = za; | ||
253 | + | ||
254 | + for (i = 0; i < oprsz; i++) { | ||
255 | + if (pg[H1(i)] & 1) { | ||
256 | + d[i] = a[tile_vslice_index(i)]; | ||
257 | + } | ||
258 | + } | ||
259 | +} | ||
260 | + | ||
261 | +void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc) | ||
262 | +{ | ||
263 | + int i, oprsz = simd_oprsz(desc) / 16; | ||
264 | + uint16_t *pg = vg; | ||
265 | + Int128 *d = vd; | ||
266 | + Int128 *a = za; | ||
267 | + | ||
268 | + /* | ||
269 | + * Int128 is used here simply to copy 16 bytes, and to simplify | ||
270 | + * the address arithmetic. | ||
271 | + */ | ||
272 | + for (i = 0; i < oprsz; i++, za += sizeof(ARMVectorReg)) { | ||
273 | + if (pg[H2(i)] & 1) { | ||
274 | + d[i] = a[tile_vslice_index(i)]; | ||
275 | + } | ||
276 | + } | ||
277 | +} | ||
278 | + | ||
279 | +#undef DO_MOVA_Z | ||
280 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
281 | index XXXXXXX..XXXXXXX 100644 | ||
282 | --- a/target/arm/sve_helper.c | ||
283 | +++ b/target/arm/sve_helper.c | ||
284 | @@ -XXX,XX +XXX,XX @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm, | ||
285 | } | ||
286 | } | ||
287 | |||
288 | +void HELPER(sve_sel_zpzz_q)(void *vd, void *vn, void *vm, | ||
289 | + void *vg, uint32_t desc) | ||
290 | +{ | ||
291 | + intptr_t i, opr_sz = simd_oprsz(desc) / 16; | ||
292 | + Int128 *d = vd, *n = vn, *m = vm; | ||
293 | + uint16_t *pg = vg; | ||
294 | + | ||
295 | + for (i = 0; i < opr_sz; i += 1) { | ||
296 | + d[i] = (pg[H2(i)] & 1 ? n : m)[i]; | ||
297 | + } | ||
298 | +} | ||
299 | + | ||
300 | /* Two operand comparison controlled by a predicate. | ||
301 | * ??? It is very tempting to want to be able to expand this inline | ||
302 | * with x86 instructions, e.g. | ||
303 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
304 | index XXXXXXX..XXXXXXX 100644 | ||
305 | --- a/target/arm/translate-sme.c | ||
306 | +++ b/target/arm/translate-sme.c | ||
307 | @@ -XXX,XX +XXX,XX @@ | ||
308 | #include "decode-sme.c.inc" | ||
309 | |||
310 | |||
311 | +/* | ||
312 | + * Resolve tile.size[index] to a host pointer, where tile and index | ||
313 | + * are always decoded together, dependent on the element size. | ||
314 | + */ | ||
315 | +static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, | ||
316 | + int tile_index, bool vertical) | ||
317 | +{ | ||
318 | + int tile = tile_index >> (4 - esz); | ||
319 | + int index = esz == MO_128 ? 0 : extract32(tile_index, 0, 4 - esz); | ||
320 | + int pos, len, offset; | ||
321 | + TCGv_i32 tmp; | ||
322 | + TCGv_ptr addr; | ||
323 | + | ||
324 | + /* Compute the final index, which is Rs+imm. */ | ||
325 | + tmp = tcg_temp_new_i32(); | ||
326 | + tcg_gen_trunc_tl_i32(tmp, cpu_reg(s, rs)); | ||
327 | + tcg_gen_addi_i32(tmp, tmp, index); | ||
328 | + | ||
329 | + /* Prepare a power-of-two modulo via extraction of @len bits. */ | ||
330 | + len = ctz32(streaming_vec_reg_size(s)) - esz; | ||
331 | + | ||
332 | + if (vertical) { | ||
247 | + /* | 333 | + /* |
248 | + * An EL2 register without EL2 but with EL3 is (usually) RES0. | 334 | + * Compute the byte offset of the index within the tile: |
249 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | 335 | + * (index % (svl / size)) * size |
336 | + * = (index % (svl >> esz)) << esz | ||
337 | + * Perform the power-of-two modulo via extraction of the low @len bits. | ||
338 | + * Perform the multiply by shifting left by @pos bits. | ||
339 | + * Perform these operations simultaneously via deposit into zero. | ||
250 | + */ | 340 | + */ |
251 | + int min_el = ctz32(r->access) / 2; | 341 | + pos = esz; |
252 | + if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | 342 | + tcg_gen_deposit_z_i32(tmp, tmp, pos, len); |
253 | + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | 343 | + |
254 | + return; | 344 | + /* |
255 | + } | 345 | + * For big-endian, adjust the indexed column byte offset within |
256 | + make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | 346 | + * the uint64_t host words that make up env->zarray[]. |
347 | + */ | ||
348 | + if (HOST_BIG_ENDIAN && esz < MO_64) { | ||
349 | + tcg_gen_xori_i32(tmp, tmp, 8 - (1 << esz)); | ||
257 | + } | 350 | + } |
258 | + } else { | 351 | + } else { |
259 | + CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | 352 | + /* |
260 | + ? PL2_RW : PL1_RW); | 353 | + * Compute the byte offset of the index within the tile: |
261 | + if ((r->access & max_el) == 0) { | 354 | + * (index % (svl / size)) * (size * sizeof(row)) |
262 | + return; | 355 | + * = (index % (svl >> esz)) << (esz + log2(sizeof(row))) |
263 | + } | 356 | + */ |
264 | + } | 357 | + pos = esz + ctz32(sizeof(ARMVectorReg)); |
265 | + | 358 | + tcg_gen_deposit_z_i32(tmp, tmp, pos, len); |
266 | /* Combine cpreg and name into one allocation. */ | 359 | + |
267 | name_len = strlen(name) + 1; | 360 | + /* Row slices are always aligned and need no endian adjustment. */ |
268 | r2 = g_malloc(sizeof(*r2) + name_len); | 361 | + } |
269 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 362 | + |
270 | r2->opaque = opaque; | 363 | + /* The tile byte offset within env->zarray is the row. */ |
364 | + offset = tile * sizeof(ARMVectorReg); | ||
365 | + | ||
366 | + /* Include the byte offset of zarray to make this relative to env. */ | ||
367 | + offset += offsetof(CPUARMState, zarray); | ||
368 | + tcg_gen_addi_i32(tmp, tmp, offset); | ||
369 | + | ||
370 | + /* Add the byte offset to env to produce the final pointer. */ | ||
371 | + addr = tcg_temp_new_ptr(); | ||
372 | + tcg_gen_ext_i32_ptr(addr, tmp); | ||
373 | + tcg_temp_free_i32(tmp); | ||
374 | + tcg_gen_add_ptr(addr, addr, cpu_env); | ||
375 | + | ||
376 | + return addr; | ||
377 | +} | ||
378 | + | ||
379 | static bool trans_ZERO(DisasContext *s, arg_ZERO *a) | ||
380 | { | ||
381 | if (!dc_isar_feature(aa64_sme, s)) { | ||
382 | @@ -XXX,XX +XXX,XX @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a) | ||
271 | } | 383 | } |
272 | 384 | return true; | |
273 | - isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | 385 | } |
274 | - if (isbanked) { | 386 | + |
275 | + if (make_const) { | 387 | +static bool trans_MOVA(DisasContext *s, arg_MOVA *a) |
276 | + /* This should not have been a very special register to begin. */ | 388 | +{ |
277 | + int old_special = r2->type & ARM_CP_SPECIAL_MASK; | 389 | + static gen_helper_gvec_4 * const h_fns[5] = { |
278 | + assert(old_special == 0 || old_special == ARM_CP_NOP); | 390 | + gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, |
279 | /* | 391 | + gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d, |
280 | - * Register is banked (using both entries in array). | 392 | + gen_helper_sve_sel_zpzz_q |
281 | - * Overwriting fieldoffset as the array is only used to define | 393 | + }; |
282 | - * banked registers but later only fieldoffset is used. | 394 | + static gen_helper_gvec_3 * const cz_fns[5] = { |
283 | + * Set the special function to CONST, retaining the other flags. | 395 | + gen_helper_sme_mova_cz_b, gen_helper_sme_mova_cz_h, |
284 | + * This is important for e.g. ARM_CP_SVE so that we still | 396 | + gen_helper_sme_mova_cz_s, gen_helper_sme_mova_cz_d, |
285 | + * take the SVE trap if CPTR_EL3.EZ == 0. | 397 | + gen_helper_sme_mova_cz_q, |
286 | */ | 398 | + }; |
287 | - r2->fieldoffset = r->bank_fieldoffsets[ns]; | 399 | + static gen_helper_gvec_3 * const zc_fns[5] = { |
288 | - } | 400 | + gen_helper_sme_mova_zc_b, gen_helper_sme_mova_zc_h, |
289 | + r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; | 401 | + gen_helper_sme_mova_zc_s, gen_helper_sme_mova_zc_d, |
290 | + /* | 402 | + gen_helper_sme_mova_zc_q, |
291 | + * Usually, these registers become RES0, but there are a few | 403 | + }; |
292 | + * special cases like VPIDR_EL2 which have a constant non-zero | 404 | + |
293 | + * value with writes ignored. | 405 | + TCGv_ptr t_za, t_zr, t_pg; |
294 | + */ | 406 | + TCGv_i32 t_desc; |
295 | + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | 407 | + int svl; |
296 | + r2->resetvalue = 0; | 408 | + |
297 | + } | 409 | + if (!dc_isar_feature(aa64_sme, s)) { |
298 | + /* | 410 | + return false; |
299 | + * ARM_CP_CONST has precedence, so removing the callbacks and | 411 | + } |
300 | + * offsets are not strictly necessary, but it is potentially | 412 | + if (!sme_smza_enabled_check(s)) { |
301 | + * less confusing to debug later. | 413 | + return true; |
302 | + */ | 414 | + } |
303 | + r2->readfn = NULL; | 415 | + |
304 | + r2->writefn = NULL; | 416 | + t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); |
305 | + r2->raw_readfn = NULL; | 417 | + t_zr = vec_full_reg_ptr(s, a->zr); |
306 | + r2->raw_writefn = NULL; | 418 | + t_pg = pred_full_reg_ptr(s, a->pg); |
307 | + r2->resetfn = NULL; | 419 | + |
308 | + r2->fieldoffset = 0; | 420 | + svl = streaming_vec_reg_size(s); |
309 | + r2->bank_fieldoffsets[0] = 0; | 421 | + t_desc = tcg_constant_i32(simd_desc(svl, svl, 0)); |
310 | + r2->bank_fieldoffsets[1] = 0; | 422 | + |
423 | + if (a->v) { | ||
424 | + /* Vertical slice -- use sme mova helpers. */ | ||
425 | + if (a->to_vec) { | ||
426 | + zc_fns[a->esz](t_zr, t_za, t_pg, t_desc); | ||
427 | + } else { | ||
428 | + cz_fns[a->esz](t_za, t_zr, t_pg, t_desc); | ||
429 | + } | ||
311 | + } else { | 430 | + } else { |
312 | + bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | 431 | + /* Horizontal slice -- reuse sve sel helpers. */ |
313 | 432 | + if (a->to_vec) { | |
314 | - if (state == ARM_CP_STATE_AA32) { | 433 | + h_fns[a->esz](t_zr, t_za, t_zr, t_pg, t_desc); |
315 | if (isbanked) { | 434 | + } else { |
316 | /* | 435 | + h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc); |
317 | - * If the register is banked then we don't need to migrate or | 436 | + } |
318 | - * reset the 32-bit instance in certain cases: | 437 | + } |
319 | - * | 438 | + |
320 | - * 1) If the register has both 32-bit and 64-bit instances then we | 439 | + tcg_temp_free_ptr(t_za); |
321 | - * can count on the 64-bit instance taking care of the | 440 | + tcg_temp_free_ptr(t_zr); |
322 | - * non-secure bank. | 441 | + tcg_temp_free_ptr(t_pg); |
323 | - * 2) If ARMv8 is enabled then we can count on a 64-bit version | 442 | + |
324 | - * taking care of the secure bank. This requires that separate | 443 | + return true; |
325 | - * 32 and 64-bit definitions are provided. | 444 | +} |
326 | + * Register is banked (using both entries in array). | ||
327 | + * Overwriting fieldoffset as the array is only used to define | ||
328 | + * banked registers but later only fieldoffset is used. | ||
329 | */ | ||
330 | - if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
331 | - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | ||
332 | + r2->fieldoffset = r->bank_fieldoffsets[ns]; | ||
333 | + } | ||
334 | + if (state == ARM_CP_STATE_AA32) { | ||
335 | + if (isbanked) { | ||
336 | + /* | ||
337 | + * If the register is banked then we don't need to migrate or | ||
338 | + * reset the 32-bit instance in certain cases: | ||
339 | + * | ||
340 | + * 1) If the register has both 32-bit and 64-bit instances | ||
341 | + * then we can count on the 64-bit instance taking care | ||
342 | + * of the non-secure bank. | ||
343 | + * 2) If ARMv8 is enabled then we can count on a 64-bit | ||
344 | + * version taking care of the secure bank. This requires | ||
345 | + * that separate 32 and 64-bit definitions are provided. | ||
346 | + */ | ||
347 | + if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
348 | + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | ||
349 | + r2->type |= ARM_CP_ALIAS; | ||
350 | + } | ||
351 | + } else if ((secstate != r->secure) && !ns) { | ||
352 | + /* | ||
353 | + * The register is not banked so we only want to allow | ||
354 | + * migration of the non-secure instance. | ||
355 | + */ | ||
356 | r2->type |= ARM_CP_ALIAS; | ||
357 | } | ||
358 | - } else if ((secstate != r->secure) && !ns) { | ||
359 | - /* | ||
360 | - * The register is not banked so we only want to allow migration | ||
361 | - * of the non-secure instance. | ||
362 | - */ | ||
363 | - r2->type |= ARM_CP_ALIAS; | ||
364 | - } | ||
365 | |||
366 | - if (HOST_BIG_ENDIAN && | ||
367 | - r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
368 | - r2->fieldoffset += sizeof(uint32_t); | ||
369 | + if (HOST_BIG_ENDIAN && | ||
370 | + r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
371 | + r2->fieldoffset += sizeof(uint32_t); | ||
372 | + } | ||
373 | } | ||
374 | } | ||
375 | |||
376 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
377 | * multiple times. Special registers (ie NOP/WFI) are | ||
378 | * never migratable and not even raw-accessible. | ||
379 | */ | ||
380 | - if (r->type & ARM_CP_SPECIAL_MASK) { | ||
381 | + if (r2->type & ARM_CP_SPECIAL_MASK) { | ||
382 | r2->type |= ARM_CP_NO_RAW; | ||
383 | } | ||
384 | if (((r->crm == CP_ANY) && crm != 0) || | ||
385 | -- | 445 | -- |
386 | 2.25.1 | 446 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When CPU-to-NUMA association isn't explicitly provided by users, | 3 | We cannot reuse the SVE functions for LD[1-4] and ST[1-4], |
4 | the default one is given by mc->get_default_cpu_node_id(). However, | 4 | because those functions accept only a Zreg register number. |
5 | the CPU topology isn't fully considered in the default association | 5 | For SME, we want to pass a pointer into ZA storage. |
6 | and this causes CPU topology broken warnings on booting Linux guest. | ||
7 | 6 | ||
8 | For example, the following warning messages are observed when the | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Linux guest is booted with the following command lines. | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | 9 | Message-id: 20220708151540.18136-21-richard.henderson@linaro.org | |
11 | /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ | ||
12 | -accel kvm -machine virt,gic-version=host \ | ||
13 | -cpu host \ | ||
14 | -smp 6,sockets=2,cores=3,threads=1 \ | ||
15 | -m 1024M,slots=16,maxmem=64G \ | ||
16 | -object memory-backend-ram,id=mem0,size=128M \ | ||
17 | -object memory-backend-ram,id=mem1,size=128M \ | ||
18 | -object memory-backend-ram,id=mem2,size=128M \ | ||
19 | -object memory-backend-ram,id=mem3,size=128M \ | ||
20 | -object memory-backend-ram,id=mem4,size=128M \ | ||
21 | -object memory-backend-ram,id=mem4,size=384M \ | ||
22 | -numa node,nodeid=0,memdev=mem0 \ | ||
23 | -numa node,nodeid=1,memdev=mem1 \ | ||
24 | -numa node,nodeid=2,memdev=mem2 \ | ||
25 | -numa node,nodeid=3,memdev=mem3 \ | ||
26 | -numa node,nodeid=4,memdev=mem4 \ | ||
27 | -numa node,nodeid=5,memdev=mem5 | ||
28 | : | ||
29 | alternatives: patching kernel code | ||
30 | BUG: arch topology borken | ||
31 | the CLS domain not a subset of the MC domain | ||
32 | <the above error log repeats> | ||
33 | BUG: arch topology borken | ||
34 | the DIE domain not a subset of the NODE domain | ||
35 | |||
36 | With current implementation of mc->get_default_cpu_node_id(), | ||
37 | CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately. | ||
38 | That's incorrect because CPU#0/1/2 should be associated with same | ||
39 | NUMA node because they're seated in same socket. | ||
40 | |||
41 | This fixes the issue by considering the socket ID when the default | ||
42 | CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids(). | ||
43 | With this applied, no more CPU topology broken warnings are seen | ||
44 | from the Linux guest. The 6 CPUs are associated with NODE#0/1, but | ||
45 | there are no CPUs associated with NODE#2/3/4/5. | ||
46 | |||
47 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
48 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
49 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
50 | Message-id: 20220503140304.855514-6-gshan@redhat.com | ||
51 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
52 | --- | 11 | --- |
53 | hw/arm/virt.c | 4 +++- | 12 | target/arm/helper-sme.h | 82 +++++ |
54 | 1 file changed, 3 insertions(+), 1 deletion(-) | 13 | target/arm/sme.decode | 9 + |
14 | target/arm/sme_helper.c | 595 +++++++++++++++++++++++++++++++++++++ | ||
15 | target/arm/translate-sme.c | 70 +++++ | ||
16 | 4 files changed, 756 insertions(+) | ||
55 | 17 | ||
56 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 18 | diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h |
57 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
58 | --- a/hw/arm/virt.c | 20 | --- a/target/arm/helper-sme.h |
59 | +++ b/hw/arm/virt.c | 21 | +++ b/target/arm/helper-sme.h |
60 | @@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
61 | 23 | DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | |
62 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) | 24 | DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
63 | { | 25 | DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
64 | - return idx % ms->numa_state->num_nodes; | 26 | + |
65 | + int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; | 27 | +DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) |
66 | + | 28 | +DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) |
67 | + return socket_id % ms->numa_state->num_nodes; | 29 | +DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) |
30 | +DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
31 | + | ||
32 | +DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
33 | +DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
34 | +DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
35 | +DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
36 | +DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
37 | +DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
38 | +DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
39 | +DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
40 | + | ||
41 | +DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
42 | +DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
43 | +DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
44 | +DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
45 | +DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
46 | +DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
47 | +DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
48 | +DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
49 | + | ||
50 | +DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
51 | +DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
52 | +DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
53 | +DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
54 | +DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
55 | +DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
56 | +DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
57 | +DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
58 | + | ||
59 | +DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
60 | +DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
61 | +DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
62 | +DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
63 | +DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
64 | +DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
65 | +DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
66 | +DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
67 | + | ||
68 | +DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
69 | +DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
70 | +DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
71 | +DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
72 | + | ||
73 | +DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
74 | +DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
75 | +DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
76 | +DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
77 | +DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
78 | +DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
79 | +DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
80 | +DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
81 | + | ||
82 | +DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
83 | +DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
84 | +DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
85 | +DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
86 | +DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
87 | +DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
88 | +DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
89 | +DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
90 | + | ||
91 | +DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
92 | +DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
93 | +DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
94 | +DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
95 | +DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
96 | +DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
97 | +DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
98 | +DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
99 | + | ||
100 | +DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
101 | +DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
102 | +DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
103 | +DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
104 | +DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
105 | +DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
106 | +DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
107 | +DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | ||
108 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode | ||
109 | index XXXXXXX..XXXXXXX 100644 | ||
110 | --- a/target/arm/sme.decode | ||
111 | +++ b/target/arm/sme.decode | ||
112 | @@ -XXX,XX +XXX,XX @@ MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ | ||
113 | &mova to_vec=1 rs=%mova_rs | ||
114 | MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ | ||
115 | &mova to_vec=1 rs=%mova_rs esz=4 | ||
116 | + | ||
117 | +### SME Memory | ||
118 | + | ||
119 | +&ldst esz rs pg rn rm za_imm v:bool st:bool | ||
120 | + | ||
121 | +LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ | ||
122 | + &ldst rs=%mova_rs | ||
123 | +LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ | ||
124 | + &ldst esz=4 rs=%mova_rs | ||
125 | diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c | ||
126 | index XXXXXXX..XXXXXXX 100644 | ||
127 | --- a/target/arm/sme_helper.c | ||
128 | +++ b/target/arm/sme_helper.c | ||
129 | @@ -XXX,XX +XXX,XX @@ | ||
130 | |||
131 | #include "qemu/osdep.h" | ||
132 | #include "cpu.h" | ||
133 | +#include "internals.h" | ||
134 | #include "tcg/tcg-gvec-desc.h" | ||
135 | #include "exec/helper-proto.h" | ||
136 | +#include "exec/cpu_ldst.h" | ||
137 | +#include "exec/exec-all.h" | ||
138 | #include "qemu/int128.h" | ||
139 | #include "vec_internal.h" | ||
140 | +#include "sve_ldst_internal.h" | ||
141 | |||
142 | /* ResetSVEState */ | ||
143 | void arm_reset_sve_state(CPUARMState *env) | ||
144 | @@ -XXX,XX +XXX,XX @@ void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc) | ||
68 | } | 145 | } |
69 | 146 | ||
70 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 147 | #undef DO_MOVA_Z |
148 | + | ||
149 | +/* | ||
150 | + * Clear elements in a tile slice comprising len bytes. | ||
151 | + */ | ||
152 | + | ||
153 | +typedef void ClearFn(void *ptr, size_t off, size_t len); | ||
154 | + | ||
155 | +static void clear_horizontal(void *ptr, size_t off, size_t len) | ||
156 | +{ | ||
157 | + memset(ptr + off, 0, len); | ||
158 | +} | ||
159 | + | ||
160 | +static void clear_vertical_b(void *vptr, size_t off, size_t len) | ||
161 | +{ | ||
162 | + for (size_t i = 0; i < len; ++i) { | ||
163 | + *(uint8_t *)(vptr + tile_vslice_offset(i + off)) = 0; | ||
164 | + } | ||
165 | +} | ||
166 | + | ||
167 | +static void clear_vertical_h(void *vptr, size_t off, size_t len) | ||
168 | +{ | ||
169 | + for (size_t i = 0; i < len; i += 2) { | ||
170 | + *(uint16_t *)(vptr + tile_vslice_offset(i + off)) = 0; | ||
171 | + } | ||
172 | +} | ||
173 | + | ||
174 | +static void clear_vertical_s(void *vptr, size_t off, size_t len) | ||
175 | +{ | ||
176 | + for (size_t i = 0; i < len; i += 4) { | ||
177 | + *(uint32_t *)(vptr + tile_vslice_offset(i + off)) = 0; | ||
178 | + } | ||
179 | +} | ||
180 | + | ||
181 | +static void clear_vertical_d(void *vptr, size_t off, size_t len) | ||
182 | +{ | ||
183 | + for (size_t i = 0; i < len; i += 8) { | ||
184 | + *(uint64_t *)(vptr + tile_vslice_offset(i + off)) = 0; | ||
185 | + } | ||
186 | +} | ||
187 | + | ||
188 | +static void clear_vertical_q(void *vptr, size_t off, size_t len) | ||
189 | +{ | ||
190 | + for (size_t i = 0; i < len; i += 16) { | ||
191 | + memset(vptr + tile_vslice_offset(i + off), 0, 16); | ||
192 | + } | ||
193 | +} | ||
194 | + | ||
195 | +/* | ||
196 | + * Copy elements from an array into a tile slice comprising len bytes. | ||
197 | + */ | ||
198 | + | ||
199 | +typedef void CopyFn(void *dst, const void *src, size_t len); | ||
200 | + | ||
201 | +static void copy_horizontal(void *dst, const void *src, size_t len) | ||
202 | +{ | ||
203 | + memcpy(dst, src, len); | ||
204 | +} | ||
205 | + | ||
206 | +static void copy_vertical_b(void *vdst, const void *vsrc, size_t len) | ||
207 | +{ | ||
208 | + const uint8_t *src = vsrc; | ||
209 | + uint8_t *dst = vdst; | ||
210 | + size_t i; | ||
211 | + | ||
212 | + for (i = 0; i < len; ++i) { | ||
213 | + dst[tile_vslice_index(i)] = src[i]; | ||
214 | + } | ||
215 | +} | ||
216 | + | ||
217 | +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len) | ||
218 | +{ | ||
219 | + const uint16_t *src = vsrc; | ||
220 | + uint16_t *dst = vdst; | ||
221 | + size_t i; | ||
222 | + | ||
223 | + for (i = 0; i < len / 2; ++i) { | ||
224 | + dst[tile_vslice_index(i)] = src[i]; | ||
225 | + } | ||
226 | +} | ||
227 | + | ||
228 | +static void copy_vertical_s(void *vdst, const void *vsrc, size_t len) | ||
229 | +{ | ||
230 | + const uint32_t *src = vsrc; | ||
231 | + uint32_t *dst = vdst; | ||
232 | + size_t i; | ||
233 | + | ||
234 | + for (i = 0; i < len / 4; ++i) { | ||
235 | + dst[tile_vslice_index(i)] = src[i]; | ||
236 | + } | ||
237 | +} | ||
238 | + | ||
239 | +static void copy_vertical_d(void *vdst, const void *vsrc, size_t len) | ||
240 | +{ | ||
241 | + const uint64_t *src = vsrc; | ||
242 | + uint64_t *dst = vdst; | ||
243 | + size_t i; | ||
244 | + | ||
245 | + for (i = 0; i < len / 8; ++i) { | ||
246 | + dst[tile_vslice_index(i)] = src[i]; | ||
247 | + } | ||
248 | +} | ||
249 | + | ||
250 | +static void copy_vertical_q(void *vdst, const void *vsrc, size_t len) | ||
251 | +{ | ||
252 | + for (size_t i = 0; i < len; i += 16) { | ||
253 | + memcpy(vdst + tile_vslice_offset(i), vsrc + i, 16); | ||
254 | + } | ||
255 | +} | ||
256 | + | ||
257 | +/* | ||
258 | + * Host and TLB primitives for vertical tile slice addressing. | ||
259 | + */ | ||
260 | + | ||
261 | +#define DO_LD(NAME, TYPE, HOST, TLB) \ | ||
262 | +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \ | ||
263 | +{ \ | ||
264 | + TYPE val = HOST(host); \ | ||
265 | + *(TYPE *)(za + tile_vslice_offset(off)) = val; \ | ||
266 | +} \ | ||
267 | +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \ | ||
268 | + intptr_t off, target_ulong addr, uintptr_t ra) \ | ||
269 | +{ \ | ||
270 | + TYPE val = TLB(env, useronly_clean_ptr(addr), ra); \ | ||
271 | + *(TYPE *)(za + tile_vslice_offset(off)) = val; \ | ||
272 | +} | ||
273 | + | ||
274 | +#define DO_ST(NAME, TYPE, HOST, TLB) \ | ||
275 | +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \ | ||
276 | +{ \ | ||
277 | + TYPE val = *(TYPE *)(za + tile_vslice_offset(off)); \ | ||
278 | + HOST(host, val); \ | ||
279 | +} \ | ||
280 | +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \ | ||
281 | + intptr_t off, target_ulong addr, uintptr_t ra) \ | ||
282 | +{ \ | ||
283 | + TYPE val = *(TYPE *)(za + tile_vslice_offset(off)); \ | ||
284 | + TLB(env, useronly_clean_ptr(addr), val, ra); \ | ||
285 | +} | ||
286 | + | ||
287 | +/* | ||
288 | + * The ARMVectorReg elements are stored in host-endian 64-bit units. | ||
289 | + * For 128-bit quantities, the sequence defined by the Elem[] pseudocode | ||
290 | + * corresponds to storing the two 64-bit pieces in little-endian order. | ||
291 | + */ | ||
292 | +#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) \ | ||
293 | +static inline void HNAME##_host(void *za, intptr_t off, void *host) \ | ||
294 | +{ \ | ||
295 | + uint64_t val0 = HOST(host), val1 = HOST(host + 8); \ | ||
296 | + uint64_t *ptr = za + off; \ | ||
297 | + ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \ | ||
298 | +} \ | ||
299 | +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \ | ||
300 | +{ \ | ||
301 | + HNAME##_host(za, tile_vslice_offset(off), host); \ | ||
302 | +} \ | ||
303 | +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \ | ||
304 | + target_ulong addr, uintptr_t ra) \ | ||
305 | +{ \ | ||
306 | + uint64_t val0 = TLB(env, useronly_clean_ptr(addr), ra); \ | ||
307 | + uint64_t val1 = TLB(env, useronly_clean_ptr(addr + 8), ra); \ | ||
308 | + uint64_t *ptr = za + off; \ | ||
309 | + ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \ | ||
310 | +} \ | ||
311 | +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \ | ||
312 | + target_ulong addr, uintptr_t ra) \ | ||
313 | +{ \ | ||
314 | + HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra); \ | ||
315 | +} | ||
316 | + | ||
317 | +#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) \ | ||
318 | +static inline void HNAME##_host(void *za, intptr_t off, void *host) \ | ||
319 | +{ \ | ||
320 | + uint64_t *ptr = za + off; \ | ||
321 | + HOST(host, ptr[BE]); \ | ||
322 | + HOST(host + 1, ptr[!BE]); \ | ||
323 | +} \ | ||
324 | +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \ | ||
325 | +{ \ | ||
326 | + HNAME##_host(za, tile_vslice_offset(off), host); \ | ||
327 | +} \ | ||
328 | +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \ | ||
329 | + target_ulong addr, uintptr_t ra) \ | ||
330 | +{ \ | ||
331 | + uint64_t *ptr = za + off; \ | ||
332 | + TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); \ | ||
333 | + TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); \ | ||
334 | +} \ | ||
335 | +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \ | ||
336 | + target_ulong addr, uintptr_t ra) \ | ||
337 | +{ \ | ||
338 | + HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra); \ | ||
339 | +} | ||
340 | + | ||
341 | +DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra) | ||
342 | +DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra) | ||
343 | +DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra) | ||
344 | +DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra) | ||
345 | +DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra) | ||
346 | +DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra) | ||
347 | +DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra) | ||
348 | + | ||
349 | +DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra) | ||
350 | +DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra) | ||
351 | + | ||
352 | +DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra) | ||
353 | +DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra) | ||
354 | +DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra) | ||
355 | +DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra) | ||
356 | +DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra) | ||
357 | +DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra) | ||
358 | +DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra) | ||
359 | + | ||
360 | +DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra) | ||
361 | +DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra) | ||
362 | + | ||
363 | +#undef DO_LD | ||
364 | +#undef DO_ST | ||
365 | +#undef DO_LDQ | ||
366 | +#undef DO_STQ | ||
367 | + | ||
368 | +/* | ||
369 | + * Common helper for all contiguous predicated loads. | ||
370 | + */ | ||
371 | + | ||
372 | +static inline QEMU_ALWAYS_INLINE | ||
373 | +void sme_ld1(CPUARMState *env, void *za, uint64_t *vg, | ||
374 | + const target_ulong addr, uint32_t desc, const uintptr_t ra, | ||
375 | + const int esz, uint32_t mtedesc, bool vertical, | ||
376 | + sve_ldst1_host_fn *host_fn, | ||
377 | + sve_ldst1_tlb_fn *tlb_fn, | ||
378 | + ClearFn *clr_fn, | ||
379 | + CopyFn *cpy_fn) | ||
380 | +{ | ||
381 | + const intptr_t reg_max = simd_oprsz(desc); | ||
382 | + const intptr_t esize = 1 << esz; | ||
383 | + intptr_t reg_off, reg_last; | ||
384 | + SVEContLdSt info; | ||
385 | + void *host; | ||
386 | + int flags; | ||
387 | + | ||
388 | + /* Find the active elements. */ | ||
389 | + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { | ||
390 | + /* The entire predicate was false; no load occurs. */ | ||
391 | + clr_fn(za, 0, reg_max); | ||
392 | + return; | ||
393 | + } | ||
394 | + | ||
395 | + /* Probe the page(s). Exit with exception for any invalid page. */ | ||
396 | + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra); | ||
397 | + | ||
398 | + /* Handle watchpoints for all active elements. */ | ||
399 | + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, | ||
400 | + BP_MEM_READ, ra); | ||
401 | + | ||
402 | + /* | ||
403 | + * Handle mte checks for all active elements. | ||
404 | + * Since TBI must be set for MTE, !mtedesc => !mte_active. | ||
405 | + */ | ||
406 | + if (mtedesc) { | ||
407 | + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, | ||
408 | + mtedesc, ra); | ||
409 | + } | ||
410 | + | ||
411 | + flags = info.page[0].flags | info.page[1].flags; | ||
412 | + if (unlikely(flags != 0)) { | ||
413 | +#ifdef CONFIG_USER_ONLY | ||
414 | + g_assert_not_reached(); | ||
415 | +#else | ||
416 | + /* | ||
417 | + * At least one page includes MMIO. | ||
418 | + * Any bus operation can fail with cpu_transaction_failed, | ||
419 | + * which for ARM will raise SyncExternal. Perform the load | ||
420 | + * into scratch memory to preserve register state until the end. | ||
421 | + */ | ||
422 | + ARMVectorReg scratch = { }; | ||
423 | + | ||
424 | + reg_off = info.reg_off_first[0]; | ||
425 | + reg_last = info.reg_off_last[1]; | ||
426 | + if (reg_last < 0) { | ||
427 | + reg_last = info.reg_off_split; | ||
428 | + if (reg_last < 0) { | ||
429 | + reg_last = info.reg_off_last[0]; | ||
430 | + } | ||
431 | + } | ||
432 | + | ||
433 | + do { | ||
434 | + uint64_t pg = vg[reg_off >> 6]; | ||
435 | + do { | ||
436 | + if ((pg >> (reg_off & 63)) & 1) { | ||
437 | + tlb_fn(env, &scratch, reg_off, addr + reg_off, ra); | ||
438 | + } | ||
439 | + reg_off += esize; | ||
440 | + } while (reg_off & 63); | ||
441 | + } while (reg_off <= reg_last); | ||
442 | + | ||
443 | + cpy_fn(za, &scratch, reg_max); | ||
444 | + return; | ||
445 | +#endif | ||
446 | + } | ||
447 | + | ||
448 | + /* The entire operation is in RAM, on valid pages. */ | ||
449 | + | ||
450 | + reg_off = info.reg_off_first[0]; | ||
451 | + reg_last = info.reg_off_last[0]; | ||
452 | + host = info.page[0].host; | ||
453 | + | ||
454 | + if (!vertical) { | ||
455 | + memset(za, 0, reg_max); | ||
456 | + } else if (reg_off) { | ||
457 | + clr_fn(za, 0, reg_off); | ||
458 | + } | ||
459 | + | ||
460 | + while (reg_off <= reg_last) { | ||
461 | + uint64_t pg = vg[reg_off >> 6]; | ||
462 | + do { | ||
463 | + if ((pg >> (reg_off & 63)) & 1) { | ||
464 | + host_fn(za, reg_off, host + reg_off); | ||
465 | + } else if (vertical) { | ||
466 | + clr_fn(za, reg_off, esize); | ||
467 | + } | ||
468 | + reg_off += esize; | ||
469 | + } while (reg_off <= reg_last && (reg_off & 63)); | ||
470 | + } | ||
471 | + | ||
472 | + /* | ||
473 | + * Use the slow path to manage the cross-page misalignment. | ||
474 | + * But we know this is RAM and cannot trap. | ||
475 | + */ | ||
476 | + reg_off = info.reg_off_split; | ||
477 | + if (unlikely(reg_off >= 0)) { | ||
478 | + tlb_fn(env, za, reg_off, addr + reg_off, ra); | ||
479 | + } | ||
480 | + | ||
481 | + reg_off = info.reg_off_first[1]; | ||
482 | + if (unlikely(reg_off >= 0)) { | ||
483 | + reg_last = info.reg_off_last[1]; | ||
484 | + host = info.page[1].host; | ||
485 | + | ||
486 | + do { | ||
487 | + uint64_t pg = vg[reg_off >> 6]; | ||
488 | + do { | ||
489 | + if ((pg >> (reg_off & 63)) & 1) { | ||
490 | + host_fn(za, reg_off, host + reg_off); | ||
491 | + } else if (vertical) { | ||
492 | + clr_fn(za, reg_off, esize); | ||
493 | + } | ||
494 | + reg_off += esize; | ||
495 | + } while (reg_off & 63); | ||
496 | + } while (reg_off <= reg_last); | ||
497 | + } | ||
498 | +} | ||
499 | + | ||
500 | +static inline QEMU_ALWAYS_INLINE | ||
501 | +void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg, | ||
502 | + target_ulong addr, uint32_t desc, uintptr_t ra, | ||
503 | + const int esz, bool vertical, | ||
504 | + sve_ldst1_host_fn *host_fn, | ||
505 | + sve_ldst1_tlb_fn *tlb_fn, | ||
506 | + ClearFn *clr_fn, | ||
507 | + CopyFn *cpy_fn) | ||
508 | +{ | ||
509 | + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
510 | + int bit55 = extract64(addr, 55, 1); | ||
511 | + | ||
512 | + /* Remove mtedesc from the normal sve descriptor. */ | ||
513 | + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
514 | + | ||
515 | + /* Perform gross MTE suppression early. */ | ||
516 | + if (!tbi_check(desc, bit55) || | ||
517 | + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { | ||
518 | + mtedesc = 0; | ||
519 | + } | ||
520 | + | ||
521 | + sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical, | ||
522 | + host_fn, tlb_fn, clr_fn, cpy_fn); | ||
523 | +} | ||
524 | + | ||
525 | +#define DO_LD(L, END, ESZ) \ | ||
526 | +void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg, \ | ||
527 | + target_ulong addr, uint32_t desc) \ | ||
528 | +{ \ | ||
529 | + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, \ | ||
530 | + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, \ | ||
531 | + clear_horizontal, copy_horizontal); \ | ||
532 | +} \ | ||
533 | +void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg, \ | ||
534 | + target_ulong addr, uint32_t desc) \ | ||
535 | +{ \ | ||
536 | + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, \ | ||
537 | + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, \ | ||
538 | + clear_vertical_##L, copy_vertical_##L); \ | ||
539 | +} \ | ||
540 | +void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \ | ||
541 | + target_ulong addr, uint32_t desc) \ | ||
542 | +{ \ | ||
543 | + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, \ | ||
544 | + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, \ | ||
545 | + clear_horizontal, copy_horizontal); \ | ||
546 | +} \ | ||
547 | +void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \ | ||
548 | + target_ulong addr, uint32_t desc) \ | ||
549 | +{ \ | ||
550 | + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, \ | ||
551 | + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, \ | ||
552 | + clear_vertical_##L, copy_vertical_##L); \ | ||
553 | +} | ||
554 | + | ||
555 | +DO_LD(b, , MO_8) | ||
556 | +DO_LD(h, _be, MO_16) | ||
557 | +DO_LD(h, _le, MO_16) | ||
558 | +DO_LD(s, _be, MO_32) | ||
559 | +DO_LD(s, _le, MO_32) | ||
560 | +DO_LD(d, _be, MO_64) | ||
561 | +DO_LD(d, _le, MO_64) | ||
562 | +DO_LD(q, _be, MO_128) | ||
563 | +DO_LD(q, _le, MO_128) | ||
564 | + | ||
565 | +#undef DO_LD | ||
566 | + | ||
567 | +/* | ||
568 | + * Common helper for all contiguous predicated stores. | ||
569 | + */ | ||
570 | + | ||
571 | +static inline QEMU_ALWAYS_INLINE | ||
572 | +void sme_st1(CPUARMState *env, void *za, uint64_t *vg, | ||
573 | + const target_ulong addr, uint32_t desc, const uintptr_t ra, | ||
574 | + const int esz, uint32_t mtedesc, bool vertical, | ||
575 | + sve_ldst1_host_fn *host_fn, | ||
576 | + sve_ldst1_tlb_fn *tlb_fn) | ||
577 | +{ | ||
578 | + const intptr_t reg_max = simd_oprsz(desc); | ||
579 | + const intptr_t esize = 1 << esz; | ||
580 | + intptr_t reg_off, reg_last; | ||
581 | + SVEContLdSt info; | ||
582 | + void *host; | ||
583 | + int flags; | ||
584 | + | ||
585 | + /* Find the active elements. */ | ||
586 | + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { | ||
587 | + /* The entire predicate was false; no store occurs. */ | ||
588 | + return; | ||
589 | + } | ||
590 | + | ||
591 | + /* Probe the page(s). Exit with exception for any invalid page. */ | ||
592 | + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra); | ||
593 | + | ||
594 | + /* Handle watchpoints for all active elements. */ | ||
595 | + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, | ||
596 | + BP_MEM_WRITE, ra); | ||
597 | + | ||
598 | + /* | ||
599 | + * Handle mte checks for all active elements. | ||
600 | + * Since TBI must be set for MTE, !mtedesc => !mte_active. | ||
601 | + */ | ||
602 | + if (mtedesc) { | ||
603 | + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, | ||
604 | + mtedesc, ra); | ||
605 | + } | ||
606 | + | ||
607 | + flags = info.page[0].flags | info.page[1].flags; | ||
608 | + if (unlikely(flags != 0)) { | ||
609 | +#ifdef CONFIG_USER_ONLY | ||
610 | + g_assert_not_reached(); | ||
611 | +#else | ||
612 | + /* | ||
613 | + * At least one page includes MMIO. | ||
614 | + * Any bus operation can fail with cpu_transaction_failed, | ||
615 | + * which for ARM will raise SyncExternal. We cannot avoid | ||
616 | + * this fault and will leave with the store incomplete. | ||
617 | + */ | ||
618 | + reg_off = info.reg_off_first[0]; | ||
619 | + reg_last = info.reg_off_last[1]; | ||
620 | + if (reg_last < 0) { | ||
621 | + reg_last = info.reg_off_split; | ||
622 | + if (reg_last < 0) { | ||
623 | + reg_last = info.reg_off_last[0]; | ||
624 | + } | ||
625 | + } | ||
626 | + | ||
627 | + do { | ||
628 | + uint64_t pg = vg[reg_off >> 6]; | ||
629 | + do { | ||
630 | + if ((pg >> (reg_off & 63)) & 1) { | ||
631 | + tlb_fn(env, za, reg_off, addr + reg_off, ra); | ||
632 | + } | ||
633 | + reg_off += esize; | ||
634 | + } while (reg_off & 63); | ||
635 | + } while (reg_off <= reg_last); | ||
636 | + return; | ||
637 | +#endif | ||
638 | + } | ||
639 | + | ||
640 | + reg_off = info.reg_off_first[0]; | ||
641 | + reg_last = info.reg_off_last[0]; | ||
642 | + host = info.page[0].host; | ||
643 | + | ||
644 | + while (reg_off <= reg_last) { | ||
645 | + uint64_t pg = vg[reg_off >> 6]; | ||
646 | + do { | ||
647 | + if ((pg >> (reg_off & 63)) & 1) { | ||
648 | + host_fn(za, reg_off, host + reg_off); | ||
649 | + } | ||
650 | + reg_off += 1 << esz; | ||
651 | + } while (reg_off <= reg_last && (reg_off & 63)); | ||
652 | + } | ||
653 | + | ||
654 | + /* | ||
655 | + * Use the slow path to manage the cross-page misalignment. | ||
656 | + * But we know this is RAM and cannot trap. | ||
657 | + */ | ||
658 | + reg_off = info.reg_off_split; | ||
659 | + if (unlikely(reg_off >= 0)) { | ||
660 | + tlb_fn(env, za, reg_off, addr + reg_off, ra); | ||
661 | + } | ||
662 | + | ||
663 | + reg_off = info.reg_off_first[1]; | ||
664 | + if (unlikely(reg_off >= 0)) { | ||
665 | + reg_last = info.reg_off_last[1]; | ||
666 | + host = info.page[1].host; | ||
667 | + | ||
668 | + do { | ||
669 | + uint64_t pg = vg[reg_off >> 6]; | ||
670 | + do { | ||
671 | + if ((pg >> (reg_off & 63)) & 1) { | ||
672 | + host_fn(za, reg_off, host + reg_off); | ||
673 | + } | ||
674 | + reg_off += 1 << esz; | ||
675 | + } while (reg_off & 63); | ||
676 | + } while (reg_off <= reg_last); | ||
677 | + } | ||
678 | +} | ||
679 | + | ||
680 | +static inline QEMU_ALWAYS_INLINE | ||
681 | +void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr, | ||
682 | + uint32_t desc, uintptr_t ra, int esz, bool vertical, | ||
683 | + sve_ldst1_host_fn *host_fn, | ||
684 | + sve_ldst1_tlb_fn *tlb_fn) | ||
685 | +{ | ||
686 | + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
687 | + int bit55 = extract64(addr, 55, 1); | ||
688 | + | ||
689 | + /* Remove mtedesc from the normal sve descriptor. */ | ||
690 | + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); | ||
691 | + | ||
692 | + /* Perform gross MTE suppression early. */ | ||
693 | + if (!tbi_check(desc, bit55) || | ||
694 | + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { | ||
695 | + mtedesc = 0; | ||
696 | + } | ||
697 | + | ||
698 | + sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc, | ||
699 | + vertical, host_fn, tlb_fn); | ||
700 | +} | ||
701 | + | ||
702 | +#define DO_ST(L, END, ESZ) \ | ||
703 | +void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg, \ | ||
704 | + target_ulong addr, uint32_t desc) \ | ||
705 | +{ \ | ||
706 | + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, \ | ||
707 | + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); \ | ||
708 | +} \ | ||
709 | +void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg, \ | ||
710 | + target_ulong addr, uint32_t desc) \ | ||
711 | +{ \ | ||
712 | + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, \ | ||
713 | + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); \ | ||
714 | +} \ | ||
715 | +void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \ | ||
716 | + target_ulong addr, uint32_t desc) \ | ||
717 | +{ \ | ||
718 | + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, \ | ||
719 | + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); \ | ||
720 | +} \ | ||
721 | +void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \ | ||
722 | + target_ulong addr, uint32_t desc) \ | ||
723 | +{ \ | ||
724 | + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, \ | ||
725 | + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); \ | ||
726 | +} | ||
727 | + | ||
728 | +DO_ST(b, , MO_8) | ||
729 | +DO_ST(h, _be, MO_16) | ||
730 | +DO_ST(h, _le, MO_16) | ||
731 | +DO_ST(s, _be, MO_32) | ||
732 | +DO_ST(s, _le, MO_32) | ||
733 | +DO_ST(d, _be, MO_64) | ||
734 | +DO_ST(d, _le, MO_64) | ||
735 | +DO_ST(q, _be, MO_128) | ||
736 | +DO_ST(q, _le, MO_128) | ||
737 | + | ||
738 | +#undef DO_ST | ||
739 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
740 | index XXXXXXX..XXXXXXX 100644 | ||
741 | --- a/target/arm/translate-sme.c | ||
742 | +++ b/target/arm/translate-sme.c | ||
743 | @@ -XXX,XX +XXX,XX @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a) | ||
744 | |||
745 | return true; | ||
746 | } | ||
747 | + | ||
748 | +static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) | ||
749 | +{ | ||
750 | + typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32); | ||
751 | + | ||
752 | + /* | ||
753 | + * Indexed by [esz][be][v][mte][st], which is (except for load/store) | ||
754 | + * also the order in which the elements appear in the function names, | ||
755 | + * and so how we must concatenate the pieces. | ||
756 | + */ | ||
757 | + | ||
758 | +#define FN_LS(F) { gen_helper_sme_ld1##F, gen_helper_sme_st1##F } | ||
759 | +#define FN_MTE(F) { FN_LS(F), FN_LS(F##_mte) } | ||
760 | +#define FN_HV(F) { FN_MTE(F##_h), FN_MTE(F##_v) } | ||
761 | +#define FN_END(L, B) { FN_HV(L), FN_HV(B) } | ||
762 | + | ||
763 | + static GenLdSt1 * const fns[5][2][2][2][2] = { | ||
764 | + FN_END(b, b), | ||
765 | + FN_END(h_le, h_be), | ||
766 | + FN_END(s_le, s_be), | ||
767 | + FN_END(d_le, d_be), | ||
768 | + FN_END(q_le, q_be), | ||
769 | + }; | ||
770 | + | ||
771 | +#undef FN_LS | ||
772 | +#undef FN_MTE | ||
773 | +#undef FN_HV | ||
774 | +#undef FN_END | ||
775 | + | ||
776 | + TCGv_ptr t_za, t_pg; | ||
777 | + TCGv_i64 addr; | ||
778 | + int svl, desc = 0; | ||
779 | + bool be = s->be_data == MO_BE; | ||
780 | + bool mte = s->mte_active[0]; | ||
781 | + | ||
782 | + if (!dc_isar_feature(aa64_sme, s)) { | ||
783 | + return false; | ||
784 | + } | ||
785 | + if (!sme_smza_enabled_check(s)) { | ||
786 | + return true; | ||
787 | + } | ||
788 | + | ||
789 | + t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); | ||
790 | + t_pg = pred_full_reg_ptr(s, a->pg); | ||
791 | + addr = tcg_temp_new_i64(); | ||
792 | + | ||
793 | + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); | ||
794 | + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | ||
795 | + | ||
796 | + if (mte) { | ||
797 | + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
798 | + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
799 | + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
800 | + desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st); | ||
801 | + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); | ||
802 | + desc <<= SVE_MTEDESC_SHIFT; | ||
803 | + } else { | ||
804 | + addr = clean_data_tbi(s, addr); | ||
805 | + } | ||
806 | + svl = streaming_vec_reg_size(s); | ||
807 | + desc = simd_desc(svl, svl, desc); | ||
808 | + | ||
809 | + fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, | ||
810 | + tcg_constant_i32(desc)); | ||
811 | + | ||
812 | + tcg_temp_free_ptr(t_za); | ||
813 | + tcg_temp_free_ptr(t_pg); | ||
814 | + tcg_temp_free_i64(addr); | ||
815 | + return true; | ||
816 | +} | ||
71 | -- | 817 | -- |
72 | 2.25.1 | 818 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This adds cluster-id in CPU instance properties, which will be used | 3 | Add a TCGv_ptr base argument, which will be cpu_env for SVE. |
4 | by arm/virt machine. Besides, the cluster-id is also verified or | 4 | We will reuse this for SME save and restore array insns. |
5 | dumped in various spots: | ||
6 | 5 | ||
7 | * hw/core/machine.c::machine_set_cpu_numa_node() to associate | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | CPU with its NUMA node. | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | 8 | Message-id: 20220708151540.18136-22-richard.henderson@linaro.org | |
10 | * hw/core/machine.c::machine_numa_finish_cpu_init() to record | ||
11 | CPU slots with no NUMA mapping set. | ||
12 | |||
13 | * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump | ||
14 | cluster-id. | ||
15 | |||
16 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
17 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
18 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
19 | Message-id: 20220503140304.855514-2-gshan@redhat.com | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | --- | 10 | --- |
22 | qapi/machine.json | 6 ++++-- | 11 | target/arm/translate-a64.h | 3 +++ |
23 | hw/core/machine-hmp-cmds.c | 4 ++++ | 12 | target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++---------- |
24 | hw/core/machine.c | 16 ++++++++++++++++ | 13 | 2 files changed, 39 insertions(+), 12 deletions(-) |
25 | 3 files changed, 24 insertions(+), 2 deletions(-) | ||
26 | 14 | ||
27 | diff --git a/qapi/machine.json b/qapi/machine.json | 15 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h |
28 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/qapi/machine.json | 17 | --- a/target/arm/translate-a64.h |
30 | +++ b/qapi/machine.json | 18 | +++ b/target/arm/translate-a64.h |
31 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
32 | # @node-id: NUMA node ID the CPU belongs to | 20 | uint32_t rm_ofs, int64_t shift, |
33 | # @socket-id: socket number within node/board the CPU belongs to | 21 | uint32_t opr_sz, uint32_t max_sz); |
34 | # @die-id: die number within socket the CPU belongs to (since 4.1) | 22 | |
35 | -# @core-id: core number within die the CPU belongs to | 23 | +void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); |
36 | +# @cluster-id: cluster number within die the CPU belongs to (since 7.1) | 24 | +void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); |
37 | +# @core-id: core number within cluster the CPU belongs to | 25 | + |
38 | # @thread-id: thread number within core the CPU belongs to | 26 | #endif /* TARGET_ARM_TRANSLATE_A64_H */ |
39 | # | 27 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
40 | -# Note: currently there are 5 properties that could be present | ||
41 | +# Note: currently there are 6 properties that could be present | ||
42 | # but management should be prepared to pass through other | ||
43 | # properties with device_add command to allow for future | ||
44 | # interface extension. This also requires the filed names to be kept in | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | 'data': { '*node-id': 'int', | ||
47 | '*socket-id': 'int', | ||
48 | '*die-id': 'int', | ||
49 | + '*cluster-id': 'int', | ||
50 | '*core-id': 'int', | ||
51 | '*thread-id': 'int' | ||
52 | } | ||
53 | diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/hw/core/machine-hmp-cmds.c | 29 | --- a/target/arm/translate-sve.c |
56 | +++ b/hw/core/machine-hmp-cmds.c | 30 | +++ b/target/arm/translate-sve.c |
57 | @@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) | 31 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, |
58 | if (c->has_die_id) { | 32 | * The load should begin at the address Rn + IMM. |
59 | monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); | 33 | */ |
34 | |||
35 | -static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
36 | +void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, | ||
37 | + int len, int rn, int imm) | ||
38 | { | ||
39 | int len_align = QEMU_ALIGN_DOWN(len, 8); | ||
40 | int len_remain = len % 8; | ||
41 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
42 | t0 = tcg_temp_new_i64(); | ||
43 | for (i = 0; i < len_align; i += 8) { | ||
44 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); | ||
45 | - tcg_gen_st_i64(t0, cpu_env, vofs + i); | ||
46 | + tcg_gen_st_i64(t0, base, vofs + i); | ||
47 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); | ||
60 | } | 48 | } |
61 | + if (c->has_cluster_id) { | 49 | tcg_temp_free_i64(t0); |
62 | + monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n", | 50 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
63 | + c->cluster_id); | 51 | clean_addr = new_tmp_a64_local(s); |
64 | + } | 52 | tcg_gen_mov_i64(clean_addr, t0); |
65 | if (c->has_core_id) { | 53 | |
66 | monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); | 54 | + if (base != cpu_env) { |
67 | } | 55 | + TCGv_ptr b = tcg_temp_local_new_ptr(); |
68 | diff --git a/hw/core/machine.c b/hw/core/machine.c | 56 | + tcg_gen_mov_ptr(b, base); |
69 | index XXXXXXX..XXXXXXX 100644 | 57 | + base = b; |
70 | --- a/hw/core/machine.c | ||
71 | +++ b/hw/core/machine.c | ||
72 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | ||
73 | return; | ||
74 | } | ||
75 | |||
76 | + if (props->has_cluster_id && !slot->props.has_cluster_id) { | ||
77 | + error_setg(errp, "cluster-id is not supported"); | ||
78 | + return; | ||
79 | + } | 58 | + } |
80 | + | 59 | + |
81 | if (props->has_socket_id && !slot->props.has_socket_id) { | 60 | gen_set_label(loop); |
82 | error_setg(errp, "socket-id is not supported"); | 61 | |
83 | return; | 62 | t0 = tcg_temp_new_i64(); |
84 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | 63 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
85 | continue; | 64 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
65 | |||
66 | tp = tcg_temp_new_ptr(); | ||
67 | - tcg_gen_add_ptr(tp, cpu_env, i); | ||
68 | + tcg_gen_add_ptr(tp, base, i); | ||
69 | tcg_gen_addi_ptr(i, i, 8); | ||
70 | tcg_gen_st_i64(t0, tp, vofs); | ||
71 | tcg_temp_free_ptr(tp); | ||
72 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
73 | |||
74 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | ||
75 | tcg_temp_free_ptr(i); | ||
76 | + | ||
77 | + if (base != cpu_env) { | ||
78 | + tcg_temp_free_ptr(base); | ||
79 | + assert(len_remain == 0); | ||
80 | + } | ||
81 | } | ||
82 | |||
83 | /* | ||
84 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
85 | default: | ||
86 | g_assert_not_reached(); | ||
86 | } | 87 | } |
87 | 88 | - tcg_gen_st_i64(t0, cpu_env, vofs + len_align); | |
88 | + if (props->has_cluster_id && | 89 | + tcg_gen_st_i64(t0, base, vofs + len_align); |
89 | + props->cluster_id != slot->props.cluster_id) { | 90 | tcg_temp_free_i64(t0); |
90 | + continue; | 91 | } |
92 | } | ||
93 | |||
94 | /* Similarly for stores. */ | ||
95 | -static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
96 | +void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, | ||
97 | + int len, int rn, int imm) | ||
98 | { | ||
99 | int len_align = QEMU_ALIGN_DOWN(len, 8); | ||
100 | int len_remain = len % 8; | ||
101 | @@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
102 | |||
103 | t0 = tcg_temp_new_i64(); | ||
104 | for (i = 0; i < len_align; i += 8) { | ||
105 | - tcg_gen_ld_i64(t0, cpu_env, vofs + i); | ||
106 | + tcg_gen_ld_i64(t0, base, vofs + i); | ||
107 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); | ||
108 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); | ||
109 | } | ||
110 | @@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
111 | clean_addr = new_tmp_a64_local(s); | ||
112 | tcg_gen_mov_i64(clean_addr, t0); | ||
113 | |||
114 | + if (base != cpu_env) { | ||
115 | + TCGv_ptr b = tcg_temp_local_new_ptr(); | ||
116 | + tcg_gen_mov_ptr(b, base); | ||
117 | + base = b; | ||
91 | + } | 118 | + } |
92 | + | 119 | + |
93 | if (props->has_die_id && props->die_id != slot->props.die_id) { | 120 | gen_set_label(loop); |
94 | continue; | 121 | |
95 | } | 122 | t0 = tcg_temp_new_i64(); |
96 | @@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu) | 123 | tp = tcg_temp_new_ptr(); |
97 | } | 124 | - tcg_gen_add_ptr(tp, cpu_env, i); |
98 | g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); | 125 | + tcg_gen_add_ptr(tp, base, i); |
126 | tcg_gen_ld_i64(t0, tp, vofs); | ||
127 | tcg_gen_addi_ptr(i, i, 8); | ||
128 | tcg_temp_free_ptr(tp); | ||
129 | @@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
130 | |||
131 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | ||
132 | tcg_temp_free_ptr(i); | ||
133 | + | ||
134 | + if (base != cpu_env) { | ||
135 | + tcg_temp_free_ptr(base); | ||
136 | + assert(len_remain == 0); | ||
137 | + } | ||
99 | } | 138 | } |
100 | + if (cpu->props.has_cluster_id) { | 139 | |
101 | + if (s->len) { | 140 | /* Predicate register stores can be any multiple of 2. */ |
102 | + g_string_append_printf(s, ", "); | 141 | if (len_remain) { |
103 | + } | 142 | t0 = tcg_temp_new_i64(); |
104 | + g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); | 143 | - tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); |
105 | + } | 144 | + tcg_gen_ld_i64(t0, base, vofs + len_align); |
106 | if (cpu->props.has_core_id) { | 145 | |
107 | if (s->len) { | 146 | switch (len_remain) { |
108 | g_string_append_printf(s, ", "); | 147 | case 2: |
148 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) | ||
149 | if (sve_access_check(s)) { | ||
150 | int size = vec_full_reg_size(s); | ||
151 | int off = vec_full_reg_offset(s, a->rd); | ||
152 | - do_ldr(s, off, size, a->rn, a->imm * size); | ||
153 | + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); | ||
154 | } | ||
155 | return true; | ||
156 | } | ||
157 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) | ||
158 | if (sve_access_check(s)) { | ||
159 | int size = pred_full_reg_size(s); | ||
160 | int off = pred_full_reg_offset(s, a->rd); | ||
161 | - do_ldr(s, off, size, a->rn, a->imm * size); | ||
162 | + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); | ||
163 | } | ||
164 | return true; | ||
165 | } | ||
166 | @@ -XXX,XX +XXX,XX @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) | ||
167 | if (sve_access_check(s)) { | ||
168 | int size = vec_full_reg_size(s); | ||
169 | int off = vec_full_reg_offset(s, a->rd); | ||
170 | - do_str(s, off, size, a->rn, a->imm * size); | ||
171 | + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); | ||
172 | } | ||
173 | return true; | ||
174 | } | ||
175 | @@ -XXX,XX +XXX,XX @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a) | ||
176 | if (sve_access_check(s)) { | ||
177 | int size = pred_full_reg_size(s); | ||
178 | int off = pred_full_reg_offset(s, a->rd); | ||
179 | - do_str(s, off, size, a->rn, a->imm * size); | ||
180 | + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); | ||
181 | } | ||
182 | return true; | ||
183 | } | ||
109 | -- | 184 | -- |
110 | 2.25.1 | 185 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The CPU topology isn't enabled on arm/virt machine yet, but we're | 3 | We can reuse the SVE functions for LDR and STR, passing in the |
4 | going to do it in next patch. After the CPU topology is enabled by | 4 | base of the ZA vector and a zero offset. |
5 | next patch, "thread-id=1" becomes invalid because the CPU core is | ||
6 | preferred on arm/virt machine. It means these two CPUs have 0/1 | ||
7 | as their core IDs, but their thread IDs are all 0. It will trigger | ||
8 | test failure as the following message indicates: | ||
9 | 5 | ||
10 | [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | 1.48s killed by signal 6 SIGABRT | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \ | 8 | Message-id: 20220708151540.18136-23-richard.henderson@linaro.org |
13 | QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \ | ||
14 | QTEST_QEMU_BINARY=./qemu-system-aarch64 \ | ||
15 | QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \ | ||
16 | /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k | ||
17 | ―――――――――――――――――――――――――――――――――――――――――――――― | ||
18 | stderr: | ||
19 | qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found | ||
20 | |||
21 | This fixes the issue by providing comprehensive SMP configurations | ||
22 | in aarch64_numa_cpu(). The SMP configurations aren't used before | ||
23 | the CPU topology is enabled in next patch. | ||
24 | |||
25 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
26 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
27 | Message-id: 20220503140304.855514-3-gshan@redhat.com | ||
28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
29 | --- | 10 | --- |
30 | tests/qtest/numa-test.c | 3 ++- | 11 | target/arm/sme.decode | 7 +++++++ |
31 | 1 file changed, 2 insertions(+), 1 deletion(-) | 12 | target/arm/translate-sme.c | 24 ++++++++++++++++++++++++ |
13 | 2 files changed, 31 insertions(+) | ||
32 | 14 | ||
33 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c | 15 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode |
34 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/tests/qtest/numa-test.c | 17 | --- a/target/arm/sme.decode |
36 | +++ b/tests/qtest/numa-test.c | 18 | +++ b/target/arm/sme.decode |
37 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | 19 | @@ -XXX,XX +XXX,XX @@ LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ |
38 | QTestState *qts; | 20 | &ldst rs=%mova_rs |
39 | g_autofree char *cli = NULL; | 21 | LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ |
40 | 22 | &ldst esz=4 rs=%mova_rs | |
41 | - cli = make_cli(data, "-machine smp.cpus=2 " | 23 | + |
42 | + cli = make_cli(data, "-machine " | 24 | +&ldstr rv rn imm |
43 | + "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " | 25 | +@ldstr ....... ... . ...... .. ... rn:5 . imm:4 \ |
44 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " | 26 | + &ldstr rv=%mova_rs |
45 | "-numa cpu,node-id=1,thread-id=0 " | 27 | + |
46 | "-numa cpu,node-id=0,thread-id=1"); | 28 | +LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr |
29 | +STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr | ||
30 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/translate-sme.c | ||
33 | +++ b/target/arm/translate-sme.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) | ||
35 | tcg_temp_free_i64(addr); | ||
36 | return true; | ||
37 | } | ||
38 | + | ||
39 | +typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int); | ||
40 | + | ||
41 | +static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) | ||
42 | +{ | ||
43 | + int svl = streaming_vec_reg_size(s); | ||
44 | + int imm = a->imm; | ||
45 | + TCGv_ptr base; | ||
46 | + | ||
47 | + if (!sme_za_enabled_check(s)) { | ||
48 | + return true; | ||
49 | + } | ||
50 | + | ||
51 | + /* ZA[n] equates to ZA0H.B[n]. */ | ||
52 | + base = get_tile_rowcol(s, MO_8, a->rv, imm, false); | ||
53 | + | ||
54 | + fn(s, base, 0, svl, a->rn, imm * svl); | ||
55 | + | ||
56 | + tcg_temp_free_ptr(base); | ||
57 | + return true; | ||
58 | +} | ||
59 | + | ||
60 | +TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) | ||
61 | +TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) | ||
47 | -- | 62 | -- |
48 | 2.25.1 | 63 | 2.25.1 |
49 | |||
50 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <quic_llindhol@quicinc.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The sbsa-ref machine is continuously evolving. Some of the changes we | ||
4 | want to make in the near future, to align with real components (e.g. | ||
5 | the GIC-700), will break compatibility for existing firmware. | ||
6 | |||
7 | Introduce two new properties to the DT generated on machine generation: | ||
8 | - machine-version-major | ||
9 | To be incremented when a platform change makes the machine | ||
10 | incompatible with existing firmware. | ||
11 | - machine-version-minor | ||
12 | To be incremented when functionality is added to the machine | ||
13 | without causing incompatibility with existing firmware. | ||
14 | to be reset to 0 when machine-version-major is incremented. | ||
15 | |||
16 | This versioning scheme is *neither*: | ||
17 | - A QEMU versioned machine type; a given version of QEMU will emulate | ||
18 | a given version of the platform. | ||
19 | - A reflection of level of SBSA (now SystemReady SR) support provided. | ||
20 | |||
21 | The version will increment on guest-visible functional changes only, | ||
22 | akin to a revision ID register found on a physical platform. | ||
23 | |||
24 | These properties are both introduced with the value 0. | ||
25 | (Hence, a machine where the DT is lacking these nodes is equivalent | ||
26 | to version 0.0.) | ||
27 | |||
28 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
29 | Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com | ||
30 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Cc: Radoslaw Biernacki <rad@semihalf.com> | ||
32 | Cc: Cédric Le Goater <clg@kaod.org> | ||
33 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20220708151540.18136-24-richard.henderson@linaro.org | ||
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
35 | --- | 7 | --- |
36 | hw/arm/sbsa-ref.c | 14 ++++++++++++++ | 8 | target/arm/helper-sme.h | 5 +++ |
37 | 1 file changed, 14 insertions(+) | 9 | target/arm/sme.decode | 11 +++++ |
10 | target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-sme.c | 31 +++++++++++++ | ||
12 | 4 files changed, 137 insertions(+) | ||
38 | 13 | ||
39 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | 14 | diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h |
40 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/hw/arm/sbsa-ref.c | 16 | --- a/target/arm/helper-sme.h |
42 | +++ b/hw/arm/sbsa-ref.c | 17 | +++ b/target/arm/helper-sme.h |
43 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms) | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i |
44 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | 19 | DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) |
45 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | 20 | DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) |
46 | 21 | DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) | |
47 | + /* | ||
48 | + * This versioning scheme is for informing platform fw only. It is neither: | ||
49 | + * - A QEMU versioned machine type; a given version of QEMU will emulate | ||
50 | + * a given version of the platform. | ||
51 | + * - A reflection of level of SBSA (now SystemReady SR) support provided. | ||
52 | + * | ||
53 | + * machine-version-major: updated when changes breaking fw compatibility | ||
54 | + * are introduced. | ||
55 | + * machine-version-minor: updated when features are added that don't break | ||
56 | + * fw compatibility. | ||
57 | + */ | ||
58 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); | ||
59 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0); | ||
60 | + | 22 | + |
61 | if (ms->numa_state->have_numa_distance) { | 23 | +DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) |
62 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); | 24 | +DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) |
63 | uint32_t *matrix = g_malloc0(size); | 25 | +DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) |
26 | +DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
27 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/sme.decode | ||
30 | +++ b/target/arm/sme.decode | ||
31 | @@ -XXX,XX +XXX,XX @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ | ||
32 | |||
33 | LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr | ||
34 | STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr | ||
35 | + | ||
36 | +### SME Add Vector to Array | ||
37 | + | ||
38 | +&adda zad zn pm pn | ||
39 | +@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda | ||
40 | +@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda | ||
41 | + | ||
42 | +ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 | ||
43 | +ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 | ||
44 | +ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 | ||
45 | +ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 | ||
46 | diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/sme_helper.c | ||
49 | +++ b/target/arm/sme_helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ DO_ST(q, _be, MO_128) | ||
51 | DO_ST(q, _le, MO_128) | ||
52 | |||
53 | #undef DO_ST | ||
54 | + | ||
55 | +void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn, | ||
56 | + void *vpm, uint32_t desc) | ||
57 | +{ | ||
58 | + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; | ||
59 | + uint64_t *pn = vpn, *pm = vpm; | ||
60 | + uint32_t *zda = vzda, *zn = vzn; | ||
61 | + | ||
62 | + for (row = 0; row < oprsz; ) { | ||
63 | + uint64_t pa = pn[row >> 4]; | ||
64 | + do { | ||
65 | + if (pa & 1) { | ||
66 | + for (col = 0; col < oprsz; ) { | ||
67 | + uint64_t pb = pm[col >> 4]; | ||
68 | + do { | ||
69 | + if (pb & 1) { | ||
70 | + zda[tile_vslice_index(row) + H4(col)] += zn[H4(col)]; | ||
71 | + } | ||
72 | + pb >>= 4; | ||
73 | + } while (++col & 15); | ||
74 | + } | ||
75 | + } | ||
76 | + pa >>= 4; | ||
77 | + } while (++row & 15); | ||
78 | + } | ||
79 | +} | ||
80 | + | ||
81 | +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn, | ||
82 | + void *vpm, uint32_t desc) | ||
83 | +{ | ||
84 | + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; | ||
85 | + uint8_t *pn = vpn, *pm = vpm; | ||
86 | + uint64_t *zda = vzda, *zn = vzn; | ||
87 | + | ||
88 | + for (row = 0; row < oprsz; ++row) { | ||
89 | + if (pn[H1(row)] & 1) { | ||
90 | + for (col = 0; col < oprsz; ++col) { | ||
91 | + if (pm[H1(col)] & 1) { | ||
92 | + zda[tile_vslice_index(row) + col] += zn[col]; | ||
93 | + } | ||
94 | + } | ||
95 | + } | ||
96 | + } | ||
97 | +} | ||
98 | + | ||
99 | +void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn, | ||
100 | + void *vpm, uint32_t desc) | ||
101 | +{ | ||
102 | + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; | ||
103 | + uint64_t *pn = vpn, *pm = vpm; | ||
104 | + uint32_t *zda = vzda, *zn = vzn; | ||
105 | + | ||
106 | + for (row = 0; row < oprsz; ) { | ||
107 | + uint64_t pa = pn[row >> 4]; | ||
108 | + do { | ||
109 | + if (pa & 1) { | ||
110 | + uint32_t zn_row = zn[H4(row)]; | ||
111 | + for (col = 0; col < oprsz; ) { | ||
112 | + uint64_t pb = pm[col >> 4]; | ||
113 | + do { | ||
114 | + if (pb & 1) { | ||
115 | + zda[tile_vslice_index(row) + H4(col)] += zn_row; | ||
116 | + } | ||
117 | + pb >>= 4; | ||
118 | + } while (++col & 15); | ||
119 | + } | ||
120 | + } | ||
121 | + pa >>= 4; | ||
122 | + } while (++row & 15); | ||
123 | + } | ||
124 | +} | ||
125 | + | ||
126 | +void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, | ||
127 | + void *vpm, uint32_t desc) | ||
128 | +{ | ||
129 | + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; | ||
130 | + uint8_t *pn = vpn, *pm = vpm; | ||
131 | + uint64_t *zda = vzda, *zn = vzn; | ||
132 | + | ||
133 | + for (row = 0; row < oprsz; ++row) { | ||
134 | + if (pn[H1(row)] & 1) { | ||
135 | + uint64_t zn_row = zn[row]; | ||
136 | + for (col = 0; col < oprsz; ++col) { | ||
137 | + if (pm[H1(col)] & 1) { | ||
138 | + zda[tile_vslice_index(row) + col] += zn_row; | ||
139 | + } | ||
140 | + } | ||
141 | + } | ||
142 | + } | ||
143 | +} | ||
144 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
145 | index XXXXXXX..XXXXXXX 100644 | ||
146 | --- a/target/arm/translate-sme.c | ||
147 | +++ b/target/arm/translate-sme.c | ||
148 | @@ -XXX,XX +XXX,XX @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) | ||
149 | |||
150 | TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) | ||
151 | TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) | ||
152 | + | ||
153 | +static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, | ||
154 | + gen_helper_gvec_4 *fn) | ||
155 | +{ | ||
156 | + int svl = streaming_vec_reg_size(s); | ||
157 | + uint32_t desc = simd_desc(svl, svl, 0); | ||
158 | + TCGv_ptr za, zn, pn, pm; | ||
159 | + | ||
160 | + if (!sme_smza_enabled_check(s)) { | ||
161 | + return true; | ||
162 | + } | ||
163 | + | ||
164 | + /* Sum XZR+zad to find ZAd. */ | ||
165 | + za = get_tile_rowcol(s, esz, 31, a->zad, false); | ||
166 | + zn = vec_full_reg_ptr(s, a->zn); | ||
167 | + pn = pred_full_reg_ptr(s, a->pn); | ||
168 | + pm = pred_full_reg_ptr(s, a->pm); | ||
169 | + | ||
170 | + fn(za, zn, pn, pm, tcg_constant_i32(desc)); | ||
171 | + | ||
172 | + tcg_temp_free_ptr(za); | ||
173 | + tcg_temp_free_ptr(zn); | ||
174 | + tcg_temp_free_ptr(pn); | ||
175 | + tcg_temp_free_ptr(pm); | ||
176 | + return true; | ||
177 | +} | ||
178 | + | ||
179 | +TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) | ||
180 | +TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) | ||
181 | +TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) | ||
182 | +TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) | ||
64 | -- | 183 | -- |
65 | 2.25.1 | 184 | 2.25.1 |
66 | |||
67 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Message-id: 20220708151540.18136-25-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/helper-sme.h | 5 +++ | ||
9 | target/arm/sme.decode | 9 +++++ | ||
10 | target/arm/sme_helper.c | 69 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-sme.c | 32 ++++++++++++++++++ | ||
12 | 4 files changed, 115 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/helper-sme.h | ||
17 | +++ b/target/arm/helper-sme.h | ||
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
19 | DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
20 | DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
21 | DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
22 | + | ||
23 | +DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, | ||
24 | + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) | ||
27 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/sme.decode | ||
30 | +++ b/target/arm/sme.decode | ||
31 | @@ -XXX,XX +XXX,XX @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 | ||
32 | ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 | ||
33 | ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 | ||
34 | ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 | ||
35 | + | ||
36 | +### SME Outer Product | ||
37 | + | ||
38 | +&op zad zn zm pm pn sub:bool | ||
39 | +@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op | ||
40 | +@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op | ||
41 | + | ||
42 | +FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 | ||
43 | +FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 | ||
44 | diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/sme_helper.c | ||
47 | +++ b/target/arm/sme_helper.c | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | #include "exec/cpu_ldst.h" | ||
50 | #include "exec/exec-all.h" | ||
51 | #include "qemu/int128.h" | ||
52 | +#include "fpu/softfloat.h" | ||
53 | #include "vec_internal.h" | ||
54 | #include "sve_ldst_internal.h" | ||
55 | |||
56 | @@ -XXX,XX +XXX,XX @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, | ||
57 | } | ||
58 | } | ||
59 | } | ||
60 | + | ||
61 | +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, | ||
62 | + void *vpm, void *vst, uint32_t desc) | ||
63 | +{ | ||
64 | + intptr_t row, col, oprsz = simd_maxsz(desc); | ||
65 | + uint32_t neg = simd_data(desc) << 31; | ||
66 | + uint16_t *pn = vpn, *pm = vpm; | ||
67 | + float_status fpst; | ||
68 | + | ||
69 | + /* | ||
70 | + * Make a copy of float_status because this operation does not | ||
71 | + * update the cumulative fp exception status. It also produces | ||
72 | + * default nans. | ||
73 | + */ | ||
74 | + fpst = *(float_status *)vst; | ||
75 | + set_default_nan_mode(true, &fpst); | ||
76 | + | ||
77 | + for (row = 0; row < oprsz; ) { | ||
78 | + uint16_t pa = pn[H2(row >> 4)]; | ||
79 | + do { | ||
80 | + if (pa & 1) { | ||
81 | + void *vza_row = vza + tile_vslice_offset(row); | ||
82 | + uint32_t n = *(uint32_t *)(vzn + H1_4(row)) ^ neg; | ||
83 | + | ||
84 | + for (col = 0; col < oprsz; ) { | ||
85 | + uint16_t pb = pm[H2(col >> 4)]; | ||
86 | + do { | ||
87 | + if (pb & 1) { | ||
88 | + uint32_t *a = vza_row + H1_4(col); | ||
89 | + uint32_t *m = vzm + H1_4(col); | ||
90 | + *a = float32_muladd(n, *m, *a, 0, vst); | ||
91 | + } | ||
92 | + col += 4; | ||
93 | + pb >>= 4; | ||
94 | + } while (col & 15); | ||
95 | + } | ||
96 | + } | ||
97 | + row += 4; | ||
98 | + pa >>= 4; | ||
99 | + } while (row & 15); | ||
100 | + } | ||
101 | +} | ||
102 | + | ||
103 | +void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, | ||
104 | + void *vpm, void *vst, uint32_t desc) | ||
105 | +{ | ||
106 | + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; | ||
107 | + uint64_t neg = (uint64_t)simd_data(desc) << 63; | ||
108 | + uint64_t *za = vza, *zn = vzn, *zm = vzm; | ||
109 | + uint8_t *pn = vpn, *pm = vpm; | ||
110 | + float_status fpst = *(float_status *)vst; | ||
111 | + | ||
112 | + set_default_nan_mode(true, &fpst); | ||
113 | + | ||
114 | + for (row = 0; row < oprsz; ++row) { | ||
115 | + if (pn[H1(row)] & 1) { | ||
116 | + uint64_t *za_row = &za[tile_vslice_index(row)]; | ||
117 | + uint64_t n = zn[row] ^ neg; | ||
118 | + | ||
119 | + for (col = 0; col < oprsz; ++col) { | ||
120 | + if (pm[H1(col)] & 1) { | ||
121 | + uint64_t *a = &za_row[col]; | ||
122 | + *a = float64_muladd(n, zm[col], *a, 0, &fpst); | ||
123 | + } | ||
124 | + } | ||
125 | + } | ||
126 | + } | ||
127 | +} | ||
128 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
129 | index XXXXXXX..XXXXXXX 100644 | ||
130 | --- a/target/arm/translate-sme.c | ||
131 | +++ b/target/arm/translate-sme.c | ||
132 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) | ||
133 | TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) | ||
134 | TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) | ||
135 | TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) | ||
136 | + | ||
137 | +static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, | ||
138 | + gen_helper_gvec_5_ptr *fn) | ||
139 | +{ | ||
140 | + int svl = streaming_vec_reg_size(s); | ||
141 | + uint32_t desc = simd_desc(svl, svl, a->sub); | ||
142 | + TCGv_ptr za, zn, zm, pn, pm, fpst; | ||
143 | + | ||
144 | + if (!sme_smza_enabled_check(s)) { | ||
145 | + return true; | ||
146 | + } | ||
147 | + | ||
148 | + /* Sum XZR+zad to find ZAd. */ | ||
149 | + za = get_tile_rowcol(s, esz, 31, a->zad, false); | ||
150 | + zn = vec_full_reg_ptr(s, a->zn); | ||
151 | + zm = vec_full_reg_ptr(s, a->zm); | ||
152 | + pn = pred_full_reg_ptr(s, a->pn); | ||
153 | + pm = pred_full_reg_ptr(s, a->pm); | ||
154 | + fpst = fpstatus_ptr(FPST_FPCR); | ||
155 | + | ||
156 | + fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); | ||
157 | + | ||
158 | + tcg_temp_free_ptr(za); | ||
159 | + tcg_temp_free_ptr(zn); | ||
160 | + tcg_temp_free_ptr(pn); | ||
161 | + tcg_temp_free_ptr(pm); | ||
162 | + tcg_temp_free_ptr(fpst); | ||
163 | + return true; | ||
164 | +} | ||
165 | + | ||
166 | +TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) | ||
167 | +TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) | ||
168 | -- | ||
169 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Message-id: 20220708151540.18136-26-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/helper-sme.h | 2 ++ | ||
9 | target/arm/sme.decode | 2 ++ | ||
10 | target/arm/sme_helper.c | 56 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-sme.c | 30 ++++++++++++++++++++ | ||
12 | 4 files changed, 90 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/helper-sme.h | ||
17 | +++ b/target/arm/helper-sme.h | ||
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, | ||
19 | void, ptr, ptr, ptr, ptr, ptr, ptr, i32) | ||
20 | DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, | ||
21 | void, ptr, ptr, ptr, ptr, ptr, ptr, i32) | ||
22 | +DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, | ||
23 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
24 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/arm/sme.decode | ||
27 | +++ b/target/arm/sme.decode | ||
28 | @@ -XXX,XX +XXX,XX @@ ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 | ||
29 | |||
30 | FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 | ||
31 | FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 | ||
32 | + | ||
33 | +BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 | ||
34 | diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/sme_helper.c | ||
37 | +++ b/target/arm/sme_helper.c | ||
38 | @@ -XXX,XX +XXX,XX @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, | ||
39 | } | ||
40 | } | ||
41 | } | ||
42 | + | ||
43 | +/* | ||
44 | + * Alter PAIR as needed for controlling predicates being false, | ||
45 | + * and for NEG on an enabled row element. | ||
46 | + */ | ||
47 | +static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg) | ||
48 | +{ | ||
49 | + /* | ||
50 | + * The pseudocode uses a conditional negate after the conditional zero. | ||
51 | + * It is simpler here to unconditionally negate before conditional zero. | ||
52 | + */ | ||
53 | + pair ^= neg; | ||
54 | + if (!(pg & 1)) { | ||
55 | + pair &= 0xffff0000u; | ||
56 | + } | ||
57 | + if (!(pg & 4)) { | ||
58 | + pair &= 0x0000ffffu; | ||
59 | + } | ||
60 | + return pair; | ||
61 | +} | ||
62 | + | ||
63 | +void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, | ||
64 | + void *vpm, uint32_t desc) | ||
65 | +{ | ||
66 | + intptr_t row, col, oprsz = simd_maxsz(desc); | ||
67 | + uint32_t neg = simd_data(desc) * 0x80008000u; | ||
68 | + uint16_t *pn = vpn, *pm = vpm; | ||
69 | + | ||
70 | + for (row = 0; row < oprsz; ) { | ||
71 | + uint16_t prow = pn[H2(row >> 4)]; | ||
72 | + do { | ||
73 | + void *vza_row = vza + tile_vslice_offset(row); | ||
74 | + uint32_t n = *(uint32_t *)(vzn + H1_4(row)); | ||
75 | + | ||
76 | + n = f16mop_adj_pair(n, prow, neg); | ||
77 | + | ||
78 | + for (col = 0; col < oprsz; ) { | ||
79 | + uint16_t pcol = pm[H2(col >> 4)]; | ||
80 | + do { | ||
81 | + if (prow & pcol & 0b0101) { | ||
82 | + uint32_t *a = vza_row + H1_4(col); | ||
83 | + uint32_t m = *(uint32_t *)(vzm + H1_4(col)); | ||
84 | + | ||
85 | + m = f16mop_adj_pair(m, pcol, 0); | ||
86 | + *a = bfdotadd(*a, n, m); | ||
87 | + | ||
88 | + col += 4; | ||
89 | + pcol >>= 4; | ||
90 | + } | ||
91 | + } while (col & 15); | ||
92 | + } | ||
93 | + row += 4; | ||
94 | + prow >>= 4; | ||
95 | + } while (row & 15); | ||
96 | + } | ||
97 | +} | ||
98 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/target/arm/translate-sme.c | ||
101 | +++ b/target/arm/translate-sme.c | ||
102 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) | ||
103 | TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) | ||
104 | TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) | ||
105 | |||
106 | +static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, | ||
107 | + gen_helper_gvec_5 *fn) | ||
108 | +{ | ||
109 | + int svl = streaming_vec_reg_size(s); | ||
110 | + uint32_t desc = simd_desc(svl, svl, a->sub); | ||
111 | + TCGv_ptr za, zn, zm, pn, pm; | ||
112 | + | ||
113 | + if (!sme_smza_enabled_check(s)) { | ||
114 | + return true; | ||
115 | + } | ||
116 | + | ||
117 | + /* Sum XZR+zad to find ZAd. */ | ||
118 | + za = get_tile_rowcol(s, esz, 31, a->zad, false); | ||
119 | + zn = vec_full_reg_ptr(s, a->zn); | ||
120 | + zm = vec_full_reg_ptr(s, a->zm); | ||
121 | + pn = pred_full_reg_ptr(s, a->pn); | ||
122 | + pm = pred_full_reg_ptr(s, a->pm); | ||
123 | + | ||
124 | + fn(za, zn, zm, pn, pm, tcg_constant_i32(desc)); | ||
125 | + | ||
126 | + tcg_temp_free_ptr(za); | ||
127 | + tcg_temp_free_ptr(zn); | ||
128 | + tcg_temp_free_ptr(pn); | ||
129 | + tcg_temp_free_ptr(pm); | ||
130 | + return true; | ||
131 | +} | ||
132 | + | ||
133 | static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, | ||
134 | gen_helper_gvec_5_ptr *fn) | ||
135 | { | ||
136 | @@ -XXX,XX +XXX,XX @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, | ||
137 | |||
138 | TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) | ||
139 | TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) | ||
140 | + | ||
141 | +/* TODO: FEAT_EBF16 */ | ||
142 | +TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) | ||
143 | -- | ||
144 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Message-id: 20220708151540.18136-27-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/helper-sme.h | 2 ++ | ||
9 | target/arm/sme.decode | 1 + | ||
10 | target/arm/sme_helper.c | 74 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-sme.c | 1 + | ||
12 | 4 files changed, 78 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/helper-sme.h | ||
17 | +++ b/target/arm/helper-sme.h | ||
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
19 | DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
20 | DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
21 | |||
22 | +DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG, | ||
23 | + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) | ||
24 | DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, | ||
25 | void, ptr, ptr, ptr, ptr, ptr, ptr, i32) | ||
26 | DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, | ||
27 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/sme.decode | ||
30 | +++ b/target/arm/sme.decode | ||
31 | @@ -XXX,XX +XXX,XX @@ FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 | ||
32 | FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 | ||
33 | |||
34 | BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 | ||
35 | +FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 | ||
36 | diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/sme_helper.c | ||
39 | +++ b/target/arm/sme_helper.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg) | ||
41 | return pair; | ||
42 | } | ||
43 | |||
44 | +static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2, | ||
45 | + float_status *s_std, float_status *s_odd) | ||
46 | +{ | ||
47 | + float64 e1r = float16_to_float64(e1 & 0xffff, true, s_std); | ||
48 | + float64 e1c = float16_to_float64(e1 >> 16, true, s_std); | ||
49 | + float64 e2r = float16_to_float64(e2 & 0xffff, true, s_std); | ||
50 | + float64 e2c = float16_to_float64(e2 >> 16, true, s_std); | ||
51 | + float64 t64; | ||
52 | + float32 t32; | ||
53 | + | ||
54 | + /* | ||
55 | + * The ARM pseudocode function FPDot performs both multiplies | ||
56 | + * and the add with a single rounding operation. Emulate this | ||
57 | + * by performing the first multiply in round-to-odd, then doing | ||
58 | + * the second multiply as fused multiply-add, and rounding to | ||
59 | + * float32 all in one step. | ||
60 | + */ | ||
61 | + t64 = float64_mul(e1r, e2r, s_odd); | ||
62 | + t64 = float64r32_muladd(e1c, e2c, t64, 0, s_std); | ||
63 | + | ||
64 | + /* This conversion is exact, because we've already rounded. */ | ||
65 | + t32 = float64_to_float32(t64, s_std); | ||
66 | + | ||
67 | + /* The final accumulation step is not fused. */ | ||
68 | + return float32_add(sum, t32, s_std); | ||
69 | +} | ||
70 | + | ||
71 | +void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, | ||
72 | + void *vpm, void *vst, uint32_t desc) | ||
73 | +{ | ||
74 | + intptr_t row, col, oprsz = simd_maxsz(desc); | ||
75 | + uint32_t neg = simd_data(desc) * 0x80008000u; | ||
76 | + uint16_t *pn = vpn, *pm = vpm; | ||
77 | + float_status fpst_odd, fpst_std; | ||
78 | + | ||
79 | + /* | ||
80 | + * Make a copy of float_status because this operation does not | ||
81 | + * update the cumulative fp exception status. It also produces | ||
82 | + * default nans. Make a second copy with round-to-odd -- see above. | ||
83 | + */ | ||
84 | + fpst_std = *(float_status *)vst; | ||
85 | + set_default_nan_mode(true, &fpst_std); | ||
86 | + fpst_odd = fpst_std; | ||
87 | + set_float_rounding_mode(float_round_to_odd, &fpst_odd); | ||
88 | + | ||
89 | + for (row = 0; row < oprsz; ) { | ||
90 | + uint16_t prow = pn[H2(row >> 4)]; | ||
91 | + do { | ||
92 | + void *vza_row = vza + tile_vslice_offset(row); | ||
93 | + uint32_t n = *(uint32_t *)(vzn + H1_4(row)); | ||
94 | + | ||
95 | + n = f16mop_adj_pair(n, prow, neg); | ||
96 | + | ||
97 | + for (col = 0; col < oprsz; ) { | ||
98 | + uint16_t pcol = pm[H2(col >> 4)]; | ||
99 | + do { | ||
100 | + if (prow & pcol & 0b0101) { | ||
101 | + uint32_t *a = vza_row + H1_4(col); | ||
102 | + uint32_t m = *(uint32_t *)(vzm + H1_4(col)); | ||
103 | + | ||
104 | + m = f16mop_adj_pair(m, pcol, 0); | ||
105 | + *a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd); | ||
106 | + | ||
107 | + col += 4; | ||
108 | + pcol >>= 4; | ||
109 | + } | ||
110 | + } while (col & 15); | ||
111 | + } | ||
112 | + row += 4; | ||
113 | + prow >>= 4; | ||
114 | + } while (row & 15); | ||
115 | + } | ||
116 | +} | ||
117 | + | ||
118 | void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, | ||
119 | void *vpm, uint32_t desc) | ||
120 | { | ||
121 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/target/arm/translate-sme.c | ||
124 | +++ b/target/arm/translate-sme.c | ||
125 | @@ -XXX,XX +XXX,XX @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, | ||
126 | return true; | ||
127 | } | ||
128 | |||
129 | +TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_h) | ||
130 | TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) | ||
131 | TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) | ||
132 | |||
133 | -- | ||
134 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Share the code to set AArch32 max features so that we no | 3 | This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. |
4 | longer have code drift between qemu{-system,}-{arm,aarch64}. | ||
5 | 4 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-9-richard.henderson@linaro.org | 7 | Message-id: 20220708151540.18136-28-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | target/arm/internals.h | 2 + | 10 | target/arm/helper-sme.h | 16 ++++++++ |
12 | target/arm/cpu64.c | 50 +----------------- | 11 | target/arm/sme.decode | 10 +++++ |
13 | target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- | 12 | target/arm/sme_helper.c | 82 ++++++++++++++++++++++++++++++++++++++ |
14 | 3 files changed, 65 insertions(+), 101 deletions(-) | 13 | target/arm/translate-sme.c | 10 +++++ |
14 | 4 files changed, 118 insertions(+) | ||
15 | 15 | ||
16 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 16 | diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/internals.h | 18 | --- a/target/arm/helper-sme.h |
19 | +++ b/target/arm/internals.h | 19 | +++ b/target/arm/helper-sme.h |
20 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, |
21 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | 21 | void, ptr, ptr, ptr, ptr, ptr, ptr, i32) |
22 | #endif | 22 | DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, |
23 | 23 | void, ptr, ptr, ptr, ptr, ptr, i32) | |
24 | +void aa32_max_features(ARMCPU *cpu); | 24 | +DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG, |
25 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
26 | +DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG, | ||
27 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG, | ||
29 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
30 | +DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG, | ||
31 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG, | ||
33 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
34 | +DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG, | ||
35 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
36 | +DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG, | ||
37 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
38 | +DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG, | ||
39 | + void, ptr, ptr, ptr, ptr, ptr, i32) | ||
40 | diff --git a/target/arm/sme.decode b/target/arm/sme.decode | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/sme.decode | ||
43 | +++ b/target/arm/sme.decode | ||
44 | @@ -XXX,XX +XXX,XX @@ FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 | ||
45 | |||
46 | BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 | ||
47 | FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 | ||
25 | + | 48 | + |
26 | #endif | 49 | +SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 |
27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 50 | +SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 |
51 | +USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32 | ||
52 | +UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32 | ||
53 | + | ||
54 | +SMOPA_d 1010000 0 11 0 ..... ... ... ..... . 0 ... @op_64 | ||
55 | +SUMOPA_d 1010000 0 11 1 ..... ... ... ..... . 0 ... @op_64 | ||
56 | +USMOPA_d 1010000 1 11 0 ..... ... ... ..... . 0 ... @op_64 | ||
57 | +UMOPA_d 1010000 1 11 1 ..... ... ... ..... . 0 ... @op_64 | ||
58 | diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/target/arm/cpu64.c | 60 | --- a/target/arm/sme_helper.c |
30 | +++ b/target/arm/cpu64.c | 61 | +++ b/target/arm/sme_helper.c |
31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 62 | @@ -XXX,XX +XXX,XX @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, |
32 | { | 63 | } while (row & 15); |
33 | ARMCPU *cpu = ARM_CPU(obj); | 64 | } |
34 | uint64_t t; | 65 | } |
35 | - uint32_t u; | ||
36 | |||
37 | if (kvm_enabled() || hvf_enabled()) { | ||
38 | /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ | ||
39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
40 | t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
41 | cpu->isar.id_aa64zfr0 = t; | ||
42 | |||
43 | - /* Replicate the same data to the 32-bit id registers. */ | ||
44 | - u = cpu->isar.id_isar5; | ||
45 | - u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ | ||
46 | - u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); | ||
47 | - u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); | ||
48 | - u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); | ||
49 | - u = FIELD_DP32(u, ID_ISAR5, RDM, 1); | ||
50 | - u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); | ||
51 | - cpu->isar.id_isar5 = u; | ||
52 | - | ||
53 | - u = cpu->isar.id_isar6; | ||
54 | - u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); | ||
55 | - u = FIELD_DP32(u, ID_ISAR6, DP, 1); | ||
56 | - u = FIELD_DP32(u, ID_ISAR6, FHM, 1); | ||
57 | - u = FIELD_DP32(u, ID_ISAR6, SB, 1); | ||
58 | - u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); | ||
59 | - u = FIELD_DP32(u, ID_ISAR6, BF16, 1); | ||
60 | - u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); | ||
61 | - cpu->isar.id_isar6 = u; | ||
62 | - | ||
63 | - u = cpu->isar.id_pfr0; | ||
64 | - u = FIELD_DP32(u, ID_PFR0, DIT, 1); | ||
65 | - cpu->isar.id_pfr0 = u; | ||
66 | - | ||
67 | - u = cpu->isar.id_pfr2; | ||
68 | - u = FIELD_DP32(u, ID_PFR2, SSBS, 1); | ||
69 | - cpu->isar.id_pfr2 = u; | ||
70 | - | ||
71 | - u = cpu->isar.id_mmfr3; | ||
72 | - u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
73 | - cpu->isar.id_mmfr3 = u; | ||
74 | - | ||
75 | - u = cpu->isar.id_mmfr4; | ||
76 | - u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
77 | - u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
78 | - u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
79 | - u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
80 | - cpu->isar.id_mmfr4 = u; | ||
81 | - | ||
82 | t = cpu->isar.id_aa64dfr0; | ||
83 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
84 | cpu->isar.id_aa64dfr0 = t; | ||
85 | |||
86 | - u = cpu->isar.id_dfr0; | ||
87 | - u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
88 | - cpu->isar.id_dfr0 = u; | ||
89 | - | ||
90 | - u = cpu->isar.mvfr1; | ||
91 | - u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
92 | - u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
93 | - cpu->isar.mvfr1 = u; | ||
94 | + /* Replicate the same data to the 32-bit id registers. */ | ||
95 | + aa32_max_features(cpu); | ||
96 | |||
97 | #ifdef CONFIG_USER_ONLY | ||
98 | /* | ||
99 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/target/arm/cpu_tcg.c | ||
102 | +++ b/target/arm/cpu_tcg.c | ||
103 | @@ -XXX,XX +XXX,XX @@ | ||
104 | #endif | ||
105 | #include "cpregs.h" | ||
106 | |||
107 | + | 66 | + |
108 | +/* Share AArch32 -cpu max features with AArch64. */ | 67 | +typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); |
109 | +void aa32_max_features(ARMCPU *cpu) | 68 | + |
69 | +static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, | ||
70 | + uint8_t *pn, uint8_t *pm, | ||
71 | + uint32_t desc, IMOPFn *fn) | ||
110 | +{ | 72 | +{ |
111 | + uint32_t t; | 73 | + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; |
74 | + bool neg = simd_data(desc); | ||
112 | + | 75 | + |
113 | + /* Add additional features supported by QEMU */ | 76 | + for (row = 0; row < oprsz; ++row) { |
114 | + t = cpu->isar.id_isar5; | 77 | + uint8_t pa = pn[H1(row)]; |
115 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | 78 | + uint64_t *za_row = &za[tile_vslice_index(row)]; |
116 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | 79 | + uint64_t n = zn[row]; |
117 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
118 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
119 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
120 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
121 | + cpu->isar.id_isar5 = t; | ||
122 | + | 80 | + |
123 | + t = cpu->isar.id_isar6; | 81 | + for (col = 0; col < oprsz; ++col) { |
124 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | 82 | + uint8_t pb = pm[H1(col)]; |
125 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | 83 | + uint64_t *a = &za_row[col]; |
126 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
127 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
128 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
129 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
130 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
131 | + cpu->isar.id_isar6 = t; | ||
132 | + | 84 | + |
133 | + t = cpu->isar.mvfr1; | 85 | + *a = fn(n, zm[col], *a, pa & pb, neg); |
134 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | 86 | + } |
135 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | 87 | + } |
136 | + cpu->isar.mvfr1 = t; | ||
137 | + | ||
138 | + t = cpu->isar.mvfr2; | ||
139 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
140 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
141 | + cpu->isar.mvfr2 = t; | ||
142 | + | ||
143 | + t = cpu->isar.id_mmfr3; | ||
144 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
145 | + cpu->isar.id_mmfr3 = t; | ||
146 | + | ||
147 | + t = cpu->isar.id_mmfr4; | ||
148 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
149 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
150 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
151 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
152 | + cpu->isar.id_mmfr4 = t; | ||
153 | + | ||
154 | + t = cpu->isar.id_pfr0; | ||
155 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
156 | + cpu->isar.id_pfr0 = t; | ||
157 | + | ||
158 | + t = cpu->isar.id_pfr2; | ||
159 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
160 | + cpu->isar.id_pfr2 = t; | ||
161 | + | ||
162 | + t = cpu->isar.id_dfr0; | ||
163 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
164 | + cpu->isar.id_dfr0 = t; | ||
165 | +} | 88 | +} |
166 | + | 89 | + |
167 | #ifndef CONFIG_USER_ONLY | 90 | +#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ |
168 | static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 91 | +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ |
169 | { | 92 | +{ \ |
170 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | 93 | + uint32_t sum0 = 0, sum1 = 0; \ |
171 | static void arm_max_initfn(Object *obj) | 94 | + /* Apply P to N as a mask, making the inactive elements 0. */ \ |
172 | { | 95 | + n &= expand_pred_b(p); \ |
173 | ARMCPU *cpu = ARM_CPU(obj); | 96 | + sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ |
174 | - uint32_t t; | 97 | + sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ |
175 | 98 | + sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ | |
176 | /* aarch64_a57_initfn, advertising none of the aarch64 features */ | 99 | + sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ |
177 | cpu->dtb_compatible = "arm,cortex-a57"; | 100 | + sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ |
178 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | 101 | + sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \ |
179 | cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | 102 | + sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ |
180 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | 103 | + sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \ |
181 | 104 | + if (neg) { \ | |
182 | - /* Add additional features supported by QEMU */ | 105 | + sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \ |
183 | - t = cpu->isar.id_isar5; | 106 | + } else { \ |
184 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | 107 | + sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \ |
185 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | 108 | + } \ |
186 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | 109 | + return ((uint64_t)sum1 << 32) | sum0; \ |
187 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | 110 | +} |
188 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | 111 | + |
189 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | 112 | +#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ |
190 | - cpu->isar.id_isar5 = t; | 113 | +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ |
191 | - | 114 | +{ \ |
192 | - t = cpu->isar.id_isar6; | 115 | + uint64_t sum = 0; \ |
193 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | 116 | + /* Apply P to N as a mask, making the inactive elements 0. */ \ |
194 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | 117 | + n &= expand_pred_h(p); \ |
195 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | 118 | + sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ |
196 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | 119 | + sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ |
197 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | 120 | + sum += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ |
198 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | 121 | + sum += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ |
199 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | 122 | + return neg ? a - sum : a + sum; \ |
200 | - cpu->isar.id_isar6 = t; | 123 | +} |
201 | - | 124 | + |
202 | - t = cpu->isar.mvfr1; | 125 | +DEF_IMOP_32(smopa_s, int8_t, int8_t) |
203 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | 126 | +DEF_IMOP_32(umopa_s, uint8_t, uint8_t) |
204 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | 127 | +DEF_IMOP_32(sumopa_s, int8_t, uint8_t) |
205 | - cpu->isar.mvfr1 = t; | 128 | +DEF_IMOP_32(usmopa_s, uint8_t, int8_t) |
206 | - | 129 | + |
207 | - t = cpu->isar.mvfr2; | 130 | +DEF_IMOP_64(smopa_d, int16_t, int16_t) |
208 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | 131 | +DEF_IMOP_64(umopa_d, uint16_t, uint16_t) |
209 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | 132 | +DEF_IMOP_64(sumopa_d, int16_t, uint16_t) |
210 | - cpu->isar.mvfr2 = t; | 133 | +DEF_IMOP_64(usmopa_d, uint16_t, int16_t) |
211 | - | 134 | + |
212 | - t = cpu->isar.id_mmfr3; | 135 | +#define DEF_IMOPH(NAME) \ |
213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | 136 | + void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \ |
214 | - cpu->isar.id_mmfr3 = t; | 137 | + void *vpm, uint32_t desc) \ |
215 | - | 138 | + { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } |
216 | - t = cpu->isar.id_mmfr4; | 139 | + |
217 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | 140 | +DEF_IMOPH(smopa_s) |
218 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | 141 | +DEF_IMOPH(umopa_s) |
219 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | 142 | +DEF_IMOPH(sumopa_s) |
220 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | 143 | +DEF_IMOPH(usmopa_s) |
221 | - cpu->isar.id_mmfr4 = t; | 144 | +DEF_IMOPH(smopa_d) |
222 | - | 145 | +DEF_IMOPH(umopa_d) |
223 | - t = cpu->isar.id_pfr0; | 146 | +DEF_IMOPH(sumopa_d) |
224 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | 147 | +DEF_IMOPH(usmopa_d) |
225 | - cpu->isar.id_pfr0 = t; | 148 | diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c |
226 | - | 149 | index XXXXXXX..XXXXXXX 100644 |
227 | - t = cpu->isar.id_pfr2; | 150 | --- a/target/arm/translate-sme.c |
228 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | 151 | +++ b/target/arm/translate-sme.c |
229 | - cpu->isar.id_pfr2 = t; | 152 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_f |
230 | - | 153 | |
231 | - t = cpu->isar.id_dfr0; | 154 | /* TODO: FEAT_EBF16 */ |
232 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | 155 | TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) |
233 | - cpu->isar.id_dfr0 = t; | 156 | + |
234 | + aa32_max_features(cpu); | 157 | +TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) |
235 | 158 | +TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) | |
236 | #ifdef CONFIG_USER_ONLY | 159 | +TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa_s) |
237 | /* | 160 | +TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa_s) |
161 | + | ||
162 | +TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_smopa_d) | ||
163 | +TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_umopa_d) | ||
164 | +TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_sumopa_d) | ||
165 | +TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_usmopa_d) | ||
238 | -- | 166 | -- |
239 | 2.25.1 | 167 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We set this for qemu-system-aarch64, but failed to do so | 3 | This is an SVE instruction that operates using the SVE vector |
4 | for the strictly 32-bit emulation. | 4 | length but that it is present only if SME is implemented. |
5 | 5 | ||
6 | Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-8-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-29-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/cpu_tcg.c | 4 ++++ | 11 | target/arm/sve.decode | 20 +++++++++++++ |
13 | 1 file changed, 4 insertions(+) | 12 | target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++ |
13 | 2 files changed, 77 insertions(+) | ||
14 | 14 | ||
15 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 15 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu_tcg.c | 17 | --- a/target/arm/sve.decode |
18 | +++ b/target/arm/cpu_tcg.c | 18 | +++ b/target/arm/sve.decode |
19 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | 19 | @@ -XXX,XX +XXX,XX @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 |
20 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | 20 | |
21 | cpu->isar.id_pfr2 = t; | 21 | ### SVE2 floating-point bfloat16 dot-product (indexed) |
22 | 22 | BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 | |
23 | + t = cpu->isar.id_dfr0; | ||
24 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
25 | + cpu->isar.id_dfr0 = t; | ||
26 | + | 23 | + |
27 | #ifdef CONFIG_USER_ONLY | 24 | +### SVE broadcast predicate element |
28 | /* | 25 | + |
29 | * Break with true ARMv8 and add back old-style VFP short-vector support. | 26 | +&psel esz pd pn pm rv imm |
27 | +%psel_rv 16:2 !function=plus_12 | ||
28 | +%psel_imm_b 22:2 19:2 | ||
29 | +%psel_imm_h 22:2 20:1 | ||
30 | +%psel_imm_s 22:2 | ||
31 | +%psel_imm_d 23:1 | ||
32 | +@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ | ||
33 | + &psel rv=%psel_rv | ||
34 | + | ||
35 | +PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ | ||
36 | + @psel esz=0 imm=%psel_imm_b | ||
37 | +PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ | ||
38 | + @psel esz=1 imm=%psel_imm_h | ||
39 | +PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ | ||
40 | + @psel esz=2 imm=%psel_imm_s | ||
41 | +PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ | ||
42 | + @psel esz=3 imm=%psel_imm_d | ||
43 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/translate-sve.c | ||
46 | +++ b/target/arm/translate-sve.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) | ||
48 | |||
49 | TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) | ||
50 | TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) | ||
51 | + | ||
52 | +static bool trans_PSEL(DisasContext *s, arg_psel *a) | ||
53 | +{ | ||
54 | + int vl = vec_full_reg_size(s); | ||
55 | + int pl = pred_gvec_reg_size(s); | ||
56 | + int elements = vl >> a->esz; | ||
57 | + TCGv_i64 tmp, didx, dbit; | ||
58 | + TCGv_ptr ptr; | ||
59 | + | ||
60 | + if (!dc_isar_feature(aa64_sme, s)) { | ||
61 | + return false; | ||
62 | + } | ||
63 | + if (!sve_access_check(s)) { | ||
64 | + return true; | ||
65 | + } | ||
66 | + | ||
67 | + tmp = tcg_temp_new_i64(); | ||
68 | + dbit = tcg_temp_new_i64(); | ||
69 | + didx = tcg_temp_new_i64(); | ||
70 | + ptr = tcg_temp_new_ptr(); | ||
71 | + | ||
72 | + /* Compute the predicate element. */ | ||
73 | + tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm); | ||
74 | + if (is_power_of_2(elements)) { | ||
75 | + tcg_gen_andi_i64(tmp, tmp, elements - 1); | ||
76 | + } else { | ||
77 | + tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements)); | ||
78 | + } | ||
79 | + | ||
80 | + /* Extract the predicate byte and bit indices. */ | ||
81 | + tcg_gen_shli_i64(tmp, tmp, a->esz); | ||
82 | + tcg_gen_andi_i64(dbit, tmp, 7); | ||
83 | + tcg_gen_shri_i64(didx, tmp, 3); | ||
84 | + if (HOST_BIG_ENDIAN) { | ||
85 | + tcg_gen_xori_i64(didx, didx, 7); | ||
86 | + } | ||
87 | + | ||
88 | + /* Load the predicate word. */ | ||
89 | + tcg_gen_trunc_i64_ptr(ptr, didx); | ||
90 | + tcg_gen_add_ptr(ptr, ptr, cpu_env); | ||
91 | + tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); | ||
92 | + | ||
93 | + /* Extract the predicate bit and replicate to MO_64. */ | ||
94 | + tcg_gen_shr_i64(tmp, tmp, dbit); | ||
95 | + tcg_gen_andi_i64(tmp, tmp, 1); | ||
96 | + tcg_gen_neg_i64(tmp, tmp); | ||
97 | + | ||
98 | + /* Apply to either copy the source, or write zeros. */ | ||
99 | + tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), | ||
100 | + pred_full_reg_offset(s, a->pn), tmp, pl, pl); | ||
101 | + | ||
102 | + tcg_temp_free_i64(tmp); | ||
103 | + tcg_temp_free_i64(dbit); | ||
104 | + tcg_temp_free_i64(didx); | ||
105 | + tcg_temp_free_ptr(ptr); | ||
106 | + return true; | ||
107 | +} | ||
30 | -- | 108 | -- |
31 | 2.25.1 | 109 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns cache speculation, which TCG does | 3 | This is an SVE instruction that operates using the SVE vector |
4 | not implement. Thus we can trivially enable this feature. | 4 | length but that it is present only if SME is implemented. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-22-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-30-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 11 | target/arm/helper-sve.h | 2 ++ |
12 | target/arm/cpu64.c | 1 + | 12 | target/arm/sve.decode | 1 + |
13 | target/arm/cpu_tcg.c | 1 + | 13 | target/arm/sve_helper.c | 16 ++++++++++++++++ |
14 | 3 files changed, 3 insertions(+) | 14 | target/arm/translate-sve.c | 2 ++ |
15 | 4 files changed, 21 insertions(+) | ||
15 | 16 | ||
16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 17 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/emulation.rst | 19 | --- a/target/arm/helper-sve.h |
19 | +++ b/docs/system/arm/emulation.rst | 20 | +++ b/target/arm/helper-sve.h |
20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
21 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | 22 | |
22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | 23 | DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | 24 | |
24 | +- FEAT_CSV3 (Cache speculation variant 3) | 25 | +DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
25 | - FEAT_DIT (Data Independent Timing instructions) | 26 | + |
26 | - FEAT_DPB (DC CVAP instruction) | 27 | DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
27 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 28 | DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 29 | DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
30 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/cpu64.c | 32 | --- a/target/arm/sve.decode |
31 | +++ b/target/arm/cpu64.c | 33 | +++ b/target/arm/sve.decode |
32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 34 | @@ -XXX,XX +XXX,XX @@ REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn |
33 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | 35 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn |
34 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | 36 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn |
35 | t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | 37 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn |
36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ | 38 | +REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0 |
37 | cpu->isar.id_aa64pfr0 = t; | 39 | |
38 | 40 | # SVE vector splice (predicated, destructive) | |
39 | t = cpu->isar.id_aa64pfr1; | 41 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm |
40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 42 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c |
41 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
42 | --- a/target/arm/cpu_tcg.c | 44 | --- a/target/arm/sve_helper.c |
43 | +++ b/target/arm/cpu_tcg.c | 45 | +++ b/target/arm/sve_helper.c |
44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 46 | @@ -XXX,XX +XXX,XX @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) |
45 | cpu->isar.id_pfr0 = t; | 47 | |
46 | 48 | DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) | |
47 | t = cpu->isar.id_pfr2; | 49 | |
48 | + t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ | 50 | +void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc) |
49 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | 51 | +{ |
50 | cpu->isar.id_pfr2 = t; | 52 | + intptr_t i, opr_sz = simd_oprsz(desc) / 8; |
53 | + uint64_t *d = vd, *n = vn; | ||
54 | + uint8_t *pg = vg; | ||
55 | + | ||
56 | + for (i = 0; i < opr_sz; i += 2) { | ||
57 | + if (pg[H1(i)] & 1) { | ||
58 | + uint64_t n0 = n[i + 0]; | ||
59 | + uint64_t n1 = n[i + 1]; | ||
60 | + d[i + 0] = n1; | ||
61 | + d[i + 1] = n0; | ||
62 | + } | ||
63 | + } | ||
64 | +} | ||
65 | + | ||
66 | DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) | ||
67 | DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) | ||
68 | DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) | ||
69 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/target/arm/translate-sve.c | ||
72 | +++ b/target/arm/translate-sve.c | ||
73 | @@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) | ||
74 | TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, | ||
75 | a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0) | ||
76 | |||
77 | +TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0) | ||
78 | + | ||
79 | TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, | ||
80 | gen_helper_sve_splice, a, a->esz) | ||
51 | 81 | ||
52 | -- | 82 | -- |
53 | 2.25.1 | 83 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Instead of starting with cortex-a15 and adding v8 features to | 3 | This is an SVE instruction that operates using the SVE vector |
4 | a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. | 4 | length but that it is present only if SME is implemented. |
5 | This fixes the long-standing to-do where we only enabled v8 | ||
6 | features for user-only. | ||
7 | 5 | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20220506180242.216785-7-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-31-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 10 | --- |
13 | target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- | 11 | target/arm/helper.h | 18 +++++++ |
14 | 1 file changed, 92 insertions(+), 59 deletions(-) | 12 | target/arm/sve.decode | 5 ++ |
13 | target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/vec_helper.c | 24 +++++++++ | ||
15 | 4 files changed, 149 insertions(+) | ||
15 | 16 | ||
16 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 17 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu_tcg.c | 19 | --- a/target/arm/helper.h |
19 | +++ b/target/arm/cpu_tcg.c | 20 | +++ b/target/arm/helper.h |
20 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, |
21 | static void arm_max_initfn(Object *obj) | 22 | DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, |
22 | { | 23 | void, ptr, ptr, ptr, ptr, ptr, i32) |
23 | ARMCPU *cpu = ARM_CPU(obj); | 24 | |
24 | + uint32_t t; | 25 | +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, |
25 | 26 | + void, ptr, ptr, ptr, ptr, i32) | |
26 | - cortex_a15_initfn(obj); | 27 | +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, |
27 | + /* aarch64_a57_initfn, advertising none of the aarch64 features */ | 28 | + void, ptr, ptr, ptr, ptr, i32) |
28 | + cpu->dtb_compatible = "arm,cortex-a57"; | 29 | +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, |
29 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 30 | + void, ptr, ptr, ptr, ptr, i32) |
30 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | 31 | +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, |
31 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | 32 | + void, ptr, ptr, ptr, ptr, i32) |
32 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | 33 | + |
33 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | 34 | +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, |
34 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | 35 | + void, ptr, ptr, ptr, ptr, i32) |
35 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | 36 | +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, |
36 | + cpu->midr = 0x411fd070; | 37 | + void, ptr, ptr, ptr, ptr, i32) |
37 | + cpu->revidr = 0x00000000; | 38 | +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, |
38 | + cpu->reset_fpsid = 0x41034070; | 39 | + void, ptr, ptr, ptr, ptr, i32) |
39 | + cpu->isar.mvfr0 = 0x10110222; | 40 | +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, |
40 | + cpu->isar.mvfr1 = 0x12111111; | 41 | + void, ptr, ptr, ptr, ptr, i32) |
41 | + cpu->isar.mvfr2 = 0x00000043; | 42 | + |
42 | + cpu->ctr = 0x8444c004; | 43 | #ifdef TARGET_AARCH64 |
43 | + cpu->reset_sctlr = 0x00c50838; | 44 | #include "helper-a64.h" |
44 | + cpu->isar.id_pfr0 = 0x00000131; | 45 | #include "helper-sve.h" |
45 | + cpu->isar.id_pfr1 = 0x00011011; | 46 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode |
46 | + cpu->isar.id_dfr0 = 0x03010066; | 47 | index XXXXXXX..XXXXXXX 100644 |
47 | + cpu->id_afr0 = 0x00000000; | 48 | --- a/target/arm/sve.decode |
48 | + cpu->isar.id_mmfr0 = 0x10101105; | 49 | +++ b/target/arm/sve.decode |
49 | + cpu->isar.id_mmfr1 = 0x40000000; | 50 | @@ -XXX,XX +XXX,XX @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ |
50 | + cpu->isar.id_mmfr2 = 0x01260000; | 51 | @psel esz=2 imm=%psel_imm_s |
51 | + cpu->isar.id_mmfr3 = 0x02102211; | 52 | PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ |
52 | + cpu->isar.id_isar0 = 0x02101110; | 53 | @psel esz=3 imm=%psel_imm_d |
53 | + cpu->isar.id_isar1 = 0x13112111; | 54 | + |
54 | + cpu->isar.id_isar2 = 0x21232042; | 55 | +### SVE clamp |
55 | + cpu->isar.id_isar3 = 0x01112131; | 56 | + |
56 | + cpu->isar.id_isar4 = 0x00011142; | 57 | +SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm |
57 | + cpu->isar.id_isar5 = 0x00011121; | 58 | +UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm |
58 | + cpu->isar.id_isar6 = 0; | 59 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
59 | + cpu->isar.dbgdidr = 0x3516d000; | 60 | index XXXXXXX..XXXXXXX 100644 |
60 | + cpu->clidr = 0x0a200023; | 61 | --- a/target/arm/translate-sve.c |
61 | + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | 62 | +++ b/target/arm/translate-sve.c |
62 | + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | 63 | @@ -XXX,XX +XXX,XX @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) |
63 | + cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | 64 | tcg_temp_free_ptr(ptr); |
64 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | 65 | return true; |
65 | |||
66 | - /* old-style VFP short-vector support */ | ||
67 | - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
68 | + /* Add additional features supported by QEMU */ | ||
69 | + t = cpu->isar.id_isar5; | ||
70 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
71 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
72 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
73 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
74 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
75 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
76 | + cpu->isar.id_isar5 = t; | ||
77 | + | ||
78 | + t = cpu->isar.id_isar6; | ||
79 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
80 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
81 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
82 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
83 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
84 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
85 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
86 | + cpu->isar.id_isar6 = t; | ||
87 | + | ||
88 | + t = cpu->isar.mvfr1; | ||
89 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
90 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
91 | + cpu->isar.mvfr1 = t; | ||
92 | + | ||
93 | + t = cpu->isar.mvfr2; | ||
94 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
95 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
96 | + cpu->isar.mvfr2 = t; | ||
97 | + | ||
98 | + t = cpu->isar.id_mmfr3; | ||
99 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
100 | + cpu->isar.id_mmfr3 = t; | ||
101 | + | ||
102 | + t = cpu->isar.id_mmfr4; | ||
103 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
104 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
105 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
106 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
107 | + cpu->isar.id_mmfr4 = t; | ||
108 | + | ||
109 | + t = cpu->isar.id_pfr0; | ||
110 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
111 | + cpu->isar.id_pfr0 = t; | ||
112 | + | ||
113 | + t = cpu->isar.id_pfr2; | ||
114 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
115 | + cpu->isar.id_pfr2 = t; | ||
116 | |||
117 | #ifdef CONFIG_USER_ONLY | ||
118 | /* | ||
119 | - * We don't set these in system emulation mode for the moment, | ||
120 | - * since we don't correctly set (all of) the ID registers to | ||
121 | - * advertise them. | ||
122 | + * Break with true ARMv8 and add back old-style VFP short-vector support. | ||
123 | + * Only do this for user-mode, where -cpu max is the default, so that | ||
124 | + * older v6 and v7 programs are more likely to work without adjustment. | ||
125 | */ | ||
126 | - set_feature(&cpu->env, ARM_FEATURE_V8); | ||
127 | - { | ||
128 | - uint32_t t; | ||
129 | - | ||
130 | - t = cpu->isar.id_isar5; | ||
131 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
132 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
133 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
134 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
135 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
136 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
137 | - cpu->isar.id_isar5 = t; | ||
138 | - | ||
139 | - t = cpu->isar.id_isar6; | ||
140 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
141 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
142 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
143 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
144 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
145 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
146 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
147 | - cpu->isar.id_isar6 = t; | ||
148 | - | ||
149 | - t = cpu->isar.mvfr1; | ||
150 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
151 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
152 | - cpu->isar.mvfr1 = t; | ||
153 | - | ||
154 | - t = cpu->isar.mvfr2; | ||
155 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
156 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
157 | - cpu->isar.mvfr2 = t; | ||
158 | - | ||
159 | - t = cpu->isar.id_mmfr3; | ||
160 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
161 | - cpu->isar.id_mmfr3 = t; | ||
162 | - | ||
163 | - t = cpu->isar.id_mmfr4; | ||
164 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
165 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
166 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
167 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
168 | - cpu->isar.id_mmfr4 = t; | ||
169 | - | ||
170 | - t = cpu->isar.id_pfr0; | ||
171 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
172 | - cpu->isar.id_pfr0 = t; | ||
173 | - | ||
174 | - t = cpu->isar.id_pfr2; | ||
175 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
176 | - cpu->isar.id_pfr2 = t; | ||
177 | - } | ||
178 | -#endif /* CONFIG_USER_ONLY */ | ||
179 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
180 | +#endif | ||
181 | } | 66 | } |
182 | #endif /* !TARGET_AARCH64 */ | 67 | + |
183 | 68 | +static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) | |
69 | +{ | ||
70 | + tcg_gen_smax_i32(d, a, n); | ||
71 | + tcg_gen_smin_i32(d, d, m); | ||
72 | +} | ||
73 | + | ||
74 | +static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) | ||
75 | +{ | ||
76 | + tcg_gen_smax_i64(d, a, n); | ||
77 | + tcg_gen_smin_i64(d, d, m); | ||
78 | +} | ||
79 | + | ||
80 | +static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | ||
81 | + TCGv_vec m, TCGv_vec a) | ||
82 | +{ | ||
83 | + tcg_gen_smax_vec(vece, d, a, n); | ||
84 | + tcg_gen_smin_vec(vece, d, d, m); | ||
85 | +} | ||
86 | + | ||
87 | +static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | ||
88 | + uint32_t a, uint32_t oprsz, uint32_t maxsz) | ||
89 | +{ | ||
90 | + static const TCGOpcode vecop[] = { | ||
91 | + INDEX_op_smin_vec, INDEX_op_smax_vec, 0 | ||
92 | + }; | ||
93 | + static const GVecGen4 ops[4] = { | ||
94 | + { .fniv = gen_sclamp_vec, | ||
95 | + .fno = gen_helper_gvec_sclamp_b, | ||
96 | + .opt_opc = vecop, | ||
97 | + .vece = MO_8 }, | ||
98 | + { .fniv = gen_sclamp_vec, | ||
99 | + .fno = gen_helper_gvec_sclamp_h, | ||
100 | + .opt_opc = vecop, | ||
101 | + .vece = MO_16 }, | ||
102 | + { .fni4 = gen_sclamp_i32, | ||
103 | + .fniv = gen_sclamp_vec, | ||
104 | + .fno = gen_helper_gvec_sclamp_s, | ||
105 | + .opt_opc = vecop, | ||
106 | + .vece = MO_32 }, | ||
107 | + { .fni8 = gen_sclamp_i64, | ||
108 | + .fniv = gen_sclamp_vec, | ||
109 | + .fno = gen_helper_gvec_sclamp_d, | ||
110 | + .opt_opc = vecop, | ||
111 | + .vece = MO_64, | ||
112 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64 } | ||
113 | + }; | ||
114 | + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); | ||
115 | +} | ||
116 | + | ||
117 | +TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a) | ||
118 | + | ||
119 | +static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) | ||
120 | +{ | ||
121 | + tcg_gen_umax_i32(d, a, n); | ||
122 | + tcg_gen_umin_i32(d, d, m); | ||
123 | +} | ||
124 | + | ||
125 | +static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) | ||
126 | +{ | ||
127 | + tcg_gen_umax_i64(d, a, n); | ||
128 | + tcg_gen_umin_i64(d, d, m); | ||
129 | +} | ||
130 | + | ||
131 | +static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | ||
132 | + TCGv_vec m, TCGv_vec a) | ||
133 | +{ | ||
134 | + tcg_gen_umax_vec(vece, d, a, n); | ||
135 | + tcg_gen_umin_vec(vece, d, d, m); | ||
136 | +} | ||
137 | + | ||
138 | +static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | ||
139 | + uint32_t a, uint32_t oprsz, uint32_t maxsz) | ||
140 | +{ | ||
141 | + static const TCGOpcode vecop[] = { | ||
142 | + INDEX_op_umin_vec, INDEX_op_umax_vec, 0 | ||
143 | + }; | ||
144 | + static const GVecGen4 ops[4] = { | ||
145 | + { .fniv = gen_uclamp_vec, | ||
146 | + .fno = gen_helper_gvec_uclamp_b, | ||
147 | + .opt_opc = vecop, | ||
148 | + .vece = MO_8 }, | ||
149 | + { .fniv = gen_uclamp_vec, | ||
150 | + .fno = gen_helper_gvec_uclamp_h, | ||
151 | + .opt_opc = vecop, | ||
152 | + .vece = MO_16 }, | ||
153 | + { .fni4 = gen_uclamp_i32, | ||
154 | + .fniv = gen_uclamp_vec, | ||
155 | + .fno = gen_helper_gvec_uclamp_s, | ||
156 | + .opt_opc = vecop, | ||
157 | + .vece = MO_32 }, | ||
158 | + { .fni8 = gen_uclamp_i64, | ||
159 | + .fniv = gen_uclamp_vec, | ||
160 | + .fno = gen_helper_gvec_uclamp_d, | ||
161 | + .opt_opc = vecop, | ||
162 | + .vece = MO_64, | ||
163 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64 } | ||
164 | + }; | ||
165 | + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); | ||
166 | +} | ||
167 | + | ||
168 | +TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a) | ||
169 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
170 | index XXXXXXX..XXXXXXX 100644 | ||
171 | --- a/target/arm/vec_helper.c | ||
172 | +++ b/target/arm/vec_helper.c | ||
173 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm, | ||
174 | } | ||
175 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
176 | } | ||
177 | + | ||
178 | +#define DO_CLAMP(NAME, TYPE) \ | ||
179 | +void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \ | ||
180 | +{ \ | ||
181 | + intptr_t i, opr_sz = simd_oprsz(desc); \ | ||
182 | + for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \ | ||
183 | + TYPE aa = *(TYPE *)(a + i); \ | ||
184 | + TYPE nn = *(TYPE *)(n + i); \ | ||
185 | + TYPE mm = *(TYPE *)(m + i); \ | ||
186 | + TYPE dd = MIN(MAX(aa, nn), mm); \ | ||
187 | + *(TYPE *)(d + i) = dd; \ | ||
188 | + } \ | ||
189 | + clear_tail(d, opr_sz, simd_maxsz(desc)); \ | ||
190 | +} | ||
191 | + | ||
192 | +DO_CLAMP(gvec_sclamp_b, int8_t) | ||
193 | +DO_CLAMP(gvec_sclamp_h, int16_t) | ||
194 | +DO_CLAMP(gvec_sclamp_s, int32_t) | ||
195 | +DO_CLAMP(gvec_sclamp_d, int64_t) | ||
196 | + | ||
197 | +DO_CLAMP(gvec_uclamp_b, uint8_t) | ||
198 | +DO_CLAMP(gvec_uclamp_h, uint16_t) | ||
199 | +DO_CLAMP(gvec_uclamp_s, uint32_t) | ||
200 | +DO_CLAMP(gvec_uclamp_d, uint64_t) | ||
184 | -- | 201 | -- |
185 | 2.25.1 | 202 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable writes to the TERR and TEA bits when RAS is enabled. | 3 | We can handle both exception entry and exception return by |
4 | These bits are otherwise RES0. | 4 | hooking into aarch64_sve_change_el. |
5 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-15-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-32-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/helper.c | 9 +++++++++ | 11 | target/arm/helper.c | 15 +++++++++++++-- |
12 | 1 file changed, 9 insertions(+) | 12 | 1 file changed, 13 insertions(+), 2 deletions(-) |
13 | 13 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 16 | --- a/target/arm/helper.c |
17 | +++ b/target/arm/helper.c | 17 | +++ b/target/arm/helper.c |
18 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 18 | @@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, |
19 | } | 19 | return; |
20 | valid_mask &= ~SCR_NET; | ||
21 | |||
22 | + if (cpu_isar_feature(aa64_ras, cpu)) { | ||
23 | + valid_mask |= SCR_TERR; | ||
24 | + } | ||
25 | if (cpu_isar_feature(aa64_lor, cpu)) { | ||
26 | valid_mask |= SCR_TLOR; | ||
27 | } | ||
28 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
29 | } | ||
30 | } else { | ||
31 | valid_mask &= ~(SCR_RW | SCR_ST); | ||
32 | + if (cpu_isar_feature(aa32_ras, cpu)) { | ||
33 | + valid_mask |= SCR_TERR; | ||
34 | + } | ||
35 | } | 20 | } |
36 | 21 | ||
37 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | 22 | + old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
38 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | 23 | + new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; |
39 | if (cpu_isar_feature(aa64_vh, cpu)) { | 24 | + |
40 | valid_mask |= HCR_E2H; | 25 | + /* |
41 | } | 26 | + * Both AArch64.TakeException and AArch64.ExceptionReturn |
42 | + if (cpu_isar_feature(aa64_ras, cpu)) { | 27 | + * invoke ResetSVEState when taking an exception from, or |
43 | + valid_mask |= HCR_TERR | HCR_TEA; | 28 | + * returning to, AArch32 state when PSTATE.SM is enabled. |
44 | + } | 29 | + */ |
45 | if (cpu_isar_feature(aa64_lor, cpu)) { | 30 | + if (old_a64 != new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { |
46 | valid_mask |= HCR_TLOR; | 31 | + arm_reset_sve_state(env); |
47 | } | 32 | + return; |
33 | + } | ||
34 | + | ||
35 | /* | ||
36 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | ||
37 | * at ELx, or not available because the EL is in AArch32 state, then | ||
38 | @@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, | ||
39 | * we already have the correct register contents when encountering the | ||
40 | * vq0->vq0 transition between EL0->EL1. | ||
41 | */ | ||
42 | - old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; | ||
43 | old_len = (old_a64 && !sve_exception_el(env, old_el) | ||
44 | ? sve_vqm1_for_el(env, old_el) : 0); | ||
45 | - new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; | ||
46 | new_len = (new_a64 && !sve_exception_el(env, new_el) | ||
47 | ? sve_vqm1_for_el(env, new_el) : 0); | ||
48 | |||
48 | -- | 49 | -- |
49 | 2.25.1 | 50 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns changes to the External Debug interface, | 3 | Note that SME remains effectively disabled for user-only, |
4 | with Secure and Non-secure access to the debug registers, and all | 4 | because we do not yet set CPACR_EL1.SMEN. This needs to |
5 | of it is outside the scope of QEMU. Indicating support for this | 5 | wait until the kernel ABI is implemented. |
6 | is mandatory with FEAT_SEL2, which we do implement. | ||
7 | 6 | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20220506180242.216785-13-richard.henderson@linaro.org | 9 | Message-id: 20220708151540.18136-33-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | docs/system/arm/emulation.rst | 1 + | 12 | docs/system/arm/emulation.rst | 4 ++++ |
14 | target/arm/cpu64.c | 2 +- | 13 | target/arm/cpu64.c | 11 +++++++++++ |
15 | target/arm/cpu_tcg.c | 4 ++-- | 14 | 2 files changed, 15 insertions(+) |
16 | 3 files changed, 4 insertions(+), 3 deletions(-) | ||
17 | 15 | ||
18 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
19 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/docs/system/arm/emulation.rst | 18 | --- a/docs/system/arm/emulation.rst |
21 | +++ b/docs/system/arm/emulation.rst | 19 | +++ b/docs/system/arm/emulation.rst |
22 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
23 | - FEAT_DIT (Data Independent Timing instructions) | 21 | - FEAT_SHA512 (Advanced SIMD SHA512 instructions) |
24 | - FEAT_DPB (DC CVAP instruction) | 22 | - FEAT_SM3 (Advanced SIMD SM3 instructions) |
25 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 23 | - FEAT_SM4 (Advanced SIMD SM4 instructions) |
26 | +- FEAT_Debugv8p4 (Debug changes for v8.4) | 24 | +- FEAT_SME (Scalable Matrix Extension) |
27 | - FEAT_DotProd (Advanced SIMD dot product instructions) | 25 | +- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) |
28 | - FEAT_FCMA (Floating-point complex number instructions) | 26 | +- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) |
29 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | 27 | +- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) |
28 | - FEAT_SPECRES (Speculation restriction instructions) | ||
29 | - FEAT_SSBS (Speculative Store Bypass Safe) | ||
30 | - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) | ||
30 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 31 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
31 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/target/arm/cpu64.c | 33 | --- a/target/arm/cpu64.c |
33 | +++ b/target/arm/cpu64.c | 34 | +++ b/target/arm/cpu64.c |
34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 35 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
35 | cpu->isar.id_aa64zfr0 = t; | 36 | */ |
36 | 37 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | |
37 | t = cpu->isar.id_aa64dfr0; | 38 | t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ |
38 | - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ | 39 | + t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ |
39 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ | 40 | t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ |
41 | cpu->isar.id_aa64pfr1 = t; | ||
42 | |||
43 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
40 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | 44 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ |
41 | cpu->isar.id_aa64dfr0 = t; | 45 | cpu->isar.id_aa64dfr0 = t; |
42 | 46 | ||
43 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 47 | + t = cpu->isar.id_aa64smfr0; |
44 | index XXXXXXX..XXXXXXX 100644 | 48 | + t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ |
45 | --- a/target/arm/cpu_tcg.c | 49 | + t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ |
46 | +++ b/target/arm/cpu_tcg.c | 50 | + t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ |
47 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 51 | + t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ |
48 | cpu->isar.id_pfr2 = t; | 52 | + t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ |
49 | 53 | + t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ | |
50 | t = cpu->isar.id_dfr0; | 54 | + t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ |
51 | - t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | 55 | + cpu->isar.id_aa64smfr0 = t; |
52 | - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | 56 | + |
53 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ | 57 | /* Replicate the same data to the 32-bit id registers. */ |
54 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ | 58 | aa32_max_features(cpu); |
55 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | 59 | |
56 | cpu->isar.id_dfr0 = t; | ||
57 | } | ||
58 | -- | 60 | -- |
59 | 2.25.1 | 61 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When the PPTT table is built, the CPU topology is re-calculated, but | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | it's unecessary because the CPU topology has been populated in | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | virt_possible_cpu_arch_ids() on arm/virt machine. | 5 | Message-id: 20220708151540.18136-34-richard.henderson@linaro.org |
6 | |||
7 | This reworks build_pptt() to avoid by reusing the existing IDs in | ||
8 | ms->possible_cpus. Currently, the only user of build_pptt() is | ||
9 | arm/virt machine. | ||
10 | |||
11 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
12 | Tested-by: Yanan Wang <wangyanan55@huawei.com> | ||
13 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
14 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
15 | Acked-by: Michael S. Tsirkin <mst@redhat.com> | ||
16 | Message-id: 20220503140304.855514-7-gshan@redhat.com | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | --- | 7 | --- |
19 | hw/acpi/aml-build.c | 111 +++++++++++++++++++------------------------- | 8 | linux-user/aarch64/target_cpu.h | 5 ++++- |
20 | 1 file changed, 48 insertions(+), 63 deletions(-) | 9 | 1 file changed, 4 insertions(+), 1 deletion(-) |
21 | 10 | ||
22 | diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c | 11 | diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h |
23 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/hw/acpi/aml-build.c | 13 | --- a/linux-user/aarch64/target_cpu.h |
25 | +++ b/hw/acpi/aml-build.c | 14 | +++ b/linux-user/aarch64/target_cpu.h |
26 | @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, | 15 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_clone_regs_parent(CPUARMState *env, unsigned flags) |
27 | const char *oem_id, const char *oem_table_id) | 16 | |
17 | static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) | ||
28 | { | 18 | { |
29 | MachineClass *mc = MACHINE_GET_CLASS(ms); | 19 | - /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is |
30 | - GQueue *list = g_queue_new(); | ||
31 | - guint pptt_start = table_data->len; | ||
32 | - guint parent_offset; | ||
33 | - guint length, i; | ||
34 | - int uid = 0; | ||
35 | - int socket; | ||
36 | + CPUArchIdList *cpus = ms->possible_cpus; | ||
37 | + int64_t socket_id = -1, cluster_id = -1, core_id = -1; | ||
38 | + uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0; | ||
39 | + uint32_t pptt_start = table_data->len; | ||
40 | + int n; | ||
41 | AcpiTable table = { .sig = "PPTT", .rev = 2, | ||
42 | .oem_id = oem_id, .oem_table_id = oem_table_id }; | ||
43 | |||
44 | acpi_table_begin(&table, table_data); | ||
45 | |||
46 | - for (socket = 0; socket < ms->smp.sockets; socket++) { | ||
47 | - g_queue_push_tail(list, | ||
48 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
49 | - build_processor_hierarchy_node( | ||
50 | - table_data, | ||
51 | - /* | ||
52 | - * Physical package - represents the boundary | ||
53 | - * of a physical package | ||
54 | - */ | ||
55 | - (1 << 0), | ||
56 | - 0, socket, NULL, 0); | ||
57 | - } | ||
58 | - | ||
59 | - if (mc->smp_props.clusters_supported) { | ||
60 | - length = g_queue_get_length(list); | ||
61 | - for (i = 0; i < length; i++) { | ||
62 | - int cluster; | ||
63 | - | ||
64 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
65 | - for (cluster = 0; cluster < ms->smp.clusters; cluster++) { | ||
66 | - g_queue_push_tail(list, | ||
67 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
68 | - build_processor_hierarchy_node( | ||
69 | - table_data, | ||
70 | - (0 << 0), /* not a physical package */ | ||
71 | - parent_offset, cluster, NULL, 0); | ||
72 | - } | ||
73 | + /* | 20 | + /* |
74 | + * This works with the assumption that cpus[n].props.*_id has been | 21 | + * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is |
75 | + * sorted from top to down levels in mc->possible_cpu_arch_ids(). | 22 | * different from AArch32 Linux, which uses TPIDRRO. |
76 | + * Otherwise, the unexpected and duplicated containers will be | 23 | */ |
77 | + * created. | 24 | env->cp15.tpidr_el[0] = newtls; |
78 | + */ | 25 | + /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */ |
79 | + for (n = 0; n < cpus->len; n++) { | 26 | + env->cp15.tpidr2_el0 = 0; |
80 | + if (cpus->cpus[n].props.socket_id != socket_id) { | ||
81 | + assert(cpus->cpus[n].props.socket_id > socket_id); | ||
82 | + socket_id = cpus->cpus[n].props.socket_id; | ||
83 | + cluster_id = -1; | ||
84 | + core_id = -1; | ||
85 | + socket_offset = table_data->len - pptt_start; | ||
86 | + build_processor_hierarchy_node(table_data, | ||
87 | + (1 << 0), /* Physical package */ | ||
88 | + 0, socket_id, NULL, 0); | ||
89 | } | ||
90 | - } | ||
91 | |||
92 | - length = g_queue_get_length(list); | ||
93 | - for (i = 0; i < length; i++) { | ||
94 | - int core; | ||
95 | - | ||
96 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
97 | - for (core = 0; core < ms->smp.cores; core++) { | ||
98 | - if (ms->smp.threads > 1) { | ||
99 | - g_queue_push_tail(list, | ||
100 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
101 | - build_processor_hierarchy_node( | ||
102 | - table_data, | ||
103 | - (0 << 0), /* not a physical package */ | ||
104 | - parent_offset, core, NULL, 0); | ||
105 | - } else { | ||
106 | - build_processor_hierarchy_node( | ||
107 | - table_data, | ||
108 | - (1 << 1) | /* ACPI Processor ID valid */ | ||
109 | - (1 << 3), /* Node is a Leaf */ | ||
110 | - parent_offset, uid++, NULL, 0); | ||
111 | + if (mc->smp_props.clusters_supported) { | ||
112 | + if (cpus->cpus[n].props.cluster_id != cluster_id) { | ||
113 | + assert(cpus->cpus[n].props.cluster_id > cluster_id); | ||
114 | + cluster_id = cpus->cpus[n].props.cluster_id; | ||
115 | + core_id = -1; | ||
116 | + cluster_offset = table_data->len - pptt_start; | ||
117 | + build_processor_hierarchy_node(table_data, | ||
118 | + (0 << 0), /* Not a physical package */ | ||
119 | + socket_offset, cluster_id, NULL, 0); | ||
120 | } | ||
121 | + } else { | ||
122 | + cluster_offset = socket_offset; | ||
123 | } | ||
124 | - } | ||
125 | |||
126 | - length = g_queue_get_length(list); | ||
127 | - for (i = 0; i < length; i++) { | ||
128 | - int thread; | ||
129 | + if (ms->smp.threads == 1) { | ||
130 | + build_processor_hierarchy_node(table_data, | ||
131 | + (1 << 1) | /* ACPI Processor ID valid */ | ||
132 | + (1 << 3), /* Node is a Leaf */ | ||
133 | + cluster_offset, n, NULL, 0); | ||
134 | + } else { | ||
135 | + if (cpus->cpus[n].props.core_id != core_id) { | ||
136 | + assert(cpus->cpus[n].props.core_id > core_id); | ||
137 | + core_id = cpus->cpus[n].props.core_id; | ||
138 | + core_offset = table_data->len - pptt_start; | ||
139 | + build_processor_hierarchy_node(table_data, | ||
140 | + (0 << 0), /* Not a physical package */ | ||
141 | + cluster_offset, core_id, NULL, 0); | ||
142 | + } | ||
143 | |||
144 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
145 | - for (thread = 0; thread < ms->smp.threads; thread++) { | ||
146 | - build_processor_hierarchy_node( | ||
147 | - table_data, | ||
148 | + build_processor_hierarchy_node(table_data, | ||
149 | (1 << 1) | /* ACPI Processor ID valid */ | ||
150 | (1 << 2) | /* Processor is a Thread */ | ||
151 | (1 << 3), /* Node is a Leaf */ | ||
152 | - parent_offset, uid++, NULL, 0); | ||
153 | + core_offset, n, NULL, 0); | ||
154 | } | ||
155 | } | ||
156 | |||
157 | - g_queue_free(list); | ||
158 | acpi_table_end(linker, &table); | ||
159 | } | 27 | } |
160 | 28 | ||
29 | static inline abi_ulong get_sp_from_cpustate(CPUARMState *state) | ||
161 | -- | 30 | -- |
162 | 2.25.1 | 31 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20220506180242.216785-18-richard.henderson@linaro.org | 5 | Message-id: 20220708151540.18136-35-richard.henderson@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | docs/system/arm/emulation.rst | 1 + | 8 | linux-user/aarch64/cpu_loop.c | 9 +++++++++ |
9 | target/arm/cpu64.c | 1 + | 9 | 1 file changed, 9 insertions(+) |
10 | target/arm/cpu_tcg.c | 1 + | ||
11 | 3 files changed, 3 insertions(+) | ||
12 | 10 | ||
13 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 11 | diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c |
14 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/docs/system/arm/emulation.rst | 13 | --- a/linux-user/aarch64/cpu_loop.c |
16 | +++ b/docs/system/arm/emulation.rst | 14 | +++ b/linux-user/aarch64/cpu_loop.c |
17 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 15 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) |
18 | - FEAT_PMULL (PMULL, PMULL2 instructions) | 16 | |
19 | - FEAT_PMUv3p1 (PMU Extensions v3.1) | 17 | switch (trapnr) { |
20 | - FEAT_PMUv3p4 (PMU Extensions v3.4) | 18 | case EXCP_SWI: |
21 | +- FEAT_RAS (Reliability, availability, and serviceability) | 19 | + /* |
22 | - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) | 20 | + * On syscall, PSTATE.ZA is preserved, along with the ZA matrix. |
23 | - FEAT_RNG (Random number generator) | 21 | + * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. |
24 | - FEAT_SB (Speculation Barrier) | 22 | + */ |
25 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 23 | + if (FIELD_EX64(env->svcr, SVCR, SM)) { |
26 | index XXXXXXX..XXXXXXX 100644 | 24 | + env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0); |
27 | --- a/target/arm/cpu64.c | 25 | + arm_rebuild_hflags(env); |
28 | +++ b/target/arm/cpu64.c | 26 | + arm_reset_sve_state(env); |
29 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 27 | + } |
30 | t = cpu->isar.id_aa64pfr0; | 28 | ret = do_syscall(env, |
31 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | 29 | env->xregs[8], |
32 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | 30 | env->xregs[0], |
33 | + t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ | ||
34 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
35 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
36 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
37 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/cpu_tcg.c | ||
40 | +++ b/target/arm/cpu_tcg.c | ||
41 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
42 | |||
43 | t = cpu->isar.id_pfr0; | ||
44 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
45 | + t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ | ||
46 | cpu->isar.id_pfr0 = t; | ||
47 | |||
48 | t = cpu->isar.id_pfr2; | ||
49 | -- | 31 | -- |
50 | 2.25.1 | 32 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This extension concerns branch speculation, which TCG does | 3 | Make sure to zero the currently reserved fields. |
4 | not implement. Thus we can trivially enable this feature. | ||
5 | 4 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-20-richard.henderson@linaro.org | 7 | Message-id: 20220708151540.18136-36-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 10 | linux-user/aarch64/signal.c | 9 ++++++++- |
12 | target/arm/cpu64.c | 1 + | 11 | 1 file changed, 8 insertions(+), 1 deletion(-) |
13 | target/arm/cpu_tcg.c | 1 + | ||
14 | 3 files changed, 3 insertions(+) | ||
15 | 12 | ||
16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 13 | diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c |
17 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/emulation.rst | 15 | --- a/linux-user/aarch64/signal.c |
19 | +++ b/docs/system/arm/emulation.rst | 16 | +++ b/linux-user/aarch64/signal.c |
20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 17 | @@ -XXX,XX +XXX,XX @@ struct target_extra_context { |
21 | - FEAT_BBM at level 2 (Translation table break-before-make levels) | 18 | struct target_sve_context { |
22 | - FEAT_BF16 (AArch64 BFloat16 instructions) | 19 | struct target_aarch64_ctx head; |
23 | - FEAT_BTI (Branch Target Identification) | 20 | uint16_t vl; |
24 | +- FEAT_CSV2 (Cache speculation variant 2) | 21 | - uint16_t reserved[3]; |
25 | - FEAT_DIT (Data Independent Timing instructions) | 22 | + uint16_t flags; |
26 | - FEAT_DPB (DC CVAP instruction) | 23 | + uint16_t reserved[2]; |
27 | - FEAT_Debugv8p2 (Debug changes for v8.2) | 24 | /* The actual SVE data immediately follows. It is laid out |
28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 25 | * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of |
29 | index XXXXXXX..XXXXXXX 100644 | 26 | * the original struct pointer. |
30 | --- a/target/arm/cpu64.c | 27 | @@ -XXX,XX +XXX,XX @@ struct target_sve_context { |
31 | +++ b/target/arm/cpu64.c | 28 | #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ |
32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 29 | (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) |
33 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | 30 | |
34 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | 31 | +#define TARGET_SVE_SIG_FLAG_SM 1 |
35 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | 32 | + |
36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ | 33 | struct target_rt_sigframe { |
37 | cpu->isar.id_aa64pfr0 = t; | 34 | struct target_siginfo info; |
38 | 35 | struct target_ucontext uc; | |
39 | t = cpu->isar.id_aa64pfr1; | 36 | @@ -XXX,XX +XXX,XX @@ static void target_setup_sve_record(struct target_sve_context *sve, |
40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 37 | { |
41 | index XXXXXXX..XXXXXXX 100644 | 38 | int i, j; |
42 | --- a/target/arm/cpu_tcg.c | 39 | |
43 | +++ b/target/arm/cpu_tcg.c | 40 | + memset(sve, 0, sizeof(*sve)); |
44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | 41 | __put_user(TARGET_SVE_MAGIC, &sve->head.magic); |
45 | cpu->isar.id_mmfr4 = t; | 42 | __put_user(size, &sve->head.size); |
46 | 43 | __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); | |
47 | t = cpu->isar.id_pfr0; | 44 | + if (FIELD_EX64(env->svcr, SVCR, SM)) { |
48 | + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ | 45 | + __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags); |
49 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | 46 | + } |
50 | t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ | 47 | |
51 | cpu->isar.id_pfr0 = t; | 48 | /* Note that SVE regs are stored as a byte stream, with each byte element |
49 | * at a subsequent address. This corresponds to a little-endian store | ||
52 | -- | 50 | -- |
53 | 2.25.1 | 51 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Update the legacy feature names to the current names. | 3 | Fold the return value setting into the goto, so each |
4 | Provide feature names for id changes that were not marked. | 4 | point of failure need not do both. |
5 | Sort the field updates into increasing bitfield order. | ||
6 | 5 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-10-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-37-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/cpu64.c | 100 +++++++++++++++++++++---------------------- | 11 | linux-user/aarch64/signal.c | 26 +++++++++++--------------- |
13 | target/arm/cpu_tcg.c | 48 ++++++++++----------- | 12 | 1 file changed, 11 insertions(+), 15 deletions(-) |
14 | 2 files changed, 74 insertions(+), 74 deletions(-) | ||
15 | 13 | ||
16 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 14 | diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu64.c | 16 | --- a/linux-user/aarch64/signal.c |
19 | +++ b/target/arm/cpu64.c | 17 | +++ b/linux-user/aarch64/signal.c |
20 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 18 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
21 | cpu->midr = t; | 19 | struct target_sve_context *sve = NULL; |
22 | 20 | uint64_t extra_datap = 0; | |
23 | t = cpu->isar.id_aa64isar0; | 21 | bool used_extra = false; |
24 | - t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ | 22 | - bool err = false; |
25 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); | 23 | int vq = 0, sve_size = 0; |
26 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ | 24 | |
27 | + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ | 25 | target_restore_general_frame(env, sf); |
28 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ | 26 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
29 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ | 27 | switch (magic) { |
30 | t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | 28 | case 0: |
31 | - t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); | 29 | if (size != 0) { |
32 | - t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); | 30 | - err = true; |
33 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); | 31 | - goto exit; |
34 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); | 32 | + goto err; |
35 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); | 33 | } |
36 | - t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); | 34 | if (used_extra) { |
37 | - t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); | 35 | ctx = NULL; |
38 | - t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ | 36 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
39 | - t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | 37 | |
40 | - t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); | 38 | case TARGET_FPSIMD_MAGIC: |
41 | + t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ | 39 | if (fpsimd || size != sizeof(struct target_fpsimd_context)) { |
42 | + t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | 40 | - err = true; |
43 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | 41 | - goto exit; |
44 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ | 42 | + goto err; |
45 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ | 43 | } |
46 | + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ | 44 | fpsimd = (struct target_fpsimd_context *)ctx; |
47 | + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ | 45 | break; |
48 | + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ | 46 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
49 | + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | 47 | break; |
50 | + t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ | 48 | } |
51 | cpu->isar.id_aa64isar0 = t; | 49 | } |
52 | 50 | - err = true; | |
53 | t = cpu->isar.id_aa64isar1; | 51 | - goto exit; |
54 | - t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); | 52 | + goto err; |
55 | - t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); | 53 | |
56 | - t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); | 54 | case TARGET_EXTRA_MAGIC: |
57 | - t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | 55 | if (extra || size != sizeof(struct target_extra_context)) { |
58 | - t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | 56 | - err = true; |
59 | - t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); | 57 | - goto exit; |
60 | - t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); | 58 | + goto err; |
61 | - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ | 59 | } |
62 | - t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); | 60 | __get_user(extra_datap, |
63 | + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ | 61 | &((struct target_extra_context *)ctx)->datap); |
64 | + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ | 62 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
65 | + t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ | 63 | /* Unknown record -- we certainly didn't generate it. |
66 | + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ | 64 | * Did we in fact get out of sync? |
67 | + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ | 65 | */ |
68 | + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | 66 | - err = true; |
69 | + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | 67 | - goto exit; |
70 | + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | 68 | + goto err; |
71 | + t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | 69 | } |
72 | cpu->isar.id_aa64isar1 = t; | 70 | ctx = (void *)ctx + size; |
73 | 71 | } | |
74 | t = cpu->isar.id_aa64pfr0; | 72 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
75 | + t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | 73 | if (fpsimd) { |
76 | + t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | 74 | target_restore_fpsimd_record(env, fpsimd); |
77 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | 75 | } else { |
78 | - t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); | 76 | - err = true; |
79 | - t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); | 77 | + goto err; |
80 | - t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); | 78 | } |
81 | - t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); | 79 | |
82 | + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | 80 | /* SVE data, if present, overwrites FPSIMD data. */ |
83 | + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | 81 | if (sve) { |
84 | cpu->isar.id_aa64pfr0 = t; | 82 | target_restore_sve_record(env, sve, vq); |
85 | 83 | } | |
86 | t = cpu->isar.id_aa64pfr1; | 84 | - |
87 | - t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | 85 | - exit: |
88 | - t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); | 86 | unlock_user(extra, extra_datap, 0); |
89 | + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ | 87 | - return err; |
90 | + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ | 88 | + return 0; |
91 | /* | 89 | + |
92 | * Begin with full support for MTE. This will be downgraded to MTE=0 | 90 | + err: |
93 | * during realize if the board provides no tag memory, much like | 91 | + unlock_user(extra, extra_datap, 0); |
94 | * we do for EL2 with the virtualization=on property. | 92 | + return 1; |
95 | */ | ||
96 | - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); | ||
97 | + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
98 | cpu->isar.id_aa64pfr1 = t; | ||
99 | |||
100 | t = cpu->isar.id_aa64mmfr0; | ||
101 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
102 | cpu->isar.id_aa64mmfr0 = t; | ||
103 | |||
104 | t = cpu->isar.id_aa64mmfr1; | ||
105 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | ||
106 | - t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); | ||
107 | - t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); | ||
108 | - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ | ||
109 | - t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ | ||
110 | - t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ | ||
111 | + t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | ||
112 | + t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | ||
113 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | ||
114 | + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | ||
115 | + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ | ||
116 | + t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | ||
117 | cpu->isar.id_aa64mmfr1 = t; | ||
118 | |||
119 | t = cpu->isar.id_aa64mmfr2; | ||
120 | - t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | ||
121 | - t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | ||
122 | - t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | ||
123 | - t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
124 | - t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
125 | - t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
126 | + t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | ||
127 | + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | ||
128 | + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
129 | + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | ||
130 | + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
131 | + t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
132 | cpu->isar.id_aa64mmfr2 = t; | ||
133 | |||
134 | t = cpu->isar.id_aa64zfr0; | ||
135 | t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); | ||
136 | - t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ | ||
137 | - t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); | ||
138 | - t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); | ||
139 | - t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); | ||
140 | - t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); | ||
141 | - t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); | ||
142 | - t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); | ||
143 | - t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
144 | + t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ | ||
145 | + t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ | ||
146 | + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ | ||
147 | + t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ | ||
148 | + t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ | ||
149 | + t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ | ||
150 | + t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ | ||
151 | + t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ | ||
152 | cpu->isar.id_aa64zfr0 = t; | ||
153 | |||
154 | t = cpu->isar.id_aa64dfr0; | ||
155 | - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
156 | + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | ||
157 | cpu->isar.id_aa64dfr0 = t; | ||
158 | |||
159 | /* Replicate the same data to the 32-bit id registers. */ | ||
160 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
161 | index XXXXXXX..XXXXXXX 100644 | ||
162 | --- a/target/arm/cpu_tcg.c | ||
163 | +++ b/target/arm/cpu_tcg.c | ||
164 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
165 | |||
166 | /* Add additional features supported by QEMU */ | ||
167 | t = cpu->isar.id_isar5; | ||
168 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
169 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
170 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
171 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ | ||
172 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ | ||
173 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ | ||
174 | t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
175 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
176 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
177 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ | ||
178 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ | ||
179 | cpu->isar.id_isar5 = t; | ||
180 | |||
181 | t = cpu->isar.id_isar6; | ||
182 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
183 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
184 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
185 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
186 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
187 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
188 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
189 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ | ||
190 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ | ||
191 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ | ||
192 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ | ||
193 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ | ||
194 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ | ||
195 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ | ||
196 | cpu->isar.id_isar6 = t; | ||
197 | |||
198 | t = cpu->isar.mvfr1; | ||
199 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
200 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
201 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ | ||
202 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ | ||
203 | cpu->isar.mvfr1 = t; | ||
204 | |||
205 | t = cpu->isar.mvfr2; | ||
206 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
207 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
208 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
209 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
210 | cpu->isar.mvfr2 = t; | ||
211 | |||
212 | t = cpu->isar.id_mmfr3; | ||
213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
214 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ | ||
215 | cpu->isar.id_mmfr3 = t; | ||
216 | |||
217 | t = cpu->isar.id_mmfr4; | ||
218 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
219 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
220 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
221 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
222 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ | ||
223 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
224 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ | ||
225 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ | ||
226 | cpu->isar.id_mmfr4 = t; | ||
227 | |||
228 | t = cpu->isar.id_pfr0; | ||
229 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
230 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ | ||
231 | cpu->isar.id_pfr0 = t; | ||
232 | |||
233 | t = cpu->isar.id_pfr2; | ||
234 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
235 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | ||
236 | cpu->isar.id_pfr2 = t; | ||
237 | |||
238 | t = cpu->isar.id_dfr0; | ||
239 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
240 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
241 | cpu->isar.id_dfr0 = t; | ||
242 | } | 93 | } |
243 | 94 | ||
95 | static abi_ulong get_sigframe(struct target_sigaction *ka, | ||
244 | -- | 96 | -- |
245 | 2.25.1 | 97 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This feature is AArch64 only, and applies to physical SErrors, | 3 | In parse_user_sigframe, the kernel rejects duplicate sve records, |
4 | which QEMU does not implement, thus the feature is a nop. | 4 | or records that are smaller than the header. We were silently |
5 | allowing these cases to pass, dropping the record. | ||
5 | 6 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-19-richard.henderson@linaro.org | 9 | Message-id: 20220708151540.18136-38-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | docs/system/arm/emulation.rst | 1 + | 12 | linux-user/aarch64/signal.c | 5 ++++- |
12 | target/arm/cpu64.c | 1 + | 13 | 1 file changed, 4 insertions(+), 1 deletion(-) |
13 | 2 files changed, 2 insertions(+) | ||
14 | 14 | ||
15 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | 15 | diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/docs/system/arm/emulation.rst | 17 | --- a/linux-user/aarch64/signal.c |
18 | +++ b/docs/system/arm/emulation.rst | 18 | +++ b/linux-user/aarch64/signal.c |
19 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | 19 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
20 | - FEAT_FlagM2 (Enhancements to flag manipulation instructions) | 20 | break; |
21 | - FEAT_HPDS (Hierarchical permission disables) | 21 | |
22 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) | 22 | case TARGET_SVE_MAGIC: |
23 | +- FEAT_IESB (Implicit error synchronization event) | 23 | + if (sve || size < sizeof(struct target_sve_context)) { |
24 | - FEAT_JSCVT (JavaScript conversion instructions) | 24 | + goto err; |
25 | - FEAT_LOR (Limited ordering regions) | 25 | + } |
26 | - FEAT_LPA (Large Physical Address space) | 26 | if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { |
27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 27 | vq = sve_vq(env); |
28 | index XXXXXXX..XXXXXXX 100644 | 28 | sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); |
29 | --- a/target/arm/cpu64.c | 29 | - if (!sve && size == sve_size) { |
30 | +++ b/target/arm/cpu64.c | 30 | + if (size == sve_size) { |
31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 31 | sve = (struct target_sve_context *)ctx; |
32 | t = cpu->isar.id_aa64mmfr2; | 32 | break; |
33 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | 33 | } |
34 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | ||
35 | + t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ | ||
36 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
37 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | ||
38 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
39 | -- | 34 | -- |
40 | 2.25.1 | 35 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <quic_llindhol@quicinc.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | NUVIA was acquired by Qualcomm in March 2021, but kept functioning on | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | separate infrastructure for a transitional period. We've now switched | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | over to contributing as Qualcomm Innovation Center (quicinc), so update | 5 | Message-id: 20220708151540.18136-39-richard.henderson@linaro.org |
6 | my email address to reflect this. | ||
7 | |||
8 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
9 | Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com | ||
10 | Cc: Leif Lindholm <leif@nuviainc.com> | ||
11 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | [Fixed commit message typo] | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 7 | --- |
16 | .mailmap | 3 ++- | 8 | linux-user/aarch64/signal.c | 3 +++ |
17 | MAINTAINERS | 2 +- | 9 | 1 file changed, 3 insertions(+) |
18 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
19 | 10 | ||
20 | diff --git a/.mailmap b/.mailmap | 11 | diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c |
21 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/.mailmap | 13 | --- a/linux-user/aarch64/signal.c |
23 | +++ b/.mailmap | 14 | +++ b/linux-user/aarch64/signal.c |
24 | @@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com> | 15 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
25 | Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> | 16 | __get_user(extra_size, |
26 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> | 17 | &((struct target_extra_context *)ctx)->size); |
27 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> | 18 | extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0); |
28 | -Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org> | 19 | + if (!extra) { |
29 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> | 20 | + return 1; |
30 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> | 21 | + } |
31 | Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org> | 22 | break; |
32 | Paul Burton <paulburton@kernel.org> <paul.burton@mips.com> | 23 | |
33 | Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com> | 24 | default: |
34 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/MAINTAINERS | ||
37 | +++ b/MAINTAINERS | ||
38 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h | ||
39 | SBSA-REF | ||
40 | M: Radoslaw Biernacki <rad@semihalf.com> | ||
41 | M: Peter Maydell <peter.maydell@linaro.org> | ||
42 | -R: Leif Lindholm <leif@nuviainc.com> | ||
43 | +R: Leif Lindholm <quic_llindhol@quicinc.com> | ||
44 | L: qemu-arm@nongnu.org | ||
45 | S: Maintained | ||
46 | F: hw/arm/sbsa-ref.c | ||
47 | -- | 25 | -- |
48 | 2.25.1 | 26 | 2.25.1 |
49 | |||
50 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Drop zcr_no_el2_reginfo and merge the 3 registers into one array, | 3 | Move the checks out of the parsing loop and into the |
4 | now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped | 4 | restore function. This more closely mirrors the code |
5 | while registering. | 5 | structure in the kernel, and is slightly clearer. |
6 | |||
7 | Reject rather than silently skip incorrect VL and SVE record sizes, | ||
8 | bringing our checks in to line with those the kernel does. | ||
6 | 9 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-4-richard.henderson@linaro.org | 12 | Message-id: 20220708151540.18136-40-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 14 | --- |
12 | target/arm/helper.c | 55 ++++++++++++++------------------------------- | 15 | linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------ |
13 | 1 file changed, 17 insertions(+), 38 deletions(-) | 16 | 1 file changed, 35 insertions(+), 16 deletions(-) |
14 | 17 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 18 | diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c |
16 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 20 | --- a/linux-user/aarch64/signal.c |
18 | +++ b/target/arm/helper.c | 21 | +++ b/linux-user/aarch64/signal.c |
19 | @@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 22 | @@ -XXX,XX +XXX,XX @@ static void target_restore_fpsimd_record(CPUARMState *env, |
20 | } | 23 | } |
21 | } | 24 | } |
22 | 25 | ||
23 | -static const ARMCPRegInfo zcr_el1_reginfo = { | 26 | -static void target_restore_sve_record(CPUARMState *env, |
24 | - .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | 27 | - struct target_sve_context *sve, int vq) |
25 | - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | 28 | +static bool target_restore_sve_record(CPUARMState *env, |
26 | - .access = PL1_RW, .type = ARM_CP_SVE, | 29 | + struct target_sve_context *sve, |
27 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | 30 | + int size) |
28 | - .writefn = zcr_write, .raw_writefn = raw_write | 31 | { |
29 | -}; | 32 | - int i, j; |
30 | - | 33 | + int i, j, vl, vq; |
31 | -static const ARMCPRegInfo zcr_el2_reginfo = { | 34 | |
32 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | 35 | - /* Note that SVE regs are stored as a byte stream, with each byte element |
33 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | 36 | + if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { |
34 | - .access = PL2_RW, .type = ARM_CP_SVE, | 37 | + return false; |
35 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | 38 | + } |
36 | - .writefn = zcr_write, .raw_writefn = raw_write | 39 | + |
37 | -}; | 40 | + __get_user(vl, &sve->vl); |
38 | - | 41 | + vq = sve_vq(env); |
39 | -static const ARMCPRegInfo zcr_no_el2_reginfo = { | 42 | + |
40 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | 43 | + /* Reject mismatched VL. */ |
41 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | 44 | + if (vl != vq * TARGET_SVE_VQ_BYTES) { |
42 | - .access = PL2_RW, .type = ARM_CP_SVE, | 45 | + return false; |
43 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore | 46 | + } |
44 | -}; | 47 | + |
45 | - | 48 | + /* Accept empty record -- used to clear PSTATE.SM. */ |
46 | -static const ARMCPRegInfo zcr_el3_reginfo = { | 49 | + if (size <= sizeof(*sve)) { |
47 | - .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | 50 | + return true; |
48 | - .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | 51 | + } |
49 | - .access = PL3_RW, .type = ARM_CP_SVE, | 52 | + |
50 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | 53 | + /* Reject non-empty but incomplete record. */ |
51 | - .writefn = zcr_write, .raw_writefn = raw_write | 54 | + if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) { |
52 | +static const ARMCPRegInfo zcr_reginfo[] = { | 55 | + return false; |
53 | + { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | 56 | + } |
54 | + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | 57 | + |
55 | + .access = PL1_RW, .type = ARM_CP_SVE, | 58 | + /* |
56 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | 59 | + * Note that SVE regs are stored as a byte stream, with each byte element |
57 | + .writefn = zcr_write, .raw_writefn = raw_write }, | 60 | * at a subsequent address. This corresponds to a little-endian load |
58 | + { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | 61 | * of our 64-bit hunks. |
59 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | 62 | */ |
60 | + .access = PL2_RW, .type = ARM_CP_SVE, | 63 | @@ -XXX,XX +XXX,XX @@ static void target_restore_sve_record(CPUARMState *env, |
61 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | 64 | } |
62 | + .writefn = zcr_write, .raw_writefn = raw_write }, | 65 | } |
63 | + { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
64 | + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
65 | + .access = PL3_RW, .type = ARM_CP_SVE, | ||
66 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
67 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
68 | }; | ||
69 | |||
70 | void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
71 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
72 | } | 66 | } |
73 | 67 | + return true; | |
74 | if (cpu_isar_feature(aa64_sve, cpu)) { | 68 | } |
75 | - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); | 69 | |
76 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | 70 | static int target_restore_sigframe(CPUARMState *env, |
77 | - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | 71 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
78 | - } else { | 72 | struct target_sve_context *sve = NULL; |
79 | - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | 73 | uint64_t extra_datap = 0; |
80 | - } | 74 | bool used_extra = false; |
81 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | 75 | - int vq = 0, sve_size = 0; |
82 | - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | 76 | + int sve_size = 0; |
83 | - } | 77 | |
84 | + define_arm_cp_regs(cpu, zcr_reginfo); | 78 | target_restore_general_frame(env, sf); |
79 | |||
80 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, | ||
81 | if (sve || size < sizeof(struct target_sve_context)) { | ||
82 | goto err; | ||
83 | } | ||
84 | - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | ||
85 | - vq = sve_vq(env); | ||
86 | - sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); | ||
87 | - if (size == sve_size) { | ||
88 | - sve = (struct target_sve_context *)ctx; | ||
89 | - break; | ||
90 | - } | ||
91 | - } | ||
92 | - goto err; | ||
93 | + sve = (struct target_sve_context *)ctx; | ||
94 | + sve_size = size; | ||
95 | + break; | ||
96 | |||
97 | case TARGET_EXTRA_MAGIC: | ||
98 | if (extra || size != sizeof(struct target_extra_context)) { | ||
99 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, | ||
85 | } | 100 | } |
86 | 101 | ||
87 | #ifdef TARGET_AARCH64 | 102 | /* SVE data, if present, overwrites FPSIMD data. */ |
103 | - if (sve) { | ||
104 | - target_restore_sve_record(env, sve, vq); | ||
105 | + if (sve && !target_restore_sve_record(env, sve, sve_size)) { | ||
106 | + goto err; | ||
107 | } | ||
108 | unlock_user(extra, extra_datap, 0); | ||
109 | return 0; | ||
88 | -- | 110 | -- |
89 | 2.25.1 | 111 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Previously we were defining some of these in user-only mode, | 3 | Set the SM bit in the SVE record on signal delivery, create the ZA record. |
4 | but none of them are accessible from user-only, therefore | 4 | Restore SM and ZA state according to the records present on return. |
5 | define them only in system mode. | ||
6 | |||
7 | This will shortly be used from cpu_tcg.c also. | ||
8 | 5 | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20220506180242.216785-6-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-41-richard.henderson@linaro.org |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | target/arm/internals.h | 6 ++++ | 11 | linux-user/aarch64/signal.c | 167 +++++++++++++++++++++++++++++++++--- |
15 | target/arm/cpu64.c | 64 +++--------------------------------------- | 12 | 1 file changed, 154 insertions(+), 13 deletions(-) |
16 | target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ | ||
17 | 3 files changed, 69 insertions(+), 60 deletions(-) | ||
18 | 13 | ||
19 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 14 | diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c |
20 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/internals.h | 16 | --- a/linux-user/aarch64/signal.c |
22 | +++ b/target/arm/internals.h | 17 | +++ b/linux-user/aarch64/signal.c |
23 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); | 18 | @@ -XXX,XX +XXX,XX @@ struct target_sve_context { |
24 | int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); | 19 | |
25 | #endif | 20 | #define TARGET_SVE_SIG_FLAG_SM 1 |
26 | 21 | ||
27 | +#ifdef CONFIG_USER_ONLY | 22 | +#define TARGET_ZA_MAGIC 0x54366345 |
28 | +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | 23 | + |
29 | +#else | 24 | +struct target_za_context { |
30 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | 25 | + struct target_aarch64_ctx head; |
31 | +#endif | 26 | + uint16_t vl; |
32 | + | 27 | + uint16_t reserved[3]; |
33 | #endif | 28 | + /* The actual ZA data immediately follows. */ |
34 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 29 | +}; |
35 | index XXXXXXX..XXXXXXX 100644 | 30 | + |
36 | --- a/target/arm/cpu64.c | 31 | +#define TARGET_ZA_SIG_REGS_OFFSET \ |
37 | +++ b/target/arm/cpu64.c | 32 | + QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES) |
38 | @@ -XXX,XX +XXX,XX @@ | 33 | +#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \ |
39 | #include "hvf_arm.h" | 34 | + (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N)) |
40 | #include "qapi/visitor.h" | 35 | +#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ |
41 | #include "hw/qdev-properties.h" | 36 | + TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) |
42 | -#include "cpregs.h" | 37 | + |
43 | +#include "internals.h" | 38 | struct target_rt_sigframe { |
44 | 39 | struct target_siginfo info; | |
45 | 40 | struct target_ucontext uc; | |
46 | -#ifndef CONFIG_USER_ONLY | 41 | @@ -XXX,XX +XXX,XX @@ static void target_setup_end_record(struct target_aarch64_ctx *end) |
47 | -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
48 | -{ | ||
49 | - ARMCPU *cpu = env_archcpu(env); | ||
50 | - | ||
51 | - /* Number of cores is in [25:24]; otherwise we RAZ */ | ||
52 | - return (cpu->core_count - 1) << 24; | ||
53 | -} | ||
54 | -#endif | ||
55 | - | ||
56 | -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
57 | -#ifndef CONFIG_USER_ONLY | ||
58 | - { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
59 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | ||
60 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | ||
61 | - .writefn = arm_cp_write_ignore }, | ||
62 | - { .name = "L2CTLR", | ||
63 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | ||
64 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | ||
65 | - .writefn = arm_cp_write_ignore }, | ||
66 | -#endif | ||
67 | - { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
68 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | ||
69 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
70 | - { .name = "L2ECTLR", | ||
71 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | ||
72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
73 | - { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | ||
74 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | ||
75 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
76 | - { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
77 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | ||
78 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | - { .name = "CPUACTLR", | ||
80 | - .cp = 15, .opc1 = 0, .crm = 15, | ||
81 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
82 | - { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
83 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | ||
84 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
85 | - { .name = "CPUECTLR", | ||
86 | - .cp = 15, .opc1 = 1, .crm = 15, | ||
87 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
88 | - { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
89 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | ||
90 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
91 | - { .name = "CPUMERRSR", | ||
92 | - .cp = 15, .opc1 = 2, .crm = 15, | ||
93 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
94 | - { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
95 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | ||
96 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
97 | - { .name = "L2MERRSR", | ||
98 | - .cp = 15, .opc1 = 3, .crm = 15, | ||
99 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
100 | -}; | ||
101 | - | ||
102 | static void aarch64_a57_initfn(Object *obj) | ||
103 | { | ||
104 | ARMCPU *cpu = ARM_CPU(obj); | ||
105 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | ||
106 | cpu->gic_num_lrs = 4; | ||
107 | cpu->gic_vpribits = 5; | ||
108 | cpu->gic_vprebits = 5; | ||
109 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
110 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
111 | } | 42 | } |
112 | 43 | ||
113 | static void aarch64_a53_initfn(Object *obj) | 44 | static void target_setup_sve_record(struct target_sve_context *sve, |
114 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | 45 | - CPUARMState *env, int vq, int size) |
115 | cpu->gic_num_lrs = 4; | 46 | + CPUARMState *env, int size) |
116 | cpu->gic_vpribits = 5; | 47 | { |
117 | cpu->gic_vprebits = 5; | 48 | - int i, j; |
118 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 49 | + int i, j, vq = sve_vq(env); |
119 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | 50 | |
51 | memset(sve, 0, sizeof(*sve)); | ||
52 | __put_user(TARGET_SVE_MAGIC, &sve->head.magic); | ||
53 | @@ -XXX,XX +XXX,XX @@ static void target_setup_sve_record(struct target_sve_context *sve, | ||
54 | } | ||
120 | } | 55 | } |
121 | 56 | ||
122 | static void aarch64_a72_initfn(Object *obj) | 57 | +static void target_setup_za_record(struct target_za_context *za, |
123 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | 58 | + CPUARMState *env, int size) |
124 | cpu->gic_num_lrs = 4; | 59 | +{ |
125 | cpu->gic_vpribits = 5; | 60 | + int vq = sme_vq(env); |
126 | cpu->gic_vprebits = 5; | 61 | + int vl = vq * TARGET_SVE_VQ_BYTES; |
127 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 62 | + int i, j; |
128 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | 63 | + |
64 | + memset(za, 0, sizeof(*za)); | ||
65 | + __put_user(TARGET_ZA_MAGIC, &za->head.magic); | ||
66 | + __put_user(size, &za->head.size); | ||
67 | + __put_user(vl, &za->vl); | ||
68 | + | ||
69 | + if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) { | ||
70 | + return; | ||
71 | + } | ||
72 | + assert(size == TARGET_ZA_SIG_CONTEXT_SIZE(vq)); | ||
73 | + | ||
74 | + /* | ||
75 | + * Note that ZA vectors are stored as a byte stream, | ||
76 | + * with each byte element at a subsequent address. | ||
77 | + */ | ||
78 | + for (i = 0; i < vl; ++i) { | ||
79 | + uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); | ||
80 | + for (j = 0; j < vq * 2; ++j) { | ||
81 | + __put_user_e(env->zarray[i].d[j], z + j, le); | ||
82 | + } | ||
83 | + } | ||
84 | +} | ||
85 | + | ||
86 | static void target_restore_general_frame(CPUARMState *env, | ||
87 | struct target_rt_sigframe *sf) | ||
88 | { | ||
89 | @@ -XXX,XX +XXX,XX @@ static void target_restore_fpsimd_record(CPUARMState *env, | ||
90 | |||
91 | static bool target_restore_sve_record(CPUARMState *env, | ||
92 | struct target_sve_context *sve, | ||
93 | - int size) | ||
94 | + int size, int *svcr) | ||
95 | { | ||
96 | - int i, j, vl, vq; | ||
97 | + int i, j, vl, vq, flags; | ||
98 | + bool sm; | ||
99 | |||
100 | - if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { | ||
101 | + __get_user(vl, &sve->vl); | ||
102 | + __get_user(flags, &sve->flags); | ||
103 | + | ||
104 | + sm = flags & TARGET_SVE_SIG_FLAG_SM; | ||
105 | + | ||
106 | + /* The cpu must support Streaming or Non-streaming SVE. */ | ||
107 | + if (sm | ||
108 | + ? !cpu_isar_feature(aa64_sme, env_archcpu(env)) | ||
109 | + : !cpu_isar_feature(aa64_sve, env_archcpu(env))) { | ||
110 | return false; | ||
111 | } | ||
112 | |||
113 | - __get_user(vl, &sve->vl); | ||
114 | - vq = sve_vq(env); | ||
115 | + /* | ||
116 | + * Note that we cannot use sve_vq() because that depends on the | ||
117 | + * current setting of PSTATE.SM, not the state to be restored. | ||
118 | + */ | ||
119 | + vq = sve_vqm1_for_el_sm(env, 0, sm) + 1; | ||
120 | |||
121 | /* Reject mismatched VL. */ | ||
122 | if (vl != vq * TARGET_SVE_VQ_BYTES) { | ||
123 | @@ -XXX,XX +XXX,XX @@ static bool target_restore_sve_record(CPUARMState *env, | ||
124 | return false; | ||
125 | } | ||
126 | |||
127 | + *svcr = FIELD_DP64(*svcr, SVCR, SM, sm); | ||
128 | + | ||
129 | /* | ||
130 | * Note that SVE regs are stored as a byte stream, with each byte element | ||
131 | * at a subsequent address. This corresponds to a little-endian load | ||
132 | @@ -XXX,XX +XXX,XX @@ static bool target_restore_sve_record(CPUARMState *env, | ||
133 | return true; | ||
129 | } | 134 | } |
130 | 135 | ||
131 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | 136 | +static bool target_restore_za_record(CPUARMState *env, |
132 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | 137 | + struct target_za_context *za, |
133 | index XXXXXXX..XXXXXXX 100644 | 138 | + int size, int *svcr) |
134 | --- a/target/arm/cpu_tcg.c | ||
135 | +++ b/target/arm/cpu_tcg.c | ||
136 | @@ -XXX,XX +XXX,XX @@ | ||
137 | #endif | ||
138 | #include "cpregs.h" | ||
139 | |||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
142 | +{ | 139 | +{ |
143 | + ARMCPU *cpu = env_archcpu(env); | 140 | + int i, j, vl, vq; |
144 | + | 141 | + |
145 | + /* Number of cores is in [25:24]; otherwise we RAZ */ | 142 | + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { |
146 | + return (cpu->core_count - 1) << 24; | 143 | + return false; |
144 | + } | ||
145 | + | ||
146 | + __get_user(vl, &za->vl); | ||
147 | + vq = sme_vq(env); | ||
148 | + | ||
149 | + /* Reject mismatched VL. */ | ||
150 | + if (vl != vq * TARGET_SVE_VQ_BYTES) { | ||
151 | + return false; | ||
152 | + } | ||
153 | + | ||
154 | + /* Accept empty record -- used to clear PSTATE.ZA. */ | ||
155 | + if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) { | ||
156 | + return true; | ||
157 | + } | ||
158 | + | ||
159 | + /* Reject non-empty but incomplete record. */ | ||
160 | + if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) { | ||
161 | + return false; | ||
162 | + } | ||
163 | + | ||
164 | + *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1); | ||
165 | + | ||
166 | + for (i = 0; i < vl; ++i) { | ||
167 | + uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); | ||
168 | + for (j = 0; j < vq * 2; ++j) { | ||
169 | + __get_user_e(env->zarray[i].d[j], z + j, le); | ||
170 | + } | ||
171 | + } | ||
172 | + return true; | ||
147 | +} | 173 | +} |
148 | + | 174 | + |
149 | +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | 175 | static int target_restore_sigframe(CPUARMState *env, |
150 | + { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | 176 | struct target_rt_sigframe *sf) |
151 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | 177 | { |
152 | + .access = PL1_RW, .readfn = l2ctlr_read, | 178 | struct target_aarch64_ctx *ctx, *extra = NULL; |
153 | + .writefn = arm_cp_write_ignore }, | 179 | struct target_fpsimd_context *fpsimd = NULL; |
154 | + { .name = "L2CTLR", | 180 | struct target_sve_context *sve = NULL; |
155 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | 181 | + struct target_za_context *za = NULL; |
156 | + .access = PL1_RW, .readfn = l2ctlr_read, | 182 | uint64_t extra_datap = 0; |
157 | + .writefn = arm_cp_write_ignore }, | 183 | bool used_extra = false; |
158 | + { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | 184 | int sve_size = 0; |
159 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | 185 | + int za_size = 0; |
160 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 186 | + int svcr = 0; |
161 | + { .name = "L2ECTLR", | 187 | |
162 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | 188 | target_restore_general_frame(env, sf); |
163 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 189 | |
164 | + { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | 190 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
165 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | 191 | sve_size = size; |
166 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 192 | break; |
167 | + { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | 193 | |
168 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | 194 | + case TARGET_ZA_MAGIC: |
169 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 195 | + if (za || size < sizeof(struct target_za_context)) { |
170 | + { .name = "CPUACTLR", | 196 | + goto err; |
171 | + .cp = 15, .opc1 = 0, .crm = 15, | 197 | + } |
172 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | 198 | + za = (struct target_za_context *)ctx; |
173 | + { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | 199 | + za_size = size; |
174 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | 200 | + break; |
175 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 201 | + |
176 | + { .name = "CPUECTLR", | 202 | case TARGET_EXTRA_MAGIC: |
177 | + .cp = 15, .opc1 = 1, .crm = 15, | 203 | if (extra || size != sizeof(struct target_extra_context)) { |
178 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | 204 | goto err; |
179 | + { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | 205 | @@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env, |
180 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | 206 | } |
181 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 207 | |
182 | + { .name = "CPUMERRSR", | 208 | /* SVE data, if present, overwrites FPSIMD data. */ |
183 | + .cp = 15, .opc1 = 2, .crm = 15, | 209 | - if (sve && !target_restore_sve_record(env, sve, sve_size)) { |
184 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | 210 | + if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) { |
185 | + { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | 211 | goto err; |
186 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | 212 | } |
187 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 213 | + if (za && !target_restore_za_record(env, za, za_size, &svcr)) { |
188 | + { .name = "L2MERRSR", | 214 | + goto err; |
189 | + .cp = 15, .opc1 = 3, .crm = 15, | 215 | + } |
190 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | 216 | + if (env->svcr != svcr) { |
191 | +}; | 217 | + env->svcr = svcr; |
192 | + | 218 | + arm_rebuild_hflags(env); |
193 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) | 219 | + } |
194 | +{ | 220 | unlock_user(extra, extra_datap, 0); |
195 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 221 | return 0; |
196 | +} | 222 | |
197 | +#endif /* !CONFIG_USER_ONLY */ | 223 | @@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka, |
198 | + | 224 | .total_size = offsetof(struct target_rt_sigframe, |
199 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | 225 | uc.tuc_mcontext.__reserved), |
200 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | 226 | }; |
201 | 227 | - int fpsimd_ofs, fr_ofs, sve_ofs = 0, vq = 0, sve_size = 0; | |
228 | + int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0; | ||
229 | + int sve_size = 0, za_size = 0; | ||
230 | struct target_rt_sigframe *frame; | ||
231 | struct target_rt_frame_record *fr; | ||
232 | abi_ulong frame_addr, return_addr; | ||
233 | @@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka, | ||
234 | &layout); | ||
235 | |||
236 | /* SVE state needs saving only if it exists. */ | ||
237 | - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | ||
238 | - vq = sve_vq(env); | ||
239 | - sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); | ||
240 | + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || | ||
241 | + cpu_isar_feature(aa64_sme, env_archcpu(env))) { | ||
242 | + sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)), 16); | ||
243 | sve_ofs = alloc_sigframe_space(sve_size, &layout); | ||
244 | } | ||
245 | + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { | ||
246 | + /* ZA state needs saving only if it is enabled. */ | ||
247 | + if (FIELD_EX64(env->svcr, SVCR, ZA)) { | ||
248 | + za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env)); | ||
249 | + } else { | ||
250 | + za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0); | ||
251 | + } | ||
252 | + za_ofs = alloc_sigframe_space(za_size, &layout); | ||
253 | + } | ||
254 | |||
255 | if (layout.extra_ofs) { | ||
256 | /* Reserve space for the extra end marker. The standard end marker | ||
257 | @@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka, | ||
258 | target_setup_end_record((void *)frame + layout.extra_end_ofs); | ||
259 | } | ||
260 | if (sve_ofs) { | ||
261 | - target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size); | ||
262 | + target_setup_sve_record((void *)frame + sve_ofs, env, sve_size); | ||
263 | + } | ||
264 | + if (za_ofs) { | ||
265 | + target_setup_za_record((void *)frame + za_ofs, env, za_size); | ||
266 | } | ||
267 | |||
268 | /* Set up the stack frame for unwinding. */ | ||
269 | @@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka, | ||
270 | env->btype = 2; | ||
271 | } | ||
272 | |||
273 | + /* | ||
274 | + * Invoke the signal handler with both SM and ZA disabled. | ||
275 | + * When clearing SM, ResetSVEState, per SMSTOP. | ||
276 | + */ | ||
277 | + if (FIELD_EX64(env->svcr, SVCR, SM)) { | ||
278 | + arm_reset_sve_state(env); | ||
279 | + } | ||
280 | + if (env->svcr) { | ||
281 | + env->svcr = 0; | ||
282 | + arm_rebuild_hflags(env); | ||
283 | + } | ||
284 | + | ||
285 | if (info) { | ||
286 | tswap_siginfo(&frame->info, info); | ||
287 | env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info); | ||
202 | -- | 288 | -- |
203 | 2.25.1 | 289 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable the a76 for virt and sbsa board use. | 3 | Add "sve" to the sve prctl functions, to distinguish |
4 | them from the coming "sme" prctls with similar names. | ||
4 | 5 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-24-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-42-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | docs/system/arm/virt.rst | 1 + | 11 | linux-user/aarch64/target_prctl.h | 8 ++++---- |
11 | hw/arm/sbsa-ref.c | 1 + | 12 | linux-user/syscall.c | 12 ++++++------ |
12 | hw/arm/virt.c | 1 + | 13 | 2 files changed, 10 insertions(+), 10 deletions(-) |
13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 69 insertions(+) | ||
15 | 14 | ||
16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 15 | diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/system/arm/virt.rst | 17 | --- a/linux-user/aarch64/target_prctl.h |
19 | +++ b/docs/system/arm/virt.rst | 18 | +++ b/linux-user/aarch64/target_prctl.h |
20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | 19 | @@ -XXX,XX +XXX,XX @@ |
21 | - ``cortex-a53`` (64-bit) | 20 | #ifndef AARCH64_TARGET_PRCTL_H |
22 | - ``cortex-a57`` (64-bit) | 21 | #define AARCH64_TARGET_PRCTL_H |
23 | - ``cortex-a72`` (64-bit) | 22 | |
24 | +- ``cortex-a76`` (64-bit) | 23 | -static abi_long do_prctl_get_vl(CPUArchState *env) |
25 | - ``a64fx`` (64-bit) | 24 | +static abi_long do_prctl_sve_get_vl(CPUArchState *env) |
26 | - ``host`` (with KVM only) | 25 | { |
27 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | 26 | ARMCPU *cpu = env_archcpu(env); |
28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | 27 | if (cpu_isar_feature(aa64_sve, cpu)) { |
29 | index XXXXXXX..XXXXXXX 100644 | 28 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_get_vl(CPUArchState *env) |
30 | --- a/hw/arm/sbsa-ref.c | 29 | } |
31 | +++ b/hw/arm/sbsa-ref.c | 30 | return -TARGET_EINVAL; |
32 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { | ||
33 | static const char * const valid_cpus[] = { | ||
34 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
35 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
36 | + ARM_CPU_TYPE_NAME("cortex-a76"), | ||
37 | ARM_CPU_TYPE_NAME("max"), | ||
38 | }; | ||
39 | |||
40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/virt.c | ||
43 | +++ b/hw/arm/virt.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | ||
45 | ARM_CPU_TYPE_NAME("cortex-a53"), | ||
46 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
47 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
48 | + ARM_CPU_TYPE_NAME("cortex-a76"), | ||
49 | ARM_CPU_TYPE_NAME("a64fx"), | ||
50 | ARM_CPU_TYPE_NAME("host"), | ||
51 | ARM_CPU_TYPE_NAME("max"), | ||
52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/cpu64.c | ||
55 | +++ b/target/arm/cpu64.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
57 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
58 | } | 31 | } |
59 | 32 | -#define do_prctl_get_vl do_prctl_get_vl | |
60 | +static void aarch64_a76_initfn(Object *obj) | 33 | +#define do_prctl_sve_get_vl do_prctl_sve_get_vl |
61 | +{ | 34 | |
62 | + ARMCPU *cpu = ARM_CPU(obj); | 35 | -static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) |
63 | + | 36 | +static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) |
64 | + cpu->dtb_compatible = "arm,cortex-a76"; | ||
65 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
73 | + | ||
74 | + /* Ordered by B2.4 AArch64 registers by functional group */ | ||
75 | + cpu->clidr = 0x82000023; | ||
76 | + cpu->ctr = 0x8444C004; | ||
77 | + cpu->dcz_blocksize = 4; | ||
78 | + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; | ||
79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | ||
80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | ||
81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; | ||
82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | ||
83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | ||
84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | ||
85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; | ||
86 | + cpu->id_afr0 = 0x00000000; | ||
87 | + cpu->isar.id_dfr0 = 0x04010088; | ||
88 | + cpu->isar.id_isar0 = 0x02101110; | ||
89 | + cpu->isar.id_isar1 = 0x13112111; | ||
90 | + cpu->isar.id_isar2 = 0x21232042; | ||
91 | + cpu->isar.id_isar3 = 0x01112131; | ||
92 | + cpu->isar.id_isar4 = 0x00010142; | ||
93 | + cpu->isar.id_isar5 = 0x01011121; | ||
94 | + cpu->isar.id_isar6 = 0x00000010; | ||
95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
103 | + cpu->midr = 0x414fd0b1; /* r4p1 */ | ||
104 | + cpu->revidr = 0; | ||
105 | + | ||
106 | + /* From B2.18 CCSIDR_EL1 */ | ||
107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | ||
108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | ||
109 | + cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ | ||
110 | + | ||
111 | + /* From B2.93 SCTLR_EL3 */ | ||
112 | + cpu->reset_sctlr = 0x30c50838; | ||
113 | + | ||
114 | + /* From B4.23 ICH_VTR_EL2 */ | ||
115 | + cpu->gic_num_lrs = 4; | ||
116 | + cpu->gic_vpribits = 5; | ||
117 | + cpu->gic_vprebits = 5; | ||
118 | + | ||
119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | ||
120 | + cpu->isar.mvfr0 = 0x10110222; | ||
121 | + cpu->isar.mvfr1 = 0x13211111; | ||
122 | + cpu->isar.mvfr2 = 0x00000043; | ||
123 | +} | ||
124 | + | ||
125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | ||
126 | { | 37 | { |
127 | /* | 38 | /* |
128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | 39 | * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. |
129 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, | 40 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) |
130 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, | 41 | } |
131 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | 42 | return -TARGET_EINVAL; |
132 | + { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | 43 | } |
133 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | 44 | -#define do_prctl_set_vl do_prctl_set_vl |
134 | { .name = "max", .initfn = aarch64_max_initfn }, | 45 | +#define do_prctl_sve_set_vl do_prctl_sve_set_vl |
135 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | 46 | |
47 | static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) | ||
48 | { | ||
49 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/linux-user/syscall.c | ||
52 | +++ b/linux-user/syscall.c | ||
53 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) | ||
54 | #ifndef do_prctl_set_fp_mode | ||
55 | #define do_prctl_set_fp_mode do_prctl_inval1 | ||
56 | #endif | ||
57 | -#ifndef do_prctl_get_vl | ||
58 | -#define do_prctl_get_vl do_prctl_inval0 | ||
59 | +#ifndef do_prctl_sve_get_vl | ||
60 | +#define do_prctl_sve_get_vl do_prctl_inval0 | ||
61 | #endif | ||
62 | -#ifndef do_prctl_set_vl | ||
63 | -#define do_prctl_set_vl do_prctl_inval1 | ||
64 | +#ifndef do_prctl_sve_set_vl | ||
65 | +#define do_prctl_sve_set_vl do_prctl_inval1 | ||
66 | #endif | ||
67 | #ifndef do_prctl_reset_keys | ||
68 | #define do_prctl_reset_keys do_prctl_inval1 | ||
69 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, | ||
70 | case PR_SET_FP_MODE: | ||
71 | return do_prctl_set_fp_mode(env, arg2); | ||
72 | case PR_SVE_GET_VL: | ||
73 | - return do_prctl_get_vl(env); | ||
74 | + return do_prctl_sve_get_vl(env); | ||
75 | case PR_SVE_SET_VL: | ||
76 | - return do_prctl_set_vl(env, arg2); | ||
77 | + return do_prctl_sve_set_vl(env, arg2); | ||
78 | case PR_PAC_RESET_KEYS: | ||
79 | if (arg3 || arg4 || arg5) { | ||
80 | return -TARGET_EINVAL; | ||
136 | -- | 81 | -- |
137 | 2.25.1 | 82 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local | 3 | These prctl set the Streaming SVE vector length, which may |
4 | vpidr_regs definition, and rely on the squashing to ARM_CP_CONST | 4 | be completely different from the Normal SVE vector length. |
5 | while registering for v8. | ||
6 | |||
7 | This is a behavior change for v7 cpus with Security Extensions and | ||
8 | without Virtualization Extensions, in that the virtualization cpregs | ||
9 | are now correctly not present. This would be a migration compatibility | ||
10 | break, except that we have an existing bug in which migration of 32-bit | ||
11 | cpus with Security Extensions enabled does not work. | ||
12 | 5 | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20220506180242.216785-3-richard.henderson@linaro.org | 8 | Message-id: 20220708151540.18136-43-richard.henderson@linaro.org |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 10 | --- |
18 | target/arm/helper.c | 158 ++++---------------------------------------- | 11 | linux-user/aarch64/target_prctl.h | 54 +++++++++++++++++++++++++++++++ |
19 | 1 file changed, 13 insertions(+), 145 deletions(-) | 12 | linux-user/syscall.c | 16 +++++++++ |
13 | 2 files changed, 70 insertions(+) | ||
20 | 14 | ||
21 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h |
22 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/helper.c | 17 | --- a/linux-user/aarch64/target_prctl.h |
24 | +++ b/target/arm/helper.c | 18 | +++ b/linux-user/aarch64/target_prctl.h |
25 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 19 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env) |
26 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | ||
27 | }; | ||
28 | |||
29 | -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ | ||
30 | -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | ||
31 | - { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
32 | - .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | ||
33 | - .access = PL2_RW, | ||
34 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | ||
35 | - { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
36 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | ||
37 | - .access = PL2_RW, | ||
38 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
39 | - { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, | ||
40 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | ||
41 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
42 | - { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, | ||
43 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | ||
44 | - .access = PL2_RW, | ||
45 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
46 | - { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
47 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | ||
48 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
49 | - { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, | ||
50 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | ||
51 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
52 | - .resetvalue = 0 }, | ||
53 | - { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | ||
54 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | ||
55 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
56 | - { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, | ||
57 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | ||
58 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
59 | - .resetvalue = 0 }, | ||
60 | - { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, | ||
61 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | ||
62 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
63 | - .resetvalue = 0 }, | ||
64 | - { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, | ||
65 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | ||
66 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
67 | - .resetvalue = 0 }, | ||
68 | - { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | ||
69 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | ||
70 | - .access = PL2_RW, .type = ARM_CP_CONST, | ||
71 | - .resetvalue = 0 }, | ||
72 | - { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
73 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | ||
74 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
75 | - { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
76 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | ||
77 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
78 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | - { .name = "VTTBR", .state = ARM_CP_STATE_AA32, | ||
80 | - .cp = 15, .opc1 = 6, .crm = 2, | ||
81 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
82 | - .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
83 | - { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | ||
84 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | ||
85 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
86 | - { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, | ||
87 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | ||
88 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
89 | - { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
90 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | ||
91 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
92 | - { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, | ||
93 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | ||
94 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
95 | - { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | ||
96 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
97 | - .resetvalue = 0 }, | ||
98 | - { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
99 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | ||
100 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
101 | - { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, | ||
102 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | ||
103 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
104 | - { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | ||
105 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
106 | - .resetvalue = 0 }, | ||
107 | - { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, | ||
108 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | ||
109 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
110 | - { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | ||
111 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
112 | - .resetvalue = 0 }, | ||
113 | - { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | ||
114 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | ||
115 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
116 | - { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
117 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | ||
118 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
119 | - { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
120 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | ||
121 | - .access = PL2_RW, .accessfn = access_tda, | ||
122 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
123 | - { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
124 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | ||
125 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
126 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
127 | - { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
128 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | ||
129 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
130 | - { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
131 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | ||
132 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
133 | - { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | ||
134 | - .type = ARM_CP_CONST, | ||
135 | - .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | ||
136 | - .access = PL2_RW, .resetvalue = 0 }, | ||
137 | -}; | ||
138 | - | ||
139 | -/* Ditto, but for registers which exist in ARMv8 but not v7 */ | ||
140 | -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | ||
141 | - { .name = "HCR2", .state = ARM_CP_STATE_AA32, | ||
142 | - .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | ||
143 | - .access = PL2_RW, | ||
144 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
145 | -}; | ||
146 | - | ||
147 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
148 | { | 20 | { |
149 | ARMCPU *cpu = env_archcpu(env); | 21 | ARMCPU *cpu = env_archcpu(env); |
150 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 22 | if (cpu_isar_feature(aa64_sve, cpu)) { |
151 | define_arm_cp_regs(cpu, v8_idregs); | 23 | + /* PSTATE.SM is always unset on syscall entry. */ |
152 | define_arm_cp_regs(cpu, v8_cp_reginfo); | 24 | return sve_vq(env) * 16; |
153 | } | 25 | } |
154 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | 26 | return -TARGET_EINVAL; |
27 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) | ||
28 | && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { | ||
29 | uint32_t vq, old_vq; | ||
30 | |||
31 | + /* PSTATE.SM is always unset on syscall entry. */ | ||
32 | old_vq = sve_vq(env); | ||
33 | |||
34 | /* | ||
35 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) | ||
36 | } | ||
37 | #define do_prctl_sve_set_vl do_prctl_sve_set_vl | ||
38 | |||
39 | +static abi_long do_prctl_sme_get_vl(CPUArchState *env) | ||
40 | +{ | ||
41 | + ARMCPU *cpu = env_archcpu(env); | ||
42 | + if (cpu_isar_feature(aa64_sme, cpu)) { | ||
43 | + return sme_vq(env) * 16; | ||
44 | + } | ||
45 | + return -TARGET_EINVAL; | ||
46 | +} | ||
47 | +#define do_prctl_sme_get_vl do_prctl_sme_get_vl | ||
155 | + | 48 | + |
49 | +static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2) | ||
50 | +{ | ||
156 | + /* | 51 | + /* |
157 | + * Register the base EL2 cpregs. | 52 | + * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT. |
158 | + * Pre v8, these registers are implemented only as part of the | 53 | + * Note the kernel definition of sve_vl_valid allows for VQ=512, |
159 | + * Virtualization Extensions (EL2 present). Beginning with v8, | 54 | + * i.e. VL=8192, even though the architectural maximum is VQ=16. |
160 | + * if EL2 is missing but EL3 is enabled, mostly these become | ||
161 | + * RES0 from EL3, with some specific exceptions. | ||
162 | + */ | 55 | + */ |
163 | + if (arm_feature(env, ARM_FEATURE_EL2) | 56 | + if (cpu_isar_feature(aa64_sme, env_archcpu(env)) |
164 | + || (arm_feature(env, ARM_FEATURE_EL3) | 57 | + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { |
165 | + && arm_feature(env, ARM_FEATURE_V8))) { | 58 | + int vq, old_vq; |
166 | uint64_t vmpidr_def = mpidr_read_val(env); | ||
167 | ARMCPRegInfo vpidr_regs[] = { | ||
168 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
169 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
170 | }; | ||
171 | define_one_arm_cp_reg(cpu, &rvbar); | ||
172 | } | ||
173 | - } else { | ||
174 | - /* If EL2 is missing but higher ELs are enabled, we need to | ||
175 | - * register the no_el2 reginfos. | ||
176 | - */ | ||
177 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
178 | - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value | ||
179 | - * of MIDR_EL1 and MPIDR_EL1. | ||
180 | - */ | ||
181 | - ARMCPRegInfo vpidr_regs[] = { | ||
182 | - { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
183 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
184 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
185 | - .type = ARM_CP_CONST, .resetvalue = cpu->midr, | ||
186 | - .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
187 | - { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
188 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
189 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
190 | - .type = ARM_CP_NO_RAW, | ||
191 | - .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | ||
192 | - }; | ||
193 | - define_arm_cp_regs(cpu, vpidr_regs); | ||
194 | - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); | ||
195 | - if (arm_feature(env, ARM_FEATURE_V8)) { | ||
196 | - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | ||
197 | - } | ||
198 | - } | ||
199 | } | ||
200 | + | 59 | + |
201 | + /* Register the base EL3 cpregs. */ | 60 | + old_vq = sme_vq(env); |
202 | if (arm_feature(env, ARM_FEATURE_EL3)) { | 61 | + |
203 | define_arm_cp_regs(cpu, el3_cp_reginfo); | 62 | + /* |
204 | ARMCPRegInfo el3_regs[] = { | 63 | + * Bound the value of vq, so that we know that it fits into |
64 | + * the 4-bit field in SMCR_EL1. Because PSTATE.SM is cleared | ||
65 | + * on syscall entry, we are not modifying the current SVE | ||
66 | + * vector length. | ||
67 | + */ | ||
68 | + vq = MAX(arg2 / 16, 1); | ||
69 | + vq = MIN(vq, 16); | ||
70 | + env->vfp.smcr_el[1] = | ||
71 | + FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1); | ||
72 | + | ||
73 | + /* Delay rebuilding hflags until we know if ZA must change. */ | ||
74 | + vq = sve_vqm1_for_el_sm(env, 0, true) + 1; | ||
75 | + | ||
76 | + if (vq != old_vq) { | ||
77 | + /* | ||
78 | + * PSTATE.ZA state is cleared on any change to SVL. | ||
79 | + * We need not call arm_rebuild_hflags because PSTATE.SM was | ||
80 | + * cleared on syscall entry, so this hasn't changed VL. | ||
81 | + */ | ||
82 | + env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0); | ||
83 | + arm_rebuild_hflags(env); | ||
84 | + } | ||
85 | + return vq * 16; | ||
86 | + } | ||
87 | + return -TARGET_EINVAL; | ||
88 | +} | ||
89 | +#define do_prctl_sme_set_vl do_prctl_sme_set_vl | ||
90 | + | ||
91 | static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) | ||
92 | { | ||
93 | ARMCPU *cpu = env_archcpu(env); | ||
94 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c | ||
95 | index XXXXXXX..XXXXXXX 100644 | ||
96 | --- a/linux-user/syscall.c | ||
97 | +++ b/linux-user/syscall.c | ||
98 | @@ -XXX,XX +XXX,XX @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) | ||
99 | #ifndef PR_SET_SYSCALL_USER_DISPATCH | ||
100 | # define PR_SET_SYSCALL_USER_DISPATCH 59 | ||
101 | #endif | ||
102 | +#ifndef PR_SME_SET_VL | ||
103 | +# define PR_SME_SET_VL 63 | ||
104 | +# define PR_SME_GET_VL 64 | ||
105 | +# define PR_SME_VL_LEN_MASK 0xffff | ||
106 | +# define PR_SME_VL_INHERIT (1 << 17) | ||
107 | +#endif | ||
108 | |||
109 | #include "target_prctl.h" | ||
110 | |||
111 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) | ||
112 | #ifndef do_prctl_set_unalign | ||
113 | #define do_prctl_set_unalign do_prctl_inval1 | ||
114 | #endif | ||
115 | +#ifndef do_prctl_sme_get_vl | ||
116 | +#define do_prctl_sme_get_vl do_prctl_inval0 | ||
117 | +#endif | ||
118 | +#ifndef do_prctl_sme_set_vl | ||
119 | +#define do_prctl_sme_set_vl do_prctl_inval1 | ||
120 | +#endif | ||
121 | |||
122 | static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, | ||
123 | abi_long arg3, abi_long arg4, abi_long arg5) | ||
124 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, | ||
125 | return do_prctl_sve_get_vl(env); | ||
126 | case PR_SVE_SET_VL: | ||
127 | return do_prctl_sve_set_vl(env, arg2); | ||
128 | + case PR_SME_GET_VL: | ||
129 | + return do_prctl_sme_get_vl(env); | ||
130 | + case PR_SME_SET_VL: | ||
131 | + return do_prctl_sme_set_vl(env, arg2); | ||
132 | case PR_PAC_RESET_KEYS: | ||
133 | if (arg3 || arg4 || arg5) { | ||
134 | return -TARGET_EINVAL; | ||
205 | -- | 135 | -- |
206 | 2.25.1 | 136 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | There is no branch prediction in TCG, therefore there is no | 3 | There's no reason to set CPACR_EL1.ZEN if SVE disabled. |
4 | need to actually include the context number into the predictor. | ||
5 | Therefore all we need to do is add the state for SCXTNUM_ELx. | ||
6 | 4 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-21-richard.henderson@linaro.org | 7 | Message-id: 20220708151540.18136-44-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 9 | --- |
12 | docs/system/arm/emulation.rst | 3 ++ | 10 | target/arm/cpu.c | 7 +++---- |
13 | target/arm/cpu.h | 16 +++++++++ | 11 | 1 file changed, 3 insertions(+), 4 deletions(-) |
14 | target/arm/cpu.c | 5 +++ | ||
15 | target/arm/cpu64.c | 3 +- | ||
16 | target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- | ||
17 | 5 files changed, 86 insertions(+), 2 deletions(-) | ||
18 | 12 | ||
19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/docs/system/arm/emulation.rst | ||
22 | +++ b/docs/system/arm/emulation.rst | ||
23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
24 | - FEAT_BF16 (AArch64 BFloat16 instructions) | ||
25 | - FEAT_BTI (Branch Target Identification) | ||
26 | - FEAT_CSV2 (Cache speculation variant 2) | ||
27 | +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | ||
28 | +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | ||
29 | +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) | ||
30 | - FEAT_DIT (Data Independent Timing instructions) | ||
31 | - FEAT_DPB (DC CVAP instruction) | ||
32 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
33 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/cpu.h | ||
36 | +++ b/target/arm/cpu.h | ||
37 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
38 | ARMPACKey apdb; | ||
39 | ARMPACKey apga; | ||
40 | } keys; | ||
41 | + | ||
42 | + uint64_t scxtnum_el[4]; | ||
43 | #endif | ||
44 | |||
45 | #if defined(CONFIG_USER_ONLY) | ||
46 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | ||
47 | #define SCTLR_WXN (1U << 19) | ||
48 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | ||
49 | #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ | ||
50 | +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ | ||
51 | #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ | ||
52 | #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ | ||
53 | #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ | ||
54 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) | ||
55 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; | ||
56 | } | ||
57 | |||
58 | +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) | ||
59 | +{ | ||
60 | + int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); | ||
61 | + if (key >= 2) { | ||
62 | + return true; /* FEAT_CSV2_2 */ | ||
63 | + } | ||
64 | + if (key == 1) { | ||
65 | + key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); | ||
66 | + return key >= 2; /* FEAT_CSV2_1p2 */ | ||
67 | + } | ||
68 | + return false; | ||
69 | +} | ||
70 | + | ||
71 | static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) | ||
72 | { | ||
73 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; | ||
74 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
75 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
76 | --- a/target/arm/cpu.c | 15 | --- a/target/arm/cpu.c |
77 | +++ b/target/arm/cpu.c | 16 | +++ b/target/arm/cpu.c |
78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | 17 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
79 | */ | 18 | /* and to the FP/Neon instructions */ |
80 | env->cp15.gcr_el1 = 0x1ffff; | 19 | env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, |
20 | CPACR_EL1, FPEN, 3); | ||
21 | - /* and to the SVE instructions */ | ||
22 | - env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, | ||
23 | - CPACR_EL1, ZEN, 3); | ||
24 | - /* with reasonable vector length */ | ||
25 | + /* and to the SVE instructions, with default vector length */ | ||
26 | if (cpu_isar_feature(aa64_sve, cpu)) { | ||
27 | + env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, | ||
28 | + CPACR_EL1, ZEN, 3); | ||
29 | env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; | ||
81 | } | 30 | } |
82 | + /* | 31 | /* |
83 | + * Disable access to SCXTNUM_EL0 from CSV2_1p2. | ||
84 | + * This is not yet exposed from the Linux kernel in any way. | ||
85 | + */ | ||
86 | + env->cp15.sctlr_el[1] |= SCTLR_TSCXT; | ||
87 | #else | ||
88 | /* Reset into the highest available EL */ | ||
89 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
90 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/target/arm/cpu64.c | ||
93 | +++ b/target/arm/cpu64.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
95 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
96 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
97 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
98 | - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ | ||
99 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | ||
100 | cpu->isar.id_aa64pfr0 = t; | ||
101 | |||
102 | t = cpu->isar.id_aa64pfr1; | ||
103 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
104 | * we do for EL2 with the virtualization=on property. | ||
105 | */ | ||
106 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
107 | + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ | ||
108 | cpu->isar.id_aa64pfr1 = t; | ||
109 | |||
110 | t = cpu->isar.id_aa64mmfr0; | ||
111 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/helper.c | ||
114 | +++ b/target/arm/helper.c | ||
115 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
116 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
117 | valid_mask |= SCR_ATA; | ||
118 | } | ||
119 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
120 | + valid_mask |= SCR_ENSCXT; | ||
121 | + } | ||
122 | } else { | ||
123 | valid_mask &= ~(SCR_RW | SCR_ST); | ||
124 | if (cpu_isar_feature(aa32_ras, cpu)) { | ||
125 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
126 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
127 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | ||
128 | } | ||
129 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
130 | + valid_mask |= HCR_ENSCXT; | ||
131 | + } | ||
132 | } | ||
133 | |||
134 | /* Clear RES0 bits. */ | ||
135 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
136 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), | ||
137 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | ||
138 | |||
139 | + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), | ||
140 | + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", | ||
141 | + isar_feature_aa64_scxtnum }, | ||
142 | + | ||
143 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ | ||
144 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | ||
145 | }; | ||
146 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
147 | }, | ||
148 | }; | ||
149 | |||
150 | -#endif | ||
151 | +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, | ||
152 | + bool isread) | ||
153 | +{ | ||
154 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
155 | + int el = arm_current_el(env); | ||
156 | + | ||
157 | + if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { | ||
158 | + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { | ||
159 | + if (hcr & HCR_TGE) { | ||
160 | + return CP_ACCESS_TRAP_EL2; | ||
161 | + } | ||
162 | + return CP_ACCESS_TRAP; | ||
163 | + } | ||
164 | + } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | ||
165 | + return CP_ACCESS_TRAP_EL2; | ||
166 | + } | ||
167 | + if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | ||
168 | + return CP_ACCESS_TRAP_EL2; | ||
169 | + } | ||
170 | + if (el < 3 | ||
171 | + && arm_feature(env, ARM_FEATURE_EL3) | ||
172 | + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | ||
173 | + return CP_ACCESS_TRAP_EL3; | ||
174 | + } | ||
175 | + return CP_ACCESS_OK; | ||
176 | +} | ||
177 | + | ||
178 | +static const ARMCPRegInfo scxtnum_reginfo[] = { | ||
179 | + { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | ||
180 | + .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | ||
181 | + .access = PL0_RW, .accessfn = access_scxtnum, | ||
182 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, | ||
183 | + { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | ||
184 | + .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | ||
185 | + .access = PL1_RW, .accessfn = access_scxtnum, | ||
186 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, | ||
187 | + { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | ||
188 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | ||
189 | + .access = PL2_RW, .accessfn = access_scxtnum, | ||
190 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | ||
191 | + { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | ||
192 | + .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | ||
193 | + .access = PL3_RW, | ||
194 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | ||
195 | +}; | ||
196 | +#endif /* TARGET_AARCH64 */ | ||
197 | |||
198 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
199 | bool isread) | ||
200 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
201 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | ||
202 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
203 | } | ||
204 | + | ||
205 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
206 | + define_arm_cp_regs(cpu, scxtnum_reginfo); | ||
207 | + } | ||
208 | #endif | ||
209 | |||
210 | if (cpu_isar_feature(any_predinv, cpu)) { | ||
211 | -- | 32 | -- |
212 | 2.25.1 | 33 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 | 3 | Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. |
4 | during arm_cpu_realizefn. | ||
5 | 4 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220506180242.216785-11-richard.henderson@linaro.org | 7 | Message-id: 20220708151540.18136-45-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | target/arm/cpu.c | 22 +++++++++++++--------- | 10 | target/arm/cpu.c | 11 +++++++++++ |
12 | 1 file changed, 13 insertions(+), 9 deletions(-) | 11 | 1 file changed, 11 insertions(+) |
13 | 12 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 15 | --- a/target/arm/cpu.c |
17 | +++ b/target/arm/cpu.c | 16 | +++ b/target/arm/cpu.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 17 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
19 | */ | 18 | CPACR_EL1, ZEN, 3); |
20 | unset_feature(env, ARM_FEATURE_EL3); | 19 | env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; |
21 | 20 | } | |
22 | - /* Disable the security extension feature bits in the processor feature | 21 | + /* and for SME instructions, with default vector length, and TPIDR2 */ |
23 | - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. | 22 | + if (cpu_isar_feature(aa64_sme, cpu)) { |
24 | + /* | 23 | + env->cp15.sctlr_el[1] |= SCTLR_EnTP2; |
25 | + * Disable the security extension feature bits in the processor | 24 | + env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, |
26 | + * feature registers as well. | 25 | + CPACR_EL1, SMEN, 3); |
27 | */ | 26 | + env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; |
28 | - cpu->isar.id_pfr1 &= ~0xf0; | 27 | + if (cpu_isar_feature(aa64_sme_fa64, cpu)) { |
29 | - cpu->isar.id_aa64pfr0 &= ~0xf000; | 28 | + env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], |
30 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | 29 | + SMCR, FA64, 1); |
31 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | 30 | + } |
32 | + ID_AA64PFR0, EL3, 0); | 31 | + } |
33 | } | 32 | /* |
34 | 33 | * Enable 48-bit address space (TODO: take reserved_va into account). | |
35 | if (!cpu->has_el2) { | 34 | * Enable TBI0 but not TBI1. |
36 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
37 | } | ||
38 | |||
39 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | ||
40 | - /* Disable the hypervisor feature bits in the processor feature | ||
41 | - * registers if we don't have EL2. These are id_pfr1[15:12] and | ||
42 | - * id_aa64pfr0_el1[11:8]. | ||
43 | + /* | ||
44 | + * Disable the hypervisor feature bits in the processor feature | ||
45 | + * registers if we don't have EL2. | ||
46 | */ | ||
47 | - cpu->isar.id_aa64pfr0 &= ~0xf00; | ||
48 | - cpu->isar.id_pfr1 &= ~0xf000; | ||
49 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
50 | + ID_AA64PFR0, EL2, 0); | ||
51 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, | ||
52 | + ID_PFR1, VIRTUALIZATION, 0); | ||
53 | } | ||
54 | |||
55 | #ifndef CONFIG_USER_ONLY | ||
56 | -- | 35 | -- |
57 | 2.25.1 | 36 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Currently, the SMP configuration isn't considered when the CPU | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | topology is populated. In this case, it's impossible to provide | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | the default CPU-to-NUMA mapping or association based on the socket | 5 | Message-id: 20220708151540.18136-46-richard.henderson@linaro.org |
6 | ID of the given CPU. | ||
7 | |||
8 | This takes account of SMP configuration when the CPU topology | ||
9 | is populated. The die ID for the given CPU isn't assigned since | ||
10 | it's not supported on arm/virt machine. Besides, the used SMP | ||
11 | configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted | ||
12 | to avoid testing failure | ||
13 | |||
14 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
15 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
16 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
17 | Message-id: 20220503140304.855514-4-gshan@redhat.com | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 7 | --- |
20 | hw/arm/virt.c | 15 ++++++++++++++- | 8 | linux-user/elfload.c | 20 ++++++++++++++++++++ |
21 | 1 file changed, 14 insertions(+), 1 deletion(-) | 9 | 1 file changed, 20 insertions(+) |
22 | 10 | ||
23 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 11 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c |
24 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/hw/arm/virt.c | 13 | --- a/linux-user/elfload.c |
26 | +++ b/hw/arm/virt.c | 14 | +++ b/linux-user/elfload.c |
27 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 15 | @@ -XXX,XX +XXX,XX @@ enum { |
28 | int n; | 16 | ARM_HWCAP2_A64_RNG = 1 << 16, |
29 | unsigned int max_cpus = ms->smp.max_cpus; | 17 | ARM_HWCAP2_A64_BTI = 1 << 17, |
30 | VirtMachineState *vms = VIRT_MACHINE(ms); | 18 | ARM_HWCAP2_A64_MTE = 1 << 18, |
31 | + MachineClass *mc = MACHINE_GET_CLASS(vms); | 19 | + ARM_HWCAP2_A64_ECV = 1 << 19, |
32 | 20 | + ARM_HWCAP2_A64_AFP = 1 << 20, | |
33 | if (ms->possible_cpus) { | 21 | + ARM_HWCAP2_A64_RPRES = 1 << 21, |
34 | assert(ms->possible_cpus->len == max_cpus); | 22 | + ARM_HWCAP2_A64_MTE3 = 1 << 22, |
35 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) | 23 | + ARM_HWCAP2_A64_SME = 1 << 23, |
36 | ms->possible_cpus->cpus[n].type = ms->cpu_type; | 24 | + ARM_HWCAP2_A64_SME_I16I64 = 1 << 24, |
37 | ms->possible_cpus->cpus[n].arch_id = | 25 | + ARM_HWCAP2_A64_SME_F64F64 = 1 << 25, |
38 | virt_cpu_mp_affinity(vms, n); | 26 | + ARM_HWCAP2_A64_SME_I8I32 = 1 << 26, |
39 | + | 27 | + ARM_HWCAP2_A64_SME_F16F32 = 1 << 27, |
40 | + assert(!mc->smp_props.dies_supported); | 28 | + ARM_HWCAP2_A64_SME_B16F32 = 1 << 28, |
41 | + ms->possible_cpus->cpus[n].props.has_socket_id = true; | 29 | + ARM_HWCAP2_A64_SME_F32F32 = 1 << 29, |
42 | + ms->possible_cpus->cpus[n].props.socket_id = | 30 | + ARM_HWCAP2_A64_SME_FA64 = 1 << 30, |
43 | + n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); | 31 | }; |
44 | + ms->possible_cpus->cpus[n].props.has_cluster_id = true; | 32 | |
45 | + ms->possible_cpus->cpus[n].props.cluster_id = | 33 | #define ELF_HWCAP get_elf_hwcap() |
46 | + (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; | 34 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap2(void) |
47 | + ms->possible_cpus->cpus[n].props.has_core_id = true; | 35 | GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); |
48 | + ms->possible_cpus->cpus[n].props.core_id = | 36 | GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); |
49 | + (n / ms->smp.threads) % ms->smp.cores; | 37 | GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); |
50 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | 38 | + GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | |
51 | - ms->possible_cpus->cpus[n].props.thread_id = n; | 39 | + ARM_HWCAP2_A64_SME_F32F32 | |
52 | + ms->possible_cpus->cpus[n].props.thread_id = | 40 | + ARM_HWCAP2_A64_SME_B16F32 | |
53 | + n % ms->smp.threads; | 41 | + ARM_HWCAP2_A64_SME_F16F32 | |
54 | } | 42 | + ARM_HWCAP2_A64_SME_I8I32)); |
55 | return ms->possible_cpus; | 43 | + GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); |
44 | + GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); | ||
45 | + GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); | ||
46 | |||
47 | return hwcaps; | ||
56 | } | 48 | } |
57 | -- | 49 | -- |
58 | 2.25.1 | 50 | 2.25.1 | diff view generated by jsdifflib |