[PULL 00/32] target-arm queue
[PULL 000/117] target-arm queue
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target-arm queue: the big stuff here is the final part of
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Massive pullreq but almost all of that is RTH's SVE
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rth's patches for Cortex-A76 and Neoverse-N1 support;
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refactoring patchset. The other interesting thing here is
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also present are Gavin's NUMA series and a few other things.
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the fix for compiling on aarch64 macos.
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4
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
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The following changes since commit f7a1ea403e0282a7f57edd4298c4f65f24165da5:
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Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
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Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-29 16:34:56 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220530
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for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
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for you to fetch changes up to b1071174d2a2ab371082b7d4b5f19e98edc61ac6:
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hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
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target/arm: Remove aa64_sve check from before disas_sve (2022-05-30 17:05:12 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* MAINTAINERS/.mailmap: update email for Leif Lindholm
22
* docs/system/arm: Add FEAT_HCX to list of emulated features
23
* hw/arm: add version information to sbsa-ref machine DT
23
* target/arm/hvf: Include missing "cpregs.h"
24
* Enable new features for -cpu max:
24
* hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
25
FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
25
* SVE: refactor to use TRANS/TRANS_FEAT macros and push
26
FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
26
SVE feature check down to individual insn level
27
* Emulate Cortex-A76
28
* Emulate Neoverse-N1
29
* Fix the virt board default NUMA topology
30
27
31
----------------------------------------------------------------
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----------------------------------------------------------------
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Gavin Shan (6):
29
Icenowy Zheng (1):
33
qapi/machine.json: Add cluster-id
30
hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
34
qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
35
hw/arm/virt: Consider SMP configuration in CPU topology
36
qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
37
hw/arm/virt: Fix CPU's default NUMA node ID
38
hw/acpi/aml-build: Use existing CPU topology to build PPTT table
39
31
40
Leif Lindholm (2):
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Peter Maydell (1):
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MAINTAINERS/.mailmap: update email for Leif Lindholm
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docs/system/arm: Add FEAT_HCX to list of emulated features
42
hw/arm: add versioning to sbsa-ref machine DT
43
34
44
Richard Henderson (24):
35
Philippe Mathieu-Daudé (1):
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target/arm: Handle cpreg registration for missing EL
36
target/arm/hvf: Include missing "cpregs.h"
46
target/arm: Drop EL3 no EL2 fallbacks
47
target/arm: Merge zcr reginfo
48
target/arm: Adjust definition of CONTEXTIDR_EL2
49
target/arm: Move cortex impdef sysregs to cpu_tcg.c
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target/arm: Update qemu-system-arm -cpu max to cortex-a57
51
target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
52
target/arm: Split out aa32_max_features
53
target/arm: Annotate arm_max_initfn with FEAT identifiers
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target/arm: Use field names for manipulating EL2 and EL3 modes
55
target/arm: Enable FEAT_Debugv8p2 for -cpu max
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target/arm: Enable FEAT_Debugv8p4 for -cpu max
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target/arm: Add minimal RAS registers
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target/arm: Enable SCR and HCR bits for RAS
59
target/arm: Implement virtual SError exceptions
60
target/arm: Implement ESB instruction
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target/arm: Enable FEAT_RAS for -cpu max
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target/arm: Enable FEAT_IESB for -cpu max
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target/arm: Enable FEAT_CSV2 for -cpu max
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target/arm: Enable FEAT_CSV2_2 for -cpu max
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target/arm: Enable FEAT_CSV3 for -cpu max
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target/arm: Enable FEAT_DGH for -cpu max
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target/arm: Define cortex-a76
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target/arm: Define neoverse-n1
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37
70
docs/system/arm/emulation.rst | 10 +
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Richard Henderson (114):
71
docs/system/arm/virt.rst | 2 +
39
target/arm: Introduce TRANS, TRANS_FEAT
72
qapi/machine.json | 6 +-
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target/arm: Move null function and sve check into gen_gvec_ool_zz
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target/arm/cpregs.h | 11 +
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target/arm: Use TRANS_FEAT for gen_gvec_ool_zz
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target/arm/cpu.h | 23 ++
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target/arm: Move null function and sve check into gen_gvec_ool_zzz
75
target/arm/helper.h | 1 +
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target/arm: Introduce gen_gvec_ool_arg_zzz
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target/arm/internals.h | 16 ++
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target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz
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target/arm/syndrome.h | 5 +
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target/arm: Use TRANS_FEAT for do_sve2_zzz_ool
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target/arm/a32.decode | 16 +-
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target/arm: Move null function and sve check into gen_gvec_ool_zzzz
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target/arm/t32.decode | 18 +-
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target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz
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hw/acpi/aml-build.c | 111 ++++----
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target/arm: Introduce gen_gvec_ool_arg_zzzz
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hw/arm/sbsa-ref.c | 16 ++
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target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool
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hw/arm/virt.c | 21 +-
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target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz
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hw/core/machine-hmp-cmds.c | 4 +
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target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz
84
hw/core/machine.c | 16 ++
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target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz
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target/arm/cpu.c | 66 ++++-
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target/arm: Use TRANS_FEAT for do_sve2_zzz_data
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target/arm/cpu64.c | 353 ++++++++++++++-----------
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target/arm: Use TRANS_FEAT for do_sve2_zzzz_data
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target/arm/cpu_tcg.c | 227 +++++++++++-----
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target/arm: Use TRANS_FEAT for do_sve2_zzw_data
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target/arm/helper.c | 600 +++++++++++++++++++++++++-----------------
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target/arm: Use TRANS_FEAT for USDOT_zzzz
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target/arm/op_helper.c | 43 +++
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target/arm: Move null function and sve check into gen_gvec_ool_zzp
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target/arm/translate-a64.c | 18 ++
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target/arm: Introduce gen_gvec_ool_arg_zpz
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target/arm/translate.c | 23 ++
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target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz
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tests/qtest/numa-test.c | 19 +-
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target/arm: Use TRANS_FEAT for do_sve2_zpz_data
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.mailmap | 3 +-
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target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi
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MAINTAINERS | 2 +-
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target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi
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25 files changed, 1068 insertions(+), 562 deletions(-)
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target/arm: Move null function and sve check into gen_gvec_ool_zzzp
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target/arm: Introduce gen_gvec_ool_arg_zpzz
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target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz
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target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool
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target/arm: Merge gen_gvec_fn_zz into do_mov_z
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target/arm: Move null function and sve check into gen_gvec_fn_zzz
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target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz
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target/arm: More use of gen_gvec_fn_arg_zzz
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target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz
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target/arm: Use TRANS_FEAT for do_sve2_fn_zzz
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target/arm: Use TRANS_FEAT for RAX1
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target/arm: Introduce gen_gvec_fn_arg_zzzz
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target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn
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target/arm: Introduce gen_gvec_fn_zzi
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target/arm: Use TRANS_FEAT for do_zz_dbm
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target/arm: Hoist sve access check through do_sel_z
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target/arm: Introduce gen_gvec_fn_arg_zzi
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target/arm: Use TRANS_FEAT for do_sve2_fn2i
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target/arm: Use TRANS_FEAT for do_vpz_ool
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target/arm: Use TRANS_FEAT for do_shift_imm
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target/arm: Introduce do_shift_zpzi
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target/arm: Use TRANS_FEAT for do_shift_zpzi
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target/arm: Use TRANS_FEAT for do_zpzzz_ool
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target/arm: Move sve check into do_index
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target/arm: Use TRANS_FEAT for do_index
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target/arm: Use TRANS_FEAT for do_adr
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target/arm: Use TRANS_FEAT for do_predset
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target/arm: Use TRANS_FEAT for RDFFR, WRFFR
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target/arm: Use TRANS_FEAT for do_pfirst_pnext
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target/arm: Use TRANS_FEAT for do_EXT
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target/arm: Use TRANS_FEAT for do_perm_pred3
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target/arm: Use TRANS_FEAT for do_perm_pred2
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target/arm: Move sve zip high_ofs into simd_data
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target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q
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target/arm: Use TRANS_FEAT for do_zip, do_zip_q
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target/arm: Use TRANS_FEAT for do_clast_vector
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target/arm: Use TRANS_FEAT for do_clast_fp
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target/arm: Use TRANS_FEAT for do_clast_general
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target/arm: Use TRANS_FEAT for do_last_fp
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target/arm: Use TRANS_FEAT for do_last_general
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target/arm: Use TRANS_FEAT for SPLICE
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target/arm: Use TRANS_FEAT for do_ppzz_flags
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target/arm: Use TRANS_FEAT for do_sve2_ppzz_flags
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target/arm: Use TRANS_FEAT for do_ppzi_flags
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target/arm: Use TRANS_FEAT for do_brk2, do_brk3
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target/arm: Use TRANS_FEAT for MUL_zzi
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target/arm: Reject dup_i w/ shifted byte early
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target/arm: Reject add/sub w/ shifted byte early
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target/arm: Reject copy w/ shifted byte early
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target/arm: Use TRANS_FEAT for ADD_zzi
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target/arm: Use TRANS_FEAT for do_zzi_sat
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target/arm: Use TRANS_FEAT for do_zzi_ool
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target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz
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target/arm: Use TRANS_FEAT for FMMLA
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target/arm: Move sve check into gen_gvec_fn_ppp
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target/arm: Implement NOT (prediates) alias
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target/arm: Use TRANS_FEAT for SEL_zpzz
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target/arm: Use TRANS_FEAT for MOVPRFX
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target/arm: Use TRANS_FEAT for FMLA
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target/arm: Use TRANS_FEAT for BFMLA
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target/arm: Rename do_zzz_fp to gen_gvec_ool_fpst_arg_zzz
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target/arm: Use TRANS_FEAT for DO_FP3
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target/arm: Use TRANS_FEAT for FMUL_zzx
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target/arm: Use TRANS_FEAT for FTMAD
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target/arm: Move null function and sve check into do_reduce
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target/arm: Use TRANS_FEAT for do_reduce
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target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE
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target/arm: Expand frint_fns for MO_8
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target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz
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target/arm: Move null function and sve check into do_frint_mode
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target/arm: Use TRANS_FEAT for do_frint_mode
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target/arm: Use TRANS_FEAT for FLOGB
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target/arm: Use TRANS_FEAT for do_ppz_fp
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target/arm: Rename do_zpzz_ptr to gen_gvec_fpst_arg_zpzz
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target/arm: Use TRANS_FEAT for gen_gvec_fpst_arg_zpzz
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target/arm: Use TRANS_FEAT for FCADD
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target/arm: Introduce gen_gvec_fpst_zzzzp
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target/arm: Use TRANS_FEAT for gen_gvec_fpst_zzzzp
141
target/arm: Move null function and sve check into do_fp_imm
142
target/arm: Use TRANS_FEAT for DO_FP_IMM
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target/arm: Use TRANS_FEAT for DO_FPCMP
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target/arm: Remove assert in trans_FCMLA_zzxz
145
target/arm: Use TRANS_FEAT for FCMLA_zzxz
146
target/arm: Use TRANS_FEAT for do_narrow_extract
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target/arm: Use TRANS_FEAT for do_shll_tb
148
target/arm: Use TRANS_FEAT for do_shr_narrow
149
target/arm: Use TRANS_FEAT for do_FMLAL_zzzw
150
target/arm: Use TRANS_FEAT for do_FMLAL_zzxw
151
target/arm: Add sve feature check for remaining trans_* functions
152
target/arm: Remove aa64_sve check from before disas_sve
153
154
docs/system/arm/emulation.rst | 1 +
155
target/arm/translate.h | 11 +
156
target/arm/sve.decode | 57 +-
157
hw/sd/allwinner-sdhost.c | 7 +
158
target/arm/hvf/hvf.c | 1 +
159
target/arm/sve_helper.c | 6 +-
160
target/arm/translate-a64.c | 2 +-
161
target/arm/translate-sve.c | 5367 +++++++++++++++--------------------------
162
8 files changed, 2067 insertions(+), 3385 deletions(-)
163
diff view generated by jsdifflib
[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
[PULL 001/117] docs/system/arm: Add FEAT_HCX to list of emulated features
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In commit 5814d587fe861fe9 we added support for emulating
2
FEAT_HCX (Support for the HCRX_EL2 register). However we
3
forgot to add it to the list in emulated.rst. Correct the
4
omission.
2
5
3
This feature is AArch64 only, and applies to physical SErrors,
6
Fixes: 5814d587fe861fe9 ("target/arm: Enable FEAT_HCX for -cpu max")
4
which QEMU does not implement, thus the feature is a nop.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220520084320.424166-1-peter.maydell@linaro.org
10
---
10
---
11
docs/system/arm/emulation.rst | 1 +
11
docs/system/arm/emulation.rst | 1 +
12
target/arm/cpu64.c | 1 +
12
1 file changed, 1 insertion(+)
13
2 files changed, 2 insertions(+)
14
13
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
16
--- a/docs/system/arm/emulation.rst
18
+++ b/docs/system/arm/emulation.rst
17
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
19
- FEAT_FRINTTS (Floating-point to integer instructions)
20
- FEAT_FlagM (Flag manipulation instructions v2)
20
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
21
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
22
+- FEAT_HCX (Support for the HCRX_EL2 register)
21
- FEAT_HPDS (Hierarchical permission disables)
23
- FEAT_HPDS (Hierarchical permission disables)
22
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
24
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
23
+- FEAT_IESB (Implicit error synchronization event)
25
- FEAT_IDST (ID space trap handling)
24
- FEAT_JSCVT (JavaScript conversion instructions)
25
- FEAT_LOR (Limited ordering regions)
26
- FEAT_LPA (Large Physical Address space)
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu64.c
30
+++ b/target/arm/cpu64.c
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
32
t = cpu->isar.id_aa64mmfr2;
33
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
34
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
35
+ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
36
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
37
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
38
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
39
--
26
--
40
2.25.1
27
2.25.1
diff view generated by jsdifflib
[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
[PULL 002/117] target/arm/hvf: Include missing "cpregs.h"
1
From: Gavin Shan <gshan@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The CPU topology isn't enabled on arm/virt machine yet, but we're
3
Fix when building HVF on macOS Aarch64:
4
going to do it in next patch. After the CPU topology is enabled by
5
next patch, "thread-id=1" becomes invalid because the CPU core is
6
preferred on arm/virt machine. It means these two CPUs have 0/1
7
as their core IDs, but their thread IDs are all 0. It will trigger
8
test failure as the following message indicates:
9
4
10
[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR
5
target/arm/hvf/hvf.c:586:15: error: unknown type name 'ARMCPRegInfo'; did you mean 'ARMCPUInfo'?
11
1.48s killed by signal 6 SIGABRT
6
const ARMCPRegInfo *ri;
12
>>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
7
^~~~~~~~~~~~
13
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \
8
ARMCPUInfo
14
QTEST_QEMU_BINARY=./qemu-system-aarch64 \
9
target/arm/cpu-qom.h:38:3: note: 'ARMCPUInfo' declared here
15
QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \
10
} ARMCPUInfo;
16
/home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
11
^
17
――――――――――――――――――――――――――――――――――――――――――――――
12
target/arm/hvf/hvf.c:589:14: error: implicit declaration of function 'get_arm_cp_reginfo' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
18
stderr:
13
ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
19
qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
14
^
15
target/arm/hvf/hvf.c:589:12: warning: incompatible integer to pointer conversion assigning to 'const ARMCPUInfo *' (aka 'const struct ARMCPUInfo *') from 'int' [-Wint-conversion]
16
ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
17
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18
target/arm/hvf/hvf.c:591:26: error: no member named 'type' in 'struct ARMCPUInfo'
19
assert(!(ri->type & ARM_CP_NO_RAW));
20
~~ ^
21
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/usr/include/assert.h:99:25: note: expanded from macro 'assert'
22
(__builtin_expect(!(e), 0) ? __assert_rtn(__func__, __ASSERT_FILE_NAME, __LINE__, #e) : (void)0)
23
^
24
target/arm/hvf/hvf.c:591:33: error: use of undeclared identifier 'ARM_CP_NO_RAW'
25
assert(!(ri->type & ARM_CP_NO_RAW));
26
^
27
1 warning and 4 errors generated.
20
28
21
This fixes the issue by providing comprehensive SMP configurations
29
Fixes: cf7c6d1004 ("target/arm: Split out cpregs.h")
22
in aarch64_numa_cpu(). The SMP configurations aren't used before
30
Reported-by: Duncan Bayne <duncan@bayne.id.au>
23
the CPU topology is enabled in next patch.
31
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
32
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Signed-off-by: Gavin Shan <gshan@redhat.com>
33
Message-id: 20220525161926.34233-1-philmd@fungible.com
26
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
34
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1029
27
Message-id: 20220503140304.855514-3-gshan@redhat.com
35
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
---
37
---
30
tests/qtest/numa-test.c | 3 ++-
38
target/arm/hvf/hvf.c | 1 +
31
1 file changed, 2 insertions(+), 1 deletion(-)
39
1 file changed, 1 insertion(+)
32
40
33
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
41
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
34
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
35
--- a/tests/qtest/numa-test.c
43
--- a/target/arm/hvf/hvf.c
36
+++ b/tests/qtest/numa-test.c
44
+++ b/target/arm/hvf/hvf.c
37
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
45
@@ -XXX,XX +XXX,XX @@
38
QTestState *qts;
46
#include "sysemu/hvf_int.h"
39
g_autofree char *cli = NULL;
47
#include "sysemu/hw_accel.h"
40
48
#include "hvf_arm.h"
41
- cli = make_cli(data, "-machine smp.cpus=2 "
49
+#include "cpregs.h"
42
+ cli = make_cli(data, "-machine "
50
43
+ "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
51
#include <mach/mach_time.h>
44
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
52
45
"-numa cpu,node-id=1,thread-id=0 "
46
"-numa cpu,node-id=0,thread-id=1");
47
--
53
--
48
2.25.1
54
2.25.1
49
55
50
56
diff view generated by jsdifflib
New patch
[PULL 003/117] hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
1
From: Icenowy Zheng <uwu@icenowy.me>
1
2
3
U-Boot queries the FIFO water level to reduce checking status register
4
when doing PIO SD card operation.
5
6
Report a FIFO water level of 1 when data is ready, to prevent the code
7
from trying to read 0 words from the FIFO each time.
8
9
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
10
Message-id: 20220520124200.2112699-1-uwu@icenowy.me
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/sd/allwinner-sdhost.c | 7 +++++++
15
1 file changed, 7 insertions(+)
16
17
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/sd/allwinner-sdhost.c
20
+++ b/hw/sd/allwinner-sdhost.c
21
@@ -XXX,XX +XXX,XX @@ enum {
22
};
23
24
enum {
25
+ SD_STAR_FIFO_EMPTY = (1 << 2),
26
SD_STAR_CARD_PRESENT = (1 << 8),
27
+ SD_STAR_FIFO_LEVEL_1 = (1 << 17),
28
};
29
30
enum {
31
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
32
break;
33
case REG_SD_STAR: /* Status */
34
res = s->status;
35
+ if (sdbus_data_ready(&s->sdbus)) {
36
+ res |= SD_STAR_FIFO_LEVEL_1;
37
+ } else {
38
+ res |= SD_STAR_FIFO_EMPTY;
39
+ }
40
break;
41
case REG_SD_FWLR: /* FIFO Water Level */
42
res = s->fifo_wlevel;
43
--
44
2.25.1
diff view generated by jsdifflib
[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
[PULL 004/117] target/arm: Introduce TRANS, TRANS_FEAT
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This extension concerns not merging memory access, which TCG does
3
Steal the idea for these leaf function expanders from PowerPC.
4
not implement. Thus we can trivially enable this feature.
5
Add a comment to handle_hint for the DGH instruction, but no code.
6
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-2-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
docs/system/arm/emulation.rst | 1 +
10
target/arm/translate.h | 11 +++++++++++
13
target/arm/cpu64.c | 1 +
11
1 file changed, 11 insertions(+)
14
target/arm/translate-a64.c | 1 +
15
3 files changed, 3 insertions(+)
16
12
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
13
diff --git a/target/arm/translate.h b/target/arm/translate.h
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/arm/emulation.rst
15
--- a/target/arm/translate.h
20
+++ b/docs/system/arm/emulation.rst
16
+++ b/target/arm/translate.h
21
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
17
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
18
*/
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
19
uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
24
- FEAT_CSV3 (Cache speculation variant 3)
20
25
+- FEAT_DGH (Data gathering hint)
21
+/*
26
- FEAT_DIT (Data Independent Timing instructions)
22
+ * Helpers for implementing sets of trans_* functions.
27
- FEAT_DPB (DC CVAP instruction)
23
+ * Defer the implementation of NAME to FUNC, with optional extra arguments.
28
- FEAT_Debugv8p2 (Debug changes for v8.2)
24
+ */
29
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
25
+#define TRANS(NAME, FUNC, ...) \
30
index XXXXXXX..XXXXXXX 100644
26
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
31
--- a/target/arm/cpu64.c
27
+ { return FUNC(s, __VA_ARGS__); }
32
+++ b/target/arm/cpu64.c
28
+#define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
29
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
34
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
30
+ { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
35
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
31
+
36
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
32
#endif /* TARGET_ARM_TRANSLATE_H */
37
+ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
38
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
39
cpu->isar.id_aa64isar1 = t;
40
41
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/translate-a64.c
44
+++ b/target/arm/translate-a64.c
45
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
46
break;
47
case 0b00100: /* SEV */
48
case 0b00101: /* SEVL */
49
+ case 0b00110: /* DGH */
50
/* we treat all as NOP at least for now */
51
break;
52
case 0b00111: /* XPACLRI */
53
--
33
--
54
2.25.1
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 005/117] target/arm: Move null function and sve check into gen_gvec_ool_zz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-3-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 36 +++++++++++++++---------------------
9
1 file changed, 15 insertions(+), 21 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
16
}
17
18
/* Invoke an out-of-line helper on 2 Zregs. */
19
-static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
20
+static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
21
int rd, int rn, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vsz, vsz, data, fn);
27
+ if (fn == NULL) {
28
+ return false;
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
33
+ vec_full_reg_offset(s, rn),
34
+ vsz, vsz, data, fn);
35
+ }
36
+ return true;
37
}
38
39
/* Invoke an out-of-line helper on 3 Zregs. */
40
@@ -XXX,XX +XXX,XX @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
41
gen_helper_sve_fexpa_s,
42
gen_helper_sve_fexpa_d,
43
};
44
- if (a->esz == 0) {
45
- return false;
46
- }
47
- if (sve_access_check(s)) {
48
- gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
49
- }
50
- return true;
51
+ return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
52
}
53
54
static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
55
@@ -XXX,XX +XXX,XX @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
56
gen_helper_sve_rev_b, gen_helper_sve_rev_h,
57
gen_helper_sve_rev_s, gen_helper_sve_rev_d
58
};
59
-
60
- if (sve_access_check(s)) {
61
- gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
62
- }
63
- return true;
64
+ return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
65
}
66
67
static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
68
@@ -XXX,XX +XXX,XX @@ static bool trans_AESMC(DisasContext *s, arg_AESMC *a)
69
if (!dc_isar_feature(aa64_sve2_aes, s)) {
70
return false;
71
}
72
- if (sve_access_check(s)) {
73
- gen_gvec_ool_zz(s, gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt);
74
- }
75
- return true;
76
+ return gen_gvec_ool_zz(s, gen_helper_crypto_aesmc,
77
+ a->rd, a->rd, a->decrypt);
78
}
79
80
static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
81
--
82
2.25.1
diff view generated by jsdifflib
New patch
[PULL 006/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_zz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using gen_gvec_ool_zz to TRANS_FEAT.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-4-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 39 +++++++++++++-------------------------
11
1 file changed, 13 insertions(+), 26 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_ADR_u32(DisasContext *s, arg_rrri *a)
18
*** SVE Integer Misc - Unpredicated Group
19
*/
20
21
-static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
22
-{
23
- static gen_helper_gvec_2 * const fns[4] = {
24
- NULL,
25
- gen_helper_sve_fexpa_h,
26
- gen_helper_sve_fexpa_s,
27
- gen_helper_sve_fexpa_d,
28
- };
29
- return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
30
-}
31
+static gen_helper_gvec_2 * const fexpa_fns[4] = {
32
+ NULL, gen_helper_sve_fexpa_h,
33
+ gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
34
+};
35
+TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
36
+ fexpa_fns[a->esz], a->rd, a->rn, 0)
37
38
static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
39
{
40
@@ -XXX,XX +XXX,XX @@ static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a)
41
return true;
42
}
43
44
-static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
45
-{
46
- static gen_helper_gvec_2 * const fns[4] = {
47
- gen_helper_sve_rev_b, gen_helper_sve_rev_h,
48
- gen_helper_sve_rev_s, gen_helper_sve_rev_d
49
- };
50
- return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
51
-}
52
+static gen_helper_gvec_2 * const rev_fns[4] = {
53
+ gen_helper_sve_rev_b, gen_helper_sve_rev_h,
54
+ gen_helper_sve_rev_s, gen_helper_sve_rev_d
55
+};
56
+TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0)
57
58
static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
59
{
60
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
61
return true;
62
}
63
64
-static bool trans_AESMC(DisasContext *s, arg_AESMC *a)
65
-{
66
- if (!dc_isar_feature(aa64_sve2_aes, s)) {
67
- return false;
68
- }
69
- return gen_gvec_ool_zz(s, gen_helper_crypto_aesmc,
70
- a->rd, a->rd, a->decrypt);
71
-}
72
+TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
73
+ gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
74
75
static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
76
{
77
--
78
2.25.1
diff view generated by jsdifflib
New patch
[PULL 007/117] target/arm: Move null function and sve check into gen_gvec_ool_zzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-5-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 74 ++++++++++++--------------------------
9
1 file changed, 23 insertions(+), 51 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 3 Zregs. */
19
-static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
20
+static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
21
int rd, int rn, int rm, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- vsz, vsz, data, fn);
28
+ if (fn == NULL) {
29
+ return false;
30
+ }
31
+ if (sve_access_check(s)) {
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
34
+ vec_full_reg_offset(s, rn),
35
+ vec_full_reg_offset(s, rm),
36
+ vsz, vsz, data, fn);
37
+ }
38
+ return true;
39
}
40
41
/* Invoke an out-of-line helper on 4 Zregs. */
42
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
43
44
static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
45
{
46
- if (fn == NULL) {
47
- return false;
48
- }
49
- if (sve_access_check(s)) {
50
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
54
}
55
56
#define DO_ZZW(NAME, name) \
57
@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
58
59
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
60
{
61
- if (sve_access_check(s)) {
62
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
63
- }
64
- return true;
65
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
66
}
67
68
static bool trans_ADR_p32(DisasContext *s, arg_rrri *a)
69
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
70
gen_helper_sve_ftssel_s,
71
gen_helper_sve_ftssel_d,
72
};
73
- if (a->esz == 0) {
74
- return false;
75
- }
76
- if (sve_access_check(s)) {
77
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
78
- }
79
- return true;
80
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
81
}
82
83
/*
84
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
85
gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
86
gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
87
};
88
-
89
- if (sve_access_check(s)) {
90
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
91
- }
92
- return true;
93
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
94
}
95
96
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
97
@@ -XXX,XX +XXX,XX @@ static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
98
if (!dc_isar_feature(aa64_sve2, s)) {
99
return false;
100
}
101
- if (sve_access_check(s)) {
102
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
103
- }
104
- return true;
105
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
106
}
107
108
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
109
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
110
static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
111
gen_helper_gvec_3 *fn)
112
{
113
- if (sve_access_check(s)) {
114
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
115
- }
116
- return true;
117
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
118
}
119
120
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
121
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
122
static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
123
gen_helper_gvec_3 *fn)
124
{
125
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
126
+ if (!dc_isar_feature(aa64_sve2, s)) {
127
return false;
128
}
129
- if (sve_access_check(s)) {
130
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
131
- }
132
- return true;
133
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
134
}
135
136
static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
137
@@ -XXX,XX +XXX,XX @@ static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
138
if (!dc_isar_feature(aa64_sve2_aes, s)) {
139
return false;
140
}
141
- if (sve_access_check(s)) {
142
- gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
143
- a->rd, a->rn, a->rm, decrypt);
144
- }
145
- return true;
146
+ return gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
147
+ a->rd, a->rn, a->rm, decrypt);
148
}
149
150
static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
151
@@ -XXX,XX +XXX,XX @@ static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
152
if (!dc_isar_feature(aa64_sve2_sm4, s)) {
153
return false;
154
}
155
- if (sve_access_check(s)) {
156
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
157
- }
158
- return true;
159
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
160
}
161
162
static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
163
--
164
2.25.1
diff view generated by jsdifflib
New patch
[PULL 008/117] target/arm: Introduce gen_gvec_ool_arg_zzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use gen_gvec_ool_arg_zzz instead of gen_gvec_ool_zzz
4
when the arguments come from arg_rrr_esz.
5
Replaces do_zzw_ool and do_zzz_data_ool.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-6-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 48 +++++++++++++++++---------------------
13
1 file changed, 21 insertions(+), 27 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
20
return true;
21
}
22
23
+static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
24
+ arg_rrr_esz *a, int data)
25
+{
26
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
27
+}
28
+
29
/* Invoke an out-of-line helper on 4 Zregs. */
30
static void gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
31
int rd, int rn, int rm, int ra, int data)
32
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
33
return do_shift_imm(s, a, false, tcg_gen_gvec_shli);
34
}
35
36
-static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
37
-{
38
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
39
-}
40
-
41
#define DO_ZZW(NAME, name) \
42
static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
43
{ \
44
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
45
gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \
46
gen_helper_sve_##name##_zzw_s, NULL \
47
}; \
48
- return do_zzw_ool(s, a, fns[a->esz]); \
49
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0); \
50
}
51
52
DO_ZZW(ASR, asr)
53
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
54
gen_helper_sve_ftssel_s,
55
gen_helper_sve_ftssel_d,
56
};
57
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
58
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
59
}
60
61
/*
62
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
63
gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
64
gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
65
};
66
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
67
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
68
}
69
70
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
71
@@ -XXX,XX +XXX,XX @@ static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
72
if (!dc_isar_feature(aa64_sve2, s)) {
73
return false;
74
}
75
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
76
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
77
}
78
79
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
80
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
81
return true;
82
}
83
84
-static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
85
- gen_helper_gvec_3 *fn)
86
-{
87
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
88
-}
89
-
90
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
91
{
92
return do_zip(s, a, false);
93
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const uzp_fns[4] = {
94
95
static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a)
96
{
97
- return do_zzz_data_ool(s, a, 0, uzp_fns[a->esz]);
98
+ return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 0);
99
}
100
101
static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a)
102
{
103
- return do_zzz_data_ool(s, a, 1 << a->esz, uzp_fns[a->esz]);
104
+ return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 1 << a->esz);
105
}
106
107
static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
108
@@ -XXX,XX +XXX,XX @@ static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
109
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
110
return false;
111
}
112
- return do_zzz_data_ool(s, a, 0, gen_helper_sve2_uzp_q);
113
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 0);
114
}
115
116
static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
117
@@ -XXX,XX +XXX,XX @@ static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
118
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
119
return false;
120
}
121
- return do_zzz_data_ool(s, a, 16, gen_helper_sve2_uzp_q);
122
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 16);
123
}
124
125
static gen_helper_gvec_3 * const trn_fns[4] = {
126
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const trn_fns[4] = {
127
128
static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a)
129
{
130
- return do_zzz_data_ool(s, a, 0, trn_fns[a->esz]);
131
+ return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 0);
132
}
133
134
static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a)
135
{
136
- return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]);
137
+ return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 1 << a->esz);
138
}
139
140
static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
141
@@ -XXX,XX +XXX,XX @@ static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
142
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
143
return false;
144
}
145
- return do_zzz_data_ool(s, a, 0, gen_helper_sve2_trn_q);
146
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 0);
147
}
148
149
static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
150
@@ -XXX,XX +XXX,XX @@ static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
151
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
152
return false;
153
}
154
- return do_zzz_data_ool(s, a, 16, gen_helper_sve2_trn_q);
155
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 16);
156
}
157
158
/*
159
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
160
if (!dc_isar_feature(aa64_sve2, s)) {
161
return false;
162
}
163
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
164
+ return gen_gvec_ool_arg_zzz(s, fn, a, 0);
165
}
166
167
static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
168
@@ -XXX,XX +XXX,XX @@ static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
169
if (!dc_isar_feature(aa64_sve2_aes, s)) {
170
return false;
171
}
172
- return gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
173
- a->rd, a->rn, a->rm, decrypt);
174
+ return gen_gvec_ool_arg_zzz(s, gen_helper_crypto_aese, a, decrypt);
175
}
176
177
static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
178
@@ -XXX,XX +XXX,XX @@ static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
179
if (!dc_isar_feature(aa64_sve2_sm4, s)) {
180
return false;
181
}
182
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
183
+ return gen_gvec_ool_arg_zzz(s, fn, a, 0);
184
}
185
186
static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
187
--
188
2.25.1
diff view generated by jsdifflib
New patch
[PULL 009/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Convert SVE translation functions using
4
gen_gvec_ool_arg_zzz to TRANS_FEAT.
5
6
Remove trivial wrappers do_aese, do_sm4.
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220527181907.189259-7-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate-sve.c | 165 ++++++++++---------------------------
14
1 file changed, 45 insertions(+), 120 deletions(-)
15
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
21
}
22
23
#define DO_ZZW(NAME, name) \
24
-static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
25
-{ \
26
- static gen_helper_gvec_3 * const fns[4] = { \
27
+ static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \
28
gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \
29
gen_helper_sve_##name##_zzw_s, NULL \
30
}; \
31
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0); \
32
-}
33
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_arg_zzz, \
34
+ name##_zzw_fns[a->esz], a, 0)
35
36
-DO_ZZW(ASR, asr)
37
-DO_ZZW(LSR, lsr)
38
-DO_ZZW(LSL, lsl)
39
+DO_ZZW(ASR_zzw, asr)
40
+DO_ZZW(LSR_zzw, lsr)
41
+DO_ZZW(LSL_zzw, lsl)
42
43
#undef DO_ZZW
44
45
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const fexpa_fns[4] = {
46
TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
47
fexpa_fns[a->esz], a->rd, a->rn, 0)
48
49
-static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
50
-{
51
- static gen_helper_gvec_3 * const fns[4] = {
52
- NULL,
53
- gen_helper_sve_ftssel_h,
54
- gen_helper_sve_ftssel_s,
55
- gen_helper_sve_ftssel_d,
56
- };
57
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
58
-}
59
+static gen_helper_gvec_3 * const ftssel_fns[4] = {
60
+ NULL, gen_helper_sve_ftssel_h,
61
+ gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d,
62
+};
63
+TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0)
64
65
/*
66
*** SVE Predicate Logical Operations Group
67
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const rev_fns[4] = {
68
};
69
TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0)
70
71
-static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
72
-{
73
- static gen_helper_gvec_3 * const fns[4] = {
74
- gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
75
- gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
76
- };
77
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
78
-}
79
+static gen_helper_gvec_3 * const sve_tbl_fns[4] = {
80
+ gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
81
+ gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
82
+};
83
+TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0)
84
85
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
86
{
87
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
88
return true;
89
}
90
91
-static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
92
-{
93
- static gen_helper_gvec_3 * const fns[4] = {
94
- gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
95
- gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d
96
- };
97
-
98
- if (!dc_isar_feature(aa64_sve2, s)) {
99
- return false;
100
- }
101
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
102
-}
103
+static gen_helper_gvec_3 * const tbx_fns[4] = {
104
+ gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
105
+ gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d
106
+};
107
+TRANS_FEAT(TBX, aa64_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a, 0)
108
109
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
110
{
111
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const uzp_fns[4] = {
112
gen_helper_sve_uzp_s, gen_helper_sve_uzp_d,
113
};
114
115
-static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a)
116
-{
117
- return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 0);
118
-}
119
+TRANS_FEAT(UZP1_z, aa64_sve, gen_gvec_ool_arg_zzz,
120
+ uzp_fns[a->esz], a, 0)
121
+TRANS_FEAT(UZP2_z, aa64_sve, gen_gvec_ool_arg_zzz,
122
+ uzp_fns[a->esz], a, 1 << a->esz)
123
124
-static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a)
125
-{
126
- return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 1 << a->esz);
127
-}
128
-
129
-static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
130
-{
131
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
132
- return false;
133
- }
134
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 0);
135
-}
136
-
137
-static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
138
-{
139
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
140
- return false;
141
- }
142
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 16);
143
-}
144
+TRANS_FEAT(UZP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
145
+ gen_helper_sve2_uzp_q, a, 0)
146
+TRANS_FEAT(UZP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
147
+ gen_helper_sve2_uzp_q, a, 16)
148
149
static gen_helper_gvec_3 * const trn_fns[4] = {
150
gen_helper_sve_trn_b, gen_helper_sve_trn_h,
151
gen_helper_sve_trn_s, gen_helper_sve_trn_d,
152
};
153
154
-static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a)
155
-{
156
- return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 0);
157
-}
158
+TRANS_FEAT(TRN1_z, aa64_sve, gen_gvec_ool_arg_zzz,
159
+ trn_fns[a->esz], a, 0)
160
+TRANS_FEAT(TRN2_z, aa64_sve, gen_gvec_ool_arg_zzz,
161
+ trn_fns[a->esz], a, 1 << a->esz)
162
163
-static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a)
164
-{
165
- return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 1 << a->esz);
166
-}
167
-
168
-static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
169
-{
170
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
171
- return false;
172
- }
173
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 0);
174
-}
175
-
176
-static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
177
-{
178
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
179
- return false;
180
- }
181
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 16);
182
-}
183
+TRANS_FEAT(TRN1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
184
+ gen_helper_sve2_trn_q, a, 0)
185
+TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
186
+ gen_helper_sve2_trn_q, a, 16)
187
188
/*
189
*** SVE Permute Vector - Predicated Group
190
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
191
TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
192
gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
193
194
-static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
195
-{
196
- if (!dc_isar_feature(aa64_sve2_aes, s)) {
197
- return false;
198
- }
199
- return gen_gvec_ool_arg_zzz(s, gen_helper_crypto_aese, a, decrypt);
200
-}
201
+TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
202
+ gen_helper_crypto_aese, a, false)
203
+TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
204
+ gen_helper_crypto_aese, a, true)
205
206
-static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
207
-{
208
- return do_aese(s, a, false);
209
-}
210
-
211
-static bool trans_AESD(DisasContext *s, arg_rrr_esz *a)
212
-{
213
- return do_aese(s, a, true);
214
-}
215
-
216
-static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
217
-{
218
- if (!dc_isar_feature(aa64_sve2_sm4, s)) {
219
- return false;
220
- }
221
- return gen_gvec_ool_arg_zzz(s, fn, a, 0);
222
-}
223
-
224
-static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
225
-{
226
- return do_sm4(s, a, gen_helper_crypto_sm4e);
227
-}
228
-
229
-static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
230
-{
231
- return do_sm4(s, a, gen_helper_crypto_sm4ekey);
232
-}
233
+TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
234
+ gen_helper_crypto_sm4e, a, 0)
235
+TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
236
+ gen_helper_crypto_sm4ekey, a, 0)
237
238
static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
239
{
240
--
241
2.25.1
diff view generated by jsdifflib
New patch
[PULL 010/117] target/arm: Use TRANS_FEAT for do_sve2_zzz_ool
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-8-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 88 ++++++++++++++------------------------
12
1 file changed, 31 insertions(+), 57 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
19
return true;
20
}
21
22
-static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
23
- gen_helper_gvec_3 *fn)
24
-{
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zzz(s, fn, a, 0);
29
-}
30
+static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
31
+ gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
32
+ gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d,
33
+};
34
+TRANS_FEAT(SMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
35
+ smulh_zzz_fns[a->esz], a, 0)
36
37
-static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
38
-{
39
- static gen_helper_gvec_3 * const fns[4] = {
40
- gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
41
- gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d,
42
- };
43
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
44
-}
45
+static gen_helper_gvec_3 * const umulh_zzz_fns[4] = {
46
+ gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h,
47
+ gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d,
48
+};
49
+TRANS_FEAT(UMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
50
+ umulh_zzz_fns[a->esz], a, 0)
51
52
-static bool trans_UMULH_zzz(DisasContext *s, arg_rrr_esz *a)
53
-{
54
- static gen_helper_gvec_3 * const fns[4] = {
55
- gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h,
56
- gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d,
57
- };
58
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
59
-}
60
+TRANS_FEAT(PMUL_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
61
+ gen_helper_gvec_pmul_b, a, 0)
62
63
-static bool trans_PMUL_zzz(DisasContext *s, arg_rrr_esz *a)
64
-{
65
- return do_sve2_zzz_ool(s, a, gen_helper_gvec_pmul_b);
66
-}
67
+static gen_helper_gvec_3 * const sqdmulh_zzz_fns[4] = {
68
+ gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h,
69
+ gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d,
70
+};
71
+TRANS_FEAT(SQDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
72
+ sqdmulh_zzz_fns[a->esz], a, 0)
73
74
-static bool trans_SQDMULH_zzz(DisasContext *s, arg_rrr_esz *a)
75
-{
76
- static gen_helper_gvec_3 * const fns[4] = {
77
- gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h,
78
- gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d,
79
- };
80
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
81
-}
82
-
83
-static bool trans_SQRDMULH_zzz(DisasContext *s, arg_rrr_esz *a)
84
-{
85
- static gen_helper_gvec_3 * const fns[4] = {
86
- gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h,
87
- gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d,
88
- };
89
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
90
-}
91
+static gen_helper_gvec_3 * const sqrdmulh_zzz_fns[4] = {
92
+ gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h,
93
+ gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d,
94
+};
95
+TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
96
+ sqrdmulh_zzz_fns[a->esz], a, 0)
97
98
/*
99
* SVE2 Integer - Predicated
100
@@ -XXX,XX +XXX,XX @@ static bool trans_UQRSHRNT(DisasContext *s, arg_rri_esz *a)
101
}
102
103
#define DO_SVE2_ZZZ_NARROW(NAME, name) \
104
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
105
-{ \
106
- static gen_helper_gvec_3 * const fns[4] = { \
107
+ static gen_helper_gvec_3 * const name##_fns[4] = { \
108
NULL, gen_helper_sve2_##name##_h, \
109
gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
110
}; \
111
- return do_sve2_zzz_ool(s, a, fns[a->esz]); \
112
-}
113
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzz, \
114
+ name##_fns[a->esz], a, 0)
115
116
DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb)
117
DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_HISTCNT(DisasContext *s, arg_rprr_esz *a)
119
return do_sve2_zpzz_ool(s, a, fns[a->esz - 2]);
120
}
121
122
-static bool trans_HISTSEG(DisasContext *s, arg_rrr_esz *a)
123
-{
124
- if (a->esz != 0) {
125
- return false;
126
- }
127
- return do_sve2_zzz_ool(s, a, gen_helper_sve2_histseg);
128
-}
129
+TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
130
+ a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
131
132
static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
133
gen_helper_gvec_4_ptr *fn)
134
--
135
2.25.1
diff view generated by jsdifflib
New patch
[PULL 011/117] target/arm: Move null function and sve check into gen_gvec_ool_zzzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-9-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 102 ++++++++++++++-----------------------
9
1 file changed, 38 insertions(+), 64 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 4 Zregs. */
19
-static void gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
20
+static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
21
int rd, int rn, int rm, int ra, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- vec_full_reg_offset(s, ra),
28
- vsz, vsz, data, fn);
29
+ if (fn == NULL) {
30
+ return false;
31
+ }
32
+ if (sve_access_check(s)) {
33
+ unsigned vsz = vec_full_reg_size(s);
34
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
35
+ vec_full_reg_offset(s, rn),
36
+ vec_full_reg_offset(s, rm),
37
+ vec_full_reg_offset(s, ra),
38
+ vsz, vsz, data, fn);
39
+ }
40
+ return true;
41
}
42
43
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
44
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
45
if (!dc_isar_feature(aa64_sve2, s)) {
46
return false;
47
}
48
- if (sve_access_check(s)) {
49
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
50
- (a->rn + 1) % 32, a->rm, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
54
+ (a->rn + 1) % 32, a->rm, 0);
55
}
56
57
static gen_helper_gvec_3 * const tbx_fns[4] = {
58
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
59
{ gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
60
{ gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
61
};
62
-
63
- if (sve_access_check(s)) {
64
- gen_gvec_ool_zzzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0);
65
- }
66
- return true;
67
+ return gen_gvec_ool_zzzz(s, fns[a->u][a->sz],
68
+ a->rd, a->rn, a->rm, a->ra, 0);
69
}
70
71
/*
72
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
73
static bool do_zzxz_ool(DisasContext *s, arg_rrxr_esz *a,
74
gen_helper_gvec_4 *fn)
75
{
76
- if (fn == NULL) {
77
- return false;
78
- }
79
- if (sve_access_check(s)) {
80
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
81
- }
82
- return true;
83
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
84
}
85
86
#define DO_RRXR(NAME, FUNC) \
87
@@ -XXX,XX +XXX,XX @@ static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
88
static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
89
gen_helper_gvec_4 *fn, int data)
90
{
91
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
92
+ if (!dc_isar_feature(aa64_sve2, s)) {
93
return false;
94
}
95
- if (sve_access_check(s)) {
96
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
97
- }
98
- return true;
99
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
100
}
101
102
static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
103
@@ -XXX,XX +XXX,XX @@ static bool trans_CMLA_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
104
if (!dc_isar_feature(aa64_sve2, s)) {
105
return false;
106
}
107
- if (sve_access_check(s)) {
108
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot);
109
- }
110
- return true;
111
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
112
+ a->rm, a->ra, a->rot);
113
}
114
115
static bool trans_CDOT_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
116
{
117
- if (!dc_isar_feature(aa64_sve2, s) || a->esz < MO_32) {
118
+ static gen_helper_gvec_4 * const fns[] = {
119
+ NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
120
+ };
121
+
122
+ if (!dc_isar_feature(aa64_sve2, s)) {
123
return false;
124
}
125
- if (sve_access_check(s)) {
126
- gen_helper_gvec_4 *fn = (a->esz == MO_32
127
- ? gen_helper_sve2_cdot_zzzz_s
128
- : gen_helper_sve2_cdot_zzzz_d);
129
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->rot);
130
- }
131
- return true;
132
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
133
+ a->rm, a->ra, a->rot);
134
}
135
136
static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
137
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
138
if (!dc_isar_feature(aa64_sve2, s)) {
139
return false;
140
}
141
- if (sve_access_check(s)) {
142
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot);
143
- }
144
- return true;
145
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
146
+ a->rm, a->ra, a->rot);
147
}
148
149
static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
150
@@ -XXX,XX +XXX,XX @@ static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
151
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
152
return false;
153
}
154
- if (sve_access_check(s)) {
155
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
156
- }
157
- return true;
158
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
159
}
160
161
static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
162
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
163
if (!dc_isar_feature(aa64_sve_bf16, s)) {
164
return false;
165
}
166
- if (sve_access_check(s)) {
167
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
168
- a->rd, a->rn, a->rm, a->ra, 0);
169
- }
170
- return true;
171
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
172
+ a->rd, a->rn, a->rm, a->ra, 0);
173
}
174
175
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
176
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
177
if (!dc_isar_feature(aa64_sve_bf16, s)) {
178
return false;
179
}
180
- if (sve_access_check(s)) {
181
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
182
- a->rd, a->rn, a->rm, a->ra, a->index);
183
- }
184
- return true;
185
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
186
+ a->rd, a->rn, a->rm, a->ra, a->index);
187
}
188
189
static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
190
@@ -XXX,XX +XXX,XX @@ static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
191
if (!dc_isar_feature(aa64_sve_bf16, s)) {
192
return false;
193
}
194
- if (sve_access_check(s)) {
195
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
196
- a->rd, a->rn, a->rm, a->ra, 0);
197
- }
198
- return true;
199
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
200
+ a->rd, a->rn, a->rm, a->ra, 0);
201
}
202
203
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
204
--
205
2.25.1
diff view generated by jsdifflib
New patch
[PULL 012/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_zzzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-10-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 89 +++++++++++++-------------------------
12
1 file changed, 29 insertions(+), 60 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const sve_tbl_fns[4] = {
19
};
20
TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0)
21
22
-static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
23
-{
24
- static gen_helper_gvec_4 * const fns[4] = {
25
- gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h,
26
- gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d
27
- };
28
-
29
- if (!dc_isar_feature(aa64_sve2, s)) {
30
- return false;
31
- }
32
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
33
- (a->rn + 1) % 32, a->rm, 0);
34
-}
35
+static gen_helper_gvec_4 * const sve2_tbl_fns[4] = {
36
+ gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h,
37
+ gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d
38
+};
39
+TRANS_FEAT(TBL_sve2, aa64_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->esz],
40
+ a->rd, a->rn, (a->rn + 1) % 32, a->rm, 0)
41
42
static gen_helper_gvec_3 * const tbx_fns[4] = {
43
gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
44
@@ -XXX,XX +XXX,XX @@ DO_ZZI(UMIN, umin)
45
46
#undef DO_ZZI
47
48
-static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
49
-{
50
- static gen_helper_gvec_4 * const fns[2][2] = {
51
- { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
52
- { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
53
- };
54
- return gen_gvec_ool_zzzz(s, fns[a->u][a->sz],
55
- a->rd, a->rn, a->rm, a->ra, 0);
56
-}
57
+static gen_helper_gvec_4 * const dot_fns[2][2] = {
58
+ { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
59
+ { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
60
+};
61
+TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
62
+ dot_fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0)
63
64
/*
65
* SVE Multiply - Indexed
66
@@ -XXX,XX +XXX,XX @@ static bool trans_UMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
67
return do_umlsl_zzzw(s, a, true);
68
}
69
70
-static bool trans_CMLA_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
71
-{
72
- static gen_helper_gvec_4 * const fns[] = {
73
- gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
74
- gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d,
75
- };
76
+static gen_helper_gvec_4 * const cmla_fns[] = {
77
+ gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
78
+ gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d,
79
+};
80
+TRANS_FEAT(CMLA_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
81
+ cmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
82
83
- if (!dc_isar_feature(aa64_sve2, s)) {
84
- return false;
85
- }
86
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
87
- a->rm, a->ra, a->rot);
88
-}
89
+static gen_helper_gvec_4 * const cdot_fns[] = {
90
+ NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
91
+};
92
+TRANS_FEAT(CDOT_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
93
+ cdot_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
94
95
-static bool trans_CDOT_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
96
-{
97
- static gen_helper_gvec_4 * const fns[] = {
98
- NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
99
- };
100
-
101
- if (!dc_isar_feature(aa64_sve2, s)) {
102
- return false;
103
- }
104
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
105
- a->rm, a->ra, a->rot);
106
-}
107
-
108
-static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
109
-{
110
- static gen_helper_gvec_4 * const fns[] = {
111
- gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h,
112
- gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d,
113
- };
114
-
115
- if (!dc_isar_feature(aa64_sve2, s)) {
116
- return false;
117
- }
118
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
119
- a->rm, a->ra, a->rot);
120
-}
121
+static gen_helper_gvec_4 * const sqrdcmlah_fns[] = {
122
+ gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h,
123
+ gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d,
124
+};
125
+TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
126
+ sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
127
128
static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
129
{
130
--
131
2.25.1
diff view generated by jsdifflib
New patch
[PULL 013/117] target/arm: Introduce gen_gvec_ool_arg_zzzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use gen_gvec_ool_arg_zzzz instead of gen_gvec_ool_zzzz
4
when the arguments come from arg_rrrr_esz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-11-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 16 ++++++++++------
12
1 file changed, 10 insertions(+), 6 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
19
return true;
20
}
21
22
+static bool gen_gvec_ool_arg_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
23
+ arg_rrrr_esz *a, int data)
24
+{
25
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
26
+}
27
+
28
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
29
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
30
int rd, int rn, int pg, int data)
31
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
32
if (!dc_isar_feature(aa64_sve2, s)) {
33
return false;
34
}
35
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
36
+ return gen_gvec_ool_arg_zzzz(s, fn, a, data);
37
}
38
39
static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
40
@@ -XXX,XX +XXX,XX @@ static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
41
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
42
return false;
43
}
44
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
45
+ return gen_gvec_ool_arg_zzzz(s, fn, a, data);
46
}
47
48
static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
49
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
50
if (!dc_isar_feature(aa64_sve_bf16, s)) {
51
return false;
52
}
53
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
54
- a->rd, a->rn, a->rm, a->ra, 0);
55
+ return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfdot, a, 0);
56
}
57
58
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
59
@@ -XXX,XX +XXX,XX @@ static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
60
if (!dc_isar_feature(aa64_sve_bf16, s)) {
61
return false;
62
}
63
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
64
- a->rd, a->rn, a->rm, a->ra, 0);
65
+ return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfmmla, a, 0);
66
}
67
68
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
69
--
70
2.25.1
diff view generated by jsdifflib
New patch
[PULL 014/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zzzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-12-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 263 +++++++++++--------------------------
12
1 file changed, 79 insertions(+), 184 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
19
return do_cadd(s, a, true, true);
20
}
21
22
-static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
23
- gen_helper_gvec_4 *fn, int data)
24
-{
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zzzz(s, fn, a, data);
29
-}
30
+static gen_helper_gvec_4 * const sabal_fns[4] = {
31
+ NULL, gen_helper_sve2_sabal_h,
32
+ gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d,
33
+};
34
+TRANS_FEAT(SABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 0)
35
+TRANS_FEAT(SABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 1)
36
37
-static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
38
-{
39
- static gen_helper_gvec_4 * const fns[2][4] = {
40
- { NULL, gen_helper_sve2_sabal_h,
41
- gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d },
42
- { NULL, gen_helper_sve2_uabal_h,
43
- gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d },
44
- };
45
- return do_sve2_zzzz_ool(s, a, fns[uns][a->esz], sel);
46
-}
47
-
48
-static bool trans_SABALB(DisasContext *s, arg_rrrr_esz *a)
49
-{
50
- return do_abal(s, a, false, false);
51
-}
52
-
53
-static bool trans_SABALT(DisasContext *s, arg_rrrr_esz *a)
54
-{
55
- return do_abal(s, a, false, true);
56
-}
57
-
58
-static bool trans_UABALB(DisasContext *s, arg_rrrr_esz *a)
59
-{
60
- return do_abal(s, a, true, false);
61
-}
62
-
63
-static bool trans_UABALT(DisasContext *s, arg_rrrr_esz *a)
64
-{
65
- return do_abal(s, a, true, true);
66
-}
67
+static gen_helper_gvec_4 * const uabal_fns[4] = {
68
+ NULL, gen_helper_sve2_uabal_h,
69
+ gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d,
70
+};
71
+TRANS_FEAT(UABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 0)
72
+TRANS_FEAT(UABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 1)
73
74
static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
75
{
76
@@ -XXX,XX +XXX,XX @@ static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
77
* Note that in this case the ESZ field encodes both size and sign.
78
* Split out 'subtract' into bit 1 of the data field for the helper.
79
*/
80
- return do_sve2_zzzz_ool(s, a, fns[a->esz & 1], (a->esz & 2) | sel);
81
+ return gen_gvec_ool_arg_zzzz(s, fns[a->esz & 1], a, (a->esz & 2) | sel);
82
}
83
84
-static bool trans_ADCLB(DisasContext *s, arg_rrrr_esz *a)
85
-{
86
- return do_adcl(s, a, false);
87
-}
88
-
89
-static bool trans_ADCLT(DisasContext *s, arg_rrrr_esz *a)
90
-{
91
- return do_adcl(s, a, true);
92
-}
93
+TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false)
94
+TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
95
96
static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
97
{
98
@@ -XXX,XX +XXX,XX @@ static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
99
return true;
100
}
101
102
-static bool do_sqdmlal_zzzw(DisasContext *s, arg_rrrr_esz *a,
103
- bool sel1, bool sel2)
104
-{
105
- static gen_helper_gvec_4 * const fns[] = {
106
- NULL, gen_helper_sve2_sqdmlal_zzzw_h,
107
- gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d,
108
- };
109
- return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1);
110
-}
111
+static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
112
+ NULL, gen_helper_sve2_sqdmlal_zzzw_h,
113
+ gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d,
114
+};
115
+TRANS_FEAT(SQDMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
116
+ sqdmlal_zzzw_fns[a->esz], a, 0)
117
+TRANS_FEAT(SQDMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
118
+ sqdmlal_zzzw_fns[a->esz], a, 3)
119
+TRANS_FEAT(SQDMLALBT, aa64_sve2, gen_gvec_ool_arg_zzzz,
120
+ sqdmlal_zzzw_fns[a->esz], a, 2)
121
122
-static bool do_sqdmlsl_zzzw(DisasContext *s, arg_rrrr_esz *a,
123
- bool sel1, bool sel2)
124
-{
125
- static gen_helper_gvec_4 * const fns[] = {
126
- NULL, gen_helper_sve2_sqdmlsl_zzzw_h,
127
- gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d,
128
- };
129
- return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1);
130
-}
131
+static gen_helper_gvec_4 * const sqdmlsl_zzzw_fns[] = {
132
+ NULL, gen_helper_sve2_sqdmlsl_zzzw_h,
133
+ gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d,
134
+};
135
+TRANS_FEAT(SQDMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
136
+ sqdmlsl_zzzw_fns[a->esz], a, 0)
137
+TRANS_FEAT(SQDMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
138
+ sqdmlsl_zzzw_fns[a->esz], a, 3)
139
+TRANS_FEAT(SQDMLSLBT, aa64_sve2, gen_gvec_ool_arg_zzzz,
140
+ sqdmlsl_zzzw_fns[a->esz], a, 2)
141
142
-static bool trans_SQDMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
143
-{
144
- return do_sqdmlal_zzzw(s, a, false, false);
145
-}
146
+static gen_helper_gvec_4 * const sqrdmlah_fns[] = {
147
+ gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h,
148
+ gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d,
149
+};
150
+TRANS_FEAT(SQRDMLAH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz,
151
+ sqrdmlah_fns[a->esz], a, 0)
152
153
-static bool trans_SQDMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
154
-{
155
- return do_sqdmlal_zzzw(s, a, true, true);
156
-}
157
+static gen_helper_gvec_4 * const sqrdmlsh_fns[] = {
158
+ gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h,
159
+ gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d,
160
+};
161
+TRANS_FEAT(SQRDMLSH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz,
162
+ sqrdmlsh_fns[a->esz], a, 0)
163
164
-static bool trans_SQDMLALBT(DisasContext *s, arg_rrrr_esz *a)
165
-{
166
- return do_sqdmlal_zzzw(s, a, false, true);
167
-}
168
+static gen_helper_gvec_4 * const smlal_zzzw_fns[] = {
169
+ NULL, gen_helper_sve2_smlal_zzzw_h,
170
+ gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d,
171
+};
172
+TRANS_FEAT(SMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
173
+ smlal_zzzw_fns[a->esz], a, 0)
174
+TRANS_FEAT(SMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
175
+ smlal_zzzw_fns[a->esz], a, 1)
176
177
-static bool trans_SQDMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
178
-{
179
- return do_sqdmlsl_zzzw(s, a, false, false);
180
-}
181
+static gen_helper_gvec_4 * const umlal_zzzw_fns[] = {
182
+ NULL, gen_helper_sve2_umlal_zzzw_h,
183
+ gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d,
184
+};
185
+TRANS_FEAT(UMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
186
+ umlal_zzzw_fns[a->esz], a, 0)
187
+TRANS_FEAT(UMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
188
+ umlal_zzzw_fns[a->esz], a, 1)
189
190
-static bool trans_SQDMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
191
-{
192
- return do_sqdmlsl_zzzw(s, a, true, true);
193
-}
194
+static gen_helper_gvec_4 * const smlsl_zzzw_fns[] = {
195
+ NULL, gen_helper_sve2_smlsl_zzzw_h,
196
+ gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d,
197
+};
198
+TRANS_FEAT(SMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
199
+ smlsl_zzzw_fns[a->esz], a, 0)
200
+TRANS_FEAT(SMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
201
+ smlsl_zzzw_fns[a->esz], a, 1)
202
203
-static bool trans_SQDMLSLBT(DisasContext *s, arg_rrrr_esz *a)
204
-{
205
- return do_sqdmlsl_zzzw(s, a, false, true);
206
-}
207
-
208
-static bool trans_SQRDMLAH_zzzz(DisasContext *s, arg_rrrr_esz *a)
209
-{
210
- static gen_helper_gvec_4 * const fns[] = {
211
- gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h,
212
- gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d,
213
- };
214
- return do_sve2_zzzz_ool(s, a, fns[a->esz], 0);
215
-}
216
-
217
-static bool trans_SQRDMLSH_zzzz(DisasContext *s, arg_rrrr_esz *a)
218
-{
219
- static gen_helper_gvec_4 * const fns[] = {
220
- gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h,
221
- gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d,
222
- };
223
- return do_sve2_zzzz_ool(s, a, fns[a->esz], 0);
224
-}
225
-
226
-static bool do_smlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
227
-{
228
- static gen_helper_gvec_4 * const fns[] = {
229
- NULL, gen_helper_sve2_smlal_zzzw_h,
230
- gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d,
231
- };
232
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
233
-}
234
-
235
-static bool trans_SMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
236
-{
237
- return do_smlal_zzzw(s, a, false);
238
-}
239
-
240
-static bool trans_SMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
241
-{
242
- return do_smlal_zzzw(s, a, true);
243
-}
244
-
245
-static bool do_umlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
246
-{
247
- static gen_helper_gvec_4 * const fns[] = {
248
- NULL, gen_helper_sve2_umlal_zzzw_h,
249
- gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d,
250
- };
251
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
252
-}
253
-
254
-static bool trans_UMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
255
-{
256
- return do_umlal_zzzw(s, a, false);
257
-}
258
-
259
-static bool trans_UMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
260
-{
261
- return do_umlal_zzzw(s, a, true);
262
-}
263
-
264
-static bool do_smlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
265
-{
266
- static gen_helper_gvec_4 * const fns[] = {
267
- NULL, gen_helper_sve2_smlsl_zzzw_h,
268
- gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d,
269
- };
270
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
271
-}
272
-
273
-static bool trans_SMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
274
-{
275
- return do_smlsl_zzzw(s, a, false);
276
-}
277
-
278
-static bool trans_SMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
279
-{
280
- return do_smlsl_zzzw(s, a, true);
281
-}
282
-
283
-static bool do_umlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
284
-{
285
- static gen_helper_gvec_4 * const fns[] = {
286
- NULL, gen_helper_sve2_umlsl_zzzw_h,
287
- gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d,
288
- };
289
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
290
-}
291
-
292
-static bool trans_UMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
293
-{
294
- return do_umlsl_zzzw(s, a, false);
295
-}
296
-
297
-static bool trans_UMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
298
-{
299
- return do_umlsl_zzzw(s, a, true);
300
-}
301
+static gen_helper_gvec_4 * const umlsl_zzzw_fns[] = {
302
+ NULL, gen_helper_sve2_umlsl_zzzw_h,
303
+ gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d,
304
+};
305
+TRANS_FEAT(UMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
306
+ umlsl_zzzw_fns[a->esz], a, 0)
307
+TRANS_FEAT(UMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
308
+ umlsl_zzzw_fns[a->esz], a, 1)
309
310
static gen_helper_gvec_4 * const cmla_fns[] = {
311
gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
312
--
313
2.25.1
diff view generated by jsdifflib
New patch
[PULL 015/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zzzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-13-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 47 ++++++++------------------------------
12
1 file changed, 10 insertions(+), 37 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_FMLSLT_zzxw(DisasContext *s, arg_rrxr_esz *a)
19
return do_FMLAL_zzxw(s, a, true, true);
20
}
21
22
-static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
23
- gen_helper_gvec_4 *fn, int data)
24
-{
25
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zzzz(s, fn, a, data);
29
-}
30
+TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
31
+ gen_helper_gvec_smmla_b, a, 0)
32
+TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
33
+ gen_helper_gvec_usmmla_b, a, 0)
34
+TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
35
+ gen_helper_gvec_ummla_b, a, 0)
36
37
-static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
38
-{
39
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_smmla_b, 0);
40
-}
41
-
42
-static bool trans_USMMLA(DisasContext *s, arg_rrrr_esz *a)
43
-{
44
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_usmmla_b, 0);
45
-}
46
-
47
-static bool trans_UMMLA(DisasContext *s, arg_rrrr_esz *a)
48
-{
49
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_ummla_b, 0);
50
-}
51
-
52
-static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
53
-{
54
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
55
- return false;
56
- }
57
- return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfdot, a, 0);
58
-}
59
+TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
60
+ gen_helper_gvec_bfdot, a, 0)
61
62
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
63
{
64
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
65
a->rd, a->rn, a->rm, a->ra, a->index);
66
}
67
68
-static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
69
-{
70
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
71
- return false;
72
- }
73
- return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfmmla, a, 0);
74
-}
75
+TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
76
+ gen_helper_gvec_bfmmla, a, 0)
77
78
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
79
{
80
--
81
2.25.1
diff view generated by jsdifflib
New patch
[PULL 016/117] target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Rename the function to match gen_gvec_ool_arg_zzzz,
4
and move to be adjacent.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-14-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 18 +++++++++---------
12
1 file changed, 9 insertions(+), 9 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
19
return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
20
}
21
22
+static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
23
+ arg_rrxr_esz *a)
24
+{
25
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
26
+}
27
+
28
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
29
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
30
int rd, int rn, int pg, int data)
31
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
32
* SVE Multiply - Indexed
33
*/
34
35
-static bool do_zzxz_ool(DisasContext *s, arg_rrxr_esz *a,
36
- gen_helper_gvec_4 *fn)
37
-{
38
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
39
-}
40
-
41
#define DO_RRXR(NAME, FUNC) \
42
static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
43
- { return do_zzxz_ool(s, a, FUNC); }
44
+ { return gen_gvec_ool_arg_zzxz(s, FUNC, a); }
45
46
DO_RRXR(trans_SDOT_zzxw_s, gen_helper_gvec_sdot_idx_b)
47
DO_RRXR(trans_SDOT_zzxw_d, gen_helper_gvec_sdot_idx_h)
48
@@ -XXX,XX +XXX,XX @@ static bool trans_SUDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
49
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
50
return false;
51
}
52
- return do_zzxz_ool(s, a, gen_helper_gvec_sudot_idx_b);
53
+ return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_sudot_idx_b, a);
54
}
55
56
static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
57
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
58
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
59
return false;
60
}
61
- return do_zzxz_ool(s, a, gen_helper_gvec_usdot_idx_b);
62
+ return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_usdot_idx_b, a);
63
}
64
65
#undef DO_RRXR
66
--
67
2.25.1
diff view generated by jsdifflib
New patch
[PULL 017/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zzxz to TRANS_FEAT. Also include
5
BFDOT_zzxz, which was using gen_gvec_ool_zzzz.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-15-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 48 +++++++++++---------------------------
13
1 file changed, 14 insertions(+), 34 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
20
* SVE Multiply - Indexed
21
*/
22
23
-#define DO_RRXR(NAME, FUNC) \
24
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
25
- { return gen_gvec_ool_arg_zzxz(s, FUNC, a); }
26
+TRANS_FEAT(SDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz,
27
+ gen_helper_gvec_sdot_idx_b, a)
28
+TRANS_FEAT(SDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz,
29
+ gen_helper_gvec_sdot_idx_h, a)
30
+TRANS_FEAT(UDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz,
31
+ gen_helper_gvec_udot_idx_b, a)
32
+TRANS_FEAT(UDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz,
33
+ gen_helper_gvec_udot_idx_h, a)
34
35
-DO_RRXR(trans_SDOT_zzxw_s, gen_helper_gvec_sdot_idx_b)
36
-DO_RRXR(trans_SDOT_zzxw_d, gen_helper_gvec_sdot_idx_h)
37
-DO_RRXR(trans_UDOT_zzxw_s, gen_helper_gvec_udot_idx_b)
38
-DO_RRXR(trans_UDOT_zzxw_d, gen_helper_gvec_udot_idx_h)
39
-
40
-static bool trans_SUDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
41
-{
42
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
43
- return false;
44
- }
45
- return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_sudot_idx_b, a);
46
-}
47
-
48
-static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
49
-{
50
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
51
- return false;
52
- }
53
- return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_usdot_idx_b, a);
54
-}
55
-
56
-#undef DO_RRXR
57
+TRANS_FEAT(SUDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
58
+ gen_helper_gvec_sudot_idx_b, a)
59
+TRANS_FEAT(USDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
60
+ gen_helper_gvec_usdot_idx_b, a)
61
62
static bool do_sve2_zzz_data(DisasContext *s, int rd, int rn, int rm, int data,
63
gen_helper_gvec_3 *fn)
64
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
65
66
TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
67
gen_helper_gvec_bfdot, a, 0)
68
-
69
-static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
70
-{
71
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
72
- return false;
73
- }
74
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
75
- a->rd, a->rn, a->rm, a->ra, a->index);
76
-}
77
+TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz,
78
+ gen_helper_gvec_bfdot_idx, a)
79
80
TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
81
gen_helper_gvec_bfmmla, a, 0)
82
--
83
2.25.1
diff view generated by jsdifflib
[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
[PULL 018/117] target/arm: Use TRANS_FEAT for do_sve2_zzz_data
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This extension concerns cache speculation, which TCG does
3
Convert SVE translation functions using do_sve2_zzz_data
4
not implement. Thus we can trivially enable this feature.
4
to use TRANS_FEAT and gen_gvec_ool_zzz.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-16-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
docs/system/arm/emulation.rst | 1 +
11
target/arm/translate-sve.c | 69 ++++++++++++++------------------------
12
target/arm/cpu64.c | 1 +
12
1 file changed, 25 insertions(+), 44 deletions(-)
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
15
13
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
16
--- a/target/arm/translate-sve.c
19
+++ b/docs/system/arm/emulation.rst
17
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SUDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
21
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
19
TRANS_FEAT(USDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
20
gen_helper_gvec_usdot_idx_b, a)
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
21
24
+- FEAT_CSV3 (Cache speculation variant 3)
22
-static bool do_sve2_zzz_data(DisasContext *s, int rd, int rn, int rm, int data,
25
- FEAT_DIT (Data Independent Timing instructions)
23
- gen_helper_gvec_3 *fn)
26
- FEAT_DPB (DC CVAP instruction)
24
-{
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
- return false;
29
index XXXXXXX..XXXXXXX 100644
27
- }
30
--- a/target/arm/cpu64.c
28
- if (sve_access_check(s)) {
31
+++ b/target/arm/cpu64.c
29
- unsigned vsz = vec_full_reg_size(s);
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
30
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
33
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
31
- vec_full_reg_offset(s, rn),
34
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
32
- vec_full_reg_offset(s, rm),
35
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
33
- vsz, vsz, data, fn);
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
34
- }
37
cpu->isar.id_aa64pfr0 = t;
35
- return true;
38
36
-}
39
t = cpu->isar.id_aa64pfr1;
37
-
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
38
#define DO_SVE2_RRX(NAME, FUNC) \
41
index XXXXXXX..XXXXXXX 100644
39
- static bool NAME(DisasContext *s, arg_rrx_esz *a) \
42
--- a/target/arm/cpu_tcg.c
40
- { return do_sve2_zzz_data(s, a->rd, a->rn, a->rm, a->index, FUNC); }
43
+++ b/target/arm/cpu_tcg.c
41
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
42
+ a->rd, a->rn, a->rm, a->index)
45
cpu->isar.id_pfr0 = t;
43
46
44
-DO_SVE2_RRX(trans_MUL_zzx_h, gen_helper_gvec_mul_idx_h)
47
t = cpu->isar.id_pfr2;
45
-DO_SVE2_RRX(trans_MUL_zzx_s, gen_helper_gvec_mul_idx_s)
48
+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
46
-DO_SVE2_RRX(trans_MUL_zzx_d, gen_helper_gvec_mul_idx_d)
49
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
47
+DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h)
50
cpu->isar.id_pfr2 = t;
48
+DO_SVE2_RRX(MUL_zzx_s, gen_helper_gvec_mul_idx_s)
49
+DO_SVE2_RRX(MUL_zzx_d, gen_helper_gvec_mul_idx_d)
50
51
-DO_SVE2_RRX(trans_SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h)
52
-DO_SVE2_RRX(trans_SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s)
53
-DO_SVE2_RRX(trans_SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d)
54
+DO_SVE2_RRX(SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h)
55
+DO_SVE2_RRX(SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s)
56
+DO_SVE2_RRX(SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d)
57
58
-DO_SVE2_RRX(trans_SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h)
59
-DO_SVE2_RRX(trans_SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s)
60
-DO_SVE2_RRX(trans_SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d)
61
+DO_SVE2_RRX(SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h)
62
+DO_SVE2_RRX(SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s)
63
+DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d)
64
65
#undef DO_SVE2_RRX
66
67
#define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \
68
- static bool NAME(DisasContext *s, arg_rrx_esz *a) \
69
- { \
70
- return do_sve2_zzz_data(s, a->rd, a->rn, a->rm, \
71
- (a->index << 1) | TOP, FUNC); \
72
- }
73
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \
74
+ a->rd, a->rn, a->rm, (a->index << 1) | TOP)
75
76
-DO_SVE2_RRX_TB(trans_SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false)
77
-DO_SVE2_RRX_TB(trans_SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false)
78
-DO_SVE2_RRX_TB(trans_SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true)
79
-DO_SVE2_RRX_TB(trans_SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true)
80
+DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false)
81
+DO_SVE2_RRX_TB(SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false)
82
+DO_SVE2_RRX_TB(SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true)
83
+DO_SVE2_RRX_TB(SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true)
84
85
-DO_SVE2_RRX_TB(trans_SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false)
86
-DO_SVE2_RRX_TB(trans_SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false)
87
-DO_SVE2_RRX_TB(trans_SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true)
88
-DO_SVE2_RRX_TB(trans_SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true)
89
+DO_SVE2_RRX_TB(SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false)
90
+DO_SVE2_RRX_TB(SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false)
91
+DO_SVE2_RRX_TB(SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true)
92
+DO_SVE2_RRX_TB(SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true)
93
94
-DO_SVE2_RRX_TB(trans_UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false)
95
-DO_SVE2_RRX_TB(trans_UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false)
96
-DO_SVE2_RRX_TB(trans_UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true)
97
-DO_SVE2_RRX_TB(trans_UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
98
+DO_SVE2_RRX_TB(UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false)
99
+DO_SVE2_RRX_TB(UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false)
100
+DO_SVE2_RRX_TB(UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true)
101
+DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
102
103
#undef DO_SVE2_RRX_TB
51
104
52
--
105
--
53
2.25.1
106
2.25.1
diff view generated by jsdifflib
New patch
[PULL 019/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zzzz_data
4
to use TRANS_FEAT and gen_gvec_ool_{zzzz,zzxz}.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-17-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 106 ++++++++++++++-----------------------
12
1 file changed, 41 insertions(+), 65 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
19
20
#undef DO_SVE2_RRX_TB
21
22
-static bool do_sve2_zzzz_data(DisasContext *s, int rd, int rn, int rm, int ra,
23
- int data, gen_helper_gvec_4 *fn)
24
-{
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- if (sve_access_check(s)) {
29
- unsigned vsz = vec_full_reg_size(s);
30
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
31
- vec_full_reg_offset(s, rn),
32
- vec_full_reg_offset(s, rm),
33
- vec_full_reg_offset(s, ra),
34
- vsz, vsz, data, fn);
35
- }
36
- return true;
37
-}
38
-
39
#define DO_SVE2_RRXR(NAME, FUNC) \
40
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
41
- { return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, a->index, FUNC); }
42
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a)
43
44
-DO_SVE2_RRXR(trans_MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
45
-DO_SVE2_RRXR(trans_MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
46
-DO_SVE2_RRXR(trans_MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
47
+DO_SVE2_RRXR(MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
48
+DO_SVE2_RRXR(MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
49
+DO_SVE2_RRXR(MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
50
51
-DO_SVE2_RRXR(trans_MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
52
-DO_SVE2_RRXR(trans_MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
53
-DO_SVE2_RRXR(trans_MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
54
+DO_SVE2_RRXR(MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
55
+DO_SVE2_RRXR(MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
56
+DO_SVE2_RRXR(MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
57
58
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
59
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
60
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
61
+DO_SVE2_RRXR(SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
62
+DO_SVE2_RRXR(SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
63
+DO_SVE2_RRXR(SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
64
65
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
66
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
67
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
68
+DO_SVE2_RRXR(SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
69
+DO_SVE2_RRXR(SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
70
+DO_SVE2_RRXR(SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
71
72
#undef DO_SVE2_RRXR
73
74
#define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \
75
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
76
- { \
77
- return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->rd, \
78
- (a->index << 1) | TOP, FUNC); \
79
- }
80
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
81
+ a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP)
82
83
-DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false)
84
-DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false)
85
-DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true)
86
-DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true)
87
+DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false)
88
+DO_SVE2_RRXR_TB(SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false)
89
+DO_SVE2_RRXR_TB(SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true)
90
+DO_SVE2_RRXR_TB(SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true)
91
92
-DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false)
93
-DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false)
94
-DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
95
-DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
96
+DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false)
97
+DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false)
98
+DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
99
+DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
100
101
-DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
102
-DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
103
-DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
104
-DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
105
+DO_SVE2_RRXR_TB(SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
106
+DO_SVE2_RRXR_TB(SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
107
+DO_SVE2_RRXR_TB(SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
108
+DO_SVE2_RRXR_TB(SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
109
110
-DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
111
-DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
112
-DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
113
-DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
114
+DO_SVE2_RRXR_TB(UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
115
+DO_SVE2_RRXR_TB(UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
116
+DO_SVE2_RRXR_TB(UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
117
+DO_SVE2_RRXR_TB(UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
118
119
-DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
120
-DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
121
-DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
122
-DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
123
+DO_SVE2_RRXR_TB(SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
124
+DO_SVE2_RRXR_TB(SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
125
+DO_SVE2_RRXR_TB(SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
126
+DO_SVE2_RRXR_TB(SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
127
128
-DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
129
-DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
130
-DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
131
-DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
132
+DO_SVE2_RRXR_TB(UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
133
+DO_SVE2_RRXR_TB(UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
134
+DO_SVE2_RRXR_TB(UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
135
+DO_SVE2_RRXR_TB(UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
136
137
#undef DO_SVE2_RRXR_TB
138
139
#define DO_SVE2_RRXR_ROT(NAME, FUNC) \
140
- static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
141
- { \
142
- return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, \
143
- (a->index << 2) | a->rot, FUNC); \
144
- }
145
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
146
+ a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot)
147
148
DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h)
149
DO_SVE2_RRXR_ROT(CMLA_zzxz_s, gen_helper_sve2_cmla_idx_s)
150
--
151
2.25.1
diff view generated by jsdifflib
[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
[PULL 020/117] target/arm: Use TRANS_FEAT for do_sve2_zzw_data
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This extension concerns branch speculation, which TCG does
3
Convert SVE translation functions using do_sve2_zzw_data
4
not implement. Thus we can trivially enable this feature.
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-18-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
docs/system/arm/emulation.rst | 1 +
11
target/arm/translate-sve.c | 297 ++++++++++++++++++-------------------
12
target/arm/cpu64.c | 1 +
12
1 file changed, 145 insertions(+), 152 deletions(-)
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
15
13
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
16
--- a/target/arm/translate-sve.c
19
+++ b/docs/system/arm/emulation.rst
17
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZPZZ(USQADD, usqadd)
21
- FEAT_BBM at level 2 (Translation table break-before-make levels)
19
* SVE2 Widening Integer Arithmetic
22
- FEAT_BF16 (AArch64 BFloat16 instructions)
20
*/
23
- FEAT_BTI (Branch Target Identification)
21
24
+- FEAT_CSV2 (Cache speculation variant 2)
22
-static bool do_sve2_zzw_ool(DisasContext *s, arg_rrr_esz *a,
25
- FEAT_DIT (Data Independent Timing instructions)
23
- gen_helper_gvec_3 *fn, int data)
26
- FEAT_DPB (DC CVAP instruction)
24
-{
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
- return false;
29
index XXXXXXX..XXXXXXX 100644
27
- }
30
--- a/target/arm/cpu64.c
28
- if (sve_access_check(s)) {
31
+++ b/target/arm/cpu64.c
29
- unsigned vsz = vec_full_reg_size(s);
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
30
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
33
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
31
- vec_full_reg_offset(s, a->rn),
34
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
32
- vec_full_reg_offset(s, a->rm),
35
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
33
- vsz, vsz, data, fn);
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
34
- }
37
cpu->isar.id_aa64pfr0 = t;
35
- return true;
38
36
-}
39
t = cpu->isar.id_aa64pfr1;
37
+static gen_helper_gvec_3 * const saddl_fns[4] = {
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
38
+ NULL, gen_helper_sve2_saddl_h,
41
index XXXXXXX..XXXXXXX 100644
39
+ gen_helper_sve2_saddl_s, gen_helper_sve2_saddl_d,
42
--- a/target/arm/cpu_tcg.c
40
+};
43
+++ b/target/arm/cpu_tcg.c
41
+TRANS_FEAT(SADDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
42
+ saddl_fns[a->esz], a, 0)
45
cpu->isar.id_mmfr4 = t;
43
+TRANS_FEAT(SADDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
46
44
+ saddl_fns[a->esz], a, 3)
47
t = cpu->isar.id_pfr0;
45
+TRANS_FEAT(SADDLBT, aa64_sve2, gen_gvec_ool_arg_zzz,
48
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
46
+ saddl_fns[a->esz], a, 2)
49
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
47
50
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
48
-#define DO_SVE2_ZZZ_TB(NAME, name, SEL1, SEL2) \
51
cpu->isar.id_pfr0 = t;
49
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
50
-{ \
51
- static gen_helper_gvec_3 * const fns[4] = { \
52
- NULL, gen_helper_sve2_##name##_h, \
53
- gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
54
- }; \
55
- return do_sve2_zzw_ool(s, a, fns[a->esz], (SEL2 << 1) | SEL1); \
56
-}
57
+static gen_helper_gvec_3 * const ssubl_fns[4] = {
58
+ NULL, gen_helper_sve2_ssubl_h,
59
+ gen_helper_sve2_ssubl_s, gen_helper_sve2_ssubl_d,
60
+};
61
+TRANS_FEAT(SSUBLB, aa64_sve2, gen_gvec_ool_arg_zzz,
62
+ ssubl_fns[a->esz], a, 0)
63
+TRANS_FEAT(SSUBLT, aa64_sve2, gen_gvec_ool_arg_zzz,
64
+ ssubl_fns[a->esz], a, 3)
65
+TRANS_FEAT(SSUBLBT, aa64_sve2, gen_gvec_ool_arg_zzz,
66
+ ssubl_fns[a->esz], a, 2)
67
+TRANS_FEAT(SSUBLTB, aa64_sve2, gen_gvec_ool_arg_zzz,
68
+ ssubl_fns[a->esz], a, 1)
69
70
-DO_SVE2_ZZZ_TB(SADDLB, saddl, false, false)
71
-DO_SVE2_ZZZ_TB(SSUBLB, ssubl, false, false)
72
-DO_SVE2_ZZZ_TB(SABDLB, sabdl, false, false)
73
+static gen_helper_gvec_3 * const sabdl_fns[4] = {
74
+ NULL, gen_helper_sve2_sabdl_h,
75
+ gen_helper_sve2_sabdl_s, gen_helper_sve2_sabdl_d,
76
+};
77
+TRANS_FEAT(SABDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
78
+ sabdl_fns[a->esz], a, 0)
79
+TRANS_FEAT(SABDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
80
+ sabdl_fns[a->esz], a, 3)
81
82
-DO_SVE2_ZZZ_TB(UADDLB, uaddl, false, false)
83
-DO_SVE2_ZZZ_TB(USUBLB, usubl, false, false)
84
-DO_SVE2_ZZZ_TB(UABDLB, uabdl, false, false)
85
+static gen_helper_gvec_3 * const uaddl_fns[4] = {
86
+ NULL, gen_helper_sve2_uaddl_h,
87
+ gen_helper_sve2_uaddl_s, gen_helper_sve2_uaddl_d,
88
+};
89
+TRANS_FEAT(UADDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
90
+ uaddl_fns[a->esz], a, 0)
91
+TRANS_FEAT(UADDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
92
+ uaddl_fns[a->esz], a, 3)
93
94
-DO_SVE2_ZZZ_TB(SADDLT, saddl, true, true)
95
-DO_SVE2_ZZZ_TB(SSUBLT, ssubl, true, true)
96
-DO_SVE2_ZZZ_TB(SABDLT, sabdl, true, true)
97
+static gen_helper_gvec_3 * const usubl_fns[4] = {
98
+ NULL, gen_helper_sve2_usubl_h,
99
+ gen_helper_sve2_usubl_s, gen_helper_sve2_usubl_d,
100
+};
101
+TRANS_FEAT(USUBLB, aa64_sve2, gen_gvec_ool_arg_zzz,
102
+ usubl_fns[a->esz], a, 0)
103
+TRANS_FEAT(USUBLT, aa64_sve2, gen_gvec_ool_arg_zzz,
104
+ usubl_fns[a->esz], a, 3)
105
106
-DO_SVE2_ZZZ_TB(UADDLT, uaddl, true, true)
107
-DO_SVE2_ZZZ_TB(USUBLT, usubl, true, true)
108
-DO_SVE2_ZZZ_TB(UABDLT, uabdl, true, true)
109
+static gen_helper_gvec_3 * const uabdl_fns[4] = {
110
+ NULL, gen_helper_sve2_uabdl_h,
111
+ gen_helper_sve2_uabdl_s, gen_helper_sve2_uabdl_d,
112
+};
113
+TRANS_FEAT(UABDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
114
+ uabdl_fns[a->esz], a, 0)
115
+TRANS_FEAT(UABDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
116
+ uabdl_fns[a->esz], a, 3)
117
118
-DO_SVE2_ZZZ_TB(SADDLBT, saddl, false, true)
119
-DO_SVE2_ZZZ_TB(SSUBLBT, ssubl, false, true)
120
-DO_SVE2_ZZZ_TB(SSUBLTB, ssubl, true, false)
121
+static gen_helper_gvec_3 * const sqdmull_fns[4] = {
122
+ NULL, gen_helper_sve2_sqdmull_zzz_h,
123
+ gen_helper_sve2_sqdmull_zzz_s, gen_helper_sve2_sqdmull_zzz_d,
124
+};
125
+TRANS_FEAT(SQDMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
126
+ sqdmull_fns[a->esz], a, 0)
127
+TRANS_FEAT(SQDMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
128
+ sqdmull_fns[a->esz], a, 3)
129
130
-DO_SVE2_ZZZ_TB(SQDMULLB_zzz, sqdmull_zzz, false, false)
131
-DO_SVE2_ZZZ_TB(SQDMULLT_zzz, sqdmull_zzz, true, true)
132
+static gen_helper_gvec_3 * const smull_fns[4] = {
133
+ NULL, gen_helper_sve2_smull_zzz_h,
134
+ gen_helper_sve2_smull_zzz_s, gen_helper_sve2_smull_zzz_d,
135
+};
136
+TRANS_FEAT(SMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
137
+ smull_fns[a->esz], a, 0)
138
+TRANS_FEAT(SMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
139
+ smull_fns[a->esz], a, 3)
140
141
-DO_SVE2_ZZZ_TB(SMULLB_zzz, smull_zzz, false, false)
142
-DO_SVE2_ZZZ_TB(SMULLT_zzz, smull_zzz, true, true)
143
+static gen_helper_gvec_3 * const umull_fns[4] = {
144
+ NULL, gen_helper_sve2_umull_zzz_h,
145
+ gen_helper_sve2_umull_zzz_s, gen_helper_sve2_umull_zzz_d,
146
+};
147
+TRANS_FEAT(UMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
148
+ umull_fns[a->esz], a, 0)
149
+TRANS_FEAT(UMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
150
+ umull_fns[a->esz], a, 3)
151
152
-DO_SVE2_ZZZ_TB(UMULLB_zzz, umull_zzz, false, false)
153
-DO_SVE2_ZZZ_TB(UMULLT_zzz, umull_zzz, true, true)
154
-
155
-static bool do_eor_tb(DisasContext *s, arg_rrr_esz *a, bool sel1)
156
-{
157
- static gen_helper_gvec_3 * const fns[4] = {
158
- gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h,
159
- gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d,
160
- };
161
- return do_sve2_zzw_ool(s, a, fns[a->esz], (!sel1 << 1) | sel1);
162
-}
163
-
164
-static bool trans_EORBT(DisasContext *s, arg_rrr_esz *a)
165
-{
166
- return do_eor_tb(s, a, false);
167
-}
168
-
169
-static bool trans_EORTB(DisasContext *s, arg_rrr_esz *a)
170
-{
171
- return do_eor_tb(s, a, true);
172
-}
173
+static gen_helper_gvec_3 * const eoril_fns[4] = {
174
+ gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h,
175
+ gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d,
176
+};
177
+TRANS_FEAT(EORBT, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 2)
178
+TRANS_FEAT(EORTB, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 1)
179
180
static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
181
{
182
@@ -XXX,XX +XXX,XX @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
183
if (a->esz == 0 && !dc_isar_feature(aa64_sve2_pmull128, s)) {
184
return false;
185
}
186
- return do_sve2_zzw_ool(s, a, fns[a->esz], sel);
187
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
188
}
189
190
-static bool trans_PMULLB(DisasContext *s, arg_rrr_esz *a)
191
-{
192
- return do_trans_pmull(s, a, false);
193
-}
194
+TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false)
195
+TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true)
196
197
-static bool trans_PMULLT(DisasContext *s, arg_rrr_esz *a)
198
-{
199
- return do_trans_pmull(s, a, true);
200
-}
201
+static gen_helper_gvec_3 * const saddw_fns[4] = {
202
+ NULL, gen_helper_sve2_saddw_h,
203
+ gen_helper_sve2_saddw_s, gen_helper_sve2_saddw_d,
204
+};
205
+TRANS_FEAT(SADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 0)
206
+TRANS_FEAT(SADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 1)
207
208
-#define DO_SVE2_ZZZ_WTB(NAME, name, SEL2) \
209
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
210
-{ \
211
- static gen_helper_gvec_3 * const fns[4] = { \
212
- NULL, gen_helper_sve2_##name##_h, \
213
- gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
214
- }; \
215
- return do_sve2_zzw_ool(s, a, fns[a->esz], SEL2); \
216
-}
217
+static gen_helper_gvec_3 * const ssubw_fns[4] = {
218
+ NULL, gen_helper_sve2_ssubw_h,
219
+ gen_helper_sve2_ssubw_s, gen_helper_sve2_ssubw_d,
220
+};
221
+TRANS_FEAT(SSUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 0)
222
+TRANS_FEAT(SSUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 1)
223
224
-DO_SVE2_ZZZ_WTB(SADDWB, saddw, false)
225
-DO_SVE2_ZZZ_WTB(SADDWT, saddw, true)
226
-DO_SVE2_ZZZ_WTB(SSUBWB, ssubw, false)
227
-DO_SVE2_ZZZ_WTB(SSUBWT, ssubw, true)
228
+static gen_helper_gvec_3 * const uaddw_fns[4] = {
229
+ NULL, gen_helper_sve2_uaddw_h,
230
+ gen_helper_sve2_uaddw_s, gen_helper_sve2_uaddw_d,
231
+};
232
+TRANS_FEAT(UADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 0)
233
+TRANS_FEAT(UADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 1)
234
235
-DO_SVE2_ZZZ_WTB(UADDWB, uaddw, false)
236
-DO_SVE2_ZZZ_WTB(UADDWT, uaddw, true)
237
-DO_SVE2_ZZZ_WTB(USUBWB, usubw, false)
238
-DO_SVE2_ZZZ_WTB(USUBWT, usubw, true)
239
+static gen_helper_gvec_3 * const usubw_fns[4] = {
240
+ NULL, gen_helper_sve2_usubw_h,
241
+ gen_helper_sve2_usubw_s, gen_helper_sve2_usubw_d,
242
+};
243
+TRANS_FEAT(USUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 0)
244
+TRANS_FEAT(USUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 1)
245
246
static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm)
247
{
248
@@ -XXX,XX +XXX,XX @@ static bool trans_USHLLT(DisasContext *s, arg_rri_esz *a)
249
return do_sve2_shll_tb(s, a, true, true);
250
}
251
252
-static bool trans_BEXT(DisasContext *s, arg_rrr_esz *a)
253
-{
254
- static gen_helper_gvec_3 * const fns[4] = {
255
- gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
256
- gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
257
- };
258
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
259
- return false;
260
- }
261
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
262
-}
263
+static gen_helper_gvec_3 * const bext_fns[4] = {
264
+ gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
265
+ gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
266
+};
267
+TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
268
+ bext_fns[a->esz], a, 0)
269
270
-static bool trans_BDEP(DisasContext *s, arg_rrr_esz *a)
271
-{
272
- static gen_helper_gvec_3 * const fns[4] = {
273
- gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
274
- gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
275
- };
276
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
277
- return false;
278
- }
279
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
280
-}
281
+static gen_helper_gvec_3 * const bdep_fns[4] = {
282
+ gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
283
+ gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
284
+};
285
+TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
286
+ bdep_fns[a->esz], a, 0)
287
288
-static bool trans_BGRP(DisasContext *s, arg_rrr_esz *a)
289
-{
290
- static gen_helper_gvec_3 * const fns[4] = {
291
- gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
292
- gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
293
- };
294
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
295
- return false;
296
- }
297
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
298
-}
299
+static gen_helper_gvec_3 * const bgrp_fns[4] = {
300
+ gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
301
+ gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
302
+};
303
+TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
304
+ bgrp_fns[a->esz], a, 0)
305
306
-static bool do_cadd(DisasContext *s, arg_rrr_esz *a, bool sq, bool rot)
307
-{
308
- static gen_helper_gvec_3 * const fns[2][4] = {
309
- { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
310
- gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d },
311
- { gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
312
- gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d },
313
- };
314
- return do_sve2_zzw_ool(s, a, fns[sq][a->esz], rot);
315
-}
316
+static gen_helper_gvec_3 * const cadd_fns[4] = {
317
+ gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
318
+ gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d,
319
+};
320
+TRANS_FEAT(CADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz,
321
+ cadd_fns[a->esz], a, 0)
322
+TRANS_FEAT(CADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz,
323
+ cadd_fns[a->esz], a, 1)
324
325
-static bool trans_CADD_rot90(DisasContext *s, arg_rrr_esz *a)
326
-{
327
- return do_cadd(s, a, false, false);
328
-}
329
-
330
-static bool trans_CADD_rot270(DisasContext *s, arg_rrr_esz *a)
331
-{
332
- return do_cadd(s, a, false, true);
333
-}
334
-
335
-static bool trans_SQCADD_rot90(DisasContext *s, arg_rrr_esz *a)
336
-{
337
- return do_cadd(s, a, true, false);
338
-}
339
-
340
-static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
341
-{
342
- return do_cadd(s, a, true, true);
343
-}
344
+static gen_helper_gvec_3 * const sqcadd_fns[4] = {
345
+ gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
346
+ gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d,
347
+};
348
+TRANS_FEAT(SQCADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz,
349
+ sqcadd_fns[a->esz], a, 0)
350
+TRANS_FEAT(SQCADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz,
351
+ sqcadd_fns[a->esz], a, 1)
352
353
static gen_helper_gvec_4 * const sabal_fns[4] = {
354
NULL, gen_helper_sve2_sabal_h,
52
--
355
--
53
2.25.1
356
2.25.1
diff view generated by jsdifflib
New patch
[PULL 021/117] target/arm: Use TRANS_FEAT for USDOT_zzzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This is the last direct user of tcg_gen_gvec_4_ool.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-19-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 17 ++---------------
11
1 file changed, 2 insertions(+), 15 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_4 * const sqrdcmlah_fns[] = {
18
TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
19
sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
20
21
-static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
22
-{
23
- if (a->esz != 2 || !dc_isar_feature(aa64_sve_i8mm, s)) {
24
- return false;
25
- }
26
- if (sve_access_check(s)) {
27
- unsigned vsz = vec_full_reg_size(s);
28
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
29
- vec_full_reg_offset(s, a->rn),
30
- vec_full_reg_offset(s, a->rm),
31
- vec_full_reg_offset(s, a->ra),
32
- vsz, vsz, 0, gen_helper_gvec_usdot_b);
33
- }
34
- return true;
35
-}
36
+TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
37
+ a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0)
38
39
TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
40
gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
41
--
42
2.25.1
diff view generated by jsdifflib
New patch
[PULL 022/117] target/arm: Move null function and sve check into gen_gvec_ool_zzp
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-20-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 37 +++++++++++++++----------------------
9
1 file changed, 15 insertions(+), 22 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
19
-static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
20
+static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
21
int rd, int rn, int pg, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- pred_full_reg_offset(s, pg),
27
- vsz, vsz, data, fn);
28
+ if (fn == NULL) {
29
+ return false;
30
+ }
31
+ if (sve_access_check(s)) {
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
34
+ vec_full_reg_offset(s, rn),
35
+ pred_full_reg_offset(s, pg),
36
+ vsz, vsz, data, fn);
37
+ }
38
+ return true;
39
}
40
41
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
42
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
43
44
static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
45
{
46
- if (fn == NULL) {
47
- return false;
48
- }
49
- if (sve_access_check(s)) {
50
- gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
54
}
55
56
#define DO_ZPZ(NAME, name) \
57
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
58
gen_helper_sve_movz_b, gen_helper_sve_movz_h,
59
gen_helper_sve_movz_s, gen_helper_sve_movz_d,
60
};
61
-
62
- if (sve_access_check(s)) {
63
- gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
64
- }
65
- return true;
66
+ return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
67
}
68
69
static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
70
gen_helper_gvec_3 *fn)
71
{
72
- if (sve_access_check(s)) {
73
- gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
74
- }
75
- return true;
76
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
77
}
78
79
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
80
--
81
2.25.1
diff view generated by jsdifflib
New patch
[PULL 023/117] target/arm: Introduce gen_gvec_ool_arg_zpz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use gen_gvec_ool_arg_zpz instead of gen_gvec_ool_zzp
4
when the arguments come from arg_rpr_esz.
5
Replaces do_zpz_ool.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-21-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 45 +++++++++++++++++++++-----------------
13
1 file changed, 25 insertions(+), 20 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
20
return true;
21
}
22
23
+static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn,
24
+ arg_rpr_esz *a, int data)
25
+{
26
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data);
27
+}
28
+
29
+
30
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
31
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
32
int rd, int rn, int rm, int pg, int data)
33
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
34
*** SVE Integer Arithmetic - Unary Predicated Group
35
*/
36
37
-static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
38
-{
39
- return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
40
-}
41
-
42
#define DO_ZPZ(NAME, name) \
43
static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
44
{ \
45
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
46
gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
47
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
48
}; \
49
- return do_zpz_ool(s, a, fns[a->esz]); \
50
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0); \
51
}
52
53
DO_ZPZ(CLS, cls)
54
@@ -XXX,XX +XXX,XX @@ static bool trans_FABS(DisasContext *s, arg_rpr_esz *a)
55
gen_helper_sve_fabs_s,
56
gen_helper_sve_fabs_d
57
};
58
- return do_zpz_ool(s, a, fns[a->esz]);
59
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
60
}
61
62
static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
63
@@ -XXX,XX +XXX,XX @@ static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
64
gen_helper_sve_fneg_s,
65
gen_helper_sve_fneg_d
66
};
67
- return do_zpz_ool(s, a, fns[a->esz]);
68
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
69
}
70
71
static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
72
@@ -XXX,XX +XXX,XX @@ static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
73
gen_helper_sve_sxtb_s,
74
gen_helper_sve_sxtb_d
75
};
76
- return do_zpz_ool(s, a, fns[a->esz]);
77
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
78
}
79
80
static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
81
@@ -XXX,XX +XXX,XX @@ static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
82
gen_helper_sve_uxtb_s,
83
gen_helper_sve_uxtb_d
84
};
85
- return do_zpz_ool(s, a, fns[a->esz]);
86
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
87
}
88
89
static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
90
@@ -XXX,XX +XXX,XX @@ static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
91
gen_helper_sve_sxth_s,
92
gen_helper_sve_sxth_d
93
};
94
- return do_zpz_ool(s, a, fns[a->esz]);
95
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
96
}
97
98
static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
99
@@ -XXX,XX +XXX,XX @@ static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
100
gen_helper_sve_uxth_s,
101
gen_helper_sve_uxth_d
102
};
103
- return do_zpz_ool(s, a, fns[a->esz]);
104
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
105
}
106
107
static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a)
108
{
109
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_sxtw_d : NULL);
110
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_sxtw_d
111
+ : NULL, a, 0);
112
}
113
114
static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a)
115
{
116
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_uxtw_d : NULL);
117
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_uxtw_d
118
+ : NULL, a, 0);
119
}
120
121
#undef DO_ZPZ
122
@@ -XXX,XX +XXX,XX @@ static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a)
123
static gen_helper_gvec_3 * const fns[4] = {
124
NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
125
};
126
- return do_zpz_ool(s, a, fns[a->esz]);
127
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
128
}
129
130
/* Call the helper that computes the ARM LastActiveElement pseudocode
131
@@ -XXX,XX +XXX,XX @@ static bool trans_REVB(DisasContext *s, arg_rpr_esz *a)
132
gen_helper_sve_revb_s,
133
gen_helper_sve_revb_d,
134
};
135
- return do_zpz_ool(s, a, fns[a->esz]);
136
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
137
}
138
139
static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
140
@@ -XXX,XX +XXX,XX @@ static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
141
gen_helper_sve_revh_s,
142
gen_helper_sve_revh_d,
143
};
144
- return do_zpz_ool(s, a, fns[a->esz]);
145
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
146
}
147
148
static bool trans_REVW(DisasContext *s, arg_rpr_esz *a)
149
{
150
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_revw_d : NULL);
151
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_revw_d
152
+ : NULL, a, 0);
153
}
154
155
static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
156
@@ -XXX,XX +XXX,XX @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
157
gen_helper_sve_rbit_s,
158
gen_helper_sve_rbit_d,
159
};
160
- return do_zpz_ool(s, a, fns[a->esz]);
161
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
162
}
163
164
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
165
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zpz_ool(DisasContext *s, arg_rpr_esz *a,
166
if (!dc_isar_feature(aa64_sve2, s)) {
167
return false;
168
}
169
- return do_zpz_ool(s, a, fn);
170
+ return gen_gvec_ool_arg_zpz(s, fn, a, 0);
171
}
172
173
static bool trans_URECPE(DisasContext *s, arg_rpr_esz *a)
174
--
175
2.25.1
diff view generated by jsdifflib
New patch
[PULL 024/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zpz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-22-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 189 ++++++++++++-------------------------
12
1 file changed, 60 insertions(+), 129 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
19
*** SVE Integer Arithmetic - Unary Predicated Group
20
*/
21
22
-#define DO_ZPZ(NAME, name) \
23
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
24
-{ \
25
- static gen_helper_gvec_3 * const fns[4] = { \
26
- gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
27
- gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
28
+#define DO_ZPZ(NAME, FEAT, name) \
29
+ static gen_helper_gvec_3 * const name##_fns[4] = { \
30
+ gen_helper_##name##_b, gen_helper_##name##_h, \
31
+ gen_helper_##name##_s, gen_helper_##name##_d, \
32
}; \
33
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0); \
34
-}
35
+ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0)
36
37
-DO_ZPZ(CLS, cls)
38
-DO_ZPZ(CLZ, clz)
39
-DO_ZPZ(CNT_zpz, cnt_zpz)
40
-DO_ZPZ(CNOT, cnot)
41
-DO_ZPZ(NOT_zpz, not_zpz)
42
-DO_ZPZ(ABS, abs)
43
-DO_ZPZ(NEG, neg)
44
+DO_ZPZ(CLS, aa64_sve, sve_cls)
45
+DO_ZPZ(CLZ, aa64_sve, sve_clz)
46
+DO_ZPZ(CNT_zpz, aa64_sve, sve_cnt_zpz)
47
+DO_ZPZ(CNOT, aa64_sve, sve_cnot)
48
+DO_ZPZ(NOT_zpz, aa64_sve, sve_not_zpz)
49
+DO_ZPZ(ABS, aa64_sve, sve_abs)
50
+DO_ZPZ(NEG, aa64_sve, sve_neg)
51
+DO_ZPZ(RBIT, aa64_sve, sve_rbit)
52
53
-static bool trans_FABS(DisasContext *s, arg_rpr_esz *a)
54
-{
55
- static gen_helper_gvec_3 * const fns[4] = {
56
- NULL,
57
- gen_helper_sve_fabs_h,
58
- gen_helper_sve_fabs_s,
59
- gen_helper_sve_fabs_d
60
- };
61
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
62
-}
63
+static gen_helper_gvec_3 * const fabs_fns[4] = {
64
+ NULL, gen_helper_sve_fabs_h,
65
+ gen_helper_sve_fabs_s, gen_helper_sve_fabs_d,
66
+};
67
+TRANS_FEAT(FABS, aa64_sve, gen_gvec_ool_arg_zpz, fabs_fns[a->esz], a, 0)
68
69
-static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
70
-{
71
- static gen_helper_gvec_3 * const fns[4] = {
72
- NULL,
73
- gen_helper_sve_fneg_h,
74
- gen_helper_sve_fneg_s,
75
- gen_helper_sve_fneg_d
76
- };
77
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
78
-}
79
+static gen_helper_gvec_3 * const fneg_fns[4] = {
80
+ NULL, gen_helper_sve_fneg_h,
81
+ gen_helper_sve_fneg_s, gen_helper_sve_fneg_d,
82
+};
83
+TRANS_FEAT(FNEG, aa64_sve, gen_gvec_ool_arg_zpz, fneg_fns[a->esz], a, 0)
84
85
-static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
86
-{
87
- static gen_helper_gvec_3 * const fns[4] = {
88
- NULL,
89
- gen_helper_sve_sxtb_h,
90
- gen_helper_sve_sxtb_s,
91
- gen_helper_sve_sxtb_d
92
- };
93
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
94
-}
95
+static gen_helper_gvec_3 * const sxtb_fns[4] = {
96
+ NULL, gen_helper_sve_sxtb_h,
97
+ gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d,
98
+};
99
+TRANS_FEAT(SXTB, aa64_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0)
100
101
-static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
102
-{
103
- static gen_helper_gvec_3 * const fns[4] = {
104
- NULL,
105
- gen_helper_sve_uxtb_h,
106
- gen_helper_sve_uxtb_s,
107
- gen_helper_sve_uxtb_d
108
- };
109
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
110
-}
111
+static gen_helper_gvec_3 * const uxtb_fns[4] = {
112
+ NULL, gen_helper_sve_uxtb_h,
113
+ gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d,
114
+};
115
+TRANS_FEAT(UXTB, aa64_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0)
116
117
-static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
118
-{
119
- static gen_helper_gvec_3 * const fns[4] = {
120
- NULL, NULL,
121
- gen_helper_sve_sxth_s,
122
- gen_helper_sve_sxth_d
123
- };
124
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
125
-}
126
+static gen_helper_gvec_3 * const sxth_fns[4] = {
127
+ NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d
128
+};
129
+TRANS_FEAT(SXTH, aa64_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0)
130
131
-static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
132
-{
133
- static gen_helper_gvec_3 * const fns[4] = {
134
- NULL, NULL,
135
- gen_helper_sve_uxth_s,
136
- gen_helper_sve_uxth_d
137
- };
138
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
139
-}
140
+static gen_helper_gvec_3 * const uxth_fns[4] = {
141
+ NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d
142
+};
143
+TRANS_FEAT(UXTH, aa64_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0)
144
145
-static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a)
146
-{
147
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_sxtw_d
148
- : NULL, a, 0);
149
-}
150
-
151
-static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a)
152
-{
153
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_uxtw_d
154
- : NULL, a, 0);
155
-}
156
-
157
-#undef DO_ZPZ
158
+TRANS_FEAT(SXTW, aa64_sve, gen_gvec_ool_arg_zpz,
159
+ a->esz == 3 ? gen_helper_sve_sxtw_d : NULL, a, 0)
160
+TRANS_FEAT(UXTW, aa64_sve, gen_gvec_ool_arg_zpz,
161
+ a->esz == 3 ? gen_helper_sve_uxtw_d : NULL, a, 0)
162
163
/*
164
*** SVE Integer Reduction Group
165
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
166
*** SVE Permute Vector - Predicated Group
167
*/
168
169
-static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a)
170
-{
171
- static gen_helper_gvec_3 * const fns[4] = {
172
- NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
173
- };
174
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
175
-}
176
+static gen_helper_gvec_3 * const compact_fns[4] = {
177
+ NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
178
+};
179
+TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0)
180
181
/* Call the helper that computes the ARM LastActiveElement pseudocode
182
* function, scaled by the element size. This includes the not found
183
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a)
184
return true;
185
}
186
187
-static bool trans_REVB(DisasContext *s, arg_rpr_esz *a)
188
-{
189
- static gen_helper_gvec_3 * const fns[4] = {
190
- NULL,
191
- gen_helper_sve_revb_h,
192
- gen_helper_sve_revb_s,
193
- gen_helper_sve_revb_d,
194
- };
195
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
196
-}
197
+static gen_helper_gvec_3 * const revb_fns[4] = {
198
+ NULL, gen_helper_sve_revb_h,
199
+ gen_helper_sve_revb_s, gen_helper_sve_revb_d,
200
+};
201
+TRANS_FEAT(REVB, aa64_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0)
202
203
-static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
204
-{
205
- static gen_helper_gvec_3 * const fns[4] = {
206
- NULL,
207
- NULL,
208
- gen_helper_sve_revh_s,
209
- gen_helper_sve_revh_d,
210
- };
211
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
212
-}
213
+static gen_helper_gvec_3 * const revh_fns[4] = {
214
+ NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d,
215
+};
216
+TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
217
218
-static bool trans_REVW(DisasContext *s, arg_rpr_esz *a)
219
-{
220
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_revw_d
221
- : NULL, a, 0);
222
-}
223
-
224
-static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
225
-{
226
- static gen_helper_gvec_3 * const fns[4] = {
227
- gen_helper_sve_rbit_b,
228
- gen_helper_sve_rbit_h,
229
- gen_helper_sve_rbit_s,
230
- gen_helper_sve_rbit_d,
231
- };
232
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
233
-}
234
+TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
235
+ a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
236
237
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
238
{
239
--
240
2.25.1
diff view generated by jsdifflib
New patch
[PULL 025/117] target/arm: Use TRANS_FEAT for do_sve2_zpz_data
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zpz_data
4
to use TRANS_FEAT and gen_gvec_ool_arg_zpz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-23-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 53 ++++++++++----------------------------
12
1 file changed, 14 insertions(+), 39 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_UADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
19
* SVE2 integer unary operations (predicated)
20
*/
21
22
-static bool do_sve2_zpz_ool(DisasContext *s, arg_rpr_esz *a,
23
- gen_helper_gvec_3 *fn)
24
-{
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zpz(s, fn, a, 0);
29
-}
30
+TRANS_FEAT(URECPE, aa64_sve2, gen_gvec_ool_arg_zpz,
31
+ a->esz == 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0)
32
33
-static bool trans_URECPE(DisasContext *s, arg_rpr_esz *a)
34
-{
35
- if (a->esz != 2) {
36
- return false;
37
- }
38
- return do_sve2_zpz_ool(s, a, gen_helper_sve2_urecpe_s);
39
-}
40
+TRANS_FEAT(URSQRTE, aa64_sve2, gen_gvec_ool_arg_zpz,
41
+ a->esz == 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0)
42
43
-static bool trans_URSQRTE(DisasContext *s, arg_rpr_esz *a)
44
-{
45
- if (a->esz != 2) {
46
- return false;
47
- }
48
- return do_sve2_zpz_ool(s, a, gen_helper_sve2_ursqrte_s);
49
-}
50
+static gen_helper_gvec_3 * const sqabs_fns[4] = {
51
+ gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h,
52
+ gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d,
53
+};
54
+TRANS_FEAT(SQABS, aa64_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0)
55
56
-static bool trans_SQABS(DisasContext *s, arg_rpr_esz *a)
57
-{
58
- static gen_helper_gvec_3 * const fns[4] = {
59
- gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h,
60
- gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d,
61
- };
62
- return do_sve2_zpz_ool(s, a, fns[a->esz]);
63
-}
64
-
65
-static bool trans_SQNEG(DisasContext *s, arg_rpr_esz *a)
66
-{
67
- static gen_helper_gvec_3 * const fns[4] = {
68
- gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h,
69
- gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d,
70
- };
71
- return do_sve2_zpz_ool(s, a, fns[a->esz]);
72
-}
73
+static gen_helper_gvec_3 * const sqneg_fns[4] = {
74
+ gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h,
75
+ gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d,
76
+};
77
+TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0)
78
79
#define DO_SVE2_ZPZZ(NAME, name) \
80
static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
81
--
82
2.25.1
diff view generated by jsdifflib
New patch
[PULL 026/117] target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Rename the function to match gen_gvec_ool_arg_zpz,
4
and move to be adjacent.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-24-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 29 ++++++++++++++---------------
12
1 file changed, 14 insertions(+), 15 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn,
19
return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data);
20
}
21
22
+static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
23
+ arg_rpri_esz *a)
24
+{
25
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
26
+}
27
28
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
29
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
30
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
31
return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
32
}
33
34
-static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
35
- gen_helper_gvec_3 *fn)
36
-{
37
- return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
38
-}
39
-
40
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
41
{
42
static gen_helper_gvec_3 * const fns[4] = {
43
@@ -XXX,XX +XXX,XX @@ static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
44
/* Shift by element size is architecturally valid. For
45
arithmetic right-shift, it's the same as by one less. */
46
a->imm = MIN(a->imm, (8 << a->esz) - 1);
47
- return do_zpzi_ool(s, a, fns[a->esz]);
48
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
49
}
50
51
static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
52
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
53
if (a->imm >= (8 << a->esz)) {
54
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
55
} else {
56
- return do_zpzi_ool(s, a, fns[a->esz]);
57
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
58
}
59
}
60
61
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
62
if (a->imm >= (8 << a->esz)) {
63
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
64
} else {
65
- return do_zpzi_ool(s, a, fns[a->esz]);
66
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
67
}
68
}
69
70
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
71
if (a->imm >= (8 << a->esz)) {
72
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
73
} else {
74
- return do_zpzi_ool(s, a, fns[a->esz]);
75
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
76
}
77
}
78
79
@@ -XXX,XX +XXX,XX @@ static bool trans_SQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
80
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
81
return false;
82
}
83
- return do_zpzi_ool(s, a, fns[a->esz]);
84
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
85
}
86
87
static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
88
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
89
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
90
return false;
91
}
92
- return do_zpzi_ool(s, a, fns[a->esz]);
93
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
94
}
95
96
static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
97
@@ -XXX,XX +XXX,XX @@ static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
98
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
99
return false;
100
}
101
- return do_zpzi_ool(s, a, fns[a->esz]);
102
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
103
}
104
105
static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
106
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
107
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
108
return false;
109
}
110
- return do_zpzi_ool(s, a, fns[a->esz]);
111
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
112
}
113
114
static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
115
@@ -XXX,XX +XXX,XX @@ static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
116
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
117
return false;
118
}
119
- return do_zpzi_ool(s, a, fns[a->esz]);
120
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
121
}
122
123
/*
124
--
125
2.25.1
diff view generated by jsdifflib
[PULL 04/32] target/arm: Merge zcr reginfo
[PULL 027/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
3
Convert some SVE translation functions using
4
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
4
gen_gvec_ool_arg_zpzi to TRANS_FEAT.
5
while registering.
6
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-25-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/helper.c | 55 ++++++++++++++-------------------------------
11
target/arm/translate-sve.c | 85 ++++++++++++++------------------------
13
1 file changed, 17 insertions(+), 38 deletions(-)
12
1 file changed, 30 insertions(+), 55 deletions(-)
14
13
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
16
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/helper.c
17
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
18
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
20
}
19
}
21
}
20
}
22
21
23
-static const ARMCPRegInfo zcr_el1_reginfo = {
22
-static bool trans_SQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
24
- .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
23
-{
25
- .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
24
- static gen_helper_gvec_3 * const fns[4] = {
26
- .access = PL1_RW, .type = ARM_CP_SVE,
25
- gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
27
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
26
- gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d,
28
- .writefn = zcr_write, .raw_writefn = raw_write
27
- };
29
-};
28
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
30
-
29
- return false;
31
-static const ARMCPRegInfo zcr_el2_reginfo = {
30
- }
32
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
31
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
33
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
32
-}
34
- .access = PL2_RW, .type = ARM_CP_SVE,
33
+static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
35
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
34
+ gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
36
- .writefn = zcr_write, .raw_writefn = raw_write
35
+ gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d,
37
-};
36
+};
38
-
37
+TRANS_FEAT(SQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi,
39
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
38
+ a->esz < 0 ? NULL : sqshl_zpzi_fns[a->esz], a)
40
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
39
41
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
40
-static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
42
- .access = PL2_RW, .type = ARM_CP_SVE,
41
-{
43
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
42
- static gen_helper_gvec_3 * const fns[4] = {
44
-};
43
- gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h,
45
-
44
- gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d,
46
-static const ARMCPRegInfo zcr_el3_reginfo = {
45
- };
47
- .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
46
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
48
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
47
- return false;
49
- .access = PL3_RW, .type = ARM_CP_SVE,
48
- }
50
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
49
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
51
- .writefn = zcr_write, .raw_writefn = raw_write
50
-}
52
+static const ARMCPRegInfo zcr_reginfo[] = {
51
+static gen_helper_gvec_3 * const uqshl_zpzi_fns[4] = {
53
+ { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
52
+ gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h,
54
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
53
+ gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d,
55
+ .access = PL1_RW, .type = ARM_CP_SVE,
54
+};
56
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
55
+TRANS_FEAT(UQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi,
57
+ .writefn = zcr_write, .raw_writefn = raw_write },
56
+ a->esz < 0 ? NULL : uqshl_zpzi_fns[a->esz], a)
58
+ { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
57
59
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
58
-static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
60
+ .access = PL2_RW, .type = ARM_CP_SVE,
59
-{
61
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
60
- static gen_helper_gvec_3 * const fns[4] = {
62
+ .writefn = zcr_write, .raw_writefn = raw_write },
61
- gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h,
63
+ { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
62
- gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d,
64
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
63
- };
65
+ .access = PL3_RW, .type = ARM_CP_SVE,
64
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
66
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
65
- return false;
67
+ .writefn = zcr_write, .raw_writefn = raw_write },
66
- }
68
};
67
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
69
68
-}
70
void hw_watchpoint_update(ARMCPU *cpu, int n)
69
+static gen_helper_gvec_3 * const srshr_fns[4] = {
71
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
70
+ gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h,
72
}
71
+ gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d,
73
72
+};
74
if (cpu_isar_feature(aa64_sve, cpu)) {
73
+TRANS_FEAT(SRSHR, aa64_sve2, gen_gvec_ool_arg_zpzi,
75
- define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
74
+ a->esz < 0 ? NULL : srshr_fns[a->esz], a)
76
- if (arm_feature(env, ARM_FEATURE_EL2)) {
75
77
- define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
76
-static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
78
- } else {
77
-{
79
- define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
78
- static gen_helper_gvec_3 * const fns[4] = {
80
- }
79
- gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h,
81
- if (arm_feature(env, ARM_FEATURE_EL3)) {
80
- gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d,
82
- define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
81
- };
83
- }
82
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
84
+ define_arm_cp_regs(cpu, zcr_reginfo);
83
- return false;
85
}
84
- }
86
85
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
87
#ifdef TARGET_AARCH64
86
-}
87
+static gen_helper_gvec_3 * const urshr_fns[4] = {
88
+ gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h,
89
+ gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d,
90
+};
91
+TRANS_FEAT(URSHR, aa64_sve2, gen_gvec_ool_arg_zpzi,
92
+ a->esz < 0 ? NULL : urshr_fns[a->esz], a)
93
94
-static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
95
-{
96
- static gen_helper_gvec_3 * const fns[4] = {
97
- gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h,
98
- gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d,
99
- };
100
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
101
- return false;
102
- }
103
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
104
-}
105
+static gen_helper_gvec_3 * const sqshlu_fns[4] = {
106
+ gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h,
107
+ gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d,
108
+};
109
+TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi,
110
+ a->esz < 0 ? NULL : sqshlu_fns[a->esz], a)
111
112
/*
113
*** SVE Bitwise Shift - Predicated Group
88
--
114
--
89
2.25.1
115
2.25.1
diff view generated by jsdifflib
New patch
[PULL 028/117] target/arm: Move null function and sve check into gen_gvec_ool_zzzp
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-26-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 42 ++++++++++++++++----------------------
9
1 file changed, 18 insertions(+), 24 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
19
-static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
20
+static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
21
int rd, int rn, int rm, int pg, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- pred_full_reg_offset(s, pg),
28
- vsz, vsz, data, fn);
29
+ if (fn == NULL) {
30
+ return false;
31
+ }
32
+ if (sve_access_check(s)) {
33
+ unsigned vsz = vec_full_reg_size(s);
34
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
35
+ vec_full_reg_offset(s, rn),
36
+ vec_full_reg_offset(s, rm),
37
+ pred_full_reg_offset(s, pg),
38
+ vsz, vsz, data, fn);
39
+ }
40
+ return true;
41
}
42
43
/* Invoke a vector expander on two Zregs. */
44
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
45
46
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
47
{
48
- if (fn == NULL) {
49
- return false;
50
- }
51
- if (sve_access_check(s)) {
52
- gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
53
- }
54
- return true;
55
+ return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
56
}
57
58
/* Select active elememnts from Zn and inactive elements from Zm,
59
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
60
61
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
62
{
63
- if (sve_access_check(s)) {
64
- gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
65
- a->rd, a->rn, a->rm, a->pg, a->esz);
66
- }
67
- return true;
68
+ return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
69
+ a->rd, a->rn, a->rm, a->pg, a->esz);
70
}
71
72
static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
73
@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
74
if (!dc_isar_feature(aa64_sve2, s)) {
75
return false;
76
}
77
- if (sve_access_check(s)) {
78
- gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
79
- a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
80
- }
81
- return true;
82
+ return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
83
+ a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
84
}
85
86
/*
87
--
88
2.25.1
diff view generated by jsdifflib
[PULL 25/32] target/arm: Define neoverse-n1
[PULL 029/117] target/arm: Introduce gen_gvec_ool_arg_zpzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Enable the n1 for virt and sbsa board use.
3
Use gen_gvec_ool_arg_zpzz instead of gen_gvec_ool_zzzp
4
when the arguments come from arg_rprr_esz.
5
Replaces do_zpzz_ool.
4
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-27-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
docs/system/arm/virt.rst | 1 +
12
target/arm/translate-sve.c | 21 +++++++++++----------
11
hw/arm/sbsa-ref.c | 1 +
13
1 file changed, 11 insertions(+), 10 deletions(-)
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
15
14
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/virt.rst
17
--- a/target/arm/translate-sve.c
19
+++ b/docs/system/arm/virt.rst
18
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
21
- ``cortex-a76`` (64-bit)
20
return true;
22
- ``a64fx`` (64-bit)
23
- ``host`` (with KVM only)
24
+- ``neoverse-n1`` (64-bit)
25
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
26
27
Note that the default is ``cortex-a15``, so for an AArch64 guest you must
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/sbsa-ref.c
31
+++ b/hw/arm/sbsa-ref.c
32
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
33
ARM_CPU_TYPE_NAME("cortex-a57"),
34
ARM_CPU_TYPE_NAME("cortex-a72"),
35
ARM_CPU_TYPE_NAME("cortex-a76"),
36
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
37
ARM_CPU_TYPE_NAME("max"),
38
};
39
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a72"),
46
ARM_CPU_TYPE_NAME("cortex-a76"),
47
ARM_CPU_TYPE_NAME("a64fx"),
48
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
49
ARM_CPU_TYPE_NAME("host"),
50
ARM_CPU_TYPE_NAME("max"),
51
};
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
57
cpu->isar.mvfr2 = 0x00000043;
58
}
21
}
59
22
60
+static void aarch64_neoverse_n1_initfn(Object *obj)
23
+static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
24
+ arg_rprr_esz *a, int data)
61
+{
25
+{
62
+ ARMCPU *cpu = ARM_CPU(obj);
26
+ return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
63
+
64
+ cpu->dtb_compatible = "arm,neoverse-n1";
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
73
+
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
75
+ cpu->clidr = 0x82000023;
76
+ cpu->ctr = 0x8444c004;
77
+ cpu->dcz_blocksize = 4;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0c1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.23 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
110
+
111
+ /* From B2.98 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
123
+}
27
+}
124
+
28
+
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
29
/* Invoke a vector expander on two Zregs. */
126
{
30
static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
127
/*
31
int esz, int rd, int rn)
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
32
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
129
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
33
*** SVE Integer Arithmetic - Binary Predicated Group
130
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
34
*/
131
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
35
132
+ { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
36
-static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
133
{ .name = "max", .initfn = aarch64_max_initfn },
37
-{
134
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
38
- return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
135
{ .name = "host", .initfn = aarch64_host_initfn },
39
-}
40
-
41
/* Select active elememnts from Zn and inactive elements from Zm,
42
* storing the result in Zd.
43
*/
44
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a) \
45
gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \
46
gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \
47
}; \
48
- return do_zpzz_ool(s, a, fns[a->esz]); \
49
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
50
}
51
52
DO_ZPZZ(AND, and)
53
@@ -XXX,XX +XXX,XX @@ static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
54
static gen_helper_gvec_4 * const fns[4] = {
55
NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
56
};
57
- return do_zpzz_ool(s, a, fns[a->esz]);
58
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
59
}
60
61
static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
62
@@ -XXX,XX +XXX,XX @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
63
static gen_helper_gvec_4 * const fns[4] = {
64
NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
65
};
66
- return do_zpzz_ool(s, a, fns[a->esz]);
67
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
68
}
69
70
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
71
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a) \
72
if (a->esz < 0 || a->esz >= 3) { \
73
return false; \
74
} \
75
- return do_zpzz_ool(s, a, fns[a->esz]); \
76
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
77
}
78
79
DO_ZPZW(ASR, asr)
80
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zpzz_ool(DisasContext *s, arg_rprr_esz *a,
81
if (!dc_isar_feature(aa64_sve2, s)) {
82
return false;
83
}
84
- return do_zpzz_ool(s, a, fn);
85
+ return gen_gvec_ool_arg_zpzz(s, fn, a, 0);
86
}
87
88
static bool trans_SADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
136
--
89
--
137
2.25.1
90
2.25.1
diff view generated by jsdifflib
New patch
[PULL 030/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zpzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-28-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 85 ++++++++++++++++----------------------
12
1 file changed, 36 insertions(+), 49 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
19
gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
20
}
21
22
-#define DO_ZPZZ(NAME, name) \
23
-static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a) \
24
-{ \
25
- static gen_helper_gvec_4 * const fns[4] = { \
26
- gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \
27
- gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \
28
+#define DO_ZPZZ(NAME, FEAT, name) \
29
+ static gen_helper_gvec_4 * const name##_zpzz_fns[4] = { \
30
+ gen_helper_##name##_zpzz_b, gen_helper_##name##_zpzz_h, \
31
+ gen_helper_##name##_zpzz_s, gen_helper_##name##_zpzz_d, \
32
}; \
33
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
34
-}
35
+ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpzz, \
36
+ name##_zpzz_fns[a->esz], a, 0)
37
38
-DO_ZPZZ(AND, and)
39
-DO_ZPZZ(EOR, eor)
40
-DO_ZPZZ(ORR, orr)
41
-DO_ZPZZ(BIC, bic)
42
+DO_ZPZZ(AND_zpzz, aa64_sve, sve_and)
43
+DO_ZPZZ(EOR_zpzz, aa64_sve, sve_eor)
44
+DO_ZPZZ(ORR_zpzz, aa64_sve, sve_orr)
45
+DO_ZPZZ(BIC_zpzz, aa64_sve, sve_bic)
46
47
-DO_ZPZZ(ADD, add)
48
-DO_ZPZZ(SUB, sub)
49
+DO_ZPZZ(ADD_zpzz, aa64_sve, sve_add)
50
+DO_ZPZZ(SUB_zpzz, aa64_sve, sve_sub)
51
52
-DO_ZPZZ(SMAX, smax)
53
-DO_ZPZZ(UMAX, umax)
54
-DO_ZPZZ(SMIN, smin)
55
-DO_ZPZZ(UMIN, umin)
56
-DO_ZPZZ(SABD, sabd)
57
-DO_ZPZZ(UABD, uabd)
58
+DO_ZPZZ(SMAX_zpzz, aa64_sve, sve_smax)
59
+DO_ZPZZ(UMAX_zpzz, aa64_sve, sve_umax)
60
+DO_ZPZZ(SMIN_zpzz, aa64_sve, sve_smin)
61
+DO_ZPZZ(UMIN_zpzz, aa64_sve, sve_umin)
62
+DO_ZPZZ(SABD_zpzz, aa64_sve, sve_sabd)
63
+DO_ZPZZ(UABD_zpzz, aa64_sve, sve_uabd)
64
65
-DO_ZPZZ(MUL, mul)
66
-DO_ZPZZ(SMULH, smulh)
67
-DO_ZPZZ(UMULH, umulh)
68
+DO_ZPZZ(MUL_zpzz, aa64_sve, sve_mul)
69
+DO_ZPZZ(SMULH_zpzz, aa64_sve, sve_smulh)
70
+DO_ZPZZ(UMULH_zpzz, aa64_sve, sve_umulh)
71
72
-DO_ZPZZ(ASR, asr)
73
-DO_ZPZZ(LSR, lsr)
74
-DO_ZPZZ(LSL, lsl)
75
+DO_ZPZZ(ASR_zpzz, aa64_sve, sve_asr)
76
+DO_ZPZZ(LSR_zpzz, aa64_sve, sve_lsr)
77
+DO_ZPZZ(LSL_zpzz, aa64_sve, sve_lsl)
78
79
-static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
80
-{
81
- static gen_helper_gvec_4 * const fns[4] = {
82
- NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
83
- };
84
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
85
-}
86
+static gen_helper_gvec_4 * const sdiv_fns[4] = {
87
+ NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
88
+};
89
+TRANS_FEAT(SDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->esz], a, 0)
90
91
-static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
92
-{
93
- static gen_helper_gvec_4 * const fns[4] = {
94
- NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
95
- };
96
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
97
-}
98
+static gen_helper_gvec_4 * const udiv_fns[4] = {
99
+ NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
100
+};
101
+TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
102
103
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
104
{
105
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi,
106
*/
107
108
#define DO_ZPZW(NAME, name) \
109
-static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a) \
110
-{ \
111
- static gen_helper_gvec_4 * const fns[3] = { \
112
+ static gen_helper_gvec_4 * const name##_zpzw_fns[4] = { \
113
gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \
114
- gen_helper_sve_##name##_zpzw_s, \
115
+ gen_helper_sve_##name##_zpzw_s, NULL \
116
}; \
117
- if (a->esz < 0 || a->esz >= 3) { \
118
- return false; \
119
- } \
120
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
121
-}
122
+ TRANS_FEAT(NAME##_zpzw, aa64_sve, gen_gvec_ool_arg_zpzz, \
123
+ a->esz < 0 ? NULL : name##_zpzw_fns[a->esz], a, 0)
124
125
DO_ZPZW(ASR, asr)
126
DO_ZPZW(LSR, lsr)
127
--
128
2.25.1
diff view generated by jsdifflib
New patch
[PULL 031/117] target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zpzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zpzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-29-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 118 +++++++++++++------------------------
12
1 file changed, 40 insertions(+), 78 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
19
return true;
20
}
21
22
-#undef DO_ZPZZ
23
-
24
/*
25
*** SVE Integer Arithmetic - Unary Predicated Group
26
*/
27
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
28
* SVE2 Integer - Predicated
29
*/
30
31
-static bool do_sve2_zpzz_ool(DisasContext *s, arg_rprr_esz *a,
32
- gen_helper_gvec_4 *fn)
33
-{
34
- if (!dc_isar_feature(aa64_sve2, s)) {
35
- return false;
36
- }
37
- return gen_gvec_ool_arg_zpzz(s, fn, a, 0);
38
-}
39
+static gen_helper_gvec_4 * const sadlp_fns[4] = {
40
+ NULL, gen_helper_sve2_sadalp_zpzz_h,
41
+ gen_helper_sve2_sadalp_zpzz_s, gen_helper_sve2_sadalp_zpzz_d,
42
+};
43
+TRANS_FEAT(SADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz,
44
+ sadlp_fns[a->esz], a, 0)
45
46
-static bool trans_SADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
47
-{
48
- static gen_helper_gvec_4 * const fns[3] = {
49
- gen_helper_sve2_sadalp_zpzz_h,
50
- gen_helper_sve2_sadalp_zpzz_s,
51
- gen_helper_sve2_sadalp_zpzz_d,
52
- };
53
- if (a->esz == 0) {
54
- return false;
55
- }
56
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
57
-}
58
-
59
-static bool trans_UADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
60
-{
61
- static gen_helper_gvec_4 * const fns[3] = {
62
- gen_helper_sve2_uadalp_zpzz_h,
63
- gen_helper_sve2_uadalp_zpzz_s,
64
- gen_helper_sve2_uadalp_zpzz_d,
65
- };
66
- if (a->esz == 0) {
67
- return false;
68
- }
69
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
70
-}
71
+static gen_helper_gvec_4 * const uadlp_fns[4] = {
72
+ NULL, gen_helper_sve2_uadalp_zpzz_h,
73
+ gen_helper_sve2_uadalp_zpzz_s, gen_helper_sve2_uadalp_zpzz_d,
74
+};
75
+TRANS_FEAT(UADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz,
76
+ uadlp_fns[a->esz], a, 0)
77
78
/*
79
* SVE2 integer unary operations (predicated)
80
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const sqneg_fns[4] = {
81
};
82
TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0)
83
84
-#define DO_SVE2_ZPZZ(NAME, name) \
85
-static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
86
-{ \
87
- static gen_helper_gvec_4 * const fns[4] = { \
88
- gen_helper_sve2_##name##_zpzz_b, gen_helper_sve2_##name##_zpzz_h, \
89
- gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d, \
90
- }; \
91
- return do_sve2_zpzz_ool(s, a, fns[a->esz]); \
92
-}
93
+DO_ZPZZ(SQSHL, aa64_sve2, sve2_sqshl)
94
+DO_ZPZZ(SQRSHL, aa64_sve2, sve2_sqrshl)
95
+DO_ZPZZ(SRSHL, aa64_sve2, sve2_srshl)
96
97
-DO_SVE2_ZPZZ(SQSHL, sqshl)
98
-DO_SVE2_ZPZZ(SQRSHL, sqrshl)
99
-DO_SVE2_ZPZZ(SRSHL, srshl)
100
+DO_ZPZZ(UQSHL, aa64_sve2, sve2_uqshl)
101
+DO_ZPZZ(UQRSHL, aa64_sve2, sve2_uqrshl)
102
+DO_ZPZZ(URSHL, aa64_sve2, sve2_urshl)
103
104
-DO_SVE2_ZPZZ(UQSHL, uqshl)
105
-DO_SVE2_ZPZZ(UQRSHL, uqrshl)
106
-DO_SVE2_ZPZZ(URSHL, urshl)
107
+DO_ZPZZ(SHADD, aa64_sve2, sve2_shadd)
108
+DO_ZPZZ(SRHADD, aa64_sve2, sve2_srhadd)
109
+DO_ZPZZ(SHSUB, aa64_sve2, sve2_shsub)
110
111
-DO_SVE2_ZPZZ(SHADD, shadd)
112
-DO_SVE2_ZPZZ(SRHADD, srhadd)
113
-DO_SVE2_ZPZZ(SHSUB, shsub)
114
+DO_ZPZZ(UHADD, aa64_sve2, sve2_uhadd)
115
+DO_ZPZZ(URHADD, aa64_sve2, sve2_urhadd)
116
+DO_ZPZZ(UHSUB, aa64_sve2, sve2_uhsub)
117
118
-DO_SVE2_ZPZZ(UHADD, uhadd)
119
-DO_SVE2_ZPZZ(URHADD, urhadd)
120
-DO_SVE2_ZPZZ(UHSUB, uhsub)
121
+DO_ZPZZ(ADDP, aa64_sve2, sve2_addp)
122
+DO_ZPZZ(SMAXP, aa64_sve2, sve2_smaxp)
123
+DO_ZPZZ(UMAXP, aa64_sve2, sve2_umaxp)
124
+DO_ZPZZ(SMINP, aa64_sve2, sve2_sminp)
125
+DO_ZPZZ(UMINP, aa64_sve2, sve2_uminp)
126
127
-DO_SVE2_ZPZZ(ADDP, addp)
128
-DO_SVE2_ZPZZ(SMAXP, smaxp)
129
-DO_SVE2_ZPZZ(UMAXP, umaxp)
130
-DO_SVE2_ZPZZ(SMINP, sminp)
131
-DO_SVE2_ZPZZ(UMINP, uminp)
132
-
133
-DO_SVE2_ZPZZ(SQADD_zpzz, sqadd)
134
-DO_SVE2_ZPZZ(UQADD_zpzz, uqadd)
135
-DO_SVE2_ZPZZ(SQSUB_zpzz, sqsub)
136
-DO_SVE2_ZPZZ(UQSUB_zpzz, uqsub)
137
-DO_SVE2_ZPZZ(SUQADD, suqadd)
138
-DO_SVE2_ZPZZ(USQADD, usqadd)
139
+DO_ZPZZ(SQADD_zpzz, aa64_sve2, sve2_sqadd)
140
+DO_ZPZZ(UQADD_zpzz, aa64_sve2, sve2_uqadd)
141
+DO_ZPZZ(SQSUB_zpzz, aa64_sve2, sve2_sqsub)
142
+DO_ZPZZ(UQSUB_zpzz, aa64_sve2, sve2_uqsub)
143
+DO_ZPZZ(SUQADD, aa64_sve2, sve2_suqadd)
144
+DO_ZPZZ(USQADD, aa64_sve2, sve2_usqadd)
145
146
/*
147
* SVE2 Widening Integer Arithmetic
148
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
149
DO_SVE2_PPZZ_MATCH(MATCH, match)
150
DO_SVE2_PPZZ_MATCH(NMATCH, nmatch)
151
152
-static bool trans_HISTCNT(DisasContext *s, arg_rprr_esz *a)
153
-{
154
- static gen_helper_gvec_4 * const fns[2] = {
155
- gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
156
- };
157
- if (a->esz < 2) {
158
- return false;
159
- }
160
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 2]);
161
-}
162
+static gen_helper_gvec_4 * const histcnt_fns[4] = {
163
+ NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
164
+};
165
+TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
166
+ histcnt_fns[a->esz], a, 0)
167
168
TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
169
a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
170
--
171
2.25.1
diff view generated by jsdifflib
[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
[PULL 032/117] target/arm: Merge gen_gvec_fn_zz into do_mov_z
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This extension concerns changes to the External Debug interface,
3
There is only one caller for gen_gvec_fn_zz; inline it.
4
with Secure and Non-secure access to the debug registers, and all
5
of it is outside the scope of QEMU. Indicating support for this
6
is mandatory with FEAT_SEL2, which we do implement.
7
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-30-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
docs/system/arm/emulation.rst | 1 +
10
target/arm/translate-sve.c | 13 +++----------
14
target/arm/cpu64.c | 2 +-
11
1 file changed, 3 insertions(+), 10 deletions(-)
15
target/arm/cpu_tcg.c | 4 ++--
16
3 files changed, 4 insertions(+), 3 deletions(-)
17
12
18
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/emulation.rst
15
--- a/target/arm/translate-sve.c
21
+++ b/docs/system/arm/emulation.rst
16
+++ b/target/arm/translate-sve.c
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
23
- FEAT_DIT (Data Independent Timing instructions)
18
return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
24
- FEAT_DPB (DC CVAP instruction)
19
}
25
- FEAT_Debugv8p2 (Debug changes for v8.2)
20
26
+- FEAT_Debugv8p4 (Debug changes for v8.4)
21
-/* Invoke a vector expander on two Zregs. */
27
- FEAT_DotProd (Advanced SIMD dot product instructions)
22
-static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
28
- FEAT_FCMA (Floating-point complex number instructions)
23
- int esz, int rd, int rn)
29
- FEAT_FHM (Floating-point half-precision multiplication instructions)
24
-{
30
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
25
- unsigned vsz = vec_full_reg_size(s);
31
index XXXXXXX..XXXXXXX 100644
26
- gvec_fn(esz, vec_full_reg_offset(s, rd),
32
--- a/target/arm/cpu64.c
27
- vec_full_reg_offset(s, rn), vsz, vsz);
33
+++ b/target/arm/cpu64.c
28
-}
34
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
29
-
35
cpu->isar.id_aa64zfr0 = t;
30
/* Invoke a vector expander on three Zregs. */
36
31
static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
37
t = cpu->isar.id_aa64dfr0;
32
int esz, int rd, int rn, int rm)
38
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
33
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
39
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
34
static bool do_mov_z(DisasContext *s, int rd, int rn)
40
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
35
{
41
cpu->isar.id_aa64dfr0 = t;
36
if (sve_access_check(s)) {
42
37
- gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
43
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
38
+ unsigned vsz = vec_full_reg_size(s);
44
index XXXXXXX..XXXXXXX 100644
39
+ tcg_gen_gvec_mov(MO_8, vec_full_reg_offset(s, rd),
45
--- a/target/arm/cpu_tcg.c
40
+ vec_full_reg_offset(s, rn), vsz, vsz);
46
+++ b/target/arm/cpu_tcg.c
41
}
47
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
42
return true;
48
cpu->isar.id_pfr2 = t;
49
50
t = cpu->isar.id_dfr0;
51
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
52
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
53
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
54
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
55
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
56
cpu->isar.id_dfr0 = t;
57
}
43
}
58
--
44
--
59
2.25.1
45
2.25.1
diff view generated by jsdifflib
New patch
[PULL 033/117] target/arm: Move null function and sve check into gen_gvec_fn_zzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-31-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 36 +++++++++++++++---------------------
9
1 file changed, 15 insertions(+), 21 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
16
}
17
18
/* Invoke a vector expander on three Zregs. */
19
-static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
20
+static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
21
int esz, int rd, int rn, int rm)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- gvec_fn(esz, vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm), vsz, vsz);
27
+ if (gvec_fn == NULL) {
28
+ return false;
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
33
+ vec_full_reg_offset(s, rn),
34
+ vec_full_reg_offset(s, rm), vsz, vsz);
35
+ }
36
+ return true;
37
}
38
39
/* Invoke a vector expander on four Zregs. */
40
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
41
42
static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
43
{
44
- if (sve_access_check(s)) {
45
- gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
46
- }
47
- return true;
48
+ return gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
49
}
50
51
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
52
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
53
if (!dc_isar_feature(aa64_sve2, s)) {
54
return false;
55
}
56
- if (sve_access_check(s)) {
57
- gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
58
- }
59
- return true;
60
+ return gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
61
}
62
63
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
64
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
65
if (!dc_isar_feature(aa64_sve2, s)) {
66
return false;
67
}
68
- if (sve_access_check(s)) {
69
- gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
70
- }
71
- return true;
72
+ return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
73
}
74
75
static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
76
@@ -XXX,XX +XXX,XX @@ static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
77
if (!dc_isar_feature(aa64_sve2_sha3, s)) {
78
return false;
79
}
80
- if (sve_access_check(s)) {
81
- gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
82
- }
83
- return true;
84
+ return gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
85
}
86
87
static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
88
--
89
2.25.1
diff view generated by jsdifflib
[PULL 16/32] target/arm: Implement virtual SError exceptions
[PULL 034/117] target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
3
Rename the function to match gen_gvec_fn_zzz,
4
and are routed to EL1 just like other virtual exceptions.
4
and move to be adjacent.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-32-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/cpu.h | 2 ++
11
target/arm/translate-sve.c | 31 ++++++++++++++++---------------
12
target/arm/internals.h | 8 ++++++++
12
1 file changed, 16 insertions(+), 15 deletions(-)
13
target/arm/syndrome.h | 5 +++++
14
target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++-
15
target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++-
16
5 files changed, 91 insertions(+), 2 deletions(-)
17
13
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
16
--- a/target/arm/translate-sve.c
21
+++ b/target/arm/cpu.h
17
+++ b/target/arm/translate-sve.c
22
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
23
#define EXCP_LSERR 21 /* v8M LSERR SecureFault */
19
return true;
24
#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
25
#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
26
+#define EXCP_VSERR 24
27
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
28
29
#define ARMV7M_EXCP_RESET 1
30
@@ -XXX,XX +XXX,XX @@ enum {
31
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
32
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
33
#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
34
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
35
36
/* The usual mapping for an AArch64 system register to its AArch32
37
* counterpart is for the 32 bit world to have access to the lower
38
diff --git a/target/arm/internals.h b/target/arm/internals.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/internals.h
41
+++ b/target/arm/internals.h
42
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
43
*/
44
void arm_cpu_update_vfiq(ARMCPU *cpu);
45
46
+/**
47
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
48
+ *
49
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
50
+ * following a change to the HCR_EL2.VSE bit.
51
+ */
52
+void arm_cpu_update_vserr(ARMCPU *cpu);
53
+
54
/**
55
* arm_mmu_idx_el:
56
* @env: The cpu environment
57
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/syndrome.h
60
+++ b/target/arm/syndrome.h
61
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
62
return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
63
}
20
}
64
21
65
+static inline uint32_t syn_serror(uint32_t extra)
22
+static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn,
23
+ arg_rrr_esz *a)
66
+{
24
+{
67
+ return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
25
+ return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
68
+}
26
+}
69
+
27
+
70
#endif /* TARGET_ARM_SYNDROME_H */
28
/* Invoke a vector expander on four Zregs. */
71
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
29
static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
72
index XXXXXXX..XXXXXXX 100644
30
int esz, int rd, int rn, int rm, int ra)
73
--- a/target/arm/cpu.c
31
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
74
+++ b/target/arm/cpu.c
32
*** SVE Logical - Unpredicated Group
75
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
33
*/
76
return (cpu->power_state != PSCI_OFF)
34
77
&& cs->interrupt_request &
35
-static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
78
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
36
-{
79
- | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
37
- return gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
80
+ | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
38
-}
81
| CPU_INTERRUPT_EXITTB);
39
-
40
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
41
{
42
- return do_zzz_fn(s, a, tcg_gen_gvec_and);
43
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_and, a);
82
}
44
}
83
45
84
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
46
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
85
return false;
47
{
86
}
48
- return do_zzz_fn(s, a, tcg_gen_gvec_or);
87
return !(env->daif & PSTATE_I);
49
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_or, a);
88
+ case EXCP_VSERR:
89
+ if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
90
+ /* VIRQs are only taken when hypervized. */
91
+ return false;
92
+ }
93
+ return !(env->daif & PSTATE_A);
94
default:
95
g_assert_not_reached();
96
}
97
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
98
goto found;
99
}
100
}
101
+ if (interrupt_request & CPU_INTERRUPT_VSERR) {
102
+ excp_idx = EXCP_VSERR;
103
+ target_el = 1;
104
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
105
+ cur_el, secure, hcr_el2)) {
106
+ /* Taking a virtual abort clears HCR_EL2.VSE */
107
+ env->cp15.hcr_el2 &= ~HCR_VSE;
108
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
109
+ goto found;
110
+ }
111
+ }
112
return false;
113
114
found:
115
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
116
}
117
}
50
}
118
51
119
+void arm_cpu_update_vserr(ARMCPU *cpu)
52
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
120
+{
121
+ /*
122
+ * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
123
+ */
124
+ CPUARMState *env = &cpu->env;
125
+ CPUState *cs = CPU(cpu);
126
+
127
+ bool new_state = env->cp15.hcr_el2 & HCR_VSE;
128
+
129
+ if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
130
+ if (new_state) {
131
+ cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
132
+ } else {
133
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
134
+ }
135
+ }
136
+}
137
+
138
#ifndef CONFIG_USER_ONLY
139
static void arm_cpu_set_irq(void *opaque, int irq, int level)
140
{
53
{
141
diff --git a/target/arm/helper.c b/target/arm/helper.c
54
- return do_zzz_fn(s, a, tcg_gen_gvec_xor);
142
index XXXXXXX..XXXXXXX 100644
55
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_xor, a);
143
--- a/target/arm/helper.c
144
+++ b/target/arm/helper.c
145
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
146
}
147
}
148
149
- /* External aborts are not possible in QEMU so A bit is always clear */
150
+ if (hcr_el2 & HCR_AMO) {
151
+ if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
152
+ ret |= CPSR_A;
153
+ }
154
+ }
155
+
156
return ret;
157
}
56
}
158
57
159
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
58
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
160
g_assert(qemu_mutex_iothread_locked());
59
{
161
arm_cpu_update_virq(cpu);
60
- return do_zzz_fn(s, a, tcg_gen_gvec_andc);
162
arm_cpu_update_vfiq(cpu);
61
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_andc, a);
163
+ arm_cpu_update_vserr(cpu);
164
}
62
}
165
63
166
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
64
static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh)
167
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
65
@@ -XXX,XX +XXX,XX @@ static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
168
[EXCP_LSERR] = "v8M LSERR UsageFault",
66
169
[EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
67
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
170
[EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
68
{
171
+ [EXCP_VSERR] = "Virtual SERR",
69
- return do_zzz_fn(s, a, tcg_gen_gvec_add);
172
};
70
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_add, a);
173
71
}
174
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
72
175
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
73
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
176
mask = CPSR_A | CPSR_I | CPSR_F;
74
{
177
offset = 4;
75
- return do_zzz_fn(s, a, tcg_gen_gvec_sub);
178
break;
76
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sub, a);
179
+ case EXCP_VSERR:
77
}
180
+ {
78
181
+ /*
79
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
182
+ * Note that this is reported as a data abort, but the DFAR
80
{
183
+ * has an UNKNOWN value. Construct the SError syndrome from
81
- return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
184
+ * AET and ExT fields.
82
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ssadd, a);
185
+ */
83
}
186
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
84
187
+
85
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
188
+ if (extended_addresses_enabled(env)) {
86
{
189
+ env->exception.fsr = arm_fi_to_lfsc(&fi);
87
- return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
190
+ } else {
88
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sssub, a);
191
+ env->exception.fsr = arm_fi_to_sfsc(&fi);
89
}
192
+ }
90
193
+ env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
91
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
194
+ A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
92
{
195
+ qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
93
- return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
196
+ env->exception.fsr);
94
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_usadd, a);
197
+
95
}
198
+ new_mode = ARM_CPU_MODE_ABT;
96
199
+ addr = 0x10;
97
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
200
+ mask = CPSR_A | CPSR_I;
98
{
201
+ offset = 8;
99
- return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
202
+ }
100
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ussub, a);
203
+ break;
101
}
204
case EXCP_SMC:
102
205
new_mode = ARM_CPU_MODE_MON;
103
/*
206
addr = 0x08;
207
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
208
case EXCP_VFIQ:
209
addr += 0x100;
210
break;
211
+ case EXCP_VSERR:
212
+ addr += 0x180;
213
+ /* Construct the SError syndrome from IDS and ISS fields. */
214
+ env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
215
+ env->cp15.esr_el[new_el] = env->exception.syndrome;
216
+ break;
217
default:
218
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
219
}
220
--
104
--
221
2.25.1
105
2.25.1
diff view generated by jsdifflib
New patch
[PULL 035/117] target/arm: More use of gen_gvec_fn_arg_zzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Two uses of gen_gvec_fn_zzz can pass on arg_rrr_esz instead.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-33-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
18
if (!dc_isar_feature(aa64_sve2, s)) {
19
return false;
20
}
21
- return gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
22
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_mul, a);
23
}
24
25
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
26
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
27
if (!dc_isar_feature(aa64_sve2, s)) {
28
return false;
29
}
30
- return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
31
+ return gen_gvec_fn_arg_zzz(s, fn, a);
32
}
33
34
static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
35
--
36
2.25.1
diff view generated by jsdifflib
New patch
[PULL 036/117] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_fn_arg_zzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-34-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 66 +++++++-------------------------------
12
1 file changed, 11 insertions(+), 55 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
19
*** SVE Logical - Unpredicated Group
20
*/
21
22
-static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
23
-{
24
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_and, a);
25
-}
26
-
27
-static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
28
-{
29
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_or, a);
30
-}
31
-
32
-static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
33
-{
34
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_xor, a);
35
-}
36
-
37
-static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
38
-{
39
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_andc, a);
40
-}
41
+TRANS_FEAT(AND_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and, a)
42
+TRANS_FEAT(ORR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or, a)
43
+TRANS_FEAT(EOR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor, a)
44
+TRANS_FEAT(BIC_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_andc, a)
45
46
static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh)
47
{
48
@@ -XXX,XX +XXX,XX @@ static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
49
*** SVE Integer Arithmetic - Unpredicated Group
50
*/
51
52
-static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
53
-{
54
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_add, a);
55
-}
56
-
57
-static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
58
-{
59
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sub, a);
60
-}
61
-
62
-static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
63
-{
64
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ssadd, a);
65
-}
66
-
67
-static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
68
-{
69
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sssub, a);
70
-}
71
-
72
-static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
73
-{
74
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_usadd, a);
75
-}
76
-
77
-static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
78
-{
79
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ussub, a);
80
-}
81
+TRANS_FEAT(ADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add, a)
82
+TRANS_FEAT(SUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub, a)
83
+TRANS_FEAT(SQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ssadd, a)
84
+TRANS_FEAT(SQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sssub, a)
85
+TRANS_FEAT(UQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_usadd, a)
86
+TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a)
87
88
/*
89
*** SVE Integer Arithmetic - Binary Predicated Group
90
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
91
* SVE2 Integer Multiply - Unpredicated
92
*/
93
94
-static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
95
-{
96
- if (!dc_isar_feature(aa64_sve2, s)) {
97
- return false;
98
- }
99
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_mul, a);
100
-}
101
+TRANS_FEAT(MUL_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mul, a)
102
103
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
104
gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
105
--
106
2.25.1
diff view generated by jsdifflib
New patch
[PULL 037/117] target/arm: Use TRANS_FEAT for do_sve2_fn_zzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_fn_zzz
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-35-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 19 ++-----------------
12
1 file changed, 2 insertions(+), 17 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SLI(DisasContext *s, arg_rri_esz *a)
19
return do_sve2_fn2i(s, a, gen_gvec_sli);
20
}
21
22
-static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
23
-{
24
- if (!dc_isar_feature(aa64_sve2, s)) {
25
- return false;
26
- }
27
- return gen_gvec_fn_arg_zzz(s, fn, a);
28
-}
29
-
30
-static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
31
-{
32
- return do_sve2_fn_zzz(s, a, gen_gvec_saba);
33
-}
34
-
35
-static bool trans_UABA(DisasContext *s, arg_rrr_esz *a)
36
-{
37
- return do_sve2_fn_zzz(s, a, gen_gvec_uaba);
38
-}
39
+TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a)
40
+TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a)
41
42
static bool do_sve2_narrow_extract(DisasContext *s, arg_rri_esz *a,
43
const GVecGen2 ops[3])
44
--
45
2.25.1
diff view generated by jsdifflib
New patch
[PULL 038/117] target/arm: Use TRANS_FEAT for RAX1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The decode for RAX1 sets esz to MO_8, because that's what
4
we use by default for "no esz present". We changed that
5
to MO_64 during translation because it is more logical for
6
the operation. However, the esz argument to gen_gvec_rax1
7
is unused and forces MO_64 within that function, so there
8
is no need to do it here as well.
9
10
Simplify to use gen_gvec_fn_arg_zzz and TRANS_FEAT.
11
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220527181907.189259-36-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/translate-sve.c | 8 +-------
18
1 file changed, 1 insertion(+), 7 deletions(-)
19
20
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/translate-sve.c
23
+++ b/target/arm/translate-sve.c
24
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
25
TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
26
gen_helper_crypto_sm4ekey, a, 0)
27
28
-static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
29
-{
30
- if (!dc_isar_feature(aa64_sve2_sha3, s)) {
31
- return false;
32
- }
33
- return gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
34
-}
35
+TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
36
37
static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
38
{
39
--
40
2.25.1
diff view generated by jsdifflib
New patch
[PULL 039/117] target/arm: Introduce gen_gvec_fn_arg_zzzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Merge gen_gvec_fn_zzzz with the sve access check and the
4
dereference of arg_rrrr_esz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-37-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 25 ++++++++++++++-----------
12
1 file changed, 14 insertions(+), 11 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn,
19
}
20
21
/* Invoke a vector expander on four Zregs. */
22
-static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
23
- int esz, int rd, int rn, int rm, int ra)
24
+static bool gen_gvec_fn_arg_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
25
+ arg_rrrr_esz *a)
26
{
27
- unsigned vsz = vec_full_reg_size(s);
28
- gvec_fn(esz, vec_full_reg_offset(s, rd),
29
- vec_full_reg_offset(s, rn),
30
- vec_full_reg_offset(s, rm),
31
- vec_full_reg_offset(s, ra), vsz, vsz);
32
+ if (gvec_fn == NULL) {
33
+ return false;
34
+ }
35
+ if (sve_access_check(s)) {
36
+ unsigned vsz = vec_full_reg_size(s);
37
+ gvec_fn(a->esz, vec_full_reg_offset(s, a->rd),
38
+ vec_full_reg_offset(s, a->rn),
39
+ vec_full_reg_offset(s, a->rm),
40
+ vec_full_reg_offset(s, a->ra), vsz, vsz);
41
+ }
42
+ return true;
43
}
44
45
/* Invoke a vector move on two Zregs. */
46
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn)
47
if (!dc_isar_feature(aa64_sve2, s)) {
48
return false;
49
}
50
- if (sve_access_check(s)) {
51
- gen_gvec_fn_zzzz(s, fn, a->esz, a->rd, a->rn, a->rm, a->ra);
52
- }
53
- return true;
54
+ return gen_gvec_fn_arg_zzzz(s, fn, a);
55
}
56
57
static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
58
--
59
2.25.1
diff view generated by jsdifflib
New patch
[PULL 040/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zzzz_fn
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-38-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 38 ++++++--------------------------------
12
1 file changed, 6 insertions(+), 32 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_XAR(DisasContext *s, arg_rrri_esz *a)
19
return true;
20
}
21
22
-static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn)
23
-{
24
- if (!dc_isar_feature(aa64_sve2, s)) {
25
- return false;
26
- }
27
- return gen_gvec_fn_arg_zzzz(s, fn, a);
28
-}
29
-
30
static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
31
{
32
tcg_gen_xor_i64(d, n, m);
33
@@ -XXX,XX +XXX,XX @@ static void gen_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
34
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
35
}
36
37
-static bool trans_EOR3(DisasContext *s, arg_rrrr_esz *a)
38
-{
39
- return do_sve2_zzzz_fn(s, a, gen_eor3);
40
-}
41
+TRANS_FEAT(EOR3, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_eor3, a)
42
43
static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
44
{
45
@@ -XXX,XX +XXX,XX @@ static void gen_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
46
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
47
}
48
49
-static bool trans_BCAX(DisasContext *s, arg_rrrr_esz *a)
50
-{
51
- return do_sve2_zzzz_fn(s, a, gen_bcax);
52
-}
53
+TRANS_FEAT(BCAX, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bcax, a)
54
55
static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
56
uint32_t a, uint32_t oprsz, uint32_t maxsz)
57
@@ -XXX,XX +XXX,XX @@ static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
58
tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz);
59
}
60
61
-static bool trans_BSL(DisasContext *s, arg_rrrr_esz *a)
62
-{
63
- return do_sve2_zzzz_fn(s, a, gen_bsl);
64
-}
65
+TRANS_FEAT(BSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a)
66
67
static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
68
{
69
@@ -XXX,XX +XXX,XX @@ static void gen_bsl1n(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
70
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
71
}
72
73
-static bool trans_BSL1N(DisasContext *s, arg_rrrr_esz *a)
74
-{
75
- return do_sve2_zzzz_fn(s, a, gen_bsl1n);
76
-}
77
+TRANS_FEAT(BSL1N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a)
78
79
static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
80
{
81
@@ -XXX,XX +XXX,XX @@ static void gen_bsl2n(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
82
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
83
}
84
85
-static bool trans_BSL2N(DisasContext *s, arg_rrrr_esz *a)
86
-{
87
- return do_sve2_zzzz_fn(s, a, gen_bsl2n);
88
-}
89
+TRANS_FEAT(BSL2N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a)
90
91
static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
92
{
93
@@ -XXX,XX +XXX,XX @@ static void gen_nbsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
94
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
95
}
96
97
-static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
98
-{
99
- return do_sve2_zzzz_fn(s, a, gen_nbsl);
100
-}
101
+TRANS_FEAT(NBSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a)
102
103
/*
104
*** SVE Integer Arithmetic - Unpredicated Group
105
--
106
2.25.1
diff view generated by jsdifflib
[PULL 24/32] target/arm: Define cortex-a76
[PULL 041/117] target/arm: Introduce gen_gvec_fn_zzi
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Enable the a76 for virt and sbsa board use.
3
We have two places that perform this particular operation.
4
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-39-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
9
---
10
docs/system/arm/virt.rst | 1 +
10
target/arm/translate-sve.c | 30 +++++++++++++++++-------------
11
hw/arm/sbsa-ref.c | 1 +
11
1 file changed, 17 insertions(+), 13 deletions(-)
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
15
12
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/virt.rst
15
--- a/target/arm/translate-sve.c
19
+++ b/docs/system/arm/virt.rst
16
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
21
- ``cortex-a53`` (64-bit)
18
return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
22
- ``cortex-a57`` (64-bit)
23
- ``cortex-a72`` (64-bit)
24
+- ``cortex-a76`` (64-bit)
25
- ``a64fx`` (64-bit)
26
- ``host`` (with KVM only)
27
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/sbsa-ref.c
31
+++ b/hw/arm/sbsa-ref.c
32
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
33
static const char * const valid_cpus[] = {
34
ARM_CPU_TYPE_NAME("cortex-a57"),
35
ARM_CPU_TYPE_NAME("cortex-a72"),
36
+ ARM_CPU_TYPE_NAME("cortex-a76"),
37
ARM_CPU_TYPE_NAME("max"),
38
};
39
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a53"),
46
ARM_CPU_TYPE_NAME("cortex-a57"),
47
ARM_CPU_TYPE_NAME("cortex-a72"),
48
+ ARM_CPU_TYPE_NAME("cortex-a76"),
49
ARM_CPU_TYPE_NAME("a64fx"),
50
ARM_CPU_TYPE_NAME("host"),
51
ARM_CPU_TYPE_NAME("max"),
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
57
define_cortex_a72_a57_a53_cp_reginfo(cpu);
58
}
19
}
59
20
60
+static void aarch64_a76_initfn(Object *obj)
21
+/* Invoke a vector expander on two Zregs and an immediate. */
22
+static bool gen_gvec_fn_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
23
+ int esz, int rd, int rn, uint64_t imm)
61
+{
24
+{
62
+ ARMCPU *cpu = ARM_CPU(obj);
25
+ if (gvec_fn == NULL) {
63
+
26
+ return false;
64
+ cpu->dtb_compatible = "arm,cortex-a76";
27
+ }
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
28
+ if (sve_access_check(s)) {
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
29
+ unsigned vsz = vec_full_reg_size(s);
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
30
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
31
+ vec_full_reg_offset(s, rn), imm, vsz, vsz);
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
32
+ }
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
33
+ return true;
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
73
+
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
75
+ cpu->clidr = 0x82000023;
76
+ cpu->ctr = 0x8444C004;
77
+ cpu->dcz_blocksize = 4;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0b1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.18 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
110
+
111
+ /* From B2.93 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
123
+}
34
+}
124
+
35
+
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
36
/* Invoke a vector expander on three Zregs. */
126
{
37
static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
127
/*
38
int esz, int rd, int rn, int rm)
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
39
@@ -XXX,XX +XXX,XX @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
129
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
40
extract32(a->dbm, 6, 6))) {
130
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
41
return false;
131
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
42
}
132
+ { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
43
- if (sve_access_check(s)) {
133
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
44
- unsigned vsz = vec_full_reg_size(s);
134
{ .name = "max", .initfn = aarch64_max_initfn },
45
- gvec_fn(MO_64, vec_full_reg_offset(s, a->rd),
135
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
46
- vec_full_reg_offset(s, a->rn), imm, vsz, vsz);
47
- }
48
- return true;
49
+ return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm);
50
}
51
52
static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a)
53
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
54
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
55
return false;
56
}
57
- if (sve_access_check(s)) {
58
- unsigned vsz = vec_full_reg_size(s);
59
- unsigned rd_ofs = vec_full_reg_offset(s, a->rd);
60
- unsigned rn_ofs = vec_full_reg_offset(s, a->rn);
61
- fn(a->esz, rd_ofs, rn_ofs, a->imm, vsz, vsz);
62
- }
63
- return true;
64
+ return gen_gvec_fn_zzi(s, fn, a->esz, a->rd, a->rn, a->imm);
65
}
66
67
static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
136
--
68
--
137
2.25.1
69
2.25.1
diff view generated by jsdifflib
New patch
[PULL 042/117] target/arm: Use TRANS_FEAT for do_zz_dbm
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-40-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
16
return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm);
17
}
18
19
-static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a)
20
-{
21
- return do_zz_dbm(s, a, tcg_gen_gvec_andi);
22
-}
23
-
24
-static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a)
25
-{
26
- return do_zz_dbm(s, a, tcg_gen_gvec_ori);
27
-}
28
-
29
-static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a)
30
-{
31
- return do_zz_dbm(s, a, tcg_gen_gvec_xori);
32
-}
33
+TRANS_FEAT(AND_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_andi)
34
+TRANS_FEAT(ORR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_ori)
35
+TRANS_FEAT(EOR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_xori)
36
37
static bool trans_DUPM(DisasContext *s, arg_DUPM *a)
38
{
39
--
40
2.25.1
diff view generated by jsdifflib
New patch
[PULL 043/117] target/arm: Hoist sve access check through do_sel_z
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The check is already done in gen_gvec_ool_zzzp,
4
which is called by do_sel_z; remove from callers.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-41-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 14 ++++----------
12
1 file changed, 4 insertions(+), 10 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a)
19
/* Select active elememnts from Zn and inactive elements from Zm,
20
* storing the result in Zd.
21
*/
22
-static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
23
+static bool do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
24
{
25
static gen_helper_gvec_4 * const fns[4] = {
26
gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
27
gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
28
};
29
- gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
30
+ return gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
31
}
32
33
#define DO_ZPZZ(NAME, FEAT, name) \
34
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
35
36
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
37
{
38
- if (sve_access_check(s)) {
39
- do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
40
- }
41
- return true;
42
+ return do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
43
}
44
45
/*
46
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a)
47
48
static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
49
{
50
- if (sve_access_check(s)) {
51
- do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
52
- }
53
- return true;
54
+ return do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
55
}
56
57
static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
58
--
59
2.25.1
diff view generated by jsdifflib
[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
[PULL 044/117] target/arm: Introduce gen_gvec_fn_arg_zzi
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
There is no branch prediction in TCG, therefore there is no
3
We have two places that perform this particular operation.
4
need to actually include the context number into the predictor.
5
Therefore all we need to do is add the state for SCXTNUM_ELx.
6
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-42-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
docs/system/arm/emulation.rst | 3 ++
10
target/arm/translate-sve.c | 21 +++++++++++++--------
13
target/arm/cpu.h | 16 +++++++++
11
1 file changed, 13 insertions(+), 8 deletions(-)
14
target/arm/cpu.c | 5 +++
15
target/arm/cpu64.c | 3 +-
16
target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++-
17
5 files changed, 86 insertions(+), 2 deletions(-)
18
12
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
15
--- a/target/arm/translate-sve.c
22
+++ b/docs/system/arm/emulation.rst
16
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
24
- FEAT_BF16 (AArch64 BFloat16 instructions)
18
return true;
25
- FEAT_BTI (Branch Target Identification)
26
- FEAT_CSV2 (Cache speculation variant 2)
27
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
28
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
29
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
30
- FEAT_DIT (Data Independent Timing instructions)
31
- FEAT_DPB (DC CVAP instruction)
32
- FEAT_Debugv8p2 (Debug changes for v8.2)
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
36
+++ b/target/arm/cpu.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
38
ARMPACKey apdb;
39
ARMPACKey apga;
40
} keys;
41
+
42
+ uint64_t scxtnum_el[4];
43
#endif
44
45
#if defined(CONFIG_USER_ONLY)
46
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
47
#define SCTLR_WXN (1U << 19)
48
#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
49
#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
50
+#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
51
#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
52
#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
53
#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
54
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
55
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
56
}
19
}
57
20
58
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
21
+static bool gen_gvec_fn_arg_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
22
+ arg_rri_esz *a)
59
+{
23
+{
60
+ int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
24
+ if (a->esz < 0) {
61
+ if (key >= 2) {
25
+ /* Invalid tsz encoding -- see tszimm_esz. */
62
+ return true; /* FEAT_CSV2_2 */
26
+ return false;
63
+ }
27
+ }
64
+ if (key == 1) {
28
+ return gen_gvec_fn_zzi(s, gvec_fn, a->esz, a->rd, a->rn, a->imm);
65
+ key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
66
+ return key >= 2; /* FEAT_CSV2_1p2 */
67
+ }
68
+ return false;
69
+}
29
+}
70
+
30
+
71
static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
31
/* Invoke a vector expander on three Zregs. */
32
static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
33
int esz, int rd, int rn, int rm)
34
@@ -XXX,XX +XXX,XX @@ static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
35
if (a->esz == 0 && extract32(s->insn, 13, 1)) {
36
return false;
37
}
38
- if (sve_access_check(s)) {
39
- unsigned vsz = vec_full_reg_size(s);
40
- tcg_gen_gvec_addi(a->esz, vec_full_reg_offset(s, a->rd),
41
- vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz);
42
- }
43
- return true;
44
+ return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
45
}
46
47
static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a)
48
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
49
50
static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
72
{
51
{
73
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
52
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
74
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
53
+ if (!dc_isar_feature(aa64_sve2, s)) {
75
index XXXXXXX..XXXXXXX 100644
54
return false;
76
--- a/target/arm/cpu.c
77
+++ b/target/arm/cpu.c
78
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
79
*/
80
env->cp15.gcr_el1 = 0x1ffff;
81
}
82
+ /*
83
+ * Disable access to SCXTNUM_EL0 from CSV2_1p2.
84
+ * This is not yet exposed from the Linux kernel in any way.
85
+ */
86
+ env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
87
#else
88
/* Reset into the highest available EL */
89
if (arm_feature(env, ARM_FEATURE_EL3)) {
90
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/cpu64.c
93
+++ b/target/arm/cpu64.c
94
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
95
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
96
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
97
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
98
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
99
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
100
cpu->isar.id_aa64pfr0 = t;
101
102
t = cpu->isar.id_aa64pfr1;
103
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
104
* we do for EL2 with the virtualization=on property.
105
*/
106
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
107
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
108
cpu->isar.id_aa64pfr1 = t;
109
110
t = cpu->isar.id_aa64mmfr0;
111
diff --git a/target/arm/helper.c b/target/arm/helper.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/helper.c
114
+++ b/target/arm/helper.c
115
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
116
if (cpu_isar_feature(aa64_mte, cpu)) {
117
valid_mask |= SCR_ATA;
118
}
119
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
120
+ valid_mask |= SCR_ENSCXT;
121
+ }
122
} else {
123
valid_mask &= ~(SCR_RW | SCR_ST);
124
if (cpu_isar_feature(aa32_ras, cpu)) {
125
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
126
if (cpu_isar_feature(aa64_mte, cpu)) {
127
valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
128
}
129
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
130
+ valid_mask |= HCR_ENSCXT;
131
+ }
132
}
55
}
133
56
- return gen_gvec_fn_zzi(s, fn, a->esz, a->rd, a->rn, a->imm);
134
/* Clear RES0 bits. */
57
+ return gen_gvec_fn_arg_zzi(s, fn, a);
135
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
58
}
136
{ K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
59
137
"TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
60
static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
138
139
+ { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
140
+ "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
141
+ isar_feature_aa64_scxtnum },
142
+
143
/* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
144
/* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
145
};
146
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
147
},
148
};
149
150
-#endif
151
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
152
+ bool isread)
153
+{
154
+ uint64_t hcr = arm_hcr_el2_eff(env);
155
+ int el = arm_current_el(env);
156
+
157
+ if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
158
+ if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
159
+ if (hcr & HCR_TGE) {
160
+ return CP_ACCESS_TRAP_EL2;
161
+ }
162
+ return CP_ACCESS_TRAP;
163
+ }
164
+ } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
165
+ return CP_ACCESS_TRAP_EL2;
166
+ }
167
+ if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
168
+ return CP_ACCESS_TRAP_EL2;
169
+ }
170
+ if (el < 3
171
+ && arm_feature(env, ARM_FEATURE_EL3)
172
+ && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
173
+ return CP_ACCESS_TRAP_EL3;
174
+ }
175
+ return CP_ACCESS_OK;
176
+}
177
+
178
+static const ARMCPRegInfo scxtnum_reginfo[] = {
179
+ { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
180
+ .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
181
+ .access = PL0_RW, .accessfn = access_scxtnum,
182
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
183
+ { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
184
+ .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
185
+ .access = PL1_RW, .accessfn = access_scxtnum,
186
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
187
+ { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
188
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
189
+ .access = PL2_RW, .accessfn = access_scxtnum,
190
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
191
+ { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
192
+ .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
193
+ .access = PL3_RW,
194
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
195
+};
196
+#endif /* TARGET_AARCH64 */
197
198
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
199
bool isread)
200
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
201
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
202
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
203
}
204
+
205
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
206
+ define_arm_cp_regs(cpu, scxtnum_reginfo);
207
+ }
208
#endif
209
210
if (cpu_isar_feature(any_predinv, cpu)) {
211
--
61
--
212
2.25.1
62
2.25.1
diff view generated by jsdifflib
New patch
[PULL 045/117] target/arm: Use TRANS_FEAT for do_sve2_fn2i
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_fn2i
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzi.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-43-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 43 ++++++--------------------------------
12
1 file changed, 6 insertions(+), 37 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
19
TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false)
20
TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
21
22
-static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
23
-{
24
- if (!dc_isar_feature(aa64_sve2, s)) {
25
- return false;
26
- }
27
- return gen_gvec_fn_arg_zzi(s, fn, a);
28
-}
29
-
30
-static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
31
-{
32
- return do_sve2_fn2i(s, a, gen_gvec_ssra);
33
-}
34
-
35
-static bool trans_USRA(DisasContext *s, arg_rri_esz *a)
36
-{
37
- return do_sve2_fn2i(s, a, gen_gvec_usra);
38
-}
39
-
40
-static bool trans_SRSRA(DisasContext *s, arg_rri_esz *a)
41
-{
42
- return do_sve2_fn2i(s, a, gen_gvec_srsra);
43
-}
44
-
45
-static bool trans_URSRA(DisasContext *s, arg_rri_esz *a)
46
-{
47
- return do_sve2_fn2i(s, a, gen_gvec_ursra);
48
-}
49
-
50
-static bool trans_SRI(DisasContext *s, arg_rri_esz *a)
51
-{
52
- return do_sve2_fn2i(s, a, gen_gvec_sri);
53
-}
54
-
55
-static bool trans_SLI(DisasContext *s, arg_rri_esz *a)
56
-{
57
- return do_sve2_fn2i(s, a, gen_gvec_sli);
58
-}
59
+TRANS_FEAT(SSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ssra, a)
60
+TRANS_FEAT(USRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_usra, a)
61
+TRANS_FEAT(SRSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_srsra, a)
62
+TRANS_FEAT(URSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ursra, a)
63
+TRANS_FEAT(SRI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sri, a)
64
+TRANS_FEAT(SLI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sli, a)
65
66
TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a)
67
TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a)
68
--
69
2.25.1
diff view generated by jsdifflib
[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
[PULL 046/117] target/arm: Use TRANS_FEAT for do_vpz_ool
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Instead of starting with cortex-a15 and adding v8 features to
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
4
Message-id: 20220527181907.189259-44-richard.henderson@linaro.org
5
This fixes the long-standing to-do where we only enabled v8
6
features for user-only.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
7
---
13
target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
8
target/arm/translate-sve.c | 20 +++++++-------------
14
1 file changed, 92 insertions(+), 59 deletions(-)
9
1 file changed, 7 insertions(+), 13 deletions(-)
15
10
16
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu_tcg.c
13
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/cpu_tcg.c
14
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
15
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
21
static void arm_max_initfn(Object *obj)
22
{
23
ARMCPU *cpu = ARM_CPU(obj);
24
+ uint32_t t;
25
26
- cortex_a15_initfn(obj);
27
+ /* aarch64_a57_initfn, advertising none of the aarch64 features */
28
+ cpu->dtb_compatible = "arm,cortex-a57";
29
+ set_feature(&cpu->env, ARM_FEATURE_V8);
30
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
31
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
32
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
33
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
34
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
35
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
36
+ cpu->midr = 0x411fd070;
37
+ cpu->revidr = 0x00000000;
38
+ cpu->reset_fpsid = 0x41034070;
39
+ cpu->isar.mvfr0 = 0x10110222;
40
+ cpu->isar.mvfr1 = 0x12111111;
41
+ cpu->isar.mvfr2 = 0x00000043;
42
+ cpu->ctr = 0x8444c004;
43
+ cpu->reset_sctlr = 0x00c50838;
44
+ cpu->isar.id_pfr0 = 0x00000131;
45
+ cpu->isar.id_pfr1 = 0x00011011;
46
+ cpu->isar.id_dfr0 = 0x03010066;
47
+ cpu->id_afr0 = 0x00000000;
48
+ cpu->isar.id_mmfr0 = 0x10101105;
49
+ cpu->isar.id_mmfr1 = 0x40000000;
50
+ cpu->isar.id_mmfr2 = 0x01260000;
51
+ cpu->isar.id_mmfr3 = 0x02102211;
52
+ cpu->isar.id_isar0 = 0x02101110;
53
+ cpu->isar.id_isar1 = 0x13112111;
54
+ cpu->isar.id_isar2 = 0x21232042;
55
+ cpu->isar.id_isar3 = 0x01112131;
56
+ cpu->isar.id_isar4 = 0x00011142;
57
+ cpu->isar.id_isar5 = 0x00011121;
58
+ cpu->isar.id_isar6 = 0;
59
+ cpu->isar.dbgdidr = 0x3516d000;
60
+ cpu->clidr = 0x0a200023;
61
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
62
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
63
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
64
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
65
66
- /* old-style VFP short-vector support */
67
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
68
+ /* Add additional features supported by QEMU */
69
+ t = cpu->isar.id_isar5;
70
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
71
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
72
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
73
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
74
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
75
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
76
+ cpu->isar.id_isar5 = t;
77
+
78
+ t = cpu->isar.id_isar6;
79
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
80
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
81
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
82
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
83
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
84
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
85
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
86
+ cpu->isar.id_isar6 = t;
87
+
88
+ t = cpu->isar.mvfr1;
89
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
90
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
91
+ cpu->isar.mvfr1 = t;
92
+
93
+ t = cpu->isar.mvfr2;
94
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
95
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
96
+ cpu->isar.mvfr2 = t;
97
+
98
+ t = cpu->isar.id_mmfr3;
99
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
100
+ cpu->isar.id_mmfr3 = t;
101
+
102
+ t = cpu->isar.id_mmfr4;
103
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
104
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
105
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
106
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
107
+ cpu->isar.id_mmfr4 = t;
108
+
109
+ t = cpu->isar.id_pfr0;
110
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
111
+ cpu->isar.id_pfr0 = t;
112
+
113
+ t = cpu->isar.id_pfr2;
114
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
115
+ cpu->isar.id_pfr2 = t;
116
117
#ifdef CONFIG_USER_ONLY
118
/*
119
- * We don't set these in system emulation mode for the moment,
120
- * since we don't correctly set (all of) the ID registers to
121
- * advertise them.
122
+ * Break with true ARMv8 and add back old-style VFP short-vector support.
123
+ * Only do this for user-mode, where -cpu max is the default, so that
124
+ * older v6 and v7 programs are more likely to work without adjustment.
125
*/
126
- set_feature(&cpu->env, ARM_FEATURE_V8);
127
- {
128
- uint32_t t;
129
-
130
- t = cpu->isar.id_isar5;
131
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
132
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
133
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
134
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
135
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
136
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
137
- cpu->isar.id_isar5 = t;
138
-
139
- t = cpu->isar.id_isar6;
140
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
141
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
142
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
143
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
144
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
145
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
146
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
147
- cpu->isar.id_isar6 = t;
148
-
149
- t = cpu->isar.mvfr1;
150
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
151
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
152
- cpu->isar.mvfr1 = t;
153
-
154
- t = cpu->isar.mvfr2;
155
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
156
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
157
- cpu->isar.mvfr2 = t;
158
-
159
- t = cpu->isar.id_mmfr3;
160
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
161
- cpu->isar.id_mmfr3 = t;
162
-
163
- t = cpu->isar.id_mmfr4;
164
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
165
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
166
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
167
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
168
- cpu->isar.id_mmfr4 = t;
169
-
170
- t = cpu->isar.id_pfr0;
171
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
172
- cpu->isar.id_pfr0 = t;
173
-
174
- t = cpu->isar.id_pfr2;
175
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
176
- cpu->isar.id_pfr2 = t;
177
- }
178
-#endif /* CONFIG_USER_ONLY */
179
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
180
+#endif
181
}
16
}
182
#endif /* !TARGET_AARCH64 */
17
18
#define DO_VPZ(NAME, name) \
19
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
20
-{ \
21
- static gen_helper_gvec_reduc * const fns[4] = { \
22
+ static gen_helper_gvec_reduc * const name##_fns[4] = { \
23
gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
24
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
25
}; \
26
- return do_vpz_ool(s, a, fns[a->esz]); \
27
-}
28
+ TRANS_FEAT(NAME, aa64_sve, do_vpz_ool, a, name##_fns[a->esz])
29
30
DO_VPZ(ORV, orv)
31
DO_VPZ(ANDV, andv)
32
@@ -XXX,XX +XXX,XX @@ DO_VPZ(UMAXV, umaxv)
33
DO_VPZ(SMINV, sminv)
34
DO_VPZ(UMINV, uminv)
35
36
-static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a)
37
-{
38
- static gen_helper_gvec_reduc * const fns[4] = {
39
- gen_helper_sve_saddv_b, gen_helper_sve_saddv_h,
40
- gen_helper_sve_saddv_s, NULL
41
- };
42
- return do_vpz_ool(s, a, fns[a->esz]);
43
-}
44
+static gen_helper_gvec_reduc * const saddv_fns[4] = {
45
+ gen_helper_sve_saddv_b, gen_helper_sve_saddv_h,
46
+ gen_helper_sve_saddv_s, NULL
47
+};
48
+TRANS_FEAT(SADDV, aa64_sve, do_vpz_ool, a, saddv_fns[a->esz])
49
50
#undef DO_VPZ
183
51
184
--
52
--
185
2.25.1
53
2.25.1
diff view generated by jsdifflib
New patch
[PULL 047/117] target/arm: Use TRANS_FEAT for do_shift_imm
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-45-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_shift_imm(DisasContext *s, arg_rri_esz *a, bool asr,
16
return true;
17
}
18
19
-static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a)
20
-{
21
- return do_shift_imm(s, a, true, tcg_gen_gvec_sari);
22
-}
23
-
24
-static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a)
25
-{
26
- return do_shift_imm(s, a, false, tcg_gen_gvec_shri);
27
-}
28
-
29
-static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
30
-{
31
- return do_shift_imm(s, a, false, tcg_gen_gvec_shli);
32
-}
33
+TRANS_FEAT(ASR_zzi, aa64_sve, do_shift_imm, a, true, tcg_gen_gvec_sari)
34
+TRANS_FEAT(LSR_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shri)
35
+TRANS_FEAT(LSL_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shli)
36
37
#define DO_ZZW(NAME, name) \
38
static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \
39
--
40
2.25.1
diff view generated by jsdifflib
[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
[PULL 048/117] target/arm: Introduce do_shift_zpzi
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
3
Share code between the various shifts using arg_rpri_esz.
4
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
5
while registering for v8.
6
4
7
This is a behavior change for v7 cpus with Security Extensions and
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
without Virtualization Extensions, in that the virtualization cpregs
6
Message-id: 20220527181907.189259-46-richard.henderson@linaro.org
9
are now correctly not present. This would be a migration compatibility
10
break, except that we have an existing bug in which migration of 32-bit
11
cpus with Security Extensions enabled does not work.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
9
---
18
target/arm/helper.c | 158 ++++----------------------------------------
10
target/arm/translate-sve.c | 68 +++++++++++++++++---------------------
19
1 file changed, 13 insertions(+), 145 deletions(-)
11
1 file changed, 30 insertions(+), 38 deletions(-)
20
12
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
22
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
15
--- a/target/arm/translate-sve.c
24
+++ b/target/arm/helper.c
16
+++ b/target/arm/translate-sve.c
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
17
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
26
.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
18
return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
27
};
19
}
28
20
29
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
21
+static bool do_shift_zpzi(DisasContext *s, arg_rpri_esz *a, bool asr,
30
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
22
+ gen_helper_gvec_3 * const fns[4])
31
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
23
+{
32
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
24
+ int max;
33
- .access = PL2_RW,
25
+
34
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
26
+ if (a->esz < 0) {
35
- { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
27
+ /* Invalid tsz encoding -- see tszimm_esz. */
36
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
28
+ return false;
37
- .access = PL2_RW,
29
+ }
38
- .type = ARM_CP_CONST, .resetvalue = 0 },
39
- { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
40
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
41
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
- { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
43
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
44
- .access = PL2_RW,
45
- .type = ARM_CP_CONST, .resetvalue = 0 },
46
- { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
47
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
48
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49
- { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
50
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
51
- .access = PL2_RW, .type = ARM_CP_CONST,
52
- .resetvalue = 0 },
53
- { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
54
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
55
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
56
- { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
57
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
58
- .access = PL2_RW, .type = ARM_CP_CONST,
59
- .resetvalue = 0 },
60
- { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
61
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
62
- .access = PL2_RW, .type = ARM_CP_CONST,
63
- .resetvalue = 0 },
64
- { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
65
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
66
- .access = PL2_RW, .type = ARM_CP_CONST,
67
- .resetvalue = 0 },
68
- { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
69
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
70
- .access = PL2_RW, .type = ARM_CP_CONST,
71
- .resetvalue = 0 },
72
- { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
73
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
74
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
- { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
76
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
77
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
78
- .type = ARM_CP_CONST, .resetvalue = 0 },
79
- { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
80
- .cp = 15, .opc1 = 6, .crm = 2,
81
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
82
- .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
83
- { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
84
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
85
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
86
- { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
87
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
88
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
89
- { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
90
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
91
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
92
- { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
93
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
94
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
95
- { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
96
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
97
- .resetvalue = 0 },
98
- { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
99
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
100
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
101
- { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
102
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
103
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
104
- { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
105
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
106
- .resetvalue = 0 },
107
- { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
108
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
109
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
110
- { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
111
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
112
- .resetvalue = 0 },
113
- { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
114
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
115
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
116
- { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
117
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
118
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
119
- { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
120
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
121
- .access = PL2_RW, .accessfn = access_tda,
122
- .type = ARM_CP_CONST, .resetvalue = 0 },
123
- { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
124
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
125
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
126
- .type = ARM_CP_CONST, .resetvalue = 0 },
127
- { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
128
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
129
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
130
- { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
131
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
132
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
133
- { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
134
- .type = ARM_CP_CONST,
135
- .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
136
- .access = PL2_RW, .resetvalue = 0 },
137
-};
138
-
139
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
140
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
141
- { .name = "HCR2", .state = ARM_CP_STATE_AA32,
142
- .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
143
- .access = PL2_RW,
144
- .type = ARM_CP_CONST, .resetvalue = 0 },
145
-};
146
-
147
static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
148
{
149
ARMCPU *cpu = env_archcpu(env);
150
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
151
define_arm_cp_regs(cpu, v8_idregs);
152
define_arm_cp_regs(cpu, v8_cp_reginfo);
153
}
154
- if (arm_feature(env, ARM_FEATURE_EL2)) {
155
+
30
+
156
+ /*
31
+ /*
157
+ * Register the base EL2 cpregs.
32
+ * Shift by element size is architecturally valid.
158
+ * Pre v8, these registers are implemented only as part of the
33
+ * For arithmetic right-shift, it's the same as by one less.
159
+ * Virtualization Extensions (EL2 present). Beginning with v8,
34
+ * For logical shifts and ASRD, it is a zeroing operation.
160
+ * if EL2 is missing but EL3 is enabled, mostly these become
161
+ * RES0 from EL3, with some specific exceptions.
162
+ */
35
+ */
163
+ if (arm_feature(env, ARM_FEATURE_EL2)
36
+ max = 8 << a->esz;
164
+ || (arm_feature(env, ARM_FEATURE_EL3)
37
+ if (a->imm >= max) {
165
+ && arm_feature(env, ARM_FEATURE_V8))) {
38
+ if (asr) {
166
uint64_t vmpidr_def = mpidr_read_val(env);
39
+ a->imm = max - 1;
167
ARMCPRegInfo vpidr_regs[] = {
40
+ } else {
168
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
41
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
169
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
42
+ }
170
};
43
+ }
171
define_one_arm_cp_reg(cpu, &rvbar);
44
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
172
}
45
+}
46
+
47
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
48
{
49
static gen_helper_gvec_3 * const fns[4] = {
50
gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
51
gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
52
};
53
- if (a->esz < 0) {
54
- /* Invalid tsz encoding -- see tszimm_esz. */
55
- return false;
56
- }
57
- /* Shift by element size is architecturally valid. For
58
- arithmetic right-shift, it's the same as by one less. */
59
- a->imm = MIN(a->imm, (8 << a->esz) - 1);
60
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
61
+ return do_shift_zpzi(s, a, true, fns);
62
}
63
64
static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
65
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
66
gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
67
gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
68
};
69
- if (a->esz < 0) {
70
- return false;
71
- }
72
- /* Shift by element size is architecturally valid.
73
- For logical shifts, it is a zeroing operation. */
74
- if (a->imm >= (8 << a->esz)) {
75
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
173
- } else {
76
- } else {
174
- /* If EL2 is missing but higher ELs are enabled, we need to
77
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
175
- * register the no_el2 reginfos.
78
- }
176
- */
79
+ return do_shift_zpzi(s, a, false, fns);
177
- if (arm_feature(env, ARM_FEATURE_EL3)) {
80
}
178
- /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
81
179
- * of MIDR_EL1 and MPIDR_EL1.
82
static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
180
- */
83
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
181
- ARMCPRegInfo vpidr_regs[] = {
84
gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
182
- { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
85
gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
183
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
86
};
184
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
87
- if (a->esz < 0) {
185
- .type = ARM_CP_CONST, .resetvalue = cpu->midr,
88
- return false;
186
- .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
89
- }
187
- { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
90
- /* Shift by element size is architecturally valid.
188
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
91
- For logical shifts, it is a zeroing operation. */
189
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
92
- if (a->imm >= (8 << a->esz)) {
190
- .type = ARM_CP_NO_RAW,
93
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
191
- .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
94
- } else {
192
- };
95
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
193
- define_arm_cp_regs(cpu, vpidr_regs);
96
- }
194
- define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
97
+ return do_shift_zpzi(s, a, false, fns);
195
- if (arm_feature(env, ARM_FEATURE_V8)) {
98
}
196
- define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
99
197
- }
100
static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
198
- }
101
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
199
}
102
gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
200
+
103
gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
201
+ /* Register the base EL3 cpregs. */
104
};
202
if (arm_feature(env, ARM_FEATURE_EL3)) {
105
- if (a->esz < 0) {
203
define_arm_cp_regs(cpu, el3_cp_reginfo);
106
- return false;
204
ARMCPRegInfo el3_regs[] = {
107
- }
108
- /* Shift by element size is architecturally valid. For arithmetic
109
- right shift for division, it is a zeroing operation. */
110
- if (a->imm >= (8 << a->esz)) {
111
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
112
- } else {
113
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
114
- }
115
+ return do_shift_zpzi(s, a, false, fns);
116
}
117
118
static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
205
--
119
--
206
2.25.1
120
2.25.1
diff view generated by jsdifflib
New patch
[PULL 049/117] target/arm: Use TRANS_FEAT for do_shift_zpzi
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-47-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 52 +++++++++++++++-----------------------
9
1 file changed, 20 insertions(+), 32 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_shift_zpzi(DisasContext *s, arg_rpri_esz *a, bool asr,
16
return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
17
}
18
19
-static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
20
-{
21
- static gen_helper_gvec_3 * const fns[4] = {
22
- gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
23
- gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
24
- };
25
- return do_shift_zpzi(s, a, true, fns);
26
-}
27
+static gen_helper_gvec_3 * const asr_zpzi_fns[4] = {
28
+ gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
29
+ gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
30
+};
31
+TRANS_FEAT(ASR_zpzi, aa64_sve, do_shift_zpzi, a, true, asr_zpzi_fns)
32
33
-static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
34
-{
35
- static gen_helper_gvec_3 * const fns[4] = {
36
- gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
37
- gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
38
- };
39
- return do_shift_zpzi(s, a, false, fns);
40
-}
41
+static gen_helper_gvec_3 * const lsr_zpzi_fns[4] = {
42
+ gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
43
+ gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
44
+};
45
+TRANS_FEAT(LSR_zpzi, aa64_sve, do_shift_zpzi, a, false, lsr_zpzi_fns)
46
47
-static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
48
-{
49
- static gen_helper_gvec_3 * const fns[4] = {
50
- gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
51
- gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
52
- };
53
- return do_shift_zpzi(s, a, false, fns);
54
-}
55
+static gen_helper_gvec_3 * const lsl_zpzi_fns[4] = {
56
+ gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
57
+ gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
58
+};
59
+TRANS_FEAT(LSL_zpzi, aa64_sve, do_shift_zpzi, a, false, lsl_zpzi_fns)
60
61
-static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
62
-{
63
- static gen_helper_gvec_3 * const fns[4] = {
64
- gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
65
- gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
66
- };
67
- return do_shift_zpzi(s, a, false, fns);
68
-}
69
+static gen_helper_gvec_3 * const asrd_fns[4] = {
70
+ gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
71
+ gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
72
+};
73
+TRANS_FEAT(ASRD, aa64_sve, do_shift_zpzi, a, false, asrd_fns)
74
75
static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
76
gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
77
--
78
2.25.1
diff view generated by jsdifflib
New patch
[PULL 050/117] target/arm: Use TRANS_FEAT for do_zpzzz_ool
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the DO_ZPZZZ macro, as it had just the two uses.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-48-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 23 ++++++++++-------------
11
1 file changed, 10 insertions(+), 13 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a,
18
return true;
19
}
20
21
-#define DO_ZPZZZ(NAME, name) \
22
-static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
23
-{ \
24
- static gen_helper_gvec_5 * const fns[4] = { \
25
- gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
26
- gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
27
- }; \
28
- return do_zpzzz_ool(s, a, fns[a->esz]); \
29
-}
30
+static gen_helper_gvec_5 * const mla_fns[4] = {
31
+ gen_helper_sve_mla_b, gen_helper_sve_mla_h,
32
+ gen_helper_sve_mla_s, gen_helper_sve_mla_d,
33
+};
34
+TRANS_FEAT(MLA, aa64_sve, do_zpzzz_ool, a, mla_fns[a->esz])
35
36
-DO_ZPZZZ(MLA, mla)
37
-DO_ZPZZZ(MLS, mls)
38
-
39
-#undef DO_ZPZZZ
40
+static gen_helper_gvec_5 * const mls_fns[4] = {
41
+ gen_helper_sve_mls_b, gen_helper_sve_mls_h,
42
+ gen_helper_sve_mls_s, gen_helper_sve_mls_d,
43
+};
44
+TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz])
45
46
/*
47
*** SVE Index Generation Group
48
--
49
2.25.1
diff view generated by jsdifflib
New patch
[PULL 051/117] target/arm: Move sve check into do_index
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-49-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 53 ++++++++++++++++++--------------------
9
1 file changed, 25 insertions(+), 28 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz])
16
*** SVE Index Generation Group
17
*/
18
19
-static void do_index(DisasContext *s, int esz, int rd,
20
+static bool do_index(DisasContext *s, int esz, int rd,
21
TCGv_i64 start, TCGv_i64 incr)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
25
- TCGv_ptr t_zd = tcg_temp_new_ptr();
26
+ unsigned vsz;
27
+ TCGv_i32 desc;
28
+ TCGv_ptr t_zd;
29
+
30
+ if (!sve_access_check(s)) {
31
+ return true;
32
+ }
33
+
34
+ vsz = vec_full_reg_size(s);
35
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
36
+ t_zd = tcg_temp_new_ptr();
37
38
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
39
if (esz == 3) {
40
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
41
tcg_temp_free_i32(i32);
42
}
43
tcg_temp_free_ptr(t_zd);
44
+ return true;
45
}
46
47
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
48
{
49
- if (sve_access_check(s)) {
50
- TCGv_i64 start = tcg_constant_i64(a->imm1);
51
- TCGv_i64 incr = tcg_constant_i64(a->imm2);
52
- do_index(s, a->esz, a->rd, start, incr);
53
- }
54
- return true;
55
+ TCGv_i64 start = tcg_constant_i64(a->imm1);
56
+ TCGv_i64 incr = tcg_constant_i64(a->imm2);
57
+ return do_index(s, a->esz, a->rd, start, incr);
58
}
59
60
static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
61
{
62
- if (sve_access_check(s)) {
63
- TCGv_i64 start = tcg_constant_i64(a->imm);
64
- TCGv_i64 incr = cpu_reg(s, a->rm);
65
- do_index(s, a->esz, a->rd, start, incr);
66
- }
67
- return true;
68
+ TCGv_i64 start = tcg_constant_i64(a->imm);
69
+ TCGv_i64 incr = cpu_reg(s, a->rm);
70
+ return do_index(s, a->esz, a->rd, start, incr);
71
}
72
73
static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
74
{
75
- if (sve_access_check(s)) {
76
- TCGv_i64 start = cpu_reg(s, a->rn);
77
- TCGv_i64 incr = tcg_constant_i64(a->imm);
78
- do_index(s, a->esz, a->rd, start, incr);
79
- }
80
- return true;
81
+ TCGv_i64 start = cpu_reg(s, a->rn);
82
+ TCGv_i64 incr = tcg_constant_i64(a->imm);
83
+ return do_index(s, a->esz, a->rd, start, incr);
84
}
85
86
static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
87
{
88
- if (sve_access_check(s)) {
89
- TCGv_i64 start = cpu_reg(s, a->rn);
90
- TCGv_i64 incr = cpu_reg(s, a->rm);
91
- do_index(s, a->esz, a->rd, start, incr);
92
- }
93
- return true;
94
+ TCGv_i64 start = cpu_reg(s, a->rn);
95
+ TCGv_i64 incr = cpu_reg(s, a->rm);
96
+ return do_index(s, a->esz, a->rd, start, incr);
97
}
98
99
/*
100
--
101
2.25.1
diff view generated by jsdifflib
New patch
[PULL 052/117] target/arm: Use TRANS_FEAT for do_index
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-50-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 35 ++++++++---------------------------
9
1 file changed, 8 insertions(+), 27 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_index(DisasContext *s, int esz, int rd,
16
return true;
17
}
18
19
-static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
20
-{
21
- TCGv_i64 start = tcg_constant_i64(a->imm1);
22
- TCGv_i64 incr = tcg_constant_i64(a->imm2);
23
- return do_index(s, a->esz, a->rd, start, incr);
24
-}
25
-
26
-static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
27
-{
28
- TCGv_i64 start = tcg_constant_i64(a->imm);
29
- TCGv_i64 incr = cpu_reg(s, a->rm);
30
- return do_index(s, a->esz, a->rd, start, incr);
31
-}
32
-
33
-static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
34
-{
35
- TCGv_i64 start = cpu_reg(s, a->rn);
36
- TCGv_i64 incr = tcg_constant_i64(a->imm);
37
- return do_index(s, a->esz, a->rd, start, incr);
38
-}
39
-
40
-static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
41
-{
42
- TCGv_i64 start = cpu_reg(s, a->rn);
43
- TCGv_i64 incr = cpu_reg(s, a->rm);
44
- return do_index(s, a->esz, a->rd, start, incr);
45
-}
46
+TRANS_FEAT(INDEX_ii, aa64_sve, do_index, a->esz, a->rd,
47
+ tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2))
48
+TRANS_FEAT(INDEX_ir, aa64_sve, do_index, a->esz, a->rd,
49
+ tcg_constant_i64(a->imm), cpu_reg(s, a->rm))
50
+TRANS_FEAT(INDEX_ri, aa64_sve, do_index, a->esz, a->rd,
51
+ cpu_reg(s, a->rn), tcg_constant_i64(a->imm))
52
+TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->rd,
53
+ cpu_reg(s, a->rn), cpu_reg(s, a->rm))
54
55
/*
56
*** SVE Stack Allocation Group
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
[PULL 053/117] target/arm: Use TRANS_FEAT for do_adr
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-51-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 23 ++++-------------------
9
1 file changed, 4 insertions(+), 19 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
16
return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
17
}
18
19
-static bool trans_ADR_p32(DisasContext *s, arg_rrri *a)
20
-{
21
- return do_adr(s, a, gen_helper_sve_adr_p32);
22
-}
23
-
24
-static bool trans_ADR_p64(DisasContext *s, arg_rrri *a)
25
-{
26
- return do_adr(s, a, gen_helper_sve_adr_p64);
27
-}
28
-
29
-static bool trans_ADR_s32(DisasContext *s, arg_rrri *a)
30
-{
31
- return do_adr(s, a, gen_helper_sve_adr_s32);
32
-}
33
-
34
-static bool trans_ADR_u32(DisasContext *s, arg_rrri *a)
35
-{
36
- return do_adr(s, a, gen_helper_sve_adr_u32);
37
-}
38
+TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
39
+TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
40
+TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
41
+TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
42
43
/*
44
*** SVE Integer Misc - Unpredicated Group
45
--
46
2.25.1
diff view generated by jsdifflib
New patch
[PULL 054/117] target/arm: Use TRANS_FEAT for do_predset
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-52-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 19 +++++--------------
9
1 file changed, 5 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
16
return true;
17
}
18
19
-static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a)
20
-{
21
- return do_predset(s, a->esz, a->rd, a->pat, a->s);
22
-}
23
+TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s)
24
25
-static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a)
26
-{
27
- /* Note pat == 31 is #all, to set all elements. */
28
- return do_predset(s, 0, FFR_PRED_NUM, 31, false);
29
-}
30
+/* Note pat == 31 is #all, to set all elements. */
31
+TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false)
32
33
-static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a)
34
-{
35
- /* Note pat == 32 is #unimp, to set no elements. */
36
- return do_predset(s, 0, a->rd, 32, false);
37
-}
38
+/* Note pat == 32 is #unimp, to set no elements. */
39
+TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false)
40
41
static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
42
{
43
--
44
2.25.1
diff view generated by jsdifflib
New patch
[PULL 055/117] target/arm: Use TRANS_FEAT for RDFFR, WRFFR
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-53-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
16
return trans_AND_pppp(s, &alt_a);
17
}
18
19
-static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a)
20
-{
21
- return do_mov_p(s, a->rd, FFR_PRED_NUM);
22
-}
23
-
24
-static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a)
25
-{
26
- return do_mov_p(s, FFR_PRED_NUM, a->rn);
27
-}
28
+TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM)
29
+TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn)
30
31
static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
32
void (*gen_fn)(TCGv_i32, TCGv_ptr,
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 056/117] target/arm: Use TRANS_FEAT for do_pfirst_pnext
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-54-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
16
return true;
17
}
18
19
-static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a)
20
-{
21
- return do_pfirst_pnext(s, a, gen_helper_sve_pfirst);
22
-}
23
-
24
-static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
25
-{
26
- return do_pfirst_pnext(s, a, gen_helper_sve_pnext);
27
-}
28
+TRANS_FEAT(PFIRST, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pfirst)
29
+TRANS_FEAT(PNEXT, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pnext)
30
31
/*
32
*** SVE Element Count Group
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 057/117] target/arm: Use TRANS_FEAT for do_EXT
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-55-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 14 ++------------
9
1 file changed, 2 insertions(+), 12 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm)
16
return true;
17
}
18
19
-static bool trans_EXT(DisasContext *s, arg_EXT *a)
20
-{
21
- return do_EXT(s, a->rd, a->rn, a->rm, a->imm);
22
-}
23
-
24
-static bool trans_EXT_sve2(DisasContext *s, arg_rri *a)
25
-{
26
- if (!dc_isar_feature(aa64_sve2, s)) {
27
- return false;
28
- }
29
- return do_EXT(s, a->rd, a->rn, (a->rn + 1) % 32, a->imm);
30
-}
31
+TRANS_FEAT(EXT, aa64_sve, do_EXT, a->rd, a->rn, a->rm, a->imm)
32
+TRANS_FEAT(EXT_sve2, aa64_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) % 32, a->imm)
33
34
/*
35
*** SVE Permute - Unpredicated Group
36
--
37
2.25.1
diff view generated by jsdifflib
New patch
[PULL 058/117] target/arm: Use TRANS_FEAT for do_perm_pred3
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-56-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 35 ++++++-----------------------------
9
1 file changed, 6 insertions(+), 29 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
16
return true;
17
}
18
19
-static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a)
20
-{
21
- return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p);
22
-}
23
-
24
-static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a)
25
-{
26
- return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p);
27
-}
28
-
29
-static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a)
30
-{
31
- return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p);
32
-}
33
-
34
-static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a)
35
-{
36
- return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p);
37
-}
38
-
39
-static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a)
40
-{
41
- return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p);
42
-}
43
-
44
-static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a)
45
-{
46
- return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p);
47
-}
48
+TRANS_FEAT(ZIP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_zip_p)
49
+TRANS_FEAT(ZIP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_zip_p)
50
+TRANS_FEAT(UZP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_uzp_p)
51
+TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p)
52
+TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p)
53
+TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p)
54
55
static bool trans_REV_p(DisasContext *s, arg_rr_esz *a)
56
{
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
[PULL 059/117] target/arm: Use TRANS_FEAT for do_perm_pred2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-57-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p)
16
TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p)
17
TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p)
18
19
-static bool trans_REV_p(DisasContext *s, arg_rr_esz *a)
20
-{
21
- return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p);
22
-}
23
-
24
-static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a)
25
-{
26
- return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p);
27
-}
28
-
29
-static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a)
30
-{
31
- return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p);
32
-}
33
+TRANS_FEAT(REV_p, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_rev_p)
34
+TRANS_FEAT(PUNPKLO, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_punpk_p)
35
+TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p)
36
37
/*
38
*** SVE Permute - Interleaving Group
39
--
40
2.25.1
diff view generated by jsdifflib
[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
[PULL 060/117] target/arm: Move sve zip high_ofs into simd_data
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
3
This is in line with how we treat uzp, and will
4
is CONTEXTIDR_EL2, which is also conditionally implemented
4
eliminate the special case code during translation.
5
with FEAT_VHE. The rest of the debug extension concerns the
6
External debug interface, which is outside the scope of QEMU.
7
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-58-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
docs/system/arm/emulation.rst | 1 +
11
target/arm/sve_helper.c | 6 ++++--
14
target/arm/cpu.c | 1 +
12
target/arm/translate-sve.c | 12 ++++++------
15
target/arm/cpu64.c | 1 +
13
2 files changed, 10 insertions(+), 8 deletions(-)
16
target/arm/cpu_tcg.c | 2 ++
17
4 files changed, 5 insertions(+)
18
14
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
17
--- a/target/arm/sve_helper.c
22
+++ b/docs/system/arm/emulation.rst
18
+++ b/target/arm/sve_helper.c
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
19
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc)
24
- FEAT_BTI (Branch Target Identification)
20
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
25
- FEAT_DIT (Data Independent Timing instructions)
21
{ \
26
- FEAT_DPB (DC CVAP instruction)
22
intptr_t oprsz = simd_oprsz(desc); \
27
+- FEAT_Debugv8p2 (Debug changes for v8.2)
23
+ intptr_t odd_ofs = simd_data(desc); \
28
- FEAT_DotProd (Advanced SIMD dot product instructions)
24
intptr_t i, oprsz_2 = oprsz / 2; \
29
- FEAT_FCMA (Floating-point complex number instructions)
25
ARMVectorReg tmp_n, tmp_m; \
30
- FEAT_FHM (Floating-point half-precision multiplication instructions)
26
/* We produce output faster than we consume input. \
31
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
27
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
28
vm = memcpy(&tmp_m, vm, oprsz_2); \
29
} \
30
for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
31
- *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + H(i)); \
32
- *(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = *(TYPE *)(vm + H(i)); \
33
+ *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + odd_ofs + H(i)); \
34
+ *(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = \
35
+ *(TYPE *)(vm + odd_ofs + H(i)); \
36
} \
37
if (sizeof(TYPE) == 16 && unlikely(oprsz & 16)) { \
38
memset(vd + oprsz - 16, 0, 16); \
39
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
32
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu.c
41
--- a/target/arm/translate-sve.c
34
+++ b/target/arm/cpu.c
42
+++ b/target/arm/translate-sve.c
35
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
43
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
36
* feature registers as well.
44
unsigned vsz = vec_full_reg_size(s);
37
*/
45
unsigned high_ofs = high ? vsz / 2 : 0;
38
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
46
tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
39
+ cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
47
- vec_full_reg_offset(s, a->rn) + high_ofs,
40
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
48
- vec_full_reg_offset(s, a->rm) + high_ofs,
41
ID_AA64PFR0, EL3, 0);
49
- vsz, vsz, 0, fns[a->esz]);
50
+ vec_full_reg_offset(s, a->rn),
51
+ vec_full_reg_offset(s, a->rm),
52
+ vsz, vsz, high_ofs, fns[a->esz]);
42
}
53
}
43
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
54
return true;
44
index XXXXXXX..XXXXXXX 100644
55
}
45
--- a/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
46
+++ b/target/arm/cpu64.c
57
unsigned vsz = vec_full_reg_size(s);
47
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
58
unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
48
cpu->isar.id_aa64zfr0 = t;
59
tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
49
60
- vec_full_reg_offset(s, a->rn) + high_ofs,
50
t = cpu->isar.id_aa64dfr0;
61
- vec_full_reg_offset(s, a->rm) + high_ofs,
51
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
62
- vsz, vsz, 0, gen_helper_sve2_zip_q);
52
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
63
+ vec_full_reg_offset(s, a->rn),
53
cpu->isar.id_aa64dfr0 = t;
64
+ vec_full_reg_offset(s, a->rm),
54
65
+ vsz, vsz, high_ofs, gen_helper_sve2_zip_q);
55
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
66
}
56
index XXXXXXX..XXXXXXX 100644
67
return true;
57
--- a/target/arm/cpu_tcg.c
58
+++ b/target/arm/cpu_tcg.c
59
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
60
cpu->isar.id_pfr2 = t;
61
62
t = cpu->isar.id_dfr0;
63
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
64
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
65
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
66
cpu->isar.id_dfr0 = t;
67
}
68
}
68
--
69
--
69
2.25.1
70
2.25.1
diff view generated by jsdifflib
New patch
[PULL 061/117] target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-59-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 25 +++++++------------------
9
1 file changed, 7 insertions(+), 18 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
16
gen_helper_sve_zip_b, gen_helper_sve_zip_h,
17
gen_helper_sve_zip_s, gen_helper_sve_zip_d,
18
};
19
+ unsigned vsz = vec_full_reg_size(s);
20
+ unsigned high_ofs = high ? vsz / 2 : 0;
21
22
- if (sve_access_check(s)) {
23
- unsigned vsz = vec_full_reg_size(s);
24
- unsigned high_ofs = high ? vsz / 2 : 0;
25
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
26
- vec_full_reg_offset(s, a->rn),
27
- vec_full_reg_offset(s, a->rm),
28
- vsz, vsz, high_ofs, fns[a->esz]);
29
- }
30
- return true;
31
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, high_ofs);
32
}
33
34
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
35
@@ -XXX,XX +XXX,XX @@ static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a)
36
37
static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
38
{
39
+ unsigned vsz = vec_full_reg_size(s);
40
+ unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
41
+
42
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
43
return false;
44
}
45
- if (sve_access_check(s)) {
46
- unsigned vsz = vec_full_reg_size(s);
47
- unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
48
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
49
- vec_full_reg_offset(s, a->rn),
50
- vec_full_reg_offset(s, a->rm),
51
- vsz, vsz, high_ofs, gen_helper_sve2_zip_q);
52
- }
53
- return true;
54
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_zip_q, a, high_ofs);
55
}
56
57
static bool trans_ZIP1_q(DisasContext *s, arg_rrr_esz *a)
58
--
59
2.25.1
diff view generated by jsdifflib
New patch
[PULL 062/117] target/arm: Use TRANS_FEAT for do_zip, do_zip_q
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_zip*
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-60-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 54 +++++++++-----------------------------
12
1 file changed, 13 insertions(+), 41 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p)
19
*** SVE Permute - Interleaving Group
20
*/
21
22
-static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
23
-{
24
- static gen_helper_gvec_3 * const fns[4] = {
25
- gen_helper_sve_zip_b, gen_helper_sve_zip_h,
26
- gen_helper_sve_zip_s, gen_helper_sve_zip_d,
27
- };
28
- unsigned vsz = vec_full_reg_size(s);
29
- unsigned high_ofs = high ? vsz / 2 : 0;
30
+static gen_helper_gvec_3 * const zip_fns[4] = {
31
+ gen_helper_sve_zip_b, gen_helper_sve_zip_h,
32
+ gen_helper_sve_zip_s, gen_helper_sve_zip_d,
33
+};
34
+TRANS_FEAT(ZIP1_z, aa64_sve, gen_gvec_ool_arg_zzz,
35
+ zip_fns[a->esz], a, 0)
36
+TRANS_FEAT(ZIP2_z, aa64_sve, gen_gvec_ool_arg_zzz,
37
+ zip_fns[a->esz], a, vec_full_reg_size(s) / 2)
38
39
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, high_ofs);
40
-}
41
-
42
-static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
43
-{
44
- return do_zip(s, a, false);
45
-}
46
-
47
-static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a)
48
-{
49
- return do_zip(s, a, true);
50
-}
51
-
52
-static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
53
-{
54
- unsigned vsz = vec_full_reg_size(s);
55
- unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
56
-
57
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
58
- return false;
59
- }
60
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_zip_q, a, high_ofs);
61
-}
62
-
63
-static bool trans_ZIP1_q(DisasContext *s, arg_rrr_esz *a)
64
-{
65
- return do_zip_q(s, a, false);
66
-}
67
-
68
-static bool trans_ZIP2_q(DisasContext *s, arg_rrr_esz *a)
69
-{
70
- return do_zip_q(s, a, true);
71
-}
72
+TRANS_FEAT(ZIP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
73
+ gen_helper_sve2_zip_q, a, 0)
74
+TRANS_FEAT(ZIP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
75
+ gen_helper_sve2_zip_q, a,
76
+ QEMU_ALIGN_DOWN(vec_full_reg_size(s), 32) / 2)
77
78
static gen_helper_gvec_3 * const uzp_fns[4] = {
79
gen_helper_sve_uzp_b, gen_helper_sve_uzp_h,
80
--
81
2.25.1
diff view generated by jsdifflib
New patch
[PULL 063/117] target/arm: Use TRANS_FEAT for do_clast_vector
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-61-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a)
20
-{
21
- return do_clast_vector(s, a, false);
22
-}
23
-
24
-static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a)
25
-{
26
- return do_clast_vector(s, a, true);
27
-}
28
+TRANS_FEAT(CLASTA_z, aa64_sve, do_clast_vector, a, false)
29
+TRANS_FEAT(CLASTB_z, aa64_sve, do_clast_vector, a, true)
30
31
/* Compute CLAST for a scalar. */
32
static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 064/117] target/arm: Use TRANS_FEAT for do_clast_fp
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-62-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a)
20
-{
21
- return do_clast_fp(s, a, false);
22
-}
23
-
24
-static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_clast_fp(s, a, true);
27
-}
28
+TRANS_FEAT(CLASTA_v, aa64_sve, do_clast_fp, a, false)
29
+TRANS_FEAT(CLASTB_v, aa64_sve, do_clast_fp, a, true)
30
31
/* Compute CLAST for a Xreg. */
32
static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before)
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 065/117] target/arm: Use TRANS_FEAT for do_clast_general
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-63-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a)
20
-{
21
- return do_clast_general(s, a, false);
22
-}
23
-
24
-static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_clast_general(s, a, true);
27
-}
28
+TRANS_FEAT(CLASTA_r, aa64_sve, do_clast_general, a, false)
29
+TRANS_FEAT(CLASTB_r, aa64_sve, do_clast_general, a, true)
30
31
/* Compute LAST for a scalar. */
32
static TCGv_i64 do_last_scalar(DisasContext *s, int esz,
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 066/117] target/arm: Use TRANS_FEAT for do_last_fp
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-64-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a)
20
-{
21
- return do_last_fp(s, a, false);
22
-}
23
-
24
-static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_last_fp(s, a, true);
27
-}
28
+TRANS_FEAT(LASTA_v, aa64_sve, do_last_fp, a, false)
29
+TRANS_FEAT(LASTB_v, aa64_sve, do_last_fp, a, true)
30
31
/* Compute LAST for a Xreg. */
32
static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before)
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 067/117] target/arm: Use TRANS_FEAT for do_last_general
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-65-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a)
20
-{
21
- return do_last_general(s, a, false);
22
-}
23
-
24
-static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_last_general(s, a, true);
27
-}
28
+TRANS_FEAT(LASTA_r, aa64_sve, do_last_general, a, false)
29
+TRANS_FEAT(LASTB_r, aa64_sve, do_last_general, a, true)
30
31
static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a)
32
{
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 068/117] target/arm: Use TRANS_FEAT for SPLICE
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-66-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 ++++-------------
9
1 file changed, 4 insertions(+), 13 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
16
TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
17
a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
18
19
-static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
20
-{
21
- return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
22
- a->rd, a->rn, a->rm, a->pg, a->esz);
23
-}
24
+TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz,
25
+ gen_helper_sve_splice, a, a->esz)
26
27
-static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
28
-{
29
- if (!dc_isar_feature(aa64_sve2, s)) {
30
- return false;
31
- }
32
- return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
33
- a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
34
-}
35
+TRANS_FEAT(SPLICE_sve2, aa64_sve2, gen_gvec_ool_zzzp, gen_helper_sve_splice,
36
+ a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz)
37
38
/*
39
*** SVE Integer Compare - Vectors Group
40
--
41
2.25.1
diff view generated by jsdifflib
New patch
[PULL 069/117] target/arm: Use TRANS_FEAT for do_ppzz_flags
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-67-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 28 ++++++++++++----------------
9
1 file changed, 12 insertions(+), 16 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
16
}
17
18
#define DO_PPZZ(NAME, name) \
19
-static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \
20
-{ \
21
- static gen_helper_gvec_flags_4 * const fns[4] = { \
22
- gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \
23
- gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \
24
- }; \
25
- return do_ppzz_flags(s, a, fns[a->esz]); \
26
-}
27
+ static gen_helper_gvec_flags_4 * const name##_ppzz_fns[4] = { \
28
+ gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \
29
+ gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \
30
+ }; \
31
+ TRANS_FEAT(NAME##_ppzz, aa64_sve, do_ppzz_flags, \
32
+ a, name##_ppzz_fns[a->esz])
33
34
DO_PPZZ(CMPEQ, cmpeq)
35
DO_PPZZ(CMPNE, cmpne)
36
@@ -XXX,XX +XXX,XX @@ DO_PPZZ(CMPHS, cmphs)
37
#undef DO_PPZZ
38
39
#define DO_PPZW(NAME, name) \
40
-static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a) \
41
-{ \
42
- static gen_helper_gvec_flags_4 * const fns[4] = { \
43
- gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \
44
- gen_helper_sve_##name##_ppzw_s, NULL \
45
- }; \
46
- return do_ppzz_flags(s, a, fns[a->esz]); \
47
-}
48
+ static gen_helper_gvec_flags_4 * const name##_ppzw_fns[4] = { \
49
+ gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \
50
+ gen_helper_sve_##name##_ppzw_s, NULL \
51
+ }; \
52
+ TRANS_FEAT(NAME##_ppzw, aa64_sve, do_ppzz_flags, \
53
+ a, name##_ppzw_fns[a->esz])
54
55
DO_PPZW(CMPEQ, cmpeq)
56
DO_PPZW(CMPNE, cmpne)
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
[PULL 070/117] target/arm: Use TRANS_FEAT for do_sve2_ppzz_flags
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-68-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 28 ++++++++--------------------
9
1 file changed, 8 insertions(+), 20 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt)
16
DO_SVE2_ZZZ_NARROW(RSUBHNB, rsubhnb)
17
DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt)
18
19
-static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
20
- gen_helper_gvec_flags_4 *fn)
21
-{
22
- if (!dc_isar_feature(aa64_sve2, s)) {
23
- return false;
24
- }
25
- return do_ppzz_flags(s, a, fn);
26
-}
27
+static gen_helper_gvec_flags_4 * const match_fns[4] = {
28
+ gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL
29
+};
30
+TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
31
32
-#define DO_SVE2_PPZZ_MATCH(NAME, name) \
33
-static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
34
-{ \
35
- static gen_helper_gvec_flags_4 * const fns[4] = { \
36
- gen_helper_sve2_##name##_ppzz_b, gen_helper_sve2_##name##_ppzz_h, \
37
- NULL, NULL \
38
- }; \
39
- return do_sve2_ppzz_flags(s, a, fns[a->esz]); \
40
-}
41
-
42
-DO_SVE2_PPZZ_MATCH(MATCH, match)
43
-DO_SVE2_PPZZ_MATCH(NMATCH, nmatch)
44
+static gen_helper_gvec_flags_4 * const nmatch_fns[4] = {
45
+ gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL
46
+};
47
+TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
48
49
static gen_helper_gvec_4 * const histcnt_fns[4] = {
50
NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
51
--
52
2.25.1
diff view generated by jsdifflib
New patch
[PULL 071/117] target/arm: Use TRANS_FEAT for do_ppzi_flags
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-69-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 8 +++-----
9
1 file changed, 3 insertions(+), 5 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
16
}
17
18
#define DO_PPZI(NAME, name) \
19
-static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a) \
20
-{ \
21
- static gen_helper_gvec_flags_3 * const fns[4] = { \
22
+ static gen_helper_gvec_flags_3 * const name##_ppzi_fns[4] = { \
23
gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \
24
gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \
25
}; \
26
- return do_ppzi_flags(s, a, fns[a->esz]); \
27
-}
28
+ TRANS_FEAT(NAME##_ppzi, aa64_sve, do_ppzi_flags, a, \
29
+ name##_ppzi_fns[a->esz])
30
31
DO_PPZI(CMPEQ, cmpeq)
32
DO_PPZI(CMPNE, cmpne)
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
[PULL 072/117] target/arm: Use TRANS_FEAT for do_brk2, do_brk3
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-70-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 45 ++++++++++++--------------------------
9
1 file changed, 14 insertions(+), 31 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
16
return true;
17
}
18
19
-static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a)
20
-{
21
- return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas);
22
-}
23
+TRANS_FEAT(BRKPA, aa64_sve, do_brk3, a,
24
+ gen_helper_sve_brkpa, gen_helper_sve_brkpas)
25
+TRANS_FEAT(BRKPB, aa64_sve, do_brk3, a,
26
+ gen_helper_sve_brkpb, gen_helper_sve_brkpbs)
27
28
-static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a)
29
-{
30
- return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs);
31
-}
32
+TRANS_FEAT(BRKA_m, aa64_sve, do_brk2, a,
33
+ gen_helper_sve_brka_m, gen_helper_sve_brkas_m)
34
+TRANS_FEAT(BRKB_m, aa64_sve, do_brk2, a,
35
+ gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m)
36
37
-static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a)
38
-{
39
- return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m);
40
-}
41
+TRANS_FEAT(BRKA_z, aa64_sve, do_brk2, a,
42
+ gen_helper_sve_brka_z, gen_helper_sve_brkas_z)
43
+TRANS_FEAT(BRKB_z, aa64_sve, do_brk2, a,
44
+ gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z)
45
46
-static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a)
47
-{
48
- return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m);
49
-}
50
-
51
-static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a)
52
-{
53
- return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z);
54
-}
55
-
56
-static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a)
57
-{
58
- return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z);
59
-}
60
-
61
-static bool trans_BRKN(DisasContext *s, arg_rpr_s *a)
62
-{
63
- return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns);
64
-}
65
+TRANS_FEAT(BRKN, aa64_sve, do_brk2, a,
66
+ gen_helper_sve_brkn, gen_helper_sve_brkns)
67
68
/*
69
*** SVE Predicate Count Group
70
--
71
2.25.1
diff view generated by jsdifflib
New patch
[PULL 073/117] target/arm: Use TRANS_FEAT for MUL_zzi
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-71-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 10 +---------
9
1 file changed, 1 insertion(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
16
return true;
17
}
18
19
-static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a)
20
-{
21
- if (sve_access_check(s)) {
22
- unsigned vsz = vec_full_reg_size(s);
23
- tcg_gen_gvec_muli(a->esz, vec_full_reg_offset(s, a->rd),
24
- vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz);
25
- }
26
- return true;
27
-}
28
+TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a)
29
30
static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
31
{
32
--
33
2.25.1
diff view generated by jsdifflib
[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
[PULL 074/117] target/arm: Reject dup_i w/ shifted byte early
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This register is present for either VHE or Debugv8p2.
3
Remove the unparsed extraction in trans_DUP_i,
4
which is intended to reject an 8-bit shift of
5
an 8-bit constant for 8-bit element.
4
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-72-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/helper.c | 15 +++++++++++----
12
target/arm/sve.decode | 5 ++++-
11
1 file changed, 11 insertions(+), 4 deletions(-)
13
target/arm/translate-sve.c | 10 ++++++----
14
2 files changed, 10 insertions(+), 5 deletions(-)
12
15
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
18
--- a/target/arm/sve.decode
16
+++ b/target/arm/helper.c
19
+++ b/target/arm/sve.decode
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
20
@@ -XXX,XX +XXX,XX @@ WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
18
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
21
FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
22
23
# SVE broadcast integer immediate (unpredicated)
24
-DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
25
+{
26
+ INVALID 00100101 00 111 00 011 1 -------- -----
27
+ DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
28
+}
29
30
# SVE integer add/subtract immediate (unpredicated)
31
ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
32
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate-sve.c
35
+++ b/target/arm/translate-sve.c
36
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
37
0x1111111111111111ull, 0x0101010101010101ull
19
};
38
};
20
39
21
+static const ARMCPRegInfo contextidr_el2 = {
40
+static bool trans_INVALID(DisasContext *s, arg_INVALID *a)
22
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
41
+{
23
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
42
+ unallocated_encoding(s);
24
+ .access = PL2_RW,
43
+ return true;
25
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
44
+}
26
+};
27
+
45
+
28
static const ARMCPRegInfo vhe_reginfo[] = {
46
/*
29
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
47
*** SVE Logical - Unpredicated Group
30
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
48
*/
31
- .access = PL2_RW,
49
@@ -XXX,XX +XXX,XX @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
32
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
50
33
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
51
static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
34
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
52
{
35
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
53
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
36
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
54
- return false;
37
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
55
- }
56
if (sve_access_check(s)) {
57
unsigned vsz = vec_full_reg_size(s);
58
int dofs = vec_full_reg_offset(s, a->rd);
59
-
60
tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm);
38
}
61
}
39
62
return true;
40
+ if (cpu_isar_feature(aa64_vh, cpu) ||
41
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
42
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
43
+ }
44
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
45
define_arm_cp_regs(cpu, vhe_reginfo);
46
}
47
--
63
--
48
2.25.1
64
2.25.1
diff view generated by jsdifflib
New patch
[PULL 075/117] target/arm: Reject add/sub w/ shifted byte early
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the unparsed extractions in trans_ADD_zzi, trans_SUBR_zzi,
4
and do_zzi_sat which are intended to reject an 8-bit shift of an
5
8-bit constant for 8-bit element.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-73-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sve.decode | 35 ++++++++++++++++++++++++++++-------
13
target/arm/translate-sve.c | 9 ---------
14
2 files changed, 28 insertions(+), 16 deletions(-)
15
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve.decode
19
+++ b/target/arm/sve.decode
20
@@ -XXX,XX +XXX,XX @@ FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
21
}
22
23
# SVE integer add/subtract immediate (unpredicated)
24
-ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
25
-SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
26
-SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
27
-SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
28
-UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
29
-SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
30
-UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
31
+{
32
+ INVALID 00100101 00 100 000 11 1 -------- -----
33
+ ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
34
+}
35
+{
36
+ INVALID 00100101 00 100 001 11 1 -------- -----
37
+ SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
38
+}
39
+{
40
+ INVALID 00100101 00 100 011 11 1 -------- -----
41
+ SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
42
+}
43
+{
44
+ INVALID 00100101 00 100 100 11 1 -------- -----
45
+ SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
46
+}
47
+{
48
+ INVALID 00100101 00 100 101 11 1 -------- -----
49
+ UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
50
+}
51
+{
52
+ INVALID 00100101 00 100 110 11 1 -------- -----
53
+ SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
54
+}
55
+{
56
+ INVALID 00100101 00 100 111 11 1 -------- -----
57
+ UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
58
+}
59
60
# SVE integer min/max immediate (unpredicated)
61
SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
62
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/translate-sve.c
65
+++ b/target/arm/translate-sve.c
66
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
67
68
static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
69
{
70
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
71
- return false;
72
- }
73
return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
74
}
75
76
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
77
.scalar_first = true }
78
};
79
80
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
81
- return false;
82
- }
83
if (sve_access_check(s)) {
84
unsigned vsz = vec_full_reg_size(s);
85
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
86
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a)
87
88
static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
89
{
90
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
91
- return false;
92
- }
93
if (sve_access_check(s)) {
94
do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
95
tcg_constant_i64(a->imm), u, d);
96
--
97
2.25.1
diff view generated by jsdifflib
New patch
[PULL 076/117] target/arm: Reject copy w/ shifted byte early
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the unparsed extractions in trans_CPY_{m,z}_i which are intended
4
to reject an 8-bit shift of an 8-bit constant for 8-bit element.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-74-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/sve.decode | 10 ++++++++--
12
target/arm/translate-sve.c | 6 ------
13
2 files changed, 8 insertions(+), 8 deletions(-)
14
15
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve.decode
18
+++ b/target/arm/sve.decode
19
@@ -XXX,XX +XXX,XX @@ DUPM 00000101 11 0000 dbm:13 rd:5
20
FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
21
22
# SVE copy integer immediate (predicated)
23
-CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
24
-CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
25
+{
26
+ INVALID 00000101 00 01 ---- 01 1 -------- -----
27
+ CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
28
+}
29
+{
30
+ INVALID 00000101 00 01 ---- 00 1 -------- -----
31
+ CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
32
+}
33
34
### SVE Permute - Extract Group
35
36
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/translate-sve.c
39
+++ b/target/arm/translate-sve.c
40
@@ -XXX,XX +XXX,XX @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
41
42
static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a)
43
{
44
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
45
- return false;
46
- }
47
if (sve_access_check(s)) {
48
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm));
49
}
50
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
51
gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d,
52
};
53
54
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
55
- return false;
56
- }
57
if (sve_access_check(s)) {
58
unsigned vsz = vec_full_reg_size(s);
59
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
60
--
61
2.25.1
diff view generated by jsdifflib
New patch
[PULL 077/117] target/arm: Use TRANS_FEAT for ADD_zzi
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-75-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 5 +----
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
16
return true;
17
}
18
19
-static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
20
-{
21
- return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
22
-}
23
+TRANS_FEAT(ADD_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_addi, a)
24
25
static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a)
26
{
27
--
28
2.25.1
diff view generated by jsdifflib
New patch
[PULL 078/117] target/arm: Use TRANS_FEAT for do_zzi_sat
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-76-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 23 ++++-------------------
9
1 file changed, 4 insertions(+), 19 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
16
return true;
17
}
18
19
-static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a)
20
-{
21
- return do_zzi_sat(s, a, false, false);
22
-}
23
-
24
-static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a)
25
-{
26
- return do_zzi_sat(s, a, true, false);
27
-}
28
-
29
-static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a)
30
-{
31
- return do_zzi_sat(s, a, false, true);
32
-}
33
-
34
-static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a)
35
-{
36
- return do_zzi_sat(s, a, true, true);
37
-}
38
+TRANS_FEAT(SQADD_zzi, aa64_sve, do_zzi_sat, a, false, false)
39
+TRANS_FEAT(UQADD_zzi, aa64_sve, do_zzi_sat, a, true, false)
40
+TRANS_FEAT(SQSUB_zzi, aa64_sve, do_zzi_sat, a, false, true)
41
+TRANS_FEAT(UQSUB_zzi, aa64_sve, do_zzi_sat, a, true, true)
42
43
static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
44
{
45
--
46
2.25.1
diff view generated by jsdifflib
New patch
[PULL 079/117] target/arm: Use TRANS_FEAT for do_zzi_ool
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-77-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 7 ++-----
9
1 file changed, 2 insertions(+), 5 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
16
}
17
18
#define DO_ZZI(NAME, name) \
19
-static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a) \
20
-{ \
21
- static gen_helper_gvec_2i * const fns[4] = { \
22
+ static gen_helper_gvec_2i * const name##i_fns[4] = { \
23
gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \
24
gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \
25
}; \
26
- return do_zzi_ool(s, a, fns[a->esz]); \
27
-}
28
+ TRANS_FEAT(NAME##_zzi, aa64_sve, do_zzi_ool, a, name##i_fns[a->esz])
29
30
DO_ZZI(SMAX, smax)
31
DO_ZZI(UMAX, umax)
32
--
33
2.25.1
diff view generated by jsdifflib
[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
[PULL 080/117] target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use these for the several varieties of floating-point
4
multiply-add instructions.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-78-richard.henderson@linaro.org
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
docs/system/arm/emulation.rst | 1 +
11
target/arm/translate-sve.c | 140 ++++++++++++++-----------------------
9
target/arm/cpu64.c | 1 +
12
1 file changed, 53 insertions(+), 87 deletions(-)
10
target/arm/cpu_tcg.c | 1 +
11
3 files changed, 3 insertions(+)
12
13
13
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/arm/emulation.rst
16
--- a/target/arm/translate-sve.c
16
+++ b/docs/system/arm/emulation.rst
17
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
18
- FEAT_PMULL (PMULL, PMULL2 instructions)
19
return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
19
- FEAT_PMUv3p1 (PMU Extensions v3.1)
20
}
20
- FEAT_PMUv3p4 (PMU Extensions v3.4)
21
21
+- FEAT_RAS (Reliability, availability, and serviceability)
22
+/* Invoke an out-of-line helper on 4 Zregs, plus a pointer. */
22
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
23
+static bool gen_gvec_ptr_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
23
- FEAT_RNG (Random number generator)
24
+ int rd, int rn, int rm, int ra,
24
- FEAT_SB (Speculation Barrier)
25
+ int data, TCGv_ptr ptr)
25
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
+{
26
index XXXXXXX..XXXXXXX 100644
27
+ if (fn == NULL) {
27
--- a/target/arm/cpu64.c
28
+ return false;
28
+++ b/target/arm/cpu64.c
29
+ }
29
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
30
+ if (sve_access_check(s)) {
30
t = cpu->isar.id_aa64pfr0;
31
+ unsigned vsz = vec_full_reg_size(s);
31
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
32
+ tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd),
32
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
33
+ vec_full_reg_offset(s, rn),
33
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */
34
+ vec_full_reg_offset(s, rm),
34
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
35
+ vec_full_reg_offset(s, ra),
35
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
36
+ ptr, vsz, vsz, data, fn);
36
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
37
+ }
37
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
38
+ return true;
38
index XXXXXXX..XXXXXXX 100644
39
+}
39
--- a/target/arm/cpu_tcg.c
40
+
40
+++ b/target/arm/cpu_tcg.c
41
+static bool gen_gvec_fpst_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
41
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
42
+ int rd, int rn, int rm, int ra,
42
43
+ int data, ARMFPStatusFlavour flavour)
43
t = cpu->isar.id_pfr0;
44
+{
44
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
45
+ TCGv_ptr status = fpstatus_ptr(flavour);
45
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
46
+ bool ret = gen_gvec_ptr_zzzz(s, fn, rd, rn, rm, ra, data, status);
46
cpu->isar.id_pfr0 = t;
47
+ tcg_temp_free_ptr(status);
47
48
+ return ret;
48
t = cpu->isar.id_pfr2;
49
+}
50
+
51
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
52
static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
53
int rd, int rn, int pg, int data)
54
@@ -XXX,XX +XXX,XX @@ DO_SVE2_RRXR_ROT(CDOT_zzxw_d, gen_helper_sve2_cdot_idx_d)
55
56
static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub)
57
{
58
- static gen_helper_gvec_4_ptr * const fns[3] = {
59
+ static gen_helper_gvec_4_ptr * const fns[4] = {
60
+ NULL,
61
gen_helper_gvec_fmla_idx_h,
62
gen_helper_gvec_fmla_idx_s,
63
gen_helper_gvec_fmla_idx_d,
64
};
65
-
66
- if (sve_access_check(s)) {
67
- unsigned vsz = vec_full_reg_size(s);
68
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
69
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
70
- vec_full_reg_offset(s, a->rn),
71
- vec_full_reg_offset(s, a->rm),
72
- vec_full_reg_offset(s, a->ra),
73
- status, vsz, vsz, (a->index << 1) | sub,
74
- fns[a->esz - 1]);
75
- tcg_temp_free_ptr(status);
76
- }
77
- return true;
78
+ return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
79
+ (a->index << 1) | sub,
80
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
81
}
82
83
static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
84
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
85
86
static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
87
{
88
- static gen_helper_gvec_4_ptr * const fns[2] = {
89
+ static gen_helper_gvec_4_ptr * const fns[4] = {
90
+ NULL,
91
gen_helper_gvec_fcmlah_idx,
92
gen_helper_gvec_fcmlas_idx,
93
+ NULL,
94
};
95
96
- tcg_debug_assert(a->esz == 1 || a->esz == 2);
97
tcg_debug_assert(a->rd == a->ra);
98
- if (sve_access_check(s)) {
99
- unsigned vsz = vec_full_reg_size(s);
100
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
101
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
102
- vec_full_reg_offset(s, a->rn),
103
- vec_full_reg_offset(s, a->rm),
104
- vec_full_reg_offset(s, a->ra),
105
- status, vsz, vsz,
106
- a->index * 4 + a->rot,
107
- fns[a->esz - 1]);
108
- tcg_temp_free_ptr(status);
109
- }
110
- return true;
111
+
112
+ return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
113
+ a->index * 4 + a->rot,
114
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
115
}
116
117
/*
118
@@ -XXX,XX +XXX,XX @@ static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
119
return false;
120
}
121
122
- if (sve_access_check(s)) {
123
- unsigned vsz = vec_full_reg_size(s);
124
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
125
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
126
- vec_full_reg_offset(s, a->rn),
127
- vec_full_reg_offset(s, a->rm),
128
- vec_full_reg_offset(s, a->ra),
129
- status, vsz, vsz, 0, fn);
130
- tcg_temp_free_ptr(status);
131
- }
132
- return true;
133
+ return gen_gvec_fpst_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR);
134
}
135
136
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
137
@@ -XXX,XX +XXX,XX @@ static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
138
if (!dc_isar_feature(aa64_sve2, s)) {
139
return false;
140
}
141
- if (sve_access_check(s)) {
142
- unsigned vsz = vec_full_reg_size(s);
143
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
144
- vec_full_reg_offset(s, a->rn),
145
- vec_full_reg_offset(s, a->rm),
146
- vec_full_reg_offset(s, a->ra),
147
- cpu_env, vsz, vsz, (sel << 1) | sub,
148
- gen_helper_sve2_fmlal_zzzw_s);
149
- }
150
- return true;
151
+ return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s,
152
+ a->rd, a->rn, a->rm, a->ra,
153
+ (sel << 1) | sub, cpu_env);
154
}
155
156
static bool trans_FMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
157
@@ -XXX,XX +XXX,XX @@ static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel)
158
if (!dc_isar_feature(aa64_sve2, s)) {
159
return false;
160
}
161
- if (sve_access_check(s)) {
162
- unsigned vsz = vec_full_reg_size(s);
163
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
164
- vec_full_reg_offset(s, a->rn),
165
- vec_full_reg_offset(s, a->rm),
166
- vec_full_reg_offset(s, a->ra),
167
- cpu_env, vsz, vsz,
168
- (a->index << 2) | (sel << 1) | sub,
169
- gen_helper_sve2_fmlal_zzxw_s);
170
- }
171
- return true;
172
+ return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s,
173
+ a->rd, a->rn, a->rm, a->ra,
174
+ (a->index << 2) | (sel << 1) | sub, cpu_env);
175
}
176
177
static bool trans_FMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
178
@@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
179
if (!dc_isar_feature(aa64_sve_bf16, s)) {
180
return false;
181
}
182
- if (sve_access_check(s)) {
183
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
184
- unsigned vsz = vec_full_reg_size(s);
185
-
186
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
187
- vec_full_reg_offset(s, a->rn),
188
- vec_full_reg_offset(s, a->rm),
189
- vec_full_reg_offset(s, a->ra),
190
- status, vsz, vsz, sel,
191
- gen_helper_gvec_bfmlal);
192
- tcg_temp_free_ptr(status);
193
- }
194
- return true;
195
+ return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal,
196
+ a->rd, a->rn, a->rm, a->ra, sel, FPST_FPCR);
197
}
198
199
static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
200
@@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
201
if (!dc_isar_feature(aa64_sve_bf16, s)) {
202
return false;
203
}
204
- if (sve_access_check(s)) {
205
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
206
- unsigned vsz = vec_full_reg_size(s);
207
-
208
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
209
- vec_full_reg_offset(s, a->rn),
210
- vec_full_reg_offset(s, a->rm),
211
- vec_full_reg_offset(s, a->ra),
212
- status, vsz, vsz, (a->index << 1) | sel,
213
- gen_helper_gvec_bfmlal_idx);
214
- tcg_temp_free_ptr(status);
215
- }
216
- return true;
217
+ return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx,
218
+ a->rd, a->rn, a->rm, a->ra,
219
+ (a->index << 1) | sel, FPST_FPCR);
220
}
221
222
static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
49
--
223
--
50
2.25.1
224
2.25.1
diff view generated by jsdifflib
New patch
[PULL 081/117] target/arm: Use TRANS_FEAT for FMMLA
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Being able to specify the feature predicate in TRANS_FEAT
4
makes it easier to split trans_FMMLA by element size,
5
which also happens to simplify the decode.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-79-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sve.decode | 7 +++----
13
target/arm/translate-sve.c | 27 ++++-----------------------
14
2 files changed, 7 insertions(+), 27 deletions(-)
15
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve.decode
19
+++ b/target/arm/sve.decode
20
@@ -XXX,XX +XXX,XX @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
21
USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm
22
23
### SVE2 floating point matrix multiply accumulate
24
-{
25
- BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
26
- FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm
27
-}
28
+BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
29
+FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
30
+FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
31
32
### SVE2 Memory Gather Load Group
33
34
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/translate-sve.c
37
+++ b/target/arm/translate-sve.c
38
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZPZZ_FP(FMINP, fminp)
39
* SVE Integer Multiply-Add (unpredicated)
40
*/
41
42
-static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
43
-{
44
- gen_helper_gvec_4_ptr *fn;
45
-
46
- switch (a->esz) {
47
- case MO_32:
48
- if (!dc_isar_feature(aa64_sve_f32mm, s)) {
49
- return false;
50
- }
51
- fn = gen_helper_fmmla_s;
52
- break;
53
- case MO_64:
54
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
55
- return false;
56
- }
57
- fn = gen_helper_fmmla_d;
58
- break;
59
- default:
60
- return false;
61
- }
62
-
63
- return gen_gvec_fpst_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR);
64
-}
65
+TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s,
66
+ a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
67
+TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d,
68
+ a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
69
70
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
71
NULL, gen_helper_sve2_sqdmlal_zzzw_h,
72
--
73
2.25.1
diff view generated by jsdifflib
[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
[PULL 082/117] target/arm: Move sve check into gen_gvec_fn_ppp
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Currently, the SMP configuration isn't considered when the CPU
3
Combined with the check already present in gen_mov_p,
4
topology is populated. In this case, it's impossible to provide
4
we can simplify some special cases in trans_AND_pppp
5
the default CPU-to-NUMA mapping or association based on the socket
5
and trans_BIC_pppp.
6
ID of the given CPU.
7
6
8
This takes account of SMP configuration when the CPU topology
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
is populated. The die ID for the given CPU isn't assigned since
8
Message-id: 20220527181907.189259-80-richard.henderson@linaro.org
10
it's not supported on arm/virt machine. Besides, the used SMP
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
12
to avoid testing failure
13
14
Signed-off-by: Gavin Shan <gshan@redhat.com>
15
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
16
Acked-by: Igor Mammedov <imammedo@redhat.com>
17
Message-id: 20220503140304.855514-4-gshan@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
11
---
20
hw/arm/virt.c | 15 ++++++++++++++-
12
target/arm/translate-sve.c | 30 ++++++++++++------------------
21
1 file changed, 14 insertions(+), 1 deletion(-)
13
1 file changed, 12 insertions(+), 18 deletions(-)
22
14
23
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/virt.c
17
--- a/target/arm/translate-sve.c
26
+++ b/hw/arm/virt.c
18
+++ b/target/arm/translate-sve.c
27
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
19
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
28
int n;
20
}
29
unsigned int max_cpus = ms->smp.max_cpus;
21
30
VirtMachineState *vms = VIRT_MACHINE(ms);
22
/* Invoke a vector expander on three Pregs. */
31
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
23
-static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
32
24
+static bool gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
33
if (ms->possible_cpus) {
25
int rd, int rn, int rm)
34
assert(ms->possible_cpus->len == max_cpus);
26
{
35
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
27
- unsigned psz = pred_gvec_reg_size(s);
36
ms->possible_cpus->cpus[n].type = ms->cpu_type;
28
- gvec_fn(MO_64, pred_full_reg_offset(s, rd),
37
ms->possible_cpus->cpus[n].arch_id =
29
- pred_full_reg_offset(s, rn),
38
virt_cpu_mp_affinity(vms, n);
30
- pred_full_reg_offset(s, rm), psz, psz);
39
+
31
+ if (sve_access_check(s)) {
40
+ assert(!mc->smp_props.dies_supported);
32
+ unsigned psz = pred_gvec_reg_size(s);
41
+ ms->possible_cpus->cpus[n].props.has_socket_id = true;
33
+ gvec_fn(MO_64, pred_full_reg_offset(s, rd),
42
+ ms->possible_cpus->cpus[n].props.socket_id =
34
+ pred_full_reg_offset(s, rn),
43
+ n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
35
+ pred_full_reg_offset(s, rm), psz, psz);
44
+ ms->possible_cpus->cpus[n].props.has_cluster_id = true;
36
+ }
45
+ ms->possible_cpus->cpus[n].props.cluster_id =
37
+ return true;
46
+ (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
38
}
47
+ ms->possible_cpus->cpus[n].props.has_core_id = true;
39
48
+ ms->possible_cpus->cpus[n].props.core_id =
40
/* Invoke a vector move on two Pregs. */
49
+ (n / ms->smp.threads) % ms->smp.cores;
41
@@ -XXX,XX +XXX,XX @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
50
ms->possible_cpus->cpus[n].props.has_thread_id = true;
42
};
51
- ms->possible_cpus->cpus[n].props.thread_id = n;
43
52
+ ms->possible_cpus->cpus[n].props.thread_id =
44
if (!a->s) {
53
+ n % ms->smp.threads;
45
- if (!sve_access_check(s)) {
46
- return true;
47
- }
48
if (a->rn == a->rm) {
49
if (a->pg == a->rn) {
50
- do_mov_p(s, a->rd, a->rn);
51
- } else {
52
- gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
53
+ return do_mov_p(s, a->rd, a->rn);
54
}
55
- return true;
56
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
57
} else if (a->pg == a->rn || a->pg == a->rm) {
58
- gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
59
- return true;
60
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
61
}
54
}
62
}
55
return ms->possible_cpus;
63
return do_pppp_flags(s, a, &op);
64
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
65
};
66
67
if (!a->s && a->pg == a->rn) {
68
- if (sve_access_check(s)) {
69
- gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
70
- }
71
- return true;
72
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
73
}
74
return do_pppp_flags(s, a, &op);
56
}
75
}
57
--
76
--
58
2.25.1
77
2.25.1
diff view generated by jsdifflib
[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
[PULL 083/117] target/arm: Implement NOT (prediates) alias
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When the PPTT table is built, the CPU topology is re-calculated, but
3
This alias is defined on EOR (prediates). While the
4
it's unecessary because the CPU topology has been populated in
4
same operation could be performed with NAND or NOR,
5
virt_possible_cpu_arch_ids() on arm/virt machine.
5
only bother with the official alias.
6
6
7
This reworks build_pptt() to avoid by reusing the existing IDs in
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
ms->possible_cpus. Currently, the only user of build_pptt() is
8
Message-id: 20220527181907.189259-81-richard.henderson@linaro.org
9
arm/virt machine.
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
11
Signed-off-by: Gavin Shan <gshan@redhat.com>
12
Tested-by: Yanan Wang <wangyanan55@huawei.com>
13
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
14
Acked-by: Igor Mammedov <imammedo@redhat.com>
15
Acked-by: Michael S. Tsirkin <mst@redhat.com>
16
Message-id: 20220503140304.855514-7-gshan@redhat.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
12
target/arm/translate-sve.c | 5 +++++
20
1 file changed, 48 insertions(+), 63 deletions(-)
13
1 file changed, 5 insertions(+)
21
14
22
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/acpi/aml-build.c
17
--- a/target/arm/translate-sve.c
25
+++ b/hw/acpi/aml-build.c
18
+++ b/target/arm/translate-sve.c
26
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
19
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
27
const char *oem_id, const char *oem_table_id)
20
.fno = gen_helper_sve_eor_pppp,
28
{
21
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
29
MachineClass *mc = MACHINE_GET_CLASS(ms);
22
};
30
- GQueue *list = g_queue_new();
23
+
31
- guint pptt_start = table_data->len;
24
+ /* Alias NOT (predicate) is EOR Pd.B, Pg/Z, Pn.B, Pg.B */
32
- guint parent_offset;
25
+ if (!a->s && a->pg == a->rm) {
33
- guint length, i;
26
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->pg, a->rn);
34
- int uid = 0;
27
+ }
35
- int socket;
28
return do_pppp_flags(s, a, &op);
36
+ CPUArchIdList *cpus = ms->possible_cpus;
37
+ int64_t socket_id = -1, cluster_id = -1, core_id = -1;
38
+ uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
39
+ uint32_t pptt_start = table_data->len;
40
+ int n;
41
AcpiTable table = { .sig = "PPTT", .rev = 2,
42
.oem_id = oem_id, .oem_table_id = oem_table_id };
43
44
acpi_table_begin(&table, table_data);
45
46
- for (socket = 0; socket < ms->smp.sockets; socket++) {
47
- g_queue_push_tail(list,
48
- GUINT_TO_POINTER(table_data->len - pptt_start));
49
- build_processor_hierarchy_node(
50
- table_data,
51
- /*
52
- * Physical package - represents the boundary
53
- * of a physical package
54
- */
55
- (1 << 0),
56
- 0, socket, NULL, 0);
57
- }
58
-
59
- if (mc->smp_props.clusters_supported) {
60
- length = g_queue_get_length(list);
61
- for (i = 0; i < length; i++) {
62
- int cluster;
63
-
64
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
65
- for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
66
- g_queue_push_tail(list,
67
- GUINT_TO_POINTER(table_data->len - pptt_start));
68
- build_processor_hierarchy_node(
69
- table_data,
70
- (0 << 0), /* not a physical package */
71
- parent_offset, cluster, NULL, 0);
72
- }
73
+ /*
74
+ * This works with the assumption that cpus[n].props.*_id has been
75
+ * sorted from top to down levels in mc->possible_cpu_arch_ids().
76
+ * Otherwise, the unexpected and duplicated containers will be
77
+ * created.
78
+ */
79
+ for (n = 0; n < cpus->len; n++) {
80
+ if (cpus->cpus[n].props.socket_id != socket_id) {
81
+ assert(cpus->cpus[n].props.socket_id > socket_id);
82
+ socket_id = cpus->cpus[n].props.socket_id;
83
+ cluster_id = -1;
84
+ core_id = -1;
85
+ socket_offset = table_data->len - pptt_start;
86
+ build_processor_hierarchy_node(table_data,
87
+ (1 << 0), /* Physical package */
88
+ 0, socket_id, NULL, 0);
89
}
90
- }
91
92
- length = g_queue_get_length(list);
93
- for (i = 0; i < length; i++) {
94
- int core;
95
-
96
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
97
- for (core = 0; core < ms->smp.cores; core++) {
98
- if (ms->smp.threads > 1) {
99
- g_queue_push_tail(list,
100
- GUINT_TO_POINTER(table_data->len - pptt_start));
101
- build_processor_hierarchy_node(
102
- table_data,
103
- (0 << 0), /* not a physical package */
104
- parent_offset, core, NULL, 0);
105
- } else {
106
- build_processor_hierarchy_node(
107
- table_data,
108
- (1 << 1) | /* ACPI Processor ID valid */
109
- (1 << 3), /* Node is a Leaf */
110
- parent_offset, uid++, NULL, 0);
111
+ if (mc->smp_props.clusters_supported) {
112
+ if (cpus->cpus[n].props.cluster_id != cluster_id) {
113
+ assert(cpus->cpus[n].props.cluster_id > cluster_id);
114
+ cluster_id = cpus->cpus[n].props.cluster_id;
115
+ core_id = -1;
116
+ cluster_offset = table_data->len - pptt_start;
117
+ build_processor_hierarchy_node(table_data,
118
+ (0 << 0), /* Not a physical package */
119
+ socket_offset, cluster_id, NULL, 0);
120
}
121
+ } else {
122
+ cluster_offset = socket_offset;
123
}
124
- }
125
126
- length = g_queue_get_length(list);
127
- for (i = 0; i < length; i++) {
128
- int thread;
129
+ if (ms->smp.threads == 1) {
130
+ build_processor_hierarchy_node(table_data,
131
+ (1 << 1) | /* ACPI Processor ID valid */
132
+ (1 << 3), /* Node is a Leaf */
133
+ cluster_offset, n, NULL, 0);
134
+ } else {
135
+ if (cpus->cpus[n].props.core_id != core_id) {
136
+ assert(cpus->cpus[n].props.core_id > core_id);
137
+ core_id = cpus->cpus[n].props.core_id;
138
+ core_offset = table_data->len - pptt_start;
139
+ build_processor_hierarchy_node(table_data,
140
+ (0 << 0), /* Not a physical package */
141
+ cluster_offset, core_id, NULL, 0);
142
+ }
143
144
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
145
- for (thread = 0; thread < ms->smp.threads; thread++) {
146
- build_processor_hierarchy_node(
147
- table_data,
148
+ build_processor_hierarchy_node(table_data,
149
(1 << 1) | /* ACPI Processor ID valid */
150
(1 << 2) | /* Processor is a Thread */
151
(1 << 3), /* Node is a Leaf */
152
- parent_offset, uid++, NULL, 0);
153
+ core_offset, n, NULL, 0);
154
}
155
}
156
157
- g_queue_free(list);
158
acpi_table_end(linker, &table);
159
}
29
}
160
30
161
--
31
--
162
2.25.1
32
2.25.1
diff view generated by jsdifflib
New patch
[PULL 084/117] target/arm: Use TRANS_FEAT for SEL_zpzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-82-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 5 +----
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_4 * const udiv_fns[4] = {
16
};
17
TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
18
19
-static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
20
-{
21
- return do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
22
-}
23
+TRANS_FEAT(SEL_zpzz, aa64_sve, do_sel_z, a->rd, a->rn, a->rm, a->pg, a->esz)
24
25
/*
26
*** SVE Integer Arithmetic - Unary Predicated Group
27
--
28
2.25.1
diff view generated by jsdifflib
New patch
[PULL 085/117] target/arm: Use TRANS_FEAT for MOVPRFX
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-83-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a)
16
* In the meantime, just emit the moves.
17
*/
18
19
-static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a)
20
-{
21
- return do_mov_z(s, a->rd, a->rn);
22
-}
23
-
24
-static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
27
-}
28
-
29
-static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
30
-{
31
- return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false);
32
-}
33
+TRANS_FEAT(MOVPRFX, aa64_sve, do_mov_z, a->rd, a->rn)
34
+TRANS_FEAT(MOVPRFX_m, aa64_sve, do_sel_z, a->rd, a->rn, a->rd, a->pg, a->esz)
35
+TRANS_FEAT(MOVPRFX_z, aa64_sve, do_movz_zpz, a->rd, a->rn, a->pg, a->esz, false)
36
37
/*
38
* SVE2 Integer Multiply - Unpredicated
39
--
40
2.25.1
diff view generated by jsdifflib
[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
[PULL 086/117] target/arm: Use TRANS_FEAT for FMLA
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When CPU-to-NUMA association isn't explicitly provided by users,
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
the default one is given by mc->get_default_cpu_node_id(). However,
4
Message-id: 20220527181907.189259-84-richard.henderson@linaro.org
5
the CPU topology isn't fully considered in the default association
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
and this causes CPU topology broken warnings on booting Linux guest.
7
8
For example, the following warning messages are observed when the
9
Linux guest is booted with the following command lines.
10
11
/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
12
-accel kvm -machine virt,gic-version=host \
13
-cpu host \
14
-smp 6,sockets=2,cores=3,threads=1 \
15
-m 1024M,slots=16,maxmem=64G \
16
-object memory-backend-ram,id=mem0,size=128M \
17
-object memory-backend-ram,id=mem1,size=128M \
18
-object memory-backend-ram,id=mem2,size=128M \
19
-object memory-backend-ram,id=mem3,size=128M \
20
-object memory-backend-ram,id=mem4,size=128M \
21
-object memory-backend-ram,id=mem4,size=384M \
22
-numa node,nodeid=0,memdev=mem0 \
23
-numa node,nodeid=1,memdev=mem1 \
24
-numa node,nodeid=2,memdev=mem2 \
25
-numa node,nodeid=3,memdev=mem3 \
26
-numa node,nodeid=4,memdev=mem4 \
27
-numa node,nodeid=5,memdev=mem5
28
:
29
alternatives: patching kernel code
30
BUG: arch topology borken
31
the CLS domain not a subset of the MC domain
32
<the above error log repeats>
33
BUG: arch topology borken
34
the DIE domain not a subset of the NODE domain
35
36
With current implementation of mc->get_default_cpu_node_id(),
37
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
38
That's incorrect because CPU#0/1/2 should be associated with same
39
NUMA node because they're seated in same socket.
40
41
This fixes the issue by considering the socket ID when the default
42
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
43
With this applied, no more CPU topology broken warnings are seen
44
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
45
there are no CPUs associated with NODE#2/3/4/5.
46
47
Signed-off-by: Gavin Shan <gshan@redhat.com>
48
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
49
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
50
Message-id: 20220503140304.855514-6-gshan@redhat.com
51
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
52
---
7
---
53
hw/arm/virt.c | 4 +++-
8
target/arm/translate-sve.c | 11 ++---------
54
1 file changed, 3 insertions(+), 1 deletion(-)
9
1 file changed, 2 insertions(+), 9 deletions(-)
55
10
56
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
57
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/arm/virt.c
13
--- a/target/arm/translate-sve.c
59
+++ b/hw/arm/virt.c
14
+++ b/target/arm/translate-sve.c
60
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
15
@@ -XXX,XX +XXX,XX @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub)
61
16
a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
62
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
63
{
64
- return idx % ms->numa_state->num_nodes;
65
+ int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
66
+
67
+ return socket_id % ms->numa_state->num_nodes;
68
}
17
}
69
18
70
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
19
-static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
20
-{
21
- return do_FMLA_zzxz(s, a, false);
22
-}
23
-
24
-static bool trans_FMLS_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
25
-{
26
- return do_FMLA_zzxz(s, a, true);
27
-}
28
+TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false)
29
+TRANS_FEAT(FMLS_zzxz, aa64_sve, do_FMLA_zzxz, a, true)
30
31
/*
32
*** SVE Floating Point Multiply Indexed Group
71
--
33
--
72
2.25.1
34
2.25.1
diff view generated by jsdifflib
[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
[PULL 087/117] target/arm: Use TRANS_FEAT for BFMLA
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In aarch64_numa_cpu(), the CPU and NUMA association is something
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
like below. Two threads in the same core/cluster/socket are
4
Message-id: 20220527181907.189259-85-richard.henderson@linaro.org
5
associated with two individual NUMA nodes, which is unreal as
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Igor Mammedov mentioned. We don't expect the association to break
7
NUMA-to-socket boundary, which matches with the real world.
8
9
NUMA-node socket cluster core thread
10
------------------------------------------
11
0 0 0 0 0
12
1 0 0 0 1
13
14
This corrects the topology for CPUs and their association with
15
NUMA nodes. After this patch is applied, the CPU and NUMA
16
association becomes something like below, which looks real.
17
Besides, socket/cluster/core/thread IDs are all checked when
18
the NUMA node IDs are verified. It helps to check if the CPU
19
topology is properly populated or not.
20
21
NUMA-node socket cluster core thread
22
------------------------------------------
23
0 1 0 0 0
24
1 0 0 0 0
25
26
Suggested-by: Igor Mammedov <imammedo@redhat.com>
27
Signed-off-by: Gavin Shan <gshan@redhat.com>
28
Acked-by: Igor Mammedov <imammedo@redhat.com>
29
Message-id: 20220503140304.855514-5-gshan@redhat.com
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
7
---
32
tests/qtest/numa-test.c | 18 ++++++++++++------
8
target/arm/translate-sve.c | 28 ++++------------------------
33
1 file changed, 12 insertions(+), 6 deletions(-)
9
1 file changed, 4 insertions(+), 24 deletions(-)
34
10
35
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
36
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
37
--- a/tests/qtest/numa-test.c
13
--- a/target/arm/translate-sve.c
38
+++ b/tests/qtest/numa-test.c
14
+++ b/target/arm/translate-sve.c
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
40
g_autofree char *cli = NULL;
16
41
17
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
42
cli = make_cli(data, "-machine "
18
{
43
- "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
19
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
44
+ "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
20
- return false;
45
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
21
- }
46
- "-numa cpu,node-id=1,thread-id=0 "
22
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal,
47
- "-numa cpu,node-id=0,thread-id=1");
23
a->rd, a->rn, a->rm, a->ra, sel, FPST_FPCR);
48
+ "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
24
}
49
+ "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
25
50
qts = qtest_init(cli);
26
-static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
51
cpus = get_cpus(qts, &resp);
27
-{
52
g_assert(cpus);
28
- return do_BFMLAL_zzzw(s, a, false);
53
29
-}
54
while ((e = qlist_pop(cpus))) {
30
-
55
QDict *cpu, *props;
31
-static bool trans_BFMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
56
- int64_t thread, node;
32
-{
57
+ int64_t socket, cluster, core, thread, node;
33
- return do_BFMLAL_zzzw(s, a, true);
58
34
-}
59
cpu = qobject_to(QDict, e);
35
+TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false)
60
g_assert(qdict_haskey(cpu, "props"));
36
+TRANS_FEAT(BFMLALT_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, true)
61
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
37
62
38
static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
63
g_assert(qdict_haskey(props, "node-id"));
39
{
64
node = qdict_get_int(props, "node-id");
40
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
65
+ g_assert(qdict_haskey(props, "socket-id"));
41
- return false;
66
+ socket = qdict_get_int(props, "socket-id");
42
- }
67
+ g_assert(qdict_haskey(props, "cluster-id"));
43
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx,
68
+ cluster = qdict_get_int(props, "cluster-id");
44
a->rd, a->rn, a->rm, a->ra,
69
+ g_assert(qdict_haskey(props, "core-id"));
45
(a->index << 1) | sel, FPST_FPCR);
70
+ core = qdict_get_int(props, "core-id");
46
}
71
g_assert(qdict_haskey(props, "thread-id"));
47
72
thread = qdict_get_int(props, "thread-id");
48
-static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
73
49
-{
74
- if (thread == 0) {
50
- return do_BFMLAL_zzxw(s, a, false);
75
+ if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
51
-}
76
g_assert_cmpint(node, ==, 1);
52
-
77
- } else if (thread == 1) {
53
-static bool trans_BFMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a)
78
+ } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
54
-{
79
g_assert_cmpint(node, ==, 0);
55
- return do_BFMLAL_zzxw(s, a, true);
80
} else {
56
-}
81
g_assert(false);
57
+TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
58
+TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true)
82
--
59
--
83
2.25.1
60
2.25.1
diff view generated by jsdifflib
[PULL 14/32] target/arm: Add minimal RAS registers
[PULL 088/117] target/arm: Rename do_zzz_fp to gen_gvec_ool_fpst_arg_zzz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add only the system registers required to implement zero error
3
Rename the function to match gen_gvec_ool_arg_zzz,
4
records. This means that all values for ERRSELR are out of range,
4
and move to be adjacent. Split out gen_gvec_fpst_zzz
5
which means that it and all of the indexed error record registers
5
as a helper while we're at it.
6
need not be implemented.
7
6
8
Add the EL2 registers required for injecting virtual SError.
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
8
Message-id: 20220527181907.189259-86-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
target/arm/cpu.h | 5 +++
12
target/arm/translate-sve.c | 50 +++++++++++++++++++++++---------------
16
target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 30 insertions(+), 20 deletions(-)
17
2 files changed, 89 insertions(+)
18
14
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
17
--- a/target/arm/translate-sve.c
22
+++ b/target/arm/cpu.h
18
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
24
uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
20
return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
25
uint64_t gcr_el1;
21
}
26
uint64_t rgsr_el1;
22
23
+/* Invoke an out-of-line helper on 3 Zregs, plus float_status. */
24
+static bool gen_gvec_fpst_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
25
+ int rd, int rn, int rm,
26
+ int data, ARMFPStatusFlavour flavour)
27
+{
28
+ if (fn == NULL) {
29
+ return false;
30
+ }
31
+ if (sve_access_check(s)) {
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ TCGv_ptr status = fpstatus_ptr(flavour);
27
+
34
+
28
+ /* Minimal RAS registers */
35
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
29
+ uint64_t disr_el1;
36
+ vec_full_reg_offset(s, rn),
30
+ uint64_t vdisr_el2;
37
+ vec_full_reg_offset(s, rm),
31
+ uint64_t vsesr_el2;
38
+ status, vsz, vsz, data, fn);
32
} cp15;
33
34
struct {
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper.c
38
+++ b/target/arm/helper.c
39
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
40
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
41
};
42
43
+/*
44
+ * Check for traps to RAS registers, which are controlled
45
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
46
+ */
47
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
48
+ bool isread)
49
+{
50
+ int el = arm_current_el(env);
51
+
39
+
52
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
40
+ tcg_temp_free_ptr(status);
53
+ return CP_ACCESS_TRAP_EL2;
54
+ }
41
+ }
55
+ if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
42
+ return true;
56
+ return CP_ACCESS_TRAP_EL3;
57
+ }
58
+ return CP_ACCESS_OK;
59
+}
43
+}
60
+
44
+
61
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
45
+static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
46
+ arg_rrr_esz *a, int data)
62
+{
47
+{
63
+ int el = arm_current_el(env);
48
+ return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data,
64
+
49
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
65
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
66
+ return env->cp15.vdisr_el2;
67
+ }
68
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
69
+ return 0; /* RAZ/WI */
70
+ }
71
+ return env->cp15.disr_el1;
72
+}
50
+}
73
+
51
+
74
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
52
/* Invoke an out-of-line helper on 4 Zregs. */
75
+{
53
static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
76
+ int el = arm_current_el(env);
54
int rd, int rn, int rm, int ra, int data)
77
+
55
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
78
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
56
*** SVE Floating Point Arithmetic - Unpredicated Group
79
+ env->cp15.vdisr_el2 = val;
57
*/
80
+ return;
58
81
+ }
59
-static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a,
82
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
60
- gen_helper_gvec_3_ptr *fn)
83
+ return; /* RAZ/WI */
61
-{
84
+ }
62
- if (fn == NULL) {
85
+ env->cp15.disr_el1 = val;
63
- return false;
86
+}
64
- }
87
+
65
- if (sve_access_check(s)) {
88
+/*
66
- unsigned vsz = vec_full_reg_size(s);
89
+ * Minimal RAS implementation with no Error Records.
67
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
90
+ * Which means that all of the Error Record registers:
68
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
91
+ * ERXADDR_EL1
69
- vec_full_reg_offset(s, a->rn),
92
+ * ERXCTLR_EL1
70
- vec_full_reg_offset(s, a->rm),
93
+ * ERXFR_EL1
71
- status, vsz, vsz, 0, fn);
94
+ * ERXMISC0_EL1
72
- tcg_temp_free_ptr(status);
95
+ * ERXMISC1_EL1
73
- }
96
+ * ERXMISC2_EL1
74
- return true;
97
+ * ERXMISC3_EL1
75
-}
98
+ * ERXPFGCDN_EL1 (RASv1p1)
76
-
99
+ * ERXPFGCTL_EL1 (RASv1p1)
77
-
100
+ * ERXPFGF_EL1 (RASv1p1)
78
#define DO_FP3(NAME, name) \
101
+ * ERXSTATUS_EL1
79
static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
102
+ * and
80
{ \
103
+ * ERRSELR_EL1
81
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
104
+ * may generate UNDEFINED, which is the effect we get by not
82
NULL, gen_helper_gvec_##name##_h, \
105
+ * listing them at all.
83
gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \
106
+ */
84
}; \
107
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
85
- return do_zzz_fp(s, a, fns[a->esz]); \
108
+ { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
86
+ return gen_gvec_fpst_arg_zzz(s, fns[a->esz], a, 0); \
109
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
87
}
110
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
88
111
+ .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
89
DO_FP3(FADD_zzz, fadd)
112
+ { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
113
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
114
+ .access = PL1_R, .accessfn = access_terr,
115
+ .type = ARM_CP_CONST, .resetvalue = 0 },
116
+ { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
117
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
118
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
119
+ { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
120
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
121
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
122
+};
123
+
124
/* Return the exception level to which exceptions should be taken
125
* via SVEAccessTrap. If an exception should be routed through
126
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
127
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
128
if (cpu_isar_feature(aa64_ssbs, cpu)) {
129
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
130
}
131
+ if (cpu_isar_feature(any_ras, cpu)) {
132
+ define_arm_cp_regs(cpu, minimal_ras_reginfo);
133
+ }
134
135
if (cpu_isar_feature(aa64_vh, cpu) ||
136
cpu_isar_feature(aa64_debugv8p2, cpu)) {
137
--
90
--
138
2.25.1
91
2.25.1
diff view generated by jsdifflib
[PULL 27/32] qapi/machine.json: Add cluster-id
[PULL 089/117] target/arm: Use TRANS_FEAT for DO_FP3
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This adds cluster-id in CPU instance properties, which will be used
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
by arm/virt machine. Besides, the cluster-id is also verified or
4
Message-id: 20220527181907.189259-87-richard.henderson@linaro.org
5
dumped in various spots:
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
7
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
8
CPU with its NUMA node.
9
10
* hw/core/machine.c::machine_numa_finish_cpu_init() to record
11
CPU slots with no NUMA mapping set.
12
13
* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
14
cluster-id.
15
16
Signed-off-by: Gavin Shan <gshan@redhat.com>
17
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
18
Acked-by: Igor Mammedov <imammedo@redhat.com>
19
Message-id: 20220503140304.855514-2-gshan@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
7
---
22
qapi/machine.json | 6 ++++--
8
target/arm/translate-sve.c | 7 ++-----
23
hw/core/machine-hmp-cmds.c | 4 ++++
9
1 file changed, 2 insertions(+), 5 deletions(-)
24
hw/core/machine.c | 16 ++++++++++++++++
25
3 files changed, 24 insertions(+), 2 deletions(-)
26
10
27
diff --git a/qapi/machine.json b/qapi/machine.json
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
28
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
29
--- a/qapi/machine.json
13
--- a/target/arm/translate-sve.c
30
+++ b/qapi/machine.json
14
+++ b/target/arm/translate-sve.c
31
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
32
# @node-id: NUMA node ID the CPU belongs to
16
*/
33
# @socket-id: socket number within node/board the CPU belongs to
17
34
# @die-id: die number within socket the CPU belongs to (since 4.1)
18
#define DO_FP3(NAME, name) \
35
-# @core-id: core number within die the CPU belongs to
19
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
36
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
20
-{ \
37
+# @core-id: core number within cluster the CPU belongs to
21
- static gen_helper_gvec_3_ptr * const fns[4] = { \
38
# @thread-id: thread number within core the CPU belongs to
22
+ static gen_helper_gvec_3_ptr * const name##_fns[4] = { \
39
#
23
NULL, gen_helper_gvec_##name##_h, \
40
-# Note: currently there are 5 properties that could be present
24
gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \
41
+# Note: currently there are 6 properties that could be present
25
}; \
42
# but management should be prepared to pass through other
26
- return gen_gvec_fpst_arg_zzz(s, fns[a->esz], a, 0); \
43
# properties with device_add command to allow for future
27
-}
44
# interface extension. This also requires the filed names to be kept in
28
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_arg_zzz, name##_fns[a->esz], a, 0)
45
@@ -XXX,XX +XXX,XX @@
29
46
'data': { '*node-id': 'int',
30
DO_FP3(FADD_zzz, fadd)
47
'*socket-id': 'int',
31
DO_FP3(FSUB_zzz, fsub)
48
'*die-id': 'int',
49
+ '*cluster-id': 'int',
50
'*core-id': 'int',
51
'*thread-id': 'int'
52
}
53
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/core/machine-hmp-cmds.c
56
+++ b/hw/core/machine-hmp-cmds.c
57
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
58
if (c->has_die_id) {
59
monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
60
}
61
+ if (c->has_cluster_id) {
62
+ monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n",
63
+ c->cluster_id);
64
+ }
65
if (c->has_core_id) {
66
monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
67
}
68
diff --git a/hw/core/machine.c b/hw/core/machine.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/core/machine.c
71
+++ b/hw/core/machine.c
72
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
73
return;
74
}
75
76
+ if (props->has_cluster_id && !slot->props.has_cluster_id) {
77
+ error_setg(errp, "cluster-id is not supported");
78
+ return;
79
+ }
80
+
81
if (props->has_socket_id && !slot->props.has_socket_id) {
82
error_setg(errp, "socket-id is not supported");
83
return;
84
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
85
continue;
86
}
87
88
+ if (props->has_cluster_id &&
89
+ props->cluster_id != slot->props.cluster_id) {
90
+ continue;
91
+ }
92
+
93
if (props->has_die_id && props->die_id != slot->props.die_id) {
94
continue;
95
}
96
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
97
}
98
g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
99
}
100
+ if (cpu->props.has_cluster_id) {
101
+ if (s->len) {
102
+ g_string_append_printf(s, ", ");
103
+ }
104
+ g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
105
+ }
106
if (cpu->props.has_core_id) {
107
if (s->len) {
108
g_string_append_printf(s, ", ");
109
--
32
--
110
2.25.1
33
2.25.1
diff view generated by jsdifflib
[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
[PULL 090/117] target/arm: Use TRANS_FEAT for FMUL_zzx
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The sbsa-ref machine is continuously evolving. Some of the changes we
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
want to make in the near future, to align with real components (e.g.
4
Message-id: 20220527181907.189259-88-richard.henderson@linaro.org
5
the GIC-700), will break compatibility for existing firmware.
6
7
Introduce two new properties to the DT generated on machine generation:
8
- machine-version-major
9
To be incremented when a platform change makes the machine
10
incompatible with existing firmware.
11
- machine-version-minor
12
To be incremented when functionality is added to the machine
13
without causing incompatibility with existing firmware.
14
to be reset to 0 when machine-version-major is incremented.
15
16
This versioning scheme is *neither*:
17
- A QEMU versioned machine type; a given version of QEMU will emulate
18
a given version of the platform.
19
- A reflection of level of SBSA (now SystemReady SR) support provided.
20
21
The version will increment on guest-visible functional changes only,
22
akin to a revision ID register found on a physical platform.
23
24
These properties are both introduced with the value 0.
25
(Hence, a machine where the DT is lacking these nodes is equivalent
26
to version 0.0.)
27
28
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
29
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
30
Cc: Peter Maydell <peter.maydell@linaro.org>
31
Cc: Radoslaw Biernacki <rad@semihalf.com>
32
Cc: Cédric Le Goater <clg@kaod.org>
33
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
---
7
---
36
hw/arm/sbsa-ref.c | 14 ++++++++++++++
8
target/arm/translate-sve.c | 26 +++++++-------------------
37
1 file changed, 14 insertions(+)
9
1 file changed, 7 insertions(+), 19 deletions(-)
38
10
39
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
40
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/sbsa-ref.c
13
--- a/target/arm/translate-sve.c
42
+++ b/hw/arm/sbsa-ref.c
14
+++ b/target/arm/translate-sve.c
43
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMLS_zzxz, aa64_sve, do_FMLA_zzxz, a, true)
44
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
16
*** SVE Floating Point Multiply Indexed Group
45
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
17
*/
46
18
47
+ /*
19
-static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a)
48
+ * This versioning scheme is for informing platform fw only. It is neither:
20
-{
49
+ * - A QEMU versioned machine type; a given version of QEMU will emulate
21
- static gen_helper_gvec_3_ptr * const fns[3] = {
50
+ * a given version of the platform.
22
- gen_helper_gvec_fmul_idx_h,
51
+ * - A reflection of level of SBSA (now SystemReady SR) support provided.
23
- gen_helper_gvec_fmul_idx_s,
52
+ *
24
- gen_helper_gvec_fmul_idx_d,
53
+ * machine-version-major: updated when changes breaking fw compatibility
25
- };
54
+ * are introduced.
26
-
55
+ * machine-version-minor: updated when features are added that don't break
27
- if (sve_access_check(s)) {
56
+ * fw compatibility.
28
- unsigned vsz = vec_full_reg_size(s);
57
+ */
29
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
58
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
30
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
59
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
31
- vec_full_reg_offset(s, a->rn),
60
+
32
- vec_full_reg_offset(s, a->rm),
61
if (ms->numa_state->have_numa_distance) {
33
- status, vsz, vsz, a->index, fns[a->esz - 1]);
62
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
34
- tcg_temp_free_ptr(status);
63
uint32_t *matrix = g_malloc0(size);
35
- }
36
- return true;
37
-}
38
+static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = {
39
+ NULL, gen_helper_gvec_fmul_idx_h,
40
+ gen_helper_gvec_fmul_idx_s, gen_helper_gvec_fmul_idx_d,
41
+};
42
+TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
43
+ fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index,
44
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
45
46
/*
47
*** SVE Floating Point Fast Reduction Group
64
--
48
--
65
2.25.1
49
2.25.1
66
67
diff view generated by jsdifflib
[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
[PULL 091/117] target/arm: Use TRANS_FEAT for FTMAD
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Enable writes to the TERR and TEA bits when RAS is enabled.
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
These bits are otherwise RES0.
4
Message-id: 20220527181907.189259-89-richard.henderson@linaro.org
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
target/arm/helper.c | 9 +++++++++
8
target/arm/translate-sve.c | 29 +++++++----------------------
12
1 file changed, 9 insertions(+)
9
1 file changed, 7 insertions(+), 22 deletions(-)
13
10
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
13
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/helper.c
14
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
15
@@ -XXX,XX +XXX,XX @@ DO_PPZ(FCMNE_ppz0, fcmne0)
19
}
16
*** SVE floating-point trig multiply-add coefficient
20
valid_mask &= ~SCR_NET;
17
*/
21
18
22
+ if (cpu_isar_feature(aa64_ras, cpu)) {
19
-static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a)
23
+ valid_mask |= SCR_TERR;
20
-{
24
+ }
21
- static gen_helper_gvec_3_ptr * const fns[3] = {
25
if (cpu_isar_feature(aa64_lor, cpu)) {
22
- gen_helper_sve_ftmad_h,
26
valid_mask |= SCR_TLOR;
23
- gen_helper_sve_ftmad_s,
27
}
24
- gen_helper_sve_ftmad_d,
28
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
25
- };
29
}
26
-
30
} else {
27
- if (a->esz == 0) {
31
valid_mask &= ~(SCR_RW | SCR_ST);
28
- return false;
32
+ if (cpu_isar_feature(aa32_ras, cpu)) {
29
- }
33
+ valid_mask |= SCR_TERR;
30
- if (sve_access_check(s)) {
34
+ }
31
- unsigned vsz = vec_full_reg_size(s);
35
}
32
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
36
33
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
37
if (!arm_feature(env, ARM_FEATURE_EL2)) {
34
- vec_full_reg_offset(s, a->rn),
38
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
35
- vec_full_reg_offset(s, a->rm),
39
if (cpu_isar_feature(aa64_vh, cpu)) {
36
- status, vsz, vsz, a->imm, fns[a->esz - 1]);
40
valid_mask |= HCR_E2H;
37
- tcg_temp_free_ptr(status);
41
}
38
- }
42
+ if (cpu_isar_feature(aa64_ras, cpu)) {
39
- return true;
43
+ valid_mask |= HCR_TERR | HCR_TEA;
40
-}
44
+ }
41
+static gen_helper_gvec_3_ptr * const ftmad_fns[4] = {
45
if (cpu_isar_feature(aa64_lor, cpu)) {
42
+ NULL, gen_helper_sve_ftmad_h,
46
valid_mask |= HCR_TLOR;
43
+ gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d,
47
}
44
+};
45
+TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
46
+ ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
47
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
48
49
/*
50
*** SVE Floating Point Accumulating Reduction Group
48
--
51
--
49
2.25.1
52
2.25.1
diff view generated by jsdifflib
[PULL 02/32] target/arm: Handle cpreg registration for missing EL
[PULL 092/117] target/arm: Move null function and sve check into do_reduce
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
More gracefully handle cpregs when EL2 and/or EL3 are missing.
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
If the reg is entirely inaccessible, do not register it at all.
4
Message-id: 20220527181907.189259-90-richard.henderson@linaro.org
5
If the reg is for EL2, and EL3 is present but EL2 is not,
6
either discard, squash to res0, const, or keep unchanged.
7
8
Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
9
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
10
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
11
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
12
13
This will simplify cpreg registration for conditional arm features.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
7
---
20
target/arm/cpregs.h | 11 +++
8
target/arm/translate-sve.c | 30 +++++++++++++++++-------------
21
target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
9
1 file changed, 17 insertions(+), 13 deletions(-)
22
2 files changed, 133 insertions(+), 56 deletions(-)
23
10
24
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
25
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpregs.h
13
--- a/target/arm/translate-sve.c
27
+++ b/target/arm/cpregs.h
14
+++ b/target/arm/translate-sve.c
28
@@ -XXX,XX +XXX,XX @@ enum {
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
29
ARM_CP_SVE = 1 << 14,
16
typedef void gen_helper_fp_reduce(TCGv_i64, TCGv_ptr, TCGv_ptr,
30
/* Flag: Do not expose in gdb sysreg xml. */
17
TCGv_ptr, TCGv_i32);
31
ARM_CP_NO_GDB = 1 << 15,
18
32
+ /*
19
-static void do_reduce(DisasContext *s, arg_rpr_esz *a,
33
+ * Flags: If EL3 but not EL2...
20
+static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
34
+ * - UNDEF: discard the cpreg,
21
gen_helper_fp_reduce *fn)
35
+ * - KEEP: retain the cpreg as is,
36
+ * - C_NZ: set const on the cpreg, but retain resetvalue,
37
+ * - else: set const on the cpreg, zero resetvalue, aka RES0.
38
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
39
+ */
40
+ ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16,
41
+ ARM_CP_EL3_NO_EL2_KEEP = 1 << 17,
42
+ ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18,
43
};
44
45
/*
46
diff --git a/target/arm/helper.c b/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/helper.c
49
+++ b/target/arm/helper.c
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
51
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
52
{ .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
53
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
54
- .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
55
+ .access = PL2_RW,
56
+ .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
57
.fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
58
{ .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
59
.opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
60
- .access = PL2_RW, .resetvalue = 0,
61
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
62
.writefn = dacr_write, .raw_writefn = raw_write,
63
.fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
64
{ .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
65
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
66
- .access = PL2_RW, .resetvalue = 0,
67
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
68
.fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
69
{ .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
70
.type = ARM_CP_ALIAS,
71
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
72
.writefn = tlbimva_hyp_is_write },
73
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
74
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
75
- .type = ARM_CP_NO_RAW, .access = PL2_W,
76
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
77
.writefn = tlbi_aa64_alle2_write },
78
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
79
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
80
- .type = ARM_CP_NO_RAW, .access = PL2_W,
81
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
82
.writefn = tlbi_aa64_vae2_write },
83
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
84
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
85
- .access = PL2_W, .type = ARM_CP_NO_RAW,
86
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
87
.writefn = tlbi_aa64_vae2_write },
88
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
89
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
90
- .access = PL2_W, .type = ARM_CP_NO_RAW,
91
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
92
.writefn = tlbi_aa64_alle2is_write },
93
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
94
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
95
- .type = ARM_CP_NO_RAW, .access = PL2_W,
96
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
97
.writefn = tlbi_aa64_vae2is_write },
98
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
99
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
100
- .access = PL2_W, .type = ARM_CP_NO_RAW,
101
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
102
.writefn = tlbi_aa64_vae2is_write },
103
#ifndef CONFIG_USER_ONLY
104
/* Unlike the other EL2-related AT operations, these must
105
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
106
{ .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
107
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
108
.access = PL2_W, .accessfn = at_s1e2_access,
109
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
110
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
111
+ .writefn = ats_write64 },
112
{ .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
113
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
114
.access = PL2_W, .accessfn = at_s1e2_access,
115
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
116
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
117
+ .writefn = ats_write64 },
118
/* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
119
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
120
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
121
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
122
{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
123
.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
124
.access = PL2_RW, .accessfn = access_tda,
125
- .type = ARM_CP_NOP },
126
+ .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
127
/* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
128
* Channel but Linux may try to access this register. The 32-bit
129
* alias is DBGDCCINT.
130
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
131
.access = PL2_W, .type = ARM_CP_NOP },
132
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
134
- .access = PL2_W, .type = ARM_CP_NO_RAW,
135
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
136
.writefn = tlbi_aa64_rvae2is_write },
137
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
138
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
139
- .access = PL2_W, .type = ARM_CP_NO_RAW,
140
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
141
.writefn = tlbi_aa64_rvae2is_write },
142
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
143
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
145
.access = PL2_W, .type = ARM_CP_NOP },
146
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
147
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
148
- .access = PL2_W, .type = ARM_CP_NO_RAW,
149
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
150
.writefn = tlbi_aa64_rvae2is_write },
151
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
152
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
153
- .access = PL2_W, .type = ARM_CP_NO_RAW,
154
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
155
.writefn = tlbi_aa64_rvae2is_write },
156
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
157
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
158
- .access = PL2_W, .type = ARM_CP_NO_RAW,
159
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
160
.writefn = tlbi_aa64_rvae2_write },
161
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
162
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
163
- .access = PL2_W, .type = ARM_CP_NO_RAW,
164
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
165
.writefn = tlbi_aa64_rvae2_write },
166
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
167
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
168
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
169
.writefn = tlbi_aa64_vae1is_write },
170
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
172
- .access = PL2_W, .type = ARM_CP_NO_RAW,
173
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
174
.writefn = tlbi_aa64_alle2is_write },
175
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
176
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
177
- .access = PL2_W, .type = ARM_CP_NO_RAW,
178
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
179
.writefn = tlbi_aa64_vae2is_write },
180
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
181
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
182
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
183
.writefn = tlbi_aa64_alle1is_write },
184
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
185
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
186
- .access = PL2_W, .type = ARM_CP_NO_RAW,
187
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
188
.writefn = tlbi_aa64_vae2is_write },
189
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
190
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
191
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
192
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
193
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
194
.access = PL2_RW, .accessfn = access_el3_aa32ns,
195
- .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
196
+ .resetvalue = cpu->midr,
197
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
198
.fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
199
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
200
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
201
.access = PL2_RW, .resetvalue = cpu->midr,
202
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
203
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
204
{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
205
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
206
.access = PL2_RW, .accessfn = access_el3_aa32ns,
207
- .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
208
+ .resetvalue = vmpidr_def,
209
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
210
.fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
211
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
212
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
213
- .access = PL2_RW,
214
- .resetvalue = vmpidr_def,
215
+ .access = PL2_RW, .resetvalue = vmpidr_def,
216
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
217
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
218
};
219
define_arm_cp_regs(cpu, vpidr_regs);
220
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
221
int crm, int opc1, int opc2,
222
const char *name)
223
{
22
{
224
+ CPUARMState *env = &cpu->env;
23
- unsigned vsz = vec_full_reg_size(s);
225
uint32_t key;
24
- unsigned p2vsz = pow2ceil(vsz);
226
ARMCPRegInfo *r2;
25
- TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
227
bool is64 = r->type & ARM_CP_64BIT;
26
+ unsigned vsz, p2vsz;
228
bool ns = secstate & ARM_CP_SECSTATE_NS;
27
+ TCGv_i32 t_desc;
229
int cp = r->cp;
28
TCGv_ptr t_zn, t_pg, status;
230
- bool isbanked;
29
TCGv_i64 temp;
231
size_t name_len;
30
232
+ bool make_const;
31
+ if (fn == NULL) {
233
32
+ return false;
234
switch (state) {
33
+ }
235
case ARM_CP_STATE_AA32:
34
+ if (!sve_access_check(s)) {
236
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
35
+ return true;
237
}
238
}
239
240
+ /*
241
+ * Eliminate registers that are not present because the EL is missing.
242
+ * Doing this here makes it easier to put all registers for a given
243
+ * feature into the same ARMCPRegInfo array and define them all at once.
244
+ */
245
+ make_const = false;
246
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
247
+ /*
248
+ * An EL2 register without EL2 but with EL3 is (usually) RES0.
249
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
250
+ */
251
+ int min_el = ctz32(r->access) / 2;
252
+ if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
253
+ if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
254
+ return;
255
+ }
256
+ make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
257
+ }
258
+ } else {
259
+ CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
260
+ ? PL2_RW : PL1_RW);
261
+ if ((r->access & max_el) == 0) {
262
+ return;
263
+ }
264
+ }
36
+ }
265
+
37
+
266
/* Combine cpreg and name into one allocation. */
38
+ vsz = vec_full_reg_size(s);
267
name_len = strlen(name) + 1;
39
+ p2vsz = pow2ceil(vsz);
268
r2 = g_malloc(sizeof(*r2) + name_len);
40
+ t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
269
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
41
temp = tcg_temp_new_i64();
270
r2->opaque = opaque;
42
t_zn = tcg_temp_new_ptr();
271
}
43
t_pg = tcg_temp_new_ptr();
272
44
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
273
- isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
45
274
- if (isbanked) {
46
write_fp_dreg(s, a->rd, temp);
275
+ if (make_const) {
47
tcg_temp_free_i64(temp);
276
+ /* This should not have been a very special register to begin. */
48
+ return true;
277
+ int old_special = r2->type & ARM_CP_SPECIAL_MASK;
49
}
278
+ assert(old_special == 0 || old_special == ARM_CP_NOP);
50
279
/*
51
#define DO_VPZ(NAME, name) \
280
- * Register is banked (using both entries in array).
52
static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
281
- * Overwriting fieldoffset as the array is only used to define
53
{ \
282
- * banked registers but later only fieldoffset is used.
54
- static gen_helper_fp_reduce * const fns[3] = { \
283
+ * Set the special function to CONST, retaining the other flags.
55
- gen_helper_sve_##name##_h, \
284
+ * This is important for e.g. ARM_CP_SVE so that we still
56
+ static gen_helper_fp_reduce * const fns[4] = { \
285
+ * take the SVE trap if CPTR_EL3.EZ == 0.
57
+ NULL, gen_helper_sve_##name##_h, \
286
*/
58
gen_helper_sve_##name##_s, \
287
- r2->fieldoffset = r->bank_fieldoffsets[ns];
59
gen_helper_sve_##name##_d, \
288
- }
60
}; \
289
+ r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
61
- if (a->esz == 0) { \
290
+ /*
62
- return false; \
291
+ * Usually, these registers become RES0, but there are a few
63
- } \
292
+ * special cases like VPIDR_EL2 which have a constant non-zero
64
- if (sve_access_check(s)) { \
293
+ * value with writes ignored.
65
- do_reduce(s, a, fns[a->esz - 1]); \
294
+ */
66
- } \
295
+ if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
67
- return true; \
296
+ r2->resetvalue = 0;
68
+ return do_reduce(s, a, fns[a->esz]); \
297
+ }
69
}
298
+ /*
70
299
+ * ARM_CP_CONST has precedence, so removing the callbacks and
71
DO_VPZ(FADDV, faddv)
300
+ * offsets are not strictly necessary, but it is potentially
301
+ * less confusing to debug later.
302
+ */
303
+ r2->readfn = NULL;
304
+ r2->writefn = NULL;
305
+ r2->raw_readfn = NULL;
306
+ r2->raw_writefn = NULL;
307
+ r2->resetfn = NULL;
308
+ r2->fieldoffset = 0;
309
+ r2->bank_fieldoffsets[0] = 0;
310
+ r2->bank_fieldoffsets[1] = 0;
311
+ } else {
312
+ bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
313
314
- if (state == ARM_CP_STATE_AA32) {
315
if (isbanked) {
316
/*
317
- * If the register is banked then we don't need to migrate or
318
- * reset the 32-bit instance in certain cases:
319
- *
320
- * 1) If the register has both 32-bit and 64-bit instances then we
321
- * can count on the 64-bit instance taking care of the
322
- * non-secure bank.
323
- * 2) If ARMv8 is enabled then we can count on a 64-bit version
324
- * taking care of the secure bank. This requires that separate
325
- * 32 and 64-bit definitions are provided.
326
+ * Register is banked (using both entries in array).
327
+ * Overwriting fieldoffset as the array is only used to define
328
+ * banked registers but later only fieldoffset is used.
329
*/
330
- if ((r->state == ARM_CP_STATE_BOTH && ns) ||
331
- (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
332
+ r2->fieldoffset = r->bank_fieldoffsets[ns];
333
+ }
334
+ if (state == ARM_CP_STATE_AA32) {
335
+ if (isbanked) {
336
+ /*
337
+ * If the register is banked then we don't need to migrate or
338
+ * reset the 32-bit instance in certain cases:
339
+ *
340
+ * 1) If the register has both 32-bit and 64-bit instances
341
+ * then we can count on the 64-bit instance taking care
342
+ * of the non-secure bank.
343
+ * 2) If ARMv8 is enabled then we can count on a 64-bit
344
+ * version taking care of the secure bank. This requires
345
+ * that separate 32 and 64-bit definitions are provided.
346
+ */
347
+ if ((r->state == ARM_CP_STATE_BOTH && ns) ||
348
+ (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
349
+ r2->type |= ARM_CP_ALIAS;
350
+ }
351
+ } else if ((secstate != r->secure) && !ns) {
352
+ /*
353
+ * The register is not banked so we only want to allow
354
+ * migration of the non-secure instance.
355
+ */
356
r2->type |= ARM_CP_ALIAS;
357
}
358
- } else if ((secstate != r->secure) && !ns) {
359
- /*
360
- * The register is not banked so we only want to allow migration
361
- * of the non-secure instance.
362
- */
363
- r2->type |= ARM_CP_ALIAS;
364
- }
365
366
- if (HOST_BIG_ENDIAN &&
367
- r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
368
- r2->fieldoffset += sizeof(uint32_t);
369
+ if (HOST_BIG_ENDIAN &&
370
+ r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
371
+ r2->fieldoffset += sizeof(uint32_t);
372
+ }
373
}
374
}
375
376
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
377
* multiple times. Special registers (ie NOP/WFI) are
378
* never migratable and not even raw-accessible.
379
*/
380
- if (r->type & ARM_CP_SPECIAL_MASK) {
381
+ if (r2->type & ARM_CP_SPECIAL_MASK) {
382
r2->type |= ARM_CP_NO_RAW;
383
}
384
if (((r->crm == CP_ANY) && crm != 0) ||
385
--
72
--
386
2.25.1
73
2.25.1
diff view generated by jsdifflib
[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
[PULL 093/117] target/arm: Use TRANS_FEAT for do_reduce
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
during arm_cpu_realizefn.
4
Message-id: 20220527181907.189259-91-richard.henderson@linaro.org
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
target/arm/cpu.c | 22 +++++++++++++---------
8
target/arm/translate-sve.c | 14 ++++++--------
12
1 file changed, 13 insertions(+), 9 deletions(-)
9
1 file changed, 6 insertions(+), 8 deletions(-)
13
10
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
13
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/cpu.c
14
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
15
@@ -XXX,XX +XXX,XX @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
19
*/
16
}
20
unset_feature(env, ARM_FEATURE_EL3);
17
21
18
#define DO_VPZ(NAME, name) \
22
- /* Disable the security extension feature bits in the processor feature
19
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
23
- * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
20
-{ \
24
+ /*
21
- static gen_helper_fp_reduce * const fns[4] = { \
25
+ * Disable the security extension feature bits in the processor
22
- NULL, gen_helper_sve_##name##_h, \
26
+ * feature registers as well.
23
- gen_helper_sve_##name##_s, \
27
*/
24
- gen_helper_sve_##name##_d, \
28
- cpu->isar.id_pfr1 &= ~0xf0;
25
+ static gen_helper_fp_reduce * const name##_fns[4] = { \
29
- cpu->isar.id_aa64pfr0 &= ~0xf000;
26
+ NULL, gen_helper_sve_##name##_h, \
30
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
27
+ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
31
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
28
}; \
32
+ ID_AA64PFR0, EL3, 0);
29
- return do_reduce(s, a, fns[a->esz]); \
33
}
30
-}
34
31
+ TRANS_FEAT(NAME, aa64_sve, do_reduce, a, name##_fns[a->esz])
35
if (!cpu->has_el2) {
32
36
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
33
DO_VPZ(FADDV, faddv)
37
}
34
DO_VPZ(FMINNMV, fminnmv)
38
35
@@ -XXX,XX +XXX,XX @@ DO_VPZ(FMAXNMV, fmaxnmv)
39
if (!arm_feature(env, ARM_FEATURE_EL2)) {
36
DO_VPZ(FMINV, fminv)
40
- /* Disable the hypervisor feature bits in the processor feature
37
DO_VPZ(FMAXV, fmaxv)
41
- * registers if we don't have EL2. These are id_pfr1[15:12] and
38
42
- * id_aa64pfr0_el1[11:8].
39
+#undef DO_VPZ
43
+ /*
40
+
44
+ * Disable the hypervisor feature bits in the processor feature
41
/*
45
+ * registers if we don't have EL2.
42
*** SVE Floating Point Unary Operations - Unpredicated Group
46
*/
43
*/
47
- cpu->isar.id_aa64pfr0 &= ~0xf00;
48
- cpu->isar.id_pfr1 &= ~0xf000;
49
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
50
+ ID_AA64PFR0, EL2, 0);
51
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
52
+ ID_PFR1, VIRTUALIZATION, 0);
53
}
54
55
#ifndef CONFIG_USER_ONLY
56
--
44
--
57
2.25.1
45
2.25.1
diff view generated by jsdifflib
[PULL 17/32] target/arm: Implement ESB instruction
[PULL 094/117] target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Check for and defer any pending virtual SError.
3
Rename do_zz_fp to gen_gvec_fpst_arg_zz, and move up.
4
Split out gen_gvec_fpst_zz as a helper while we're at it.
4
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-92-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/helper.h | 1 +
11
target/arm/translate-sve.c | 77 ++++++++++++++++++--------------------
11
target/arm/a32.decode | 16 ++++++++------
12
1 file changed, 36 insertions(+), 41 deletions(-)
12
target/arm/t32.decode | 18 ++++++++--------
13
target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-a64.c | 17 +++++++++++++++
15
target/arm/translate.c | 23 ++++++++++++++++++++
16
6 files changed, 103 insertions(+), 15 deletions(-)
17
13
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
16
--- a/target/arm/translate-sve.c
21
+++ b/target/arm/helper.h
17
+++ b/target/arm/translate-sve.c
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
23
DEF_HELPER_1(yield, void, env)
24
DEF_HELPER_1(pre_hvc, void, env)
25
DEF_HELPER_2(pre_smc, void, env, i32)
26
+DEF_HELPER_1(vesb, void, env)
27
28
DEF_HELPER_3(cpsr_write, void, env, i32, i32)
29
DEF_HELPER_2(cpsr_write_eret, void, env, i32)
30
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/a32.decode
33
+++ b/target/arm/a32.decode
34
@@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
35
36
{
37
{
38
- YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
39
- WFE ---- 0011 0010 0000 1111 ---- 0000 0010
40
- WFI ---- 0011 0010 0000 1111 ---- 0000 0011
41
+ [
42
+ YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
43
+ WFE ---- 0011 0010 0000 1111 ---- 0000 0010
44
+ WFI ---- 0011 0010 0000 1111 ---- 0000 0011
45
46
- # TODO: Implement SEV, SEVL; may help SMP performance.
47
- # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
48
- # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
49
+ # TODO: Implement SEV, SEVL; may help SMP performance.
50
+ # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
51
+ # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
52
+
53
+ ESB ---- 0011 0010 0000 1111 ---- 0001 0000
54
+ ]
55
56
# The canonical nop ends in 00000000, but the whole of the
57
# rest of the space executes as nop if otherwise unsupported.
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
63
[
64
# Hints, and CPS
65
{
66
- YIELD 1111 0011 1010 1111 1000 0000 0000 0001
67
- WFE 1111 0011 1010 1111 1000 0000 0000 0010
68
- WFI 1111 0011 1010 1111 1000 0000 0000 0011
69
+ [
70
+ YIELD 1111 0011 1010 1111 1000 0000 0000 0001
71
+ WFE 1111 0011 1010 1111 1000 0000 0000 0010
72
+ WFI 1111 0011 1010 1111 1000 0000 0000 0011
73
74
- # TODO: Implement SEV, SEVL; may help SMP performance.
75
- # SEV 1111 0011 1010 1111 1000 0000 0000 0100
76
- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
77
+ # TODO: Implement SEV, SEVL; may help SMP performance.
78
+ # SEV 1111 0011 1010 1111 1000 0000 0000 0100
79
+ # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
80
81
- # For M-profile minimal-RAS ESB can be a NOP, which is the
82
- # default behaviour since it is in the hint space.
83
- # ESB 1111 0011 1010 1111 1000 0000 0001 0000
84
+ ESB 1111 0011 1010 1111 1000 0000 0001 0000
85
+ ]
86
87
# The canonical nop ends in 0000 0000, but the whole rest
88
# of the space is "reserved hint, behaves as nop".
89
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/op_helper.c
92
+++ b/target/arm/op_helper.c
93
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
94
access_type, mmu_idx, ra);
95
}
96
}
97
+
98
+/*
99
+ * This function corresponds to AArch64.vESBOperation().
100
+ * Note that the AArch32 version is not functionally different.
101
+ */
102
+void HELPER(vesb)(CPUARMState *env)
103
+{
104
+ /*
105
+ * The EL2Enabled() check is done inside arm_hcr_el2_eff,
106
+ * and will return HCR_EL2.VSE == 0, so nothing happens.
107
+ */
108
+ uint64_t hcr = arm_hcr_el2_eff(env);
109
+ bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
110
+ bool pending = enabled && (hcr & HCR_VSE);
111
+ bool masked = (env->daif & PSTATE_A);
112
+
113
+ /* If VSE pending and masked, defer the exception. */
114
+ if (pending && masked) {
115
+ uint32_t syndrome;
116
+
117
+ if (arm_el_is_aa64(env, 1)) {
118
+ /* Copy across IDS and ISS from VSESR. */
119
+ syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
120
+ } else {
121
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
122
+
123
+ if (extended_addresses_enabled(env)) {
124
+ syndrome = arm_fi_to_lfsc(&fi);
125
+ } else {
126
+ syndrome = arm_fi_to_sfsc(&fi);
127
+ }
128
+ /* Copy across AET and ExT from VSESR. */
129
+ syndrome |= env->cp15.vsesr_el2 & 0xd000;
130
+ }
131
+
132
+ /* Set VDISR_EL2.A along with the syndrome. */
133
+ env->cp15.vdisr_el2 = syndrome | (1u << 31);
134
+
135
+ /* Clear pending virtual SError */
136
+ env->cp15.hcr_el2 &= ~HCR_VSE;
137
+ cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
138
+ }
139
+}
140
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
141
index XXXXXXX..XXXXXXX 100644
142
--- a/target/arm/translate-a64.c
143
+++ b/target/arm/translate-a64.c
144
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
145
gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
146
}
147
break;
148
+ case 0b10000: /* ESB */
149
+ /* Without RAS, we must implement this as NOP. */
150
+ if (dc_isar_feature(aa64_ras, s)) {
151
+ /*
152
+ * QEMU does not have a source of physical SErrors,
153
+ * so we are only concerned with virtual SErrors.
154
+ * The pseudocode in the ARM for this case is
155
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
156
+ * AArch64.vESBOperation();
157
+ * Most of the condition can be evaluated at translation time.
158
+ * Test for EL2 present, and defer test for SEL2 to runtime.
159
+ */
160
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
161
+ gen_helper_vesb(cpu_env);
162
+ }
163
+ }
164
+ break;
165
case 0b11000: /* PACIAZ */
166
if (s->pauth_active) {
167
gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
168
diff --git a/target/arm/translate.c b/target/arm/translate.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/arm/translate.c
171
+++ b/target/arm/translate.c
172
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
173
return true;
19
return true;
174
}
20
}
175
21
176
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
22
+static bool gen_gvec_fpst_zz(DisasContext *s, gen_helper_gvec_2_ptr *fn,
23
+ int rd, int rn, int data,
24
+ ARMFPStatusFlavour flavour)
177
+{
25
+{
178
+ /*
26
+ if (fn == NULL) {
179
+ * For M-profile, minimal-RAS ESB can be a NOP.
27
+ return false;
180
+ * Without RAS, we must implement this as NOP.
28
+ }
181
+ */
29
+ if (sve_access_check(s)) {
182
+ if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
30
+ unsigned vsz = vec_full_reg_size(s);
183
+ /*
31
+ TCGv_ptr status = fpstatus_ptr(flavour);
184
+ * QEMU does not have a source of physical SErrors,
32
+
185
+ * so we are only concerned with virtual SErrors.
33
+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
186
+ * The pseudocode in the ARM for this case is
34
+ vec_full_reg_offset(s, rn),
187
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
35
+ status, vsz, vsz, data, fn);
188
+ * AArch32.vESBOperation();
36
+ tcg_temp_free_ptr(status);
189
+ * Most of the condition can be evaluated at translation time.
190
+ * Test for EL2 present, and defer test for SEL2 to runtime.
191
+ */
192
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
193
+ gen_helper_vesb(cpu_env);
194
+ }
195
+ }
37
+ }
196
+ return true;
38
+ return true;
197
+}
39
+}
198
+
40
+
199
static bool trans_NOP(DisasContext *s, arg_NOP *a)
41
+static bool gen_gvec_fpst_arg_zz(DisasContext *s, gen_helper_gvec_2_ptr *fn,
200
{
42
+ arg_rr_esz *a, int data)
201
return true;
43
+{
44
+ return gen_gvec_fpst_zz(s, fn, a->rd, a->rn, data,
45
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
46
+}
47
+
48
/* Invoke an out-of-line helper on 3 Zregs. */
49
static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
50
int rd, int rn, int rm, int data)
51
@@ -XXX,XX +XXX,XX @@ DO_VPZ(FMAXV, fmaxv)
52
*** SVE Floating Point Unary Operations - Unpredicated Group
53
*/
54
55
-static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)
56
-{
57
- unsigned vsz = vec_full_reg_size(s);
58
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
59
+static gen_helper_gvec_2_ptr * const frecpe_fns[] = {
60
+ NULL, gen_helper_gvec_frecpe_h,
61
+ gen_helper_gvec_frecpe_s, gen_helper_gvec_frecpe_d,
62
+};
63
+TRANS_FEAT(FRECPE, aa64_sve, gen_gvec_fpst_arg_zz, frecpe_fns[a->esz], a, 0)
64
65
- tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),
66
- vec_full_reg_offset(s, a->rn),
67
- status, vsz, vsz, 0, fn);
68
- tcg_temp_free_ptr(status);
69
-}
70
-
71
-static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a)
72
-{
73
- static gen_helper_gvec_2_ptr * const fns[3] = {
74
- gen_helper_gvec_frecpe_h,
75
- gen_helper_gvec_frecpe_s,
76
- gen_helper_gvec_frecpe_d,
77
- };
78
- if (a->esz == 0) {
79
- return false;
80
- }
81
- if (sve_access_check(s)) {
82
- do_zz_fp(s, a, fns[a->esz - 1]);
83
- }
84
- return true;
85
-}
86
-
87
-static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a)
88
-{
89
- static gen_helper_gvec_2_ptr * const fns[3] = {
90
- gen_helper_gvec_frsqrte_h,
91
- gen_helper_gvec_frsqrte_s,
92
- gen_helper_gvec_frsqrte_d,
93
- };
94
- if (a->esz == 0) {
95
- return false;
96
- }
97
- if (sve_access_check(s)) {
98
- do_zz_fp(s, a, fns[a->esz - 1]);
99
- }
100
- return true;
101
-}
102
+static gen_helper_gvec_2_ptr * const frsqrte_fns[] = {
103
+ NULL, gen_helper_gvec_frsqrte_h,
104
+ gen_helper_gvec_frsqrte_s, gen_helper_gvec_frsqrte_d,
105
+};
106
+TRANS_FEAT(FRSQRTE, aa64_sve, gen_gvec_fpst_arg_zz, frsqrte_fns[a->esz], a, 0)
107
108
/*
109
*** SVE Floating Point Compare with Zero Group
202
--
110
--
203
2.25.1
111
2.25.1
diff view generated by jsdifflib
[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
[PULL 095/117] target/arm: Expand frint_fns for MO_8
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Update the legacy feature names to the current names.
3
Simplify indexing of this array. This will allow folding
4
Provide feature names for id changes that were not marked.
4
of the illegal esz == 0 into the normal fn == NULL check.
5
Sort the field updates into increasing bitfield order.
6
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-93-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/cpu64.c | 100 +++++++++++++++++++++----------------------
11
target/arm/translate-sve.c | 15 ++++++++-------
13
target/arm/cpu_tcg.c | 48 ++++++++++-----------
12
1 file changed, 8 insertions(+), 7 deletions(-)
14
2 files changed, 74 insertions(+), 74 deletions(-)
15
13
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu64.c
16
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/cpu64.c
17
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
18
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a)
21
cpu->midr = t;
19
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd);
22
23
t = cpu->isar.id_aa64isar0;
24
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
25
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
26
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
27
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
28
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
29
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
30
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
31
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
32
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
33
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
34
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
35
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
36
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
37
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
38
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
39
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
40
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
41
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
42
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
43
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
44
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
45
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
46
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
47
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
48
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
49
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
50
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
51
cpu->isar.id_aa64isar0 = t;
52
53
t = cpu->isar.id_aa64isar1;
54
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
55
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
56
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
57
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
58
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
59
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
60
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
61
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
62
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
63
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
64
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
65
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
66
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
67
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
68
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
69
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
70
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
71
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
72
cpu->isar.id_aa64isar1 = t;
73
74
t = cpu->isar.id_aa64pfr0;
75
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
76
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
77
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
78
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
79
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
80
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
81
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
82
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
83
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
84
cpu->isar.id_aa64pfr0 = t;
85
86
t = cpu->isar.id_aa64pfr1;
87
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
88
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
89
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
90
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
91
/*
92
* Begin with full support for MTE. This will be downgraded to MTE=0
93
* during realize if the board provides no tag memory, much like
94
* we do for EL2 with the virtualization=on property.
95
*/
96
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
97
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
98
cpu->isar.id_aa64pfr1 = t;
99
100
t = cpu->isar.id_aa64mmfr0;
101
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
102
cpu->isar.id_aa64mmfr0 = t;
103
104
t = cpu->isar.id_aa64mmfr1;
105
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
106
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
107
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
108
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
109
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
110
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
111
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
112
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
113
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
114
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
115
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
116
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
117
cpu->isar.id_aa64mmfr1 = t;
118
119
t = cpu->isar.id_aa64mmfr2;
120
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
121
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
122
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
123
- t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
124
- t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
125
- t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
126
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
127
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
128
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
129
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
130
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
131
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
132
cpu->isar.id_aa64mmfr2 = t;
133
134
t = cpu->isar.id_aa64zfr0;
135
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
136
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
137
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
138
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
139
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
140
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
141
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
142
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
143
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
144
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
145
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
146
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
147
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
148
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
149
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
150
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
151
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
152
cpu->isar.id_aa64zfr0 = t;
153
154
t = cpu->isar.id_aa64dfr0;
155
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
156
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
157
cpu->isar.id_aa64dfr0 = t;
158
159
/* Replicate the same data to the 32-bit id registers. */
160
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/arm/cpu_tcg.c
163
+++ b/target/arm/cpu_tcg.c
164
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
165
166
/* Add additional features supported by QEMU */
167
t = cpu->isar.id_isar5;
168
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
169
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
170
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
171
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
172
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
173
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
174
t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
175
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
176
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
177
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
178
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
179
cpu->isar.id_isar5 = t;
180
181
t = cpu->isar.id_isar6;
182
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
183
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
184
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
185
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
186
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
187
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
188
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
189
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
190
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
191
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
192
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
193
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
194
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
195
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
196
cpu->isar.id_isar6 = t;
197
198
t = cpu->isar.mvfr1;
199
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
200
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
201
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
202
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
203
cpu->isar.mvfr1 = t;
204
205
t = cpu->isar.mvfr2;
206
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
207
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
208
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
cpu->isar.mvfr2 = t;
211
212
t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
215
cpu->isar.id_mmfr3 = t;
216
217
t = cpu->isar.id_mmfr4;
218
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
219
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
220
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
221
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
222
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
223
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
224
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
225
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/
226
cpu->isar.id_mmfr4 = t;
227
228
t = cpu->isar.id_pfr0;
229
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
230
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
231
cpu->isar.id_pfr0 = t;
232
233
t = cpu->isar.id_pfr2;
234
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
235
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
236
cpu->isar.id_pfr2 = t;
237
238
t = cpu->isar.id_dfr0;
239
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
240
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
241
cpu->isar.id_dfr0 = t;
242
}
20
}
243
21
22
-static gen_helper_gvec_3_ptr * const frint_fns[3] = {
23
+static gen_helper_gvec_3_ptr * const frint_fns[] = {
24
+ NULL,
25
gen_helper_sve_frint_h,
26
gen_helper_sve_frint_s,
27
gen_helper_sve_frint_d
28
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)
29
return false;
30
}
31
return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,
32
- frint_fns[a->esz - 1]);
33
+ frint_fns[a->esz]);
34
}
35
36
static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)
37
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
38
if (a->esz == 0) {
39
return false;
40
}
41
- return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz - 1]);
42
+ return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
43
}
44
45
static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
46
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
47
if (a->esz == 0) {
48
return false;
49
}
50
- return do_frint_mode(s, a, float_round_up, frint_fns[a->esz - 1]);
51
+ return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
52
}
53
54
static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
55
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
56
if (a->esz == 0) {
57
return false;
58
}
59
- return do_frint_mode(s, a, float_round_down, frint_fns[a->esz - 1]);
60
+ return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
61
}
62
63
static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
64
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
65
if (a->esz == 0) {
66
return false;
67
}
68
- return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz - 1]);
69
+ return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
70
}
71
72
static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
73
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
74
if (a->esz == 0) {
75
return false;
76
}
77
- return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz - 1]);
78
+ return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
79
}
80
81
static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)
244
--
82
--
245
2.25.1
83
2.25.1
diff view generated by jsdifflib
[PULL 09/32] target/arm: Split out aa32_max_features
[PULL 096/117] target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Share the code to set AArch32 max features so that we no
3
Rename the function to match other expansion function and
4
longer have code drift between qemu{-system,}-{arm,aarch64}.
4
move to be adjacent. Split out gen_gvec_fpst_zzp as a
5
helper while we're at it.
5
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-94-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/internals.h | 2 +
12
target/arm/translate-sve.c | 392 ++++++++++++-------------------------
12
target/arm/cpu64.c | 50 +-----------------
13
1 file changed, 129 insertions(+), 263 deletions(-)
13
target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++-------------------
14
3 files changed, 65 insertions(+), 101 deletions(-)
15
14
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
17
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/internals.h
18
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
21
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
20
return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
22
#endif
21
}
23
22
24
+void aa32_max_features(ARMCPU *cpu);
23
+static bool gen_gvec_fpst_zzp(DisasContext *s, gen_helper_gvec_3_ptr *fn,
24
+ int rd, int rn, int pg, int data,
25
+ ARMFPStatusFlavour flavour)
26
+{
27
+ if (fn == NULL) {
28
+ return false;
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ TCGv_ptr status = fpstatus_ptr(flavour);
25
+
33
+
26
#endif
34
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
35
+ vec_full_reg_offset(s, rn),
28
index XXXXXXX..XXXXXXX 100644
36
+ pred_full_reg_offset(s, pg),
29
--- a/target/arm/cpu64.c
37
+ status, vsz, vsz, data, fn);
30
+++ b/target/arm/cpu64.c
38
+ tcg_temp_free_ptr(status);
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
39
+ }
32
{
40
+ return true;
33
ARMCPU *cpu = ARM_CPU(obj);
34
uint64_t t;
35
- uint32_t u;
36
37
if (kvm_enabled() || hvf_enabled()) {
38
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
40
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
41
cpu->isar.id_aa64zfr0 = t;
42
43
- /* Replicate the same data to the 32-bit id registers. */
44
- u = cpu->isar.id_isar5;
45
- u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
46
- u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
47
- u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
48
- u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
49
- u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
50
- u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
51
- cpu->isar.id_isar5 = u;
52
-
53
- u = cpu->isar.id_isar6;
54
- u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
55
- u = FIELD_DP32(u, ID_ISAR6, DP, 1);
56
- u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
57
- u = FIELD_DP32(u, ID_ISAR6, SB, 1);
58
- u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
59
- u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
60
- u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
61
- cpu->isar.id_isar6 = u;
62
-
63
- u = cpu->isar.id_pfr0;
64
- u = FIELD_DP32(u, ID_PFR0, DIT, 1);
65
- cpu->isar.id_pfr0 = u;
66
-
67
- u = cpu->isar.id_pfr2;
68
- u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
69
- cpu->isar.id_pfr2 = u;
70
-
71
- u = cpu->isar.id_mmfr3;
72
- u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
73
- cpu->isar.id_mmfr3 = u;
74
-
75
- u = cpu->isar.id_mmfr4;
76
- u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
77
- u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
78
- u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
79
- u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
80
- cpu->isar.id_mmfr4 = u;
81
-
82
t = cpu->isar.id_aa64dfr0;
83
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
84
cpu->isar.id_aa64dfr0 = t;
85
86
- u = cpu->isar.id_dfr0;
87
- u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
88
- cpu->isar.id_dfr0 = u;
89
-
90
- u = cpu->isar.mvfr1;
91
- u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
92
- u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
93
- cpu->isar.mvfr1 = u;
94
+ /* Replicate the same data to the 32-bit id registers. */
95
+ aa32_max_features(cpu);
96
97
#ifdef CONFIG_USER_ONLY
98
/*
99
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/cpu_tcg.c
102
+++ b/target/arm/cpu_tcg.c
103
@@ -XXX,XX +XXX,XX @@
104
#endif
105
#include "cpregs.h"
106
107
+
108
+/* Share AArch32 -cpu max features with AArch64. */
109
+void aa32_max_features(ARMCPU *cpu)
110
+{
111
+ uint32_t t;
112
+
113
+ /* Add additional features supported by QEMU */
114
+ t = cpu->isar.id_isar5;
115
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
116
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
117
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
118
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
119
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
120
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
121
+ cpu->isar.id_isar5 = t;
122
+
123
+ t = cpu->isar.id_isar6;
124
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
125
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
126
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
127
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
128
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
129
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
130
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
131
+ cpu->isar.id_isar6 = t;
132
+
133
+ t = cpu->isar.mvfr1;
134
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
135
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
136
+ cpu->isar.mvfr1 = t;
137
+
138
+ t = cpu->isar.mvfr2;
139
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
140
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
141
+ cpu->isar.mvfr2 = t;
142
+
143
+ t = cpu->isar.id_mmfr3;
144
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
145
+ cpu->isar.id_mmfr3 = t;
146
+
147
+ t = cpu->isar.id_mmfr4;
148
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
149
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
150
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
151
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
152
+ cpu->isar.id_mmfr4 = t;
153
+
154
+ t = cpu->isar.id_pfr0;
155
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
156
+ cpu->isar.id_pfr0 = t;
157
+
158
+ t = cpu->isar.id_pfr2;
159
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
160
+ cpu->isar.id_pfr2 = t;
161
+
162
+ t = cpu->isar.id_dfr0;
163
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
164
+ cpu->isar.id_dfr0 = t;
165
+}
41
+}
166
+
42
+
167
#ifndef CONFIG_USER_ONLY
43
+static bool gen_gvec_fpst_arg_zpz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
168
static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
44
+ arg_rpr_esz *a, int data,
45
+ ARMFPStatusFlavour flavour)
46
+{
47
+ return gen_gvec_fpst_zzp(s, fn, a->rd, a->rn, a->pg, data, flavour);
48
+}
49
+
50
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
51
static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
52
int rd, int rn, int rm, int pg, int data)
53
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
54
*** SVE Floating Point Unary Operations Predicated Group
55
*/
56
57
-static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
58
- bool is_fp16, gen_helper_gvec_3_ptr *fn)
59
-{
60
- if (sve_access_check(s)) {
61
- unsigned vsz = vec_full_reg_size(s);
62
- TCGv_ptr status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
63
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
64
- vec_full_reg_offset(s, rn),
65
- pred_full_reg_offset(s, pg),
66
- status, vsz, vsz, 0, fn);
67
- tcg_temp_free_ptr(status);
68
- }
69
- return true;
70
-}
71
+TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
72
+ gen_helper_sve_fcvt_sh, a, 0, FPST_FPCR)
73
+TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
74
+ gen_helper_sve_fcvt_hs, a, 0, FPST_FPCR)
75
76
-static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a)
77
-{
78
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
79
-}
80
+TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
81
+ gen_helper_sve_bfcvt, a, 0, FPST_FPCR)
82
83
-static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a)
84
-{
85
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hs);
86
-}
87
+TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
88
+ gen_helper_sve_fcvt_dh, a, 0, FPST_FPCR)
89
+TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
90
+ gen_helper_sve_fcvt_hd, a, 0, FPST_FPCR)
91
+TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
92
+ gen_helper_sve_fcvt_ds, a, 0, FPST_FPCR)
93
+TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
94
+ gen_helper_sve_fcvt_sd, a, 0, FPST_FPCR)
95
96
-static bool trans_BFCVT(DisasContext *s, arg_rpr_esz *a)
97
-{
98
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
99
- return false;
100
- }
101
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvt);
102
-}
103
+TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
104
+ gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16)
105
+TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
106
+ gen_helper_sve_fcvtzu_hh, a, 0, FPST_FPCR_F16)
107
+TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
108
+ gen_helper_sve_fcvtzs_hs, a, 0, FPST_FPCR_F16)
109
+TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
110
+ gen_helper_sve_fcvtzu_hs, a, 0, FPST_FPCR_F16)
111
+TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
112
+ gen_helper_sve_fcvtzs_hd, a, 0, FPST_FPCR_F16)
113
+TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
114
+ gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16)
115
116
-static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a)
117
-{
118
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
119
-}
120
+TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
121
+ gen_helper_sve_fcvtzs_ss, a, 0, FPST_FPCR)
122
+TRANS_FEAT(FCVTZU_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
123
+ gen_helper_sve_fcvtzu_ss, a, 0, FPST_FPCR)
124
+TRANS_FEAT(FCVTZS_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
125
+ gen_helper_sve_fcvtzs_sd, a, 0, FPST_FPCR)
126
+TRANS_FEAT(FCVTZU_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
127
+ gen_helper_sve_fcvtzu_sd, a, 0, FPST_FPCR)
128
+TRANS_FEAT(FCVTZS_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
129
+ gen_helper_sve_fcvtzs_ds, a, 0, FPST_FPCR)
130
+TRANS_FEAT(FCVTZU_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
131
+ gen_helper_sve_fcvtzu_ds, a, 0, FPST_FPCR)
132
133
-static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a)
134
-{
135
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hd);
136
-}
137
-
138
-static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a)
139
-{
140
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_ds);
141
-}
142
-
143
-static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a)
144
-{
145
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sd);
146
-}
147
-
148
-static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a)
149
-{
150
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hh);
151
-}
152
-
153
-static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a)
154
-{
155
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hh);
156
-}
157
-
158
-static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a)
159
-{
160
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hs);
161
-}
162
-
163
-static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a)
164
-{
165
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hs);
166
-}
167
-
168
-static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a)
169
-{
170
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hd);
171
-}
172
-
173
-static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a)
174
-{
175
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hd);
176
-}
177
-
178
-static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a)
179
-{
180
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ss);
181
-}
182
-
183
-static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a)
184
-{
185
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ss);
186
-}
187
-
188
-static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a)
189
-{
190
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_sd);
191
-}
192
-
193
-static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a)
194
-{
195
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_sd);
196
-}
197
-
198
-static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a)
199
-{
200
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ds);
201
-}
202
-
203
-static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a)
204
-{
205
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ds);
206
-}
207
-
208
-static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a)
209
-{
210
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_dd);
211
-}
212
-
213
-static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a)
214
-{
215
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd);
216
-}
217
+TRANS_FEAT(FCVTZS_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
218
+ gen_helper_sve_fcvtzs_dd, a, 0, FPST_FPCR)
219
+TRANS_FEAT(FCVTZU_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
220
+ gen_helper_sve_fcvtzu_dd, a, 0, FPST_FPCR)
221
222
static gen_helper_gvec_3_ptr * const frint_fns[] = {
223
NULL,
224
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3_ptr * const frint_fns[] = {
225
gen_helper_sve_frint_s,
226
gen_helper_sve_frint_d
227
};
228
+TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz],
229
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
230
231
-static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)
232
-{
233
- if (a->esz == 0) {
234
- return false;
235
- }
236
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,
237
- frint_fns[a->esz]);
238
-}
239
-
240
-static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)
241
-{
242
- static gen_helper_gvec_3_ptr * const fns[3] = {
243
- gen_helper_sve_frintx_h,
244
- gen_helper_sve_frintx_s,
245
- gen_helper_sve_frintx_d
246
- };
247
- if (a->esz == 0) {
248
- return false;
249
- }
250
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
251
-}
252
+static gen_helper_gvec_3_ptr * const frintx_fns[] = {
253
+ NULL,
254
+ gen_helper_sve_frintx_h,
255
+ gen_helper_sve_frintx_s,
256
+ gen_helper_sve_frintx_d
257
+};
258
+TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
259
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
260
261
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
262
int mode, gen_helper_gvec_3_ptr *fn)
263
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
264
return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
265
}
266
267
-static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)
268
-{
269
- static gen_helper_gvec_3_ptr * const fns[3] = {
270
- gen_helper_sve_frecpx_h,
271
- gen_helper_sve_frecpx_s,
272
- gen_helper_sve_frecpx_d
273
- };
274
- if (a->esz == 0) {
275
- return false;
276
- }
277
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
278
-}
279
+static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
280
+ NULL, gen_helper_sve_frecpx_h,
281
+ gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d,
282
+};
283
+TRANS_FEAT(FRECPX, aa64_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz],
284
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
285
286
-static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a)
287
-{
288
- static gen_helper_gvec_3_ptr * const fns[3] = {
289
- gen_helper_sve_fsqrt_h,
290
- gen_helper_sve_fsqrt_s,
291
- gen_helper_sve_fsqrt_d
292
- };
293
- if (a->esz == 0) {
294
- return false;
295
- }
296
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
297
-}
298
+static gen_helper_gvec_3_ptr * const fsqrt_fns[] = {
299
+ NULL, gen_helper_sve_fsqrt_h,
300
+ gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d,
301
+};
302
+TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz],
303
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
304
305
-static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a)
306
-{
307
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh);
308
-}
309
+TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
310
+ gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16)
311
+TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
312
+ gen_helper_sve_scvt_sh, a, 0, FPST_FPCR_F16)
313
+TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
314
+ gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16)
315
316
-static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a)
317
-{
318
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh);
319
-}
320
+TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
321
+ gen_helper_sve_scvt_ss, a, 0, FPST_FPCR)
322
+TRANS_FEAT(SCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
323
+ gen_helper_sve_scvt_ds, a, 0, FPST_FPCR)
324
325
-static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a)
326
-{
327
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh);
328
-}
329
+TRANS_FEAT(SCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
330
+ gen_helper_sve_scvt_sd, a, 0, FPST_FPCR)
331
+TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
332
+ gen_helper_sve_scvt_dd, a, 0, FPST_FPCR)
333
334
-static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a)
335
-{
336
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss);
337
-}
338
+TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
339
+ gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16)
340
+TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
341
+ gen_helper_sve_ucvt_sh, a, 0, FPST_FPCR_F16)
342
+TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
343
+ gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16)
344
345
-static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a)
346
-{
347
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds);
348
-}
349
+TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
350
+ gen_helper_sve_ucvt_ss, a, 0, FPST_FPCR)
351
+TRANS_FEAT(UCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
352
+ gen_helper_sve_ucvt_ds, a, 0, FPST_FPCR)
353
+TRANS_FEAT(UCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
354
+ gen_helper_sve_ucvt_sd, a, 0, FPST_FPCR)
355
356
-static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a)
357
-{
358
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd);
359
-}
360
-
361
-static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a)
362
-{
363
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd);
364
-}
365
-
366
-static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a)
367
-{
368
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh);
369
-}
370
-
371
-static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a)
372
-{
373
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh);
374
-}
375
-
376
-static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a)
377
-{
378
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh);
379
-}
380
-
381
-static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a)
382
-{
383
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss);
384
-}
385
-
386
-static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a)
387
-{
388
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds);
389
-}
390
-
391
-static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a)
392
-{
393
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd);
394
-}
395
-
396
-static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a)
397
-{
398
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd);
399
-}
400
+TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
401
+ gen_helper_sve_ucvt_dd, a, 0, FPST_FPCR)
402
403
/*
404
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
405
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
406
407
TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
408
409
-static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
410
-{
411
- if (!dc_isar_feature(aa64_sve2, s)) {
412
- return false;
413
- }
414
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_sh);
415
-}
416
+TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz,
417
+ gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR)
418
+TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz,
419
+ gen_helper_sve2_fcvtnt_ds, a, 0, FPST_FPCR)
420
421
-static bool trans_BFCVTNT(DisasContext *s, arg_rpr_esz *a)
422
-{
423
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
424
- return false;
425
- }
426
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvtnt);
427
-}
428
+TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
429
+ gen_helper_sve_bfcvtnt, a, 0, FPST_FPCR)
430
431
-static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a)
432
-{
433
- if (!dc_isar_feature(aa64_sve2, s)) {
434
- return false;
435
- }
436
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_ds);
437
-}
438
-
439
-static bool trans_FCVTLT_hs(DisasContext *s, arg_rpr_esz *a)
440
-{
441
- if (!dc_isar_feature(aa64_sve2, s)) {
442
- return false;
443
- }
444
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_hs);
445
-}
446
-
447
-static bool trans_FCVTLT_sd(DisasContext *s, arg_rpr_esz *a)
448
-{
449
- if (!dc_isar_feature(aa64_sve2, s)) {
450
- return false;
451
- }
452
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_sd);
453
-}
454
+TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
455
+ gen_helper_sve2_fcvtlt_hs, a, 0, FPST_FPCR)
456
+TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
457
+ gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
458
459
static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a)
169
{
460
{
170
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
171
static void arm_max_initfn(Object *obj)
172
{
173
ARMCPU *cpu = ARM_CPU(obj);
174
- uint32_t t;
175
176
/* aarch64_a57_initfn, advertising none of the aarch64 features */
177
cpu->dtb_compatible = "arm,cortex-a57";
178
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
179
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
180
define_cortex_a72_a57_a53_cp_reginfo(cpu);
181
182
- /* Add additional features supported by QEMU */
183
- t = cpu->isar.id_isar5;
184
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
185
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
186
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
187
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
188
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
189
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
190
- cpu->isar.id_isar5 = t;
191
-
192
- t = cpu->isar.id_isar6;
193
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
194
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
195
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
196
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
197
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
198
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
199
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
200
- cpu->isar.id_isar6 = t;
201
-
202
- t = cpu->isar.mvfr1;
203
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
204
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
205
- cpu->isar.mvfr1 = t;
206
-
207
- t = cpu->isar.mvfr2;
208
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
- cpu->isar.mvfr2 = t;
211
-
212
- t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
- cpu->isar.id_mmfr3 = t;
215
-
216
- t = cpu->isar.id_mmfr4;
217
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
218
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
219
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
220
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
221
- cpu->isar.id_mmfr4 = t;
222
-
223
- t = cpu->isar.id_pfr0;
224
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
225
- cpu->isar.id_pfr0 = t;
226
-
227
- t = cpu->isar.id_pfr2;
228
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
229
- cpu->isar.id_pfr2 = t;
230
-
231
- t = cpu->isar.id_dfr0;
232
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
233
- cpu->isar.id_dfr0 = t;
234
+ aa32_max_features(cpu);
235
236
#ifdef CONFIG_USER_ONLY
237
/*
238
--
461
--
239
2.25.1
462
2.25.1
diff view generated by jsdifflib
[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
[PULL 097/117] target/arm: Move null function and sve check into do_frint_mode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Previously we were defining some of these in user-only mode,
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
but none of them are accessible from user-only, therefore
4
Message-id: 20220527181907.189259-95-richard.henderson@linaro.org
5
define them only in system mode.
6
7
This will shortly be used from cpu_tcg.c also.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
7
---
14
target/arm/internals.h | 6 ++++
8
target/arm/translate-sve.c | 52 +++++++++++++++++---------------------
15
target/arm/cpu64.c | 64 +++---------------------------------------
9
1 file changed, 23 insertions(+), 29 deletions(-)
16
target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++
17
3 files changed, 69 insertions(+), 60 deletions(-)
18
10
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
13
--- a/target/arm/translate-sve.c
22
+++ b/target/arm/internals.h
14
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
24
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
16
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
25
#endif
17
int mode, gen_helper_gvec_3_ptr *fn)
26
18
{
27
+#ifdef CONFIG_USER_ONLY
19
- if (sve_access_check(s)) {
28
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
20
- unsigned vsz = vec_full_reg_size(s);
29
+#else
21
- TCGv_i32 tmode = tcg_const_i32(mode);
30
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
22
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
31
+#endif
23
+ unsigned vsz;
24
+ TCGv_i32 tmode;
25
+ TCGv_ptr status;
26
27
- gen_helper_set_rmode(tmode, tmode, status);
28
-
29
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
30
- vec_full_reg_offset(s, a->rn),
31
- pred_full_reg_offset(s, a->pg),
32
- status, vsz, vsz, 0, fn);
33
-
34
- gen_helper_set_rmode(tmode, tmode, status);
35
- tcg_temp_free_i32(tmode);
36
- tcg_temp_free_ptr(status);
37
+ if (fn == NULL) {
38
+ return false;
39
}
40
+ if (!sve_access_check(s)) {
41
+ return true;
42
+ }
32
+
43
+
33
#endif
44
+ vsz = vec_full_reg_size(s);
34
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
45
+ tmode = tcg_const_i32(mode);
35
index XXXXXXX..XXXXXXX 100644
46
+ status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
36
--- a/target/arm/cpu64.c
47
+
37
+++ b/target/arm/cpu64.c
48
+ gen_helper_set_rmode(tmode, tmode, status);
38
@@ -XXX,XX +XXX,XX @@
49
+
39
#include "hvf_arm.h"
50
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
40
#include "qapi/visitor.h"
51
+ vec_full_reg_offset(s, a->rn),
41
#include "hw/qdev-properties.h"
52
+ pred_full_reg_offset(s, a->pg),
42
-#include "cpregs.h"
53
+ status, vsz, vsz, 0, fn);
43
+#include "internals.h"
54
+
44
55
+ gen_helper_set_rmode(tmode, tmode, status);
45
56
+ tcg_temp_free_i32(tmode);
46
-#ifndef CONFIG_USER_ONLY
57
+ tcg_temp_free_ptr(status);
47
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
58
return true;
48
-{
59
}
49
- ARMCPU *cpu = env_archcpu(env);
60
50
-
61
static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
51
- /* Number of cores is in [25:24]; otherwise we RAZ */
52
- return (cpu->core_count - 1) << 24;
53
-}
54
-#endif
55
-
56
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
57
-#ifndef CONFIG_USER_ONLY
58
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
59
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
60
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
61
- .writefn = arm_cp_write_ignore },
62
- { .name = "L2CTLR",
63
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
64
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
65
- .writefn = arm_cp_write_ignore },
66
-#endif
67
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
68
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
69
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
70
- { .name = "L2ECTLR",
71
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
72
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
73
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
74
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
75
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
76
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
77
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
78
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
- { .name = "CPUACTLR",
80
- .cp = 15, .opc1 = 0, .crm = 15,
81
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
82
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
83
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
84
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
85
- { .name = "CPUECTLR",
86
- .cp = 15, .opc1 = 1, .crm = 15,
87
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
88
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
89
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
90
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
91
- { .name = "CPUMERRSR",
92
- .cp = 15, .opc1 = 2, .crm = 15,
93
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
94
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
95
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
96
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
97
- { .name = "L2MERRSR",
98
- .cp = 15, .opc1 = 3, .crm = 15,
99
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
100
-};
101
-
102
static void aarch64_a57_initfn(Object *obj)
103
{
62
{
104
ARMCPU *cpu = ARM_CPU(obj);
63
- if (a->esz == 0) {
105
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
64
- return false;
106
cpu->gic_num_lrs = 4;
65
- }
107
cpu->gic_vpribits = 5;
66
return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
108
cpu->gic_vprebits = 5;
109
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
110
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
111
}
67
}
112
68
113
static void aarch64_a53_initfn(Object *obj)
69
static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
114
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
70
{
115
cpu->gic_num_lrs = 4;
71
- if (a->esz == 0) {
116
cpu->gic_vpribits = 5;
72
- return false;
117
cpu->gic_vprebits = 5;
73
- }
118
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
74
return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
119
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
120
}
75
}
121
76
122
static void aarch64_a72_initfn(Object *obj)
77
static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
123
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
78
{
124
cpu->gic_num_lrs = 4;
79
- if (a->esz == 0) {
125
cpu->gic_vpribits = 5;
80
- return false;
126
cpu->gic_vprebits = 5;
81
- }
127
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
82
return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
128
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
129
}
83
}
130
84
131
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
85
static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
132
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
86
{
133
index XXXXXXX..XXXXXXX 100644
87
- if (a->esz == 0) {
134
--- a/target/arm/cpu_tcg.c
88
- return false;
135
+++ b/target/arm/cpu_tcg.c
89
- }
136
@@ -XXX,XX +XXX,XX @@
90
return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
137
#endif
91
}
138
#include "cpregs.h"
92
139
93
static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
140
+#ifndef CONFIG_USER_ONLY
94
{
141
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
95
- if (a->esz == 0) {
142
+{
96
- return false;
143
+ ARMCPU *cpu = env_archcpu(env);
97
- }
144
+
98
return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
145
+ /* Number of cores is in [25:24]; otherwise we RAZ */
99
}
146
+ return (cpu->core_count - 1) << 24;
147
+}
148
+
149
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
150
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
151
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
152
+ .access = PL1_RW, .readfn = l2ctlr_read,
153
+ .writefn = arm_cp_write_ignore },
154
+ { .name = "L2CTLR",
155
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
156
+ .access = PL1_RW, .readfn = l2ctlr_read,
157
+ .writefn = arm_cp_write_ignore },
158
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
159
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
160
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
161
+ { .name = "L2ECTLR",
162
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
163
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
164
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
165
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
166
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
167
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
168
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
169
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
170
+ { .name = "CPUACTLR",
171
+ .cp = 15, .opc1 = 0, .crm = 15,
172
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
173
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
174
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
175
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
176
+ { .name = "CPUECTLR",
177
+ .cp = 15, .opc1 = 1, .crm = 15,
178
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
179
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
180
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
181
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
182
+ { .name = "CPUMERRSR",
183
+ .cp = 15, .opc1 = 2, .crm = 15,
184
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
185
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
186
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
187
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
188
+ { .name = "L2MERRSR",
189
+ .cp = 15, .opc1 = 3, .crm = 15,
190
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
191
+};
192
+
193
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
194
+{
195
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
196
+}
197
+#endif /* !CONFIG_USER_ONLY */
198
+
199
/* CPU models. These are not needed for the AArch64 linux-user build. */
200
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
201
100
202
--
101
--
203
2.25.1
102
2.25.1
diff view generated by jsdifflib
[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
[PULL 098/117] target/arm: Use TRANS_FEAT for do_frint_mode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We set this for qemu-system-aarch64, but failed to do so
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
for the strictly 32-bit emulation.
4
Message-id: 20220527181907.189259-96-richard.henderson@linaro.org
5
6
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
target/arm/cpu_tcg.c | 4 ++++
8
target/arm/translate-sve.c | 53 ++++++++++----------------------------
13
1 file changed, 4 insertions(+)
9
1 file changed, 14 insertions(+), 39 deletions(-)
14
10
15
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu_tcg.c
13
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/cpu_tcg.c
14
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
15
@@ -XXX,XX +XXX,XX @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
20
t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
16
return true;
21
cpu->isar.id_pfr2 = t;
17
}
22
18
23
+ t = cpu->isar.id_dfr0;
19
-static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
24
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
20
-{
25
+ cpu->isar.id_dfr0 = t;
21
- return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
26
+
22
-}
27
#ifdef CONFIG_USER_ONLY
23
-
28
/*
24
-static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
29
* Break with true ARMv8 and add back old-style VFP short-vector support.
25
-{
26
- return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
27
-}
28
-
29
-static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
30
-{
31
- return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
32
-}
33
-
34
-static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
35
-{
36
- return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
37
-}
38
-
39
-static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
40
-{
41
- return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
42
-}
43
+TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a,
44
+ float_round_nearest_even, frint_fns[a->esz])
45
+TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a,
46
+ float_round_up, frint_fns[a->esz])
47
+TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a,
48
+ float_round_down, frint_fns[a->esz])
49
+TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a,
50
+ float_round_to_zero, frint_fns[a->esz])
51
+TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a,
52
+ float_round_ties_away, frint_fns[a->esz])
53
54
static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
55
NULL, gen_helper_sve_frecpx_h,
56
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
57
TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
58
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
59
60
-static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a)
61
-{
62
- if (!dc_isar_feature(aa64_sve2, s)) {
63
- return false;
64
- }
65
- return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve_fcvt_ds);
66
-}
67
-
68
-static bool trans_FCVTXNT_ds(DisasContext *s, arg_rpr_esz *a)
69
-{
70
- if (!dc_isar_feature(aa64_sve2, s)) {
71
- return false;
72
- }
73
- return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve2_fcvtnt_ds);
74
-}
75
+TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
76
+ float_round_to_odd, gen_helper_sve_fcvt_ds)
77
+TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
78
+ float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
79
80
static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a)
81
{
30
--
82
--
31
2.25.1
83
2.25.1
diff view generated by jsdifflib
[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
[PULL 099/117] target/arm: Use TRANS_FEAT for FLOGB
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
separate infrastructure for a transitional period. We've now switched
4
Message-id: 20220527181907.189259-97-richard.henderson@linaro.org
5
over to contributing as Qualcomm Innovation Center (quicinc), so update
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
my email address to reflect this.
7
8
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
9
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
10
Cc: Leif Lindholm <leif@nuviainc.com>
11
Cc: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
[Fixed commit message typo]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
7
---
16
.mailmap | 3 ++-
8
target/arm/translate-sve.c | 29 ++++++-----------------------
17
MAINTAINERS | 2 +-
9
1 file changed, 6 insertions(+), 23 deletions(-)
18
2 files changed, 3 insertions(+), 2 deletions(-)
19
10
20
diff --git a/.mailmap b/.mailmap
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
22
--- a/.mailmap
13
--- a/target/arm/translate-sve.c
23
+++ b/.mailmap
14
+++ b/target/arm/translate-sve.c
24
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
25
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
16
TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
26
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
17
float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
27
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
18
28
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
19
-static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a)
29
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
20
-{
30
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
21
- static gen_helper_gvec_3_ptr * const fns[] = {
31
Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
22
- NULL, gen_helper_flogb_h,
32
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
23
- gen_helper_flogb_s, gen_helper_flogb_d
33
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
24
- };
34
diff --git a/MAINTAINERS b/MAINTAINERS
25
-
35
index XXXXXXX..XXXXXXX 100644
26
- if (!dc_isar_feature(aa64_sve2, s) || fns[a->esz] == NULL) {
36
--- a/MAINTAINERS
27
- return false;
37
+++ b/MAINTAINERS
28
- }
38
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
29
- if (sve_access_check(s)) {
39
SBSA-REF
30
- TCGv_ptr status =
40
M: Radoslaw Biernacki <rad@semihalf.com>
31
- fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
41
M: Peter Maydell <peter.maydell@linaro.org>
32
- unsigned vsz = vec_full_reg_size(s);
42
-R: Leif Lindholm <leif@nuviainc.com>
33
-
43
+R: Leif Lindholm <quic_llindhol@quicinc.com>
34
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
44
L: qemu-arm@nongnu.org
35
- vec_full_reg_offset(s, a->rn),
45
S: Maintained
36
- pred_full_reg_offset(s, a->pg),
46
F: hw/arm/sbsa-ref.c
37
- status, vsz, vsz, 0, fns[a->esz]);
38
- tcg_temp_free_ptr(status);
39
- }
40
- return true;
41
-}
42
+static gen_helper_gvec_3_ptr * const flogb_fns[] = {
43
+ NULL, gen_helper_flogb_h,
44
+ gen_helper_flogb_s, gen_helper_flogb_d
45
+};
46
+TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
47
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
48
49
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
50
{
47
--
51
--
48
2.25.1
52
2.25.1
49
50
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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