Series comparison

-[PULL 00/32] target-arm queue
+[PULL 00/34] target-arm queue
-target-arm queue: the big stuff here is the final part of
+I might squeeze in another pullreq before softfreeze, but the
-rth's patches for Cortex-A76 and Neoverse-N1 support;
+queue was already big enough that I wanted to send this lot out now.
 also present are Gavin's NUMA series and a few other things.
-thanks
 -- PMM
-The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
+The following changes since commit 4abf70a661a5df3886ac9d7c19c3617fa92b922a:
-  Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
+  Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging (2020-07-03 15:34:45 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200703
-for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
+for you to fetch changes up to 0f10bf84a9d489259a5b11c6aa1b05c1175b76ea:
-  hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
+  Deprecate TileGX port (2020-07-03 16:59:46 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * MAINTAINERS/.mailmap: update email for Leif Lindholm
+ * i.MX6UL EVK board: put PHYs in the correct places
- * hw/arm: add version information to sbsa-ref machine DT
+ * hw/arm/virt: Let the virtio-iommu bypass MSIs
- * Enable new features for -cpu max:
+ * target/arm: kvm: Handle DABT with no valid ISS
-   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
+ * hw/arm/virt-acpi-build: Only expose flash on older machine types
-   FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
+ * target/arm: Fix temp double-free in sve ldr/str
- * Emulate Cortex-A76
+ * hw/display/bcm2835_fb.c: Initialize all fields of struct
- * Emulate Neoverse-N1
+ * hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak
- * Fix the virt board default NUMA topology
+ * Deprecate TileGX port
 ----------------------------------------------------------------
-Gavin Shan (6):
+Andrew Jones (4):
-      qapi/machine.json: Add cluster-id
+      tests/acpi: remove stale allowed tables
-      qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
+      tests/acpi: virt: allow DSDT acpi table changes
-      hw/arm/virt: Consider SMP configuration in CPU topology
+      hw/arm/virt-acpi-build: Only expose flash on older machine types
-      qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
+      tests/acpi: virt: update golden masters for DSDT
       hw/arm/virt: Fix CPU's default NUMA node ID
       hw/acpi/aml-build: Use existing CPU topology to build PPTT table
-Leif Lindholm (2):
+Beata Michalska (2):
-      MAINTAINERS/.mailmap: update email for Leif Lindholm
+      target/arm: kvm: Handle DABT with no valid ISS
-      hw/arm: add versioning to sbsa-ref machine DT
+      target/arm: kvm: Handle misconfigured dabt injection
-Richard Henderson (24):
+Eric Auger (5):
-      target/arm: Handle cpreg registration for missing EL
+      qdev: Introduce DEFINE_PROP_RESERVED_REGION
-      target/arm: Drop EL3 no EL2 fallbacks
+      virtio-iommu: Implement RESV_MEM probe request
-      target/arm: Merge zcr reginfo
+      virtio-iommu: Handle reserved regions in the translation process
-      target/arm: Adjust definition of CONTEXTIDR_EL2
+      virtio-iommu-pci: Add array of Interval properties
-      target/arm: Move cortex impdef sysregs to cpu_tcg.c
+      hw/arm/virt: Let the virtio-iommu bypass MSIs
       target/arm: Update qemu-system-arm -cpu max to cortex-a57
       target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
       target/arm: Split out aa32_max_features
       target/arm: Annotate arm_max_initfn with FEAT identifiers
       target/arm: Use field names for manipulating EL2 and EL3 modes
       target/arm: Enable FEAT_Debugv8p2 for -cpu max
       target/arm: Enable FEAT_Debugv8p4 for -cpu max
       target/arm: Add minimal RAS registers
       target/arm: Enable SCR and HCR bits for RAS
       target/arm: Implement virtual SError exceptions
       target/arm: Implement ESB instruction
       target/arm: Enable FEAT_RAS for -cpu max
       target/arm: Enable FEAT_IESB for -cpu max
       target/arm: Enable FEAT_CSV2 for -cpu max
       target/arm: Enable FEAT_CSV2_2 for -cpu max
       target/arm: Enable FEAT_CSV3 for -cpu max
       target/arm: Enable FEAT_DGH for -cpu max
       target/arm: Define cortex-a76
       target/arm: Define neoverse-n1
- docs/system/arm/emulation.rst |  10 +
+Jean-Christophe Dubois (3):
- docs/system/arm/virt.rst      |   2 +
+      Add a phy-num property to the i.MX FEC emulator
- qapi/machine.json             |   6 +-
+      Add the ability to select a different PHY for each i.MX6UL FEC interface
- target/arm/cpregs.h           |  11 +
+      Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.
- target/arm/cpu.h              |  23 ++
- target/arm/helper.h           |   1 +
+Peter Maydell (19):
- target/arm/internals.h        |  16 ++
+      hw/display/bcm2835_fb.c: Initialize all fields of struct
- target/arm/syndrome.h         |   5 +
+      hw/arm/spitz: Detabify
- target/arm/a32.decode         |  16 +-
+      hw/arm/spitz: Create SpitzMachineClass abstract base class
- target/arm/t32.decode         |  18 +-
+      hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
- hw/acpi/aml-build.c           | 111 ++++----
+      hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
- hw/arm/sbsa-ref.c             |  16 ++
+      hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
- hw/arm/virt.c                 |  21 +-
+      hw/misc/max111x: provide QOM properties for setting initial values
- hw/core/machine-hmp-cmds.c    |   4 +
+      hw/misc/max111x: Don't use vmstate_register()
- hw/core/machine.c             |  16 ++
+      ssi: Add ssi_realize_and_unref()
- target/arm/cpu.c              |  66 ++++-
+      hw/arm/spitz: Use max111x properties to set initial values
- target/arm/cpu64.c            | 353 ++++++++++++++-----------
+      hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
- target/arm/cpu_tcg.c          | 227 +++++++++++-----
+      hw/misc/max111x: Create header file for documentation, TYPE_ macros
- target/arm/helper.c           | 600 +++++++++++++++++++++++++-----------------
+      hw/arm/spitz: Encapsulate misc GPIO handling in a device
- target/arm/op_helper.c        |  43 +++
+      hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
- target/arm/translate-a64.c    |  18 ++
+      hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
- target/arm/translate.c        |  23 ++
+      hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
- tests/qtest/numa-test.c       |  19 +-
+      hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
- .mailmap                      |   3 +-
+      Replace uses of FROM_SSI_SLAVE() macro with QOM casts
- MAINTAINERS                   |   2 +-
+      Deprecate TileGX port
-files changed, 1068 insertions(+), 562 deletions(-)
 Richard Henderson (1):
       target/arm: Fix temp double-free in sve ldr/str
  docs/system/deprecated.rst                  |  11 +
  include/exec/memory.h                       |   6 +
  include/hw/arm/fsl-imx6ul.h                 |   2 +
  include/hw/arm/pxa.h                        |   1 -
  include/hw/arm/sharpsl.h                    |   3 -
  include/hw/arm/virt.h                       |   8 +
  include/hw/misc/max111x.h                   |  56 +++
  include/hw/net/imx_fec.h                    |   1 +
  include/hw/qdev-properties.h                |   3 +
  include/hw/ssi/ssi.h                        |  31 +-
  include/hw/virtio/virtio-iommu.h            |   2 +
  include/qemu/typedefs.h                     |   1 +
  target/arm/cpu.h                            |   2 +
  target/arm/kvm_arm.h                        |  10 +
  target/arm/translate-a64.h                  |   1 +
  tests/qtest/bios-tables-test-allowed-diff.h |  18 -
  hw/arm/fsl-imx6ul.c                         |  10 +
  hw/arm/mcimx6ul-evk.c                       |   2 +
  hw/arm/pxa2xx_pic.c                         |   9 +-
  hw/arm/spitz.c                              | 507 ++++++++++++++++------------
  hw/arm/virt-acpi-build.c                    |   5 +-
  hw/arm/virt.c                               |  33 ++
  hw/arm/z2.c                                 |  11 +-
  hw/core/qdev-properties.c                   |  89 +++++
  hw/display/ads7846.c                        |   9 +-
  hw/display/bcm2835_fb.c                     |   4 +
  hw/display/ssd0323.c                        |  10 +-
  hw/gpio/zaurus.c                            |  12 +-
  hw/misc/max111x.c                           |  86 +++--
  hw/net/imx_fec.c                            |  24 +-
  hw/sd/ssi-sd.c                              |   4 +-
  hw/ssi/ssi.c                                |   7 +-
  hw/virtio/virtio-iommu-pci.c                |  11 +
  hw/virtio/virtio-iommu.c                    | 114 ++++++-
  target/arm/kvm.c                            |  80 +++++
  target/arm/kvm32.c                          |  34 ++
  target/arm/kvm64.c                          |  49 +++
  target/arm/translate-a64.c                  |   6 +
  target/arm/translate-sve.c                  |   8 +-
  MAINTAINERS                                 |   1 +
  hw/net/trace-events                         |   4 +-
  hw/virtio/trace-events                      |   1 +
  tests/data/acpi/virt/DSDT                   | Bin 5307 -> 5205 bytes
  tests/data/acpi/virt/DSDT.memhp             | Bin 6668 -> 6566 bytes
  tests/data/acpi/virt/DSDT.numamem           | Bin 5307 -> 5205 bytes
 files changed, 974 insertions(+), 312 deletions(-)
  create mode 100644 include/hw/misc/max111x.h

-[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
+[PULL 01/34] Add a phy-num property to the i.MX FEC emulator
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
+We need a solution to use an Ethernet PHY that is not the first device
-during arm_cpu_realizefn.
+on the MDIO bus (device 0 on MDIO bus).
+As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but
+only one MDIO bus on which the 2 related PHY are connected but at unique
+addresses.
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c | 22 +++++++++++++---------
+ include/hw/net/imx_fec.h |  1 +
-file changed, 13 insertions(+), 9 deletions(-)
+ hw/net/imx_fec.c         | 24 +++++++++++++++++-------
  hw/net/trace-events      |  4 ++--
 files changed, 20 insertions(+), 9 deletions(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/include/hw/net/imx_fec.h
-+++ b/target/arm/cpu.c
++++ b/include/hw/net/imx_fec.h
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ typedef struct IMXFECState {
-          */
+     uint32_t phy_advertise;
-         unset_feature(env, ARM_FEATURE_EL3);
+     uint32_t phy_int;
+     uint32_t phy_int_mask;
--        /* Disable the security extension feature bits in the processor feature
++    uint32_t phy_num;
--         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
-+        /*
+     bool is_fec;
-+         * Disable the security extension feature bits in the processor
-+         * feature registers as well.
+diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
-          */
+index XXXXXXX..XXXXXXX 100644
--        cpu->isar.id_pfr1 &= ~0xf0;
+--- a/hw/net/imx_fec.c
--        cpu->isar.id_aa64pfr0 &= ~0xf000;
++++ b/hw/net/imx_fec.c
-+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
+@@ -XXX,XX +XXX,XX @@ static void imx_phy_reset(IMXFECState *s)
-+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+ static uint32_t imx_phy_read(IMXFECState *s, int reg)
-+                                           ID_AA64PFR0, EL3, 0);
+ {
      uint32_t val;
 +    uint32_t phy = reg / 32;
 -    if (reg > 31) {
 -        /* we only advertise one phy */
 +    if (phy != s->phy_num) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
 +                      TYPE_IMX_FEC, __func__, phy);
          return 0;
      }
-     if (!cpu->has_el2) {
++    reg %= 32;
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
++
      switch (reg) {
      case 0:     /* Basic Control */
          val = s->phy_control;
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
          break;
      }
-     if (!arm_feature(env, ARM_FEATURE_EL2)) {
+-    trace_imx_phy_read(val, reg);
--        /* Disable the hypervisor feature bits in the processor feature
++    trace_imx_phy_read(val, phy, reg);
--         * registers if we don't have EL2. These are id_pfr1[15:12] and
--         * id_aa64pfr0_el1[11:8].
+     return val;
-+        /*
+ }
-+         * Disable the hypervisor feature bits in the processor feature
-+         * registers if we don't have EL2.
+ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
-          */
+ {
--        cpu->isar.id_aa64pfr0 &= ~0xf00;
+-    trace_imx_phy_write(val, reg);
--        cpu->isar.id_pfr1 &= ~0xf000;
++    uint32_t phy = reg / 32;
-+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-+                                           ID_AA64PFR0, EL2, 0);
+-    if (reg > 31) {
-+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
+-        /* we only advertise one phy */
-+                                       ID_PFR1, VIRTUALIZATION, 0);
++    if (phy != s->phy_num) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
 +                      TYPE_IMX_FEC, __func__, phy);
          return;
      }
- #ifndef CONFIG_USER_ONLY
++    reg %= 32;
 +
 +    trace_imx_phy_write(val, phy, reg);
 +
      switch (reg) {
      case 0:     /* Basic Control */
          if (val & 0x8000) {
@@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
                                                         extract32(value,
 , 10)));
          } else {
 -            /* This a write operation */
 +            /* This is a write operation */
              imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
          }
          /* raise the interrupt as the PHY operation is done */
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
  static Property imx_eth_properties[] = {
      DEFINE_NIC_PROPERTIES(IMXFECState, conf),
      DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
 +    DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
      DEFINE_PROP_END_OF_LIST(),
  };
 diff --git a/hw/net/trace-events b/hw/net/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/trace-events
 +++ b/hw/net/trace-events
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
  i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
  # imx_fec.c
 -imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
 -imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
 +imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
 +imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
  imx_phy_update_link(const char *s) "%s"
  imx_phy_reset(void) ""
  imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
 --
-.25.1
+.20.1

-[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
+[PULL 02/34] Add the ability to select a different PHY for each i.MX6UL FEC interface
-From: Gavin Shan <gshan@redhat.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-In aarch64_numa_cpu(), the CPU and NUMA association is something
+Add properties to the i.MX6UL processor to be able to select a
-like below. Two threads in the same core/cluster/socket are
+particular PHY on the MDIO bus for each FEC device.
 associated with two individual NUMA nodes, which is unreal as
 Igor Mammedov mentioned. We don't expect the association to break
 NUMA-to-socket boundary, which matches with the real world.
-    NUMA-node  socket  cluster   core   thread
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-    ------------------------------------------
+Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net
-0        0        0      0
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 0        0        0      1
 This corrects the topology for CPUs and their association with
 NUMA nodes. After this patch is applied, the CPU and NUMA
 association becomes something like below, which looks real.
 Besides, socket/cluster/core/thread IDs are all checked when
 the NUMA node IDs are verified. It helps to check if the CPU
 topology is properly populated or not.
     NUMA-node  socket  cluster   core   thread
     ------------------------------------------
 1        0        0       0
 0        0        0       0
 Suggested-by: Igor Mammedov <imammedo@redhat.com>
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Acked-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20220503140304.855514-5-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/qtest/numa-test.c | 18 ++++++++++++------
+ include/hw/arm/fsl-imx6ul.h |  2 ++
-file changed, 12 insertions(+), 6 deletions(-)
+ hw/arm/fsl-imx6ul.c         | 10 ++++++++++
 files changed, 12 insertions(+)
-diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/numa-test.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/tests/qtest/numa-test.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
+@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
-     g_autofree char *cli = NULL;
+     MemoryRegion       caam;
+     MemoryRegion       ocram;
-     cli = make_cli(data, "-machine "
+     MemoryRegion       ocram_alias;
--        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
++
-+        "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
++    uint32_t           phy_num[FSL_IMX6UL_NUM_ETHS];
-         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
+ } FslIMX6ULState;
--        "-numa cpu,node-id=1,thread-id=0 "
--        "-numa cpu,node-id=0,thread-id=1");
+ enum FslIMX6ULMemoryMap {
-+        "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
-+        "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
+index XXXXXXX..XXXXXXX 100644
-     qts = qtest_init(cli);
+--- a/hw/arm/fsl-imx6ul.c
-     cpus = get_cpus(qts, &resp);
++++ b/hw/arm/fsl-imx6ul.c
-     g_assert(cpus);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+             FSL_IMX6UL_ENET2_TIMER_IRQ,
-     while ((e = qlist_pop(cpus))) {
+         };
-         QDict *cpu, *props;
--        int64_t thread, node;
++        object_property_set_uint(OBJECT(&s->eth[i]),
-+        int64_t socket, cluster, core, thread, node;
++                                 s->phy_num[i],
++                                 "phy-num", &error_abort);
-         cpu = qobject_to(QDict, e);
+         object_property_set_uint(OBJECT(&s->eth[i]),
-         g_assert(qdict_haskey(cpu, "props"));
+                                  FSL_IMX6UL_ETH_NUM_TX_RINGS,
-@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
+                                  "tx-ring-num", &error_abort);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
-         g_assert(qdict_haskey(props, "node-id"));
+                                 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
-         node = qdict_get_int(props, "node-id");
+ }
-+        g_assert(qdict_haskey(props, "socket-id"));
-+        socket = qdict_get_int(props, "socket-id");
++static Property fsl_imx6ul_properties[] = {
-+        g_assert(qdict_haskey(props, "cluster-id"));
++    DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
-+        cluster = qdict_get_int(props, "cluster-id");
++    DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
-+        g_assert(qdict_haskey(props, "core-id"));
++    DEFINE_PROP_END_OF_LIST(),
-+        core = qdict_get_int(props, "core-id");
++};
-         g_assert(qdict_haskey(props, "thread-id"));
++
-         thread = qdict_get_int(props, "thread-id");
+ static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
+ {
--        if (thread == 0) {
+     DeviceClass *dc = DEVICE_CLASS(oc);
-+        if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
-             g_assert_cmpint(node, ==, 1);
++    device_class_set_props(dc, fsl_imx6ul_properties);
--        } else if (thread == 1) {
+     dc->realize = fsl_imx6ul_realize;
-+        } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
+     dc->desc = "i.MX6UL SOC";
-             g_assert_cmpint(node, ==, 0);
+     /* Reason: Uses serial_hds and nd_table in realize() directly */
          } else {
              g_assert(false);
 --
-.25.1
+.20.1

-[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
+[PULL 03/34] Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.
-From: Leif Lindholm <quic_llindhol@quicinc.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-The sbsa-ref machine is continuously evolving. Some of the changes we
+The i.MX6UL EVK 14x14 board uses:
-want to make in the near future, to align with real components (e.g.
+- PHY 2 for FEC 1
-the GIC-700), will break compatibility for existing firmware.
+- PHY 1 for FEC 2
-Introduce two new properties to the DT generated on machine generation:
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-- machine-version-major
+Message-id: fb41992126c091a71d76ab3d1898959091f60583.1593296112.git.jcd@tribudubois.net
   To be incremented when a platform change makes the machine
   incompatible with existing firmware.
 - machine-version-minor
   To be incremented when functionality is added to the machine
   without causing incompatibility with existing firmware.
   to be reset to 0 when machine-version-major is incremented.
 This versioning scheme is *neither*:
 - A QEMU versioned machine type; a given version of QEMU will emulate
   a given version of the platform.
 - A reflection of level of SBSA (now SystemReady SR) support provided.
 The version will increment on guest-visible functional changes only,
 akin to a revision ID register found on a physical platform.
 These properties are both introduced with the value 0.
 (Hence, a machine where the DT is lacking these nodes is equivalent
 to version 0.0.)
 Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
 Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Cc: Radoslaw Biernacki <rad@semihalf.com>
 Cc: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/sbsa-ref.c | 14 ++++++++++++++
+ hw/arm/mcimx6ul-evk.c | 2 ++
-file changed, 14 insertions(+)
+file changed, 2 insertions(+)
-diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
+diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/sbsa-ref.c
+--- a/hw/arm/mcimx6ul-evk.c
-+++ b/hw/arm/sbsa-ref.c
++++ b/hw/arm/mcimx6ul-evk.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
+@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
-     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
-     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
+     s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
+     object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
-+    /*
++    object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal);
-+     * This versioning scheme is for informing platform fw only. It is neither:
++    object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal);
-+     * - A QEMU versioned machine type; a given version of QEMU will emulate
+     qdev_realize(DEVICE(s), NULL, &error_fatal);
-+     *   a given version of the platform.
-+     * - A reflection of level of SBSA (now SystemReady SR) support provided.
+     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
 +     *
 +     * machine-version-major: updated when changes breaking fw compatibility
 +     *                        are introduced.
 +     * machine-version-minor: updated when features are added that don't break
 +     *                        fw compatibility.
 +     */
 +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
 +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
 +
      if (ms->numa_state->have_numa_distance) {
          int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
          uint32_t *matrix = g_malloc0(size);
 --
-.25.1
+.20.1

-[PULL 14/32] target/arm: Add minimal RAS registers
+[PULL 04/34] qdev: Introduce DEFINE_PROP_RESERVED_REGION
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Eric Auger <eric.auger@redhat.com>
-Add only the system registers required to implement zero error
+Introduce a new property defining a reserved region:
-records.  This means that all values for ERRSELR are out of range,
+<low address>:<high address>:<type>.
 which means that it and all of the indexed error record registers
 need not be implemented.
-Add the EL2 registers required for injecting virtual SError.
+This will be used to encode reserved IOVA regions.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+For instance, in virtio-iommu use case, reserved IOVA regions
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+will be passed by the machine code to the virtio-iommu-pci
-Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
+device (an array of those). The type of the reserved region
 will match the virtio_iommu_probe_resv_mem subtype value:
 - VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0)
 - VIRTIO_IOMMU_RESV_MEM_T_MSI (1)
 on PC/Q35 machine, this will be used to inform the
 virtio-iommu-pci device it should bypass the MSI region.
 The reserved region will be: 0xfee00000:0xfeefffff:1.
 On ARM, we can declare the ITS MSI doorbell as an MSI
 region to prevent MSIs from being mapped on guest side.
 Signed-off-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Markus Armbruster <armbru@redhat.com>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Message-id: 20200629070404.10969-2-eric.auger@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h    |  5 +++
+ include/exec/memory.h        |  6 +++
- target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
+ include/hw/qdev-properties.h |  3 ++
-files changed, 89 insertions(+)
+ include/qemu/typedefs.h      |  1 +
  hw/core/qdev-properties.c    | 89 ++++++++++++++++++++++++++++++++++++
 files changed, 99 insertions(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/include/exec/memory.h b/include/exec/memory.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/include/exec/memory.h
-+++ b/target/arm/cpu.h
++++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+@@ -XXX,XX +XXX,XX @@ extern bool global_dirty_log;
-         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
-         uint64_t gcr_el1;
+ typedef struct MemoryRegionOps MemoryRegionOps;
-         uint64_t rgsr_el1;
 +struct ReservedRegion {
 +    hwaddr low;
 +    hwaddr high;
 +    unsigned type;
 +};
 +
-+        /* Minimal RAS registers */
+ typedef struct IOMMUTLBEntry IOMMUTLBEntry;
-+        uint64_t disr_el1;
-+        uint64_t vdisr_el2;
+ /* See address_space_translate: bit 0 is read, bit 1 is write.  */
-+        uint64_t vsesr_el2;
+diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
      } cp15;
      struct {
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/include/hw/qdev-properties.h
-+++ b/target/arm/helper.c
++++ b/include/hw/qdev-properties.h
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_string;
-       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
+ extern const PropertyInfo qdev_prop_chr;
  extern const PropertyInfo qdev_prop_tpm;
  extern const PropertyInfo qdev_prop_macaddr;
 +extern const PropertyInfo qdev_prop_reserved_region;
  extern const PropertyInfo qdev_prop_on_off_auto;
  extern const PropertyInfo qdev_prop_multifd_compression;
  extern const PropertyInfo qdev_prop_losttickpolicy;
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_width;
      DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *)
  #define DEFINE_PROP_MACADDR(_n, _s, _f)         \
      DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
 +#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f)         \
 +    DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion)
  #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
      DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
  #define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \
 diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/qemu/typedefs.h
 +++ b/include/qemu/typedefs.h
@@ -XXX,XX +XXX,XX @@ typedef struct ISABus ISABus;
  typedef struct ISADevice ISADevice;
  typedef struct IsaDma IsaDma;
  typedef struct MACAddr MACAddr;
 +typedef struct ReservedRegion ReservedRegion;
  typedef struct MachineClass MachineClass;
  typedef struct MachineState MachineState;
  typedef struct MemoryListener MemoryListener;
 diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/qdev-properties.c
 +++ b/hw/core/qdev-properties.c
@@ -XXX,XX +XXX,XX @@
  #include "chardev/char.h"
  #include "qemu/uuid.h"
  #include "qemu/units.h"
 +#include "qemu/cutils.h"
  void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
                                    Error **errp)
@@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_macaddr = {
      .set   = set_mac,
  };
++/* --- Reserved Region --- */
++
 +/*
-+ * Check for traps to RAS registers, which are controlled
++ * Accepted syntax:
-+ * by HCR_EL2.TERR and SCR_EL3.TERR.
++ *   <low address>:<high address>:<type>
 + *   where low/high addresses are uint64_t in hexadecimal
 + *   and type is a non-negative decimal integer
 + */
-+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
++static void get_reserved_region(Object *obj, Visitor *v, const char *name,
-+                                  bool isread)
++                                void *opaque, Error **errp)
 +{
-+    int el = arm_current_el(env);
++    DeviceState *dev = DEVICE(obj);
 +    Property *prop = opaque;
 +    ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
 +    char buffer[64];
 +    char *p = buffer;
 +    int rc;
 +
-+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
++    rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u",
-+        return CP_ACCESS_TRAP_EL2;
++                  rr->low, rr->high, rr->type);
-+    }
++    assert(rc < sizeof(buffer));
-+    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
++
-+        return CP_ACCESS_TRAP_EL3;
++    visit_type_str(v, name, &p, errp);
 +    }
 +    return CP_ACCESS_OK;
 +}
 +
-+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
++static void set_reserved_region(Object *obj, Visitor *v, const char *name,
 +                                void *opaque, Error **errp)
 +{
-+    int el = arm_current_el(env);
++    DeviceState *dev = DEVICE(obj);
 +    Property *prop = opaque;
 +    ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
 +    Error *local_err = NULL;
 +    const char *endptr;
 +    char *str;
 +    int ret;
 +
-+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
++    if (dev->realized) {
-+        return env->cp15.vdisr_el2;
++        qdev_prop_set_after_realize(dev, name, errp);
 +        return;
 +    }
-+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
++
-+        return 0; /* RAZ/WI */
++    visit_type_str(v, name, &str, &local_err);
 +    if (local_err) {
 +        error_propagate(errp, local_err);
 +        return;
 +    }
-+    return env->cp15.disr_el1;
++
 +    ret = qemu_strtou64(str, &endptr, 16, &rr->low);
 +    if (ret) {
 +        error_setg(errp, "start address of '%s'"
 +                   " must be a hexadecimal integer", name);
 +        goto out;
 +    }
 +    if (*endptr != ':') {
 +        goto separator_error;
 +    }
 +
 +    ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high);
 +    if (ret) {
 +        error_setg(errp, "end address of '%s'"
 +                   " must be a hexadecimal integer", name);
 +        goto out;
 +    }
 +    if (*endptr != ':') {
 +        goto separator_error;
 +    }
 +
 +    ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type);
 +    if (ret) {
 +        error_setg(errp, "type of '%s'"
 +                   " must be a non-negative decimal integer", name);
 +    }
 +    goto out;
 +
 +separator_error:
 +    error_setg(errp, "reserved region fields must be separated with ':'");
 +out:
 +    g_free(str);
 +    return;
 +}
 +
-+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
++const PropertyInfo qdev_prop_reserved_region = {
-+{
++    .name  = "reserved_region",
-+    int el = arm_current_el(env);
++    .description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0",
-+
++    .get   = get_reserved_region,
-+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
++    .set   = set_reserved_region,
 +        env->cp15.vdisr_el2 = val;
 +        return;
 +    }
 +    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
 +        return; /* RAZ/WI */
 +    }
 +    env->cp15.disr_el1 = val;
 +}
 +
 +/*
 + * Minimal RAS implementation with no Error Records.
 + * Which means that all of the Error Record registers:
 + *   ERXADDR_EL1
 + *   ERXCTLR_EL1
 + *   ERXFR_EL1
 + *   ERXMISC0_EL1
 + *   ERXMISC1_EL1
 + *   ERXMISC2_EL1
 + *   ERXMISC3_EL1
 + *   ERXPFGCDN_EL1  (RASv1p1)
 + *   ERXPFGCTL_EL1  (RASv1p1)
 + *   ERXPFGF_EL1    (RASv1p1)
 + *   ERXSTATUS_EL1
 + * and
 + *   ERRSELR_EL1
 + * may generate UNDEFINED, which is the effect we get by not
 + * listing them at all.
 + */
 +static const ARMCPRegInfo minimal_ras_reginfo[] = {
 +    { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
 +      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
 +      .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
 +    { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
 +      .access = PL1_R, .accessfn = access_terr,
 +      .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
 +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
 +    { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
 +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
 +};
 +
- /* Return the exception level to which exceptions should be taken
+ /* --- on/off/auto --- */
-  * via SVEAccessTrap.  If an exception should be routed through
-  * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
+ const PropertyInfo qdev_prop_on_off_auto = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      if (cpu_isar_feature(aa64_ssbs, cpu)) {
          define_one_arm_cp_reg(cpu, &ssbs_reginfo);
      }
 +    if (cpu_isar_feature(any_ras, cpu)) {
 +        define_arm_cp_regs(cpu, minimal_ras_reginfo);
 +    }
      if (cpu_isar_feature(aa64_vh, cpu) ||
          cpu_isar_feature(aa64_debugv8p2, cpu)) {
 --
-.25.1
+.20.1

-[PULL 27/32] qapi/machine.json: Add cluster-id
+[PULL 05/34] virtio-iommu: Implement RESV_MEM probe request
-From: Gavin Shan <gshan@redhat.com>
+From: Eric Auger <eric.auger@redhat.com>
-This adds cluster-id in CPU instance properties, which will be used
+This patch implements the PROBE request. At the moment,
-by arm/virt machine. Besides, the cluster-id is also verified or
+only THE RESV_MEM property is handled. The first goal is
-dumped in various spots:
+to report iommu wide reserved regions such as the MSI regions
+set by the machine code. On x86 this will be the IOAPIC MSI
-  * hw/core/machine.c::machine_set_cpu_numa_node() to associate
+region, [0xFEE00000 - 0xFEEFFFFF], on ARM this may be the ITS
-    CPU with its NUMA node.
+doorbell.
-  * hw/core/machine.c::machine_numa_finish_cpu_init() to record
+In the future we may introduce per device reserved regions.
-    CPU slots with no NUMA mapping set.
+This will be useful when protecting host assigned devices
+which may expose their own reserved regions
-  * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
-    cluster-id.
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
-Signed-off-by: Gavin Shan <gshan@redhat.com>
+Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
-Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Message-id: 20200629070404.10969-3-eric.auger@redhat.com
 Acked-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20220503140304.855514-2-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- qapi/machine.json          |  6 ++++--
+ include/hw/virtio/virtio-iommu.h |  2 +
- hw/core/machine-hmp-cmds.c |  4 ++++
+ hw/virtio/virtio-iommu.c         | 94 ++++++++++++++++++++++++++++++--
- hw/core/machine.c          | 16 ++++++++++++++++
+ hw/virtio/trace-events           |  1 +
-files changed, 24 insertions(+), 2 deletions(-)
+files changed, 93 insertions(+), 4 deletions(-)
-diff --git a/qapi/machine.json b/qapi/machine.json
+diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h
 index XXXXXXX..XXXXXXX 100644
---- a/qapi/machine.json
+--- a/include/hw/virtio/virtio-iommu.h
-+++ b/qapi/machine.json
++++ b/include/hw/virtio/virtio-iommu.h
@@ -XXX,XX +XXX,XX @@ typedef struct VirtIOIOMMU {
      GHashTable *as_by_busptr;
      IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX];
      PCIBus *primary_bus;
 +    ReservedRegion *reserved_regions;
 +    uint32_t nb_reserved_regions;
      GTree *domains;
      QemuMutex mutex;
      GTree *endpoints;
 diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/virtio/virtio-iommu.c
 +++ b/hw/virtio/virtio-iommu.c
 @@ -XXX,XX +XXX,XX @@
- # @node-id: NUMA node ID the CPU belongs to
- # @socket-id: socket number within node/board the CPU belongs to
+ /* Max size */
- # @die-id: die number within socket the CPU belongs to (since 4.1)
+ #define VIOMMU_DEFAULT_QUEUE_SIZE 256
--# @core-id: core number within die the CPU belongs to
++#define VIOMMU_PROBE_SIZE 512
-+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
-+# @core-id: core number within cluster the CPU belongs to
+ typedef struct VirtIOIOMMUDomain {
- # @thread-id: thread number within core the CPU belongs to
+     uint32_t id;
- #
+@@ -XXX,XX +XXX,XX @@ static int virtio_iommu_unmap(VirtIOIOMMU *s,
--# Note: currently there are 5 properties that could be present
+     return ret;
-+# Note: currently there are 6 properties that could be present
+ }
- #       but management should be prepared to pass through other
- #       properties with device_add command to allow for future
++static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep,
- #       interface extension. This also requires the filed names to be kept in
++                                               uint8_t *buf, size_t free)
-@@ -XXX,XX +XXX,XX @@
++{
-   'data': { '*node-id': 'int',
++    struct virtio_iommu_probe_resv_mem prop = {};
-             '*socket-id': 'int',
++    size_t size = sizeof(prop), length = size - sizeof(prop.head), total;
-             '*die-id': 'int',
++    int i;
-+            '*cluster-id': 'int',
++
-             '*core-id': 'int',
++    total = size * s->nb_reserved_regions;
-             '*thread-id': 'int'
++
-   }
++    if (total > free) {
-diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
++        return -ENOSPC;
 +    }
 +
 +    for (i = 0; i < s->nb_reserved_regions; i++) {
 +        unsigned subtype = s->reserved_regions[i].type;
 +
 +        assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED ||
 +               subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI);
 +        prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM);
 +        prop.head.length = cpu_to_le16(length);
 +        prop.subtype = subtype;
 +        prop.start = cpu_to_le64(s->reserved_regions[i].low);
 +        prop.end = cpu_to_le64(s->reserved_regions[i].high);
 +
 +        memcpy(buf, &prop, size);
 +
 +        trace_virtio_iommu_fill_resv_property(ep, prop.subtype,
 +                                              prop.start, prop.end);
 +        buf += size;
 +    }
 +    return total;
 +}
 +
 +/**
 + * virtio_iommu_probe - Fill the probe request buffer with
 + * the properties the device is able to return
 + */
 +static int virtio_iommu_probe(VirtIOIOMMU *s,
 +                              struct virtio_iommu_req_probe *req,
 +                              uint8_t *buf)
 +{
 +    uint32_t ep_id = le32_to_cpu(req->endpoint);
 +    size_t free = VIOMMU_PROBE_SIZE;
 +    ssize_t count;
 +
 +    if (!virtio_iommu_mr(s, ep_id)) {
 +        return VIRTIO_IOMMU_S_NOENT;
 +    }
 +
 +    count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free);
 +    if (count < 0) {
 +        return VIRTIO_IOMMU_S_INVAL;
 +    }
 +    buf += count;
 +    free -= count;
 +
 +    return VIRTIO_IOMMU_S_OK;
 +}
 +
  static int virtio_iommu_iov_to_req(struct iovec *iov,
                                     unsigned int iov_cnt,
                                     void *req, size_t req_sz)
@@ -XXX,XX +XXX,XX @@ virtio_iommu_handle_req(detach)
  virtio_iommu_handle_req(map)
  virtio_iommu_handle_req(unmap)
 +static int virtio_iommu_handle_probe(VirtIOIOMMU *s,
 +                                     struct iovec *iov,
 +                                     unsigned int iov_cnt,
 +                                     uint8_t *buf)
 +{
 +    struct virtio_iommu_req_probe req;
 +    int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req));
 +
 +    return ret ? ret : virtio_iommu_probe(s, &req, buf);
 +}
 +
  static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
  {
      VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
      struct virtio_iommu_req_head head;
      struct virtio_iommu_req_tail tail = {};
 +    size_t output_size = sizeof(tail), sz;
      VirtQueueElement *elem;
      unsigned int iov_cnt;
      struct iovec *iov;
 -    size_t sz;
 +    void *buf = NULL;
      for (;;) {
          elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
          case VIRTIO_IOMMU_T_UNMAP:
              tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
              break;
 +        case VIRTIO_IOMMU_T_PROBE:
 +        {
 +            struct virtio_iommu_req_tail *ptail;
 +
 +            output_size = s->config.probe_size + sizeof(tail);
 +            buf = g_malloc0(output_size);
 +
 +            ptail = (struct virtio_iommu_req_tail *)
 +                        (buf + s->config.probe_size);
 +            ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf);
 +        }
          default:
              tail.status = VIRTIO_IOMMU_S_UNSUPP;
          }
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
  out:
          sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
 -                          &tail, sizeof(tail));
 -        assert(sz == sizeof(tail));
 +                          buf ? buf : &tail, output_size);
 +        assert(sz == output_size);
 -        virtqueue_push(vq, elem, sizeof(tail));
 +        virtqueue_push(vq, elem, sz);
          virtio_notify(vdev, vq);
          g_free(elem);
 +        g_free(buf);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
      s->config.page_size_mask = TARGET_PAGE_MASK;
      s->config.input_range.end = -1UL;
      s->config.domain_range.end = 32;
 +    s->config.probe_size = VIOMMU_PROBE_SIZE;
      virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX);
      virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC);
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
      virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP);
      virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS);
      virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO);
 +    virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE);
      qemu_mutex_init(&s->mutex);
 diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/machine-hmp-cmds.c
+--- a/hw/virtio/trace-events
-+++ b/hw/core/machine-hmp-cmds.c
++++ b/hw/virtio/trace-events
-@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
+@@ -XXX,XX +XXX,XX @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d"
-         if (c->has_die_id) {
+ virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d"
-             monitor_printf(mon, "    die-id: \"%" PRIu64 "\"\n", c->die_id);
+ virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d"
-         }
+ virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64
-+        if (c->has_cluster_id) {
++virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64
 +            monitor_printf(mon, "    cluster-id: \"%" PRIu64 "\"\n",
 +                           c->cluster_id);
 +        }
          if (c->has_core_id) {
              monitor_printf(mon, "    core-id: \"%" PRIu64 "\"\n", c->core_id);
          }
 diff --git a/hw/core/machine.c b/hw/core/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/machine.c
 +++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
              return;
          }
 +        if (props->has_cluster_id && !slot->props.has_cluster_id) {
 +            error_setg(errp, "cluster-id is not supported");
 +            return;
 +        }
 +
          if (props->has_socket_id && !slot->props.has_socket_id) {
              error_setg(errp, "socket-id is not supported");
              return;
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
                  continue;
          }
 +        if (props->has_cluster_id &&
 +            props->cluster_id != slot->props.cluster_id) {
 +                continue;
 +        }
 +
          if (props->has_die_id && props->die_id != slot->props.die_id) {
                  continue;
          }
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
          }
          g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
      }
 +    if (cpu->props.has_cluster_id) {
 +        if (s->len) {
 +            g_string_append_printf(s, ", ");
 +        }
 +        g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
 +    }
      if (cpu->props.has_core_id) {
          if (s->len) {
              g_string_append_printf(s, ", ");
 --
-.25.1
+.20.1

-[PULL 02/32] target/arm: Handle cpreg registration for missing EL
+[PULL 06/34] virtio-iommu: Handle reserved regions in the translation process
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Eric Auger <eric.auger@redhat.com>
-More gracefully handle cpregs when EL2 and/or EL3 are missing.
+When translating an address we need to check if it belongs to
-If the reg is entirely inaccessible, do not register it at all.
+a reserved virtual address range. If it does, there are 2 cases:
 If the reg is for EL2, and EL3 is present but EL2 is not,
 either discard, squash to res0, const, or keep unchanged.
-Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
+- it belongs to a RESERVED region: the guest should neither use
-with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
+  this address in a MAP not instruct the end-point to DMA on
-translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
+  them. We report an error
 Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
-This will simplify cpreg registration for conditional arm features.
+- It belongs to an MSI region: we bypass the translation.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Xu <peterx@redhat.com>
-Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
+Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Message-id: 20200629070404.10969-4-eric.auger@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h |  11 +++
+ hw/virtio/virtio-iommu.c | 20 ++++++++++++++++++++
- target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
+file changed, 20 insertions(+)
 files changed, 133 insertions(+), 56 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/hw/virtio/virtio-iommu.c
-+++ b/target/arm/cpregs.h
++++ b/hw/virtio/virtio-iommu.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
-     ARM_CP_SVE                   = 1 << 14,
+     uint32_t sid, flags;
-     /* Flag: Do not expose in gdb sysreg xml. */
+     bool bypass_allowed;
-     ARM_CP_NO_GDB                = 1 << 15,
+     bool found;
-+    /*
++    int i;
-+     * Flags: If EL3 but not EL2...
-+     *   - UNDEF: discard the cpreg,
+     interval.low = addr;
-+     *   -  KEEP: retain the cpreg as is,
+     interval.high = addr + 1;
-+     *   -  C_NZ: set const on the cpreg, but retain resetvalue,
+@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
-+     *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
+         goto unlock;
 +     * See rule RJFFP in section D1.1.3 of DDI0487H.a.
 +     */
 +    ARM_CP_EL3_NO_EL2_UNDEF      = 1 << 16,
 +    ARM_CP_EL3_NO_EL2_KEEP       = 1 << 17,
 +    ARM_CP_EL3_NO_EL2_C_NZ       = 1 << 18,
  };
  /*
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
      { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
 +      .access = PL2_RW,
 +      .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
        .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
      { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
 -      .access = PL2_RW, .resetvalue = 0,
 +      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
        .writefn = dacr_write, .raw_writefn = raw_write,
        .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
      { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
 -      .access = PL2_RW, .resetvalue = 0,
 +      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
        .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
      { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
        .type = ARM_CP_ALIAS,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
        .writefn = tlbimva_hyp_is_write },
      { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_alle2_write },
      { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2_write },
      { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2_write },
      { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_alle2is_write },
      { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
      { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
  #ifndef CONFIG_USER_ONLY
      /* Unlike the other EL2-related AT operations, these must
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
      { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
        .access = PL2_W, .accessfn = at_s1e2_access,
 -      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
 +      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
 +      .writefn = ats_write64 },
      { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
        .access = PL2_W, .accessfn = at_s1e2_access,
 -      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
 +      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
 +      .writefn = ats_write64 },
      /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
       * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
       * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
        .access = PL2_RW, .accessfn = access_tda,
 -      .type = ARM_CP_NOP },
 +      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
      /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
       * Channel but Linux may try to access this register. The 32-bit
       * alias is DBGDCCINT.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .access = PL2_W, .type = ARM_CP_NOP },
      { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
      { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
      { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2_write },
     { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2_write },
     { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_alle2is_write },
      { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .writefn = tlbi_aa64_alle1is_write },
      { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
      { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
                .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -              .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
 +              .resetvalue = cpu->midr,
 +              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
              { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
                .access = PL2_RW, .resetvalue = cpu->midr,
 +              .type = ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
              { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
                .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -              .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
 +              .resetvalue = vmpidr_def,
 +              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
              { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
 -              .access = PL2_RW,
 -              .resetvalue = vmpidr_def,
 +              .access = PL2_RW, .resetvalue = vmpidr_def,
 +              .type = ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
          };
          define_arm_cp_regs(cpu, vpidr_regs);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                     int crm, int opc1, int opc2,
                                     const char *name)
  {
 +    CPUARMState *env = &cpu->env;
      uint32_t key;
      ARMCPRegInfo *r2;
      bool is64 = r->type & ARM_CP_64BIT;
      bool ns = secstate & ARM_CP_SECSTATE_NS;
      int cp = r->cp;
 -    bool isbanked;
      size_t name_len;
 +    bool make_const;
      switch (state) {
      case ARM_CP_STATE_AA32:
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          }
      }
-+    /*
++    for (i = 0; i < s->nb_reserved_regions; i++) {
-+     * Eliminate registers that are not present because the EL is missing.
++        ReservedRegion *reg = &s->reserved_regions[i];
-+     * Doing this here makes it easier to put all registers for a given
++
-+     * feature into the same ARMCPRegInfo array and define them all at once.
++        if (addr >= reg->low && addr <= reg->high) {
-+     */
++            switch (reg->type) {
-+    make_const = false;
++            case VIRTIO_IOMMU_RESV_MEM_T_MSI:
-+    if (arm_feature(env, ARM_FEATURE_EL3)) {
++                entry.perm = flag;
-+        /*
++                break;
-+         * An EL2 register without EL2 but with EL3 is (usually) RES0.
++            case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:
-+         * See rule RJFFP in section D1.1.3 of DDI0487H.a.
++            default:
-+         */
++                virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING,
-+        int min_el = ctz32(r->access) / 2;
++                                          VIRTIO_IOMMU_FAULT_F_ADDRESS,
-+        if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
++                                          sid, addr);
-+            if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
++                break;
 +                return;
 +            }
-+            make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
++            goto unlock;
 +        }
 +    } else {
 +        CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
 +                                 ? PL2_RW : PL1_RW);
 +        if ((r->access & max_el) == 0) {
 +            return;
 +        }
 +    }
 +
-     /* Combine cpreg and name into one allocation. */
+     if (!ep->domain) {
-     name_len = strlen(name) + 1;
+         if (!bypass_allowed) {
-     r2 = g_malloc(sizeof(*r2) + name_len);
+             error_report_once("%s %02x:%02x.%01x not attached to any domain",
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          r2->opaque = opaque;
      }
 -    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 -    if (isbanked) {
 +    if (make_const) {
 +        /* This should not have been a very special register to begin. */
 +        int old_special = r2->type & ARM_CP_SPECIAL_MASK;
 +        assert(old_special == 0 || old_special == ARM_CP_NOP);
          /*
 -         * Register is banked (using both entries in array).
 -         * Overwriting fieldoffset as the array is only used to define
 -         * banked registers but later only fieldoffset is used.
 +         * Set the special function to CONST, retaining the other flags.
 +         * This is important for e.g. ARM_CP_SVE so that we still
 +         * take the SVE trap if CPTR_EL3.EZ == 0.
           */
 -        r2->fieldoffset = r->bank_fieldoffsets[ns];
 -    }
 +        r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
 +        /*
 +         * Usually, these registers become RES0, but there are a few
 +         * special cases like VPIDR_EL2 which have a constant non-zero
 +         * value with writes ignored.
 +         */
 +        if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
 +            r2->resetvalue = 0;
 +        }
 +        /*
 +         * ARM_CP_CONST has precedence, so removing the callbacks and
 +         * offsets are not strictly necessary, but it is potentially
 +         * less confusing to debug later.
 +         */
 +        r2->readfn = NULL;
 +        r2->writefn = NULL;
 +        r2->raw_readfn = NULL;
 +        r2->raw_writefn = NULL;
 +        r2->resetfn = NULL;
 +        r2->fieldoffset = 0;
 +        r2->bank_fieldoffsets[0] = 0;
 +        r2->bank_fieldoffsets[1] = 0;
 +    } else {
 +        bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 -    if (state == ARM_CP_STATE_AA32) {
          if (isbanked) {
              /*
 -             * If the register is banked then we don't need to migrate or
 -             * reset the 32-bit instance in certain cases:
 -             *
 -             * 1) If the register has both 32-bit and 64-bit instances then we
 -             *    can count on the 64-bit instance taking care of the
 -             *    non-secure bank.
 -             * 2) If ARMv8 is enabled then we can count on a 64-bit version
 -             *    taking care of the secure bank.  This requires that separate
 -             *    32 and 64-bit definitions are provided.
 +             * Register is banked (using both entries in array).
 +             * Overwriting fieldoffset as the array is only used to define
 +             * banked registers but later only fieldoffset is used.
               */
 -            if ((r->state == ARM_CP_STATE_BOTH && ns) ||
 -                (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
 +            r2->fieldoffset = r->bank_fieldoffsets[ns];
 +        }
 +        if (state == ARM_CP_STATE_AA32) {
 +            if (isbanked) {
 +                /*
 +                 * If the register is banked then we don't need to migrate or
 +                 * reset the 32-bit instance in certain cases:
 +                 *
 +                 * 1) If the register has both 32-bit and 64-bit instances
 +                 *    then we can count on the 64-bit instance taking care
 +                 *    of the non-secure bank.
 +                 * 2) If ARMv8 is enabled then we can count on a 64-bit
 +                 *    version taking care of the secure bank.  This requires
 +                 *    that separate 32 and 64-bit definitions are provided.
 +                 */
 +                if ((r->state == ARM_CP_STATE_BOTH && ns) ||
 +                    (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
 +                    r2->type |= ARM_CP_ALIAS;
 +                }
 +            } else if ((secstate != r->secure) && !ns) {
 +                /*
 +                 * The register is not banked so we only want to allow
 +                 * migration of the non-secure instance.
 +                 */
                  r2->type |= ARM_CP_ALIAS;
              }
 -        } else if ((secstate != r->secure) && !ns) {
 -            /*
 -             * The register is not banked so we only want to allow migration
 -             * of the non-secure instance.
 -             */
 -            r2->type |= ARM_CP_ALIAS;
 -        }
 -        if (HOST_BIG_ENDIAN &&
 -            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
 -            r2->fieldoffset += sizeof(uint32_t);
 +            if (HOST_BIG_ENDIAN &&
 +                r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
 +                r2->fieldoffset += sizeof(uint32_t);
 +            }
          }
      }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
       * multiple times. Special registers (ie NOP/WFI) are
       * never migratable and not even raw-accessible.
       */
 -    if (r->type & ARM_CP_SPECIAL_MASK) {
 +    if (r2->type & ARM_CP_SPECIAL_MASK) {
          r2->type |= ARM_CP_NO_RAW;
      }
      if (((r->crm == CP_ANY) && crm != 0) ||
 --
-.25.1
+.20.1

-[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
+[PULL 07/34] virtio-iommu-pci: Add array of Interval properties
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Eric Auger <eric.auger@redhat.com>
-Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
+The machine may need to pass reserved regions to the
-vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
+virtio-iommu-pci device (such as the MSI window on x86
-while registering for v8.
+or the MSI doorbells on ARM).
-This is a behavior change for v7 cpus with Security Extensions and
+So let's add an array of Interval properties.
 without Virtualization Extensions, in that the virtualization cpregs
 are now correctly not present.  This would be a migration compatibility
 break, except that we have an existing bug in which migration of 32-bit
 cpus with Security Extensions enabled does not work.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Note: if some reserved regions are already set by the
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+machine code - which should be the case in general -,
-Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
+the length of the property array is already set and
 prevents the end-user from modifying them. For example,
 attempting to use:
 -device virtio-iommu-pci,\
  len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1
 would result in the following error message:
 qemu-system-aarch64: -device virtio-iommu-pci,addr=0xa,
 len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1:
 array size property len-reserved-regions may not be set more than once
 Otherwise, for example, adding two reserved regions is achieved
 using the following options:
 -device virtio-iommu-pci,addr=0xa,len-reserved-regions=2,\
  reserved-regions[0]=0xfee00000:0xfeefffff:1,\
  reserved-regions[1]=0x1000000:100ffff:1
 Signed-off-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Peter Xu <peterx@redhat.com>
 Message-id: 20200629070404.10969-5-eric.auger@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 158 ++++----------------------------------------
+ hw/virtio/virtio-iommu-pci.c | 11 +++++++++++
-file changed, 13 insertions(+), 145 deletions(-)
+file changed, 11 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/virtio/virtio-iommu-pci.c
-+++ b/target/arm/helper.c
++++ b/hw/virtio/virtio-iommu-pci.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ struct VirtIOIOMMUPCI {
-       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
  static Property virtio_iommu_pci_properties[] = {
      DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
 +    DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI,
 +                      vdev.nb_reserved_regions, vdev.reserved_regions,
 +                      qdev_prop_reserved_region, ReservedRegion),
      DEFINE_PROP_END_OF_LIST(),
  };
--/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
+@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
 -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
 -    { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
 -      .access = PL2_RW,
 -      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
 -    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
 -      .access = PL2_RW,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
 -      .access = PL2_RW,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
 -      .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
 -      .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
 -      .access = PL2_RW, .type = ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
 -      .access = PL2_RW, .type = ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
 -      .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
 -      .cp = 15, .opc1 = 6, .crm = 2,
 -      .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
 -      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
 -      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
 -      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
 -      .access = PL2_RW, .accessfn = access_tda,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
 -      .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
 -      .type = ARM_CP_CONST,
 -      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
 -      .access = PL2_RW, .resetvalue = 0 },
 -};
 -
 -/* Ditto, but for registers which exist in ARMv8 but not v7 */
 -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
 -    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
 -      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
 -      .access = PL2_RW,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -};
 -
  static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
  {
-     ARMCPU *cpu = env_archcpu(env);
+     VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev);
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+     DeviceState *vdev = DEVICE(&dev->vdev);
-         define_arm_cp_regs(cpu, v8_idregs);
++    VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
-         define_arm_cp_regs(cpu, v8_cp_reginfo);
      if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
          MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
                            "-no-acpi\n");
          return;
      }
--    if (arm_feature(env, ARM_FEATURE_EL2)) {
++    for (int i = 0; i < s->nb_reserved_regions; i++) {
-+
++        if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED &&
-+    /*
++            s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) {
-+     * Register the base EL2 cpregs.
++            error_setg(errp, "reserved region %d has an invalid type", i);
-+     * Pre v8, these registers are implemented only as part of the
++            error_append_hint(errp, "Valid values are 0 and 1\n");
-+     * Virtualization Extensions (EL2 present).  Beginning with v8,
++        }
-+     * if EL2 is missing but EL3 is enabled, mostly these become
++    }
-+     * RES0 from EL3, with some specific exceptions.
+     object_property_set_link(OBJECT(dev),
-+     */
+                              OBJECT(pci_get_bus(&vpci_dev->pci_dev)),
-+    if (arm_feature(env, ARM_FEATURE_EL2)
+                              "primary-bus", &error_abort);
 +        || (arm_feature(env, ARM_FEATURE_EL3)
 +            && arm_feature(env, ARM_FEATURE_V8))) {
          uint64_t vmpidr_def = mpidr_read_val(env);
          ARMCPRegInfo vpidr_regs[] = {
              { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              };
              define_one_arm_cp_reg(cpu, &rvbar);
          }
 -    } else {
 -        /* If EL2 is missing but higher ELs are enabled, we need to
 -         * register the no_el2 reginfos.
 -         */
 -        if (arm_feature(env, ARM_FEATURE_EL3)) {
 -            /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
 -             * of MIDR_EL1 and MPIDR_EL1.
 -             */
 -            ARMCPRegInfo vpidr_regs[] = {
 -                { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
 -                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
 -                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -                  .type = ARM_CP_CONST, .resetvalue = cpu->midr,
 -                  .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
 -                { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
 -                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
 -                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -                  .type = ARM_CP_NO_RAW,
 -                  .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
 -            };
 -            define_arm_cp_regs(cpu, vpidr_regs);
 -            define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
 -            if (arm_feature(env, ARM_FEATURE_V8)) {
 -                define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
 -            }
 -        }
      }
 +
 +    /* Register the base EL3 cpregs. */
      if (arm_feature(env, ARM_FEATURE_EL3)) {
          define_arm_cp_regs(cpu, el3_cp_reginfo);
          ARMCPRegInfo el3_regs[] = {
 --
-.25.1
+.20.1

-[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
+[PULL 08/34] hw/arm/virt: Let the virtio-iommu bypass MSIs
-From: Gavin Shan <gshan@redhat.com>
+From: Eric Auger <eric.auger@redhat.com>
-When CPU-to-NUMA association isn't explicitly provided by users,
+At the moment the virtio-iommu translates MSI transactions.
-the default one is given by mc->get_default_cpu_node_id(). However,
+This behavior is inherited from ARM SMMU. The virt machine
-the CPU topology isn't fully considered in the default association
+code knows where the guest MSI doorbells are so we can easily
-and this causes CPU topology broken warnings on booting Linux guest.
+declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
 setting the guest will not map MSIs through the IOMMU and those
 transactions will be simply bypassed.
-For example, the following warning messages are observed when the
+Depending on which MSI controller is in use (ITS or GICV2M),
-Linux guest is booted with the following command lines.
+we declare either:
 - the ITS interrupt translation space (ITS_base + 0x10000),
   containing the GITS_TRANSLATOR or
 - The GICV2M single frame, containing the MSI_SETSP_NS register.
-  /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
-  -accel kvm -machine virt,gic-version=host               \
+Message-id: 20200629070404.10969-6-eric.auger@redhat.com
-  -cpu host                                               \
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
   -smp 6,sockets=2,cores=3,threads=1                      \
   -m 1024M,slots=16,maxmem=64G                            \
   -object memory-backend-ram,id=mem0,size=128M            \
   -object memory-backend-ram,id=mem1,size=128M            \
   -object memory-backend-ram,id=mem2,size=128M            \
   -object memory-backend-ram,id=mem3,size=128M            \
   -object memory-backend-ram,id=mem4,size=128M            \
   -object memory-backend-ram,id=mem4,size=384M            \
   -numa node,nodeid=0,memdev=mem0                         \
   -numa node,nodeid=1,memdev=mem1                         \
   -numa node,nodeid=2,memdev=mem2                         \
   -numa node,nodeid=3,memdev=mem3                         \
   -numa node,nodeid=4,memdev=mem4                         \
   -numa node,nodeid=5,memdev=mem5
          :
   alternatives: patching kernel code
   BUG: arch topology borken
   the CLS domain not a subset of the MC domain
   <the above error log repeats>
   BUG: arch topology borken
   the DIE domain not a subset of the NODE domain
 With current implementation of mc->get_default_cpu_node_id(),
 CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
 That's incorrect because CPU#0/1/2 should be associated with same
 NUMA node because they're seated in same socket.
 This fixes the issue by considering the socket ID when the default
 CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
 With this applied, no more CPU topology broken warnings are seen
 from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
 there are no CPUs associated with NODE#2/3/4/5.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Message-id: 20220503140304.855514-6-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 4 +++-
+ include/hw/arm/virt.h |  7 +++++++
-file changed, 3 insertions(+), 1 deletion(-)
+ hw/arm/virt.c         | 30 ++++++++++++++++++++++++++++++
 files changed, 37 insertions(+)
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/virt.h
++++ b/include/hw/arm/virt.h
+@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
+     VIRT_IOMMU_VIRTIO,
+ } VirtIOMMUType;
++typedef enum VirtMSIControllerType {
++    VIRT_MSI_CTRL_NONE,
++    VIRT_MSI_CTRL_GICV2M,
++    VIRT_MSI_CTRL_ITS,
++} VirtMSIControllerType;
++
+ typedef enum VirtGICType {
+     VIRT_GIC_VERSION_MAX,
+     VIRT_GIC_VERSION_HOST,
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+     OnOffAuto acpi;
+     VirtGICType gic_version;
+     VirtIOMMUType iommu;
++    VirtMSIControllerType msi_controller;
+     uint16_t virtio_iommu_bdf;
+     struct arm_boot_info bootinfo;
+     MemMapEntry *memmap;
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
+@@ -XXX,XX +XXX,XX @@ static void create_its(VirtMachineState *vms)
+     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
- static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
      fdt_add_its_gic_node(vms);
 +    vms->msi_controller = VIRT_MSI_CTRL_ITS;
  }
  static void create_v2m(VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms)
      }
      fdt_add_v2m_gic_node(vms);
 +    vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
  }
  static void create_gic(VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ out:
  static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
                                              DeviceState *dev, Error **errp)
  {
--    return idx % ms->numa_state->num_nodes;
++    VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
 +    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
 +
-+    return socket_id % ms->numa_state->num_nodes;
+     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
          virt_memory_pre_plug(hotplug_dev, dev, errp);
 +    } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
 +        hwaddr db_start = 0, db_end = 0;
 +        char *resv_prop_str;
 +
 +        switch (vms->msi_controller) {
 +        case VIRT_MSI_CTRL_NONE:
 +            return;
 +        case VIRT_MSI_CTRL_ITS:
 +            /* GITS_TRANSLATER page */
 +            db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
 +            db_end = base_memmap[VIRT_GIC_ITS].base +
 +                     base_memmap[VIRT_GIC_ITS].size - 1;
 +            break;
 +        case VIRT_MSI_CTRL_GICV2M:
 +            /* MSI_SETSPI_NS page */
 +            db_start = base_memmap[VIRT_GIC_V2M].base;
 +            db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
 +            break;
 +        }
 +        resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
 +                                        db_start, db_end,
 +                                        VIRTIO_IOMMU_RESV_MEM_T_MSI);
 +
 +        qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
 +        qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
 +        g_free(resv_prop_str);
      }
  }
- static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
 --
-.25.1
+.20.1

-[PULL 16/32] target/arm: Implement virtual SError exceptions
+[PULL 09/34] target/arm: kvm: Handle DABT with no valid ISS
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Beata Michalska <beata.michalska@linaro.org>
-Virtual SError exceptions are raised by setting HCR_EL2.VSE,
+On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
-and are routed to EL1 just like other virtual exceptions.
+exception with no valid ISS info to be decoded. The lack of decode info
 makes it at least tricky to emulate those instruction which is one of the
 (many) reasons why KVM will not even try to do so.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Add support for handling those by requesting KVM to inject external
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+dabt into the quest.
-Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
 Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
 Reviewed-by: Andrew Jones <drjones@redhat.com>
 Message-id: 20200629114110.30723-2-beata.michalska@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h       |  2 ++
+ target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
- target/arm/internals.h |  8 ++++++++
+file changed, 52 insertions(+)
  target/arm/syndrome.h  |  5 +++++
  target/arm/cpu.c       | 38 +++++++++++++++++++++++++++++++++++++-
  target/arm/helper.c    | 40 +++++++++++++++++++++++++++++++++++++++-
 files changed, 91 insertions(+), 2 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/target/arm/kvm.c
-+++ b/target/arm/cpu.h
++++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
- #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
- #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
+ static bool cap_has_mp_state;
- #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
+ static bool cap_has_inject_serror_esr;
-+#define EXCP_VSERR          24
++static bool cap_has_inject_ext_dabt;
- /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
+ static ARMHostCPUFeatures arm_host_cpu_features;
- #define ARMV7M_EXCP_RESET   1
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
- #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
+         ret = -EINVAL;
  #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
  #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
  /* The usual mapping for an AArch64 system register to its AArch32
   * counterpart is for the 32 bit world to have access to the lower
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
   */
  void arm_cpu_update_vfiq(ARMCPU *cpu);
 +/**
 + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
 + *
 + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
 + * following a change to the HCR_EL2.VSE bit.
 + */
 +void arm_cpu_update_vserr(ARMCPU *cpu);
 +
  /**
   * arm_mmu_idx_el:
   * @env: The cpu environment
 diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/syndrome.h
 +++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
      return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
  }
 +static inline uint32_t syn_serror(uint32_t extra)
 +{
 +    return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
 +}
 +
  #endif /* TARGET_ARM_SYNDROME_H */
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
      return (cpu->power_state != PSCI_OFF)
          && cs->interrupt_request &
          (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
 -         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
 +         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
           | CPU_INTERRUPT_EXITTB);
  }
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
              return false;
          }
          return !(env->daif & PSTATE_I);
 +    case EXCP_VSERR:
 +        if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
 +            /* VIRQs are only taken when hypervized.  */
 +            return false;
 +        }
 +        return !(env->daif & PSTATE_A);
      default:
          g_assert_not_reached();
      }
-@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-             goto found;
++    if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
-         }
++        if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) {
-     }
++            error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap");
 +    if (interrupt_request & CPU_INTERRUPT_VSERR) {
 +        excp_idx = EXCP_VSERR;
 +        target_el = 1;
 +        if (arm_excp_unmasked(cs, excp_idx, target_el,
 +                              cur_el, secure, hcr_el2)) {
 +            /* Taking a virtual abort clears HCR_EL2.VSE */
 +            env->cp15.hcr_el2 &= ~HCR_VSE;
 +            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
 +            goto found;
 +        }
 +    }
      return false;
   found:
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
      }
  }
 +void arm_cpu_update_vserr(ARMCPU *cpu)
 +{
 +    /*
 +     * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
 +     */
 +    CPUARMState *env = &cpu->env;
 +    CPUState *cs = CPU(cpu);
 +
 +    bool new_state = env->cp15.hcr_el2 & HCR_VSE;
 +
 +    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
 +        if (new_state) {
 +            cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
 +        } else {
-+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
++            /* Set status for supporting the external dabt injection */
-+        }
++            cap_has_inject_ext_dabt = kvm_check_extension(s,
-+    }
++                                    KVM_CAP_ARM_INJECT_EXT_DABT);
 +}
 +
  #ifndef CONFIG_USER_ONLY
  static void arm_cpu_set_irq(void *opaque, int irq, int level)
  {
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
          }
      }
 -    /* External aborts are not possible in QEMU so A bit is always clear */
 +    if (hcr_el2 & HCR_AMO) {
 +        if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
 +            ret |= CPSR_A;
 +        }
 +    }
 +
      return ret;
  }
-@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
+@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
-     g_assert(qemu_mutex_iothread_locked());
+     }
      arm_cpu_update_virq(cpu);
      arm_cpu_update_vfiq(cpu);
 +    arm_cpu_update_vserr(cpu);
  }
- static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
++/**
-@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
++ * kvm_arm_handle_dabt_nisv:
-             [EXCP_LSERR] = "v8M LSERR UsageFault",
++ * @cs: CPUState
-             [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
++ * @esr_iss: ISS encoding (limited) for the exception from Data Abort
-             [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
++ *           ISV bit set to '0b0' -> no valid instruction syndrome
-+            [EXCP_VSERR] = "Virtual SERR",
++ * @fault_ipa: faulting address for the synchronous data abort
-         };
++ *
++ * Returns: 0 if the exception has been handled, < 0 otherwise
-         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
++ */
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
++static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
-         mask = CPSR_A | CPSR_I | CPSR_F;
++                                    uint64_t fault_ipa)
-         offset = 4;
++{
 +    /*
 +     * Request KVM to inject the external data abort into the guest
 +     */
 +    if (cap_has_inject_ext_dabt) {
 +        struct kvm_vcpu_events events = { };
 +        /*
 +         * The external data abort event will be handled immediately by KVM
 +         * using the address fault that triggered the exit on given VCPU.
 +         * Requesting injection of the external data abort does not rely
 +         * on any other VCPU state. Therefore, in this particular case, the VCPU
 +         * synchronization can be exceptionally skipped.
 +         */
 +        events.exception.ext_dabt_pending = 1;
 +        /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
 +        return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
 +    } else {
 +        error_report("Data abort exception triggered by guest memory access "
 +                     "at physical address: 0x"  TARGET_FMT_lx,
 +                     (target_ulong)fault_ipa);
 +        error_printf("KVM unable to emulate faulting instruction.\n");
 +    }
 +    return -1;
 +}
 +
  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
              ret = EXCP_DEBUG;
          } /* otherwise return to guest */
          break;
-+    case EXCP_VSERR:
++    case KVM_EXIT_ARM_NISV:
-+        {
++        /* External DABT with no valid iss to decode */
-+            /*
++        ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss,
-+             * Note that this is reported as a data abort, but the DFAR
++                                       run->arm_nisv.fault_ipa);
 +             * has an UNKNOWN value.  Construct the SError syndrome from
 +             * AET and ExT fields.
 +             */
 +            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
 +
 +            if (extended_addresses_enabled(env)) {
 +                env->exception.fsr = arm_fi_to_lfsc(&fi);
 +            } else {
 +                env->exception.fsr = arm_fi_to_sfsc(&fi);
 +            }
 +            env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
 +            A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
 +            qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
 +                          env->exception.fsr);
 +
 +            new_mode = ARM_CPU_MODE_ABT;
 +            addr = 0x10;
 +            mask = CPSR_A | CPSR_I;
 +            offset = 8;
 +        }
 +        break;
      case EXCP_SMC:
          new_mode = ARM_CPU_MODE_MON;
          addr = 0x08;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
      case EXCP_VFIQ:
          addr += 0x100;
          break;
 +    case EXCP_VSERR:
 +        addr += 0x180;
 +        /* Construct the SError syndrome from IDS and ISS fields. */
 +        env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
 +        env->cp15.esr_el[new_el] = env->exception.syndrome;
 +        break;
      default:
-         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
+         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
-     }
+                       __func__, run->exit_reason);
 --
-.25.1
+.20.1

-[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
+[PULL 10/34] target/arm: kvm: Handle misconfigured dabt injection
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Beata Michalska <beata.michalska@linaro.org>
-There is no branch prediction in TCG, therefore there is no
+Injecting external data abort through KVM might trigger
-need to actually include the context number into the predictor.
+an issue on kernels that do not get updated to include the KVM fix.
-Therefore all we need to do is add the state for SCXTNUM_ELx.
+For those and aarch32 guests, the injected abort gets misconfigured
+to be an implementation defined exception. This leads to the guest
 repeatedly re-running the faulting instruction.
 Add support for handling that case.
 [
   Fixed-by: 018f22f95e8a
     ('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
   Fixed-by: 21aecdbd7f3a
     ('KVM: arm: Make inject_abt32() inject an external abort instead')
 ]
 Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
 Acked-by: Andrew Jones <drjones@redhat.com>
 Message-id: 20200629114110.30723-3-beata.michalska@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/emulation.rst |  3 ++
+ target/arm/cpu.h     |  2 ++
- target/arm/cpu.h              | 16 +++++++++
+ target/arm/kvm_arm.h | 10 +++++++++
- target/arm/cpu.c              |  5 +++
+ target/arm/kvm.c     | 30 ++++++++++++++++++++++++++-
- target/arm/cpu64.c            |  3 +-
+ target/arm/kvm32.c   | 34 ++++++++++++++++++++++++++++++
- target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
+ target/arm/kvm64.c   | 49 ++++++++++++++++++++++++++++++++++++++++++++
-files changed, 86 insertions(+), 2 deletions(-)
+files changed, 124 insertions(+), 1 deletion(-)
 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/emulation.rst
 +++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
  - FEAT_BF16 (AArch64 BFloat16 instructions)
  - FEAT_BTI (Branch Target Identification)
  - FEAT_CSV2 (Cache speculation variant 2)
 +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
 +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
 +- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
  - FEAT_DIT (Data Independent Timing instructions)
  - FEAT_DPB (DC CVAP instruction)
  - FEAT_Debugv8p2 (Debug changes for v8.2)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
-         ARMPACKey apdb;
+         uint64_t esr;
-         ARMPACKey apga;
+     } serror;
-     } keys;
-+
++    uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
-+    uint64_t scxtnum_el[4];
++
- #endif
+     /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
+     uint32_t irq_line_state;
- #if defined(CONFIG_USER_ONLY)
-@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
- #define SCTLR_WXN     (1U << 19)
+index XXXXXXX..XXXXXXX 100644
- #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
+--- a/target/arm/kvm_arm.h
- #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
++++ b/target/arm/kvm_arm.h
-+#define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_hw_debug_active(CPUState *cs);
- #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
+ struct kvm_guest_debug_arch;
- #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
+ void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
- #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
++/**
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
++ * kvm_arm_verify_ext_dabt_pending:
 + * @cs: CPUState
 + *
 + * Verify the fault status code wrt the Ext DABT injection
 + *
 + * Returns: true if the fault status code is as expected, false otherwise
 + */
 +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
 +
  /**
   * its_class_name:
   *
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu)
  void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
  {
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +
 +    if (unlikely(env->ext_dabt_raised)) {
 +        /*
 +         * Verifying that the ext DABT has been properly injected,
 +         * otherwise risking indefinitely re-running the faulting instruction
 +         * Covering a very narrow case for kernels 5.5..5.5.4
 +         * when injected abort was misconfigured to be
 +         * an IMPLEMENTATION DEFINED exception (for 32-bit EL1)
 +         */
 +        if (!arm_feature(env, ARM_FEATURE_AARCH64) &&
 +            unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) {
 +
 +            error_report("Data abort exception with no valid ISS generated by "
 +                   "guest memory access. KVM unable to emulate faulting "
 +                   "instruction. Failed to inject an external data abort "
 +                   "into the guest.");
 +            abort();
 +       }
 +       /* Clear the status */
 +       env->ext_dabt_raised = 0;
 +    }
  }
-+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
+ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
  static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
                                      uint64_t fault_ipa)
  {
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
      /*
       * Request KVM to inject the external data abort into the guest
       */
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
           */
          events.exception.ext_dabt_pending = 1;
          /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
 -        return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
 +        if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) {
 +            env->ext_dabt_raised = 1;
 +            return 0;
 +        }
      } else {
          error_report("Data abort exception triggered by guest memory access "
                       "at physical address: 0x"  TARGET_FMT_lx,
 diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm32.c
 +++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
  {
      qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
  }
 +
 +#define ARM_REG_DFSR  ARM_CP15_REG32(0, 5, 0, 0)
 +#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
 +/*
 + *DFSR:
 + *      TTBCR.EAE == 0
 + *          FS[4]   - DFSR[10]
 + *          FS[3:0] - DFSR[3:0]
 + *      TTBCR.EAE == 1
 + *          FS, bits [5:0]
 + */
 +#define DFSR_FSC(lpae, v) \
 +    ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
 +
 +#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
 +
 +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
 +{
-+    int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
++    uint32_t dfsr_val;
-+    if (key >= 2) {
++
-+        return true;      /* FEAT_CSV2_2 */
++    if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
-+    }
++        ARMCPU *cpu = ARM_CPU(cs);
-+    if (key == 1) {
++        CPUARMState *env = &cpu->env;
-+        key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
++        uint32_t ttbcr;
-+        return key >= 2;  /* FEAT_CSV2_1p2 */
++        int lpae = 0;
 +
 +        if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
 +            lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
 +        }
 +        /* The verification is based on FS filed of the DFSR reg only*/
 +        return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
 +    }
 +    return false;
 +}
-+
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
- static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
+index XXXXXXX..XXXXXXX 100644
- {
+--- a/target/arm/kvm64.c
-     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
++++ b/target/arm/kvm64.c
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+     return false;
-+++ b/target/arm/cpu.c
+ }
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
++
-              */
++#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
-             env->cp15.gcr_el1 = 0x1ffff;
++#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
-         }
++
 +/*
 + * ESR_EL1
 + * ISS encoding
 + * AARCH64: DFSC,   bits [5:0]
 + * AARCH32:
 + *      TTBCR.EAE == 0
 + *          FS[4]   - DFSR[10]
 + *          FS[3:0] - DFSR[3:0]
 + *      TTBCR.EAE == 1
 + *          FS, bits [5:0]
 + */
 +#define ESR_DFSC(aarch64, lpae, v)        \
 +    ((aarch64 || (lpae)) ? ((v) & 0x3F)   \
 +               : (((v) >> 6) | ((v) & 0x1F)))
 +
 +#define ESR_DFSC_EXTABT(aarch64, lpae) \
 +    ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
 +
 +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
 +{
 +    uint64_t dfsr_val;
 +
 +    if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
 +        ARMCPU *cpu = ARM_CPU(cs);
 +        CPUARMState *env = &cpu->env;
 +        int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
 +        int lpae = 0;
 +
 +        if (!aarch64_mode) {
 +            uint64_t ttbcr;
 +
 +            if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
 +                lpae = arm_feature(env, ARM_FEATURE_LPAE)
 +                        && (ttbcr & TTBCR_EAE);
 +            }
 +        }
 +        /*
-+         * Disable access to SCXTNUM_EL0 from CSV2_1p2.
++         * The verification here is based on the DFSC bits
-+         * This is not yet exposed from the Linux kernel in any way.
++         * of the ESR_EL1 reg only
 +         */
-+        env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
++         return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
- #else
++                ESR_DFSC_EXTABT(aarch64_mode, lpae));
          /* Reset into the highest available EL */
          if (arm_feature(env, ARM_FEATURE_EL3)) {
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
      t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
      t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
 -    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
      cpu->isar.id_aa64pfr0 = t;
      t = cpu->isar.id_aa64pfr1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
       * we do for EL2 with the virtualization=on property.
       */
      t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
 +    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
      cpu->isar.id_aa64pfr1 = t;
      t = cpu->isar.id_aa64mmfr0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          if (cpu_isar_feature(aa64_mte, cpu)) {
              valid_mask |= SCR_ATA;
          }
 +        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
 +            valid_mask |= SCR_ENSCXT;
 +        }
      } else {
          valid_mask &= ~(SCR_RW | SCR_ST);
          if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
          if (cpu_isar_feature(aa64_mte, cpu)) {
              valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
          }
 +        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
 +            valid_mask |= HCR_ENSCXT;
 +        }
      }
      /* Clear RES0 bits.  */
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
          { K(3, 0,  5, 6, 0), K(3, 4,  5, 6, 0), K(3, 5, 5, 6, 0),
            "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
 +        { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
 +          "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
 +          isar_feature_aa64_scxtnum },
 +
          /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
          /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
      };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
      },
  };
 -#endif
 +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                     bool isread)
 +{
 +    uint64_t hcr = arm_hcr_el2_eff(env);
 +    int el = arm_current_el(env);
 +
 +    if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
 +        if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
 +            if (hcr & HCR_TGE) {
 +                return CP_ACCESS_TRAP_EL2;
 +            }
 +            return CP_ACCESS_TRAP;
 +        }
 +    } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
 +        return CP_ACCESS_TRAP_EL2;
 +    }
-+    if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
++    return false;
 +        return CP_ACCESS_TRAP_EL2;
 +    }
 +    if (el < 3
 +        && arm_feature(env, ARM_FEATURE_EL3)
 +        && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
 +        return CP_ACCESS_TRAP_EL3;
 +    }
 +    return CP_ACCESS_OK;
 +}
-+
-+static const ARMCPRegInfo scxtnum_reginfo[] = {
-+    { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
-+      .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
-+      .access = PL0_RW, .accessfn = access_scxtnum,
-+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
-+    { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
-+      .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
-+      .access = PL1_RW, .accessfn = access_scxtnum,
-+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
-+    { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
-+      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
-+      .access = PL2_RW, .accessfn = access_scxtnum,
-+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
-+    { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
-+      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
-+      .access = PL3_RW,
-+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
-+};
-+#endif /* TARGET_AARCH64 */
- static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
-                                      bool isread)
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-         define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
-         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
-     }
-+
-+    if (cpu_isar_feature(aa64_scxtnum, cpu)) {
-+        define_arm_cp_regs(cpu, scxtnum_reginfo);
-+    }
- #endif
-     if (cpu_isar_feature(any_predinv, cpu)) {
 --
-.25.1
+.20.1

-[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
+[PULL 11/34] tests/acpi: remove stale allowed tables
-From: Gavin Shan <gshan@redhat.com>
+From: Andrew Jones <drjones@redhat.com>
-The CPU topology isn't enabled on arm/virt machine yet, but we're
+Fixes: 93dd625f8bf7 ("tests/acpi: update expected data files")
-going to do it in next patch. After the CPU topology is enabled by
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-next patch, "thread-id=1" becomes invalid because the CPU core is
+Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
-preferred on arm/virt machine. It means these two CPUs have 0/1
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-as their core IDs, but their thread IDs are all 0. It will trigger
+Message-id: 20200629140938.17566-2-drjones@redhat.com
 test failure as the following message indicates:
   [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test  ERROR
 .48s   killed by signal 6 SIGABRT
   >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
       QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon         \
       QTEST_QEMU_BINARY=./qemu-system-aarch64                                       \
       QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83                                  \
       /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
   ――――――――――――――――――――――――――――――――――――――――――――――
   stderr:
   qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
 This fixes the issue by providing comprehensive SMP configurations
 in aarch64_numa_cpu(). The SMP configurations aren't used before
 the CPU topology is enabled in next patch.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Message-id: 20220503140304.855514-3-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/qtest/numa-test.c | 3 ++-
+ tests/qtest/bios-tables-test-allowed-diff.h | 18 ------------------
-file changed, 2 insertions(+), 1 deletion(-)
+file changed, 18 deletions(-)
-diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/numa-test.c
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
-+++ b/tests/qtest/numa-test.c
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
-@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
+@@ -1,19 +1 @@
-     QTestState *qts;
+ /* List of comma-separated changed AML files to ignore */
-     g_autofree char *cli = NULL;
+-"tests/data/acpi/pc/DSDT",
+-"tests/data/acpi/pc/DSDT.acpihmat",
--    cli = make_cli(data, "-machine smp.cpus=2 "
+-"tests/data/acpi/pc/DSDT.bridge",
-+    cli = make_cli(data, "-machine "
+-"tests/data/acpi/pc/DSDT.cphp",
-+        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+-"tests/data/acpi/pc/DSDT.dimmpxm",
-         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
+-"tests/data/acpi/pc/DSDT.ipmikcs",
-         "-numa cpu,node-id=1,thread-id=0 "
+-"tests/data/acpi/pc/DSDT.memhp",
-         "-numa cpu,node-id=0,thread-id=1");
+-"tests/data/acpi/pc/DSDT.numamem",
 -"tests/data/acpi/q35/DSDT",
 -"tests/data/acpi/q35/DSDT.acpihmat",
 -"tests/data/acpi/q35/DSDT.bridge",
 -"tests/data/acpi/q35/DSDT.cphp",
 -"tests/data/acpi/q35/DSDT.dimmpxm",
 -"tests/data/acpi/q35/DSDT.ipmibt",
 -"tests/data/acpi/q35/DSDT.memhp",
 -"tests/data/acpi/q35/DSDT.mmio64",
 -"tests/data/acpi/q35/DSDT.numamem",
 -"tests/data/acpi/q35/DSDT.tis",
 --
-.25.1
+.20.1

-[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
+[PULL 12/34] tests/acpi: virt: allow DSDT acpi table changes
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-This extension concerns not merging memory access, which TCG does
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-not implement.  Thus we can trivially enable this feature.
+Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
-Add a comment to handle_hint for the DGH instruction, but no code.
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20200629140938.17566-3-drjones@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/emulation.rst | 1 +
+ tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
- target/arm/cpu64.c            | 1 +
+file changed, 3 insertions(+)
  target/arm/translate-a64.c    | 1 +
 files changed, 3 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
-+++ b/docs/system/arm/emulation.rst
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -1 +1,4 @@
- - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+ /* List of comma-separated changed AML files to ignore */
- - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
++"tests/data/acpi/virt/DSDT",
- - FEAT_CSV3 (Cache speculation variant 3)
++"tests/data/acpi/virt/DSDT.memhp",
-+- FEAT_DGH (Data gathering hint)
++"tests/data/acpi/virt/DSDT.numamem",
  - FEAT_DIT (Data Independent Timing instructions)
  - FEAT_DPB (DC CVAP instruction)
  - FEAT_Debugv8p2 (Debug changes for v8.2)
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
      t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
      t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1);      /* FEAT_DGH */
      t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
      cpu->isar.id_aa64isar1 = t;
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
          break;
      case 0b00100: /* SEV */
      case 0b00101: /* SEVL */
 +    case 0b00110: /* DGH */
          /* we treat all as NOP at least for now */
          break;
      case 0b00111: /* XPACLRI */
 --
-.25.1
+.20.1

-[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
+[PULL 13/34] hw/arm/virt-acpi-build: Only expose flash on older machine types
-From: Gavin Shan <gshan@redhat.com>
+From: Andrew Jones <drjones@redhat.com>
-Currently, the SMP configuration isn't considered when the CPU
+The flash device is exclusively for the host-controlled firmware, so
-topology is populated. In this case, it's impossible to provide
+we should not expose it to the OS. Exposing it risks the OS messing
-the default CPU-to-NUMA mapping or association based on the socket
+with it, which could break firmware runtime services and surprise the
-ID of the given CPU.
+OS when all its changes disappear after reboot.
-This takes account of SMP configuration when the CPU topology
+As firmware needs the device and uses DT, we leave the device exposed
-is populated. The die ID for the given CPU isn't assigned since
+there. It's up to firmware to remove the nodes from DT before sending
-it's not supported on arm/virt machine. Besides, the used SMP
+it on to the OS. However, there's no need to force firmware to remove
-configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
+tables from ACPI (which it doesn't know how to do anyway), so we
-to avoid testing failure
+simply don't add the tables in the first place. But, as we've been
 adding the tables for quite some time and don't want to change the
 default hardware exposed to versioned machines, then we only stop
 exposing the flash device tables for 5.1 and later machine types.
-Signed-off-by: Gavin Shan <gshan@redhat.com>
+Suggested-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
-Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Suggested-by: Laszlo Ersek <lersek@redhat.com>
-Acked-by: Igor Mammedov <imammedo@redhat.com>
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-Message-id: 20220503140304.855514-4-gshan@redhat.com
+Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 Message-id: 20200629140938.17566-4-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 15 ++++++++++++++-
+ include/hw/arm/virt.h    | 1 +
-file changed, 14 insertions(+), 1 deletion(-)
+ hw/arm/virt-acpi-build.c | 5 ++++-
  hw/arm/virt.c            | 3 +++
 files changed, 8 insertions(+), 1 deletion(-)
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/virt.h
++++ b/include/hw/arm/virt.h
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+     bool no_highmem_ecam;
+     bool no_ged;   /* Machines < 4.2 has no support for ACPI GED device */
+     bool kvm_no_adjvtime;
++    bool acpi_expose_flash;
+ } VirtMachineClass;
+ typedef struct {
+diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt-acpi-build.c
++++ b/hw/arm/virt-acpi-build.c
+@@ -XXX,XX +XXX,XX @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
+ static void
+ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+ {
++    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
+     Aml *scope, *dsdt;
+     MachineState *ms = MACHINE(vms);
+     const MemMapEntry *memmap = vms->memmap;
+@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+     acpi_dsdt_add_cpus(scope, vms->smp_cpus);
+     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
+                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
+-    acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
++    if (vmc->acpi_expose_flash) {
++        acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
++    }
+     acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
+     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
+                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
+@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
-     int n;
-     unsigned int max_cpus = ms->smp.max_cpus;
+ static void virt_machine_5_0_options(MachineClass *mc)
-     VirtMachineState *vms = VIRT_MACHINE(ms);
+ {
-+    MachineClass *mc = MACHINE_GET_CLASS(vms);
++    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
      if (ms->possible_cpus) {
          assert(ms->possible_cpus->len == max_cpus);
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
          ms->possible_cpus->cpus[n].type = ms->cpu_type;
          ms->possible_cpus->cpus[n].arch_id =
              virt_cpu_mp_affinity(vms, n);
 +
-+        assert(!mc->smp_props.dies_supported);
+     virt_machine_5_1_options(mc);
-+        ms->possible_cpus->cpus[n].props.has_socket_id = true;
+     compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
-+        ms->possible_cpus->cpus[n].props.socket_id =
+     mc->numa_mem_supported = true;
-+            n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
++    vmc->acpi_expose_flash = true;
 +        ms->possible_cpus->cpus[n].props.has_cluster_id = true;
 +        ms->possible_cpus->cpus[n].props.cluster_id =
 +            (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
 +        ms->possible_cpus->cpus[n].props.has_core_id = true;
 +        ms->possible_cpus->cpus[n].props.core_id =
 +            (n / ms->smp.threads) % ms->smp.cores;
          ms->possible_cpus->cpus[n].props.has_thread_id = true;
 -        ms->possible_cpus->cpus[n].props.thread_id = n;
 +        ms->possible_cpus->cpus[n].props.thread_id =
 +            n % ms->smp.threads;
      }
      return ms->possible_cpus;
  }
+ DEFINE_VIRT_MACHINE(5, 0)
 --
-.25.1
+.20.1

-[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
+[PULL 14/34] tests/acpi: virt: update golden masters for DSDT
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-This extension concerns cache speculation, which TCG does
+Differences between disassembled ASL files for DSDT:
 not implement.  Thus we can trivially enable this feature.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+@@ -XXX,XX +XXX,XX @@
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+  *
-Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
+  * Disassembling to symbolic ASL+ operators
   *
 - * Disassembly of a, Mon Jun 29 09:50:01 2020
 + * Disassembly of b, Mon Jun 29 09:50:03 2020
   *
   * Original Table Header:
   *     Signature        "DSDT"
 - *     Length           0x000014BB (5307)
 + *     Length           0x00001455 (5205)
   *     Revision         0x02
 - *     Checksum         0xD1
 + *     Checksum         0xE1
   *     OEM ID           "BOCHS "
   *     OEM Table ID     "BXPCDSDT"
   *     OEM Revision     0x00000001 (1)
@@ -XXX,XX +XXX,XX @@
              })
          }
 -        Device (FLS0)
 -        {
 -            Name (_HID, "LNRO0015")  // _HID: Hardware ID
 -            Name (_UID, Zero)  // _UID: Unique ID
 -            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
 -            {
 -                Memory32Fixed (ReadWrite,
 -                    0x00000000,         // Address Base
 -                    0x04000000,         // Address Length
 -                    )
 -            })
 -        }
 -
 -        Device (FLS1)
 -        {
 -            Name (_HID, "LNRO0015")  // _HID: Hardware ID
 -            Name (_UID, One)  // _UID: Unique ID
 -            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
 -            {
 -                Memory32Fixed (ReadWrite,
 -                    0x04000000,         // Address Base
 -                    0x04000000,         // Address Length
 -                    )
 -            })
 -        }
 -
          Device (FWCF)
          {
              Name (_HID, "QEMU0002")  // _HID: Hardware ID
 The other two binaries have the same changes (the removal of the
 flash devices).
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 Message-id: 20200629140938.17566-5-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/emulation.rst | 1 +
+ tests/qtest/bios-tables-test-allowed-diff.h |   3 ---
- target/arm/cpu64.c            | 1 +
+ tests/data/acpi/virt/DSDT                   | Bin 5307 -> 5205 bytes
- target/arm/cpu_tcg.c          | 1 +
+ tests/data/acpi/virt/DSDT.memhp             | Bin 6668 -> 6566 bytes
-files changed, 3 insertions(+)
+ tests/data/acpi/virt/DSDT.numamem           | Bin 5307 -> 5205 bytes
 files changed, 3 deletions(-)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
-+++ b/docs/system/arm/emulation.rst
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -1,4 +1 @@
- - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
+ /* List of comma-separated changed AML files to ignore */
- - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+-"tests/data/acpi/virt/DSDT",
- - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
+-"tests/data/acpi/virt/DSDT.memhp",
-+- FEAT_CSV3 (Cache speculation variant 3)
+-"tests/data/acpi/virt/DSDT.numamem",
- - FEAT_DIT (Data Independent Timing instructions)
+diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT
  - FEAT_DPB (DC CVAP instruction)
  - FEAT_Debugv8p2 (Debug changes for v8.2)
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+GIT binary patch
-+++ b/target/arm/cpu64.c
+delta 28
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a
-     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
-     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
+delta 156
-     t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
+zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
-+    t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1);      /* FEAT_CSV3 */
+zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
-     cpu->isar.id_aa64pfr0 = t;
+LaERl^1zUvy_;n(J
-     t = cpu->isar.id_aa64pfr1;
+diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
+GIT binary patch
-+++ b/target/arm/cpu_tcg.c
+delta 28
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+kcmeA%S!T@T66_MPOp<|tiD@F2G*jb@iRuX(-^xn@0CHUjRR910
-     cpu->isar.id_pfr0 = t;
+delta 156
-     t = cpu->isar.id_pfr2;
+zcmZ2x++)J!66_MfBgMeL^l>7WG*kP$iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^
-+    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
+zE<n;bC|FRCi?5B7fsp|MSSlH!n?PC&v1wsM*TMqS1=eEW7Vhi@(GuwD8){%+U<5Qj
-     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
+LIK*+|0yaqism~!^
-     cpu->isar.id_pfr2 = t;
+diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem
 index XXXXXXX..XXXXXXX 100644
 GIT binary patch
 delta 28
 kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a
 delta 156
 zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
 zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
 LaERl^1zUvy_;n(J
 --
-.25.1
+.20.1

-[PULL 17/32] target/arm: Implement ESB instruction
+[PULL 15/34] target/arm: Fix temp double-free in sve ldr/str
 From: Richard Henderson <richard.henderson@linaro.org>
-Check for and defer any pending virtual SError.
+The temp that gets assigned to clean_addr has been allocated with
 new_tmp_a64, which means that it will be freed at the end of the
 instruction.  Freeing it earlier leads to assertion failure.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+The loop creates a complication, in which we allocate a new local
 temp, which does need freeing, and the final code path is shared
 between the loop and non-loop.
 Fix this complication by adding new_tmp_a64_local so that the new
 local temp is freed at the end, and can be treated exactly like
 the non-loop path.
 Fixes: bba87d0a0f4
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200702175605.1987125-1-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.h        |  1 +
+ target/arm/translate-a64.h | 1 +
- target/arm/a32.decode      | 16 ++++++++------
+ target/arm/translate-a64.c | 6 ++++++
- target/arm/t32.decode      | 18 ++++++++--------
+ target/arm/translate-sve.c | 8 ++------
- target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
+files changed, 9 insertions(+), 6 deletions(-)
  target/arm/translate-a64.c | 17 +++++++++++++++
  target/arm/translate.c     | 23 ++++++++++++++++++++
 files changed, 103 insertions(+), 15 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/target/arm/translate-a64.h
-+++ b/target/arm/helper.h
++++ b/target/arm/translate-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
+@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
- DEF_HELPER_1(yield, void, env)
+     } while (0)
- DEF_HELPER_1(pre_hvc, void, env)
- DEF_HELPER_2(pre_smc, void, env, i32)
+ TCGv_i64 new_tmp_a64(DisasContext *s);
-+DEF_HELPER_1(vesb, void, env)
++TCGv_i64 new_tmp_a64_local(DisasContext *s);
+ TCGv_i64 new_tmp_a64_zero(DisasContext *s);
- DEF_HELPER_3(cpsr_write, void, env, i32, i32)
+ TCGv_i64 cpu_reg(DisasContext *s, int reg);
- DEF_HELPER_2(cpsr_write_eret, void, env, i32)
+ TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
 diff --git a/target/arm/a32.decode b/target/arm/a32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/a32.decode
 +++ b/target/arm/a32.decode
@@ -XXX,XX +XXX,XX @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
  {
    {
 -    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
 -    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
 -    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
 +    [
 +      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
 +      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
 +      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 -    # TODO: Implement SEV, SEVL; may help SMP performance.
 -    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
 -    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
 +      # TODO: Implement SEV, SEVL; may help SMP performance.
 +      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
 +      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
 +
 +      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
 +    ]
      # The canonical nop ends in 00000000, but the whole of the
      # rest of the space executes as nop if otherwise unsupported.
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
    [
      # Hints, and CPS
      {
 -      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
 -      WFE        1111 0011 1010 1111 1000 0000 0000 0010
 -      WFI        1111 0011 1010 1111 1000 0000 0000 0011
 +      [
 +        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
 +        WFE      1111 0011 1010 1111 1000 0000 0000 0010
 +        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 -      # TODO: Implement SEV, SEVL; may help SMP performance.
 -      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
 -      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
 +        # TODO: Implement SEV, SEVL; may help SMP performance.
 +        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
 +        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 -      # For M-profile minimal-RAS ESB can be a NOP, which is the
 -      # default behaviour since it is in the hint space.
 -      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +        ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +      ]
        # The canonical nop ends in 0000 0000, but the whole rest
        # of the space is "reserved hint, behaves as nop".
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/op_helper.c
 +++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                       access_type, mmu_idx, ra);
      }
  }
 +
 +/*
 + * This function corresponds to AArch64.vESBOperation().
 + * Note that the AArch32 version is not functionally different.
 + */
 +void HELPER(vesb)(CPUARMState *env)
 +{
 +    /*
 +     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
 +     * and will return HCR_EL2.VSE == 0, so nothing happens.
 +     */
 +    uint64_t hcr = arm_hcr_el2_eff(env);
 +    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
 +    bool pending = enabled && (hcr & HCR_VSE);
 +    bool masked  = (env->daif & PSTATE_A);
 +
 +    /* If VSE pending and masked, defer the exception.  */
 +    if (pending && masked) {
 +        uint32_t syndrome;
 +
 +        if (arm_el_is_aa64(env, 1)) {
 +            /* Copy across IDS and ISS from VSESR. */
 +            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
 +        } else {
 +            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
 +
 +            if (extended_addresses_enabled(env)) {
 +                syndrome = arm_fi_to_lfsc(&fi);
 +            } else {
 +                syndrome = arm_fi_to_sfsc(&fi);
 +            }
 +            /* Copy across AET and ExT from VSESR. */
 +            syndrome |= env->cp15.vsesr_el2 & 0xd000;
 +        }
 +
 +        /* Set VDISR_EL2.A along with the syndrome. */
 +        env->cp15.vdisr_el2 = syndrome | (1u << 31);
 +
 +        /* Clear pending virtual SError */
 +        env->cp15.hcr_el2 &= ~HCR_VSE;
 +        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
 +    }
 +}
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
+@@ -XXX,XX +XXX,XX @@ TCGv_i64 new_tmp_a64(DisasContext *s)
-             gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+     return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
          }
          break;
 +    case 0b10000: /* ESB */
 +        /* Without RAS, we must implement this as NOP. */
 +        if (dc_isar_feature(aa64_ras, s)) {
 +            /*
 +             * QEMU does not have a source of physical SErrors,
 +             * so we are only concerned with virtual SErrors.
 +             * The pseudocode in the ARM for this case is
 +             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
 +             *      AArch64.vESBOperation();
 +             * Most of the condition can be evaluated at translation time.
 +             * Test for EL2 present, and defer test for SEL2 to runtime.
 +             */
 +            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
 +                gen_helper_vesb(cpu_env);
 +            }
 +        }
 +        break;
      case 0b11000: /* PACIAZ */
          if (s->pauth_active) {
              gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
      return true;
  }
-+static bool trans_ESB(DisasContext *s, arg_ESB *a)
++TCGv_i64 new_tmp_a64_local(DisasContext *s)
 +{
-+    /*
++    assert(s->tmp_a64_count < TMP_A64_MAX);
-+     * For M-profile, minimal-RAS ESB can be a NOP.
++    return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64();
 +     * Without RAS, we must implement this as NOP.
 +     */
 +    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
 +        /*
 +         * QEMU does not have a source of physical SErrors,
 +         * so we are only concerned with virtual SErrors.
 +         * The pseudocode in the ARM for this case is
 +         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
 +         *      AArch32.vESBOperation();
 +         * Most of the condition can be evaluated at translation time.
 +         * Test for EL2 present, and defer test for SEL2 to runtime.
 +         */
 +        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
 +            gen_helper_vesb(cpu_env);
 +        }
 +    }
 +    return true;
 +}
 +
- static bool trans_NOP(DisasContext *s, arg_NOP *a)
+ TCGv_i64 new_tmp_a64_zero(DisasContext *s)
  {
-     return true;
+     TCGv_i64 t = new_tmp_a64(s);
 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-sve.c
 +++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          /* Copy the clean address into a local temp, live across the loop. */
          t0 = clean_addr;
 -        clean_addr = tcg_temp_local_new_i64();
 +        clean_addr = new_tmp_a64_local(s);
          tcg_gen_mov_i64(clean_addr, t0);
 -        tcg_temp_free_i64(t0);
          gen_set_label(loop);
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
          tcg_temp_free_i64(t0);
      }
 -    tcg_temp_free_i64(clean_addr);
  }
  /* Similarly for stores.  */
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          /* Copy the clean address into a local temp, live across the loop. */
          t0 = clean_addr;
 -        clean_addr = tcg_temp_local_new_i64();
 +        clean_addr = new_tmp_a64_local(s);
          tcg_gen_mov_i64(clean_addr, t0);
 -        tcg_temp_free_i64(t0);
          gen_set_label(loop);
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          }
          tcg_temp_free_i64(t0);
      }
 -    tcg_temp_free_i64(clean_addr);
  }
  static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
 --
-.25.1
+.20.1

-[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
+[PULL 16/34] hw/display/bcm2835_fb.c: Initialize all fields of struct
-From: Richard Henderson <richard.henderson@linaro.org>
+In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we
 pass a pointer to a local struct to another function without
 initializing all its fields.  This is a real bug:
 bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig
 struct into s->config, so any fields we don't initialize will corrupt
 the state of the device.
-We set this for qemu-system-aarch64, but failed to do so
+Copy the two fields which we don't want to update (pixo and alpha)
-for the strictly 32-bit emulation.
+from the existing config so we don't accidentally change them.
-Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
+Fixes: cfb7ba983857e40e88
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200628195436.27582-1-peter.maydell@linaro.org
 ---
- target/arm/cpu_tcg.c | 4 ++++
+ hw/display/bcm2835_fb.c | 4 ++++
 file changed, 4 insertions(+)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
+diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
+--- a/hw/display/bcm2835_fb.c
-+++ b/target/arm/cpu_tcg.c
++++ b/hw/display/bcm2835_fb.c
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
-     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+     newconf.base = s->vcram_base | (value & 0xc0000000);
-     cpu->isar.id_pfr2 = t;
+     newconf.base += BCM2835_FB_OFFSET;
-+    t = cpu->isar.id_dfr0;
++    /* Copy fields which we don't want to change from the existing config */
-+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
++    newconf.pixo = s->config.pixo;
-+    cpu->isar.id_dfr0 = t;
++    newconf.alpha = s->config.alpha;
 +
- #ifdef CONFIG_USER_ONLY
+     bcm2835_fb_validate_config(&newconf);
-     /*
-      * Break with true ARMv8 and add back old-style VFP short-vector support.
+     pitch = bcm2835_fb_get_pitch(&newconf);
 --
-.25.1
+.20.1

-[PULL 24/32] target/arm: Define cortex-a76
+[PULL 17/34] hw/arm/spitz: Detabify
-From: Richard Henderson <richard.henderson@linaro.org>
+The spitz board has been around a long time, and still has a fair number
+of hard-coded tab characters in it. We're about to do some work on
-Enable the a76 for virt and sbsa board use.
+this source file, so start out by expanding out the tabs.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+This commit is a pure whitespace only change.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-2-peter.maydell@linaro.org
 ---
- docs/system/arm/virt.rst |  1 +
+ hw/arm/spitz.c | 156 ++++++++++++++++++++++++-------------------------
- hw/arm/sbsa-ref.c        |  1 +
+file changed, 78 insertions(+), 78 deletions(-)
- hw/arm/virt.c            |  1 +
- target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 files changed, 69 insertions(+)
 diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/virt.rst
+--- a/hw/arm/spitz.c
-+++ b/docs/system/arm/virt.rst
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
+@@ -XXX,XX +XXX,XX @@
- - ``cortex-a53`` (64-bit)
+ #include "cpu.h"
- - ``cortex-a57`` (64-bit)
- - ``cortex-a72`` (64-bit)
+ #undef REG_FMT
-+- ``cortex-a76`` (64-bit)
+-#define REG_FMT            "0x%02lx"
- - ``a64fx`` (64-bit)
++#define REG_FMT                         "0x%02lx"
- - ``host`` (with KVM only)
- - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
+ /* Spitz Flash */
-diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
+-#define FLASH_BASE        0x0c000000
-index XXXXXXX..XXXXXXX 100644
+-#define FLASH_ECCLPLB        0x00    /* Line parity 7 - 0 bit */
---- a/hw/arm/sbsa-ref.c
+-#define FLASH_ECCLPUB        0x04    /* Line parity 15 - 8 bit */
-+++ b/hw/arm/sbsa-ref.c
+-#define FLASH_ECCCP        0x08    /* Column parity 5 - 0 bit */
-@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
+-#define FLASH_ECCCNTR        0x0c    /* ECC byte counter */
- static const char * const valid_cpus[] = {
+-#define FLASH_ECCCLRR        0x10    /* Clear ECC */
-     ARM_CPU_TYPE_NAME("cortex-a57"),
+-#define FLASH_FLASHIO        0x14    /* Flash I/O */
-     ARM_CPU_TYPE_NAME("cortex-a72"),
+-#define FLASH_FLASHCTL        0x18    /* Flash Control */
-+    ARM_CPU_TYPE_NAME("cortex-a76"),
++#define FLASH_BASE              0x0c000000
-     ARM_CPU_TYPE_NAME("max"),
++#define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
 +#define FLASH_ECCLPUB           0x04    /* Line parity 15 - 8 bit */
 +#define FLASH_ECCCP             0x08    /* Column parity 5 - 0 bit */
 +#define FLASH_ECCCNTR           0x0c    /* ECC byte counter */
 +#define FLASH_ECCCLRR           0x10    /* Clear ECC */
 +#define FLASH_FLASHIO           0x14    /* Flash I/O */
 +#define FLASH_FLASHCTL          0x18    /* Flash Control */
 -#define FLASHCTL_CE0        (1 << 0)
 -#define FLASHCTL_CLE        (1 << 1)
 -#define FLASHCTL_ALE        (1 << 2)
 -#define FLASHCTL_WP        (1 << 3)
 -#define FLASHCTL_CE1        (1 << 4)
 -#define FLASHCTL_RYBY        (1 << 5)
 -#define FLASHCTL_NCE        (FLASHCTL_CE0 | FLASHCTL_CE1)
 +#define FLASHCTL_CE0            (1 << 0)
 +#define FLASHCTL_CLE            (1 << 1)
 +#define FLASHCTL_ALE            (1 << 2)
 +#define FLASHCTL_WP             (1 << 3)
 +#define FLASHCTL_CE1            (1 << 4)
 +#define FLASHCTL_RYBY           (1 << 5)
 +#define FLASHCTL_NCE            (FLASHCTL_CE0 | FLASHCTL_CE1)
  #define TYPE_SL_NAND "sl-nand"
  #define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
      int ryby;
      switch (addr) {
 -#define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
 +#define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
      case FLASH_ECCLPLB:
          return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
                  BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
 -#define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
 +#define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
      case FLASH_ECCLPUB:
          return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
                  BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
@@ -XXX,XX +XXX,XX @@ static void sl_nand_realize(DeviceState *dev, Error **errp)
  /* Spitz Keyboard */
 -#define SPITZ_KEY_STROBE_NUM    11
 -#define SPITZ_KEY_SENSE_NUM    7
 +#define SPITZ_KEY_STROBE_NUM    11
 +#define SPITZ_KEY_SENSE_NUM     7
  static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
 , 17, 91, 34, 36, 38, 39
@@ -XXX,XX +XXX,XX @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
      { 0x52, 0x43, 0x01, 0x47, 0x49,  -1 ,  -1 ,  -1 ,  -1 ,  -1 ,  -1  },
  };
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+-#define SPITZ_GPIO_AK_INT    13    /* Remote control */
-index XXXXXXX..XXXXXXX 100644
+-#define SPITZ_GPIO_SYNC        16    /* Sync button */
---- a/hw/arm/virt.c
+-#define SPITZ_GPIO_ON_KEY    95    /* Power button */
-+++ b/hw/arm/virt.c
+-#define SPITZ_GPIO_SWA        97    /* Lid */
-@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
+-#define SPITZ_GPIO_SWB        96    /* Tablet mode */
-     ARM_CPU_TYPE_NAME("cortex-a53"),
++#define SPITZ_GPIO_AK_INT       13      /* Remote control */
-     ARM_CPU_TYPE_NAME("cortex-a57"),
++#define SPITZ_GPIO_SYNC                 16      /* Sync button */
-     ARM_CPU_TYPE_NAME("cortex-a72"),
++#define SPITZ_GPIO_ON_KEY       95      /* Power button */
-+    ARM_CPU_TYPE_NAME("cortex-a76"),
++#define SPITZ_GPIO_SWA          97      /* Lid */
-     ARM_CPU_TYPE_NAME("a64fx"),
++#define SPITZ_GPIO_SWB          96      /* Tablet mode */
-     ARM_CPU_TYPE_NAME("host"),
-     ARM_CPU_TYPE_NAME("max"),
+ /* The special buttons are mapped to unused keys */
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+ static const int spitz_gpiomap[5] = {
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
---- a/target/arm/cpu64.c
+ #define SPITZ_MOD_CTRL    (1 << 8)
-+++ b/target/arm/cpu64.c
+ #define SPITZ_MOD_FN      (1 << 9)
-@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
-     define_cortex_a72_a57_a53_cp_reginfo(cpu);
+-#define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
 +#define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
  static void spitz_keyboard_handler(void *opaque, int keycode)
  {
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_handler(void *opaque, int keycode)
      uint16_t code;
      int mapcode;
      switch (keycode) {
 -    case 0x2a:    /* Left Shift */
 +    case 0x2a:  /* Left Shift */
          s->modifiers |= 1;
          break;
      case 0xaa:
          s->modifiers &= ~1;
          break;
 -    case 0x36:    /* Right Shift */
 +    case 0x36:  /* Right Shift */
          s->modifiers |= 2;
          break;
      case 0xb6:
          s->modifiers &= ~2;
          break;
 -    case 0x1d:    /* Control */
 +    case 0x1d:  /* Control */
          s->modifiers |= 4;
          break;
      case 0x9d:
          s->modifiers &= ~4;
          break;
 -    case 0x38:    /* Alt */
 +    case 0x38:  /* Alt */
          s->modifiers |= 8;
          break;
      case 0xb8:
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
  /* LCD backlight controller */
 -#define LCDTG_RESCTL    0x00
 -#define LCDTG_PHACTRL    0x01
 -#define LCDTG_DUTYCTRL    0x02
 -#define LCDTG_POWERREG0    0x03
 -#define LCDTG_POWERREG1    0x04
 -#define LCDTG_GPOR3    0x05
 -#define LCDTG_PICTRL    0x06
 -#define LCDTG_POLCTRL    0x07
 +#define LCDTG_RESCTL    0x00
 +#define LCDTG_PHACTRL   0x01
 +#define LCDTG_DUTYCTRL  0x02
 +#define LCDTG_POWERREG0         0x03
 +#define LCDTG_POWERREG1         0x04
 +#define LCDTG_GPOR3     0x05
 +#define LCDTG_PICTRL    0x06
 +#define LCDTG_POLCTRL   0x07
  typedef struct {
      SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
  /* SSP devices */
 -#define CORGI_SSP_PORT        2
 +#define CORGI_SSP_PORT          2
 -#define SPITZ_GPIO_LCDCON_CS    53
 -#define SPITZ_GPIO_ADS7846_CS    14
 -#define SPITZ_GPIO_MAX1111_CS    20
 -#define SPITZ_GPIO_TP_INT    11
 +#define SPITZ_GPIO_LCDCON_CS    53
 +#define SPITZ_GPIO_ADS7846_CS   14
 +#define SPITZ_GPIO_MAX1111_CS   20
 +#define SPITZ_GPIO_TP_INT       11
  static DeviceState *max1111;
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
      s->enable[line] = !level;
  }
-+static void aarch64_a76_initfn(Object *obj)
+-#define MAX1111_BATT_VOLT    1
-+{
+-#define MAX1111_BATT_TEMP    2
-+    ARMCPU *cpu = ARM_CPU(obj);
+-#define MAX1111_ACIN_VOLT    3
-+
++#define MAX1111_BATT_VOLT       1
-+    cpu->dtb_compatible = "arm,cortex-a76";
++#define MAX1111_BATT_TEMP       2
-+    set_feature(&cpu->env, ARM_FEATURE_V8);
++#define MAX1111_ACIN_VOLT       3
-+    set_feature(&cpu->env, ARM_FEATURE_NEON);
-+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+-#define SPITZ_BATTERY_TEMP    0xe0    /* About 2.9V */
-+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+-#define SPITZ_BATTERY_VOLT    0xd0    /* About 4.0V */
-+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+-#define SPITZ_CHARGEON_ACIN    0x80    /* About 5.0V */
-+    set_feature(&cpu->env, ARM_FEATURE_EL2);
++#define SPITZ_BATTERY_TEMP      0xe0    /* About 2.9V */
-+    set_feature(&cpu->env, ARM_FEATURE_EL3);
++#define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
-+    set_feature(&cpu->env, ARM_FEATURE_PMU);
++#define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
-+
-+    /* Ordered by B2.4 AArch64 registers by functional group */
+ static void spitz_adc_temp_on(void *opaque, int line, int level)
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444C004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0b1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.18 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
 +
 +    /* From B2.93 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +}
 +
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
  {
-     /*
+@@ -XXX,XX +XXX,XX @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
-@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
-     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
+ /* Wm8750 and Max7310 on I2C */
-     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
-     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
+-#define AKITA_MAX_ADDR    0x18
-+    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
+-#define SPITZ_WM_ADDRL    0x1b
-     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+-#define SPITZ_WM_ADDRH    0x1a
-     { .name = "max",                .initfn = aarch64_max_initfn },
++#define AKITA_MAX_ADDR  0x18
- #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
++#define SPITZ_WM_ADDRL  0x1b
 +#define SPITZ_WM_ADDRH  0x1a
 -#define SPITZ_GPIO_WM    5
 +#define SPITZ_GPIO_WM   5
  static void spitz_wm8750_addr(void *opaque, int line, int level)
  {
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
      }
  }
 -#define SPITZ_SCP_LED_GREEN        1
 -#define SPITZ_SCP_JK_B            2
 -#define SPITZ_SCP_CHRG_ON        3
 -#define SPITZ_SCP_MUTE_L        4
 -#define SPITZ_SCP_MUTE_R        5
 -#define SPITZ_SCP_CF_POWER        6
 -#define SPITZ_SCP_LED_ORANGE        7
 -#define SPITZ_SCP_JK_A            8
 -#define SPITZ_SCP_ADC_TEMP_ON        9
 -#define SPITZ_SCP2_IR_ON        1
 -#define SPITZ_SCP2_AKIN_PULLUP        2
 -#define SPITZ_SCP2_BACKLIGHT_CONT    7
 -#define SPITZ_SCP2_BACKLIGHT_ON        8
 -#define SPITZ_SCP2_MIC_BIAS        9
 +#define SPITZ_SCP_LED_GREEN             1
 +#define SPITZ_SCP_JK_B                  2
 +#define SPITZ_SCP_CHRG_ON               3
 +#define SPITZ_SCP_MUTE_L                4
 +#define SPITZ_SCP_MUTE_R                5
 +#define SPITZ_SCP_CF_POWER              6
 +#define SPITZ_SCP_LED_ORANGE            7
 +#define SPITZ_SCP_JK_A                  8
 +#define SPITZ_SCP_ADC_TEMP_ON           9
 +#define SPITZ_SCP2_IR_ON                1
 +#define SPITZ_SCP2_AKIN_PULLUP          2
 +#define SPITZ_SCP2_BACKLIGHT_CONT       7
 +#define SPITZ_SCP2_BACKLIGHT_ON                 8
 +#define SPITZ_SCP2_MIC_BIAS             9
  static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
                  DeviceState *scp0, DeviceState *scp1)
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
      qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
  }
 -#define SPITZ_GPIO_HSYNC        22
 -#define SPITZ_GPIO_SD_DETECT        9
 -#define SPITZ_GPIO_SD_WP        81
 -#define SPITZ_GPIO_ON_RESET        89
 -#define SPITZ_GPIO_BAT_COVER        90
 -#define SPITZ_GPIO_CF1_IRQ        105
 -#define SPITZ_GPIO_CF1_CD        94
 -#define SPITZ_GPIO_CF2_IRQ        106
 -#define SPITZ_GPIO_CF2_CD        93
 +#define SPITZ_GPIO_HSYNC                22
 +#define SPITZ_GPIO_SD_DETECT            9
 +#define SPITZ_GPIO_SD_WP                81
 +#define SPITZ_GPIO_ON_RESET             89
 +#define SPITZ_GPIO_BAT_COVER            90
 +#define SPITZ_GPIO_CF1_IRQ              105
 +#define SPITZ_GPIO_CF1_CD               94
 +#define SPITZ_GPIO_CF2_IRQ              106
 +#define SPITZ_GPIO_CF2_CD               93
  static int spitz_hsync;
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
  /* Board init.  */
  enum spitz_model_e { spitz, akita, borzoi, terrier };
 -#define SPITZ_RAM    0x04000000
 -#define SPITZ_ROM    0x00800000
 +#define SPITZ_RAM       0x04000000
 +#define SPITZ_ROM       0x00800000
  static struct arm_boot_info spitz_binfo = {
      .loader_start = PXA2XX_SDRAM_BASE,
 --
-.25.1
+.20.1

-[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
+[PULL 18/34] hw/arm/spitz: Create SpitzMachineClass abstract base class
-From: Richard Henderson <richard.henderson@linaro.org>
+For the four Spitz-family machines (akita, borzoi, spitz, terrier)
+create a proper abstract class SpitzMachineClass which encapsulates
-This extension concerns branch speculation, which TCG does
+the common behaviour, rather than having them all derive directly
-not implement.  Thus we can trivially enable this feature.
+from TYPE_MACHINE:
+ * instead of each machine class setting mc->init to a wrapper
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+   function which calls spitz_common_init() with parameters,
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+   put that data in the SpitzMachineClass and make spitz_common_init
-Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
+   the SpitzMachineClass machine-init function
  * move the settings of mc->block_default_type and
    mc->ignore_memory_transaction_failures into the SpitzMachineClass
    class init rather than repeating them in each machine's class init
 (The motivation is that we're going to want to keep some state in
 the SpitzMachineState so we can connect GPIOs between devices created
 in one sub-function of the machine init to devices created in a
 different sub-function.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200628142429.17111-3-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++--------------------
- target/arm/cpu64.c            | 1 +
+file changed, 55 insertions(+), 36 deletions(-)
- target/arm/cpu_tcg.c          | 1 +
-files changed, 3 insertions(+)
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/hw/arm/spitz.c
-+++ b/docs/system/arm/emulation.rst
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@
- - FEAT_BBM at level 2 (Translation table break-before-make levels)
+ #include "exec/address-spaces.h"
- - FEAT_BF16 (AArch64 BFloat16 instructions)
+ #include "cpu.h"
- - FEAT_BTI (Branch Target Identification)
-+- FEAT_CSV2 (Cache speculation variant 2)
++enum spitz_model_e { spitz, akita, borzoi, terrier };
- - FEAT_DIT (Data Independent Timing instructions)
++
- - FEAT_DPB (DC CVAP instruction)
++typedef struct {
- - FEAT_Debugv8p2 (Debug changes for v8.2)
++    MachineClass parent;
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
++    enum spitz_model_e model;
-index XXXXXXX..XXXXXXX 100644
++    int arm_id;
---- a/target/arm/cpu64.c
++} SpitzMachineClass;
-+++ b/target/arm/cpu64.c
++
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
++typedef struct {
-     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
++    MachineState parent;
-     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
++} SpitzMachineState;
-     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
++
-+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
++#define TYPE_SPITZ_MACHINE "spitz-common"
-     cpu->isar.id_aa64pfr0 = t;
++#define SPITZ_MACHINE(obj) \
++    OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE)
-     t = cpu->isar.id_aa64pfr1;
++#define SPITZ_MACHINE_GET_CLASS(obj) \
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
++    OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE)
-index XXXXXXX..XXXXXXX 100644
++#define SPITZ_MACHINE_CLASS(klass) \
---- a/target/arm/cpu_tcg.c
++    OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
-+++ b/target/arm/cpu_tcg.c
++
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+ #undef REG_FMT
-     cpu->isar.id_mmfr4 = t;
+ #define REG_FMT                         "0x%02lx"
-     t = cpu->isar.id_pfr0;
+@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
-+    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CVS2 */
+ }
-     t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
-     t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
+ /* Board init.  */
-     cpu->isar.id_pfr0 = t;
+-enum spitz_model_e { spitz, akita, borzoi, terrier };
 -
  #define SPITZ_RAM       0x04000000
  #define SPITZ_ROM       0x00800000
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
      .ram_size = 0x04000000,
  };
 -static void spitz_common_init(MachineState *machine,
 -                              enum spitz_model_e model, int arm_id)
 +static void spitz_common_init(MachineState *machine)
  {
 +    SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
 +    enum spitz_model_e model = smc->model;
      PXA2xxState *mpu;
      DeviceState *scp0, *scp1 = NULL;
      MemoryRegion *address_space_mem = get_system_memory();
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine,
          /* A 4.0 GB microdrive is permanently sitting in CF slot 0.  */
          spitz_microdrive_attach(mpu, 0);
 -    spitz_binfo.board_id = arm_id;
 +    spitz_binfo.board_id = smc->arm_id;
      arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
      sl_bootparam_write(SL_PXA_PARAM_BASE);
  }
 -static void spitz_init(MachineState *machine)
 +static void spitz_common_class_init(ObjectClass *oc, void *data)
  {
 -    spitz_common_init(machine, spitz, 0x2c9);
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +
 +    mc->block_default_type = IF_IDE;
 +    mc->ignore_memory_transaction_failures = true;
 +    mc->init = spitz_common_init;
  }
 -static void borzoi_init(MachineState *machine)
 -{
 -    spitz_common_init(machine, borzoi, 0x33f);
 -}
 -
 -static void akita_init(MachineState *machine)
 -{
 -    spitz_common_init(machine, akita, 0x2e8);
 -}
 -
 -static void terrier_init(MachineState *machine)
 -{
 -    spitz_common_init(machine, terrier, 0x33f);
 -}
 +static const TypeInfo spitz_common_info = {
 +    .name = TYPE_SPITZ_MACHINE,
 +    .parent = TYPE_MACHINE,
 +    .abstract = true,
 +    .instance_size = sizeof(SpitzMachineState),
 +    .class_size = sizeof(SpitzMachineClass),
 +    .class_init = spitz_common_class_init,
 +};
  static void akitapda_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
      mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
 -    mc->init = akita_init;
 -    mc->ignore_memory_transaction_failures = true;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
 +    smc->model = akita;
 +    smc->arm_id = 0x2e8;
  }
  static const TypeInfo akitapda_type = {
      .name = MACHINE_TYPE_NAME("akita"),
 -    .parent = TYPE_MACHINE,
 +    .parent = TYPE_SPITZ_MACHINE,
      .class_init = akitapda_class_init,
  };
  static void spitzpda_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
      mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
 -    mc->init = spitz_init;
 -    mc->block_default_type = IF_IDE;
 -    mc->ignore_memory_transaction_failures = true;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
 +    smc->model = spitz;
 +    smc->arm_id = 0x2c9;
  }
  static const TypeInfo spitzpda_type = {
      .name = MACHINE_TYPE_NAME("spitz"),
 -    .parent = TYPE_MACHINE,
 +    .parent = TYPE_SPITZ_MACHINE,
      .class_init = spitzpda_class_init,
  };
  static void borzoipda_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
      mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
 -    mc->init = borzoi_init;
 -    mc->block_default_type = IF_IDE;
 -    mc->ignore_memory_transaction_failures = true;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
 +    smc->model = borzoi;
 +    smc->arm_id = 0x33f;
  }
  static const TypeInfo borzoipda_type = {
      .name = MACHINE_TYPE_NAME("borzoi"),
 -    .parent = TYPE_MACHINE,
 +    .parent = TYPE_SPITZ_MACHINE,
      .class_init = borzoipda_class_init,
  };
  static void terrierpda_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
      mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
 -    mc->init = terrier_init;
 -    mc->block_default_type = IF_IDE;
 -    mc->ignore_memory_transaction_failures = true;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
 +    smc->model = terrier;
 +    smc->arm_id = 0x33f;
  }
  static const TypeInfo terrierpda_type = {
      .name = MACHINE_TYPE_NAME("terrier"),
 -    .parent = TYPE_MACHINE,
 +    .parent = TYPE_SPITZ_MACHINE,
      .class_init = terrierpda_class_init,
  };
  static void spitz_machine_init(void)
  {
 +    type_register_static(&spitz_common_info);
      type_register_static(&akitapda_type);
      type_register_static(&spitzpda_type);
      type_register_static(&borzoipda_type);
 --
-.25.1
+.20.1

-[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
+[PULL 19/34] hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
-From: Richard Henderson <richard.henderson@linaro.org>
+Keep pointers to the MPU and the SSI devices in SpitzMachineState.
 We're going to want to make GPIO connections between some of the
 SSI devices and the SCPs, so we want to keep hold of a pointer to
 those; putting the MPU into the struct allows us to pass just
 one thing to spitz_ssp_attach() rather than two.
-This feature is AArch64 only, and applies to physical SErrors,
+We have to retain the setting of the global "max1111" variable
-which QEMU does not implement, thus the feature is a nop.
+for the moment as it is used in spitz_adc_temp_on(); later in
 this series of commits we will be able to remove it.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-4-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++----------------------
- target/arm/cpu64.c            | 1 +
+file changed, 28 insertions(+), 22 deletions(-)
 files changed, 2 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/hw/arm/spitz.c
-+++ b/docs/system/arm/emulation.rst
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@ typedef struct {
- - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
- - FEAT_HPDS (Hierarchical permission disables)
+ typedef struct {
- - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
+     MachineState parent;
-+- FEAT_IESB (Implicit error synchronization event)
++    PXA2xxState *mpu;
- - FEAT_JSCVT (JavaScript conversion instructions)
++    DeviceState *mux;
- - FEAT_LOR (Limited ordering regions)
++    DeviceState *lcdtg;
- - FEAT_LPA (Large Physical Address space)
++    DeviceState *ads7846;
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
++    DeviceState *max1111;
-index XXXXXXX..XXXXXXX 100644
+ } SpitzMachineState;
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
+ #define TYPE_SPITZ_MACHINE "spitz-common"
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_realize(SSISlave *d, Error **errp)
-     t = cpu->isar.id_aa64mmfr2;
+     s->bus[2] = ssi_create_bus(dev, "ssi2");
-     t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
+ }
-     t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
-+    t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1);     /* FEAT_IESB */
+-static void spitz_ssp_attach(PXA2xxState *cpu)
-     t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
++static void spitz_ssp_attach(SpitzMachineState *sms)
-     t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
+ {
-     t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
+-    DeviceState *mux;
 -    DeviceState *dev;
      void *bus;
 -    mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
 +    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
 -    bus = qdev_get_child_bus(mux, "ssi0");
 -    ssi_create_slave(bus, "spitz-lcdtg");
 +    bus = qdev_get_child_bus(sms->mux, "ssi0");
 +    sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
 -    bus = qdev_get_child_bus(mux, "ssi1");
 -    dev = ssi_create_slave(bus, "ads7846");
 -    qdev_connect_gpio_out(dev, 0,
 -                          qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
 +    bus = qdev_get_child_bus(sms->mux, "ssi1");
 +    sms->ads7846 = ssi_create_slave(bus, "ads7846");
 +    qdev_connect_gpio_out(sms->ads7846, 0,
 +                          qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
 -    bus = qdev_get_child_bus(mux, "ssi2");
 -    max1111 = ssi_create_slave(bus, "max1111");
 -    max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
 -    max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
 -    max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
 +    bus = qdev_get_child_bus(sms->mux, "ssi2");
 +    sms->max1111 = ssi_create_slave(bus, "max1111");
 +    max1111 = sms->max1111;
 +    max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
 +    max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
 +    max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
 -    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
 -                        qdev_get_gpio_in(mux, 0));
 -    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
 -                        qdev_get_gpio_in(mux, 1));
 -    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
 -                        qdev_get_gpio_in(mux, 2));
 +    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
 +                        qdev_get_gpio_in(sms->mux, 0));
 +    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS,
 +                        qdev_get_gpio_in(sms->mux, 1));
 +    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS,
 +                        qdev_get_gpio_in(sms->mux, 2));
  }
  /* CF Microdrive */
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
  static void spitz_common_init(MachineState *machine)
  {
      SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
 +    SpitzMachineState *sms = SPITZ_MACHINE(machine);
      enum spitz_model_e model = smc->model;
      PXA2xxState *mpu;
      DeviceState *scp0, *scp1 = NULL;
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
      /* Setup CPU & memory */
      mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
                        machine->cpu_type);
 +    sms->mpu = mpu;
      sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
      /* Setup peripherals */
      spitz_keyboard_register(mpu);
 -    spitz_ssp_attach(mpu);
 +    spitz_ssp_attach(sms);
      scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
      if (model != akita) {
 --
-.25.1
+.20.1

-[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
+[PULL 20/34] hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
-From: Richard Henderson <richard.henderson@linaro.org>
+Keep pointers to scp0, scp1 in SpitzMachineState, and just pass
 that to spitz_scoop_gpio_setup().
-Enable writes to the TERR and TEA bits when RAS is enabled.
+(We'll want to use some of the other fields in SpitzMachineState
-These bits are otherwise RES0.
+in that function in the next commit.)
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-5-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 9 +++++++++
+ hw/arm/spitz.c | 34 +++++++++++++++++++---------------
-file changed, 9 insertions(+)
+file changed, 19 insertions(+), 15 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/spitz.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+@@ -XXX,XX +XXX,XX @@ typedef struct {
-         }
+     DeviceState *lcdtg;
-         valid_mask &= ~SCR_NET;
+     DeviceState *ads7846;
+     DeviceState *max1111;
-+        if (cpu_isar_feature(aa64_ras, cpu)) {
++    DeviceState *scp0;
-+            valid_mask |= SCR_TERR;
++    DeviceState *scp1;
-+        }
+ } SpitzMachineState;
-         if (cpu_isar_feature(aa64_lor, cpu)) {
-             valid_mask |= SCR_TLOR;
+ #define TYPE_SPITZ_MACHINE "spitz-common"
-         }
+@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
-@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+ #define SPITZ_SCP2_BACKLIGHT_ON                 8
-         }
+ #define SPITZ_SCP2_MIC_BIAS             9
-     } else {
-         valid_mask &= ~(SCR_RW | SCR_ST);
+-static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
-+        if (cpu_isar_feature(aa32_ras, cpu)) {
+-                DeviceState *scp0, DeviceState *scp1)
-+            valid_mask |= SCR_TERR;
++static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
-+        }
+ {
 -    qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
 +    qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
 -    if (scp1) {
 -        qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
 -        qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
 +    if (sms->scp1) {
 +        qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
 +                              outsignals[4]);
 +        qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
 +                              outsignals[5]);
      }
-     if (!arm_feature(env, ARM_FEATURE_EL2)) {
+-    qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
-@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
++    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
-         if (cpu_isar_feature(aa64_vh, cpu)) {
+ }
-             valid_mask |= HCR_E2H;
-         }
+ #define SPITZ_GPIO_HSYNC                22
-+        if (cpu_isar_feature(aa64_ras, cpu)) {
+@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
-+            valid_mask |= HCR_TERR | HCR_TEA;
+     SpitzMachineState *sms = SPITZ_MACHINE(machine);
-+        }
+     enum spitz_model_e model = smc->model;
-         if (cpu_isar_feature(aa64_lor, cpu)) {
+     PXA2xxState *mpu;
-             valid_mask |= HCR_TLOR;
+-    DeviceState *scp0, *scp1 = NULL;
-         }
+     MemoryRegion *address_space_mem = get_system_memory();
      MemoryRegion *rom = g_new(MemoryRegion, 1);
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
      spitz_ssp_attach(sms);
 -    scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
 +    sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
      if (model != akita) {
 -        scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
 +        sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
 +    } else {
 +        sms->scp1 = NULL;
      }
 -    spitz_scoop_gpio_setup(mpu, scp0, scp1);
 +    spitz_scoop_gpio_setup(sms);
      spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
 --
-.25.1
+.20.1

-[PULL 04/32] target/arm: Merge zcr reginfo
+[PULL 21/34] hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
-From: Richard Henderson <richard.henderson@linaro.org>
+Currently the Spitz board uses a nasty hack for the GPIO lines
 that pass "bit5" and "power" information to the LCD controller:
 the lcdtg realize function sets a global variable to point to
 the instance it just realized, and then the functions spitz_bl_power()
 and spitz_bl_bit5() use that to find the device they are changing
 the internal state of. There is a comment reading:
  FIXME: Implement GPIO properly and remove this hack.
 which was added in 2009.
-Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
+Implement GPIO properly and remove this hack.
 now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
 while registering.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-6-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 55 ++++++++++++++-------------------------------
+ hw/arm/spitz.c | 28 ++++++++++++----------------
-file changed, 17 insertions(+), 38 deletions(-)
+file changed, 12 insertions(+), 16 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/spitz.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static void spitz_bl_update(SpitzLCDTG *s)
          zaurus_printf("LCD Backlight now off\n");
  }
 -/* FIXME: Implement GPIO properly and remove this hack.  */
 -static SpitzLCDTG *spitz_lcdtg;
 -
  static inline void spitz_bl_bit5(void *opaque, int line, int level)
  {
 -    SpitzLCDTG *s = spitz_lcdtg;
 +    SpitzLCDTG *s = opaque;
      int prev = s->bl_intensity;
      if (level)
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_bit5(void *opaque, int line, int level)
  static inline void spitz_bl_power(void *opaque, int line, int level)
  {
 -    SpitzLCDTG *s = spitz_lcdtg;
 +    SpitzLCDTG *s = opaque;
      s->bl_power = !!level;
      spitz_bl_update(s);
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
      return 0;
  }
 -static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
 +static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
  {
 -    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
 +    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
 +    DeviceState *dev = DEVICE(s);
 -    spitz_lcdtg = s;
      s->bl_power = 0;
      s->bl_intensity = 0x20;
 +
 +    qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1);
 +    qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1);
  }
  /* SSP devices */
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
      case 3:
          zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
          break;
 -    case 4:
 -        spitz_bl_bit5(opaque, line, level);
 -        break;
 -    case 5:
 -        spitz_bl_power(opaque, line, level);
 -        break;
      case 6:
          spitz_adc_temp_on(opaque, line, level);
          break;
 +    default:
 +        g_assert_not_reached();
      }
  }
--static const ARMCPRegInfo zcr_el1_reginfo = {
+@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
--    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
--    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
+     if (sms->scp1) {
--    .access = PL1_RW, .type = ARM_CP_SVE,
+         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
--    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
+-                              outsignals[4]);
--    .writefn = zcr_write, .raw_writefn = raw_write
++                              qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0));
--};
+         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
--
+-                              outsignals[5]);
--static const ARMCPRegInfo zcr_el2_reginfo = {
++                              qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
 -    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
 -    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
 -    .access = PL2_RW, .type = ARM_CP_SVE,
 -    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
 -    .writefn = zcr_write, .raw_writefn = raw_write
 -};
 -
 -static const ARMCPRegInfo zcr_no_el2_reginfo = {
 -    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
 -    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
 -    .access = PL2_RW, .type = ARM_CP_SVE,
 -    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
 -};
 -
 -static const ARMCPRegInfo zcr_el3_reginfo = {
 -    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
 -    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
 -    .access = PL3_RW, .type = ARM_CP_SVE,
 -    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
 -    .writefn = zcr_write, .raw_writefn = raw_write
 +static const ARMCPRegInfo zcr_reginfo[] = {
 +    { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_SVE,
 +      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
 +      .writefn = zcr_write, .raw_writefn = raw_write },
 +    { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
 +      .access = PL2_RW, .type = ARM_CP_SVE,
 +      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
 +      .writefn = zcr_write, .raw_writefn = raw_write },
 +    { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
 +      .access = PL3_RW, .type = ARM_CP_SVE,
 +      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
 +      .writefn = zcr_write, .raw_writefn = raw_write },
  };
  void hw_watchpoint_update(ARMCPU *cpu, int n)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      }
-     if (cpu_isar_feature(aa64_sve, cpu)) {
+     qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 -        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
 -        if (arm_feature(env, ARM_FEATURE_EL2)) {
 -            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
 -        } else {
 -            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
 -        }
 -        if (arm_feature(env, ARM_FEATURE_EL3)) {
 -            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
 -        }
 +        define_arm_cp_regs(cpu, zcr_reginfo);
      }
  #ifdef TARGET_AARCH64
 --
-.25.1
+.20.1

-[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
+[PULL 22/34] hw/misc/max111x: provide QOM properties for setting initial values
-From: Richard Henderson <richard.henderson@linaro.org>
+Add some QOM properties to the max111x ADC device to allow the
 initial values to be configured. Currently this is done by
 board code calling max111x_set_input() after it creates the
 device, which doesn't work on system reset.
-Previously we were defining some of these in user-only mode,
+This requires us to implement a reset method for this device,
-but none of them are accessible from user-only, therefore
+so while we're doing that make sure we reset the other parts
-define them only in system mode.
+of the device state.
-This will shortly be used from cpu_tcg.c also.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20200628142429.17111-7-peter.maydell@linaro.org
 ---
  hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++---------
 file changed, 47 insertions(+), 10 deletions(-)
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/internals.h |  6 ++++
  target/arm/cpu64.c     | 64 +++---------------------------------------
  target/arm/cpu_tcg.c   | 59 ++++++++++++++++++++++++++++++++++++++
 files changed, 69 insertions(+), 60 deletions(-)
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/hw/misc/max111x.c
-+++ b/target/arm/internals.h
++++ b/hw/misc/max111x.c
-@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
+@@ -XXX,XX +XXX,XX @@
- int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
+ #include "hw/ssi/ssi.h"
- #endif
+ #include "migration/vmstate.h"
+ #include "qemu/module.h"
-+#ifdef CONFIG_USER_ONLY
++#include "hw/qdev-properties.h"
-+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
-+#else
+ typedef struct {
-+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+     SSISlave parent_obj;
-+#endif
      qemu_irq interrupt;
 +    /* Values of inputs at system reset (settable by QOM property) */
 +    uint8_t reset_input[8];
 +
- #endif
+     uint8_t tb1, rb2, rb3;
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+     int cycle;
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
-+++ b/target/arm/cpu64.c
+     qdev_init_gpio_out(dev, &s->interrupt, 1);
-@@ -XXX,XX +XXX,XX @@
- #include "hvf_arm.h"
+     s->inputs = inputs;
- #include "qapi/visitor.h"
+-    /* TODO: add a user interface for setting these */
- #include "hw/qdev-properties.h"
+-    s->input[0] = 0xf0;
--#include "cpregs.h"
+-    s->input[1] = 0xe0;
-+#include "internals.h"
+-    s->input[2] = 0xd0;
+-    s->input[3] = 0xc0;
+-    s->input[4] = 0xb0;
--#ifndef CONFIG_USER_ONLY
+-    s->input[5] = 0xa0;
--static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+-    s->input[6] = 0x90;
--{
+-    s->input[7] = 0x80;
--    ARMCPU *cpu = env_archcpu(env);
+-    s->com = 0;
--
--    /* Number of cores is in [25:24]; otherwise we RAZ */
+     vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
--    return (cpu->core_count - 1) << 24;
+                      &vmstate_max111x, s);
--}
+@@ -XXX,XX +XXX,XX @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value)
--#endif
+     s->input[line] = value;
 -
 -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
 -#ifndef CONFIG_USER_ONLY
 -    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
 -      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
 -      .writefn = arm_cp_write_ignore },
 -    { .name = "L2CTLR",
 -      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
 -      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
 -      .writefn = arm_cp_write_ignore },
 -#endif
 -    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2ECTLR",
 -      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUACTLR",
 -      .cp = 15, .opc1 = 0, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUECTLR",
 -      .cp = 15, .opc1 = 1, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUMERRSR",
 -      .cp = 15, .opc1 = 2, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2MERRSR",
 -      .cp = 15, .opc1 = 3, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -};
 -
  static void aarch64_a57_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
      cpu->gic_num_lrs = 4;
      cpu->gic_vpribits = 5;
      cpu->gic_vprebits = 5;
 -    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
- static void aarch64_a53_initfn(Object *obj)
++static void max111x_reset(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
      cpu->gic_num_lrs = 4;
      cpu->gic_vpribits = 5;
      cpu->gic_vprebits = 5;
 -    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
  static void aarch64_a72_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      cpu->gic_num_lrs = 4;
      cpu->gic_vpribits = 5;
      cpu->gic_vprebits = 5;
 -    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #endif
  #include "cpregs.h"
 +#ifndef CONFIG_USER_ONLY
 +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
-+    ARMCPU *cpu = env_archcpu(env);
++    MAX111xState *s = MAX_111X(dev);
 +    int i;
 +
-+    /* Number of cores is in [25:24]; otherwise we RAZ */
++    for (i = 0; i < s->inputs; i++) {
-+    return (cpu->core_count - 1) << 24;
++        s->input[i] = s->reset_input[i];
 +    }
 +    s->com = 0;
 +    s->tb1 = 0;
 +    s->rb2 = 0;
 +    s->rb3 = 0;
 +    s->cycle = 0;
 +}
 +
-+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
++static Property max1110_properties[] = {
-+    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
++    /* Reset values for ADC inputs */
-+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
++    DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
-+      .access = PL1_RW, .readfn = l2ctlr_read,
++    DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
-+      .writefn = arm_cp_write_ignore },
++    DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
-+    { .name = "L2CTLR",
++    DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
-+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
++    DEFINE_PROP_END_OF_LIST(),
 +      .access = PL1_RW, .readfn = l2ctlr_read,
 +      .writefn = arm_cp_write_ignore },
 +    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2ECTLR",
 +      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUACTLR",
 +      .cp = 15, .opc1 = 0, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUECTLR",
 +      .cp = 15, .opc1 = 1, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUMERRSR",
 +      .cp = 15, .opc1 = 2, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2MERRSR",
 +      .cp = 15, .opc1 = 3, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +};
 +
-+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
++static Property max1111_properties[] = {
-+{
++    /* Reset values for ADC inputs */
-+    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
++    DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
-+}
++    DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
-+#endif /* !CONFIG_USER_ONLY */
++    DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
 +    DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
 +    DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0),
 +    DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0),
 +    DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90),
 +    DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
- /* CPU models. These are not needed for the AArch64 linux-user build. */
+ static void max111x_class_init(ObjectClass *klass, void *data)
- #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+ {
+     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
      k->transfer = max111x_transfer;
 +    dc->reset = max111x_reset;
  }
  static const TypeInfo max111x_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max111x_info = {
  static void max1110_class_init(ObjectClass *klass, void *data)
  {
      SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
      k->realize = max1110_realize;
 +    device_class_set_props(dc, max1110_properties);
  }
  static const TypeInfo max1110_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max1110_info = {
  static void max1111_class_init(ObjectClass *klass, void *data)
  {
      SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
      k->realize = max1111_realize;
 +    device_class_set_props(dc, max1111_properties);
  }
  static const TypeInfo max1111_info = {
 --
-.25.1
+.20.1

-[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
+[PULL 23/34] hw/misc/max111x: Don't use vmstate_register()
-From: Richard Henderson <richard.henderson@linaro.org>
+The max111x is a proper qdev device; we can use dc->vmsd rather than
 directly calling vmstate_register().
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+It's possible that this is a migration compat break, but the only
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+boards that use this device are the spitz-family ('akita', 'borzoi',
-Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
+'spitz', 'terrier').
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-8-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ hw/misc/max111x.c | 3 +--
- target/arm/cpu64.c            | 1 +
+file changed, 1 insertion(+), 2 deletions(-)
  target/arm/cpu_tcg.c          | 1 +
 files changed, 3 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/hw/misc/max111x.c
-+++ b/docs/system/arm/emulation.rst
++++ b/hw/misc/max111x.c
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
- - FEAT_PMULL (PMULL, PMULL2 instructions)
- - FEAT_PMUv3p1 (PMU Extensions v3.1)
+     s->inputs = inputs;
- - FEAT_PMUv3p4 (PMU Extensions v3.4)
-+- FEAT_RAS (Reliability, availability, and serviceability)
+-    vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
- - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
+-                     &vmstate_max111x, s);
- - FEAT_RNG (Random number generator)
+     return 0;
- - FEAT_SB (Speculation Barrier)
+ }
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static void max111x_class_init(ObjectClass *klass, void *data)
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
+     k->transfer = max111x_transfer;
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+     dc->reset = max111x_reset;
-     t = cpu->isar.id_aa64pfr0;
++    dc->vmsd = &vmstate_max111x;
-     t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
+ }
-     t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
-+    t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1);       /* FEAT_RAS */
+ static const TypeInfo max111x_info = {
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
      t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
      t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
      t = cpu->isar.id_pfr0;
      t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
 +    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
      cpu->isar.id_pfr0 = t;
      t = cpu->isar.id_pfr2;
 --
-.25.1
+.20.1

-[PULL 25/32] target/arm: Define neoverse-n1
+[PULL 24/34] ssi: Add ssi_realize_and_unref()
-From: Richard Henderson <richard.henderson@linaro.org>
+Add an ssi_realize_and_unref(), for the benefit of callers
 who want to be able to create an SSI device, set QOM properties
 on it, and then do the realize-and-unref afterwards.
-Enable the n1 for virt and sbsa board use.
+The API works on the same principle as the recently added
 qdev_realize_and_undef(), sysbus_realize_and_undef(), etc.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-9-peter.maydell@linaro.org
 ---
- docs/system/arm/virt.rst |  1 +
+ include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++
- hw/arm/sbsa-ref.c        |  1 +
+ hw/ssi/ssi.c         |  7 ++++++-
- hw/arm/virt.c            |  1 +
+files changed, 32 insertions(+), 1 deletion(-)
  target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 files changed, 69 insertions(+)
-diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
+diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/virt.rst
+--- a/include/hw/ssi/ssi.h
-+++ b/docs/system/arm/virt.rst
++++ b/include/hw/ssi/ssi.h
-@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
+@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ssi_slave;
- - ``cortex-a76`` (64-bit)
+ }
- - ``a64fx`` (64-bit)
- - ``host`` (with KVM only)
+ DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
-+- ``neoverse-n1`` (64-bit)
++/**
- - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
++ * ssi_realize_and_unref: realize and unref an SSI slave device
++ * @dev: SSI slave device to realize
- Note that the default is ``cortex-a15``, so for an AArch64 guest you must
++ * @bus: SSI bus to put it on
-diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
++ * @errp: error pointer
 + *
 + * Call 'realize' on @dev, put it on the specified @bus, and drop the
 + * reference to it. Errors are reported via @errp and by returning
 + * false.
 + *
 + * This function is useful if you have created @dev via qdev_new()
 + * (which takes a reference to the device it returns to you), so that
 + * you can set properties on it before realizing it. If you don't need
 + * to set properties then ssi_create_slave() is probably better (as it
 + * does the create, init and realize in one step).
 + *
 + * If you are embedding the SSI slave into another QOM device and
 + * initialized it via some variant on object_initialize_child() then
 + * do not use this function, because that family of functions arrange
 + * for the only reference to the child device to be held by the parent
 + * via the child<> property, and so the reference-count-drop done here
 + * would be incorrect.  (Instead you would want ssi_realize(), which
 + * doesn't currently exist but would be trivial to create if we had
 + * any code that wanted it.)
 + */
 +bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
  /* Master interface.  */
  SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
 diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/sbsa-ref.c
+--- a/hw/ssi/ssi.c
-+++ b/hw/arm/sbsa-ref.c
++++ b/hw/ssi/ssi.c
-@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo ssi_slave_info = {
-     ARM_CPU_TYPE_NAME("cortex-a57"),
+     .abstract = true,
      ARM_CPU_TYPE_NAME("cortex-a72"),
      ARM_CPU_TYPE_NAME("cortex-a76"),
 +    ARM_CPU_TYPE_NAME("neoverse-n1"),
      ARM_CPU_TYPE_NAME("max"),
  };
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
++bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
      ARM_CPU_TYPE_NAME("cortex-a72"),
      ARM_CPU_TYPE_NAME("cortex-a76"),
      ARM_CPU_TYPE_NAME("a64fx"),
 +    ARM_CPU_TYPE_NAME("neoverse-n1"),
      ARM_CPU_TYPE_NAME("host"),
      ARM_CPU_TYPE_NAME("max"),
  };
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
      cpu->isar.mvfr2 = 0x00000043;
  }
 +static void aarch64_neoverse_n1_initfn(Object *obj)
 +{
-+    ARMCPU *cpu = ARM_CPU(obj);
++    return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
 +
 +    cpu->dtb_compatible = "arm,neoverse-n1";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444c004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0c1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.23 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
 +
 +    /* From B2.98 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +}
 +
- void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+ DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
  {
-     /*
+     DeviceState *dev = qdev_new(name);
-@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
-     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
+-    qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal);
-     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
++    ssi_realize_and_unref(dev, bus, &error_fatal);
-     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+     return dev;
-+    { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
+ }
-     { .name = "max",                .initfn = aarch64_max_initfn },
  #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
      { .name = "host",               .initfn = aarch64_host_initfn },
 --
-.25.1
+.20.1

-New patch
+[PULL 25/34] hw/arm/spitz: Use max111x properties to set initial values
+Use the new max111x qdev properties to set the initial input
+values rather than calling max111x_set_input(); this means that
+on system reset the inputs will correctly return to their initial
+values.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200628142429.17111-10-peter.maydell@linaro.org
+---
+ hw/arm/spitz.c | 11 +++++++----
+file changed, 7 insertions(+), 4 deletions(-)
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
+                           qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
+     bus = qdev_get_child_bus(sms->mux, "ssi2");
+-    sms->max1111 = ssi_create_slave(bus, "max1111");
++    sms->max1111 = qdev_new("max1111");
+     max1111 = sms->max1111;
+-    max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
+-    max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
+-    max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
++    qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
++                        SPITZ_BATTERY_VOLT);
++    qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
++    qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */,
++                        SPITZ_CHARGEON_ACIN);
++    ssi_realize_and_unref(sms->max1111, bus, &error_fatal);
+     qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
+                         qdev_get_gpio_in(sms->mux, 0));
+--
+.20.1

-[PULL 09/32] target/arm: Split out aa32_max_features
+[PULL 26/34] hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
-From: Richard Henderson <richard.henderson@linaro.org>
+The max111x ADC device model allows other code to set the level on
 the 8 ADC inputs using the max111x_set_input() function.  Replace
 this with generic qdev GPIO inputs, which also allow inputs to be set
 to arbitrary values.
-Share the code to set AArch32 max features so that we no
+Using GPIO lines will make it easier for board code to wire things
-longer have code drift between qemu{-system,}-{arm,aarch64}.
+up, so that if device A wants to set the ADC input it doesn't need to
 have a direct pointer to the max111x but can just set that value on
 its output GPIO, which is then wired up by the board to the
 appropriate max111x input.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-11-peter.maydell@linaro.org
 ---
- target/arm/internals.h |   2 +
+ include/hw/ssi/ssi.h |  3 ---
- target/arm/cpu64.c     |  50 +-----------------
+ hw/arm/spitz.c       |  9 +++++----
- target/arm/cpu_tcg.c   | 114 ++++++++++++++++++++++-------------------
+ hw/misc/max111x.c    | 16 +++++++++-------
-files changed, 65 insertions(+), 101 deletions(-)
+files changed, 14 insertions(+), 14 deletions(-)
-diff --git a/target/arm/internals.h b/target/arm/internals.h
+diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/include/hw/ssi/ssi.h
-+++ b/target/arm/internals.h
++++ b/include/hw/ssi/ssi.h
-@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+@@ -XXX,XX +XXX,XX @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
- void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
  uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
 -/* max111x.c */
 -void max111x_set_input(DeviceState *dev, int line, uint8_t value);
 -
  #endif
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
-+void aa32_max_features(ARMCPU *cpu);
+index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/spitz.c
 +++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  static void spitz_adc_temp_on(void *opaque, int line, int level)
  {
 +    int batt_temp;
 +
- #endif
+     if (!max1111)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+         return;
 -    if (level)
 -        max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
 -    else
 -        max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
 +    batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
 +
 +    qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
  }
  static void corgi_ssp_realize(SSISlave *d, Error **errp)
 diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/hw/misc/max111x.c
-+++ b/target/arm/cpu64.c
++++ b/hw/misc/max111x.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_max111x = {
- {
+     }
-     ARMCPU *cpu = ARM_CPU(obj);
+ };
-     uint64_t t;
--    uint32_t u;
++static void max111x_input_set(void *opaque, int line, int value)
++{
-     if (kvm_enabled() || hvf_enabled()) {
++    MAX111xState *s = MAX_111X(opaque);
          /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
      cpu->isar.id_aa64zfr0 = t;
 -    /* Replicate the same data to the 32-bit id registers.  */
 -    u = cpu->isar.id_isar5;
 -    u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
 -    u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
 -    u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
 -    u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
 -    u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
 -    u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
 -    cpu->isar.id_isar5 = u;
 -
 -    u = cpu->isar.id_isar6;
 -    u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, DP, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, SB, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
 -    cpu->isar.id_isar6 = u;
 -
 -    u = cpu->isar.id_pfr0;
 -    u = FIELD_DP32(u, ID_PFR0, DIT, 1);
 -    cpu->isar.id_pfr0 = u;
 -
 -    u = cpu->isar.id_pfr2;
 -    u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
 -    cpu->isar.id_pfr2 = u;
 -
 -    u = cpu->isar.id_mmfr3;
 -    u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
 -    cpu->isar.id_mmfr3 = u;
 -
 -    u = cpu->isar.id_mmfr4;
 -    u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -    u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -    u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
 -    u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
 -    cpu->isar.id_mmfr4 = u;
 -
      t = cpu->isar.id_aa64dfr0;
      t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
      cpu->isar.id_aa64dfr0 = t;
 -    u = cpu->isar.id_dfr0;
 -    u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
 -    cpu->isar.id_dfr0 = u;
 -
 -    u = cpu->isar.mvfr1;
 -    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
 -    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
 -    cpu->isar.mvfr1 = u;
 +    /* Replicate the same data to the 32-bit id registers.  */
 +    aa32_max_features(cpu);
  #ifdef CONFIG_USER_ONLY
      /*
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #endif
  #include "cpregs.h"
 +
-+/* Share AArch32 -cpu max features with AArch64. */
++    assert(line >= 0 && line < s->inputs);
-+void aa32_max_features(ARMCPU *cpu)
++    s->input[line] = value;
 +{
 +    uint32_t t;
 +
 +    /* Add additional features supported by QEMU */
 +    t = cpu->isar.id_isar5;
 +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 +    cpu->isar.id_isar5 = t;
 +
 +    t = cpu->isar.id_isar6;
 +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 +    cpu->isar.id_isar6 = t;
 +
 +    t = cpu->isar.mvfr1;
 +    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 +    cpu->isar.mvfr1 = t;
 +
 +    t = cpu->isar.mvfr2;
 +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 +    cpu->isar.mvfr2 = t;
 +
 +    t = cpu->isar.id_mmfr3;
 +    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +    cpu->isar.id_mmfr3 = t;
 +
 +    t = cpu->isar.id_mmfr4;
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +    cpu->isar.id_mmfr4 = t;
 +
 +    t = cpu->isar.id_pfr0;
 +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 +    cpu->isar.id_pfr0 = t;
 +
 +    t = cpu->isar.id_pfr2;
 +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 +    cpu->isar.id_pfr2 = t;
 +
 +    t = cpu->isar.id_dfr0;
 +    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
 +    cpu->isar.id_dfr0 = t;
 +}
 +
- #ifndef CONFIG_USER_ONLY
+ static int max111x_init(SSISlave *d, int inputs)
  static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
-@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
+     DeviceState *dev = DEVICE(d);
- static void arm_max_initfn(Object *obj)
+     MAX111xState *s = MAX_111X(dev);
      qdev_init_gpio_out(dev, &s->interrupt, 1);
 +    qdev_init_gpio_in(dev, max111x_input_set, inputs);
      s->inputs = inputs;
@@ -XXX,XX +XXX,XX @@ static void max1111_realize(SSISlave *dev, Error **errp)
      max111x_init(dev, 4);
  }
 -void max111x_set_input(DeviceState *dev, int line, uint8_t value)
 -{
 -    MAX111xState *s = MAX_111X(dev);
 -    assert(line >= 0 && line < s->inputs);
 -    s->input[line] = value;
 -}
 -
  static void max111x_reset(DeviceState *dev)
  {
-     ARMCPU *cpu = ARM_CPU(obj);
+     MAX111xState *s = MAX_111X(dev);
 -    uint32_t t;
      /* aarch64_a57_initfn, advertising none of the aarch64 features */
      cpu->dtb_compatible = "arm,cortex-a57";
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
      cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
      define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -    /* Add additional features supported by QEMU */
 -    t = cpu->isar.id_isar5;
 -    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 -    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 -    cpu->isar.id_isar5 = t;
 -
 -    t = cpu->isar.id_isar6;
 -    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 -    cpu->isar.id_isar6 = t;
 -
 -    t = cpu->isar.mvfr1;
 -    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 -    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 -    cpu->isar.mvfr1 = t;
 -
 -    t = cpu->isar.mvfr2;
 -    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 -    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 -    cpu->isar.mvfr2 = t;
 -
 -    t = cpu->isar.id_mmfr3;
 -    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 -    cpu->isar.id_mmfr3 = t;
 -
 -    t = cpu->isar.id_mmfr4;
 -    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 -    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 -    cpu->isar.id_mmfr4 = t;
 -
 -    t = cpu->isar.id_pfr0;
 -    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 -    cpu->isar.id_pfr0 = t;
 -
 -    t = cpu->isar.id_pfr2;
 -    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 -    cpu->isar.id_pfr2 = t;
 -
 -    t = cpu->isar.id_dfr0;
 -    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
 -    cpu->isar.id_dfr0 = t;
 +    aa32_max_features(cpu);
  #ifdef CONFIG_USER_ONLY
      /*
 --
-.25.1
+.20.1

-[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
+[PULL 27/34] hw/misc/max111x: Create header file for documentation, TYPE_ macros
-From: Leif Lindholm <quic_llindhol@quicinc.com>
+Create a header file for the hw/misc/max111x device, in the
 usual modern style for QOM devices:
  * definition of the TYPE_ constants and macros
  * definition of the device's state struct so that it can
    be embedded in other structs if desired
  * documentation of the interface
-NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
+This allows us to use TYPE_MAX_1111 in the spitz.c code rather
-separate infrastructure for a transitional period. We've now switched
+than the string "max1111".
 over to contributing as Qualcomm Innovation Center (quicinc), so update
 my email address to reflect this.
-Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
 Cc: Leif Lindholm <leif@nuviainc.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-[Fixed commit message typo]
+Message-id: 20200628142429.17111-12-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- .mailmap    | 3 ++-
+ include/hw/misc/max111x.h | 56 +++++++++++++++++++++++++++++++++++++++
- MAINTAINERS | 2 +-
+ hw/arm/spitz.c            |  3 ++-
-files changed, 3 insertions(+), 2 deletions(-)
+ hw/misc/max111x.c         | 24 +----------------
  MAINTAINERS               |  1 +
 files changed, 60 insertions(+), 24 deletions(-)
  create mode 100644 include/hw/misc/max111x.h
-diff --git a/.mailmap b/.mailmap
+diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/max111x.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Maxim MAX1110/1111 ADC chip emulation.
 + *
 + * Copyright (c) 2006 Openedhand Ltd.
 + * Written by Andrzej Zaborowski <balrog@zabor.org>
 + *
 + * This code is licensed under the GNU GPLv2.
 + *
 + * Contributions after 2012-01-13 are licensed under the terms of the
 + * GNU GPL, version 2 or (at your option) any later version.
 + */
 +
 +#ifndef HW_MISC_MAX111X_H
 +#define HW_MISC_MAX111X_H
 +
 +#include "hw/ssi/ssi.h"
 +
 +/*
 + * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
 + * is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
 + * 8-bit ADC channels.
 + *
 + * QEMU interface:
 + *  + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
 + *    of each ADC input, as an unsigned 8-bit value
 + *  + GPIO output 0: interrupt line
 + *  + Properties "input0" to "input3" (max1110) or "input0" to "input7"
 + *    (max1111): initial reset values for ADC inputs.
 + *
 + * Known bugs:
 + *  + the interrupt line is not correctly implemented, and will never
 + *    be lowered once it has been asserted.
 + */
 +typedef struct {
 +    SSISlave parent_obj;
 +
 +    qemu_irq interrupt;
 +    /* Values of inputs at system reset (settable by QOM property) */
 +    uint8_t reset_input[8];
 +
 +    uint8_t tb1, rb2, rb3;
 +    int cycle;
 +
 +    uint8_t input[8];
 +    int inputs, com;
 +} MAX111xState;
 +
 +#define TYPE_MAX_111X "max111x"
 +
 +#define MAX_111X(obj) \
 +    OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
 +
 +#define TYPE_MAX_1110 "max1110"
 +#define TYPE_MAX_1111 "max1111"
 +
 +#endif
 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
---- a/.mailmap
+--- a/hw/arm/spitz.c
-+++ b/.mailmap
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
+@@ -XXX,XX +XXX,XX @@
- Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
+ #include "audio/audio.h"
- Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
+ #include "hw/boards.h"
- James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
+ #include "hw/sysbus.h"
--Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
++#include "hw/misc/max111x.h"
-+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
+ #include "migration/vmstate.h"
-+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
+ #include "exec/address-spaces.h"
- Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
+ #include "cpu.h"
- Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
+@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
- Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
+                           qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
      bus = qdev_get_child_bus(sms->mux, "ssi2");
 -    sms->max1111 = qdev_new("max1111");
 +    sms->max1111 = qdev_new(TYPE_MAX_1111);
      max1111 = sms->max1111;
      qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
                          SPITZ_BATTERY_VOLT);
 diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/max111x.c
 +++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
 +#include "hw/misc/max111x.h"
  #include "hw/irq.h"
 -#include "hw/ssi/ssi.h"
  #include "migration/vmstate.h"
  #include "qemu/module.h"
  #include "hw/qdev-properties.h"
 -typedef struct {
 -    SSISlave parent_obj;
 -
 -    qemu_irq interrupt;
 -    /* Values of inputs at system reset (settable by QOM property) */
 -    uint8_t reset_input[8];
 -
 -    uint8_t tb1, rb2, rb3;
 -    int cycle;
 -
 -    uint8_t input[8];
 -    int inputs, com;
 -} MAX111xState;
 -
 -#define TYPE_MAX_111X "max111x"
 -
 -#define MAX_111X(obj) \
 -    OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
 -
 -#define TYPE_MAX_1110 "max1110"
 -#define TYPE_MAX_1111 "max1111"
 -
  /* Control-byte bitfields */
  #define CB_PD0        (1 << 0)
  #define CB_PD1        (1 << 1)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
+@@ -XXX,XX +XXX,XX @@ F: hw/gpio/max7310.c
- SBSA-REF
+ F: hw/gpio/zaurus.c
- M: Radoslaw Biernacki <rad@semihalf.com>
+ F: hw/misc/mst_fpga.c
- M: Peter Maydell <peter.maydell@linaro.org>
+ F: hw/misc/max111x.c
--R: Leif Lindholm <leif@nuviainc.com>
++F: include/hw/misc/max111x.h
-+R: Leif Lindholm <quic_llindhol@quicinc.com>
+ F: include/hw/arm/pxa.h
- L: qemu-arm@nongnu.org
+ F: include/hw/arm/sharpsl.h
- S: Maintained
+ F: include/hw/display/tc6393xb.h
  F: hw/arm/sbsa-ref.c
 --
-.25.1
+.20.1

-[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
+[PULL 28/34] hw/arm/spitz: Encapsulate misc GPIO handling in a device
-From: Richard Henderson <richard.henderson@linaro.org>
+Currently we have a free-floating set of IRQs and a function
+spitz_out_switch() which handle some miscellaneous GPIO lines for the
-This register is present for either VHE or Debugv8p2.
+spitz board.  Encapsulate this behaviour in a simple QOM device.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+At this point we can finally remove the 'max1111' global, because the
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+ADC battery-temperature value is now handled by the misc-gpio device
-Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
+writing the value to its outbound "adc-temp" GPIO, which the board
 code wires up to the appropriate inbound GPIO line on the max1111.
 This commit also fixes Coverity issue CID 1421913 (which pointed out
 that the 'outsignals' in spitz_scoop_gpio_setup() were leaked),
 because it removes the use of the qemu_allocate_irqs() API from this
 code entirely.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-13-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 15 +++++++++++----
+ hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++----------------
-file changed, 11 insertions(+), 4 deletions(-)
+file changed, 87 insertions(+), 42 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/spitz.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
+@@ -XXX,XX +XXX,XX @@ typedef struct {
-       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+     DeviceState *max1111;
      DeviceState *scp0;
      DeviceState *scp1;
 +    DeviceState *misc_gpio;
  } SpitzMachineState;
  #define TYPE_SPITZ_MACHINE "spitz-common"
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
  #define SPITZ_GPIO_MAX1111_CS   20
  #define SPITZ_GPIO_TP_INT       11
 -static DeviceState *max1111;
 -
  /* "Demux" the signal based on current chipselect */
  typedef struct {
      SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  #define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
  #define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
 -static void spitz_adc_temp_on(void *opaque, int line, int level)
 -{
 -    int batt_temp;
 -
 -    if (!max1111)
 -        return;
 -
 -    batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
 -
 -    qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
 -}
 -
  static void corgi_ssp_realize(SSISlave *d, Error **errp)
  {
      DeviceState *dev = DEVICE(d);
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
      bus = qdev_get_child_bus(sms->mux, "ssi2");
      sms->max1111 = qdev_new(TYPE_MAX_1111);
 -    max1111 = sms->max1111;
      qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
                          SPITZ_BATTERY_VOLT);
      qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
@@ -XXX,XX +XXX,XX @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu)
  /* Other peripherals */
 -static void spitz_out_switch(void *opaque, int line, int level)
 +/*
 + * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards.
 + *
 + * QEMU interface:
 + *  + named GPIO inputs "green-led", "orange-led", "charging", "discharging":
 + *    these currently just print messages that the line has been signalled
 + *  + named GPIO input "adc-temp-on": set to cause the battery-temperature
 + *    value to be passed to the max111x ADC
 + *  + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
 + */
 +#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
 +#define SPITZ_MISC_GPIO(obj) \
 +    OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
 +
 +typedef struct SpitzMiscGPIOState {
 +    SysBusDevice parent_obj;
 +
 +    qemu_irq adc_value;
 +} SpitzMiscGPIOState;
 +
 +static void spitz_misc_charging(void *opaque, int n, int level)
  {
 -    switch (line) {
 -    case 0:
 -        zaurus_printf("Charging %s.\n", level ? "off" : "on");
 -        break;
 -    case 1:
 -        zaurus_printf("Discharging %s.\n", level ? "on" : "off");
 -        break;
 -    case 2:
 -        zaurus_printf("Green LED %s.\n", level ? "on" : "off");
 -        break;
 -    case 3:
 -        zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
 -        break;
 -    case 6:
 -        spitz_adc_temp_on(opaque, line, level);
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 +    zaurus_printf("Charging %s.\n", level ? "off" : "on");
 +}
 +
 +static void spitz_misc_discharging(void *opaque, int n, int level)
 +{
 +    zaurus_printf("Discharging %s.\n", level ? "off" : "on");
 +}
 +
 +static void spitz_misc_green_led(void *opaque, int n, int level)
 +{
 +    zaurus_printf("Green LED %s.\n", level ? "off" : "on");
 +}
 +
 +static void spitz_misc_orange_led(void *opaque, int n, int level)
 +{
 +    zaurus_printf("Orange LED %s.\n", level ? "off" : "on");
 +}
 +
 +static void spitz_misc_adc_temp(void *opaque, int n, int level)
 +{
 +    SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque);
 +    int batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
 +
 +    qemu_set_irq(s->adc_value, batt_temp);
 +}
 +
 +static void spitz_misc_gpio_init(Object *obj)
 +{
 +    SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj);
 +    DeviceState *dev = DEVICE(obj);
 +
 +    qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1);
 +    qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1);
 +    qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1);
 +    qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1);
 +    qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1);
 +
 +    qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1);
  }
  #define SPITZ_SCP_LED_GREEN             1
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
  static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
  {
 -    qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
 +    DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL);
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
 +    sms->misc_gpio = miscdev;
 +
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON,
 +                          qdev_get_gpio_in_named(miscdev, "charging", 0));
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B,
 +                          qdev_get_gpio_in_named(miscdev, "discharging", 0));
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN,
 +                          qdev_get_gpio_in_named(miscdev, "green-led", 0));
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE,
 +                          qdev_get_gpio_in_named(miscdev, "orange-led", 0));
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON,
 +                          qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0));
 +    qdev_connect_gpio_out_named(miscdev, "adc-temp", 0,
 +                                qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP));
      if (sms->scp1) {
          qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
          qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
                                qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
      }
 -
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
  }
  #define SPITZ_GPIO_HSYNC                22
@@ -XXX,XX +XXX,XX @@ static const TypeInfo spitz_lcdtg_info = {
      .class_init    = spitz_lcdtg_class_init,
  };
-+static const ARMCPRegInfo contextidr_el2 = {
++static const TypeInfo spitz_misc_gpio_info = {
-+    .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
++    .name = TYPE_SPITZ_MISC_GPIO,
-+    .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
++    .parent = TYPE_SYS_BUS_DEVICE,
-+    .access = PL2_RW,
++    .instance_size = sizeof(SpitzMiscGPIOState),
-+    .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
++    .instance_init = spitz_misc_gpio_init,
 +    /*
 +     * No class_init required: device has no internal state so does not
 +     * need to set up reset or vmstate, and does not have a realize method.
 +     */
 +};
 +
- static const ARMCPRegInfo vhe_reginfo[] = {
+ static void spitz_register_types(void)
--    { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+ {
--      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+     type_register_static(&corgi_ssp_info);
--      .access = PL2_RW,
+     type_register_static(&spitz_lcdtg_info);
--      .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
+     type_register_static(&spitz_keyboard_info);
-     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
+     type_register_static(&sl_nand_info);
-       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
++    type_register_static(&spitz_misc_gpio_info);
-       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
+ }
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
+ type_init(spitz_register_types)
      }
 +    if (cpu_isar_feature(aa64_vh, cpu) ||
 +        cpu_isar_feature(aa64_debugv8p2, cpu)) {
 +        define_one_arm_cp_reg(cpu, &contextidr_el2);
 +    }
      if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
          define_arm_cp_regs(cpu, vhe_reginfo);
      }
 --
-.25.1
+.20.1

-[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
+[PULL 29/34] hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
-From: Richard Henderson <richard.henderson@linaro.org>
+Instead of logging guest accesses to invalid register offsets in this
 device using zaurus_printf() (which just prints to stderr), use the
 usual qemu_log_mask(LOG_GUEST_ERROR,...).
-Update the legacy feature names to the current names.
+Since this was the only use of the zaurus_printf() macro outside
-Provide feature names for id changes that were not marked.
+spitz.c, we can move the definition of that macro from sharpsl.h
-Sort the field updates into increasing bitfield order.
+to spitz.c.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-14-peter.maydell@linaro.org
 ---
- target/arm/cpu64.c   | 100 +++++++++++++++++++++----------------------
+ include/hw/arm/sharpsl.h |  3 ---
- target/arm/cpu_tcg.c |  48 ++++++++++-----------
+ hw/arm/spitz.c           |  3 +++
-files changed, 74 insertions(+), 74 deletions(-)
+ hw/gpio/zaurus.c         | 12 +++++++-----
 files changed, 10 insertions(+), 8 deletions(-)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/include/hw/arm/sharpsl.h
-+++ b/target/arm/cpu64.c
++++ b/include/hw/arm/sharpsl.h
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@
-     cpu->midr = t;
+ #include "exec/hwaddr.h"
-     t = cpu->isar.id_aa64isar0;
--    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
+-#define zaurus_printf(format, ...)    \
--    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
+-    fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
--    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
+-
-+    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
+ /* zaurus.c */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
-+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
+ #define SL_PXA_PARAM_BASE    0xa0000a00
-     t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 -    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
 -    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
 -    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
 +    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
      cpu->isar.id_aa64isar0 = t;
      t = cpu->isar.id_aa64isar1;
 -    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
 -    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
 +    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
      cpu->isar.id_aa64isar1 = t;
      t = cpu->isar.id_aa64pfr0;
 +    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
 +    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
      cpu->isar.id_aa64pfr0 = t;
      t = cpu->isar.id_aa64pfr1;
 -    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
 +    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
 +    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
      /*
       * Begin with full support for MTE. This will be downgraded to MTE=0
       * during realize if the board provides no tag memory, much like
       * we do for EL2 with the virtualization=on property.
       */
 -    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
 +    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
      cpu->isar.id_aa64pfr1 = t;
      t = cpu->isar.id_aa64mmfr0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      cpu->isar.id_aa64mmfr0 = t;
      t = cpu->isar.id_aa64mmfr1;
 -    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
      cpu->isar.id_aa64mmfr1 = t;
      t = cpu->isar.id_aa64mmfr2;
 -    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
      cpu->isar.id_aa64mmfr2 = t;
      t = cpu->isar.id_aa64zfr0;
      t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
 -    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
 +    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
      cpu->isar.id_aa64zfr0 = t;
      t = cpu->isar.id_aa64dfr0;
 -    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
 +    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
      cpu->isar.id_aa64dfr0 = t;
      /* Replicate the same data to the 32-bit id registers.  */
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
+--- a/hw/arm/spitz.c
-+++ b/target/arm/cpu_tcg.c
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+ #define SPITZ_MACHINE_CLASS(klass) \
-     /* Add additional features supported by QEMU */
+     OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
-     t = cpu->isar.id_isar5;
--    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
++#define zaurus_printf(format, ...)                              \
--    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
++    fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
--    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
++
-+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
+ #undef REG_FMT
-+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
+ #define REG_FMT                         "0x%02lx"
-+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
-     t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c
--    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+index XXXXXXX..XXXXXXX 100644
--    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+--- a/hw/gpio/zaurus.c
-+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
++++ b/hw/gpio/zaurus.c
-+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
+@@ -XXX,XX +XXX,XX @@
-     cpu->isar.id_isar5 = t;
+ #include "hw/sysbus.h"
+ #include "migration/vmstate.h"
-     t = cpu->isar.id_isar6;
+ #include "qemu/module.h"
--    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+-
--    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+-#undef REG_FMT
--    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+-#define REG_FMT            "0x%02lx"
--    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
++#include "qemu/log.h"
--    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
--    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+ /* SCOOP devices */
--    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
+@@ -XXX,XX +XXX,XX @@ static uint64_t scoop_read(void *opaque, hwaddr addr,
-+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
+     case SCOOP_GPRR:
-+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
+         return s->gpio_level;
-+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
+     default:
-+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
+-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
-+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
++        qemu_log_mask(LOG_GUEST_ERROR,
-+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
++                      "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n",
-     cpu->isar.id_isar6 = t;
++                      addr);
+     }
-     t = cpu->isar.mvfr1;
--    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+     return 0;
--    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+@@ -XXX,XX +XXX,XX @@ static void scoop_write(void *opaque, hwaddr addr,
-+    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
+         scoop_gpio_handler_update(s);
-+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
+         break;
-     cpu->isar.mvfr1 = t;
+     default:
+-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
-     t = cpu->isar.mvfr2;
++        qemu_log_mask(LOG_GUEST_ERROR,
--    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
++                      "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n",
--    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
++                      addr);
-+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
+     }
 +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
      cpu->isar.mvfr2 = t;
      t = cpu->isar.id_mmfr3;
 -    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
      cpu->isar.id_mmfr3 = t;
      t = cpu->isar.id_mmfr4;
 -    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 -    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
 +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
 +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
      cpu->isar.id_mmfr4 = t;
      t = cpu->isar.id_pfr0;
 -    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
      cpu->isar.id_pfr0 = t;
      t = cpu->isar.id_pfr2;
 -    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
      cpu->isar.id_pfr2 = t;
      t = cpu->isar.id_dfr0;
 -    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
 +    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
      cpu->isar.id_dfr0 = t;
  }
 --
-.25.1
+.20.1

-New patch
+[PULL 30/34] hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
+Instead of logging guest accesses to invalid register offsets in the
+Spitz flash device with zaurus_printf() (which just prints to stderr),
+use the usual qemu_log_mask(LOG_GUEST_ERROR,...).
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-15-peter.maydell@linaro.org
+---
+ hw/arm/spitz.c | 12 +++++++-----
+file changed, 7 insertions(+), 5 deletions(-)
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/ssi/ssi.h"
+ #include "hw/block/flash.h"
+ #include "qemu/timer.h"
++#include "qemu/log.h"
+ #include "hw/arm/sharpsl.h"
+ #include "ui/console.h"
+ #include "hw/audio/wm8750.h"
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+ #define zaurus_printf(format, ...)                              \
+     fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
+-#undef REG_FMT
+-#define REG_FMT                         "0x%02lx"
+-
+ /* Spitz Flash */
+ #define FLASH_BASE              0x0c000000
+ #define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
+@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
+         return ecc_digest(&s->ecc, nand_getio(s->nand));
+     default:
+-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n",
++                      addr);
+     }
+     return 0;
+ }
+@@ -XXX,XX +XXX,XX @@ static void sl_write(void *opaque, hwaddr addr,
+         break;
+     default:
+-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n",
++                      addr);
+     }
+ }
+--
+.20.1

-[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
+[PULL 31/34] hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
-From: Richard Henderson <richard.henderson@linaro.org>
+Instead of using printf() for logging guest accesses to invalid
 register offsets in the pxa2xx PIC device, use the usual
 qemu_log_mask(LOG_GUEST_ERROR,...).
-This extension concerns changes to the External Debug interface,
+This was the only user of the REG_FMT macro in pxa.h, so we can
-with Secure and Non-secure access to the debug registers, and all
+remove that.
 of it is outside the scope of QEMU.  Indicating support for this
 is mandatory with FEAT_SEL2, which we do implement.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-16-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ include/hw/arm/pxa.h | 1 -
- target/arm/cpu64.c            | 2 +-
+ hw/arm/pxa2xx_pic.c  | 9 +++++++--
- target/arm/cpu_tcg.c          | 4 ++--
+files changed, 7 insertions(+), 3 deletions(-)
 files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/include/hw/arm/pxa.h
-+++ b/docs/system/arm/emulation.rst
++++ b/include/hw/arm/pxa.h
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
- - FEAT_DIT (Data Independent Timing instructions)
+ };
- - FEAT_DPB (DC CVAP instruction)
- - FEAT_Debugv8p2 (Debug changes for v8.2)
+ # define PA_FMT            "0x%08lx"
-+- FEAT_Debugv8p4 (Debug changes for v8.4)
+-# define REG_FMT        "0x" TARGET_FMT_plx
- - FEAT_DotProd (Advanced SIMD dot product instructions)
- - FEAT_FCMA (Floating-point complex number instructions)
+ PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
- - FEAT_FHM (Floating-point half-precision multiplication instructions)
+                          const char *revision);
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/hw/arm/pxa2xx_pic.c
-+++ b/target/arm/cpu64.c
++++ b/hw/arm/pxa2xx_pic.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@
-     cpu->isar.id_aa64zfr0 = t;
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
-     t = cpu->isar.id_aa64dfr0;
+ #include "qemu/module.h"
--    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8);  /* FEAT_Debugv8p2 */
++#include "qemu/log.h"
-+    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9);  /* FEAT_Debugv8p4 */
+ #include "cpu.h"
-     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
+ #include "hw/arm/pxa.h"
-     cpu->isar.id_aa64dfr0 = t;
+ #include "hw/sysbus.h"
+@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
+     case ICHP:    /* Highest Priority register */
-index XXXXXXX..XXXXXXX 100644
+         return pxa2xx_pic_highest(s);
---- a/target/arm/cpu_tcg.c
+     default:
-+++ b/target/arm/cpu_tcg.c
+-        printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
++        qemu_log_mask(LOG_GUEST_ERROR,
-     cpu->isar.id_pfr2 = t;
++                      "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
++                      "\n", offset);
-     t = cpu->isar.id_dfr0;
+         return 0;
--    t = FIELD_DP32(t, ID_DFR0, COPDBG, 8);        /* FEAT_Debugv8p2 */
+     }
 -    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8);       /* FEAT_Debugv8p2 */
 +    t = FIELD_DP32(t, ID_DFR0, COPDBG, 9);        /* FEAT_Debugv8p4 */
 +    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9);       /* FEAT_Debugv8p4 */
      t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
      cpu->isar.id_dfr0 = t;
  }
+@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
+         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
+         break;
+     default:
+-        printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "pxa2xx_pic_mem_write: bad register offset 0x%"
++                      HWADDR_PRIx "\n", offset);
+         return;
+     }
+     pxa2xx_pic_update(opaque);
 --
-.25.1
+.20.1

-[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
+[PULL 32/34] hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
-From: Richard Henderson <richard.henderson@linaro.org>
+The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the
 usual QOM TYPE and casting macros; provide and use them.
-The only portion of FEAT_Debugv8p2 that is relevant to QEMU
+In particular, we can safely use the QOM cast macros instead of
-is CONTEXTIDR_EL2, which is also conditionally implemented
+FROM_SSI_SLAVE() because in both cases the 'ssidev' field of
-with FEAT_VHE.  The rest of the debug extension concerns the
+the instance state struct is the first field in it.
 External debug interface, which is outside the scope of QEMU.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-17-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ hw/arm/spitz.c | 23 +++++++++++++++--------
- target/arm/cpu.c              | 1 +
+file changed, 15 insertions(+), 8 deletions(-)
  target/arm/cpu64.c            | 1 +
  target/arm/cpu_tcg.c          | 2 ++
 files changed, 5 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/hw/arm/spitz.c
-+++ b/docs/system/arm/emulation.rst
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
- - FEAT_BTI (Branch Target Identification)
+ #define LCDTG_PICTRL    0x06
- - FEAT_DIT (Data Independent Timing instructions)
+ #define LCDTG_POLCTRL   0x07
- - FEAT_DPB (DC CVAP instruction)
-+- FEAT_Debugv8p2 (Debug changes for v8.2)
++#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
- - FEAT_DotProd (Advanced SIMD dot product instructions)
++#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
- - FEAT_FCMA (Floating-point complex number instructions)
++
- - FEAT_FHM (Floating-point half-precision multiplication instructions)
+ typedef struct {
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+     SSISlave ssidev;
-index XXXXXXX..XXXXXXX 100644
+     uint32_t bl_intensity;
---- a/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_power(void *opaque, int line, int level)
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
-          * feature registers as well.
+ {
-          */
+-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
-         cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
++    SpitzLCDTG *s = SPITZ_LCDTG(dev);
-+        cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
+     int addr;
-         cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+     addr = value >> 5;
-                                            ID_AA64PFR0, EL3, 0);
+     value &= 0x1f;
-     }
+@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
+ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
---- a/target/arm/cpu64.c
+ {
-+++ b/target/arm/cpu64.c
+-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
++    SpitzLCDTG *s = SPITZ_LCDTG(ssi);
-     cpu->isar.id_aa64zfr0 = t;
+     DeviceState *dev = DEVICE(s);
-     t = cpu->isar.id_aa64dfr0;
+     s->bl_power = 0;
-+    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8);  /* FEAT_Debugv8p2 */
+@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
-     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
+ #define SPITZ_GPIO_MAX1111_CS   20
-     cpu->isar.id_aa64dfr0 = t;
+ #define SPITZ_GPIO_TP_INT       11
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
++#define TYPE_CORGI_SSP "corgi-ssp"
-index XXXXXXX..XXXXXXX 100644
++#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
---- a/target/arm/cpu_tcg.c
++
-+++ b/target/arm/cpu_tcg.c
+ /* "Demux" the signal based on current chipselect */
-@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+ typedef struct {
-     cpu->isar.id_pfr2 = t;
+     SSISlave ssidev;
+@@ -XXX,XX +XXX,XX @@ typedef struct {
-     t = cpu->isar.id_dfr0;
-+    t = FIELD_DP32(t, ID_DFR0, COPDBG, 8);        /* FEAT_Debugv8p2 */
+ static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
-+    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8);       /* FEAT_Debugv8p2 */
+ {
-     t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
+-    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
-     cpu->isar.id_dfr0 = t;
++    CorgiSSPState *s = CORGI_SSP(dev);
      int i;
      for (i = 0; i < 3; i++) {
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  static void corgi_ssp_realize(SSISlave *d, Error **errp)
  {
      DeviceState *dev = DEVICE(d);
 -    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d);
 +    CorgiSSPState *s = CORGI_SSP(d);
      qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
      s->bus[0] = ssi_create_bus(dev, "ssi0");
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
  {
      void *bus;
 -    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
 +    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
 +                                TYPE_CORGI_SSP);
      bus = qdev_get_child_bus(sms->mux, "ssi0");
 -    sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
 +    sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
      bus = qdev_get_child_bus(sms->mux, "ssi1");
      sms->ads7846 = ssi_create_slave(bus, "ads7846");
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data)
  }
+ static const TypeInfo corgi_ssp_info = {
+-    .name          = "corgi-ssp",
++    .name          = TYPE_CORGI_SSP,
+     .parent        = TYPE_SSI_SLAVE,
+     .instance_size = sizeof(CorgiSSPState),
+     .class_init    = corgi_ssp_class_init,
+@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
+ }
+ static const TypeInfo spitz_lcdtg_info = {
+-    .name          = "spitz-lcdtg",
++    .name          = TYPE_SPITZ_LCDTG,
+     .parent        = TYPE_SSI_SLAVE,
+     .instance_size = sizeof(SpitzLCDTG),
+     .class_init    = spitz_lcdtg_class_init,
 --
-.25.1
+.20.1

-[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
+[PULL 33/34] Replace uses of FROM_SSI_SLAVE() macro with QOM casts
-From: Gavin Shan <gshan@redhat.com>
+The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way
 to cast from an SSISlave* to the instance struct of a subtype of
 TYPE_SSI_SLAVE.  Switch to using the QOM cast macros instead, which
 have the same effect (by writing the QOM macros if the types were
 previously missing them.)
-When the PPTT table is built, the CPU topology is re-calculated, but
+(The FROM_SSI_SLAVE() macro allows the SSISlave member of the
-it's unecessary because the CPU topology has been populated in
+subtype's struct to be anywhere as long as it is named "ssidev",
-virt_possible_cpu_arch_ids() on arm/virt machine.
+whereas a QOM cast macro insists that it is the first thing in the
 subtype's struct.  This is true for all the types we convert here.)
-This reworks build_pptt() to avoid by reusing the existing IDs in
+This removes all the uses of FROM_SSI_SLAVE() so we can delete the
-ms->possible_cpus. Currently, the only user of build_pptt() is
+definition.
 arm/virt machine.
-Signed-off-by: Gavin Shan <gshan@redhat.com>
-Tested-by: Yanan Wang <wangyanan55@huawei.com>
-Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
-Acked-by: Igor Mammedov <imammedo@redhat.com>
-Acked-by: Michael S. Tsirkin <mst@redhat.com>
-Message-id: 20220503140304.855514-7-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-18-peter.maydell@linaro.org
 ---
- hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
+ include/hw/ssi/ssi.h |  2 --
-file changed, 48 insertions(+), 63 deletions(-)
+ hw/arm/z2.c          | 11 +++++++----
  hw/display/ads7846.c |  9 ++++++---
  hw/display/ssd0323.c | 10 +++++++---
  hw/sd/ssi-sd.c       |  4 ++--
 files changed, 22 insertions(+), 14 deletions(-)
-diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
+diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/acpi/aml-build.c
+--- a/include/hw/ssi/ssi.h
-+++ b/hw/acpi/aml-build.c
++++ b/include/hw/ssi/ssi.h
-@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
+@@ -XXX,XX +XXX,XX @@ struct SSISlave {
-                 const char *oem_id, const char *oem_table_id)
+     bool cs;
  };
 -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
 -
  extern const VMStateDescription vmstate_ssi_slave;
  #define VMSTATE_SSI_SLAVE(_field, _state) {                          \
 diff --git a/hw/arm/z2.c b/hw/arm/z2.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/z2.c
 +++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
      int pos;
  } ZipitLCD;
 +#define TYPE_ZIPIT_LCD "zipit-lcd"
 +#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD)
 +
  static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
  {
-     MachineClass *mc = MACHINE_GET_CLASS(ms);
+-    ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
--    GQueue *list = g_queue_new();
++    ZipitLCD *z = ZIPIT_LCD(dev);
--    guint pptt_start = table_data->len;
+     uint16_t val;
--    guint parent_offset;
+     if (z->selected) {
--    guint length, i;
+         z->buf[z->pos] = value & 0xff;
--    int uid = 0;
+@@ -XXX,XX +XXX,XX @@ static void z2_lcd_cs(void *opaque, int line, int level)
--    int socket;
-+    CPUArchIdList *cpus = ms->possible_cpus;
+ static void zipit_lcd_realize(SSISlave *dev, Error **errp)
-+    int64_t socket_id = -1, cluster_id = -1, core_id = -1;
+ {
-+    uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
+-    ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
-+    uint32_t pptt_start = table_data->len;
++    ZipitLCD *z = ZIPIT_LCD(dev);
-+    int n;
+     z->selected = 0;
-     AcpiTable table = { .sig = "PPTT", .rev = 2,
+     z->enabled = 0;
-                         .oem_id = oem_id, .oem_table_id = oem_table_id };
+     z->pos = 0;
+@@ -XXX,XX +XXX,XX @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data)
      acpi_table_begin(&table, table_data);
 -    for (socket = 0; socket < ms->smp.sockets; socket++) {
 -        g_queue_push_tail(list,
 -            GUINT_TO_POINTER(table_data->len - pptt_start));
 -        build_processor_hierarchy_node(
 -            table_data,
 -            /*
 -             * Physical package - represents the boundary
 -             * of a physical package
 -             */
 -            (1 << 0),
 -            0, socket, NULL, 0);
 -    }
 -
 -    if (mc->smp_props.clusters_supported) {
 -        length = g_queue_get_length(list);
 -        for (i = 0; i < length; i++) {
 -            int cluster;
 -
 -            parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -            for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
 -                g_queue_push_tail(list,
 -                    GUINT_TO_POINTER(table_data->len - pptt_start));
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (0 << 0), /* not a physical package */
 -                    parent_offset, cluster, NULL, 0);
 -            }
 +    /*
 +     * This works with the assumption that cpus[n].props.*_id has been
 +     * sorted from top to down levels in mc->possible_cpu_arch_ids().
 +     * Otherwise, the unexpected and duplicated containers will be
 +     * created.
 +     */
 +    for (n = 0; n < cpus->len; n++) {
 +        if (cpus->cpus[n].props.socket_id != socket_id) {
 +            assert(cpus->cpus[n].props.socket_id > socket_id);
 +            socket_id = cpus->cpus[n].props.socket_id;
 +            cluster_id = -1;
 +            core_id = -1;
 +            socket_offset = table_data->len - pptt_start;
 +            build_processor_hierarchy_node(table_data,
 +                (1 << 0), /* Physical package */
 +                0, socket_id, NULL, 0);
          }
 -    }
 -    length = g_queue_get_length(list);
 -    for (i = 0; i < length; i++) {
 -        int core;
 -
 -        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -        for (core = 0; core < ms->smp.cores; core++) {
 -            if (ms->smp.threads > 1) {
 -                g_queue_push_tail(list,
 -                    GUINT_TO_POINTER(table_data->len - pptt_start));
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (0 << 0), /* not a physical package */
 -                    parent_offset, core, NULL, 0);
 -            } else {
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (1 << 1) | /* ACPI Processor ID valid */
 -                    (1 << 3),  /* Node is a Leaf */
 -                    parent_offset, uid++, NULL, 0);
 +        if (mc->smp_props.clusters_supported) {
 +            if (cpus->cpus[n].props.cluster_id != cluster_id) {
 +                assert(cpus->cpus[n].props.cluster_id > cluster_id);
 +                cluster_id = cpus->cpus[n].props.cluster_id;
 +                core_id = -1;
 +                cluster_offset = table_data->len - pptt_start;
 +                build_processor_hierarchy_node(table_data,
 +                    (0 << 0), /* Not a physical package */
 +                    socket_offset, cluster_id, NULL, 0);
              }
 +        } else {
 +            cluster_offset = socket_offset;
          }
 -    }
 -    length = g_queue_get_length(list);
 -    for (i = 0; i < length; i++) {
 -        int thread;
 +        if (ms->smp.threads == 1) {
 +            build_processor_hierarchy_node(table_data,
 +                (1 << 1) | /* ACPI Processor ID valid */
 +                (1 << 3),  /* Node is a Leaf */
 +                cluster_offset, n, NULL, 0);
 +        } else {
 +            if (cpus->cpus[n].props.core_id != core_id) {
 +                assert(cpus->cpus[n].props.core_id > core_id);
 +                core_id = cpus->cpus[n].props.core_id;
 +                core_offset = table_data->len - pptt_start;
 +                build_processor_hierarchy_node(table_data,
 +                    (0 << 0), /* Not a physical package */
 +                    cluster_offset, core_id, NULL, 0);
 +            }
 -        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -        for (thread = 0; thread < ms->smp.threads; thread++) {
 -            build_processor_hierarchy_node(
 -                table_data,
 +            build_processor_hierarchy_node(table_data,
                  (1 << 1) | /* ACPI Processor ID valid */
                  (1 << 2) | /* Processor is a Thread */
                  (1 << 3),  /* Node is a Leaf */
 -                parent_offset, uid++, NULL, 0);
 +                core_offset, n, NULL, 0);
          }
      }
 -    g_queue_free(list);
      acpi_table_end(linker, &table);
  }
+ static const TypeInfo zipit_lcd_info = {
+-    .name          = "zipit-lcd",
++    .name          = TYPE_ZIPIT_LCD,
+     .parent        = TYPE_SSI_SLAVE,
+     .instance_size = sizeof(ZipitLCD),
+     .class_init    = zipit_lcd_class_init,
+@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
+     type_register_static(&zipit_lcd_info);
+     type_register_static(&aer915_info);
+-    z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd");
++    z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD);
+     bus = pxa2xx_i2c_bus(mpu->i2c[0]);
+     i2c_create_slave(bus, TYPE_AER915, 0x55);
+     wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b);
+diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/display/ads7846.c
++++ b/hw/display/ads7846.c
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+     int output;
+ } ADS7846State;
++#define TYPE_ADS7846 "ads7846"
++#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846)
++
+ /* Control-byte bitfields */
+ #define CB_PD0        (1 << 0)
+ #define CB_PD1        (1 << 1)
+@@ -XXX,XX +XXX,XX @@ static void ads7846_int_update(ADS7846State *s)
+ static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value)
+ {
+-    ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev);
++    ADS7846State *s = ADS7846(dev);
+     switch (s->cycle ++) {
+     case 0:
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ads7846 = {
+ static void ads7846_realize(SSISlave *d, Error **errp)
+ {
+     DeviceState *dev = DEVICE(d);
+-    ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d);
++    ADS7846State *s = ADS7846(d);
+     qdev_init_gpio_out(dev, &s->interrupt, 1);
+@@ -XXX,XX +XXX,XX @@ static void ads7846_class_init(ObjectClass *klass, void *data)
+ }
+ static const TypeInfo ads7846_info = {
+-    .name          = "ads7846",
++    .name          = TYPE_ADS7846,
+     .parent        = TYPE_SSI_SLAVE,
+     .instance_size = sizeof(ADS7846State),
+     .class_init    = ads7846_class_init,
+diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/display/ssd0323.c
++++ b/hw/display/ssd0323.c
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+     uint8_t framebuffer[128 * 80 / 2];
+ } ssd0323_state;
++#define TYPE_SSD0323 "ssd0323"
++#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323)
++
++
+ static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
+ {
+-    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
++    ssd0323_state *s = SSD0323(dev);
+     switch (s->mode) {
+     case SSD0323_DATA:
+@@ -XXX,XX +XXX,XX @@ static const GraphicHwOps ssd0323_ops = {
+ static void ssd0323_realize(SSISlave *d, Error **errp)
+ {
+     DeviceState *dev = DEVICE(d);
+-    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
++    ssd0323_state *s = SSD0323(d);
+     s->col_end = 63;
+     s->row_end = 79;
+@@ -XXX,XX +XXX,XX @@ static void ssd0323_class_init(ObjectClass *klass, void *data)
+ }
+ static const TypeInfo ssd0323_info = {
+-    .name          = "ssd0323",
++    .name          = TYPE_SSD0323,
+     .parent        = TYPE_SSI_SLAVE,
+     .instance_size = sizeof(ssd0323_state),
+     .class_init    = ssd0323_class_init,
+diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/sd/ssi-sd.c
++++ b/hw/sd/ssi-sd.c
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+ static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
+ {
+-    ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev);
++    ssi_sd_state *s = SSI_SD(dev);
+     /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data.  */
+     if (s->mode == SSI_SD_DATA_READ && val == 0x4d) {
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ssi_sd = {
+ static void ssi_sd_realize(SSISlave *d, Error **errp)
+ {
+-    ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
++    ssi_sd_state *s = SSI_SD(d);
+     DeviceState *carddev;
+     DriveInfo *dinfo;
+     Error *err = NULL;
 --
-.25.1
+.20.1

-[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
+[PULL 34/34] Deprecate TileGX port
-From: Richard Henderson <richard.henderson@linaro.org>
+Deprecate our TileGX target support:
  * we have no active maintainer for it
  * it has had essentially no contributions (other than tree-wide cleanups
    and similar) since it was first added
  * the Linux kernel dropped support in 2018, as has glibc
-Instead of starting with cortex-a15 and adding v8 features to
+Note the deprecation in the manual, but don't try to print a warning
-a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
+when QEMU runs -- printing unsuppressable messages is more obtrusive
-This fixes the long-standing to-do where we only enabled v8
+for linux-user mode than it would be for system-emulation mode, and
-features for user-only.
+it doesn't seem worth trying to invent a new suppressible-error
 system for linux-user just for this.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Message-id: 20200619154831.26319-1-peter.maydell@linaro.org
 ---
- target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
+ docs/system/deprecated.rst | 11 +++++++++++
-file changed, 92 insertions(+), 59 deletions(-)
+file changed, 11 insertions(+)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
+diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
+--- a/docs/system/deprecated.rst
-+++ b/target/arm/cpu_tcg.c
++++ b/docs/system/deprecated.rst
-@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
- static void arm_max_initfn(Object *obj)
- {
+   json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
-     ARMCPU *cpu = ARM_CPU(obj);
-+    uint32_t t;
++linux-user mode CPUs
++--------------------
 -    cortex_a15_initfn(obj);
 +    /* aarch64_a57_initfn, advertising none of the aarch64 features */
 +    cpu->dtb_compatible = "arm,cortex-a57";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->midr = 0x411fd070;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034070;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x8444c004;
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10101105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_isar6 = 0;
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -    /* old-style VFP short-vector support */
 -    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 +    /* Add additional features supported by QEMU */
 +    t = cpu->isar.id_isar5;
 +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 +    cpu->isar.id_isar5 = t;
 +
-+    t = cpu->isar.id_isar6;
++``tilegx`` CPUs (since 5.1.0)
-+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
++'''''''''''''''''''''''''''''
 +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 +    cpu->isar.id_isar6 = t;
 +
-+    t = cpu->isar.mvfr1;
++The ``tilegx`` guest CPU support (which was only implemented in
-+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
++linux-user mode) is deprecated and will be removed in a future version
-+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
++of QEMU. Support for this CPU was removed from the upstream Linux
-+    cpu->isar.mvfr1 = t;
++kernel in 2018, and has also been dropped from glibc.
 +
-+    t = cpu->isar.mvfr2;
+ Related binaries
-+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+ ----------------
 +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 +    cpu->isar.mvfr2 = t;
 +
 +    t = cpu->isar.id_mmfr3;
 +    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +    cpu->isar.id_mmfr3 = t;
 +
 +    t = cpu->isar.id_mmfr4;
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +    cpu->isar.id_mmfr4 = t;
 +
 +    t = cpu->isar.id_pfr0;
 +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 +    cpu->isar.id_pfr0 = t;
 +
 +    t = cpu->isar.id_pfr2;
 +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 +    cpu->isar.id_pfr2 = t;
  #ifdef CONFIG_USER_ONLY
      /*
 -     * We don't set these in system emulation mode for the moment,
 -     * since we don't correctly set (all of) the ID registers to
 -     * advertise them.
 +     * Break with true ARMv8 and add back old-style VFP short-vector support.
 +     * Only do this for user-mode, where -cpu max is the default, so that
 +     * older v6 and v7 programs are more likely to work without adjustment.
       */
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    {
 -        uint32_t t;
 -
 -        t = cpu->isar.id_isar5;
 -        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 -        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 -        cpu->isar.id_isar5 = t;
 -
 -        t = cpu->isar.id_isar6;
 -        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 -        cpu->isar.id_isar6 = t;
 -
 -        t = cpu->isar.mvfr1;
 -        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 -        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 -        cpu->isar.mvfr1 = t;
 -
 -        t = cpu->isar.mvfr2;
 -        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 -        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 -        cpu->isar.mvfr2 = t;
 -
 -        t = cpu->isar.id_mmfr3;
 -        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 -        cpu->isar.id_mmfr3 = t;
 -
 -        t = cpu->isar.id_mmfr4;
 -        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 -        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 -        cpu->isar.id_mmfr4 = t;
 -
 -        t = cpu->isar.id_pfr0;
 -        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 -        cpu->isar.id_pfr0 = t;
 -
 -        t = cpu->isar.id_pfr2;
 -        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 -        cpu->isar.id_pfr2 = t;
 -    }
 -#endif /* CONFIG_USER_ONLY */
 +    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 +#endif
  }
  #endif /* !TARGET_AARCH64 */
 --
-.25.1
+.20.1

target-arm queue: the big stuff here is the final part of
rth's patches for Cortex-A76 and Neoverse-N1 support;
also present are Gavin's NUMA series and a few other things.

thanks
-- PMM

The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:

Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509

for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:

hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)

----------------------------------------------------------------
target-arm queue:
 * MAINTAINERS/.mailmap: update email for Leif Lindholm
 * hw/arm: add version information to sbsa-ref machine DT
 * Enable new features for -cpu max:
   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
   FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
 * Emulate Cortex-A76
 * Emulate Neoverse-N1
 * Fix the virt board default NUMA topology

----------------------------------------------------------------
Gavin Shan (6):
      qapi/machine.json: Add cluster-id
      qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
      hw/arm/virt: Consider SMP configuration in CPU topology
      qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
      hw/arm/virt: Fix CPU's default NUMA node ID
      hw/acpi/aml-build: Use existing CPU topology to build PPTT table

Leif Lindholm (2):
      MAINTAINERS/.mailmap: update email for Leif Lindholm
      hw/arm: add versioning to sbsa-ref machine DT

Richard Henderson (24):
      target/arm: Handle cpreg registration for missing EL
      target/arm: Drop EL3 no EL2 fallbacks
      target/arm: Merge zcr reginfo
      target/arm: Adjust definition of CONTEXTIDR_EL2
      target/arm: Move cortex impdef sysregs to cpu_tcg.c
      target/arm: Update qemu-system-arm -cpu max to cortex-a57
      target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
      target/arm: Split out aa32_max_features
      target/arm: Annotate arm_max_initfn with FEAT identifiers
      target/arm: Use field names for manipulating EL2 and EL3 modes
      target/arm: Enable FEAT_Debugv8p2 for -cpu max
      target/arm: Enable FEAT_Debugv8p4 for -cpu max
      target/arm: Add minimal RAS registers
      target/arm: Enable SCR and HCR bits for RAS
      target/arm: Implement virtual SError exceptions
      target/arm: Implement ESB instruction
      target/arm: Enable FEAT_RAS for -cpu max
      target/arm: Enable FEAT_IESB for -cpu max
      target/arm: Enable FEAT_CSV2 for -cpu max
      target/arm: Enable FEAT_CSV2_2 for -cpu max
      target/arm: Enable FEAT_CSV3 for -cpu max
      target/arm: Enable FEAT_DGH for -cpu max
      target/arm: Define cortex-a76
      target/arm: Define neoverse-n1

From: Leif Lindholm <quic_llindhol@quicinc.com>

NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innovation Center (quicinc), so update
my email address to reflect this.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[Fixed commit message typo]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 .mailmap    | 3 ++-
 MAINTAINERS | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.mailmap b/.mailmap
index XXXXXXX..XXXXXXX 100644
--- a/.mailmap
+++ b/.mailmap
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
 James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
 Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
 Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
 Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
 SBSA-REF
 M: Radoslaw Biernacki <rad@semihalf.com>
 M: Peter Maydell <peter.maydell@linaro.org>
-R: Leif Lindholm <leif@nuviainc.com>
+R: Leif Lindholm <quic_llindhol@quicinc.com>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/sbsa-ref.c
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.

Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.

This will simplify cpreg registration for conditional arm features.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h |  11 +++
 target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
 2 files changed, 133 insertions(+), 56 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SVE                   = 1 << 14,
     /* Flag: Do not expose in gdb sysreg xml. */
     ARM_CP_NO_GDB                = 1 << 15,
+    /*
+     * Flags: If EL3 but not EL2...
+     *   - UNDEF: discard the cpreg,
+     *   -  KEEP: retain the cpreg as is,
+     *   -  C_NZ: set const on the cpreg, but retain resetvalue,
+     *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
+     * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+     */
+    ARM_CP_EL3_NO_EL2_UNDEF      = 1 << 16,
+    ARM_CP_EL3_NO_EL2_KEEP       = 1 << 17,
+    ARM_CP_EL3_NO_EL2_C_NZ       = 1 << 18,
 };
 
 /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
+      .access = PL2_RW,
+      .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
       .writefn = dacr_write, .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
       .type = ARM_CP_ALIAS,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .writefn = tlbimva_hyp_is_write },
     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2_write },
     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2_write },
     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2_write },
     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2is_write },
     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
 #ifndef CONFIG_USER_ONLY
     /* Unlike the other EL2-related AT operations, these must
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
       .access = PL2_W, .accessfn = at_s1e2_access,
-      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn = ats_write64 },
     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
       .access = PL2_W, .accessfn = at_s1e2_access,
-      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn = ats_write64 },
     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .accessfn = access_tda,
-      .type = ARM_CP_NOP },
+      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
     /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
      * Channel but Linux may try to access this register. The 32-bit
      * alias is DBGDCCINT.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
    { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NOP },
    { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
    { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2_write },
    { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2_write },
    { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2is_write },
     { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
    { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .writefn = tlbi_aa64_alle1is_write },
     { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL2_RW, .accessfn = access_el3_aa32ns,
-              .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
+              .resetvalue = cpu->midr,
+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL2_RW, .resetvalue = cpu->midr,
+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
               .access = PL2_RW, .accessfn = access_el3_aa32ns,
-              .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
+              .resetvalue = vmpidr_def,
+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-              .access = PL2_RW,
-              .resetvalue = vmpidr_def,
+              .access = PL2_RW, .resetvalue = vmpidr_def,
+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
         };
         define_arm_cp_regs(cpu, vpidr_regs);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
+    CPUARMState *env = &cpu->env;
     uint32_t key;
     ARMCPRegInfo *r2;
     bool is64 = r->type & ARM_CP_64BIT;
     bool ns = secstate & ARM_CP_SECSTATE_NS;
     int cp = r->cp;
-    bool isbanked;
     size_t name_len;
+    bool make_const;
 
     switch (state) {
     case ARM_CP_STATE_AA32:
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
     }
 
+    /*
+     * Eliminate registers that are not present because the EL is missing.
+     * Doing this here makes it easier to put all registers for a given
+     * feature into the same ARMCPRegInfo array and define them all at once.
+     */
+    make_const = false;
+    if (arm_feature(env, ARM_FEATURE_EL3)) {
+        /*
+         * An EL2 register without EL2 but with EL3 is (usually) RES0.
+         * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+         */
+        int min_el = ctz32(r->access) / 2;
+        if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
+            if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
+                return;
+            }
+            make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
+        }
+    } else {
+        CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
+                                 ? PL2_RW : PL1_RW);
+        if ((r->access & max_el) == 0) {
+            return;
+        }
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         r2->opaque = opaque;
     }
 
-    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
-    if (isbanked) {
+    if (make_const) {
+        /* This should not have been a very special register to begin. */
+        int old_special = r2->type & ARM_CP_SPECIAL_MASK;
+        assert(old_special == 0 || old_special == ARM_CP_NOP);
         /*
-         * Register is banked (using both entries in array).
-         * Overwriting fieldoffset as the array is only used to define
-         * banked registers but later only fieldoffset is used.
+         * Set the special function to CONST, retaining the other flags.
+         * This is important for e.g. ARM_CP_SVE so that we still
+         * take the SVE trap if CPTR_EL3.EZ == 0.
          */
-        r2->fieldoffset = r->bank_fieldoffsets[ns];
-    }
+        r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
+        /*
+         * Usually, these registers become RES0, but there are a few
+         * special cases like VPIDR_EL2 which have a constant non-zero
+         * value with writes ignored.
+         */
+        if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
+            r2->resetvalue = 0;
+        }
+        /*
+         * ARM_CP_CONST has precedence, so removing the callbacks and
+         * offsets are not strictly necessary, but it is potentially
+         * less confusing to debug later.
+         */
+        r2->readfn = NULL;
+        r2->writefn = NULL;
+        r2->raw_readfn = NULL;
+        r2->raw_writefn = NULL;
+        r2->resetfn = NULL;
+        r2->fieldoffset = 0;
+        r2->bank_fieldoffsets[0] = 0;
+        r2->bank_fieldoffsets[1] = 0;
+    } else {
+        bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 
-    if (state == ARM_CP_STATE_AA32) {
         if (isbanked) {
             /*
-             * If the register is banked then we don't need to migrate or
-             * reset the 32-bit instance in certain cases:
-             *
-             * 1) If the register has both 32-bit and 64-bit instances then we
-             *    can count on the 64-bit instance taking care of the
-             *    non-secure bank.
-             * 2) If ARMv8 is enabled then we can count on a 64-bit version
-             *    taking care of the secure bank.  This requires that separate
-             *    32 and 64-bit definitions are provided.
+             * Register is banked (using both entries in array).
+             * Overwriting fieldoffset as the array is only used to define
+             * banked registers but later only fieldoffset is used.
              */
-            if ((r->state == ARM_CP_STATE_BOTH && ns) ||
-                (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
+            r2->fieldoffset = r->bank_fieldoffsets[ns];
+        }
+        if (state == ARM_CP_STATE_AA32) {
+            if (isbanked) {
+                /*
+                 * If the register is banked then we don't need to migrate or
+                 * reset the 32-bit instance in certain cases:
+                 *
+                 * 1) If the register has both 32-bit and 64-bit instances
+                 *    then we can count on the 64-bit instance taking care
+                 *    of the non-secure bank.
+                 * 2) If ARMv8 is enabled then we can count on a 64-bit
+                 *    version taking care of the secure bank.  This requires
+                 *    that separate 32 and 64-bit definitions are provided.
+                 */
+                if ((r->state == ARM_CP_STATE_BOTH && ns) ||
+                    (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
+                    r2->type |= ARM_CP_ALIAS;
+                }
+            } else if ((secstate != r->secure) && !ns) {
+                /*
+                 * The register is not banked so we only want to allow
+                 * migration of the non-secure instance.
+                 */
                 r2->type |= ARM_CP_ALIAS;
             }
-        } else if ((secstate != r->secure) && !ns) {
-            /*
-             * The register is not banked so we only want to allow migration
-             * of the non-secure instance.
-             */
-            r2->type |= ARM_CP_ALIAS;
-        }
 
-        if (HOST_BIG_ENDIAN &&
-            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
-            r2->fieldoffset += sizeof(uint32_t);
+            if (HOST_BIG_ENDIAN &&
+                r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
+                r2->fieldoffset += sizeof(uint32_t);
+            }
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * multiple times. Special registers (ie NOP/WFI) are
      * never migratable and not even raw-accessible.
      */
-    if (r->type & ARM_CP_SPECIAL_MASK) {
+    if (r2->type & ARM_CP_SPECIAL_MASK) {
         r2->type |= ARM_CP_NO_RAW;
     }
     if (((r->crm == CP_ANY) && crm != 0) ||
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.

This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that the virtualization cpregs
are now correctly not present.  This would be a migration compatibility
break, except that we have an existing bug in which migration of 32-bit
cpus with Security Extensions enabled does not work.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 158 ++++----------------------------------------
 1 file changed, 13 insertions(+), 145 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
 };
 
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
-    { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
-      .access = PL2_RW,
-      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
-    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 6, .crm = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
-      .access = PL2_RW, .accessfn = access_tda,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
-      .type = ARM_CP_CONST,
-      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .resetvalue = 0 },
-};
-
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
-    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-};
-
 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, v8_idregs);
         define_arm_cp_regs(cpu, v8_cp_reginfo);
     }
-    if (arm_feature(env, ARM_FEATURE_EL2)) {
+
+    /*
+     * Register the base EL2 cpregs.
+     * Pre v8, these registers are implemented only as part of the
+     * Virtualization Extensions (EL2 present).  Beginning with v8,
+     * if EL2 is missing but EL3 is enabled, mostly these become
+     * RES0 from EL3, with some specific exceptions.
+     */
+    if (arm_feature(env, ARM_FEATURE_EL2)
+        || (arm_feature(env, ARM_FEATURE_EL3)
+            && arm_feature(env, ARM_FEATURE_V8))) {
         uint64_t vmpidr_def = mpidr_read_val(env);
         ARMCPRegInfo vpidr_regs[] = {
             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             };
             define_one_arm_cp_reg(cpu, &rvbar);
         }
-    } else {
-        /* If EL2 is missing but higher ELs are enabled, we need to
-         * register the no_el2 reginfos.
-         */
-        if (arm_feature(env, ARM_FEATURE_EL3)) {
-            /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
-             * of MIDR_EL1 and MPIDR_EL1.
-             */
-            ARMCPRegInfo vpidr_regs[] = {
-                { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
-                  .type = ARM_CP_CONST, .resetvalue = cpu->midr,
-                  .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
-                { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
-                  .type = ARM_CP_NO_RAW,
-                  .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
-            };
-            define_arm_cp_regs(cpu, vpidr_regs);
-            define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
-            if (arm_feature(env, ARM_FEATURE_V8)) {
-                define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
-            }
-        }
     }
+
+    /* Register the base EL3 cpregs. */
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         define_arm_cp_regs(cpu, el3_cp_reginfo);
         ARMCPRegInfo el3_regs[] = {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 55 ++++++++++++++-------------------------------
 1 file changed, 17 insertions(+), 38 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 }
 
-static const ARMCPRegInfo zcr_el1_reginfo = {
-    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL1_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
-    .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_el2_reginfo = {
-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL2_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
-    .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL2_RW, .type = ARM_CP_SVE,
-    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
-};
-
-static const ARMCPRegInfo zcr_el3_reginfo = {
-    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL3_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
-    .writefn = zcr_write, .raw_writefn = raw_write
+static const ARMCPRegInfo zcr_reginfo[] = {
+    { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
+    { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
+    { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL3_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
 };
 
 void hw_watchpoint_update(ARMCPU *cpu, int n)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (cpu_isar_feature(aa64_sve, cpu)) {
-        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
-        if (arm_feature(env, ARM_FEATURE_EL2)) {
-            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
-        } else {
-            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
-        }
-        if (arm_feature(env, ARM_FEATURE_EL3)) {
-            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
-        }
+        define_arm_cp_regs(cpu, zcr_reginfo);
     }
 
 #ifdef TARGET_AARCH64
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This register is present for either VHE or Debugv8p2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 };
 
+static const ARMCPRegInfo contextidr_el2 = {
+    .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+    .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+    .access = PL2_RW,
+    .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
 static const ARMCPRegInfo vhe_reginfo[] = {
-    { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
-      .access = PL2_RW,
-      .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
     }
 
+    if (cpu_isar_feature(aa64_vh, cpu) ||
+        cpu_isar_feature(aa64_debugv8p2, cpu)) {
+        define_one_arm_cp_reg(cpu, &contextidr_el2);
+    }
     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
         define_arm_cp_regs(cpu, vhe_reginfo);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.

This will shortly be used from cpu_tcg.c also.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h |  6 ++++
 target/arm/cpu64.c     | 64 +++---------------------------------------
 target/arm/cpu_tcg.c   | 59 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+), 60 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
 #endif
 
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "hvf_arm.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
-#include "cpregs.h"
+#include "internals.h"
 
 
-#ifndef CONFIG_USER_ONLY
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
-    ARMCPU *cpu = env_archcpu(env);
-
-    /* Number of cores is in [25:24]; otherwise we RAZ */
-    return (cpu->core_count - 1) << 24;
-}
-#endif
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
-#ifndef CONFIG_USER_ONLY
-    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
-    { .name = "L2CTLR",
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
-#endif
-    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2ECTLR",
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUACTLR",
-      .cp = 15, .opc1 = 0, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUECTLR",
-      .cp = 15, .opc1 = 1, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUMERRSR",
-      .cp = 15, .opc1 = 2, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2MERRSR",
-      .cp = 15, .opc1 = 3, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-};
-
 static void aarch64_a57_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 static void aarch64_a53_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 static void aarch64_a72_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #endif
 #include "cpregs.h"
 
+#ifndef CONFIG_USER_ONLY
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    /* Number of cores is in [25:24]; otherwise we RAZ */
+    return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+      .access = PL1_RW, .readfn = l2ctlr_read,
+      .writefn = arm_cp_write_ignore },
+    { .name = "L2CTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+      .access = PL1_RW, .readfn = l2ctlr_read,
+      .writefn = arm_cp_write_ignore },
+    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2ECTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUACTLR",
+      .cp = 15, .opc1 = 0, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUECTLR",
+      .cp = 15, .opc1 = 1, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUMERRSR",
+      .cp = 15, .opc1 = 2, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2MERRSR",
+      .cp = 15, .opc1 = 3, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
+#endif /* !CONFIG_USER_ONLY */
+
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
 1 file changed, 92 insertions(+), 59 deletions(-)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t t;
 
-    cortex_a15_initfn(obj);
+    /* aarch64_a57_initfn, advertising none of the aarch64 features */
+    cpu->dtb_compatible = "arm,cortex-a57";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x411fd070;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0;
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
-    /* old-style VFP short-vector support */
-    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+    /* Add additional features supported by QEMU */
+    t = cpu->isar.id_isar5;
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    cpu->isar.id_isar5 = t;
+
+    t = cpu->isar.id_isar6;
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    cpu->isar.id_isar6 = t;
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    t = cpu->isar.id_mmfr3;
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    cpu->isar.id_mmfr3 = t;
+
+    t = cpu->isar.id_mmfr4;
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    cpu->isar.id_mmfr4 = t;
+
+    t = cpu->isar.id_pfr0;
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    cpu->isar.id_pfr0 = t;
+
+    t = cpu->isar.id_pfr2;
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    cpu->isar.id_pfr2 = t;
 
 #ifdef CONFIG_USER_ONLY
     /*
-     * We don't set these in system emulation mode for the moment,
-     * since we don't correctly set (all of) the ID registers to
-     * advertise them.
+     * Break with true ARMv8 and add back old-style VFP short-vector support.
+     * Only do this for user-mode, where -cpu max is the default, so that
+     * older v6 and v7 programs are more likely to work without adjustment.
      */
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    {
-        uint32_t t;
-
-        t = cpu->isar.id_isar5;
-        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-        cpu->isar.id_isar5 = t;
-
-        t = cpu->isar.id_isar6;
-        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-        t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-        t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-        cpu->isar.id_isar6 = t;
-
-        t = cpu->isar.mvfr1;
-        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-        cpu->isar.mvfr1 = t;
-
-        t = cpu->isar.mvfr2;
-        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-        cpu->isar.mvfr2 = t;
-
-        t = cpu->isar.id_mmfr3;
-        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-        cpu->isar.id_mmfr3 = t;
-
-        t = cpu->isar.id_mmfr4;
-        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-        cpu->isar.id_mmfr4 = t;
-
-        t = cpu->isar.id_pfr0;
-        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-        cpu->isar.id_pfr0 = t;
-
-        t = cpu->isar.id_pfr2;
-        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-        cpu->isar.id_pfr2 = t;
-    }
-#endif /* CONFIG_USER_ONLY */
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+#endif
 }
 #endif /* !TARGET_AARCH64 */
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.

Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
     cpu->isar.id_pfr2 = t;
 
+    t = cpu->isar.id_dfr0;
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    cpu->isar.id_dfr0 = t;
+
 #ifdef CONFIG_USER_ONLY
     /*
      * Break with true ARMv8 and add back old-style VFP short-vector support.
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h |   2 +
 target/arm/cpu64.c     |  50 +-----------------
 target/arm/cpu_tcg.c   | 114 ++++++++++++++++++++++-------------------
 3 files changed, 65 insertions(+), 101 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+void aa32_max_features(ARMCPU *cpu);
+
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     uint64_t t;
-    uint32_t u;
 
     if (kvm_enabled() || hvf_enabled()) {
         /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
     cpu->isar.id_aa64zfr0 = t;
 
-    /* Replicate the same data to the 32-bit id registers.  */
-    u = cpu->isar.id_isar5;
-    u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
-    u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
-    u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
-    u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
-    u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
-    u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
-    cpu->isar.id_isar5 = u;
-
-    u = cpu->isar.id_isar6;
-    u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
-    u = FIELD_DP32(u, ID_ISAR6, DP, 1);
-    u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
-    u = FIELD_DP32(u, ID_ISAR6, SB, 1);
-    u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
-    u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
-    u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
-    cpu->isar.id_isar6 = u;
-
-    u = cpu->isar.id_pfr0;
-    u = FIELD_DP32(u, ID_PFR0, DIT, 1);
-    cpu->isar.id_pfr0 = u;
-
-    u = cpu->isar.id_pfr2;
-    u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
-    cpu->isar.id_pfr2 = u;
-
-    u = cpu->isar.id_mmfr3;
-    u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
-    cpu->isar.id_mmfr3 = u;
-
-    u = cpu->isar.id_mmfr4;
-    u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
-    u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
-    cpu->isar.id_mmfr4 = u;
-
     t = cpu->isar.id_aa64dfr0;
     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
     cpu->isar.id_aa64dfr0 = t;
 
-    u = cpu->isar.id_dfr0;
-    u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-    cpu->isar.id_dfr0 = u;
-
-    u = cpu->isar.mvfr1;
-    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
-    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
-    cpu->isar.mvfr1 = u;
+    /* Replicate the same data to the 32-bit id registers.  */
+    aa32_max_features(cpu);
 
 #ifdef CONFIG_USER_ONLY
     /*
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #endif
 #include "cpregs.h"
 
+
+/* Share AArch32 -cpu max features with AArch64. */
+void aa32_max_features(ARMCPU *cpu)
+{
+    uint32_t t;
+
+    /* Add additional features supported by QEMU */
+    t = cpu->isar.id_isar5;
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    cpu->isar.id_isar5 = t;
+
+    t = cpu->isar.id_isar6;
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    cpu->isar.id_isar6 = t;
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    t = cpu->isar.id_mmfr3;
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    cpu->isar.id_mmfr3 = t;
+
+    t = cpu->isar.id_mmfr4;
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    cpu->isar.id_mmfr4 = t;
+
+    t = cpu->isar.id_pfr0;
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    cpu->isar.id_pfr0 = t;
+
+    t = cpu->isar.id_pfr2;
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    cpu->isar.id_pfr2 = t;
+
+    t = cpu->isar.id_dfr0;
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    cpu->isar.id_dfr0 = t;
+}
+
 #ifndef CONFIG_USER_ONLY
 static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    uint32_t t;
 
     /* aarch64_a57_initfn, advertising none of the aarch64 features */
     cpu->dtb_compatible = "arm,cortex-a57";
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
-    /* Add additional features supported by QEMU */
-    t = cpu->isar.id_isar5;
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-    cpu->isar.id_isar5 = t;
-
-    t = cpu->isar.id_isar6;
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-    cpu->isar.id_isar6 = t;
-
-    t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-    cpu->isar.mvfr1 = t;
-
-    t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-    cpu->isar.mvfr2 = t;
-
-    t = cpu->isar.id_mmfr3;
-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-    cpu->isar.id_mmfr3 = t;
-
-    t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-    cpu->isar.id_mmfr4 = t;
-
-    t = cpu->isar.id_pfr0;
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-    cpu->isar.id_pfr0 = t;
-
-    t = cpu->isar.id_pfr2;
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-    cpu->isar.id_pfr2 = t;
-
-    t = cpu->isar.id_dfr0;
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-    cpu->isar.id_dfr0 = t;
+    aa32_max_features(cpu);
 
 #ifdef CONFIG_USER_ONLY
     /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu64.c   | 100 +++++++++++++++++++++----------------------
 target/arm/cpu_tcg.c |  48 ++++++++++-----------
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     cpu->midr = t;
 
     t = cpu->isar.id_aa64isar0;
-    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
     t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
-    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
-    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
-    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
+    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
+    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
+    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
+    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
     cpu->isar.id_aa64isar0 = t;
 
     t = cpu->isar.id_aa64isar1;
-    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
-    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
-    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
+    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
+    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
+    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
+    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
+    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
     cpu->isar.id_aa64isar1 = t;
 
     t = cpu->isar.id_aa64pfr0;
+    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
+    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
+    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
     cpu->isar.id_aa64pfr0 = t;
 
     t = cpu->isar.id_aa64pfr1;
-    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
-    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
+    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
+    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
     /*
      * Begin with full support for MTE. This will be downgraded to MTE=0
      * during realize if the board provides no tag memory, much like
      * we do for EL2 with the virtualization=on property.
      */
-    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
+    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
     cpu->isar.id_aa64pfr1 = t;
 
     t = cpu->isar.id_aa64mmfr0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     cpu->isar.id_aa64mmfr0 = t;
 
     t = cpu->isar.id_aa64mmfr1;
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
-    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
-    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
-    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
+    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
+    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
     cpu->isar.id_aa64mmfr1 = t;
 
     t = cpu->isar.id_aa64mmfr2;
-    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
-    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
-    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
-    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
-    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
+    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
+    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
+    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
+    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
+    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
+    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
     cpu->isar.id_aa64mmfr2 = t;
 
     t = cpu->isar.id_aa64zfr0;
     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
-    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
+    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
+    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
+    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
+    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
     cpu->isar.id_aa64zfr0 = t;
 
     t = cpu->isar.id_aa64dfr0;
-    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
     cpu->isar.id_aa64dfr0 = t;
 
     /* Replicate the same data to the 32-bit id registers.  */
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
 
     /* Add additional features supported by QEMU */
     t = cpu->isar.id_isar5;
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
     t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
     cpu->isar.id_isar5 = t;
 
     t = cpu->isar.id_isar6;
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
     cpu->isar.id_isar6 = t;
 
     t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
     cpu->isar.mvfr1 = t;
 
     t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
     cpu->isar.mvfr2 = t;
 
     t = cpu->isar.id_mmfr3;
-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
     cpu->isar.id_mmfr4 = t;
 
     t = cpu->isar.id_pfr0;
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
     cpu->isar.id_pfr0 = t;
 
     t = cpu->isar.id_pfr2;
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
     cpu->isar.id_pfr2 = t;
 
     t = cpu->isar.id_dfr0;
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
     cpu->isar.id_dfr0 = t;
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          */
         unset_feature(env, ARM_FEATURE_EL3);
 
-        /* Disable the security extension feature bits in the processor feature
-         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
+        /*
+         * Disable the security extension feature bits in the processor
+         * feature registers as well.
          */
-        cpu->isar.id_pfr1 &= ~0xf0;
-        cpu->isar.id_aa64pfr0 &= ~0xf000;
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL3, 0);
     }
 
     if (!cpu->has_el2) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
-        /* Disable the hypervisor feature bits in the processor feature
-         * registers if we don't have EL2. These are id_pfr1[15:12] and
-         * id_aa64pfr0_el1[11:8].
+        /*
+         * Disable the hypervisor feature bits in the processor feature
+         * registers if we don't have EL2.
          */
-        cpu->isar.id_aa64pfr0 &= ~0xf00;
-        cpu->isar.id_pfr1 &= ~0xf000;
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL2, 0);
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
+                                       ID_PFR1, VIRTUALIZATION, 0);
     }
 
 #ifndef CONFIG_USER_ONLY
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE.  The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu.c              | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 2 ++
 4 files changed, 5 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU.  Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 2 +-
 target/arm/cpu_tcg.c          | 4 ++--
 3 files changed, 4 insertions(+), 3 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Add only the system registers required to implement zero error
records.  This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.

Add the EL2 registers required for injecting virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  5 +++
 target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
         uint64_t gcr_el1;
         uint64_t rgsr_el1;
+
+        /* Minimal RAS registers */
+        uint64_t disr_el1;
+        uint64_t vdisr_el2;
+        uint64_t vsesr_el2;
     } cp15;
 
     struct {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 };
 
+/*
+ * Check for traps to RAS registers, which are controlled
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
+ */
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+        return env->cp15.vdisr_el2;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+        return 0; /* RAZ/WI */
+    }
+    return env->cp15.disr_el1;
+}
+
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+        env->cp15.vdisr_el2 = val;
+        return;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+        return; /* RAZ/WI */
+    }
+    env->cp15.disr_el1 = val;
+}
+
+/*
+ * Minimal RAS implementation with no Error Records.
+ * Which means that all of the Error Record registers:
+ *   ERXADDR_EL1
+ *   ERXCTLR_EL1
+ *   ERXFR_EL1
+ *   ERXMISC0_EL1
+ *   ERXMISC1_EL1
+ *   ERXMISC2_EL1
+ *   ERXMISC3_EL1
+ *   ERXPFGCDN_EL1  (RASv1p1)
+ *   ERXPFGCTL_EL1  (RASv1p1)
+ *   ERXPFGF_EL1    (RASv1p1)
+ *   ERXSTATUS_EL1
+ * and
+ *   ERRSELR_EL1
+ * may generate UNDEFINED, which is the effect we get by not
+ * listing them at all.
+ */
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
+    { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
+      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
+      .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
+    { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
+      .access = PL1_R, .accessfn = access_terr,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
+    { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
+};
+
 /* Return the exception level to which exceptions should be taken
  * via SVEAccessTrap.  If an exception should be routed through
  * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_ssbs, cpu)) {
         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
     }
+    if (cpu_isar_feature(any_ras, cpu)) {
+        define_arm_cp_regs(cpu, minimal_ras_reginfo);
+    }
 
     if (cpu_isar_feature(aa64_vh, cpu) ||
         cpu_isar_feature(aa64_debugv8p2, cpu)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
         valid_mask &= ~SCR_NET;
 
+        if (cpu_isar_feature(aa64_ras, cpu)) {
+            valid_mask |= SCR_TERR;
+        }
         if (cpu_isar_feature(aa64_lor, cpu)) {
             valid_mask |= SCR_TLOR;
         }
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
+        if (cpu_isar_feature(aa32_ras, cpu)) {
+            valid_mask |= SCR_TERR;
+        }
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         if (cpu_isar_feature(aa64_vh, cpu)) {
             valid_mask |= HCR_E2H;
         }
+        if (cpu_isar_feature(aa64_ras, cpu)) {
+            valid_mask |= HCR_TERR | HCR_TEA;
+        }
         if (cpu_isar_feature(aa64_lor, cpu)) {
             valid_mask |= HCR_TLOR;
         }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |  2 ++
 target/arm/internals.h |  8 ++++++++
 target/arm/syndrome.h  |  5 +++++
 target/arm/cpu.c       | 38 +++++++++++++++++++++++++++++++++++++-
 target/arm/helper.c    | 40 +++++++++++++++++++++++++++++++++++++++-
 5 files changed, 91 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
 #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
 #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
+#define EXCP_VSERR          24
 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
 
 #define ARMV7M_EXCP_RESET   1
@@ -XXX,XX +XXX,XX @@ enum {
 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
 
 /* The usual mapping for an AArch64 system register to its AArch32
  * counterpart is for the 32 bit world to have access to the lower
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
  */
 void arm_cpu_update_vfiq(ARMCPU *cpu);
 
+/**
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
+ *
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
+ * following a change to the HCR_EL2.VSE bit.
+ */
+void arm_cpu_update_vserr(ARMCPU *cpu);
+
 /**
  * arm_mmu_idx_el:
  * @env: The cpu environment
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
     return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 }
 
+static inline uint32_t syn_serror(uint32_t extra)
+{
+    return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
+}
+
 #endif /* TARGET_ARM_SYNDROME_H */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
     return (cpu->power_state != PSCI_OFF)
         && cs->interrupt_request &
         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
-         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
+         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
          | CPU_INTERRUPT_EXITTB);
 }
 
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
             return false;
         }
         return !(env->daif & PSTATE_I);
+    case EXCP_VSERR:
+        if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
+            /* VIRQs are only taken when hypervized.  */
+            return false;
+        }
+        return !(env->daif & PSTATE_A);
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
             goto found;
         }
     }
+    if (interrupt_request & CPU_INTERRUPT_VSERR) {
+        excp_idx = EXCP_VSERR;
+        target_el = 1;
+        if (arm_excp_unmasked(cs, excp_idx, target_el,
+                              cur_el, secure, hcr_el2)) {
+            /* Taking a virtual abort clears HCR_EL2.VSE */
+            env->cp15.hcr_el2 &= ~HCR_VSE;
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+            goto found;
+        }
+    }
     return false;
 
  found:
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
     }
 }
 
+void arm_cpu_update_vserr(ARMCPU *cpu)
+{
+    /*
+     * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
+     */
+    CPUARMState *env = &cpu->env;
+    CPUState *cs = CPU(cpu);
+
+    bool new_state = env->cp15.hcr_el2 & HCR_VSE;
+
+    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
+        if (new_state) {
+            cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
+        } else {
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+        }
+    }
+}
+
 #ifndef CONFIG_USER_ONLY
 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
         }
     }
 
-    /* External aborts are not possible in QEMU so A bit is always clear */
+    if (hcr_el2 & HCR_AMO) {
+        if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
+            ret |= CPSR_A;
+        }
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
     g_assert(qemu_mutex_iothread_locked());
     arm_cpu_update_virq(cpu);
     arm_cpu_update_vfiq(cpu);
+    arm_cpu_update_vserr(cpu);
 }
 
 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
             [EXCP_LSERR] = "v8M LSERR UsageFault",
             [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
             [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
+            [EXCP_VSERR] = "Virtual SERR",
         };
 
         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
         mask = CPSR_A | CPSR_I | CPSR_F;
         offset = 4;
         break;
+    case EXCP_VSERR:
+        {
+            /*
+             * Note that this is reported as a data abort, but the DFAR
+             * has an UNKNOWN value.  Construct the SError syndrome from
+             * AET and ExT fields.
+             */
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
+
+            if (extended_addresses_enabled(env)) {
+                env->exception.fsr = arm_fi_to_lfsc(&fi);
+            } else {
+                env->exception.fsr = arm_fi_to_sfsc(&fi);
+            }
+            env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
+            A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
+            qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
+                          env->exception.fsr);
+
+            new_mode = ARM_CPU_MODE_ABT;
+            addr = 0x10;
+            mask = CPSR_A | CPSR_I;
+            offset = 8;
+        }
+        break;
     case EXCP_SMC:
         new_mode = ARM_CPU_MODE_MON;
         addr = 0x08;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     case EXCP_VFIQ:
         addr += 0x100;
         break;
+    case EXCP_VSERR:
+        addr += 0x180;
+        /* Construct the SError syndrome from IDS and ISS fields. */
+        env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
+        env->cp15.esr_el[new_el] = env->exception.syndrome;
+        break;
     default:
         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Check for and defer any pending virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  1 +
 target/arm/a32.decode      | 16 ++++++++------
 target/arm/t32.decode      | 18 ++++++++--------
 target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c | 17 +++++++++++++++
 target/arm/translate.c     | 23 ++++++++++++++++++++
 6 files changed, 103 insertions(+), 15 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
 DEF_HELPER_1(yield, void, env)
 DEF_HELPER_1(pre_hvc, void, env)
 DEF_HELPER_2(pre_smc, void, env, i32)
+DEF_HELPER_1(vesb, void, env)
 
 DEF_HELPER_3(cpsr_write, void, env, i32, i32)
 DEF_HELPER_2(cpsr_write_eret, void, env, i32)
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -XXX,XX +XXX,XX @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
 
 {
   {
-    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
-    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
-    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
+    [
+      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
+      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
+      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 
-    # TODO: Implement SEV, SEVL; may help SMP performance.
-    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
-    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
+      # TODO: Implement SEV, SEVL; may help SMP performance.
+      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
+      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
+
+      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
+    ]
 
     # The canonical nop ends in 00000000, but the whole of the
     # rest of the space executes as nop if otherwise unsupported.
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
   [
     # Hints, and CPS
     {
-      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
-      WFE        1111 0011 1010 1111 1000 0000 0000 0010
-      WFI        1111 0011 1010 1111 1000 0000 0000 0011
+      [
+        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
+        WFE      1111 0011 1010 1111 1000 0000 0000 0010
+        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 
-      # TODO: Implement SEV, SEVL; may help SMP performance.
-      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
-      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
+        # TODO: Implement SEV, SEVL; may help SMP performance.
+        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
+        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 
-      # For M-profile minimal-RAS ESB can be a NOP, which is the
-      # default behaviour since it is in the hint space.
-      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
+        ESB      1111 0011 1010 1111 1000 0000 0001 0000
+      ]
 
       # The canonical nop ends in 0000 0000, but the whole rest
       # of the space is "reserved hint, behaves as nop".
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                      access_type, mmu_idx, ra);
     }
 }
+
+/*
+ * This function corresponds to AArch64.vESBOperation().
+ * Note that the AArch32 version is not functionally different.
+ */
+void HELPER(vesb)(CPUARMState *env)
+{
+    /*
+     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
+     * and will return HCR_EL2.VSE == 0, so nothing happens.
+     */
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
+    bool pending = enabled && (hcr & HCR_VSE);
+    bool masked  = (env->daif & PSTATE_A);
+
+    /* If VSE pending and masked, defer the exception.  */
+    if (pending && masked) {
+        uint32_t syndrome;
+
+        if (arm_el_is_aa64(env, 1)) {
+            /* Copy across IDS and ISS from VSESR. */
+            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
+        } else {
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
+
+            if (extended_addresses_enabled(env)) {
+                syndrome = arm_fi_to_lfsc(&fi);
+            } else {
+                syndrome = arm_fi_to_sfsc(&fi);
+            }
+            /* Copy across AET and ExT from VSESR. */
+            syndrome |= env->cp15.vsesr_el2 & 0xd000;
+        }
+
+        /* Set VDISR_EL2.A along with the syndrome. */
+        env->cp15.vdisr_el2 = syndrome | (1u << 31);
+
+        /* Clear pending virtual SError */
+        env->cp15.hcr_el2 &= ~HCR_VSE;
+        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
+    }
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
             gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
         }
         break;
+    case 0b10000: /* ESB */
+        /* Without RAS, we must implement this as NOP. */
+        if (dc_isar_feature(aa64_ras, s)) {
+            /*
+             * QEMU does not have a source of physical SErrors,
+             * so we are only concerned with virtual SErrors.
+             * The pseudocode in the ARM for this case is
+             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+             *      AArch64.vESBOperation();
+             * Most of the condition can be evaluated at translation time.
+             * Test for EL2 present, and defer test for SEL2 to runtime.
+             */
+            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+                gen_helper_vesb(cpu_env);
+            }
+        }
+        break;
     case 0b11000: /* PACIAZ */
         if (s->pauth_active) {
             gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
     return true;
 }
 
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
+{
+    /*
+     * For M-profile, minimal-RAS ESB can be a NOP.
+     * Without RAS, we must implement this as NOP.
+     */
+    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
+        /*
+         * QEMU does not have a source of physical SErrors,
+         * so we are only concerned with virtual SErrors.
+         * The pseudocode in the ARM for this case is
+         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+         *      AArch32.vESBOperation();
+         * Most of the condition can be evaluated at translation time.
+         * Test for EL2 present, and defer test for SEL2 to runtime.
+         */
+        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+            gen_helper_vesb(cpu_env);
+        }
+    }
+    return true;
+}
+
 static bool trans_NOP(DisasContext *s, arg_NOP *a)
 {
     return true;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 2 files changed, 2 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns branch speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst |  3 ++
 target/arm/cpu.h              | 16 +++++++++
 target/arm/cpu.c              |  5 +++
 target/arm/cpu64.c            |  3 +-
 target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
 5 files changed, 86 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_BF16 (AArch64 BFloat16 instructions)
 - FEAT_BTI (Branch Target Identification)
 - FEAT_CSV2 (Cache speculation variant 2)
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
 - FEAT_DIT (Data Independent Timing instructions)
 - FEAT_DPB (DC CVAP instruction)
 - FEAT_Debugv8p2 (Debug changes for v8.2)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         ARMPACKey apdb;
         ARMPACKey apga;
     } keys;
+
+    uint64_t scxtnum_el[4];
 #endif
 
 #if defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
 #define SCTLR_WXN     (1U << 19)
 #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
 #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
+#define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
 #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
 #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
 #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
 }
 
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
+{
+    int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
+    if (key >= 2) {
+        return true;      /* FEAT_CSV2_2 */
+    }
+    if (key == 1) {
+        key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
+        return key >= 2;  /* FEAT_CSV2_1p2 */
+    }
+    return false;
+}
+
 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
              */
             env->cp15.gcr_el1 = 0x1ffff;
         }
+        /*
+         * Disable access to SCXTNUM_EL0 from CSV2_1p2.
+         * This is not yet exposed from the Linux kernel in any way.
+         */
+        env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
 #else
         /* Reset into the highest available EL */
         if (arm_feature(env, ARM_FEATURE_EL3)) {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr0 = t;
 
     t = cpu->isar.id_aa64pfr1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      * we do for EL2 with the virtualization=on property.
      */
     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
+    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr1 = t;
 
     t = cpu->isar.id_aa64mmfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= SCR_ATA;
         }
+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+            valid_mask |= SCR_ENSCXT;
+        }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
         if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
         }
+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+            valid_mask |= HCR_ENSCXT;
+        }
     }
 
     /* Clear RES0 bits.  */
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
         { K(3, 0,  5, 6, 0), K(3, 4,  5, 6, 0), K(3, 5, 5, 6, 0),
           "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
 
+        { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
+          "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
+          isar_feature_aa64_scxtnum },
+
         /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
         /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
     };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
     },
 };
 
-#endif
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
+                                     bool isread)
+{
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    int el = arm_current_el(env);
+
+    if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
+        if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
+            if (hcr & HCR_TGE) {
+                return CP_ACCESS_TRAP_EL2;
+            }
+            return CP_ACCESS_TRAP;
+        }
+    } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3
+        && arm_feature(env, ARM_FEATURE_EL3)
+        && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static const ARMCPRegInfo scxtnum_reginfo[] = {
+    { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL0_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
+    { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL1_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
+    { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL2_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
+    { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL3_RW,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
+};
+#endif /* TARGET_AARCH64 */
 
 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
                                      bool isread)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     }
+
+    if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+        define_arm_cp_regs(cpu, scxtnum_reginfo);
+    }
 #endif
 
     if (cpu_isar_feature(any_predinv, cpu)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns cache speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns not merging memory access, which TCG does
not implement.  Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/translate-a64.c    | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

Enable the a76 for virt and sbsa board use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/sbsa-ref.c        |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a53`` (64-bit)
 - ``cortex-a57`` (64-bit)
 - ``cortex-a72`` (64-bit)
+- ``cortex-a76`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
 static const char * const valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("max"),
 };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a53"),
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("a64fx"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
+static void aarch64_a76_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a76";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444C004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0b1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.18 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+    /* From B2.93 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+}
+
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
+    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable the n1 for virt and sbsa board use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/sbsa-ref.c        |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a76`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
+- ``neoverse-n1`` (64-bit)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
 
 Note that the default is ``cortex-a15``, so for an AArch64 guest you must
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
+    ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("max"),
 };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("a64fx"),
+    ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
     cpu->isar.mvfr2 = 0x00000043;
 }
 
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,neoverse-n1";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444c004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0c1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.23 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+    /* From B2.98 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+}
+
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+    { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
     { .name = "host",               .initfn = aarch64_host_initfn },
-- 
2.25.1

From: Leif Lindholm <quic_llindhol@quicinc.com>

The sbsa-ref machine is continuously evolving. Some of the changes we
want to make in the near future, to align with real components (e.g.
the GIC-700), will break compatibility for existing firmware.

Introduce two new properties to the DT generated on machine generation:
- machine-version-major
  To be incremented when a platform change makes the machine
  incompatible with existing firmware.
- machine-version-minor
  To be incremented when functionality is added to the machine
  without causing incompatibility with existing firmware.
  to be reset to 0 when machine-version-major is incremented.

This versioning scheme is *neither*:
- A QEMU versioned machine type; a given version of QEMU will emulate
  a given version of the platform.
- A reflection of level of SBSA (now SystemReady SR) support provided.

The version will increment on guest-visible functional changes only,
akin to a revision ID register found on a physical platform.

These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 
+    /*
+     * This versioning scheme is for informing platform fw only. It is neither:
+     * - A QEMU versioned machine type; a given version of QEMU will emulate
+     *   a given version of the platform.
+     * - A reflection of level of SBSA (now SystemReady SR) support provided.
+     *
+     * machine-version-major: updated when changes breaking fw compatibility
+     *                        are introduced.
+     * machine-version-minor: updated when features are added that don't break
+     *                        fw compatibility.
+     */
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
+
     if (ms->numa_state->have_numa_distance) {
         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
         uint32_t *matrix = g_malloc0(size);
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:

* hw/core/machine.c::machine_set_cpu_numa_node() to associate
    CPU with its NUMA node.

* hw/core/machine.c::machine_numa_finish_cpu_init() to record
    CPU slots with no NUMA mapping set.

* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
    cluster-id.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 qapi/machine.json          |  6 ++++--
 hw/core/machine-hmp-cmds.c |  4 ++++
 hw/core/machine.c          | 16 ++++++++++++++++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/qapi/machine.json b/qapi/machine.json
index XXXXXXX..XXXXXXX 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -XXX,XX +XXX,XX @@
 # @node-id: NUMA node ID the CPU belongs to
 # @socket-id: socket number within node/board the CPU belongs to
 # @die-id: die number within socket the CPU belongs to (since 4.1)
-# @core-id: core number within die the CPU belongs to
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
+# @core-id: core number within cluster the CPU belongs to
 # @thread-id: thread number within core the CPU belongs to
 #
-# Note: currently there are 5 properties that could be present
+# Note: currently there are 6 properties that could be present
 #       but management should be prepared to pass through other
 #       properties with device_add command to allow for future
 #       interface extension. This also requires the filed names to be kept in
@@ -XXX,XX +XXX,XX @@
   'data': { '*node-id': 'int',
             '*socket-id': 'int',
             '*die-id': 'int',
+            '*cluster-id': 'int',
             '*core-id': 'int',
             '*thread-id': 'int'
   }
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine-hmp-cmds.c
+++ b/hw/core/machine-hmp-cmds.c
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
         if (c->has_die_id) {
             monitor_printf(mon, "    die-id: \"%" PRIu64 "\"\n", c->die_id);
         }
+        if (c->has_cluster_id) {
+            monitor_printf(mon, "    cluster-id: \"%" PRIu64 "\"\n",
+                           c->cluster_id);
+        }
         if (c->has_core_id) {
             monitor_printf(mon, "    core-id: \"%" PRIu64 "\"\n", c->core_id);
         }
diff --git a/hw/core/machine.c b/hw/core/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
             return;
         }
 
+        if (props->has_cluster_id && !slot->props.has_cluster_id) {
+            error_setg(errp, "cluster-id is not supported");
+            return;
+        }
+
         if (props->has_socket_id && !slot->props.has_socket_id) {
             error_setg(errp, "socket-id is not supported");
             return;
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
                 continue;
         }
 
+        if (props->has_cluster_id &&
+            props->cluster_id != slot->props.cluster_id) {
+                continue;
+        }
+
         if (props->has_die_id && props->die_id != slot->props.die_id) {
                 continue;
         }
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
         }
         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
     }
+    if (cpu->props.has_cluster_id) {
+        if (s->len) {
+            g_string_append_printf(s, ", ");
+        }
+        g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
+    }
     if (cpu->props.has_core_id) {
         if (s->len) {
             g_string_append_printf(s, ", ");
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

The CPU topology isn't enabled on arm/virt machine yet, but we're
going to do it in next patch. After the CPU topology is enabled by
next patch, "thread-id=1" becomes invalid because the CPU core is
preferred on arm/virt machine. It means these two CPUs have 0/1
as their core IDs, but their thread IDs are all 0. It will trigger
test failure as the following message indicates:

[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test  ERROR
  1.48s   killed by signal 6 SIGABRT
  >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
      QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon         \
      QTEST_QEMU_BINARY=./qemu-system-aarch64                                       \
      QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83                                  \
      /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
  ――――――――――――――――――――――――――――――――――――――――――――――
  stderr:
  qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found

This fixes the issue by providing comprehensive SMP configurations
in aarch64_numa_cpu(). The SMP configurations aren't used before
the CPU topology is enabled in next patch.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/numa-test.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Gavin Shan <gshan@redhat.com>

Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.

This takes account of SMP configuration when the CPU topology
is populated. The die ID for the given CPU isn't assigned since
it's not supported on arm/virt machine. Besides, the used SMP
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
to avoid testing failure

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-4-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
     int n;
     unsigned int max_cpus = ms->smp.max_cpus;
     VirtMachineState *vms = VIRT_MACHINE(ms);
+    MachineClass *mc = MACHINE_GET_CLASS(vms);
 
     if (ms->possible_cpus) {
         assert(ms->possible_cpus->len == max_cpus);
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
         ms->possible_cpus->cpus[n].type = ms->cpu_type;
         ms->possible_cpus->cpus[n].arch_id =
             virt_cpu_mp_affinity(vms, n);
+
+        assert(!mc->smp_props.dies_supported);
+        ms->possible_cpus->cpus[n].props.has_socket_id = true;
+        ms->possible_cpus->cpus[n].props.socket_id =
+            n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
+        ms->possible_cpus->cpus[n].props.has_cluster_id = true;
+        ms->possible_cpus->cpus[n].props.cluster_id =
+            (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
+        ms->possible_cpus->cpus[n].props.has_core_id = true;
+        ms->possible_cpus->cpus[n].props.core_id =
+            (n / ms->smp.threads) % ms->smp.cores;
         ms->possible_cpus->cpus[n].props.has_thread_id = true;
-        ms->possible_cpus->cpus[n].props.thread_id = n;
+        ms->possible_cpus->cpus[n].props.thread_id =
+            n % ms->smp.threads;
     }
     return ms->possible_cpus;
 }
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

In aarch64_numa_cpu(), the CPU and NUMA association is something
like below. Two threads in the same core/cluster/socket are
associated with two individual NUMA nodes, which is unreal as
Igor Mammedov mentioned. We don't expect the association to break
NUMA-to-socket boundary, which matches with the real world.

NUMA-node  socket  cluster   core   thread
    ------------------------------------------
        0       0        0        0      0
        1       0        0        0      1

This corrects the topology for CPUs and their association with
NUMA nodes. After this patch is applied, the CPU and NUMA
association becomes something like below, which looks real.
Besides, socket/cluster/core/thread IDs are all checked when
the NUMA node IDs are verified. It helps to check if the CPU
topology is properly populated or not.

NUMA-node  socket  cluster   core   thread
    ------------------------------------------
       0        1        0        0       0
       1        0        0        0       0

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-5-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/numa-test.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/numa-test.c
+++ b/tests/qtest/numa-test.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
     g_autofree char *cli = NULL;
 
     cli = make_cli(data, "-machine "
-        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+        "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
-        "-numa cpu,node-id=1,thread-id=0 "
-        "-numa cpu,node-id=0,thread-id=1");
+        "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
+        "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
     qts = qtest_init(cli);
     cpus = get_cpus(qts, &resp);
     g_assert(cpus);
 
     while ((e = qlist_pop(cpus))) {
         QDict *cpu, *props;
-        int64_t thread, node;
+        int64_t socket, cluster, core, thread, node;
 
         cpu = qobject_to(QDict, e);
         g_assert(qdict_haskey(cpu, "props"));
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
 
         g_assert(qdict_haskey(props, "node-id"));
         node = qdict_get_int(props, "node-id");
+        g_assert(qdict_haskey(props, "socket-id"));
+        socket = qdict_get_int(props, "socket-id");
+        g_assert(qdict_haskey(props, "cluster-id"));
+        cluster = qdict_get_int(props, "cluster-id");
+        g_assert(qdict_haskey(props, "core-id"));
+        core = qdict_get_int(props, "core-id");
         g_assert(qdict_haskey(props, "thread-id"));
         thread = qdict_get_int(props, "thread-id");
 
-        if (thread == 0) {
+        if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
             g_assert_cmpint(node, ==, 1);
-        } else if (thread == 1) {
+        } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
             g_assert_cmpint(node, ==, 0);
         } else {
             g_assert(false);
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.

For example, the following warning messages are observed when the
Linux guest is booted with the following command lines.

/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
  -accel kvm -machine virt,gic-version=host               \
  -cpu host                                               \
  -smp 6,sockets=2,cores=3,threads=1                      \
  -m 1024M,slots=16,maxmem=64G                            \
  -object memory-backend-ram,id=mem0,size=128M            \
  -object memory-backend-ram,id=mem1,size=128M            \
  -object memory-backend-ram,id=mem2,size=128M            \
  -object memory-backend-ram,id=mem3,size=128M            \
  -object memory-backend-ram,id=mem4,size=128M            \
  -object memory-backend-ram,id=mem4,size=384M            \
  -numa node,nodeid=0,memdev=mem0                         \
  -numa node,nodeid=1,memdev=mem1                         \
  -numa node,nodeid=2,memdev=mem2                         \
  -numa node,nodeid=3,memdev=mem3                         \
  -numa node,nodeid=4,memdev=mem4                         \
  -numa node,nodeid=5,memdev=mem5
         :
  alternatives: patching kernel code
  BUG: arch topology borken
  the CLS domain not a subset of the MC domain
  <the above error log repeats>
  BUG: arch topology borken
  the DIE domain not a subset of the NODE domain

With current implementation of mc->get_default_cpu_node_id(),
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
That's incorrect because CPU#0/1/2 should be associated with same
NUMA node because they're seated in same socket.

This fixes the issue by considering the socket ID when the default
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
With this applied, no more CPU topology broken warnings are seen
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
there are no CPUs associated with NODE#2/3/4/5.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 
 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
 {
-    return idx % ms->numa_state->num_nodes;
+    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
+
+    return socket_id % ms->numa_state->num_nodes;
 }
 
 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.

This reworks build_pptt() to avoid by reusing the existing IDs in
ms->possible_cpus. Currently, the only user of build_pptt() is
arm/virt machine.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Tested-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20220503140304.855514-7-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
 1 file changed, 48 insertions(+), 63 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
                 const char *oem_id, const char *oem_table_id)
 {
     MachineClass *mc = MACHINE_GET_CLASS(ms);
-    GQueue *list = g_queue_new();
-    guint pptt_start = table_data->len;
-    guint parent_offset;
-    guint length, i;
-    int uid = 0;
-    int socket;
+    CPUArchIdList *cpus = ms->possible_cpus;
+    int64_t socket_id = -1, cluster_id = -1, core_id = -1;
+    uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
+    uint32_t pptt_start = table_data->len;
+    int n;
     AcpiTable table = { .sig = "PPTT", .rev = 2,
                         .oem_id = oem_id, .oem_table_id = oem_table_id };
 
     acpi_table_begin(&table, table_data);
 
-    for (socket = 0; socket < ms->smp.sockets; socket++) {
-        g_queue_push_tail(list,
-            GUINT_TO_POINTER(table_data->len - pptt_start));
-        build_processor_hierarchy_node(
-            table_data,
-            /*
-             * Physical package - represents the boundary
-             * of a physical package
-             */
-            (1 << 0),
-            0, socket, NULL, 0);
-    }
-
-    if (mc->smp_props.clusters_supported) {
-        length = g_queue_get_length(list);
-        for (i = 0; i < length; i++) {
-            int cluster;
-
-            parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-            for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
-                g_queue_push_tail(list,
-                    GUINT_TO_POINTER(table_data->len - pptt_start));
-                build_processor_hierarchy_node(
-                    table_data,
-                    (0 << 0), /* not a physical package */
-                    parent_offset, cluster, NULL, 0);
-            }
+    /*
+     * This works with the assumption that cpus[n].props.*_id has been
+     * sorted from top to down levels in mc->possible_cpu_arch_ids().
+     * Otherwise, the unexpected and duplicated containers will be
+     * created.
+     */
+    for (n = 0; n < cpus->len; n++) {
+        if (cpus->cpus[n].props.socket_id != socket_id) {
+            assert(cpus->cpus[n].props.socket_id > socket_id);
+            socket_id = cpus->cpus[n].props.socket_id;
+            cluster_id = -1;
+            core_id = -1;
+            socket_offset = table_data->len - pptt_start;
+            build_processor_hierarchy_node(table_data,
+                (1 << 0), /* Physical package */
+                0, socket_id, NULL, 0);
         }
-    }
 
-    length = g_queue_get_length(list);
-    for (i = 0; i < length; i++) {
-        int core;
-
-        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-        for (core = 0; core < ms->smp.cores; core++) {
-            if (ms->smp.threads > 1) {
-                g_queue_push_tail(list,
-                    GUINT_TO_POINTER(table_data->len - pptt_start));
-                build_processor_hierarchy_node(
-                    table_data,
-                    (0 << 0), /* not a physical package */
-                    parent_offset, core, NULL, 0);
-            } else {
-                build_processor_hierarchy_node(
-                    table_data,
-                    (1 << 1) | /* ACPI Processor ID valid */
-                    (1 << 3),  /* Node is a Leaf */
-                    parent_offset, uid++, NULL, 0);
+        if (mc->smp_props.clusters_supported) {
+            if (cpus->cpus[n].props.cluster_id != cluster_id) {
+                assert(cpus->cpus[n].props.cluster_id > cluster_id);
+                cluster_id = cpus->cpus[n].props.cluster_id;
+                core_id = -1;
+                cluster_offset = table_data->len - pptt_start;
+                build_processor_hierarchy_node(table_data,
+                    (0 << 0), /* Not a physical package */
+                    socket_offset, cluster_id, NULL, 0);
             }
+        } else {
+            cluster_offset = socket_offset;
         }
-    }
 
-    length = g_queue_get_length(list);
-    for (i = 0; i < length; i++) {
-        int thread;
+        if (ms->smp.threads == 1) {
+            build_processor_hierarchy_node(table_data,
+                (1 << 1) | /* ACPI Processor ID valid */
+                (1 << 3),  /* Node is a Leaf */
+                cluster_offset, n, NULL, 0);
+        } else {
+            if (cpus->cpus[n].props.core_id != core_id) {
+                assert(cpus->cpus[n].props.core_id > core_id);
+                core_id = cpus->cpus[n].props.core_id;
+                core_offset = table_data->len - pptt_start;
+                build_processor_hierarchy_node(table_data,
+                    (0 << 0), /* Not a physical package */
+                    cluster_offset, core_id, NULL, 0);
+            }
 
-        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-        for (thread = 0; thread < ms->smp.threads; thread++) {
-            build_processor_hierarchy_node(
-                table_data,
+            build_processor_hierarchy_node(table_data,
                 (1 << 1) | /* ACPI Processor ID valid */
                 (1 << 2) | /* Processor is a Thread */
                 (1 << 3),  /* Node is a Leaf */
-                parent_offset, uid++, NULL, 0);
+                core_offset, n, NULL, 0);
         }
     }
 
-    g_queue_free(list);
     acpi_table_end(linker, &table);
 }
 
-- 
2.25.1

I might squeeze in another pullreq before softfreeze, but the
queue was already big enough that I wanted to send this lot out now.

-- PMM

The following changes since commit 4abf70a661a5df3886ac9d7c19c3617fa92b922a:

Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging (2020-07-03 15:34:45 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200703

for you to fetch changes up to 0f10bf84a9d489259a5b11c6aa1b05c1175b76ea:

Deprecate TileGX port (2020-07-03 16:59:46 +0100)

----------------------------------------------------------------
target-arm queue:
 * i.MX6UL EVK board: put PHYs in the correct places
 * hw/arm/virt: Let the virtio-iommu bypass MSIs
 * target/arm: kvm: Handle DABT with no valid ISS
 * hw/arm/virt-acpi-build: Only expose flash on older machine types
 * target/arm: Fix temp double-free in sve ldr/str
 * hw/display/bcm2835_fb.c: Initialize all fields of struct
 * hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak
 * Deprecate TileGX port

----------------------------------------------------------------
Andrew Jones (4):
      tests/acpi: remove stale allowed tables
      tests/acpi: virt: allow DSDT acpi table changes
      hw/arm/virt-acpi-build: Only expose flash on older machine types
      tests/acpi: virt: update golden masters for DSDT

Beata Michalska (2):
      target/arm: kvm: Handle DABT with no valid ISS
      target/arm: kvm: Handle misconfigured dabt injection

Eric Auger (5):
      qdev: Introduce DEFINE_PROP_RESERVED_REGION
      virtio-iommu: Implement RESV_MEM probe request
      virtio-iommu: Handle reserved regions in the translation process
      virtio-iommu-pci: Add array of Interval properties
      hw/arm/virt: Let the virtio-iommu bypass MSIs

Jean-Christophe Dubois (3):
      Add a phy-num property to the i.MX FEC emulator
      Add the ability to select a different PHY for each i.MX6UL FEC interface
      Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.

Peter Maydell (19):
      hw/display/bcm2835_fb.c: Initialize all fields of struct
      hw/arm/spitz: Detabify
      hw/arm/spitz: Create SpitzMachineClass abstract base class
      hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
      hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
      hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
      hw/misc/max111x: provide QOM properties for setting initial values
      hw/misc/max111x: Don't use vmstate_register()
      ssi: Add ssi_realize_and_unref()
      hw/arm/spitz: Use max111x properties to set initial values
      hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
      hw/misc/max111x: Create header file for documentation, TYPE_ macros
      hw/arm/spitz: Encapsulate misc GPIO handling in a device
      hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
      hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
      hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
      hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
      Replace uses of FROM_SSI_SLAVE() macro with QOM casts
      Deprecate TileGX port

Richard Henderson (1):
      target/arm: Fix temp double-free in sve ldr/str

From: Jean-Christophe Dubois <jcd@tribudubois.net>

We need a solution to use an Ethernet PHY that is not the first device
on the MDIO bus (device 0 on MDIO bus).

As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but
only one MDIO bus on which the 2 related PHY are connected but at unique
addresses.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/net/imx_fec.h |  1 +
 hw/net/imx_fec.c         | 24 +++++++++++++++++-------
 hw/net/trace-events      |  4 ++--
 3 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/net/imx_fec.h
+++ b/include/hw/net/imx_fec.h
@@ -XXX,XX +XXX,XX @@ typedef struct IMXFECState {
     uint32_t phy_advertise;
     uint32_t phy_int;
     uint32_t phy_int_mask;
+    uint32_t phy_num;
 
     bool is_fec;
 
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_phy_reset(IMXFECState *s)
 static uint32_t imx_phy_read(IMXFECState *s, int reg)
 {
     uint32_t val;
+    uint32_t phy = reg / 32;
 
-    if (reg > 31) {
-        /* we only advertise one phy */
+    if (phy != s->phy_num) {
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
+                      TYPE_IMX_FEC, __func__, phy);
         return 0;
     }
 
+    reg %= 32;
+
     switch (reg) {
     case 0:     /* Basic Control */
         val = s->phy_control;
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
         break;
     }
 
-    trace_imx_phy_read(val, reg);
+    trace_imx_phy_read(val, phy, reg);
 
     return val;
 }
 
 static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
 {
-    trace_imx_phy_write(val, reg);
+    uint32_t phy = reg / 32;
 
-    if (reg > 31) {
-        /* we only advertise one phy */
+    if (phy != s->phy_num) {
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
+                      TYPE_IMX_FEC, __func__, phy);
         return;
     }
 
+    reg %= 32;
+
+    trace_imx_phy_write(val, phy, reg);
+
     switch (reg) {
     case 0:     /* Basic Control */
         if (val & 0x8000) {
@@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
                                                        extract32(value,
                                                                  18, 10)));
         } else {
-            /* This a write operation */
+            /* This is a write operation */
             imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
         }
         /* raise the interrupt as the PHY operation is done */
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
 static Property imx_eth_properties[] = {
     DEFINE_NIC_PROPERTIES(IMXFECState, conf),
     DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
+    DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/net/trace-events b/hw/net/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
 i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
 
 # imx_fec.c
-imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
-imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
+imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
+imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
 imx_phy_update_link(const char *s) "%s"
 imx_phy_reset(void) ""
 imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
-- 
2.20.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

Add properties to the i.MX6UL processor to be able to select a
particular PHY on the MDIO bus for each FEC device.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 ++
 hw/arm/fsl-imx6ul.c         | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
     MemoryRegion       caam;
     MemoryRegion       ocram;
     MemoryRegion       ocram_alias;
+
+    uint32_t           phy_num[FSL_IMX6UL_NUM_ETHS];
 } FslIMX6ULState;
 
 enum FslIMX6ULMemoryMap {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_ENET2_TIMER_IRQ,
         };
 
+        object_property_set_uint(OBJECT(&s->eth[i]),
+                                 s->phy_num[i],
+                                 "phy-num", &error_abort);
         object_property_set_uint(OBJECT(&s->eth[i]),
                                  FSL_IMX6UL_ETH_NUM_TX_RINGS,
                                  "tx-ring-num", &error_abort);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
 }
 
+static Property fsl_imx6ul_properties[] = {
+    DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
+    DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
+    device_class_set_props(dc, fsl_imx6ul_properties);
     dc->realize = fsl_imx6ul_realize;
     dc->desc = "i.MX6UL SOC";
     /* Reason: Uses serial_hds and nd_table in realize() directly */
-- 
2.20.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The i.MX6UL EVK 14x14 board uses:
- PHY 2 for FEC 1
- PHY 1 for FEC 2

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: fb41992126c091a71d76ab3d1898959091f60583.1593296112.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mcimx6ul-evk.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
 
     s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
     object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
+    object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal);
+    object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal);
     qdev_realize(DEVICE(s), NULL, &error_fatal);
 
     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

Introduce a new property defining a reserved region:
<low address>:<high address>:<type>.

This will be used to encode reserved IOVA regions.

For instance, in virtio-iommu use case, reserved IOVA regions
will be passed by the machine code to the virtio-iommu-pci
device (an array of those). The type of the reserved region
will match the virtio_iommu_probe_resv_mem subtype value:
- VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0)
- VIRTIO_IOMMU_RESV_MEM_T_MSI (1)

on PC/Q35 machine, this will be used to inform the
virtio-iommu-pci device it should bypass the MSI region.
The reserved region will be: 0xfee00000:0xfeefffff:1.

On ARM, we can declare the ITS MSI doorbell as an MSI
region to prevent MSIs from being mapped on guest side.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20200629070404.10969-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/memory.h        |  6 +++
 include/hw/qdev-properties.h |  3 ++
 include/qemu/typedefs.h      |  1 +
 hw/core/qdev-properties.c    | 89 ++++++++++++++++++++++++++++++++++++
 4 files changed, 99 insertions(+)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ extern bool global_dirty_log;
 
 typedef struct MemoryRegionOps MemoryRegionOps;
 
+struct ReservedRegion {
+    hwaddr low;
+    hwaddr high;
+    unsigned type;
+};
+
 typedef struct IOMMUTLBEntry IOMMUTLBEntry;
 
 /* See address_space_translate: bit 0 is read, bit 1 is write.  */
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_string;
 extern const PropertyInfo qdev_prop_chr;
 extern const PropertyInfo qdev_prop_tpm;
 extern const PropertyInfo qdev_prop_macaddr;
+extern const PropertyInfo qdev_prop_reserved_region;
 extern const PropertyInfo qdev_prop_on_off_auto;
 extern const PropertyInfo qdev_prop_multifd_compression;
 extern const PropertyInfo qdev_prop_losttickpolicy;
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_width;
     DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *)
 #define DEFINE_PROP_MACADDR(_n, _s, _f)         \
     DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
+#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f)         \
+    DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion)
 #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
 #define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -XXX,XX +XXX,XX @@ typedef struct ISABus ISABus;
 typedef struct ISADevice ISADevice;
 typedef struct IsaDma IsaDma;
 typedef struct MACAddr MACAddr;
+typedef struct ReservedRegion ReservedRegion;
 typedef struct MachineClass MachineClass;
 typedef struct MachineState MachineState;
 typedef struct MemoryListener MemoryListener;
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -XXX,XX +XXX,XX @@
 #include "chardev/char.h"
 #include "qemu/uuid.h"
 #include "qemu/units.h"
+#include "qemu/cutils.h"
 
 void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
                                   Error **errp)
@@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_macaddr = {
     .set   = set_mac,
 };
 
+/* --- Reserved Region --- */
+
+/*
+ * Accepted syntax:
+ *   <low address>:<high address>:<type>
+ *   where low/high addresses are uint64_t in hexadecimal
+ *   and type is a non-negative decimal integer
+ */
+static void get_reserved_region(Object *obj, Visitor *v, const char *name,
+                                void *opaque, Error **errp)
+{
+    DeviceState *dev = DEVICE(obj);
+    Property *prop = opaque;
+    ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
+    char buffer[64];
+    char *p = buffer;
+    int rc;
+
+    rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u",
+                  rr->low, rr->high, rr->type);
+    assert(rc < sizeof(buffer));
+
+    visit_type_str(v, name, &p, errp);
+}
+
+static void set_reserved_region(Object *obj, Visitor *v, const char *name,
+                                void *opaque, Error **errp)
+{
+    DeviceState *dev = DEVICE(obj);
+    Property *prop = opaque;
+    ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
+    Error *local_err = NULL;
+    const char *endptr;
+    char *str;
+    int ret;
+
+    if (dev->realized) {
+        qdev_prop_set_after_realize(dev, name, errp);
+        return;
+    }
+
+    visit_type_str(v, name, &str, &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    ret = qemu_strtou64(str, &endptr, 16, &rr->low);
+    if (ret) {
+        error_setg(errp, "start address of '%s'"
+                   " must be a hexadecimal integer", name);
+        goto out;
+    }
+    if (*endptr != ':') {
+        goto separator_error;
+    }
+
+    ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high);
+    if (ret) {
+        error_setg(errp, "end address of '%s'"
+                   " must be a hexadecimal integer", name);
+        goto out;
+    }
+    if (*endptr != ':') {
+        goto separator_error;
+    }
+
+    ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type);
+    if (ret) {
+        error_setg(errp, "type of '%s'"
+                   " must be a non-negative decimal integer", name);
+    }
+    goto out;
+
+separator_error:
+    error_setg(errp, "reserved region fields must be separated with ':'");
+out:
+    g_free(str);
+    return;
+}
+
+const PropertyInfo qdev_prop_reserved_region = {
+    .name  = "reserved_region",
+    .description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0",
+    .get   = get_reserved_region,
+    .set   = set_reserved_region,
+};
+
 /* --- on/off/auto --- */
 
 const PropertyInfo qdev_prop_on_off_auto = {
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

This patch implements the PROBE request. At the moment,
only THE RESV_MEM property is handled. The first goal is
to report iommu wide reserved regions such as the MSI regions
set by the machine code. On x86 this will be the IOAPIC MSI
region, [0xFEE00000 - 0xFEEFFFFF], on ARM this may be the ITS
doorbell.

In the future we may introduce per device reserved regions.
This will be useful when protecting host assigned devices
which may expose their own reserved regions

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20200629070404.10969-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/virtio/virtio-iommu.h |  2 +
 hw/virtio/virtio-iommu.c         | 94 ++++++++++++++++++++++++++++++--
 hw/virtio/trace-events           |  1 +
 3 files changed, 93 insertions(+), 4 deletions(-)

diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/virtio/virtio-iommu.h
+++ b/include/hw/virtio/virtio-iommu.h
@@ -XXX,XX +XXX,XX @@ typedef struct VirtIOIOMMU {
     GHashTable *as_by_busptr;
     IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX];
     PCIBus *primary_bus;
+    ReservedRegion *reserved_regions;
+    uint32_t nb_reserved_regions;
     GTree *domains;
     QemuMutex mutex;
     GTree *endpoints;
diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/virtio-iommu.c
+++ b/hw/virtio/virtio-iommu.c
@@ -XXX,XX +XXX,XX @@
 
 /* Max size */
 #define VIOMMU_DEFAULT_QUEUE_SIZE 256
+#define VIOMMU_PROBE_SIZE 512
 
 typedef struct VirtIOIOMMUDomain {
     uint32_t id;
@@ -XXX,XX +XXX,XX @@ static int virtio_iommu_unmap(VirtIOIOMMU *s,
     return ret;
 }
 
+static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep,
+                                               uint8_t *buf, size_t free)
+{
+    struct virtio_iommu_probe_resv_mem prop = {};
+    size_t size = sizeof(prop), length = size - sizeof(prop.head), total;
+    int i;
+
+    total = size * s->nb_reserved_regions;
+
+    if (total > free) {
+        return -ENOSPC;
+    }
+
+    for (i = 0; i < s->nb_reserved_regions; i++) {
+        unsigned subtype = s->reserved_regions[i].type;
+
+        assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED ||
+               subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI);
+        prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM);
+        prop.head.length = cpu_to_le16(length);
+        prop.subtype = subtype;
+        prop.start = cpu_to_le64(s->reserved_regions[i].low);
+        prop.end = cpu_to_le64(s->reserved_regions[i].high);
+
+        memcpy(buf, &prop, size);
+
+        trace_virtio_iommu_fill_resv_property(ep, prop.subtype,
+                                              prop.start, prop.end);
+        buf += size;
+    }
+    return total;
+}
+
+/**
+ * virtio_iommu_probe - Fill the probe request buffer with
+ * the properties the device is able to return
+ */
+static int virtio_iommu_probe(VirtIOIOMMU *s,
+                              struct virtio_iommu_req_probe *req,
+                              uint8_t *buf)
+{
+    uint32_t ep_id = le32_to_cpu(req->endpoint);
+    size_t free = VIOMMU_PROBE_SIZE;
+    ssize_t count;
+
+    if (!virtio_iommu_mr(s, ep_id)) {
+        return VIRTIO_IOMMU_S_NOENT;
+    }
+
+    count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free);
+    if (count < 0) {
+        return VIRTIO_IOMMU_S_INVAL;
+    }
+    buf += count;
+    free -= count;
+
+    return VIRTIO_IOMMU_S_OK;
+}
+
 static int virtio_iommu_iov_to_req(struct iovec *iov,
                                    unsigned int iov_cnt,
                                    void *req, size_t req_sz)
@@ -XXX,XX +XXX,XX @@ virtio_iommu_handle_req(detach)
 virtio_iommu_handle_req(map)
 virtio_iommu_handle_req(unmap)
 
+static int virtio_iommu_handle_probe(VirtIOIOMMU *s,
+                                     struct iovec *iov,
+                                     unsigned int iov_cnt,
+                                     uint8_t *buf)
+{
+    struct virtio_iommu_req_probe req;
+    int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req));
+
+    return ret ? ret : virtio_iommu_probe(s, &req, buf);
+}
+
 static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
 {
     VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
     struct virtio_iommu_req_head head;
     struct virtio_iommu_req_tail tail = {};
+    size_t output_size = sizeof(tail), sz;
     VirtQueueElement *elem;
     unsigned int iov_cnt;
     struct iovec *iov;
-    size_t sz;
+    void *buf = NULL;
 
     for (;;) {
         elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
         case VIRTIO_IOMMU_T_UNMAP:
             tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
             break;
+        case VIRTIO_IOMMU_T_PROBE:
+        {
+            struct virtio_iommu_req_tail *ptail;
+
+            output_size = s->config.probe_size + sizeof(tail);
+            buf = g_malloc0(output_size);
+
+            ptail = (struct virtio_iommu_req_tail *)
+                        (buf + s->config.probe_size);
+            ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf);
+        }
         default:
             tail.status = VIRTIO_IOMMU_S_UNSUPP;
         }
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
 
 out:
         sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
-                          &tail, sizeof(tail));
-        assert(sz == sizeof(tail));
+                          buf ? buf : &tail, output_size);
+        assert(sz == output_size);
 
-        virtqueue_push(vq, elem, sizeof(tail));
+        virtqueue_push(vq, elem, sz);
         virtio_notify(vdev, vq);
         g_free(elem);
+        g_free(buf);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
     s->config.page_size_mask = TARGET_PAGE_MASK;
     s->config.input_range.end = -1UL;
     s->config.domain_range.end = 32;
+    s->config.probe_size = VIOMMU_PROBE_SIZE;
 
     virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX);
     virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC);
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
     virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP);
     virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS);
     virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO);
+    virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE);
 
     qemu_mutex_init(&s->mutex);
 
diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/trace-events
+++ b/hw/virtio/trace-events
@@ -XXX,XX +XXX,XX @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d"
 virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d"
 virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d"
 virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64
+virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

When translating an address we need to check if it belongs to
a reserved virtual address range. If it does, there are 2 cases:

- it belongs to a RESERVED region: the guest should neither use
  this address in a MAP not instruct the end-point to DMA on
  them. We report an error

- It belongs to an MSI region: we bypass the translation.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20200629070404.10969-4-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/virtio/virtio-iommu.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/virtio-iommu.c
+++ b/hw/virtio/virtio-iommu.c
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
     uint32_t sid, flags;
     bool bypass_allowed;
     bool found;
+    int i;
 
     interval.low = addr;
     interval.high = addr + 1;
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
         goto unlock;
     }
 
+    for (i = 0; i < s->nb_reserved_regions; i++) {
+        ReservedRegion *reg = &s->reserved_regions[i];
+
+        if (addr >= reg->low && addr <= reg->high) {
+            switch (reg->type) {
+            case VIRTIO_IOMMU_RESV_MEM_T_MSI:
+                entry.perm = flag;
+                break;
+            case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:
+            default:
+                virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING,
+                                          VIRTIO_IOMMU_FAULT_F_ADDRESS,
+                                          sid, addr);
+                break;
+            }
+            goto unlock;
+        }
+    }
+
     if (!ep->domain) {
         if (!bypass_allowed) {
             error_report_once("%s %02x:%02x.%01x not attached to any domain",
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

The machine may need to pass reserved regions to the
virtio-iommu-pci device (such as the MSI window on x86
or the MSI doorbells on ARM).

So let's add an array of Interval properties.

Note: if some reserved regions are already set by the
machine code - which should be the case in general -,
the length of the property array is already set and
prevents the end-user from modifying them. For example,
attempting to use:

-device virtio-iommu-pci,\
 len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1

would result in the following error message:

qemu-system-aarch64: -device virtio-iommu-pci,addr=0xa,
len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1:
array size property len-reserved-regions may not be set more than once

Otherwise, for example, adding two reserved regions is achieved
using the following options:

-device virtio-iommu-pci,addr=0xa,len-reserved-regions=2,\
 reserved-regions[0]=0xfee00000:0xfeefffff:1,\
 reserved-regions[1]=0x1000000:100ffff:1

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-id: 20200629070404.10969-5-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/virtio/virtio-iommu-pci.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/virtio-iommu-pci.c
+++ b/hw/virtio/virtio-iommu-pci.c
@@ -XXX,XX +XXX,XX @@ struct VirtIOIOMMUPCI {
 
 static Property virtio_iommu_pci_properties[] = {
     DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
+    DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI,
+                      vdev.nb_reserved_regions, vdev.reserved_regions,
+                      qdev_prop_reserved_region, ReservedRegion),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
 {
     VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev);
     DeviceState *vdev = DEVICE(&dev->vdev);
+    VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
 
     if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
         MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
                           "-no-acpi\n");
         return;
     }
+    for (int i = 0; i < s->nb_reserved_regions; i++) {
+        if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED &&
+            s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) {
+            error_setg(errp, "reserved region %d has an invalid type", i);
+            error_append_hint(errp, "Valid values are 0 and 1\n");
+        }
+    }
     object_property_set_link(OBJECT(dev),
                              OBJECT(pci_get_bus(&vpci_dev->pci_dev)),
                              "primary-bus", &error_abort);
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

At the moment the virtio-iommu translates MSI transactions.
This behavior is inherited from ARM SMMU. The virt machine
code knows where the guest MSI doorbells are so we can easily
declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
setting the guest will not map MSIs through the IOMMU and those
transactions will be simply bypassed.

Depending on which MSI controller is in use (ITS or GICV2M),
we declare either:
- the ITS interrupt translation space (ITS_base + 0x10000),
  containing the GITS_TRANSLATOR or
- The GICV2M single frame, containing the MSI_SETSP_NS register.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20200629070404.10969-6-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h |  7 +++++++
 hw/arm/virt.c         | 30 ++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
     VIRT_IOMMU_VIRTIO,
 } VirtIOMMUType;
 
+typedef enum VirtMSIControllerType {
+    VIRT_MSI_CTRL_NONE,
+    VIRT_MSI_CTRL_GICV2M,
+    VIRT_MSI_CTRL_ITS,
+} VirtMSIControllerType;
+
 typedef enum VirtGICType {
     VIRT_GIC_VERSION_MAX,
     VIRT_GIC_VERSION_HOST,
@@ -XXX,XX +XXX,XX @@ typedef struct {
     OnOffAuto acpi;
     VirtGICType gic_version;
     VirtIOMMUType iommu;
+    VirtMSIControllerType msi_controller;
     uint16_t virtio_iommu_bdf;
     struct arm_boot_info bootinfo;
     MemMapEntry *memmap;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_its(VirtMachineState *vms)
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
 
     fdt_add_its_gic_node(vms);
+    vms->msi_controller = VIRT_MSI_CTRL_ITS;
 }
 
 static void create_v2m(VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms)
     }
 
     fdt_add_v2m_gic_node(vms);
+    vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
 }
 
 static void create_gic(VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ out:
 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
                                             DeviceState *dev, Error **errp)
 {
+    VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
+
     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
         virt_memory_pre_plug(hotplug_dev, dev, errp);
+    } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
+        hwaddr db_start = 0, db_end = 0;
+        char *resv_prop_str;
+
+        switch (vms->msi_controller) {
+        case VIRT_MSI_CTRL_NONE:
+            return;
+        case VIRT_MSI_CTRL_ITS:
+            /* GITS_TRANSLATER page */
+            db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
+            db_end = base_memmap[VIRT_GIC_ITS].base +
+                     base_memmap[VIRT_GIC_ITS].size - 1;
+            break;
+        case VIRT_MSI_CTRL_GICV2M:
+            /* MSI_SETSPI_NS page */
+            db_start = base_memmap[VIRT_GIC_V2M].base;
+            db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
+            break;
+        }
+        resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
+                                        db_start, db_end,
+                                        VIRTIO_IOMMU_RESV_MEM_T_MSI);
+
+        qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
+        qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
+        g_free(resv_prop_str);
     }
 }
 
-- 
2.20.1

From: Beata Michalska <beata.michalska@linaro.org>

On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
exception with no valid ISS info to be decoded. The lack of decode info
makes it at least tricky to emulate those instruction which is one of the
(many) reasons why KVM will not even try to do so.

Add support for handling those by requesting KVM to inject external
dabt into the quest.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200629114110.30723-2-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
 
 static bool cap_has_mp_state;
 static bool cap_has_inject_serror_esr;
+static bool cap_has_inject_ext_dabt;
 
 static ARMHostCPUFeatures arm_host_cpu_features;
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
         ret = -EINVAL;
     }
 
+    if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
+        if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) {
+            error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap");
+        } else {
+            /* Set status for supporting the external dabt injection */
+            cap_has_inject_ext_dabt = kvm_check_extension(s,
+                                    KVM_CAP_ARM_INJECT_EXT_DABT);
+        }
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
     }
 }
 
+/**
+ * kvm_arm_handle_dabt_nisv:
+ * @cs: CPUState
+ * @esr_iss: ISS encoding (limited) for the exception from Data Abort
+ *           ISV bit set to '0b0' -> no valid instruction syndrome
+ * @fault_ipa: faulting address for the synchronous data abort
+ *
+ * Returns: 0 if the exception has been handled, < 0 otherwise
+ */
+static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
+                                    uint64_t fault_ipa)
+{
+    /*
+     * Request KVM to inject the external data abort into the guest
+     */
+    if (cap_has_inject_ext_dabt) {
+        struct kvm_vcpu_events events = { };
+        /*
+         * The external data abort event will be handled immediately by KVM
+         * using the address fault that triggered the exit on given VCPU.
+         * Requesting injection of the external data abort does not rely
+         * on any other VCPU state. Therefore, in this particular case, the VCPU
+         * synchronization can be exceptionally skipped.
+         */
+        events.exception.ext_dabt_pending = 1;
+        /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
+        return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
+    } else {
+        error_report("Data abort exception triggered by guest memory access "
+                     "at physical address: 0x"  TARGET_FMT_lx,
+                     (target_ulong)fault_ipa);
+        error_printf("KVM unable to emulate faulting instruction.\n");
+    }
+    return -1;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
             ret = EXCP_DEBUG;
         } /* otherwise return to guest */
         break;
+    case KVM_EXIT_ARM_NISV:
+        /* External DABT with no valid iss to decode */
+        ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss,
+                                       run->arm_nisv.fault_ipa);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.20.1

From: Beata Michalska <beata.michalska@linaro.org>

Injecting external data abort through KVM might trigger
an issue on kernels that do not get updated to include the KVM fix.
For those and aarch32 guests, the injected abort gets misconfigured
to be an implementation defined exception. This leads to the guest
repeatedly re-running the faulting instruction.

Add support for handling that case.

[
  Fixed-by: 018f22f95e8a
	('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
  Fixed-by: 21aecdbd7f3a
	('KVM: arm: Make inject_abt32() inject an external abort instead')
]

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Acked-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200629114110.30723-3-beata.michalska@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |  2 ++
 target/arm/kvm_arm.h | 10 +++++++++
 target/arm/kvm.c     | 30 ++++++++++++++++++++++++++-
 target/arm/kvm32.c   | 34 ++++++++++++++++++++++++++++++
 target/arm/kvm64.c   | 49 ++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 124 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
         uint64_t esr;
     } serror;
 
+    uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
+
     /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
     uint32_t irq_line_state;
 
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_hw_debug_active(CPUState *cs);
 struct kvm_guest_debug_arch;
 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
 
+/**
+ * kvm_arm_verify_ext_dabt_pending:
+ * @cs: CPUState
+ *
+ * Verify the fault status code wrt the Ext DABT injection
+ *
+ * Returns: true if the fault status code is as expected, false otherwise
+ */
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
+
 /**
  * its_class_name:
  *
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu)
 
 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
 {
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+
+    if (unlikely(env->ext_dabt_raised)) {
+        /*
+         * Verifying that the ext DABT has been properly injected,
+         * otherwise risking indefinitely re-running the faulting instruction
+         * Covering a very narrow case for kernels 5.5..5.5.4
+         * when injected abort was misconfigured to be
+         * an IMPLEMENTATION DEFINED exception (for 32-bit EL1)
+         */
+        if (!arm_feature(env, ARM_FEATURE_AARCH64) &&
+            unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) {
+
+            error_report("Data abort exception with no valid ISS generated by "
+                   "guest memory access. KVM unable to emulate faulting "
+                   "instruction. Failed to inject an external data abort "
+                   "into the guest.");
+            abort();
+       }
+       /* Clear the status */
+       env->ext_dabt_raised = 0;
+    }
 }
 
 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
 static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
                                     uint64_t fault_ipa)
 {
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
     /*
      * Request KVM to inject the external data abort into the guest
      */
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
          */
         events.exception.ext_dabt_pending = 1;
         /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
-        return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
+        if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) {
+            env->ext_dabt_raised = 1;
+            return 0;
+        }
     } else {
         error_report("Data abort exception triggered by guest memory access "
                      "at physical address: 0x"  TARGET_FMT_lx,
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
 {
     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 }
+
+#define ARM_REG_DFSR  ARM_CP15_REG32(0, 5, 0, 0)
+#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
+/*
+ *DFSR:
+ *      TTBCR.EAE == 0
+ *          FS[4]   - DFSR[10]
+ *          FS[3:0] - DFSR[3:0]
+ *      TTBCR.EAE == 1
+ *          FS, bits [5:0]
+ */
+#define DFSR_FSC(lpae, v) \
+    ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
+
+#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
+
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
+{
+    uint32_t dfsr_val;
+
+    if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
+        ARMCPU *cpu = ARM_CPU(cs);
+        CPUARMState *env = &cpu->env;
+        uint32_t ttbcr;
+        int lpae = 0;
+
+        if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
+            lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
+        }
+        /* The verification is based on FS filed of the DFSR reg only*/
+        return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
+    }
+    return false;
+}
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 
     return false;
 }
+
+#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
+#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
+
+/*
+ * ESR_EL1
+ * ISS encoding
+ * AARCH64: DFSC,   bits [5:0]
+ * AARCH32:
+ *      TTBCR.EAE == 0
+ *          FS[4]   - DFSR[10]
+ *          FS[3:0] - DFSR[3:0]
+ *      TTBCR.EAE == 1
+ *          FS, bits [5:0]
+ */
+#define ESR_DFSC(aarch64, lpae, v)        \
+    ((aarch64 || (lpae)) ? ((v) & 0x3F)   \
+               : (((v) >> 6) | ((v) & 0x1F)))
+
+#define ESR_DFSC_EXTABT(aarch64, lpae) \
+    ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
+
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
+{
+    uint64_t dfsr_val;
+
+    if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
+        ARMCPU *cpu = ARM_CPU(cs);
+        CPUARMState *env = &cpu->env;
+        int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
+        int lpae = 0;
+
+        if (!aarch64_mode) {
+            uint64_t ttbcr;
+
+            if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
+                lpae = arm_feature(env, ARM_FEATURE_LPAE)
+                        && (ttbcr & TTBCR_EAE);
+            }
+        }
+        /*
+         * The verification here is based on the DFSC bits
+         * of the ESR_EL1 reg only
+         */
+         return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
+                ESR_DFSC_EXTABT(aarch64_mode, lpae));
+    }
+    return false;
+}
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Fixes: 93dd625f8bf7 ("tests/acpi: update expected data files")
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20200629140938.17566-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/bios-tables-test-allowed-diff.h | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,19 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/pc/DSDT",
-"tests/data/acpi/pc/DSDT.acpihmat",
-"tests/data/acpi/pc/DSDT.bridge",
-"tests/data/acpi/pc/DSDT.cphp",
-"tests/data/acpi/pc/DSDT.dimmpxm",
-"tests/data/acpi/pc/DSDT.ipmikcs",
-"tests/data/acpi/pc/DSDT.memhp",
-"tests/data/acpi/pc/DSDT.numamem",
-"tests/data/acpi/q35/DSDT",
-"tests/data/acpi/q35/DSDT.acpihmat",
-"tests/data/acpi/q35/DSDT.bridge",
-"tests/data/acpi/q35/DSDT.cphp",
-"tests/data/acpi/q35/DSDT.dimmpxm",
-"tests/data/acpi/q35/DSDT.ipmibt",
-"tests/data/acpi/q35/DSDT.memhp",
-"tests/data/acpi/q35/DSDT.mmio64",
-"tests/data/acpi/q35/DSDT.numamem",
-"tests/data/acpi/q35/DSDT.tis",
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

The flash device is exclusively for the host-controlled firmware, so
we should not expose it to the OS. Exposing it risks the OS messing
with it, which could break firmware runtime services and surprise the
OS when all its changes disappear after reboot.

As firmware needs the device and uses DT, we leave the device exposed
there. It's up to firmware to remove the nodes from DT before sending
it on to the OS. However, there's no need to force firmware to remove
tables from ACPI (which it doesn't know how to do anyway), so we
simply don't add the tables in the first place. But, as we've been
adding the tables for quite some time and don't want to change the
default hardware exposed to versioned machines, then we only stop
exposing the flash device tables for 5.1 and later machine types.

Suggested-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-id: 20200629140938.17566-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h    | 1 +
 hw/arm/virt-acpi-build.c | 5 ++++-
 hw/arm/virt.c            | 3 +++
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
     bool no_highmem_ecam;
     bool no_ged;   /* Machines < 4.2 has no support for ACPI GED device */
     bool kvm_no_adjvtime;
+    bool acpi_expose_flash;
 } VirtMachineClass;
 
 typedef struct {
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
 static void
 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 {
+    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
     Aml *scope, *dsdt;
     MachineState *ms = MACHINE(vms);
     const MemMapEntry *memmap = vms->memmap;
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     acpi_dsdt_add_cpus(scope, vms->smp_cpus);
     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
-    acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
+    if (vmc->acpi_expose_flash) {
+        acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
+    }
     acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
 
 static void virt_machine_5_0_options(MachineClass *mc)
 {
+    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
     virt_machine_5_1_options(mc);
     compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
     mc->numa_mem_supported = true;
+    vmc->acpi_expose_flash = true;
 }
 DEFINE_VIRT_MACHINE(5, 0)
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Differences between disassembled ASL files for DSDT:

@@ -XXX,XX +XXX,XX @@
  *
  * Disassembling to symbolic ASL+ operators
  *
- * Disassembly of a, Mon Jun 29 09:50:01 2020
+ * Disassembly of b, Mon Jun 29 09:50:03 2020
  *
  * Original Table Header:
  *     Signature        "DSDT"
- *     Length           0x000014BB (5307)
+ *     Length           0x00001455 (5205)
  *     Revision         0x02
- *     Checksum         0xD1
+ *     Checksum         0xE1
  *     OEM ID           "BOCHS "
  *     OEM Table ID     "BXPCDSDT"
  *     OEM Revision     0x00000001 (1)
@@ -XXX,XX +XXX,XX @@
             })
         }

-        Device (FLS0)
-        {
-            Name (_HID, "LNRO0015")  // _HID: Hardware ID
-            Name (_UID, Zero)  // _UID: Unique ID
-            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-            {
-                Memory32Fixed (ReadWrite,
-                    0x00000000,         // Address Base
-                    0x04000000,         // Address Length
-                    )
-            })
-        }
-
-        Device (FLS1)
-        {
-            Name (_HID, "LNRO0015")  // _HID: Hardware ID
-            Name (_UID, One)  // _UID: Unique ID
-            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-            {
-                Memory32Fixed (ReadWrite,
-                    0x04000000,         // Address Base
-                    0x04000000,         // Address Length
-                    )
-            })
-        }
-
         Device (FWCF)
         {
             Name (_HID, "QEMU0002")  // _HID: Hardware ID

The other two binaries have the same changes (the removal of the
flash devices).

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-id: 20200629140938.17566-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/bios-tables-test-allowed-diff.h |   3 ---
 tests/data/acpi/virt/DSDT                   | Bin 5307 -> 5205 bytes
 tests/data/acpi/virt/DSDT.memhp             | Bin 6668 -> 6566 bytes
 tests/data/acpi/virt/DSDT.numamem           | Bin 5307 -> 5205 bytes
 4 files changed, 3 deletions(-)

delta 156
zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
LaERl^1zUvy_;n(J

diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
index XXXXXXX..XXXXXXX 100644
GIT binary patch
delta 28
kcmeA%S!T@T66_MPOp<|tiD@F2G*jb@iRuX(-^xn@0CHUjRR910

delta 156
zcmZ2x++)J!66_MfBgMeL^l>7WG*kP$iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^
zE<n;bC|FRCi?5B7fsp|MSSlH!n?PC&v1wsM*TMqS1=eEW7Vhi@(GuwD8){%+U<5Qj
LIK*+|0yaqism~!^

diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem
index XXXXXXX..XXXXXXX 100644
GIT binary patch
delta 28
kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a

delta 156
zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
LaERl^1zUvy_;n(J

-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The temp that gets assigned to clean_addr has been allocated with
new_tmp_a64, which means that it will be freed at the end of the
instruction.  Freeing it earlier leads to assertion failure.

The loop creates a complication, in which we allocate a new local
temp, which does need freeing, and the final code path is shared
between the loop and non-loop.

Fix this complication by adding new_tmp_a64_local so that the new
local temp is freed at the end, and can be treated exactly like
the non-loop path.

Fixes: bba87d0a0f4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200702175605.1987125-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.h | 1 +
 target/arm/translate-a64.c | 6 ++++++
 target/arm/translate-sve.c | 8 ++------
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
     } while (0)
 
 TCGv_i64 new_tmp_a64(DisasContext *s);
+TCGv_i64 new_tmp_a64_local(DisasContext *s);
 TCGv_i64 new_tmp_a64_zero(DisasContext *s);
 TCGv_i64 cpu_reg(DisasContext *s, int reg);
 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ TCGv_i64 new_tmp_a64(DisasContext *s)
     return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
 }
 
+TCGv_i64 new_tmp_a64_local(DisasContext *s)
+{
+    assert(s->tmp_a64_count < TMP_A64_MAX);
+    return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64();
+}
+
 TCGv_i64 new_tmp_a64_zero(DisasContext *s)
 {
     TCGv_i64 t = new_tmp_a64(s);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
 
         /* Copy the clean address into a local temp, live across the loop. */
         t0 = clean_addr;
-        clean_addr = tcg_temp_local_new_i64();
+        clean_addr = new_tmp_a64_local(s);
         tcg_gen_mov_i64(clean_addr, t0);
-        tcg_temp_free_i64(t0);
 
         gen_set_label(loop);
 
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
         tcg_temp_free_i64(t0);
     }
-    tcg_temp_free_i64(clean_addr);
 }
 
 /* Similarly for stores.  */
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
 
         /* Copy the clean address into a local temp, live across the loop. */
         t0 = clean_addr;
-        clean_addr = tcg_temp_local_new_i64();
+        clean_addr = new_tmp_a64_local(s);
         tcg_gen_mov_i64(clean_addr, t0);
-        tcg_temp_free_i64(t0);
 
         gen_set_label(loop);
 
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         }
         tcg_temp_free_i64(t0);
     }
-    tcg_temp_free_i64(clean_addr);
 }
 
 static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
-- 
2.20.1

In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we
pass a pointer to a local struct to another function without
initializing all its fields.  This is a real bug:
bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig
struct into s->config, so any fields we don't initialize will corrupt
the state of the device.

Copy the two fields which we don't want to update (pixo and alpha)
from the existing config so we don't accidentally change them.

Fixes: cfb7ba983857e40e88
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200628195436.27582-1-peter.maydell@linaro.org
---
 hw/display/bcm2835_fb.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/bcm2835_fb.c
+++ b/hw/display/bcm2835_fb.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
     newconf.base = s->vcram_base | (value & 0xc0000000);
     newconf.base += BCM2835_FB_OFFSET;
 
+    /* Copy fields which we don't want to change from the existing config */
+    newconf.pixo = s->config.pixo;
+    newconf.alpha = s->config.alpha;
+
     bcm2835_fb_validate_config(&newconf);
 
     pitch = bcm2835_fb_get_pitch(&newconf);
-- 
2.20.1

The spitz board has been around a long time, and still has a fair number
of hard-coded tab characters in it. We're about to do some work on
this source file, so start out by expanding out the tabs.

This commit is a pure whitespace only change.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-2-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 156 ++++++++++++++++++++++++-------------------------
 1 file changed, 78 insertions(+), 78 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 
 #undef REG_FMT
-#define REG_FMT			"0x%02lx"
+#define REG_FMT                         "0x%02lx"
 
 /* Spitz Flash */
-#define FLASH_BASE		0x0c000000
-#define FLASH_ECCLPLB		0x00	/* Line parity 7 - 0 bit */
-#define FLASH_ECCLPUB		0x04	/* Line parity 15 - 8 bit */
-#define FLASH_ECCCP		0x08	/* Column parity 5 - 0 bit */
-#define FLASH_ECCCNTR		0x0c	/* ECC byte counter */
-#define FLASH_ECCCLRR		0x10	/* Clear ECC */
-#define FLASH_FLASHIO		0x14	/* Flash I/O */
-#define FLASH_FLASHCTL		0x18	/* Flash Control */
+#define FLASH_BASE              0x0c000000
+#define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
+#define FLASH_ECCLPUB           0x04    /* Line parity 15 - 8 bit */
+#define FLASH_ECCCP             0x08    /* Column parity 5 - 0 bit */
+#define FLASH_ECCCNTR           0x0c    /* ECC byte counter */
+#define FLASH_ECCCLRR           0x10    /* Clear ECC */
+#define FLASH_FLASHIO           0x14    /* Flash I/O */
+#define FLASH_FLASHCTL          0x18    /* Flash Control */
 
-#define FLASHCTL_CE0		(1 << 0)
-#define FLASHCTL_CLE		(1 << 1)
-#define FLASHCTL_ALE		(1 << 2)
-#define FLASHCTL_WP		(1 << 3)
-#define FLASHCTL_CE1		(1 << 4)
-#define FLASHCTL_RYBY		(1 << 5)
-#define FLASHCTL_NCE		(FLASHCTL_CE0 | FLASHCTL_CE1)
+#define FLASHCTL_CE0            (1 << 0)
+#define FLASHCTL_CLE            (1 << 1)
+#define FLASHCTL_ALE            (1 << 2)
+#define FLASHCTL_WP             (1 << 3)
+#define FLASHCTL_CE1            (1 << 4)
+#define FLASHCTL_RYBY           (1 << 5)
+#define FLASHCTL_NCE            (FLASHCTL_CE0 | FLASHCTL_CE1)
 
 #define TYPE_SL_NAND "sl-nand"
 #define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
     int ryby;
 
     switch (addr) {
-#define BSHR(byte, from, to)	((s->ecc.lp[byte] >> (from - to)) & (1 << to))
+#define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
     case FLASH_ECCLPLB:
         return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
                 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
 
-#define BSHL(byte, from, to)	((s->ecc.lp[byte] << (to - from)) & (1 << to))
+#define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
     case FLASH_ECCLPUB:
         return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
                 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
@@ -XXX,XX +XXX,XX @@ static void sl_nand_realize(DeviceState *dev, Error **errp)
 
 /* Spitz Keyboard */
 
-#define SPITZ_KEY_STROBE_NUM	11
-#define SPITZ_KEY_SENSE_NUM	7
+#define SPITZ_KEY_STROBE_NUM    11
+#define SPITZ_KEY_SENSE_NUM     7
 
 static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
     12, 17, 91, 34, 36, 38, 39
@@ -XXX,XX +XXX,XX @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
     { 0x52, 0x43, 0x01, 0x47, 0x49,  -1 ,  -1 ,  -1 ,  -1 ,  -1 ,  -1  },
 };
 
-#define SPITZ_GPIO_AK_INT	13	/* Remote control */
-#define SPITZ_GPIO_SYNC		16	/* Sync button */
-#define SPITZ_GPIO_ON_KEY	95	/* Power button */
-#define SPITZ_GPIO_SWA		97	/* Lid */
-#define SPITZ_GPIO_SWB		96	/* Tablet mode */
+#define SPITZ_GPIO_AK_INT       13      /* Remote control */
+#define SPITZ_GPIO_SYNC                 16      /* Sync button */
+#define SPITZ_GPIO_ON_KEY       95      /* Power button */
+#define SPITZ_GPIO_SWA          97      /* Lid */
+#define SPITZ_GPIO_SWB          96      /* Tablet mode */
 
 /* The special buttons are mapped to unused keys */
 static const int spitz_gpiomap[5] = {
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
 #define SPITZ_MOD_CTRL    (1 << 8)
 #define SPITZ_MOD_FN      (1 << 9)
 
-#define QUEUE_KEY(c)	s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
+#define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
 
 static void spitz_keyboard_handler(void *opaque, int keycode)
 {
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_handler(void *opaque, int keycode)
     uint16_t code;
     int mapcode;
     switch (keycode) {
-    case 0x2a:	/* Left Shift */
+    case 0x2a:  /* Left Shift */
         s->modifiers |= 1;
         break;
     case 0xaa:
         s->modifiers &= ~1;
         break;
-    case 0x36:	/* Right Shift */
+    case 0x36:  /* Right Shift */
         s->modifiers |= 2;
         break;
     case 0xb6:
         s->modifiers &= ~2;
         break;
-    case 0x1d:	/* Control */
+    case 0x1d:  /* Control */
         s->modifiers |= 4;
         break;
     case 0x9d:
         s->modifiers &= ~4;
         break;
-    case 0x38:	/* Alt */
+    case 0x38:  /* Alt */
         s->modifiers |= 8;
         break;
     case 0xb8:
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
 
 /* LCD backlight controller */
 
-#define LCDTG_RESCTL	0x00
-#define LCDTG_PHACTRL	0x01
-#define LCDTG_DUTYCTRL	0x02
-#define LCDTG_POWERREG0	0x03
-#define LCDTG_POWERREG1	0x04
-#define LCDTG_GPOR3	0x05
-#define LCDTG_PICTRL	0x06
-#define LCDTG_POLCTRL	0x07
+#define LCDTG_RESCTL    0x00
+#define LCDTG_PHACTRL   0x01
+#define LCDTG_DUTYCTRL  0x02
+#define LCDTG_POWERREG0         0x03
+#define LCDTG_POWERREG1         0x04
+#define LCDTG_GPOR3     0x05
+#define LCDTG_PICTRL    0x06
+#define LCDTG_POLCTRL   0x07
 
 typedef struct {
     SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
 
 /* SSP devices */
 
-#define CORGI_SSP_PORT		2
+#define CORGI_SSP_PORT          2
 
-#define SPITZ_GPIO_LCDCON_CS	53
-#define SPITZ_GPIO_ADS7846_CS	14
-#define SPITZ_GPIO_MAX1111_CS	20
-#define SPITZ_GPIO_TP_INT	11
+#define SPITZ_GPIO_LCDCON_CS    53
+#define SPITZ_GPIO_ADS7846_CS   14
+#define SPITZ_GPIO_MAX1111_CS   20
+#define SPITZ_GPIO_TP_INT       11
 
 static DeviceState *max1111;
 
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
     s->enable[line] = !level;
 }
 
-#define MAX1111_BATT_VOLT	1
-#define MAX1111_BATT_TEMP	2
-#define MAX1111_ACIN_VOLT	3
+#define MAX1111_BATT_VOLT       1
+#define MAX1111_BATT_TEMP       2
+#define MAX1111_ACIN_VOLT       3
 
-#define SPITZ_BATTERY_TEMP	0xe0	/* About 2.9V */
-#define SPITZ_BATTERY_VOLT	0xd0	/* About 4.0V */
-#define SPITZ_CHARGEON_ACIN	0x80	/* About 5.0V */
+#define SPITZ_BATTERY_TEMP      0xe0    /* About 2.9V */
+#define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
+#define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
 
 static void spitz_adc_temp_on(void *opaque, int line, int level)
 {
@@ -XXX,XX +XXX,XX @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
 
 /* Wm8750 and Max7310 on I2C */
 
-#define AKITA_MAX_ADDR	0x18
-#define SPITZ_WM_ADDRL	0x1b
-#define SPITZ_WM_ADDRH	0x1a
+#define AKITA_MAX_ADDR  0x18
+#define SPITZ_WM_ADDRL  0x1b
+#define SPITZ_WM_ADDRH  0x1a
 
-#define SPITZ_GPIO_WM	5
+#define SPITZ_GPIO_WM   5
 
 static void spitz_wm8750_addr(void *opaque, int line, int level)
 {
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
     }
 }
 
-#define SPITZ_SCP_LED_GREEN		1
-#define SPITZ_SCP_JK_B			2
-#define SPITZ_SCP_CHRG_ON		3
-#define SPITZ_SCP_MUTE_L		4
-#define SPITZ_SCP_MUTE_R		5
-#define SPITZ_SCP_CF_POWER		6
-#define SPITZ_SCP_LED_ORANGE		7
-#define SPITZ_SCP_JK_A			8
-#define SPITZ_SCP_ADC_TEMP_ON		9
-#define SPITZ_SCP2_IR_ON		1
-#define SPITZ_SCP2_AKIN_PULLUP		2
-#define SPITZ_SCP2_BACKLIGHT_CONT	7
-#define SPITZ_SCP2_BACKLIGHT_ON		8
-#define SPITZ_SCP2_MIC_BIAS		9
+#define SPITZ_SCP_LED_GREEN             1
+#define SPITZ_SCP_JK_B                  2
+#define SPITZ_SCP_CHRG_ON               3
+#define SPITZ_SCP_MUTE_L                4
+#define SPITZ_SCP_MUTE_R                5
+#define SPITZ_SCP_CF_POWER              6
+#define SPITZ_SCP_LED_ORANGE            7
+#define SPITZ_SCP_JK_A                  8
+#define SPITZ_SCP_ADC_TEMP_ON           9
+#define SPITZ_SCP2_IR_ON                1
+#define SPITZ_SCP2_AKIN_PULLUP          2
+#define SPITZ_SCP2_BACKLIGHT_CONT       7
+#define SPITZ_SCP2_BACKLIGHT_ON                 8
+#define SPITZ_SCP2_MIC_BIAS             9
 
 static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
                 DeviceState *scp0, DeviceState *scp1)
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
     qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 }
 
-#define SPITZ_GPIO_HSYNC		22
-#define SPITZ_GPIO_SD_DETECT		9
-#define SPITZ_GPIO_SD_WP		81
-#define SPITZ_GPIO_ON_RESET		89
-#define SPITZ_GPIO_BAT_COVER		90
-#define SPITZ_GPIO_CF1_IRQ		105
-#define SPITZ_GPIO_CF1_CD		94
-#define SPITZ_GPIO_CF2_IRQ		106
-#define SPITZ_GPIO_CF2_CD		93
+#define SPITZ_GPIO_HSYNC                22
+#define SPITZ_GPIO_SD_DETECT            9
+#define SPITZ_GPIO_SD_WP                81
+#define SPITZ_GPIO_ON_RESET             89
+#define SPITZ_GPIO_BAT_COVER            90
+#define SPITZ_GPIO_CF1_IRQ              105
+#define SPITZ_GPIO_CF1_CD               94
+#define SPITZ_GPIO_CF2_IRQ              106
+#define SPITZ_GPIO_CF2_CD               93
 
 static int spitz_hsync;
 
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
 /* Board init.  */
 enum spitz_model_e { spitz, akita, borzoi, terrier };
 
-#define SPITZ_RAM	0x04000000
-#define SPITZ_ROM	0x00800000
+#define SPITZ_RAM       0x04000000
+#define SPITZ_ROM       0x00800000
 
 static struct arm_boot_info spitz_binfo = {
     .loader_start = PXA2XX_SDRAM_BASE,
-- 
2.20.1

For the four Spitz-family machines (akita, borzoi, spitz, terrier)
create a proper abstract class SpitzMachineClass which encapsulates
the common behaviour, rather than having them all derive directly
from TYPE_MACHINE:
 * instead of each machine class setting mc->init to a wrapper
   function which calls spitz_common_init() with parameters,
   put that data in the SpitzMachineClass and make spitz_common_init
   the SpitzMachineClass machine-init function
 * move the settings of mc->block_default_type and
   mc->ignore_memory_transaction_failures into the SpitzMachineClass
   class init rather than repeating them in each machine's class init

(The motivation is that we're going to want to keep some state in
the SpitzMachineState so we can connect GPIOs between devices created
in one sub-function of the machine init to devices created in a
different sub-function.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200628142429.17111-3-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++--------------------
 1 file changed, 55 insertions(+), 36 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "cpu.h"
 
+enum spitz_model_e { spitz, akita, borzoi, terrier };
+
+typedef struct {
+    MachineClass parent;
+    enum spitz_model_e model;
+    int arm_id;
+} SpitzMachineClass;
+
+typedef struct {
+    MachineState parent;
+} SpitzMachineState;
+
+#define TYPE_SPITZ_MACHINE "spitz-common"
+#define SPITZ_MACHINE(obj) \
+    OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE)
+#define SPITZ_MACHINE_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE)
+#define SPITZ_MACHINE_CLASS(klass) \
+    OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
+
 #undef REG_FMT
 #define REG_FMT                         "0x%02lx"
 
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
 }
 
 /* Board init.  */
-enum spitz_model_e { spitz, akita, borzoi, terrier };
-
 #define SPITZ_RAM       0x04000000
 #define SPITZ_ROM       0x00800000
 
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
     .ram_size = 0x04000000,
 };
 
-static void spitz_common_init(MachineState *machine,
-                              enum spitz_model_e model, int arm_id)
+static void spitz_common_init(MachineState *machine)
 {
+    SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
+    enum spitz_model_e model = smc->model;
     PXA2xxState *mpu;
     DeviceState *scp0, *scp1 = NULL;
     MemoryRegion *address_space_mem = get_system_memory();
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine,
         /* A 4.0 GB microdrive is permanently sitting in CF slot 0.  */
         spitz_microdrive_attach(mpu, 0);
 
-    spitz_binfo.board_id = arm_id;
+    spitz_binfo.board_id = smc->arm_id;
     arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
     sl_bootparam_write(SL_PXA_PARAM_BASE);
 }
 
-static void spitz_init(MachineState *machine)
+static void spitz_common_class_init(ObjectClass *oc, void *data)
 {
-    spitz_common_init(machine, spitz, 0x2c9);
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->block_default_type = IF_IDE;
+    mc->ignore_memory_transaction_failures = true;
+    mc->init = spitz_common_init;
 }
 
-static void borzoi_init(MachineState *machine)
-{
-    spitz_common_init(machine, borzoi, 0x33f);
-}
-
-static void akita_init(MachineState *machine)
-{
-    spitz_common_init(machine, akita, 0x2e8);
-}
-
-static void terrier_init(MachineState *machine)
-{
-    spitz_common_init(machine, terrier, 0x33f);
-}
+static const TypeInfo spitz_common_info = {
+    .name = TYPE_SPITZ_MACHINE,
+    .parent = TYPE_MACHINE,
+    .abstract = true,
+    .instance_size = sizeof(SpitzMachineState),
+    .class_size = sizeof(SpitzMachineClass),
+    .class_init = spitz_common_class_init,
+};
 
 static void akitapda_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
 
     mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
-    mc->init = akita_init;
-    mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
+    smc->model = akita;
+    smc->arm_id = 0x2e8;
 }
 
 static const TypeInfo akitapda_type = {
     .name = MACHINE_TYPE_NAME("akita"),
-    .parent = TYPE_MACHINE,
+    .parent = TYPE_SPITZ_MACHINE,
     .class_init = akitapda_class_init,
 };
 
 static void spitzpda_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
 
     mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
-    mc->init = spitz_init;
-    mc->block_default_type = IF_IDE;
-    mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
+    smc->model = spitz;
+    smc->arm_id = 0x2c9;
 }
 
 static const TypeInfo spitzpda_type = {
     .name = MACHINE_TYPE_NAME("spitz"),
-    .parent = TYPE_MACHINE,
+    .parent = TYPE_SPITZ_MACHINE,
     .class_init = spitzpda_class_init,
 };
 
 static void borzoipda_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
 
     mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
-    mc->init = borzoi_init;
-    mc->block_default_type = IF_IDE;
-    mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
+    smc->model = borzoi;
+    smc->arm_id = 0x33f;
 }
 
 static const TypeInfo borzoipda_type = {
     .name = MACHINE_TYPE_NAME("borzoi"),
-    .parent = TYPE_MACHINE,
+    .parent = TYPE_SPITZ_MACHINE,
     .class_init = borzoipda_class_init,
 };
 
 static void terrierpda_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
 
     mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
-    mc->init = terrier_init;
-    mc->block_default_type = IF_IDE;
-    mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
+    smc->model = terrier;
+    smc->arm_id = 0x33f;
 }
 
 static const TypeInfo terrierpda_type = {
     .name = MACHINE_TYPE_NAME("terrier"),
-    .parent = TYPE_MACHINE,
+    .parent = TYPE_SPITZ_MACHINE,
     .class_init = terrierpda_class_init,
 };
 
 static void spitz_machine_init(void)
 {
+    type_register_static(&spitz_common_info);
     type_register_static(&akitapda_type);
     type_register_static(&spitzpda_type);
     type_register_static(&borzoipda_type);
-- 
2.20.1

Keep pointers to the MPU and the SSI devices in SpitzMachineState.
We're going to want to make GPIO connections between some of the
SSI devices and the SCPs, so we want to keep hold of a pointer to
those; putting the MPU into the struct allows us to pass just
one thing to spitz_ssp_attach() rather than two.

We have to retain the setting of the global "max1111" variable
for the moment as it is used in spitz_adc_temp_on(); later in
this series of commits we will be able to remove it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-4-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++----------------------
 1 file changed, 28 insertions(+), 22 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 typedef struct {
     MachineState parent;
+    PXA2xxState *mpu;
+    DeviceState *mux;
+    DeviceState *lcdtg;
+    DeviceState *ads7846;
+    DeviceState *max1111;
 } SpitzMachineState;
 
 #define TYPE_SPITZ_MACHINE "spitz-common"
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_realize(SSISlave *d, Error **errp)
     s->bus[2] = ssi_create_bus(dev, "ssi2");
 }
 
-static void spitz_ssp_attach(PXA2xxState *cpu)
+static void spitz_ssp_attach(SpitzMachineState *sms)
 {
-    DeviceState *mux;
-    DeviceState *dev;
     void *bus;
 
-    mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
+    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
 
-    bus = qdev_get_child_bus(mux, "ssi0");
-    ssi_create_slave(bus, "spitz-lcdtg");
+    bus = qdev_get_child_bus(sms->mux, "ssi0");
+    sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
 
-    bus = qdev_get_child_bus(mux, "ssi1");
-    dev = ssi_create_slave(bus, "ads7846");
-    qdev_connect_gpio_out(dev, 0,
-                          qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
+    bus = qdev_get_child_bus(sms->mux, "ssi1");
+    sms->ads7846 = ssi_create_slave(bus, "ads7846");
+    qdev_connect_gpio_out(sms->ads7846, 0,
+                          qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
 
-    bus = qdev_get_child_bus(mux, "ssi2");
-    max1111 = ssi_create_slave(bus, "max1111");
-    max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
-    max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
-    max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
+    bus = qdev_get_child_bus(sms->mux, "ssi2");
+    sms->max1111 = ssi_create_slave(bus, "max1111");
+    max1111 = sms->max1111;
+    max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
+    max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
+    max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
 
-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
-                        qdev_get_gpio_in(mux, 0));
-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
-                        qdev_get_gpio_in(mux, 1));
-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
-                        qdev_get_gpio_in(mux, 2));
+    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
+                        qdev_get_gpio_in(sms->mux, 0));
+    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS,
+                        qdev_get_gpio_in(sms->mux, 1));
+    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS,
+                        qdev_get_gpio_in(sms->mux, 2));
 }
 
 /* CF Microdrive */
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
 static void spitz_common_init(MachineState *machine)
 {
     SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
+    SpitzMachineState *sms = SPITZ_MACHINE(machine);
     enum spitz_model_e model = smc->model;
     PXA2xxState *mpu;
     DeviceState *scp0, *scp1 = NULL;
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
     /* Setup CPU & memory */
     mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
                       machine->cpu_type);
+    sms->mpu = mpu;
 
     sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
 
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
     /* Setup peripherals */
     spitz_keyboard_register(mpu);
 
-    spitz_ssp_attach(mpu);
+    spitz_ssp_attach(sms);
 
     scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
     if (model != akita) {
-- 
2.20.1

Keep pointers to scp0, scp1 in SpitzMachineState, and just pass
that to spitz_scoop_gpio_setup().

(We'll want to use some of the other fields in SpitzMachineState
in that function in the next commit.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-5-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 34 +++++++++++++++++++---------------
 1 file changed, 19 insertions(+), 15 deletions(-)

Currently the Spitz board uses a nasty hack for the GPIO lines
that pass "bit5" and "power" information to the LCD controller:
the lcdtg realize function sets a global variable to point to
the instance it just realized, and then the functions spitz_bl_power()
and spitz_bl_bit5() use that to find the device they are changing
the internal state of. There is a comment reading:
 FIXME: Implement GPIO properly and remove this hack.
which was added in 2009.

Implement GPIO properly and remove this hack.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-6-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void spitz_bl_update(SpitzLCDTG *s)
         zaurus_printf("LCD Backlight now off\n");
 }
 
-/* FIXME: Implement GPIO properly and remove this hack.  */
-static SpitzLCDTG *spitz_lcdtg;
-
 static inline void spitz_bl_bit5(void *opaque, int line, int level)
 {
-    SpitzLCDTG *s = spitz_lcdtg;
+    SpitzLCDTG *s = opaque;
     int prev = s->bl_intensity;
 
     if (level)
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_bit5(void *opaque, int line, int level)
 
 static inline void spitz_bl_power(void *opaque, int line, int level)
 {
-    SpitzLCDTG *s = spitz_lcdtg;
+    SpitzLCDTG *s = opaque;
     s->bl_power = !!level;
     spitz_bl_update(s);
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
     return 0;
 }
 
-static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
+static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
 {
-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
+    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
+    DeviceState *dev = DEVICE(s);
 
-    spitz_lcdtg = s;
     s->bl_power = 0;
     s->bl_intensity = 0x20;
+
+    qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1);
+    qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1);
 }
 
 /* SSP devices */
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
     case 3:
         zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
         break;
-    case 4:
-        spitz_bl_bit5(opaque, line, level);
-        break;
-    case 5:
-        spitz_bl_power(opaque, line, level);
-        break;
     case 6:
         spitz_adc_temp_on(opaque, line, level);
         break;
+    default:
+        g_assert_not_reached();
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
 
     if (sms->scp1) {
         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
-                              outsignals[4]);
+                              qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0));
         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
-                              outsignals[5]);
+                              qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
     }
 
     qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
-- 
2.20.1

Add some QOM properties to the max111x ADC device to allow the
initial values to be configured. Currently this is done by
board code calling max111x_set_input() after it creates the
device, which doesn't work on system reset.

This requires us to implement a reset method for this device,
so while we're doing that make sure we reset the other parts
of the device state.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-7-peter.maydell@linaro.org
---
 hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 47 insertions(+), 10 deletions(-)

diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/ssi/ssi.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
+#include "hw/qdev-properties.h"
 
 typedef struct {
     SSISlave parent_obj;
 
     qemu_irq interrupt;
+    /* Values of inputs at system reset (settable by QOM property) */
+    uint8_t reset_input[8];
+
     uint8_t tb1, rb2, rb3;
     int cycle;
 
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
     qdev_init_gpio_out(dev, &s->interrupt, 1);
 
     s->inputs = inputs;
-    /* TODO: add a user interface for setting these */
-    s->input[0] = 0xf0;
-    s->input[1] = 0xe0;
-    s->input[2] = 0xd0;
-    s->input[3] = 0xc0;
-    s->input[4] = 0xb0;
-    s->input[5] = 0xa0;
-    s->input[6] = 0x90;
-    s->input[7] = 0x80;
-    s->com = 0;
 
     vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
                      &vmstate_max111x, s);
@@ -XXX,XX +XXX,XX @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value)
     s->input[line] = value;
 }
 
+static void max111x_reset(DeviceState *dev)
+{
+    MAX111xState *s = MAX_111X(dev);
+    int i;
+
+    for (i = 0; i < s->inputs; i++) {
+        s->input[i] = s->reset_input[i];
+    }
+    s->com = 0;
+    s->tb1 = 0;
+    s->rb2 = 0;
+    s->rb3 = 0;
+    s->cycle = 0;
+}
+
+static Property max1110_properties[] = {
+    /* Reset values for ADC inputs */
+    DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
+    DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
+    DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
+    DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static Property max1111_properties[] = {
+    /* Reset values for ADC inputs */
+    DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
+    DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
+    DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
+    DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
+    DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0),
+    DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0),
+    DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90),
+    DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void max111x_class_init(ObjectClass *klass, void *data)
 {
     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
 
     k->transfer = max111x_transfer;
+    dc->reset = max111x_reset;
 }
 
 static const TypeInfo max111x_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max111x_info = {
 static void max1110_class_init(ObjectClass *klass, void *data)
 {
     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
 
     k->realize = max1110_realize;
+    device_class_set_props(dc, max1110_properties);
 }
 
 static const TypeInfo max1110_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max1110_info = {
 static void max1111_class_init(ObjectClass *klass, void *data)
 {
     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
 
     k->realize = max1111_realize;
+    device_class_set_props(dc, max1111_properties);
 }
 
 static const TypeInfo max1111_info = {
-- 
2.20.1

The max111x is a proper qdev device; we can use dc->vmsd rather than
directly calling vmstate_register().

It's possible that this is a migration compat break, but the only
boards that use this device are the spitz-family ('akita', 'borzoi',
'spitz', 'terrier').

diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
 
     s->inputs = inputs;
 
-    vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
-                     &vmstate_max111x, s);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static void max111x_class_init(ObjectClass *klass, void *data)
 
     k->transfer = max111x_transfer;
     dc->reset = max111x_reset;
+    dc->vmsd = &vmstate_max111x;
 }
 
 static const TypeInfo max111x_info = {
-- 
2.20.1

Add an ssi_realize_and_unref(), for the benefit of callers
who want to be able to create an SSI device, set QOM properties
on it, and then do the realize-and-unref afterwards.

The API works on the same principle as the recently added
qdev_realize_and_undef(), sysbus_realize_and_undef(), etc.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-9-peter.maydell@linaro.org
---
 include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++
 hw/ssi/ssi.c         |  7 ++++++-
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ssi_slave;
 }
 
 DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
+/**
+ * ssi_realize_and_unref: realize and unref an SSI slave device
+ * @dev: SSI slave device to realize
+ * @bus: SSI bus to put it on
+ * @errp: error pointer
+ *
+ * Call 'realize' on @dev, put it on the specified @bus, and drop the
+ * reference to it. Errors are reported via @errp and by returning
+ * false.
+ *
+ * This function is useful if you have created @dev via qdev_new()
+ * (which takes a reference to the device it returns to you), so that
+ * you can set properties on it before realizing it. If you don't need
+ * to set properties then ssi_create_slave() is probably better (as it
+ * does the create, init and realize in one step).
+ *
+ * If you are embedding the SSI slave into another QOM device and
+ * initialized it via some variant on object_initialize_child() then
+ * do not use this function, because that family of functions arrange
+ * for the only reference to the child device to be held by the parent
+ * via the child<> property, and so the reference-count-drop done here
+ * would be incorrect.  (Instead you would want ssi_realize(), which
+ * doesn't currently exist but would be trivial to create if we had
+ * any code that wanted it.)
+ */
+bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
 
 /* Master interface.  */
 SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/ssi.c
+++ b/hw/ssi/ssi.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ssi_slave_info = {
     .abstract = true,
 };
 
+bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
+{
+    return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
+}
+
 DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
 {
     DeviceState *dev = qdev_new(name);
 
-    qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal);
+    ssi_realize_and_unref(dev, bus, &error_fatal);
     return dev;
 }
 
-- 
2.20.1

Use the new max111x qdev properties to set the initial input
values rather than calling max111x_set_input(); this means that
on system reset the inputs will correctly return to their initial
values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200628142429.17111-10-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
                           qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
 
     bus = qdev_get_child_bus(sms->mux, "ssi2");
-    sms->max1111 = ssi_create_slave(bus, "max1111");
+    sms->max1111 = qdev_new("max1111");
     max1111 = sms->max1111;
-    max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
-    max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
-    max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
+    qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
+                        SPITZ_BATTERY_VOLT);
+    qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
+    qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */,
+                        SPITZ_CHARGEON_ACIN);
+    ssi_realize_and_unref(sms->max1111, bus, &error_fatal);
 
     qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
                         qdev_get_gpio_in(sms->mux, 0));
-- 
2.20.1

The max111x ADC device model allows other code to set the level on
the 8 ADC inputs using the max111x_set_input() function.  Replace
this with generic qdev GPIO inputs, which also allow inputs to be set
to arbitrary values.

Using GPIO lines will make it easier for board code to wire things
up, so that if device A wants to set the ADC input it doesn't need to
have a direct pointer to the max111x but can just set that value on
its output GPIO, which is then wired up by the board to the
appropriate max111x input.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-11-peter.maydell@linaro.org
---
 include/hw/ssi/ssi.h |  3 ---
 hw/arm/spitz.c       |  9 +++++----
 hw/misc/max111x.c    | 16 +++++++++-------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -XXX,XX +XXX,XX @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
 
 uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
 
-/* max111x.c */
-void max111x_set_input(DeviceState *dev, int line, uint8_t value);
-
 #endif
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
 
 static void spitz_adc_temp_on(void *opaque, int line, int level)
 {
+    int batt_temp;
+
     if (!max1111)
         return;
 
-    if (level)
-        max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
-    else
-        max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
+    batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
+
+    qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
 }
 
 static void corgi_ssp_realize(SSISlave *d, Error **errp)
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_max111x = {
     }
 };
 
+static void max111x_input_set(void *opaque, int line, int value)
+{
+    MAX111xState *s = MAX_111X(opaque);
+
+    assert(line >= 0 && line < s->inputs);
+    s->input[line] = value;
+}
+
 static int max111x_init(SSISlave *d, int inputs)
 {
     DeviceState *dev = DEVICE(d);
     MAX111xState *s = MAX_111X(dev);
 
     qdev_init_gpio_out(dev, &s->interrupt, 1);
+    qdev_init_gpio_in(dev, max111x_input_set, inputs);
 
     s->inputs = inputs;
 
@@ -XXX,XX +XXX,XX @@ static void max1111_realize(SSISlave *dev, Error **errp)
     max111x_init(dev, 4);
 }
 
-void max111x_set_input(DeviceState *dev, int line, uint8_t value)
-{
-    MAX111xState *s = MAX_111X(dev);
-    assert(line >= 0 && line < s->inputs);
-    s->input[line] = value;
-}
-
 static void max111x_reset(DeviceState *dev)
 {
     MAX111xState *s = MAX_111X(dev);
-- 
2.20.1

Create a header file for the hw/misc/max111x device, in the
usual modern style for QOM devices:
 * definition of the TYPE_ constants and macros
 * definition of the device's state struct so that it can
   be embedded in other structs if desired
 * documentation of the interface

This allows us to use TYPE_MAX_1111 in the spitz.c code rather
than the string "max1111".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200628142429.17111-12-peter.maydell@linaro.org
---
 include/hw/misc/max111x.h | 56 +++++++++++++++++++++++++++++++++++++++
 hw/arm/spitz.c            |  3 ++-
 hw/misc/max111x.c         | 24 +----------------
 MAINTAINERS               |  1 +
 4 files changed, 60 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/misc/max111x.h

diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/max111x.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Maxim MAX1110/1111 ADC chip emulation.
+ *
+ * Copyright (c) 2006 Openedhand Ltd.
+ * Written by Andrzej Zaborowski <balrog@zabor.org>
+ *
+ * This code is licensed under the GNU GPLv2.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#ifndef HW_MISC_MAX111X_H
+#define HW_MISC_MAX111X_H
+
+#include "hw/ssi/ssi.h"
+
+/*
+ * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
+ * is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
+ * 8-bit ADC channels.
+ *
+ * QEMU interface:
+ *  + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
+ *    of each ADC input, as an unsigned 8-bit value
+ *  + GPIO output 0: interrupt line
+ *  + Properties "input0" to "input3" (max1110) or "input0" to "input7"
+ *    (max1111): initial reset values for ADC inputs.
+ *
+ * Known bugs:
+ *  + the interrupt line is not correctly implemented, and will never
+ *    be lowered once it has been asserted.
+ */
+typedef struct {
+    SSISlave parent_obj;
+
+    qemu_irq interrupt;
+    /* Values of inputs at system reset (settable by QOM property) */
+    uint8_t reset_input[8];
+
+    uint8_t tb1, rb2, rb3;
+    int cycle;
+
+    uint8_t input[8];
+    int inputs, com;
+} MAX111xState;
+
+#define TYPE_MAX_111X "max111x"
+
+#define MAX_111X(obj) \
+    OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
+
+#define TYPE_MAX_1110 "max1110"
+#define TYPE_MAX_1111 "max1111"
+
+#endif
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "audio/audio.h"
 #include "hw/boards.h"
 #include "hw/sysbus.h"
+#include "hw/misc/max111x.h"
 #include "migration/vmstate.h"
 #include "exec/address-spaces.h"
 #include "cpu.h"
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
                           qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
 
     bus = qdev_get_child_bus(sms->mux, "ssi2");
-    sms->max1111 = qdev_new("max1111");
+    sms->max1111 = qdev_new(TYPE_MAX_1111);
     max1111 = sms->max1111;
     qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
                         SPITZ_BATTERY_VOLT);
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/misc/max111x.h"
 #include "hw/irq.h"
-#include "hw/ssi/ssi.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
 #include "hw/qdev-properties.h"
 
-typedef struct {
-    SSISlave parent_obj;
-
-    qemu_irq interrupt;
-    /* Values of inputs at system reset (settable by QOM property) */
-    uint8_t reset_input[8];
-
-    uint8_t tb1, rb2, rb3;
-    int cycle;
-
-    uint8_t input[8];
-    int inputs, com;
-} MAX111xState;
-
-#define TYPE_MAX_111X "max111x"
-
-#define MAX_111X(obj) \
-    OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
-
-#define TYPE_MAX_1110 "max1110"
-#define TYPE_MAX_1111 "max1111"
-
 /* Control-byte bitfields */
 #define CB_PD0		(1 << 0)
 #define CB_PD1		(1 << 1)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/gpio/max7310.c
 F: hw/gpio/zaurus.c
 F: hw/misc/mst_fpga.c
 F: hw/misc/max111x.c
+F: include/hw/misc/max111x.h
 F: include/hw/arm/pxa.h
 F: include/hw/arm/sharpsl.h
 F: include/hw/display/tc6393xb.h
-- 
2.20.1

Currently we have a free-floating set of IRQs and a function
spitz_out_switch() which handle some miscellaneous GPIO lines for the
spitz board.  Encapsulate this behaviour in a simple QOM device.

At this point we can finally remove the 'max1111' global, because the
ADC battery-temperature value is now handled by the misc-gpio device
writing the value to its outbound "adc-temp" GPIO, which the board
code wires up to the appropriate inbound GPIO line on the max1111.

This commit also fixes Coverity issue CID 1421913 (which pointed out
that the 'outsignals' in spitz_scoop_gpio_setup() were leaked),
because it removes the use of the qemu_allocate_irqs() API from this
code entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-13-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++----------------
 1 file changed, 87 insertions(+), 42 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     DeviceState *max1111;
     DeviceState *scp0;
     DeviceState *scp1;
+    DeviceState *misc_gpio;
 } SpitzMachineState;
 
 #define TYPE_SPITZ_MACHINE "spitz-common"
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
 #define SPITZ_GPIO_MAX1111_CS   20
 #define SPITZ_GPIO_TP_INT       11
 
-static DeviceState *max1111;
-
 /* "Demux" the signal based on current chipselect */
 typedef struct {
     SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
 #define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
 #define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
 
-static void spitz_adc_temp_on(void *opaque, int line, int level)
-{
-    int batt_temp;
-
-    if (!max1111)
-        return;
-
-    batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
-
-    qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
-}
-
 static void corgi_ssp_realize(SSISlave *d, Error **errp)
 {
     DeviceState *dev = DEVICE(d);
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
 
     bus = qdev_get_child_bus(sms->mux, "ssi2");
     sms->max1111 = qdev_new(TYPE_MAX_1111);
-    max1111 = sms->max1111;
     qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
                         SPITZ_BATTERY_VOLT);
     qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
@@ -XXX,XX +XXX,XX @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu)
 
 /* Other peripherals */
 
-static void spitz_out_switch(void *opaque, int line, int level)
+/*
+ * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards.
+ *
+ * QEMU interface:
+ *  + named GPIO inputs "green-led", "orange-led", "charging", "discharging":
+ *    these currently just print messages that the line has been signalled
+ *  + named GPIO input "adc-temp-on": set to cause the battery-temperature
+ *    value to be passed to the max111x ADC
+ *  + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
+ */
+#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
+#define SPITZ_MISC_GPIO(obj) \
+    OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
+
+typedef struct SpitzMiscGPIOState {
+    SysBusDevice parent_obj;
+
+    qemu_irq adc_value;
+} SpitzMiscGPIOState;
+
+static void spitz_misc_charging(void *opaque, int n, int level)
 {
-    switch (line) {
-    case 0:
-        zaurus_printf("Charging %s.\n", level ? "off" : "on");
-        break;
-    case 1:
-        zaurus_printf("Discharging %s.\n", level ? "on" : "off");
-        break;
-    case 2:
-        zaurus_printf("Green LED %s.\n", level ? "on" : "off");
-        break;
-    case 3:
-        zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
-        break;
-    case 6:
-        spitz_adc_temp_on(opaque, line, level);
-        break;
-    default:
-        g_assert_not_reached();
-    }
+    zaurus_printf("Charging %s.\n", level ? "off" : "on");
+}
+
+static void spitz_misc_discharging(void *opaque, int n, int level)
+{
+    zaurus_printf("Discharging %s.\n", level ? "off" : "on");
+}
+
+static void spitz_misc_green_led(void *opaque, int n, int level)
+{
+    zaurus_printf("Green LED %s.\n", level ? "off" : "on");
+}
+
+static void spitz_misc_orange_led(void *opaque, int n, int level)
+{
+    zaurus_printf("Orange LED %s.\n", level ? "off" : "on");
+}
+
+static void spitz_misc_adc_temp(void *opaque, int n, int level)
+{
+    SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque);
+    int batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
+
+    qemu_set_irq(s->adc_value, batt_temp);
+}
+
+static void spitz_misc_gpio_init(Object *obj)
+{
+    SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj);
+    DeviceState *dev = DEVICE(obj);
+
+    qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1);
+    qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1);
+    qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1);
+    qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1);
+    qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1);
+
+    qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1);
 }
 
 #define SPITZ_SCP_LED_GREEN             1
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
 
 static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
 {
-    qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
+    DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL);
 
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
+    sms->misc_gpio = miscdev;
+
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON,
+                          qdev_get_gpio_in_named(miscdev, "charging", 0));
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B,
+                          qdev_get_gpio_in_named(miscdev, "discharging", 0));
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN,
+                          qdev_get_gpio_in_named(miscdev, "green-led", 0));
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE,
+                          qdev_get_gpio_in_named(miscdev, "orange-led", 0));
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON,
+                          qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0));
+    qdev_connect_gpio_out_named(miscdev, "adc-temp", 0,
+                                qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP));
 
     if (sms->scp1) {
         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
                               qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
     }
-
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 }
 
 #define SPITZ_GPIO_HSYNC                22
@@ -XXX,XX +XXX,XX @@ static const TypeInfo spitz_lcdtg_info = {
     .class_init    = spitz_lcdtg_class_init,
 };
 
+static const TypeInfo spitz_misc_gpio_info = {
+    .name = TYPE_SPITZ_MISC_GPIO,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SpitzMiscGPIOState),
+    .instance_init = spitz_misc_gpio_init,
+    /*
+     * No class_init required: device has no internal state so does not
+     * need to set up reset or vmstate, and does not have a realize method.
+     */
+};
+
 static void spitz_register_types(void)
 {
     type_register_static(&corgi_ssp_info);
     type_register_static(&spitz_lcdtg_info);
     type_register_static(&spitz_keyboard_info);
     type_register_static(&sl_nand_info);
+    type_register_static(&spitz_misc_gpio_info);
 }
 
 type_init(spitz_register_types)
-- 
2.20.1

Instead of logging guest accesses to invalid register offsets in this
device using zaurus_printf() (which just prints to stderr), use the
usual qemu_log_mask(LOG_GUEST_ERROR,...).

Since this was the only use of the zaurus_printf() macro outside
spitz.c, we can move the definition of that macro from sharpsl.h
to spitz.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-14-peter.maydell@linaro.org
---
 include/hw/arm/sharpsl.h |  3 ---
 hw/arm/spitz.c           |  3 +++
 hw/gpio/zaurus.c         | 12 +++++++-----
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/sharpsl.h
+++ b/include/hw/arm/sharpsl.h
@@ -XXX,XX +XXX,XX @@
 
 #include "exec/hwaddr.h"
 
-#define zaurus_printf(format, ...)	\
-    fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
-
 /* zaurus.c */
 
 #define SL_PXA_PARAM_BASE	0xa0000a00
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
 #define SPITZ_MACHINE_CLASS(klass) \
     OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
 
+#define zaurus_printf(format, ...)                              \
+    fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
+
 #undef REG_FMT
 #define REG_FMT                         "0x%02lx"
 
diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/zaurus.c
+++ b/hw/gpio/zaurus.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
-
-#undef REG_FMT
-#define REG_FMT			"0x%02lx"
+#include "qemu/log.h"
 
 /* SCOOP devices */
 
@@ -XXX,XX +XXX,XX @@ static uint64_t scoop_read(void *opaque, hwaddr addr,
     case SCOOP_GPRR:
         return s->gpio_level;
     default:
-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n",
+                      addr);
     }
 
     return 0;
@@ -XXX,XX +XXX,XX @@ static void scoop_write(void *opaque, hwaddr addr,
         scoop_gpio_handler_update(s);
         break;
     default:
-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n",
+                      addr);
     }
 }
 
-- 
2.20.1

Instead of logging guest accesses to invalid register offsets in the
Spitz flash device with zaurus_printf() (which just prints to stderr),
use the usual qemu_log_mask(LOG_GUEST_ERROR,...).

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/ssi/ssi.h"
 #include "hw/block/flash.h"
 #include "qemu/timer.h"
+#include "qemu/log.h"
 #include "hw/arm/sharpsl.h"
 #include "ui/console.h"
 #include "hw/audio/wm8750.h"
@@ -XXX,XX +XXX,XX @@ typedef struct {
 #define zaurus_printf(format, ...)                              \
     fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
 
-#undef REG_FMT
-#define REG_FMT                         "0x%02lx"
-
 /* Spitz Flash */
 #define FLASH_BASE              0x0c000000
 #define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
         return ecc_digest(&s->ecc, nand_getio(s->nand));
 
     default:
-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n",
+                      addr);
     }
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ static void sl_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n",
+                      addr);
     }
 }
 
-- 
2.20.1

Instead of using printf() for logging guest accesses to invalid
register offsets in the pxa2xx PIC device, use the usual
qemu_log_mask(LOG_GUEST_ERROR,...).

This was the only user of the REG_FMT macro in pxa.h, so we can
remove that.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-16-peter.maydell@linaro.org
---
 include/hw/arm/pxa.h | 1 -
 hw/arm/pxa2xx_pic.c  | 9 +++++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/pxa.h
+++ b/include/hw/arm/pxa.h
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
 };
 
 # define PA_FMT			"0x%08lx"
-# define REG_FMT		"0x" TARGET_FMT_plx
 
 PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
                          const char *revision);
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/module.h"
+#include "qemu/log.h"
 #include "cpu.h"
 #include "hw/arm/pxa.h"
 #include "hw/sysbus.h"
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
     case ICHP:	/* Highest Priority register */
         return pxa2xx_pic_highest(s);
     default:
-        printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
+                      "\n", offset);
         return 0;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
         break;
     default:
-        printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pxa2xx_pic_mem_write: bad register offset 0x%"
+                      HWADDR_PRIx "\n", offset);
         return;
     }
     pxa2xx_pic_update(opaque);
-- 
2.20.1

The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the
usual QOM TYPE and casting macros; provide and use them.

In particular, we can safely use the QOM cast macros instead of
FROM_SSI_SLAVE() because in both cases the 'ssidev' field of
the instance state struct is the first field in it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-17-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
 #define LCDTG_PICTRL    0x06
 #define LCDTG_POLCTRL   0x07
 
+#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
+#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
+
 typedef struct {
     SSISlave ssidev;
     uint32_t bl_intensity;
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_power(void *opaque, int line, int level)
 
 static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
 {
-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
+    SpitzLCDTG *s = SPITZ_LCDTG(dev);
     int addr;
     addr = value >> 5;
     value &= 0x1f;
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
 
 static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
 {
-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
+    SpitzLCDTG *s = SPITZ_LCDTG(ssi);
     DeviceState *dev = DEVICE(s);
 
     s->bl_power = 0;
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
 #define SPITZ_GPIO_MAX1111_CS   20
 #define SPITZ_GPIO_TP_INT       11
 
+#define TYPE_CORGI_SSP "corgi-ssp"
+#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
+
 /* "Demux" the signal based on current chipselect */
 typedef struct {
     SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
 {
-    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
+    CorgiSSPState *s = CORGI_SSP(dev);
     int i;
 
     for (i = 0; i < 3; i++) {
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
 static void corgi_ssp_realize(SSISlave *d, Error **errp)
 {
     DeviceState *dev = DEVICE(d);
-    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d);
+    CorgiSSPState *s = CORGI_SSP(d);
 
     qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
     s->bus[0] = ssi_create_bus(dev, "ssi0");
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
 {
     void *bus;
 
-    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
+    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
+                                TYPE_CORGI_SSP);
 
     bus = qdev_get_child_bus(sms->mux, "ssi0");
-    sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
+    sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
 
     bus = qdev_get_child_bus(sms->mux, "ssi1");
     sms->ads7846 = ssi_create_slave(bus, "ads7846");
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo corgi_ssp_info = {
-    .name          = "corgi-ssp",
+    .name          = TYPE_CORGI_SSP,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(CorgiSSPState),
     .class_init    = corgi_ssp_class_init,
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo spitz_lcdtg_info = {
-    .name          = "spitz-lcdtg",
+    .name          = TYPE_SPITZ_LCDTG,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(SpitzLCDTG),
     .class_init    = spitz_lcdtg_class_init,
-- 
2.20.1

The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way
to cast from an SSISlave* to the instance struct of a subtype of
TYPE_SSI_SLAVE.  Switch to using the QOM cast macros instead, which
have the same effect (by writing the QOM macros if the types were
previously missing them.)

(The FROM_SSI_SLAVE() macro allows the SSISlave member of the
subtype's struct to be anywhere as long as it is named "ssidev",
whereas a QOM cast macro insists that it is the first thing in the
subtype's struct.  This is true for all the types we convert here.)

This removes all the uses of FROM_SSI_SLAVE() so we can delete the
definition.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-18-peter.maydell@linaro.org
---
 include/hw/ssi/ssi.h |  2 --
 hw/arm/z2.c          | 11 +++++++----
 hw/display/ads7846.c |  9 ++++++---
 hw/display/ssd0323.c | 10 +++++++---
 hw/sd/ssi-sd.c       |  4 ++--
 5 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -XXX,XX +XXX,XX @@ struct SSISlave {
     bool cs;
 };
 
-#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
-
 extern const VMStateDescription vmstate_ssi_slave;
 
 #define VMSTATE_SSI_SLAVE(_field, _state) {                          \
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     int pos;
 } ZipitLCD;
 
+#define TYPE_ZIPIT_LCD "zipit-lcd"
+#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD)
+
 static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
 {
-    ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
+    ZipitLCD *z = ZIPIT_LCD(dev);
     uint16_t val;
     if (z->selected) {
         z->buf[z->pos] = value & 0xff;
@@ -XXX,XX +XXX,XX @@ static void z2_lcd_cs(void *opaque, int line, int level)
 
 static void zipit_lcd_realize(SSISlave *dev, Error **errp)
 {
-    ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
+    ZipitLCD *z = ZIPIT_LCD(dev);
     z->selected = 0;
     z->enabled = 0;
     z->pos = 0;
@@ -XXX,XX +XXX,XX @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo zipit_lcd_info = {
-    .name          = "zipit-lcd",
+    .name          = TYPE_ZIPIT_LCD,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(ZipitLCD),
     .class_init    = zipit_lcd_class_init,
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
 
     type_register_static(&zipit_lcd_info);
     type_register_static(&aer915_info);
-    z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd");
+    z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD);
     bus = pxa2xx_i2c_bus(mpu->i2c[0]);
     i2c_create_slave(bus, TYPE_AER915, 0x55);
     wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b);
diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/ads7846.c
+++ b/hw/display/ads7846.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     int output;
 } ADS7846State;
 
+#define TYPE_ADS7846 "ads7846"
+#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846)
+
 /* Control-byte bitfields */
 #define CB_PD0		(1 << 0)
 #define CB_PD1		(1 << 1)
@@ -XXX,XX +XXX,XX @@ static void ads7846_int_update(ADS7846State *s)
 
 static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value)
 {
-    ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev);
+    ADS7846State *s = ADS7846(dev);
 
     switch (s->cycle ++) {
     case 0:
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ads7846 = {
 static void ads7846_realize(SSISlave *d, Error **errp)
 {
     DeviceState *dev = DEVICE(d);
-    ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d);
+    ADS7846State *s = ADS7846(d);
 
     qdev_init_gpio_out(dev, &s->interrupt, 1);
 
@@ -XXX,XX +XXX,XX @@ static void ads7846_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo ads7846_info = {
-    .name          = "ads7846",
+    .name          = TYPE_ADS7846,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(ADS7846State),
     .class_init    = ads7846_class_init,
diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/ssd0323.c
+++ b/hw/display/ssd0323.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     uint8_t framebuffer[128 * 80 / 2];
 } ssd0323_state;
 
+#define TYPE_SSD0323 "ssd0323"
+#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323)
+
+
 static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
 {
-    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
+    ssd0323_state *s = SSD0323(dev);
 
     switch (s->mode) {
     case SSD0323_DATA:
@@ -XXX,XX +XXX,XX @@ static const GraphicHwOps ssd0323_ops = {
 static void ssd0323_realize(SSISlave *d, Error **errp)
 {
     DeviceState *dev = DEVICE(d);
-    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
+    ssd0323_state *s = SSD0323(d);
 
     s->col_end = 63;
     s->row_end = 79;
@@ -XXX,XX +XXX,XX @@ static void ssd0323_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo ssd0323_info = {
-    .name          = "ssd0323",
+    .name          = TYPE_SSD0323,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(ssd0323_state),
     .class_init    = ssd0323_class_init,
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
 {
-    ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev);
+    ssi_sd_state *s = SSI_SD(dev);
 
     /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data.  */
     if (s->mode == SSI_SD_DATA_READ && val == 0x4d) {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ssi_sd = {
 
 static void ssi_sd_realize(SSISlave *d, Error **errp)
 {
-    ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
+    ssi_sd_state *s = SSI_SD(d);
     DeviceState *carddev;
     DriveInfo *dinfo;
     Error *err = NULL;
-- 
2.20.1

Deprecate our TileGX target support:
 * we have no active maintainer for it
 * it has had essentially no contributions (other than tree-wide cleanups
   and similar) since it was first added
 * the Linux kernel dropped support in 2018, as has glibc

Note the deprecation in the manual, but don't try to print a warning
when QEMU runs -- printing unsuppressable messages is more obtrusive
for linux-user mode than it would be for system-emulation mode, and
it doesn't seem worth trying to invent a new suppressible-error
system for linux-user just for this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20200619154831.26319-1-peter.maydell@linaro.org
---
 docs/system/deprecated.rst | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
 
   json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
 
+linux-user mode CPUs
+--------------------
+
+``tilegx`` CPUs (since 5.1.0)
+'''''''''''''''''''''''''''''
+
+The ``tilegx`` guest CPU support (which was only implemented in
+linux-user mode) is deprecated and will be removed in a future version
+of QEMU. Support for this CPU was removed from the upstream Linux
+kernel in 2018, and has also been dropped from glibc.
+
 Related binaries
 ----------------
 
-- 
2.20.1