1 | Two small bugfixes, plus most of RTH's refactoring of cpregs | 1 | First arm pullreq of the cycle; this is mostly my softfloat NaN |
---|---|---|---|
2 | handling. | 2 | handling series. (Lots more in my to-review queue, but I don't |
3 | like pullreqs growing too close to a hundred patches at a time :-)) | ||
3 | 4 | ||
5 | thanks | ||
4 | -- PMM | 6 | -- PMM |
5 | 7 | ||
6 | The following changes since commit 1fba9dc71a170b3a05b9d3272dd8ecfe7f26e215: | 8 | The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17: |
7 | 9 | ||
8 | Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging (2022-05-04 08:07:02 -0700) | 10 | Open 10.0 development tree (2024-12-10 17:41:17 +0000) |
9 | 11 | ||
10 | are available in the Git repository at: | 12 | are available in the Git repository at: |
11 | 13 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220505 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211 |
13 | 15 | ||
14 | for you to fetch changes up to 99a50d1a67c602126fc2b3a4812d3000eba9bf34: | 16 | for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8: |
15 | 17 | ||
16 | target/arm: read access to performance counters from EL0 (2022-05-05 09:36:22 +0100) | 18 | MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000) |
17 | 19 | ||
18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
19 | target-arm queue: | 21 | target-arm queue: |
20 | * Enable read access to performance counters from EL0 | 22 | * hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs |
21 | * Enable SCTLR_EL1.BT0 for aarch64-linux-user | 23 | * fpu: Make muladd NaN handling runtime-selected, not compile-time |
22 | * Refactoring of cpreg handling | 24 | * fpu: Make default NaN pattern runtime-selected, not compile-time |
25 | * fpu: Minor NaN-related cleanups | ||
26 | * MAINTAINERS: email address updates | ||
23 | 27 | ||
24 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
25 | Alex Zuepke (1): | 29 | Bernhard Beschow (5): |
26 | target/arm: read access to performance counters from EL0 | 30 | hw/net/lan9118: Extract lan9118_phy |
31 | hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations | ||
32 | hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register | ||
33 | hw/net/lan9118_phy: Reuse MII constants | ||
34 | hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement | ||
27 | 35 | ||
28 | Richard Henderson (22): | 36 | Leif Lindholm (1): |
29 | target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user | 37 | MAINTAINERS: update email address for Leif Lindholm |
30 | target/arm: Split out cpregs.h | ||
31 | target/arm: Reorg CPAccessResult and access_check_cp_reg | ||
32 | target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h | ||
33 | target/arm: Make some more cpreg data static const | ||
34 | target/arm: Reorg ARMCPRegInfo type field bits | ||
35 | target/arm: Avoid bare abort() or assert(0) | ||
36 | target/arm: Change cpreg access permissions to enum | ||
37 | target/arm: Name CPState type | ||
38 | target/arm: Name CPSecureState type | ||
39 | target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases | ||
40 | target/arm: Store cpregs key in the hash table directly | ||
41 | target/arm: Merge allocation of the cpreg and its name | ||
42 | target/arm: Hoist computation of key in add_cpreg_to_hashtable | ||
43 | target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable | ||
44 | target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable | ||
45 | target/arm: Hoist isbanked computation in add_cpreg_to_hashtable | ||
46 | target/arm: Perform override check early in add_cpreg_to_hashtable | ||
47 | target/arm: Reformat comments in add_cpreg_to_hashtable | ||
48 | target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable | ||
49 | target/arm: Add isar predicates for FEAT_Debugv8p2 | ||
50 | target/arm: Add isar_feature_{aa64,any}_ras | ||
51 | 38 | ||
52 | target/arm/cpregs.h | 453 ++++++++++++++++++++++++++++++++++++++ | 39 | Peter Maydell (54): |
53 | target/arm/cpu.h | 393 +++------------------------------ | 40 | fpu: handle raising Invalid for infzero in pick_nan_muladd |
54 | hw/arm/pxa2xx.c | 2 +- | 41 | fpu: Check for default_nan_mode before calling pickNaNMulAdd |
55 | hw/arm/pxa2xx_pic.c | 2 +- | 42 | softfloat: Allow runtime choice of inf * 0 + NaN result |
56 | hw/intc/arm_gicv3_cpuif.c | 6 +- | 43 | tests/fp: Explicitly set inf-zero-nan rule |
57 | hw/intc/arm_gicv3_kvm.c | 3 +- | 44 | target/arm: Set FloatInfZeroNaNRule explicitly |
58 | target/arm/cpu.c | 25 +-- | 45 | target/s390: Set FloatInfZeroNaNRule explicitly |
59 | target/arm/cpu64.c | 2 +- | 46 | target/ppc: Set FloatInfZeroNaNRule explicitly |
60 | target/arm/cpu_tcg.c | 5 +- | 47 | target/mips: Set FloatInfZeroNaNRule explicitly |
61 | target/arm/gdbstub.c | 5 +- | 48 | target/sparc: Set FloatInfZeroNaNRule explicitly |
62 | target/arm/helper.c | 358 +++++++++++++----------------- | 49 | target/xtensa: Set FloatInfZeroNaNRule explicitly |
63 | target/arm/hvf/hvf.c | 2 +- | 50 | target/x86: Set FloatInfZeroNaNRule explicitly |
64 | target/arm/kvm-stub.c | 4 +- | 51 | target/loongarch: Set FloatInfZeroNaNRule explicitly |
65 | target/arm/kvm.c | 4 +- | 52 | target/hppa: Set FloatInfZeroNaNRule explicitly |
66 | target/arm/machine.c | 4 +- | 53 | softfloat: Pass have_snan to pickNaNMulAdd |
67 | target/arm/op_helper.c | 57 ++--- | 54 | softfloat: Allow runtime choice of NaN propagation for muladd |
68 | target/arm/translate-a64.c | 14 +- | 55 | tests/fp: Explicitly set 3-NaN propagation rule |
69 | target/arm/translate-neon.c | 2 +- | 56 | target/arm: Set Float3NaNPropRule explicitly |
70 | target/arm/translate.c | 13 +- | 57 | target/loongarch: Set Float3NaNPropRule explicitly |
71 | tests/tcg/aarch64/bti-3.c | 42 ++++ | 58 | target/ppc: Set Float3NaNPropRule explicitly |
72 | tests/tcg/aarch64/Makefile.target | 6 +- | 59 | target/s390x: Set Float3NaNPropRule explicitly |
73 | 21 files changed, 738 insertions(+), 664 deletions(-) | 60 | target/sparc: Set Float3NaNPropRule explicitly |
74 | create mode 100644 target/arm/cpregs.h | 61 | target/mips: Set Float3NaNPropRule explicitly |
75 | create mode 100644 tests/tcg/aarch64/bti-3.c | 62 | target/xtensa: Set Float3NaNPropRule explicitly |
63 | target/i386: Set Float3NaNPropRule explicitly | ||
64 | target/hppa: Set Float3NaNPropRule explicitly | ||
65 | fpu: Remove use_first_nan field from float_status | ||
66 | target/m68k: Don't pass NULL float_status to floatx80_default_nan() | ||
67 | softfloat: Create floatx80 default NaN from parts64_default_nan | ||
68 | target/loongarch: Use normal float_status in fclass_s and fclass_d helpers | ||
69 | target/m68k: In frem helper, initialize local float_status from env->fp_status | ||
70 | target/m68k: Init local float_status from env fp_status in gdb get/set reg | ||
71 | target/sparc: Initialize local scratch float_status from env->fp_status | ||
72 | target/ppc: Use env->fp_status in helper_compute_fprf functions | ||
73 | fpu: Allow runtime choice of default NaN value | ||
74 | tests/fp: Set default NaN pattern explicitly | ||
75 | target/microblaze: Set default NaN pattern explicitly | ||
76 | target/i386: Set default NaN pattern explicitly | ||
77 | target/hppa: Set default NaN pattern explicitly | ||
78 | target/alpha: Set default NaN pattern explicitly | ||
79 | target/arm: Set default NaN pattern explicitly | ||
80 | target/loongarch: Set default NaN pattern explicitly | ||
81 | target/m68k: Set default NaN pattern explicitly | ||
82 | target/mips: Set default NaN pattern explicitly | ||
83 | target/openrisc: Set default NaN pattern explicitly | ||
84 | target/ppc: Set default NaN pattern explicitly | ||
85 | target/sh4: Set default NaN pattern explicitly | ||
86 | target/rx: Set default NaN pattern explicitly | ||
87 | target/s390x: Set default NaN pattern explicitly | ||
88 | target/sparc: Set default NaN pattern explicitly | ||
89 | target/xtensa: Set default NaN pattern explicitly | ||
90 | target/hexagon: Set default NaN pattern explicitly | ||
91 | target/riscv: Set default NaN pattern explicitly | ||
92 | target/tricore: Set default NaN pattern explicitly | ||
93 | fpu: Remove default handling for dnan_pattern | ||
94 | |||
95 | Richard Henderson (11): | ||
96 | target/arm: Copy entire float_status in is_ebf | ||
97 | softfloat: Inline pickNaNMulAdd | ||
98 | softfloat: Use goto for default nan case in pick_nan_muladd | ||
99 | softfloat: Remove which from parts_pick_nan_muladd | ||
100 | softfloat: Pad array size in pick_nan_muladd | ||
101 | softfloat: Move propagateFloatx80NaN to softfloat.c | ||
102 | softfloat: Use parts_pick_nan in propagateFloatx80NaN | ||
103 | softfloat: Inline pickNaN | ||
104 | softfloat: Share code between parts_pick_nan cases | ||
105 | softfloat: Sink frac_cmp in parts_pick_nan until needed | ||
106 | softfloat: Replace WHICH with RET in parts_pick_nan | ||
107 | |||
108 | Vikram Garhwal (1): | ||
109 | MAINTAINERS: Add correct email address for Vikram Garhwal | ||
110 | |||
111 | MAINTAINERS | 4 +- | ||
112 | include/fpu/softfloat-helpers.h | 38 +++- | ||
113 | include/fpu/softfloat-types.h | 89 +++++++- | ||
114 | include/hw/net/imx_fec.h | 9 +- | ||
115 | include/hw/net/lan9118_phy.h | 37 ++++ | ||
116 | include/hw/net/mii.h | 6 + | ||
117 | target/mips/fpu_helper.h | 20 ++ | ||
118 | target/sparc/helper.h | 4 +- | ||
119 | fpu/softfloat.c | 19 ++ | ||
120 | hw/net/imx_fec.c | 146 ++------------ | ||
121 | hw/net/lan9118.c | 137 ++----------- | ||
122 | hw/net/lan9118_phy.c | 222 ++++++++++++++++++++ | ||
123 | linux-user/arm/nwfpe/fpa11.c | 5 + | ||
124 | target/alpha/cpu.c | 2 + | ||
125 | target/arm/cpu.c | 10 + | ||
126 | target/arm/tcg/vec_helper.c | 20 +- | ||
127 | target/hexagon/cpu.c | 2 + | ||
128 | target/hppa/fpu_helper.c | 12 ++ | ||
129 | target/i386/tcg/fpu_helper.c | 12 ++ | ||
130 | target/loongarch/tcg/fpu_helper.c | 14 +- | ||
131 | target/m68k/cpu.c | 14 +- | ||
132 | target/m68k/fpu_helper.c | 6 +- | ||
133 | target/m68k/helper.c | 6 +- | ||
134 | target/microblaze/cpu.c | 2 + | ||
135 | target/mips/msa.c | 10 + | ||
136 | target/openrisc/cpu.c | 2 + | ||
137 | target/ppc/cpu_init.c | 19 ++ | ||
138 | target/ppc/fpu_helper.c | 3 +- | ||
139 | target/riscv/cpu.c | 2 + | ||
140 | target/rx/cpu.c | 2 + | ||
141 | target/s390x/cpu.c | 5 + | ||
142 | target/sh4/cpu.c | 2 + | ||
143 | target/sparc/cpu.c | 6 + | ||
144 | target/sparc/fop_helper.c | 8 +- | ||
145 | target/sparc/translate.c | 4 +- | ||
146 | target/tricore/helper.c | 2 + | ||
147 | target/xtensa/cpu.c | 4 + | ||
148 | target/xtensa/fpu_helper.c | 3 +- | ||
149 | tests/fp/fp-bench.c | 7 + | ||
150 | tests/fp/fp-test-log2.c | 1 + | ||
151 | tests/fp/fp-test.c | 7 + | ||
152 | fpu/softfloat-parts.c.inc | 152 +++++++++++--- | ||
153 | fpu/softfloat-specialize.c.inc | 412 ++------------------------------------ | ||
154 | .mailmap | 5 +- | ||
155 | hw/net/Kconfig | 5 + | ||
156 | hw/net/meson.build | 1 + | ||
157 | hw/net/trace-events | 10 +- | ||
158 | 47 files changed, 778 insertions(+), 730 deletions(-) | ||
159 | create mode 100644 include/hw/net/lan9118_phy.h | ||
160 | create mode 100644 hw/net/lan9118_phy.c | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Move ARMCPRegInfo and all related declarations to a new | 3 | A very similar implementation of the same device exists in imx_fec. Prepare for |
4 | internal header, out of the public cpu.h. | 4 | a common implementation by extracting a device model into its own files. |
5 | 5 | ||
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Some migration state has been moved into the new device model which breaks |
7 | migration compatibility for the following machines: | ||
8 | * smdkc210 | ||
9 | * realview-* | ||
10 | * vexpress-* | ||
11 | * kzm | ||
12 | * mps2-* | ||
13 | |||
14 | While breaking migration ABI, fix the size of the MII registers to be 16 bit, | ||
15 | as defined by IEEE 802.3u. | ||
16 | |||
17 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
18 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 20 | Message-id: 20241102125724.532843-2-shentey@gmail.com |
9 | Message-id: 20220501055028.646596-2-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 22 | --- |
12 | target/arm/cpregs.h | 413 +++++++++++++++++++++++++++++++++++++ | 23 | include/hw/net/lan9118_phy.h | 37 ++++++++ |
13 | target/arm/cpu.h | 368 --------------------------------- | 24 | hw/net/lan9118.c | 137 +++++----------------------- |
14 | hw/arm/pxa2xx.c | 1 + | 25 | hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++ |
15 | hw/arm/pxa2xx_pic.c | 1 + | 26 | hw/net/Kconfig | 4 + |
16 | hw/intc/arm_gicv3_cpuif.c | 1 + | 27 | hw/net/meson.build | 1 + |
17 | hw/intc/arm_gicv3_kvm.c | 2 + | 28 | 5 files changed, 233 insertions(+), 115 deletions(-) |
18 | target/arm/cpu.c | 1 + | 29 | create mode 100644 include/hw/net/lan9118_phy.h |
19 | target/arm/cpu64.c | 1 + | 30 | create mode 100644 hw/net/lan9118_phy.c |
20 | target/arm/cpu_tcg.c | 1 + | ||
21 | target/arm/gdbstub.c | 3 +- | ||
22 | target/arm/helper.c | 1 + | ||
23 | target/arm/op_helper.c | 1 + | ||
24 | target/arm/translate-a64.c | 4 +- | ||
25 | target/arm/translate.c | 3 +- | ||
26 | 14 files changed, 427 insertions(+), 374 deletions(-) | ||
27 | create mode 100644 target/arm/cpregs.h | ||
28 | 31 | ||
29 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 32 | diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h |
30 | new file mode 100644 | 33 | new file mode 100644 |
31 | index XXXXXXX..XXXXXXX | 34 | index XXXXXXX..XXXXXXX |
32 | --- /dev/null | 35 | --- /dev/null |
33 | +++ b/target/arm/cpregs.h | 36 | +++ b/include/hw/net/lan9118_phy.h |
34 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ |
35 | +/* | 38 | +/* |
36 | + * QEMU ARM CP Register access and descriptions | 39 | + * SMSC LAN9118 PHY emulation |
37 | + * | 40 | + * |
38 | + * Copyright (c) 2022 Linaro Ltd | 41 | + * Copyright (c) 2009 CodeSourcery, LLC. |
42 | + * Written by Paul Brook | ||
39 | + * | 43 | + * |
40 | + * This program is free software; you can redistribute it and/or | 44 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
41 | + * modify it under the terms of the GNU General Public License | 45 | + * See the COPYING file in the top-level directory. |
42 | + * as published by the Free Software Foundation; either version 2 | ||
43 | + * of the License, or (at your option) any later version. | ||
44 | + * | ||
45 | + * This program is distributed in the hope that it will be useful, | ||
46 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
47 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
48 | + * GNU General Public License for more details. | ||
49 | + * | ||
50 | + * You should have received a copy of the GNU General Public License | ||
51 | + * along with this program; if not, see | ||
52 | + * <http://www.gnu.org/licenses/gpl-2.0.html> | ||
53 | + */ | 46 | + */ |
54 | + | 47 | + |
55 | +#ifndef TARGET_ARM_CPREGS_H | 48 | +#ifndef HW_NET_LAN9118_PHY_H |
56 | +#define TARGET_ARM_CPREGS_H | 49 | +#define HW_NET_LAN9118_PHY_H |
57 | + | 50 | + |
58 | +/* | 51 | +#include "qom/object.h" |
59 | + * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a | 52 | +#include "hw/sysbus.h" |
60 | + * special-behaviour cp reg and bits [11..8] indicate what behaviour | 53 | + |
61 | + * it has. Otherwise it is a simple cp reg, where CONST indicates that | 54 | +#define TYPE_LAN9118_PHY "lan9118-phy" |
62 | + * TCG can assume the value to be constant (ie load at translate time) | 55 | +OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY) |
63 | + * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | 56 | + |
64 | + * indicates that the TB should not be ended after a write to this register | 57 | +typedef struct Lan9118PhyState { |
65 | + * (the default is that the TB ends after cp writes). OVERRIDE permits | 58 | + SysBusDevice parent_obj; |
66 | + * a register definition to override a previous definition for the | 59 | + |
67 | + * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | 60 | + uint16_t status; |
68 | + * old must have the OVERRIDE bit set. | 61 | + uint16_t control; |
69 | + * ALIAS indicates that this register is an alias view of some underlying | 62 | + uint16_t advertise; |
70 | + * state which is also visible via another register, and that the other | 63 | + uint16_t ints; |
71 | + * register is handling migration and reset; registers marked ALIAS will not be | 64 | + uint16_t int_mask; |
72 | + * migrated but may have their state set by syncing of register state from KVM. | 65 | + qemu_irq irq; |
73 | + * NO_RAW indicates that this register has no underlying state and does not | 66 | + bool link_down; |
74 | + * support raw access for state saving/loading; it will not be used for either | 67 | +} Lan9118PhyState; |
75 | + * migration or KVM state synchronization. (Typically this is for "registers" | 68 | + |
76 | + * which are actually used as instructions for cache maintenance and so on.) | 69 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down); |
77 | + * IO indicates that this register does I/O and therefore its accesses | 70 | +void lan9118_phy_reset(Lan9118PhyState *s); |
78 | + * need to be marked with gen_io_start() and also end the TB. In particular, | 71 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg); |
79 | + * registers which implement clocks or timers require this. | 72 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val); |
80 | + * RAISES_EXC is for when the read or write hook might raise an exception; | 73 | + |
81 | + * the generated code will synchronize the CPU state before calling the hook | ||
82 | + * so that it is safe for the hook to call raise_exception(). | ||
83 | + * NEWEL is for writes to registers that might change the exception | ||
84 | + * level - typically on older ARM chips. For those cases we need to | ||
85 | + * re-read the new el when recomputing the translation flags. | ||
86 | + */ | ||
87 | +#define ARM_CP_SPECIAL 0x0001 | ||
88 | +#define ARM_CP_CONST 0x0002 | ||
89 | +#define ARM_CP_64BIT 0x0004 | ||
90 | +#define ARM_CP_SUPPRESS_TB_END 0x0008 | ||
91 | +#define ARM_CP_OVERRIDE 0x0010 | ||
92 | +#define ARM_CP_ALIAS 0x0020 | ||
93 | +#define ARM_CP_IO 0x0040 | ||
94 | +#define ARM_CP_NO_RAW 0x0080 | ||
95 | +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) | ||
96 | +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) | ||
97 | +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | ||
98 | +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | ||
99 | +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | ||
100 | +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) | ||
101 | +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) | ||
102 | +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA | ||
103 | +#define ARM_CP_FPU 0x1000 | ||
104 | +#define ARM_CP_SVE 0x2000 | ||
105 | +#define ARM_CP_NO_GDB 0x4000 | ||
106 | +#define ARM_CP_RAISES_EXC 0x8000 | ||
107 | +#define ARM_CP_NEWEL 0x10000 | ||
108 | +/* Used only as a terminator for ARMCPRegInfo lists */ | ||
109 | +#define ARM_CP_SENTINEL 0xfffff | ||
110 | +/* Mask of only the flag bits in a type field */ | ||
111 | +#define ARM_CP_FLAG_MASK 0x1f0ff | ||
112 | + | ||
113 | +/* | ||
114 | + * Valid values for ARMCPRegInfo state field, indicating which of | ||
115 | + * the AArch32 and AArch64 execution states this register is visible in. | ||
116 | + * If the reginfo doesn't explicitly specify then it is AArch32 only. | ||
117 | + * If the reginfo is declared to be visible in both states then a second | ||
118 | + * reginfo is synthesised for the AArch32 view of the AArch64 register, | ||
119 | + * such that the AArch32 view is the lower 32 bits of the AArch64 one. | ||
120 | + * Note that we rely on the values of these enums as we iterate through | ||
121 | + * the various states in some places. | ||
122 | + */ | ||
123 | +enum { | ||
124 | + ARM_CP_STATE_AA32 = 0, | ||
125 | + ARM_CP_STATE_AA64 = 1, | ||
126 | + ARM_CP_STATE_BOTH = 2, | ||
127 | +}; | ||
128 | + | ||
129 | +/* | ||
130 | + * ARM CP register secure state flags. These flags identify security state | ||
131 | + * attributes for a given CP register entry. | ||
132 | + * The existence of both or neither secure and non-secure flags indicates that | ||
133 | + * the register has both a secure and non-secure hash entry. A single one of | ||
134 | + * these flags causes the register to only be hashed for the specified | ||
135 | + * security state. | ||
136 | + * Although definitions may have any combination of the S/NS bits, each | ||
137 | + * registered entry will only have one to identify whether the entry is secure | ||
138 | + * or non-secure. | ||
139 | + */ | ||
140 | +enum { | ||
141 | + ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | ||
142 | + ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | ||
143 | +}; | ||
144 | + | ||
145 | +/* | ||
146 | + * Return true if cptype is a valid type field. This is used to try to | ||
147 | + * catch errors where the sentinel has been accidentally left off the end | ||
148 | + * of a list of registers. | ||
149 | + */ | ||
150 | +static inline bool cptype_valid(int cptype) | ||
151 | +{ | ||
152 | + return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | ||
153 | + || ((cptype & ARM_CP_SPECIAL) && | ||
154 | + ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); | ||
155 | +} | ||
156 | + | ||
157 | +/* | ||
158 | + * Access rights: | ||
159 | + * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | ||
160 | + * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | ||
161 | + * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | ||
162 | + * (ie any of the privileged modes in Secure state, or Monitor mode). | ||
163 | + * If a register is accessible in one privilege level it's always accessible | ||
164 | + * in higher privilege levels too. Since "Secure PL1" also follows this rule | ||
165 | + * (ie anything visible in PL2 is visible in S-PL1, some things are only | ||
166 | + * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | ||
167 | + * terminology a little and call this PL3. | ||
168 | + * In AArch64 things are somewhat simpler as the PLx bits line up exactly | ||
169 | + * with the ELx exception levels. | ||
170 | + * | ||
171 | + * If access permissions for a register are more complex than can be | ||
172 | + * described with these bits, then use a laxer set of restrictions, and | ||
173 | + * do the more restrictive/complex check inside a helper function. | ||
174 | + */ | ||
175 | +#define PL3_R 0x80 | ||
176 | +#define PL3_W 0x40 | ||
177 | +#define PL2_R (0x20 | PL3_R) | ||
178 | +#define PL2_W (0x10 | PL3_W) | ||
179 | +#define PL1_R (0x08 | PL2_R) | ||
180 | +#define PL1_W (0x04 | PL2_W) | ||
181 | +#define PL0_R (0x02 | PL1_R) | ||
182 | +#define PL0_W (0x01 | PL1_W) | ||
183 | + | ||
184 | +/* | ||
185 | + * For user-mode some registers are accessible to EL0 via a kernel | ||
186 | + * trap-and-emulate ABI. In this case we define the read permissions | ||
187 | + * as actually being PL0_R. However some bits of any given register | ||
188 | + * may still be masked. | ||
189 | + */ | ||
190 | +#ifdef CONFIG_USER_ONLY | ||
191 | +#define PL0U_R PL0_R | ||
192 | +#else | ||
193 | +#define PL0U_R PL1_R | ||
194 | +#endif | 74 | +#endif |
195 | + | 75 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c |
196 | +#define PL3_RW (PL3_R | PL3_W) | ||
197 | +#define PL2_RW (PL2_R | PL2_W) | ||
198 | +#define PL1_RW (PL1_R | PL1_W) | ||
199 | +#define PL0_RW (PL0_R | PL0_W) | ||
200 | + | ||
201 | +typedef enum CPAccessResult { | ||
202 | + /* Access is permitted */ | ||
203 | + CP_ACCESS_OK = 0, | ||
204 | + /* | ||
205 | + * Access fails due to a configurable trap or enable which would | ||
206 | + * result in a categorized exception syndrome giving information about | ||
207 | + * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | ||
208 | + * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or | ||
209 | + * PL1 if in EL0, otherwise to the current EL). | ||
210 | + */ | ||
211 | + CP_ACCESS_TRAP = 1, | ||
212 | + /* | ||
213 | + * Access fails and results in an exception syndrome 0x0 ("uncategorized"). | ||
214 | + * Note that this is not a catch-all case -- the set of cases which may | ||
215 | + * result in this failure is specifically defined by the architecture. | ||
216 | + */ | ||
217 | + CP_ACCESS_TRAP_UNCATEGORIZED = 2, | ||
218 | + /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ | ||
219 | + CP_ACCESS_TRAP_EL2 = 3, | ||
220 | + CP_ACCESS_TRAP_EL3 = 4, | ||
221 | + /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ | ||
222 | + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, | ||
223 | + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, | ||
224 | +} CPAccessResult; | ||
225 | + | ||
226 | +typedef struct ARMCPRegInfo ARMCPRegInfo; | ||
227 | + | ||
228 | +/* | ||
229 | + * Access functions for coprocessor registers. These cannot fail and | ||
230 | + * may not raise exceptions. | ||
231 | + */ | ||
232 | +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
233 | +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | ||
234 | + uint64_t value); | ||
235 | +/* Access permission check functions for coprocessor registers. */ | ||
236 | +typedef CPAccessResult CPAccessFn(CPUARMState *env, | ||
237 | + const ARMCPRegInfo *opaque, | ||
238 | + bool isread); | ||
239 | +/* Hook function for register reset */ | ||
240 | +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
241 | + | ||
242 | +#define CP_ANY 0xff | ||
243 | + | ||
244 | +/* Definition of an ARM coprocessor register */ | ||
245 | +struct ARMCPRegInfo { | ||
246 | + /* Name of register (useful mainly for debugging, need not be unique) */ | ||
247 | + const char *name; | ||
248 | + /* | ||
249 | + * Location of register: coprocessor number and (crn,crm,opc1,opc2) | ||
250 | + * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | ||
251 | + * 'wildcard' field -- any value of that field in the MRC/MCR insn | ||
252 | + * will be decoded to this register. The register read and write | ||
253 | + * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | ||
254 | + * used by the program, so it is possible to register a wildcard and | ||
255 | + * then behave differently on read/write if necessary. | ||
256 | + * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | ||
257 | + * must both be zero. | ||
258 | + * For AArch64-visible registers, opc0 is also used. | ||
259 | + * Since there are no "coprocessors" in AArch64, cp is purely used as a | ||
260 | + * way to distinguish (for KVM's benefit) guest-visible system registers | ||
261 | + * from demuxed ones provided to preserve the "no side effects on | ||
262 | + * KVM register read/write from QEMU" semantics. cp==0x13 is guest | ||
263 | + * visible (to match KVM's encoding); cp==0 will be converted to | ||
264 | + * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | ||
265 | + */ | ||
266 | + uint8_t cp; | ||
267 | + uint8_t crn; | ||
268 | + uint8_t crm; | ||
269 | + uint8_t opc0; | ||
270 | + uint8_t opc1; | ||
271 | + uint8_t opc2; | ||
272 | + /* Execution state in which this register is visible: ARM_CP_STATE_* */ | ||
273 | + int state; | ||
274 | + /* Register type: ARM_CP_* bits/values */ | ||
275 | + int type; | ||
276 | + /* Access rights: PL*_[RW] */ | ||
277 | + int access; | ||
278 | + /* Security state: ARM_CP_SECSTATE_* bits/values */ | ||
279 | + int secure; | ||
280 | + /* | ||
281 | + * The opaque pointer passed to define_arm_cp_regs_with_opaque() when | ||
282 | + * this register was defined: can be used to hand data through to the | ||
283 | + * register read/write functions, since they are passed the ARMCPRegInfo*. | ||
284 | + */ | ||
285 | + void *opaque; | ||
286 | + /* | ||
287 | + * Value of this register, if it is ARM_CP_CONST. Otherwise, if | ||
288 | + * fieldoffset is non-zero, the reset value of the register. | ||
289 | + */ | ||
290 | + uint64_t resetvalue; | ||
291 | + /* | ||
292 | + * Offset of the field in CPUARMState for this register. | ||
293 | + * This is not needed if either: | ||
294 | + * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs | ||
295 | + * 2. both readfn and writefn are specified | ||
296 | + */ | ||
297 | + ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | ||
298 | + | ||
299 | + /* | ||
300 | + * Offsets of the secure and non-secure fields in CPUARMState for the | ||
301 | + * register if it is banked. These fields are only used during the static | ||
302 | + * registration of a register. During hashing the bank associated | ||
303 | + * with a given security state is copied to fieldoffset which is used from | ||
304 | + * there on out. | ||
305 | + * | ||
306 | + * It is expected that register definitions use either fieldoffset or | ||
307 | + * bank_fieldoffsets in the definition but not both. It is also expected | ||
308 | + * that both bank offsets are set when defining a banked register. This | ||
309 | + * use indicates that a register is banked. | ||
310 | + */ | ||
311 | + ptrdiff_t bank_fieldoffsets[2]; | ||
312 | + | ||
313 | + /* | ||
314 | + * Function for making any access checks for this register in addition to | ||
315 | + * those specified by the 'access' permissions bits. If NULL, no extra | ||
316 | + * checks required. The access check is performed at runtime, not at | ||
317 | + * translate time. | ||
318 | + */ | ||
319 | + CPAccessFn *accessfn; | ||
320 | + /* | ||
321 | + * Function for handling reads of this register. If NULL, then reads | ||
322 | + * will be done by loading from the offset into CPUARMState specified | ||
323 | + * by fieldoffset. | ||
324 | + */ | ||
325 | + CPReadFn *readfn; | ||
326 | + /* | ||
327 | + * Function for handling writes of this register. If NULL, then writes | ||
328 | + * will be done by writing to the offset into CPUARMState specified | ||
329 | + * by fieldoffset. | ||
330 | + */ | ||
331 | + CPWriteFn *writefn; | ||
332 | + /* | ||
333 | + * Function for doing a "raw" read; used when we need to copy | ||
334 | + * coprocessor state to the kernel for KVM or out for | ||
335 | + * migration. This only needs to be provided if there is also a | ||
336 | + * readfn and it has side effects (for instance clear-on-read bits). | ||
337 | + */ | ||
338 | + CPReadFn *raw_readfn; | ||
339 | + /* | ||
340 | + * Function for doing a "raw" write; used when we need to copy KVM | ||
341 | + * kernel coprocessor state into userspace, or for inbound | ||
342 | + * migration. This only needs to be provided if there is also a | ||
343 | + * writefn and it masks out "unwritable" bits or has write-one-to-clear | ||
344 | + * or similar behaviour. | ||
345 | + */ | ||
346 | + CPWriteFn *raw_writefn; | ||
347 | + /* | ||
348 | + * Function for resetting the register. If NULL, then reset will be done | ||
349 | + * by writing resetvalue to the field specified in fieldoffset. If | ||
350 | + * fieldoffset is 0 then no reset will be done. | ||
351 | + */ | ||
352 | + CPResetFn *resetfn; | ||
353 | + | ||
354 | + /* | ||
355 | + * "Original" writefn and readfn. | ||
356 | + * For ARMv8.1-VHE register aliases, we overwrite the read/write | ||
357 | + * accessor functions of various EL1/EL0 to perform the runtime | ||
358 | + * check for which sysreg should actually be modified, and then | ||
359 | + * forwards the operation. Before overwriting the accessors, | ||
360 | + * the original function is copied here, so that accesses that | ||
361 | + * really do go to the EL1/EL0 version proceed normally. | ||
362 | + * (The corresponding EL2 register is linked via opaque.) | ||
363 | + */ | ||
364 | + CPReadFn *orig_readfn; | ||
365 | + CPWriteFn *orig_writefn; | ||
366 | +}; | ||
367 | + | ||
368 | +/* | ||
369 | + * Macros which are lvalues for the field in CPUARMState for the | ||
370 | + * ARMCPRegInfo *ri. | ||
371 | + */ | ||
372 | +#define CPREG_FIELD32(env, ri) \ | ||
373 | + (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | ||
374 | +#define CPREG_FIELD64(env, ri) \ | ||
375 | + (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | ||
376 | + | ||
377 | +#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | ||
378 | + | ||
379 | +void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | ||
380 | + const ARMCPRegInfo *regs, void *opaque); | ||
381 | +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
382 | + const ARMCPRegInfo *regs, void *opaque); | ||
383 | +static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
384 | +{ | ||
385 | + define_arm_cp_regs_with_opaque(cpu, regs, 0); | ||
386 | +} | ||
387 | +static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
388 | +{ | ||
389 | + define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | ||
390 | +} | ||
391 | +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); | ||
392 | + | ||
393 | +/* | ||
394 | + * Definition of an ARM co-processor register as viewed from | ||
395 | + * userspace. This is used for presenting sanitised versions of | ||
396 | + * registers to userspace when emulating the Linux AArch64 CPU | ||
397 | + * ID/feature ABI (advertised as HWCAP_CPUID). | ||
398 | + */ | ||
399 | +typedef struct ARMCPRegUserSpaceInfo { | ||
400 | + /* Name of register */ | ||
401 | + const char *name; | ||
402 | + | ||
403 | + /* Is the name actually a glob pattern */ | ||
404 | + bool is_glob; | ||
405 | + | ||
406 | + /* Only some bits are exported to user space */ | ||
407 | + uint64_t exported_bits; | ||
408 | + | ||
409 | + /* Fixed bits are applied after the mask */ | ||
410 | + uint64_t fixed_bits; | ||
411 | +} ARMCPRegUserSpaceInfo; | ||
412 | + | ||
413 | +#define REGUSERINFO_SENTINEL { .name = NULL } | ||
414 | + | ||
415 | +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); | ||
416 | + | ||
417 | +/* CPWriteFn that can be used to implement writes-ignored behaviour */ | ||
418 | +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | ||
419 | + uint64_t value); | ||
420 | +/* CPReadFn that can be used for read-as-zero behaviour */ | ||
421 | +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); | ||
422 | + | ||
423 | +/* | ||
424 | + * CPResetFn that does nothing, for use if no reset is required even | ||
425 | + * if fieldoffset is non zero. | ||
426 | + */ | ||
427 | +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
428 | + | ||
429 | +/* | ||
430 | + * Return true if this reginfo struct's field in the cpu state struct | ||
431 | + * is 64 bits wide. | ||
432 | + */ | ||
433 | +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) | ||
434 | +{ | ||
435 | + return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); | ||
436 | +} | ||
437 | + | ||
438 | +static inline bool cp_access_ok(int current_el, | ||
439 | + const ARMCPRegInfo *ri, int isread) | ||
440 | +{ | ||
441 | + return (ri->access >> ((current_el * 2) + isread)) & 1; | ||
442 | +} | ||
443 | + | ||
444 | +/* Raw read of a coprocessor register (as needed for migration, etc) */ | ||
445 | +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); | ||
446 | + | ||
447 | +#endif /* TARGET_ARM_CPREGS_H */ | ||
448 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
449 | index XXXXXXX..XXXXXXX 100644 | 76 | index XXXXXXX..XXXXXXX 100644 |
450 | --- a/target/arm/cpu.h | 77 | --- a/hw/net/lan9118.c |
451 | +++ b/target/arm/cpu.h | 78 | +++ b/hw/net/lan9118.c |
452 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | 79 | @@ -XXX,XX +XXX,XX @@ |
453 | return kvmid; | 80 | #include "net/net.h" |
81 | #include "net/eth.h" | ||
82 | #include "hw/irq.h" | ||
83 | +#include "hw/net/lan9118_phy.h" | ||
84 | #include "hw/net/lan9118.h" | ||
85 | #include "hw/ptimer.h" | ||
86 | #include "hw/qdev-properties.h" | ||
87 | @@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) | ||
88 | #define MAC_CR_RXEN 0x00000004 | ||
89 | #define MAC_CR_RESERVED 0x7f404213 | ||
90 | |||
91 | -#define PHY_INT_ENERGYON 0x80 | ||
92 | -#define PHY_INT_AUTONEG_COMPLETE 0x40 | ||
93 | -#define PHY_INT_FAULT 0x20 | ||
94 | -#define PHY_INT_DOWN 0x10 | ||
95 | -#define PHY_INT_AUTONEG_LP 0x08 | ||
96 | -#define PHY_INT_PARFAULT 0x04 | ||
97 | -#define PHY_INT_AUTONEG_PAGE 0x02 | ||
98 | - | ||
99 | #define GPT_TIMER_EN 0x20000000 | ||
100 | |||
101 | /* | ||
102 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | ||
103 | uint32_t mac_mii_data; | ||
104 | uint32_t mac_flow; | ||
105 | |||
106 | - uint32_t phy_status; | ||
107 | - uint32_t phy_control; | ||
108 | - uint32_t phy_advertise; | ||
109 | - uint32_t phy_int; | ||
110 | - uint32_t phy_int_mask; | ||
111 | + Lan9118PhyState mii; | ||
112 | + IRQState mii_irq; | ||
113 | |||
114 | int32_t eeprom_writable; | ||
115 | uint8_t eeprom[128]; | ||
116 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | ||
117 | |||
118 | static const VMStateDescription vmstate_lan9118 = { | ||
119 | .name = "lan9118", | ||
120 | - .version_id = 2, | ||
121 | - .minimum_version_id = 1, | ||
122 | + .version_id = 3, | ||
123 | + .minimum_version_id = 3, | ||
124 | .fields = (const VMStateField[]) { | ||
125 | VMSTATE_PTIMER(timer, lan9118_state), | ||
126 | VMSTATE_UINT32(irq_cfg, lan9118_state), | ||
127 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = { | ||
128 | VMSTATE_UINT32(mac_mii_acc, lan9118_state), | ||
129 | VMSTATE_UINT32(mac_mii_data, lan9118_state), | ||
130 | VMSTATE_UINT32(mac_flow, lan9118_state), | ||
131 | - VMSTATE_UINT32(phy_status, lan9118_state), | ||
132 | - VMSTATE_UINT32(phy_control, lan9118_state), | ||
133 | - VMSTATE_UINT32(phy_advertise, lan9118_state), | ||
134 | - VMSTATE_UINT32(phy_int, lan9118_state), | ||
135 | - VMSTATE_UINT32(phy_int_mask, lan9118_state), | ||
136 | VMSTATE_INT32(eeprom_writable, lan9118_state), | ||
137 | VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), | ||
138 | VMSTATE_INT32(tx_fifo_size, lan9118_state), | ||
139 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s) | ||
140 | lan9118_mac_changed(s); | ||
454 | } | 141 | } |
455 | 142 | ||
456 | -/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a | 143 | -static void phy_update_irq(lan9118_state *s) |
457 | - * special-behaviour cp reg and bits [11..8] indicate what behaviour | 144 | +static void lan9118_update_irq(void *opaque, int n, int level) |
458 | - * it has. Otherwise it is a simple cp reg, where CONST indicates that | 145 | { |
459 | - * TCG can assume the value to be constant (ie load at translate time) | 146 | - if (s->phy_int & s->phy_int_mask) { |
460 | - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | 147 | + lan9118_state *s = opaque; |
461 | - * indicates that the TB should not be ended after a write to this register | 148 | + |
462 | - * (the default is that the TB ends after cp writes). OVERRIDE permits | 149 | + if (level) { |
463 | - * a register definition to override a previous definition for the | 150 | s->int_sts |= PHY_INT; |
464 | - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | 151 | } else { |
465 | - * old must have the OVERRIDE bit set. | 152 | s->int_sts &= ~PHY_INT; |
466 | - * ALIAS indicates that this register is an alias view of some underlying | 153 | @@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s) |
467 | - * state which is also visible via another register, and that the other | 154 | lan9118_update(s); |
468 | - * register is handling migration and reset; registers marked ALIAS will not be | 155 | } |
469 | - * migrated but may have their state set by syncing of register state from KVM. | 156 | |
470 | - * NO_RAW indicates that this register has no underlying state and does not | 157 | -static void phy_update_link(lan9118_state *s) |
471 | - * support raw access for state saving/loading; it will not be used for either | ||
472 | - * migration or KVM state synchronization. (Typically this is for "registers" | ||
473 | - * which are actually used as instructions for cache maintenance and so on.) | ||
474 | - * IO indicates that this register does I/O and therefore its accesses | ||
475 | - * need to be marked with gen_io_start() and also end the TB. In particular, | ||
476 | - * registers which implement clocks or timers require this. | ||
477 | - * RAISES_EXC is for when the read or write hook might raise an exception; | ||
478 | - * the generated code will synchronize the CPU state before calling the hook | ||
479 | - * so that it is safe for the hook to call raise_exception(). | ||
480 | - * NEWEL is for writes to registers that might change the exception | ||
481 | - * level - typically on older ARM chips. For those cases we need to | ||
482 | - * re-read the new el when recomputing the translation flags. | ||
483 | - */ | ||
484 | -#define ARM_CP_SPECIAL 0x0001 | ||
485 | -#define ARM_CP_CONST 0x0002 | ||
486 | -#define ARM_CP_64BIT 0x0004 | ||
487 | -#define ARM_CP_SUPPRESS_TB_END 0x0008 | ||
488 | -#define ARM_CP_OVERRIDE 0x0010 | ||
489 | -#define ARM_CP_ALIAS 0x0020 | ||
490 | -#define ARM_CP_IO 0x0040 | ||
491 | -#define ARM_CP_NO_RAW 0x0080 | ||
492 | -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) | ||
493 | -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) | ||
494 | -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | ||
495 | -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | ||
496 | -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | ||
497 | -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) | ||
498 | -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) | ||
499 | -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA | ||
500 | -#define ARM_CP_FPU 0x1000 | ||
501 | -#define ARM_CP_SVE 0x2000 | ||
502 | -#define ARM_CP_NO_GDB 0x4000 | ||
503 | -#define ARM_CP_RAISES_EXC 0x8000 | ||
504 | -#define ARM_CP_NEWEL 0x10000 | ||
505 | -/* Used only as a terminator for ARMCPRegInfo lists */ | ||
506 | -#define ARM_CP_SENTINEL 0xfffff | ||
507 | -/* Mask of only the flag bits in a type field */ | ||
508 | -#define ARM_CP_FLAG_MASK 0x1f0ff | ||
509 | - | ||
510 | -/* Valid values for ARMCPRegInfo state field, indicating which of | ||
511 | - * the AArch32 and AArch64 execution states this register is visible in. | ||
512 | - * If the reginfo doesn't explicitly specify then it is AArch32 only. | ||
513 | - * If the reginfo is declared to be visible in both states then a second | ||
514 | - * reginfo is synthesised for the AArch32 view of the AArch64 register, | ||
515 | - * such that the AArch32 view is the lower 32 bits of the AArch64 one. | ||
516 | - * Note that we rely on the values of these enums as we iterate through | ||
517 | - * the various states in some places. | ||
518 | - */ | ||
519 | -enum { | ||
520 | - ARM_CP_STATE_AA32 = 0, | ||
521 | - ARM_CP_STATE_AA64 = 1, | ||
522 | - ARM_CP_STATE_BOTH = 2, | ||
523 | -}; | ||
524 | - | ||
525 | -/* ARM CP register secure state flags. These flags identify security state | ||
526 | - * attributes for a given CP register entry. | ||
527 | - * The existence of both or neither secure and non-secure flags indicates that | ||
528 | - * the register has both a secure and non-secure hash entry. A single one of | ||
529 | - * these flags causes the register to only be hashed for the specified | ||
530 | - * security state. | ||
531 | - * Although definitions may have any combination of the S/NS bits, each | ||
532 | - * registered entry will only have one to identify whether the entry is secure | ||
533 | - * or non-secure. | ||
534 | - */ | ||
535 | -enum { | ||
536 | - ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | ||
537 | - ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | ||
538 | -}; | ||
539 | - | ||
540 | -/* Return true if cptype is a valid type field. This is used to try to | ||
541 | - * catch errors where the sentinel has been accidentally left off the end | ||
542 | - * of a list of registers. | ||
543 | - */ | ||
544 | -static inline bool cptype_valid(int cptype) | ||
545 | -{ | 158 | -{ |
546 | - return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | 159 | - /* Autonegotiation status mirrors link status. */ |
547 | - || ((cptype & ARM_CP_SPECIAL) && | 160 | - if (qemu_get_queue(s->nic)->link_down) { |
548 | - ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); | 161 | - s->phy_status &= ~0x0024; |
162 | - s->phy_int |= PHY_INT_DOWN; | ||
163 | - } else { | ||
164 | - s->phy_status |= 0x0024; | ||
165 | - s->phy_int |= PHY_INT_ENERGYON; | ||
166 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
167 | - } | ||
168 | - phy_update_irq(s); | ||
549 | -} | 169 | -} |
550 | - | 170 | - |
551 | -/* Access rights: | 171 | static void lan9118_set_link(NetClientState *nc) |
552 | - * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | ||
553 | - * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | ||
554 | - * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | ||
555 | - * (ie any of the privileged modes in Secure state, or Monitor mode). | ||
556 | - * If a register is accessible in one privilege level it's always accessible | ||
557 | - * in higher privilege levels too. Since "Secure PL1" also follows this rule | ||
558 | - * (ie anything visible in PL2 is visible in S-PL1, some things are only | ||
559 | - * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | ||
560 | - * terminology a little and call this PL3. | ||
561 | - * In AArch64 things are somewhat simpler as the PLx bits line up exactly | ||
562 | - * with the ELx exception levels. | ||
563 | - * | ||
564 | - * If access permissions for a register are more complex than can be | ||
565 | - * described with these bits, then use a laxer set of restrictions, and | ||
566 | - * do the more restrictive/complex check inside a helper function. | ||
567 | - */ | ||
568 | -#define PL3_R 0x80 | ||
569 | -#define PL3_W 0x40 | ||
570 | -#define PL2_R (0x20 | PL3_R) | ||
571 | -#define PL2_W (0x10 | PL3_W) | ||
572 | -#define PL1_R (0x08 | PL2_R) | ||
573 | -#define PL1_W (0x04 | PL2_W) | ||
574 | -#define PL0_R (0x02 | PL1_R) | ||
575 | -#define PL0_W (0x01 | PL1_W) | ||
576 | - | ||
577 | -/* | ||
578 | - * For user-mode some registers are accessible to EL0 via a kernel | ||
579 | - * trap-and-emulate ABI. In this case we define the read permissions | ||
580 | - * as actually being PL0_R. However some bits of any given register | ||
581 | - * may still be masked. | ||
582 | - */ | ||
583 | -#ifdef CONFIG_USER_ONLY | ||
584 | -#define PL0U_R PL0_R | ||
585 | -#else | ||
586 | -#define PL0U_R PL1_R | ||
587 | -#endif | ||
588 | - | ||
589 | -#define PL3_RW (PL3_R | PL3_W) | ||
590 | -#define PL2_RW (PL2_R | PL2_W) | ||
591 | -#define PL1_RW (PL1_R | PL1_W) | ||
592 | -#define PL0_RW (PL0_R | PL0_W) | ||
593 | - | ||
594 | /* Return the highest implemented Exception Level */ | ||
595 | static inline int arm_highest_el(CPUARMState *env) | ||
596 | { | 172 | { |
597 | @@ -XXX,XX +XXX,XX @@ static inline int arm_current_el(CPUARMState *env) | 173 | - phy_update_link(qemu_get_nic_opaque(nc)); |
174 | -} | ||
175 | - | ||
176 | -static void phy_reset(lan9118_state *s) | ||
177 | -{ | ||
178 | - s->phy_status = 0x7809; | ||
179 | - s->phy_control = 0x3000; | ||
180 | - s->phy_advertise = 0x01e1; | ||
181 | - s->phy_int_mask = 0; | ||
182 | - s->phy_int = 0; | ||
183 | - phy_update_link(s); | ||
184 | + lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii, | ||
185 | + nc->link_down); | ||
186 | } | ||
187 | |||
188 | static void lan9118_reset(DeviceState *d) | ||
189 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d) | ||
190 | s->read_word_n = 0; | ||
191 | s->write_word_n = 0; | ||
192 | |||
193 | - phy_reset(s); | ||
194 | - | ||
195 | s->eeprom_writable = 0; | ||
196 | lan9118_reload_eeprom(s); | ||
197 | } | ||
198 | @@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s) | ||
199 | uint32_t status; | ||
200 | |||
201 | /* FIXME: Honor TX disable, and allow queueing of packets. */ | ||
202 | - if (s->phy_control & 0x4000) { | ||
203 | + if (s->mii.control & 0x4000) { | ||
204 | /* This assumes the receive routine doesn't touch the VLANClient. */ | ||
205 | qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); | ||
206 | } else { | ||
207 | @@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val) | ||
598 | } | 208 | } |
599 | } | 209 | } |
600 | 210 | ||
601 | -typedef struct ARMCPRegInfo ARMCPRegInfo; | 211 | -static uint32_t do_phy_read(lan9118_state *s, int reg) |
602 | - | ||
603 | -typedef enum CPAccessResult { | ||
604 | - /* Access is permitted */ | ||
605 | - CP_ACCESS_OK = 0, | ||
606 | - /* Access fails due to a configurable trap or enable which would | ||
607 | - * result in a categorized exception syndrome giving information about | ||
608 | - * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | ||
609 | - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or | ||
610 | - * PL1 if in EL0, otherwise to the current EL). | ||
611 | - */ | ||
612 | - CP_ACCESS_TRAP = 1, | ||
613 | - /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). | ||
614 | - * Note that this is not a catch-all case -- the set of cases which may | ||
615 | - * result in this failure is specifically defined by the architecture. | ||
616 | - */ | ||
617 | - CP_ACCESS_TRAP_UNCATEGORIZED = 2, | ||
618 | - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ | ||
619 | - CP_ACCESS_TRAP_EL2 = 3, | ||
620 | - CP_ACCESS_TRAP_EL3 = 4, | ||
621 | - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ | ||
622 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, | ||
623 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, | ||
624 | -} CPAccessResult; | ||
625 | - | ||
626 | -/* Access functions for coprocessor registers. These cannot fail and | ||
627 | - * may not raise exceptions. | ||
628 | - */ | ||
629 | -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
630 | -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | ||
631 | - uint64_t value); | ||
632 | -/* Access permission check functions for coprocessor registers. */ | ||
633 | -typedef CPAccessResult CPAccessFn(CPUARMState *env, | ||
634 | - const ARMCPRegInfo *opaque, | ||
635 | - bool isread); | ||
636 | -/* Hook function for register reset */ | ||
637 | -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | ||
638 | - | ||
639 | -#define CP_ANY 0xff | ||
640 | - | ||
641 | -/* Definition of an ARM coprocessor register */ | ||
642 | -struct ARMCPRegInfo { | ||
643 | - /* Name of register (useful mainly for debugging, need not be unique) */ | ||
644 | - const char *name; | ||
645 | - /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | ||
646 | - * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | ||
647 | - * 'wildcard' field -- any value of that field in the MRC/MCR insn | ||
648 | - * will be decoded to this register. The register read and write | ||
649 | - * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | ||
650 | - * used by the program, so it is possible to register a wildcard and | ||
651 | - * then behave differently on read/write if necessary. | ||
652 | - * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | ||
653 | - * must both be zero. | ||
654 | - * For AArch64-visible registers, opc0 is also used. | ||
655 | - * Since there are no "coprocessors" in AArch64, cp is purely used as a | ||
656 | - * way to distinguish (for KVM's benefit) guest-visible system registers | ||
657 | - * from demuxed ones provided to preserve the "no side effects on | ||
658 | - * KVM register read/write from QEMU" semantics. cp==0x13 is guest | ||
659 | - * visible (to match KVM's encoding); cp==0 will be converted to | ||
660 | - * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | ||
661 | - */ | ||
662 | - uint8_t cp; | ||
663 | - uint8_t crn; | ||
664 | - uint8_t crm; | ||
665 | - uint8_t opc0; | ||
666 | - uint8_t opc1; | ||
667 | - uint8_t opc2; | ||
668 | - /* Execution state in which this register is visible: ARM_CP_STATE_* */ | ||
669 | - int state; | ||
670 | - /* Register type: ARM_CP_* bits/values */ | ||
671 | - int type; | ||
672 | - /* Access rights: PL*_[RW] */ | ||
673 | - int access; | ||
674 | - /* Security state: ARM_CP_SECSTATE_* bits/values */ | ||
675 | - int secure; | ||
676 | - /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when | ||
677 | - * this register was defined: can be used to hand data through to the | ||
678 | - * register read/write functions, since they are passed the ARMCPRegInfo*. | ||
679 | - */ | ||
680 | - void *opaque; | ||
681 | - /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | ||
682 | - * fieldoffset is non-zero, the reset value of the register. | ||
683 | - */ | ||
684 | - uint64_t resetvalue; | ||
685 | - /* Offset of the field in CPUARMState for this register. | ||
686 | - * | ||
687 | - * This is not needed if either: | ||
688 | - * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs | ||
689 | - * 2. both readfn and writefn are specified | ||
690 | - */ | ||
691 | - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | ||
692 | - | ||
693 | - /* Offsets of the secure and non-secure fields in CPUARMState for the | ||
694 | - * register if it is banked. These fields are only used during the static | ||
695 | - * registration of a register. During hashing the bank associated | ||
696 | - * with a given security state is copied to fieldoffset which is used from | ||
697 | - * there on out. | ||
698 | - * | ||
699 | - * It is expected that register definitions use either fieldoffset or | ||
700 | - * bank_fieldoffsets in the definition but not both. It is also expected | ||
701 | - * that both bank offsets are set when defining a banked register. This | ||
702 | - * use indicates that a register is banked. | ||
703 | - */ | ||
704 | - ptrdiff_t bank_fieldoffsets[2]; | ||
705 | - | ||
706 | - /* Function for making any access checks for this register in addition to | ||
707 | - * those specified by the 'access' permissions bits. If NULL, no extra | ||
708 | - * checks required. The access check is performed at runtime, not at | ||
709 | - * translate time. | ||
710 | - */ | ||
711 | - CPAccessFn *accessfn; | ||
712 | - /* Function for handling reads of this register. If NULL, then reads | ||
713 | - * will be done by loading from the offset into CPUARMState specified | ||
714 | - * by fieldoffset. | ||
715 | - */ | ||
716 | - CPReadFn *readfn; | ||
717 | - /* Function for handling writes of this register. If NULL, then writes | ||
718 | - * will be done by writing to the offset into CPUARMState specified | ||
719 | - * by fieldoffset. | ||
720 | - */ | ||
721 | - CPWriteFn *writefn; | ||
722 | - /* Function for doing a "raw" read; used when we need to copy | ||
723 | - * coprocessor state to the kernel for KVM or out for | ||
724 | - * migration. This only needs to be provided if there is also a | ||
725 | - * readfn and it has side effects (for instance clear-on-read bits). | ||
726 | - */ | ||
727 | - CPReadFn *raw_readfn; | ||
728 | - /* Function for doing a "raw" write; used when we need to copy KVM | ||
729 | - * kernel coprocessor state into userspace, or for inbound | ||
730 | - * migration. This only needs to be provided if there is also a | ||
731 | - * writefn and it masks out "unwritable" bits or has write-one-to-clear | ||
732 | - * or similar behaviour. | ||
733 | - */ | ||
734 | - CPWriteFn *raw_writefn; | ||
735 | - /* Function for resetting the register. If NULL, then reset will be done | ||
736 | - * by writing resetvalue to the field specified in fieldoffset. If | ||
737 | - * fieldoffset is 0 then no reset will be done. | ||
738 | - */ | ||
739 | - CPResetFn *resetfn; | ||
740 | - | ||
741 | - /* | ||
742 | - * "Original" writefn and readfn. | ||
743 | - * For ARMv8.1-VHE register aliases, we overwrite the read/write | ||
744 | - * accessor functions of various EL1/EL0 to perform the runtime | ||
745 | - * check for which sysreg should actually be modified, and then | ||
746 | - * forwards the operation. Before overwriting the accessors, | ||
747 | - * the original function is copied here, so that accesses that | ||
748 | - * really do go to the EL1/EL0 version proceed normally. | ||
749 | - * (The corresponding EL2 register is linked via opaque.) | ||
750 | - */ | ||
751 | - CPReadFn *orig_readfn; | ||
752 | - CPWriteFn *orig_writefn; | ||
753 | -}; | ||
754 | - | ||
755 | -/* Macros which are lvalues for the field in CPUARMState for the | ||
756 | - * ARMCPRegInfo *ri. | ||
757 | - */ | ||
758 | -#define CPREG_FIELD32(env, ri) \ | ||
759 | - (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | ||
760 | -#define CPREG_FIELD64(env, ri) \ | ||
761 | - (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | ||
762 | - | ||
763 | -#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | ||
764 | - | ||
765 | -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | ||
766 | - const ARMCPRegInfo *regs, void *opaque); | ||
767 | -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
768 | - const ARMCPRegInfo *regs, void *opaque); | ||
769 | -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
770 | -{ | 212 | -{ |
771 | - define_arm_cp_regs_with_opaque(cpu, regs, 0); | 213 | - uint32_t val; |
214 | - | ||
215 | - switch (reg) { | ||
216 | - case 0: /* Basic Control */ | ||
217 | - return s->phy_control; | ||
218 | - case 1: /* Basic Status */ | ||
219 | - return s->phy_status; | ||
220 | - case 2: /* ID1 */ | ||
221 | - return 0x0007; | ||
222 | - case 3: /* ID2 */ | ||
223 | - return 0xc0d1; | ||
224 | - case 4: /* Auto-neg advertisement */ | ||
225 | - return s->phy_advertise; | ||
226 | - case 5: /* Auto-neg Link Partner Ability */ | ||
227 | - return 0x0f71; | ||
228 | - case 6: /* Auto-neg Expansion */ | ||
229 | - return 1; | ||
230 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
231 | - case 29: /* Interrupt source. */ | ||
232 | - val = s->phy_int; | ||
233 | - s->phy_int = 0; | ||
234 | - phy_update_irq(s); | ||
235 | - return val; | ||
236 | - case 30: /* Interrupt mask */ | ||
237 | - return s->phy_int_mask; | ||
238 | - default: | ||
239 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
240 | - "do_phy_read: PHY read reg %d\n", reg); | ||
241 | - return 0; | ||
242 | - } | ||
772 | -} | 243 | -} |
773 | -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | 244 | - |
245 | -static void do_phy_write(lan9118_state *s, int reg, uint32_t val) | ||
774 | -{ | 246 | -{ |
775 | - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | 247 | - switch (reg) { |
248 | - case 0: /* Basic Control */ | ||
249 | - if (val & 0x8000) { | ||
250 | - phy_reset(s); | ||
251 | - break; | ||
252 | - } | ||
253 | - s->phy_control = val & 0x7980; | ||
254 | - /* Complete autonegotiation immediately. */ | ||
255 | - if (val & 0x1000) { | ||
256 | - s->phy_status |= 0x0020; | ||
257 | - } | ||
258 | - break; | ||
259 | - case 4: /* Auto-neg advertisement */ | ||
260 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
261 | - break; | ||
262 | - /* TODO 17, 18, 27, 31 */ | ||
263 | - case 30: /* Interrupt mask */ | ||
264 | - s->phy_int_mask = val & 0xff; | ||
265 | - phy_update_irq(s); | ||
266 | - break; | ||
267 | - default: | ||
268 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
269 | - "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
270 | - } | ||
776 | -} | 271 | -} |
777 | -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); | 272 | - |
778 | - | 273 | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) |
779 | -/* | 274 | { |
780 | - * Definition of an ARM co-processor register as viewed from | 275 | switch (reg) { |
781 | - * userspace. This is used for presenting sanitised versions of | 276 | @@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val) |
782 | - * registers to userspace when emulating the Linux AArch64 CPU | 277 | if (val & 2) { |
783 | - * ID/feature ABI (advertised as HWCAP_CPUID). | 278 | DPRINTF("PHY write %d = 0x%04x\n", |
784 | - */ | 279 | (val >> 6) & 0x1f, s->mac_mii_data); |
785 | -typedef struct ARMCPRegUserSpaceInfo { | 280 | - do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); |
786 | - /* Name of register */ | 281 | + lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data); |
787 | - const char *name; | 282 | } else { |
788 | - | 283 | - s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); |
789 | - /* Is the name actually a glob pattern */ | 284 | + s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f); |
790 | - bool is_glob; | 285 | DPRINTF("PHY read %d = 0x%04x\n", |
791 | - | 286 | (val >> 6) & 0x1f, s->mac_mii_data); |
792 | - /* Only some bits are exported to user space */ | 287 | } |
793 | - uint64_t exported_bits; | 288 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, |
794 | - | 289 | break; |
795 | - /* Fixed bits are applied after the mask */ | 290 | case CSR_PMT_CTRL: |
796 | - uint64_t fixed_bits; | 291 | if (val & 0x400) { |
797 | -} ARMCPRegUserSpaceInfo; | 292 | - phy_reset(s); |
798 | - | 293 | + lan9118_phy_reset(&s->mii); |
799 | -#define REGUSERINFO_SENTINEL { .name = NULL } | 294 | } |
800 | - | 295 | s->pmt_ctrl &= ~0x34e; |
801 | -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); | 296 | s->pmt_ctrl |= (val & 0x34e); |
802 | - | 297 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) |
803 | -/* CPWriteFn that can be used to implement writes-ignored behaviour */ | 298 | const MemoryRegionOps *mem_ops = |
804 | -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | 299 | s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; |
805 | - uint64_t value); | 300 | |
806 | -/* CPReadFn that can be used for read-as-zero behaviour */ | 301 | + qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0); |
807 | -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); | 302 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); |
808 | - | 303 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { |
809 | -/* CPResetFn that does nothing, for use if no reset is required even | 304 | + return; |
810 | - * if fieldoffset is non zero. | 305 | + } |
811 | - */ | 306 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); |
812 | -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | 307 | + |
813 | - | 308 | memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s, |
814 | -/* Return true if this reginfo struct's field in the cpu state struct | 309 | "lan9118-mmio", 0x100); |
815 | - * is 64 bits wide. | 310 | sysbus_init_mmio(sbd, &s->mmio); |
816 | - */ | 311 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
817 | -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) | 312 | new file mode 100644 |
818 | -{ | 313 | index XXXXXXX..XXXXXXX |
819 | - return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); | 314 | --- /dev/null |
820 | -} | 315 | +++ b/hw/net/lan9118_phy.c |
821 | - | 316 | @@ -XXX,XX +XXX,XX @@ |
822 | -static inline bool cp_access_ok(int current_el, | 317 | +/* |
823 | - const ARMCPRegInfo *ri, int isread) | 318 | + * SMSC LAN9118 PHY emulation |
824 | -{ | 319 | + * |
825 | - return (ri->access >> ((current_el * 2) + isread)) & 1; | 320 | + * Copyright (c) 2009 CodeSourcery, LLC. |
826 | -} | 321 | + * Written by Paul Brook |
827 | - | 322 | + * |
828 | -/* Raw read of a coprocessor register (as needed for migration, etc) */ | 323 | + * This code is licensed under the GNU GPL v2 |
829 | -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); | 324 | + * |
830 | - | 325 | + * Contributions after 2012-01-13 are licensed under the terms of the |
831 | /** | 326 | + * GNU GPL, version 2 or (at your option) any later version. |
832 | * write_list_to_cpustate | 327 | + */ |
833 | * @cpu: ARMCPU | 328 | + |
834 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c | 329 | +#include "qemu/osdep.h" |
330 | +#include "hw/net/lan9118_phy.h" | ||
331 | +#include "hw/irq.h" | ||
332 | +#include "hw/resettable.h" | ||
333 | +#include "migration/vmstate.h" | ||
334 | +#include "qemu/log.h" | ||
335 | + | ||
336 | +#define PHY_INT_ENERGYON (1 << 7) | ||
337 | +#define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
338 | +#define PHY_INT_FAULT (1 << 5) | ||
339 | +#define PHY_INT_DOWN (1 << 4) | ||
340 | +#define PHY_INT_AUTONEG_LP (1 << 3) | ||
341 | +#define PHY_INT_PARFAULT (1 << 2) | ||
342 | +#define PHY_INT_AUTONEG_PAGE (1 << 1) | ||
343 | + | ||
344 | +static void lan9118_phy_update_irq(Lan9118PhyState *s) | ||
345 | +{ | ||
346 | + qemu_set_irq(s->irq, !!(s->ints & s->int_mask)); | ||
347 | +} | ||
348 | + | ||
349 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
350 | +{ | ||
351 | + uint16_t val; | ||
352 | + | ||
353 | + switch (reg) { | ||
354 | + case 0: /* Basic Control */ | ||
355 | + return s->control; | ||
356 | + case 1: /* Basic Status */ | ||
357 | + return s->status; | ||
358 | + case 2: /* ID1 */ | ||
359 | + return 0x0007; | ||
360 | + case 3: /* ID2 */ | ||
361 | + return 0xc0d1; | ||
362 | + case 4: /* Auto-neg advertisement */ | ||
363 | + return s->advertise; | ||
364 | + case 5: /* Auto-neg Link Partner Ability */ | ||
365 | + return 0x0f71; | ||
366 | + case 6: /* Auto-neg Expansion */ | ||
367 | + return 1; | ||
368 | + /* TODO 17, 18, 27, 29, 30, 31 */ | ||
369 | + case 29: /* Interrupt source. */ | ||
370 | + val = s->ints; | ||
371 | + s->ints = 0; | ||
372 | + lan9118_phy_update_irq(s); | ||
373 | + return val; | ||
374 | + case 30: /* Interrupt mask */ | ||
375 | + return s->int_mask; | ||
376 | + default: | ||
377 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
378 | + "lan9118_phy_read: PHY read reg %d\n", reg); | ||
379 | + return 0; | ||
380 | + } | ||
381 | +} | ||
382 | + | ||
383 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
384 | +{ | ||
385 | + switch (reg) { | ||
386 | + case 0: /* Basic Control */ | ||
387 | + if (val & 0x8000) { | ||
388 | + lan9118_phy_reset(s); | ||
389 | + break; | ||
390 | + } | ||
391 | + s->control = val & 0x7980; | ||
392 | + /* Complete autonegotiation immediately. */ | ||
393 | + if (val & 0x1000) { | ||
394 | + s->status |= 0x0020; | ||
395 | + } | ||
396 | + break; | ||
397 | + case 4: /* Auto-neg advertisement */ | ||
398 | + s->advertise = (val & 0x2d7f) | 0x80; | ||
399 | + break; | ||
400 | + /* TODO 17, 18, 27, 31 */ | ||
401 | + case 30: /* Interrupt mask */ | ||
402 | + s->int_mask = val & 0xff; | ||
403 | + lan9118_phy_update_irq(s); | ||
404 | + break; | ||
405 | + default: | ||
406 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
407 | + "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
408 | + } | ||
409 | +} | ||
410 | + | ||
411 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
412 | +{ | ||
413 | + s->link_down = link_down; | ||
414 | + | ||
415 | + /* Autonegotiation status mirrors link status. */ | ||
416 | + if (link_down) { | ||
417 | + s->status &= ~0x0024; | ||
418 | + s->ints |= PHY_INT_DOWN; | ||
419 | + } else { | ||
420 | + s->status |= 0x0024; | ||
421 | + s->ints |= PHY_INT_ENERGYON; | ||
422 | + s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
423 | + } | ||
424 | + lan9118_phy_update_irq(s); | ||
425 | +} | ||
426 | + | ||
427 | +void lan9118_phy_reset(Lan9118PhyState *s) | ||
428 | +{ | ||
429 | + s->control = 0x3000; | ||
430 | + s->status = 0x7809; | ||
431 | + s->advertise = 0x01e1; | ||
432 | + s->int_mask = 0; | ||
433 | + s->ints = 0; | ||
434 | + lan9118_phy_update_link(s, s->link_down); | ||
435 | +} | ||
436 | + | ||
437 | +static void lan9118_phy_reset_hold(Object *obj, ResetType type) | ||
438 | +{ | ||
439 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
440 | + | ||
441 | + lan9118_phy_reset(s); | ||
442 | +} | ||
443 | + | ||
444 | +static void lan9118_phy_init(Object *obj) | ||
445 | +{ | ||
446 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
447 | + | ||
448 | + qdev_init_gpio_out(DEVICE(s), &s->irq, 1); | ||
449 | +} | ||
450 | + | ||
451 | +static const VMStateDescription vmstate_lan9118_phy = { | ||
452 | + .name = "lan9118-phy", | ||
453 | + .version_id = 1, | ||
454 | + .minimum_version_id = 1, | ||
455 | + .fields = (const VMStateField[]) { | ||
456 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
457 | + VMSTATE_UINT16(status, Lan9118PhyState), | ||
458 | + VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
459 | + VMSTATE_UINT16(ints, Lan9118PhyState), | ||
460 | + VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
461 | + VMSTATE_BOOL(link_down, Lan9118PhyState), | ||
462 | + VMSTATE_END_OF_LIST() | ||
463 | + } | ||
464 | +}; | ||
465 | + | ||
466 | +static void lan9118_phy_class_init(ObjectClass *klass, void *data) | ||
467 | +{ | ||
468 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
469 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
470 | + | ||
471 | + rc->phases.hold = lan9118_phy_reset_hold; | ||
472 | + dc->vmsd = &vmstate_lan9118_phy; | ||
473 | +} | ||
474 | + | ||
475 | +static const TypeInfo types[] = { | ||
476 | + { | ||
477 | + .name = TYPE_LAN9118_PHY, | ||
478 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
479 | + .instance_size = sizeof(Lan9118PhyState), | ||
480 | + .instance_init = lan9118_phy_init, | ||
481 | + .class_init = lan9118_phy_class_init, | ||
482 | + } | ||
483 | +}; | ||
484 | + | ||
485 | +DEFINE_TYPES(types) | ||
486 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
835 | index XXXXXXX..XXXXXXX 100644 | 487 | index XXXXXXX..XXXXXXX 100644 |
836 | --- a/hw/arm/pxa2xx.c | 488 | --- a/hw/net/Kconfig |
837 | +++ b/hw/arm/pxa2xx.c | 489 | +++ b/hw/net/Kconfig |
838 | @@ -XXX,XX +XXX,XX @@ | 490 | @@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI |
839 | #include "qemu/cutils.h" | 491 | config SMC91C111 |
840 | #include "qemu/log.h" | 492 | bool |
841 | #include "qom/object.h" | 493 | |
842 | +#include "target/arm/cpregs.h" | 494 | +config LAN9118_PHY |
843 | 495 | + bool | |
844 | static struct { | 496 | + |
845 | hwaddr io_base; | 497 | config LAN9118 |
846 | diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c | 498 | bool |
499 | + select LAN9118_PHY | ||
500 | select PTIMER | ||
501 | |||
502 | config NE2000_ISA | ||
503 | diff --git a/hw/net/meson.build b/hw/net/meson.build | ||
847 | index XXXXXXX..XXXXXXX 100644 | 504 | index XXXXXXX..XXXXXXX 100644 |
848 | --- a/hw/arm/pxa2xx_pic.c | 505 | --- a/hw/net/meson.build |
849 | +++ b/hw/arm/pxa2xx_pic.c | 506 | +++ b/hw/net/meson.build |
850 | @@ -XXX,XX +XXX,XX @@ | 507 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c')) |
851 | #include "hw/sysbus.h" | 508 | |
852 | #include "migration/vmstate.h" | 509 | system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c')) |
853 | #include "qom/object.h" | 510 | system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c')) |
854 | +#include "target/arm/cpregs.h" | 511 | +system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c')) |
855 | 512 | system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) | |
856 | #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ | 513 | system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c')) |
857 | #define ICMR 0x04 /* Interrupt Controller Mask register */ | 514 | system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) |
858 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
859 | index XXXXXXX..XXXXXXX 100644 | ||
860 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
861 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
862 | @@ -XXX,XX +XXX,XX @@ | ||
863 | #include "gicv3_internal.h" | ||
864 | #include "hw/irq.h" | ||
865 | #include "cpu.h" | ||
866 | +#include "target/arm/cpregs.h" | ||
867 | |||
868 | /* | ||
869 | * Special case return value from hppvi_index(); must be larger than | ||
870 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
871 | index XXXXXXX..XXXXXXX 100644 | ||
872 | --- a/hw/intc/arm_gicv3_kvm.c | ||
873 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
874 | @@ -XXX,XX +XXX,XX @@ | ||
875 | #include "vgic_common.h" | ||
876 | #include "migration/blocker.h" | ||
877 | #include "qom/object.h" | ||
878 | +#include "target/arm/cpregs.h" | ||
879 | + | ||
880 | |||
881 | #ifdef DEBUG_GICV3_KVM | ||
882 | #define DPRINTF(fmt, ...) \ | ||
883 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
884 | index XXXXXXX..XXXXXXX 100644 | ||
885 | --- a/target/arm/cpu.c | ||
886 | +++ b/target/arm/cpu.c | ||
887 | @@ -XXX,XX +XXX,XX @@ | ||
888 | #include "kvm_arm.h" | ||
889 | #include "disas/capstone.h" | ||
890 | #include "fpu/softfloat.h" | ||
891 | +#include "cpregs.h" | ||
892 | |||
893 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) | ||
894 | { | ||
895 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
896 | index XXXXXXX..XXXXXXX 100644 | ||
897 | --- a/target/arm/cpu64.c | ||
898 | +++ b/target/arm/cpu64.c | ||
899 | @@ -XXX,XX +XXX,XX @@ | ||
900 | #include "hvf_arm.h" | ||
901 | #include "qapi/visitor.h" | ||
902 | #include "hw/qdev-properties.h" | ||
903 | +#include "cpregs.h" | ||
904 | |||
905 | |||
906 | #ifndef CONFIG_USER_ONLY | ||
907 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
908 | index XXXXXXX..XXXXXXX 100644 | ||
909 | --- a/target/arm/cpu_tcg.c | ||
910 | +++ b/target/arm/cpu_tcg.c | ||
911 | @@ -XXX,XX +XXX,XX @@ | ||
912 | #if !defined(CONFIG_USER_ONLY) | ||
913 | #include "hw/boards.h" | ||
914 | #endif | ||
915 | +#include "cpregs.h" | ||
916 | |||
917 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | ||
918 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | ||
919 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
920 | index XXXXXXX..XXXXXXX 100644 | ||
921 | --- a/target/arm/gdbstub.c | ||
922 | +++ b/target/arm/gdbstub.c | ||
923 | @@ -XXX,XX +XXX,XX @@ | ||
924 | */ | ||
925 | #include "qemu/osdep.h" | ||
926 | #include "cpu.h" | ||
927 | -#include "internals.h" | ||
928 | #include "exec/gdbstub.h" | ||
929 | +#include "internals.h" | ||
930 | +#include "cpregs.h" | ||
931 | |||
932 | typedef struct RegisterSysregXmlParam { | ||
933 | CPUState *cs; | ||
934 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
935 | index XXXXXXX..XXXXXXX 100644 | ||
936 | --- a/target/arm/helper.c | ||
937 | +++ b/target/arm/helper.c | ||
938 | @@ -XXX,XX +XXX,XX @@ | ||
939 | #include "exec/cpu_ldst.h" | ||
940 | #include "semihosting/common-semi.h" | ||
941 | #endif | ||
942 | +#include "cpregs.h" | ||
943 | |||
944 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ | ||
945 | #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ | ||
946 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
947 | index XXXXXXX..XXXXXXX 100644 | ||
948 | --- a/target/arm/op_helper.c | ||
949 | +++ b/target/arm/op_helper.c | ||
950 | @@ -XXX,XX +XXX,XX @@ | ||
951 | #include "internals.h" | ||
952 | #include "exec/exec-all.h" | ||
953 | #include "exec/cpu_ldst.h" | ||
954 | +#include "cpregs.h" | ||
955 | |||
956 | #define SIGNBIT (uint32_t)0x80000000 | ||
957 | #define SIGNBIT64 ((uint64_t)1 << 63) | ||
958 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
959 | index XXXXXXX..XXXXXXX 100644 | ||
960 | --- a/target/arm/translate-a64.c | ||
961 | +++ b/target/arm/translate-a64.c | ||
962 | @@ -XXX,XX +XXX,XX @@ | ||
963 | #include "translate.h" | ||
964 | #include "internals.h" | ||
965 | #include "qemu/host-utils.h" | ||
966 | - | ||
967 | #include "semihosting/semihost.h" | ||
968 | #include "exec/gen-icount.h" | ||
969 | - | ||
970 | #include "exec/helper-proto.h" | ||
971 | #include "exec/helper-gen.h" | ||
972 | #include "exec/log.h" | ||
973 | - | ||
974 | +#include "cpregs.h" | ||
975 | #include "translate-a64.h" | ||
976 | #include "qemu/atomic128.h" | ||
977 | |||
978 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
979 | index XXXXXXX..XXXXXXX 100644 | ||
980 | --- a/target/arm/translate.c | ||
981 | +++ b/target/arm/translate.c | ||
982 | @@ -XXX,XX +XXX,XX @@ | ||
983 | #include "qemu/bitops.h" | ||
984 | #include "arm_ldst.h" | ||
985 | #include "semihosting/semihost.h" | ||
986 | - | ||
987 | #include "exec/helper-proto.h" | ||
988 | #include "exec/helper-gen.h" | ||
989 | - | ||
990 | #include "exec/log.h" | ||
991 | +#include "cpregs.h" | ||
992 | |||
993 | |||
994 | #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) | ||
995 | -- | 515 | -- |
996 | 2.25.1 | 516 | 2.34.1 |
997 | |||
998 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bernhard Beschow <shentey@gmail.com> | ||
1 | 2 | ||
3 | imx_fec models the same PHY as lan9118_phy. The code is almost the same with | ||
4 | imx_fec having more logging and tracing. Merge these improvements into | ||
5 | lan9118_phy and reuse in imx_fec to fix the code duplication. | ||
6 | |||
7 | Some migration state how resides in the new device model which breaks migration | ||
8 | compatibility for the following machines: | ||
9 | * imx25-pdk | ||
10 | * sabrelite | ||
11 | * mcimx7d-sabre | ||
12 | * mcimx6ul-evk | ||
13 | |||
14 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
15 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Message-id: 20241102125724.532843-3-shentey@gmail.com | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | include/hw/net/imx_fec.h | 9 ++- | ||
21 | hw/net/imx_fec.c | 146 ++++----------------------------------- | ||
22 | hw/net/lan9118_phy.c | 82 ++++++++++++++++------ | ||
23 | hw/net/Kconfig | 1 + | ||
24 | hw/net/trace-events | 10 +-- | ||
25 | 5 files changed, 85 insertions(+), 163 deletions(-) | ||
26 | |||
27 | diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/include/hw/net/imx_fec.h | ||
30 | +++ b/include/hw/net/imx_fec.h | ||
31 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC) | ||
32 | #define TYPE_IMX_ENET "imx.enet" | ||
33 | |||
34 | #include "hw/sysbus.h" | ||
35 | +#include "hw/net/lan9118_phy.h" | ||
36 | +#include "hw/irq.h" | ||
37 | #include "net/net.h" | ||
38 | |||
39 | #define ENET_EIR 1 | ||
40 | @@ -XXX,XX +XXX,XX @@ struct IMXFECState { | ||
41 | uint32_t tx_descriptor[ENET_TX_RING_NUM]; | ||
42 | uint32_t tx_ring_num; | ||
43 | |||
44 | - uint32_t phy_status; | ||
45 | - uint32_t phy_control; | ||
46 | - uint32_t phy_advertise; | ||
47 | - uint32_t phy_int; | ||
48 | - uint32_t phy_int_mask; | ||
49 | + Lan9118PhyState mii; | ||
50 | + IRQState mii_irq; | ||
51 | uint32_t phy_num; | ||
52 | bool phy_connected; | ||
53 | struct IMXFECState *phy_consumer; | ||
54 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/net/imx_fec.c | ||
57 | +++ b/hw/net/imx_fec.c | ||
58 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = { | ||
59 | |||
60 | static const VMStateDescription vmstate_imx_eth = { | ||
61 | .name = TYPE_IMX_FEC, | ||
62 | - .version_id = 2, | ||
63 | - .minimum_version_id = 2, | ||
64 | + .version_id = 3, | ||
65 | + .minimum_version_id = 3, | ||
66 | .fields = (const VMStateField[]) { | ||
67 | VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), | ||
68 | VMSTATE_UINT32(rx_descriptor, IMXFECState), | ||
69 | VMSTATE_UINT32(tx_descriptor[0], IMXFECState), | ||
70 | - VMSTATE_UINT32(phy_status, IMXFECState), | ||
71 | - VMSTATE_UINT32(phy_control, IMXFECState), | ||
72 | - VMSTATE_UINT32(phy_advertise, IMXFECState), | ||
73 | - VMSTATE_UINT32(phy_int, IMXFECState), | ||
74 | - VMSTATE_UINT32(phy_int_mask, IMXFECState), | ||
75 | VMSTATE_END_OF_LIST() | ||
76 | }, | ||
77 | .subsections = (const VMStateDescription * const []) { | ||
78 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = { | ||
79 | }, | ||
80 | }; | ||
81 | |||
82 | -#define PHY_INT_ENERGYON (1 << 7) | ||
83 | -#define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
84 | -#define PHY_INT_FAULT (1 << 5) | ||
85 | -#define PHY_INT_DOWN (1 << 4) | ||
86 | -#define PHY_INT_AUTONEG_LP (1 << 3) | ||
87 | -#define PHY_INT_PARFAULT (1 << 2) | ||
88 | -#define PHY_INT_AUTONEG_PAGE (1 << 1) | ||
89 | - | ||
90 | static void imx_eth_update(IMXFECState *s); | ||
91 | |||
92 | /* | ||
93 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s); | ||
94 | * For now we don't handle any GPIO/interrupt line, so the OS will | ||
95 | * have to poll for the PHY status. | ||
96 | */ | ||
97 | -static void imx_phy_update_irq(IMXFECState *s) | ||
98 | +static void imx_phy_update_irq(void *opaque, int n, int level) | ||
99 | { | ||
100 | - imx_eth_update(s); | ||
101 | -} | ||
102 | - | ||
103 | -static void imx_phy_update_link(IMXFECState *s) | ||
104 | -{ | ||
105 | - /* Autonegotiation status mirrors link status. */ | ||
106 | - if (qemu_get_queue(s->nic)->link_down) { | ||
107 | - trace_imx_phy_update_link("down"); | ||
108 | - s->phy_status &= ~0x0024; | ||
109 | - s->phy_int |= PHY_INT_DOWN; | ||
110 | - } else { | ||
111 | - trace_imx_phy_update_link("up"); | ||
112 | - s->phy_status |= 0x0024; | ||
113 | - s->phy_int |= PHY_INT_ENERGYON; | ||
114 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
115 | - } | ||
116 | - imx_phy_update_irq(s); | ||
117 | + imx_eth_update(opaque); | ||
118 | } | ||
119 | |||
120 | static void imx_eth_set_link(NetClientState *nc) | ||
121 | { | ||
122 | - imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); | ||
123 | -} | ||
124 | - | ||
125 | -static void imx_phy_reset(IMXFECState *s) | ||
126 | -{ | ||
127 | - trace_imx_phy_reset(); | ||
128 | - | ||
129 | - s->phy_status = 0x7809; | ||
130 | - s->phy_control = 0x3000; | ||
131 | - s->phy_advertise = 0x01e1; | ||
132 | - s->phy_int_mask = 0; | ||
133 | - s->phy_int = 0; | ||
134 | - imx_phy_update_link(s); | ||
135 | + lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii, | ||
136 | + nc->link_down); | ||
137 | } | ||
138 | |||
139 | static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
140 | { | ||
141 | - uint32_t val; | ||
142 | uint32_t phy = reg / 32; | ||
143 | |||
144 | if (!s->phy_connected) { | ||
145 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
146 | |||
147 | reg %= 32; | ||
148 | |||
149 | - switch (reg) { | ||
150 | - case 0: /* Basic Control */ | ||
151 | - val = s->phy_control; | ||
152 | - break; | ||
153 | - case 1: /* Basic Status */ | ||
154 | - val = s->phy_status; | ||
155 | - break; | ||
156 | - case 2: /* ID1 */ | ||
157 | - val = 0x0007; | ||
158 | - break; | ||
159 | - case 3: /* ID2 */ | ||
160 | - val = 0xc0d1; | ||
161 | - break; | ||
162 | - case 4: /* Auto-neg advertisement */ | ||
163 | - val = s->phy_advertise; | ||
164 | - break; | ||
165 | - case 5: /* Auto-neg Link Partner Ability */ | ||
166 | - val = 0x0f71; | ||
167 | - break; | ||
168 | - case 6: /* Auto-neg Expansion */ | ||
169 | - val = 1; | ||
170 | - break; | ||
171 | - case 29: /* Interrupt source. */ | ||
172 | - val = s->phy_int; | ||
173 | - s->phy_int = 0; | ||
174 | - imx_phy_update_irq(s); | ||
175 | - break; | ||
176 | - case 30: /* Interrupt mask */ | ||
177 | - val = s->phy_int_mask; | ||
178 | - break; | ||
179 | - case 17: | ||
180 | - case 18: | ||
181 | - case 27: | ||
182 | - case 31: | ||
183 | - qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", | ||
184 | - TYPE_IMX_FEC, __func__, reg); | ||
185 | - val = 0; | ||
186 | - break; | ||
187 | - default: | ||
188 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
189 | - TYPE_IMX_FEC, __func__, reg); | ||
190 | - val = 0; | ||
191 | - break; | ||
192 | - } | ||
193 | - | ||
194 | - trace_imx_phy_read(val, phy, reg); | ||
195 | - | ||
196 | - return val; | ||
197 | + return lan9118_phy_read(&s->mii, reg); | ||
198 | } | ||
199 | |||
200 | static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
201 | @@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
202 | |||
203 | reg %= 32; | ||
204 | |||
205 | - trace_imx_phy_write(val, phy, reg); | ||
206 | - | ||
207 | - switch (reg) { | ||
208 | - case 0: /* Basic Control */ | ||
209 | - if (val & 0x8000) { | ||
210 | - imx_phy_reset(s); | ||
211 | - } else { | ||
212 | - s->phy_control = val & 0x7980; | ||
213 | - /* Complete autonegotiation immediately. */ | ||
214 | - if (val & 0x1000) { | ||
215 | - s->phy_status |= 0x0020; | ||
216 | - } | ||
217 | - } | ||
218 | - break; | ||
219 | - case 4: /* Auto-neg advertisement */ | ||
220 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
221 | - break; | ||
222 | - case 30: /* Interrupt mask */ | ||
223 | - s->phy_int_mask = val & 0xff; | ||
224 | - imx_phy_update_irq(s); | ||
225 | - break; | ||
226 | - case 17: | ||
227 | - case 18: | ||
228 | - case 27: | ||
229 | - case 31: | ||
230 | - qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", | ||
231 | - TYPE_IMX_FEC, __func__, reg); | ||
232 | - break; | ||
233 | - default: | ||
234 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
235 | - TYPE_IMX_FEC, __func__, reg); | ||
236 | - break; | ||
237 | - } | ||
238 | + lan9118_phy_write(&s->mii, reg, val); | ||
239 | } | ||
240 | |||
241 | static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) | ||
242 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d) | ||
243 | |||
244 | s->rx_descriptor = 0; | ||
245 | memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); | ||
246 | - | ||
247 | - /* We also reset the PHY */ | ||
248 | - imx_phy_reset(s); | ||
249 | } | ||
250 | |||
251 | static uint32_t imx_default_read(IMXFECState *s, uint32_t index) | ||
252 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp) | ||
253 | sysbus_init_irq(sbd, &s->irq[0]); | ||
254 | sysbus_init_irq(sbd, &s->irq[1]); | ||
255 | |||
256 | + qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0); | ||
257 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
258 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
259 | + return; | ||
260 | + } | ||
261 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); | ||
262 | + | ||
263 | qemu_macaddr_default_if_unset(&s->conf.macaddr); | ||
264 | |||
265 | s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, | ||
266 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
267 | index XXXXXXX..XXXXXXX 100644 | ||
268 | --- a/hw/net/lan9118_phy.c | ||
269 | +++ b/hw/net/lan9118_phy.c | ||
270 | @@ -XXX,XX +XXX,XX @@ | ||
271 | * Copyright (c) 2009 CodeSourcery, LLC. | ||
272 | * Written by Paul Brook | ||
273 | * | ||
274 | + * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> | ||
275 | + * | ||
276 | * This code is licensed under the GNU GPL v2 | ||
277 | * | ||
278 | * Contributions after 2012-01-13 are licensed under the terms of the | ||
279 | @@ -XXX,XX +XXX,XX @@ | ||
280 | #include "hw/resettable.h" | ||
281 | #include "migration/vmstate.h" | ||
282 | #include "qemu/log.h" | ||
283 | +#include "trace.h" | ||
284 | |||
285 | #define PHY_INT_ENERGYON (1 << 7) | ||
286 | #define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
287 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
288 | |||
289 | switch (reg) { | ||
290 | case 0: /* Basic Control */ | ||
291 | - return s->control; | ||
292 | + val = s->control; | ||
293 | + break; | ||
294 | case 1: /* Basic Status */ | ||
295 | - return s->status; | ||
296 | + val = s->status; | ||
297 | + break; | ||
298 | case 2: /* ID1 */ | ||
299 | - return 0x0007; | ||
300 | + val = 0x0007; | ||
301 | + break; | ||
302 | case 3: /* ID2 */ | ||
303 | - return 0xc0d1; | ||
304 | + val = 0xc0d1; | ||
305 | + break; | ||
306 | case 4: /* Auto-neg advertisement */ | ||
307 | - return s->advertise; | ||
308 | + val = s->advertise; | ||
309 | + break; | ||
310 | case 5: /* Auto-neg Link Partner Ability */ | ||
311 | - return 0x0f71; | ||
312 | + val = 0x0f71; | ||
313 | + break; | ||
314 | case 6: /* Auto-neg Expansion */ | ||
315 | - return 1; | ||
316 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
317 | + val = 1; | ||
318 | + break; | ||
319 | case 29: /* Interrupt source. */ | ||
320 | val = s->ints; | ||
321 | s->ints = 0; | ||
322 | lan9118_phy_update_irq(s); | ||
323 | - return val; | ||
324 | + break; | ||
325 | case 30: /* Interrupt mask */ | ||
326 | - return s->int_mask; | ||
327 | + val = s->int_mask; | ||
328 | + break; | ||
329 | + case 17: | ||
330 | + case 18: | ||
331 | + case 27: | ||
332 | + case 31: | ||
333 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
334 | + __func__, reg); | ||
335 | + val = 0; | ||
336 | + break; | ||
337 | default: | ||
338 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
339 | - "lan9118_phy_read: PHY read reg %d\n", reg); | ||
340 | - return 0; | ||
341 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
342 | + __func__, reg); | ||
343 | + val = 0; | ||
344 | + break; | ||
345 | } | ||
346 | + | ||
347 | + trace_lan9118_phy_read(val, reg); | ||
348 | + | ||
349 | + return val; | ||
350 | } | ||
351 | |||
352 | void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
353 | { | ||
354 | + trace_lan9118_phy_write(val, reg); | ||
355 | + | ||
356 | switch (reg) { | ||
357 | case 0: /* Basic Control */ | ||
358 | if (val & 0x8000) { | ||
359 | lan9118_phy_reset(s); | ||
360 | - break; | ||
361 | - } | ||
362 | - s->control = val & 0x7980; | ||
363 | - /* Complete autonegotiation immediately. */ | ||
364 | - if (val & 0x1000) { | ||
365 | - s->status |= 0x0020; | ||
366 | + } else { | ||
367 | + s->control = val & 0x7980; | ||
368 | + /* Complete autonegotiation immediately. */ | ||
369 | + if (val & 0x1000) { | ||
370 | + s->status |= 0x0020; | ||
371 | + } | ||
372 | } | ||
373 | break; | ||
374 | case 4: /* Auto-neg advertisement */ | ||
375 | s->advertise = (val & 0x2d7f) | 0x80; | ||
376 | break; | ||
377 | - /* TODO 17, 18, 27, 31 */ | ||
378 | case 30: /* Interrupt mask */ | ||
379 | s->int_mask = val & 0xff; | ||
380 | lan9118_phy_update_irq(s); | ||
381 | break; | ||
382 | + case 17: | ||
383 | + case 18: | ||
384 | + case 27: | ||
385 | + case 31: | ||
386 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
387 | + __func__, reg); | ||
388 | + break; | ||
389 | default: | ||
390 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
391 | - "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
392 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
393 | + __func__, reg); | ||
394 | + break; | ||
395 | } | ||
396 | } | ||
397 | |||
398 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
399 | |||
400 | /* Autonegotiation status mirrors link status. */ | ||
401 | if (link_down) { | ||
402 | + trace_lan9118_phy_update_link("down"); | ||
403 | s->status &= ~0x0024; | ||
404 | s->ints |= PHY_INT_DOWN; | ||
405 | } else { | ||
406 | + trace_lan9118_phy_update_link("up"); | ||
407 | s->status |= 0x0024; | ||
408 | s->ints |= PHY_INT_ENERGYON; | ||
409 | s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
410 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
411 | |||
412 | void lan9118_phy_reset(Lan9118PhyState *s) | ||
413 | { | ||
414 | + trace_lan9118_phy_reset(); | ||
415 | + | ||
416 | s->control = 0x3000; | ||
417 | s->status = 0x7809; | ||
418 | s->advertise = 0x01e1; | ||
419 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = { | ||
420 | .version_id = 1, | ||
421 | .minimum_version_id = 1, | ||
422 | .fields = (const VMStateField[]) { | ||
423 | - VMSTATE_UINT16(control, Lan9118PhyState), | ||
424 | VMSTATE_UINT16(status, Lan9118PhyState), | ||
425 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
426 | VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
427 | VMSTATE_UINT16(ints, Lan9118PhyState), | ||
428 | VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
429 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
430 | index XXXXXXX..XXXXXXX 100644 | ||
431 | --- a/hw/net/Kconfig | ||
432 | +++ b/hw/net/Kconfig | ||
433 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC | ||
434 | |||
435 | config IMX_FEC | ||
436 | bool | ||
437 | + select LAN9118_PHY | ||
438 | |||
439 | config CADENCE | ||
440 | bool | ||
441 | diff --git a/hw/net/trace-events b/hw/net/trace-events | ||
442 | index XXXXXXX..XXXXXXX 100644 | ||
443 | --- a/hw/net/trace-events | ||
444 | +++ b/hw/net/trace-events | ||
445 | @@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" | ||
446 | allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 | ||
447 | allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 | ||
448 | |||
449 | +# lan9118_phy.c | ||
450 | +lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16 | ||
451 | +lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16 | ||
452 | +lan9118_phy_update_link(const char *s) "%s" | ||
453 | +lan9118_phy_reset(void) "" | ||
454 | + | ||
455 | # lance.c | ||
456 | lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" | ||
457 | lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" | ||
458 | @@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" | ||
459 | i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" | ||
460 | |||
461 | # imx_fec.c | ||
462 | -imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" | ||
463 | imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" | ||
464 | -imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" | ||
465 | imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" | ||
466 | -imx_phy_update_link(const char *s) "%s" | ||
467 | -imx_phy_reset(void) "" | ||
468 | imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" | ||
469 | imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" | ||
470 | imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" | ||
471 | -- | ||
472 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bernhard Beschow <shentey@gmail.com> | ||
1 | 2 | ||
3 | Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and | ||
4 | fixes the MSB of selector field to be zero, as specified in the datasheet. | ||
5 | |||
6 | Fixes: 2a424990170b "LAN9118 emulation" | ||
7 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
8 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20241102125724.532843-4-shentey@gmail.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/net/lan9118_phy.c | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/net/lan9118_phy.c | ||
19 | +++ b/hw/net/lan9118_phy.c | ||
20 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
21 | val = s->advertise; | ||
22 | break; | ||
23 | case 5: /* Auto-neg Link Partner Ability */ | ||
24 | - val = 0x0f71; | ||
25 | + val = 0x0fe1; | ||
26 | break; | ||
27 | case 6: /* Auto-neg Expansion */ | ||
28 | val = 1; | ||
29 | -- | ||
30 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Standardize on g_assert_not_reached() for "should not happen". | 3 | Prefer named constants over magic values for better readability. |
4 | Retain abort() when preceeded by fprintf or error_report. | ||
5 | 4 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20220501055028.646596-7-richard.henderson@linaro.org | 6 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
7 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
8 | Message-id: 20241102125724.532843-5-shentey@gmail.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/helper.c | 7 +++---- | 11 | include/hw/net/mii.h | 6 +++++ |
12 | target/arm/hvf/hvf.c | 2 +- | 12 | hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++---------------- |
13 | target/arm/kvm-stub.c | 4 ++-- | 13 | 2 files changed, 46 insertions(+), 23 deletions(-) |
14 | target/arm/kvm.c | 4 ++-- | ||
15 | target/arm/machine.c | 4 ++-- | ||
16 | target/arm/translate-a64.c | 4 ++-- | ||
17 | target/arm/translate-neon.c | 2 +- | ||
18 | target/arm/translate.c | 4 ++-- | ||
19 | 8 files changed, 15 insertions(+), 16 deletions(-) | ||
20 | 14 | ||
21 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h |
22 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/helper.c | 17 | --- a/include/hw/net/mii.h |
24 | +++ b/target/arm/helper.c | 18 | +++ b/include/hw/net/mii.h |
25 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | 19 | @@ -XXX,XX +XXX,XX @@ |
26 | break; | 20 | #define MII_BMSR_JABBER (1 << 1) /* Jabber detected */ |
27 | default: | 21 | #define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */ |
28 | /* broken reginfo with out-of-range opc1 */ | 22 | |
29 | - assert(false); | 23 | +#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */ |
30 | - break; | 24 | #define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */ |
31 | + g_assert_not_reached(); | 25 | #define MII_ANAR_PAUSE (1 << 10) /* Try for pause */ |
32 | } | 26 | #define MII_ANAR_TXFD (1 << 8) |
33 | /* assert our permissions are not too lax (stricter is fine) */ | 27 | @@ -XXX,XX +XXX,XX @@ |
34 | assert((r->access & ~mask) == 0); | 28 | #define MII_ANAR_10FD (1 << 6) |
35 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, | 29 | #define MII_ANAR_10 (1 << 5) |
36 | break; | 30 | #define MII_ANAR_CSMACD (1 << 0) |
37 | default: | 31 | +#define MII_ANAR_SELECT (0x001f) /* Selector bits */ |
38 | /* Never happens, but compiler isn't smart enough to tell. */ | 32 | |
39 | - abort(); | 33 | #define MII_ANLPAR_ACK (1 << 14) |
40 | + g_assert_not_reached(); | 34 | #define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */ |
41 | } | 35 | @@ -XXX,XX +XXX,XX @@ |
42 | } | 36 | #define RTL8201CP_PHYID1 0x0000 |
43 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | 37 | #define RTL8201CP_PHYID2 0x8201 |
44 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, | 38 | |
45 | break; | 39 | +/* SMSC LAN9118 */ |
46 | default: | 40 | +#define SMSCLAN9118_PHYID1 0x0007 |
47 | /* Never happens, but compiler isn't smart enough to tell. */ | 41 | +#define SMSCLAN9118_PHYID2 0xc0d1 |
48 | - abort(); | 42 | + |
49 | + g_assert_not_reached(); | 43 | /* RealTek 8211E */ |
50 | } | 44 | #define RTL8211E_PHYID1 0x001c |
51 | } | 45 | #define RTL8211E_PHYID2 0xc915 |
52 | if (domain_prot == 3) { | 46 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
53 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | 47 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/target/arm/hvf/hvf.c | 48 | --- a/hw/net/lan9118_phy.c |
56 | +++ b/target/arm/hvf/hvf.c | 49 | +++ b/hw/net/lan9118_phy.c |
57 | @@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu) | ||
58 | /* we got kicked, no exit to process */ | ||
59 | return 0; | ||
60 | default: | ||
61 | - assert(0); | ||
62 | + g_assert_not_reached(); | ||
63 | } | ||
64 | |||
65 | hvf_sync_vtimer(cpu); | ||
66 | diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/kvm-stub.c | ||
69 | +++ b/target/arm/kvm-stub.c | ||
70 | @@ -XXX,XX +XXX,XX @@ | 50 | @@ -XXX,XX +XXX,XX @@ |
71 | 51 | ||
72 | bool write_kvmstate_to_list(ARMCPU *cpu) | 52 | #include "qemu/osdep.h" |
73 | { | 53 | #include "hw/net/lan9118_phy.h" |
74 | - abort(); | 54 | +#include "hw/net/mii.h" |
75 | + g_assert_not_reached(); | 55 | #include "hw/irq.h" |
76 | } | 56 | #include "hw/resettable.h" |
77 | 57 | #include "migration/vmstate.h" | |
78 | bool write_list_to_kvmstate(ARMCPU *cpu, int level) | 58 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) |
79 | { | 59 | uint16_t val; |
80 | - abort(); | 60 | |
81 | + g_assert_not_reached(); | 61 | switch (reg) { |
82 | } | 62 | - case 0: /* Basic Control */ |
83 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | 63 | + case MII_BMCR: |
84 | index XXXXXXX..XXXXXXX 100644 | 64 | val = s->control; |
85 | --- a/target/arm/kvm.c | ||
86 | +++ b/target/arm/kvm.c | ||
87 | @@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu) | ||
88 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | ||
89 | break; | ||
90 | default: | ||
91 | - abort(); | ||
92 | + g_assert_not_reached(); | ||
93 | } | ||
94 | if (ret) { | ||
95 | ok = false; | ||
96 | @@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) | ||
97 | r.addr = (uintptr_t)(cpu->cpreg_values + i); | ||
98 | break; | ||
99 | default: | ||
100 | - abort(); | ||
101 | + g_assert_not_reached(); | ||
102 | } | ||
103 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); | ||
104 | if (ret) { | ||
105 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/machine.c | ||
108 | +++ b/target/arm/machine.c | ||
109 | @@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque) | ||
110 | if (kvm_enabled()) { | ||
111 | if (!write_kvmstate_to_list(cpu)) { | ||
112 | /* This should never fail */ | ||
113 | - abort(); | ||
114 | + g_assert_not_reached(); | ||
115 | } | ||
116 | |||
117 | /* | ||
118 | @@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque) | ||
119 | } else { | ||
120 | if (!write_cpustate_to_list(cpu, false)) { | ||
121 | /* This should never fail. */ | ||
122 | - abort(); | ||
123 | + g_assert_not_reached(); | ||
124 | } | ||
125 | } | ||
126 | |||
127 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
128 | index XXXXXXX..XXXXXXX 100644 | ||
129 | --- a/target/arm/translate-a64.c | ||
130 | +++ b/target/arm/translate-a64.c | ||
131 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | ||
132 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | ||
133 | break; | 65 | break; |
134 | default: | 66 | - case 1: /* Basic Status */ |
135 | - abort(); | 67 | + case MII_BMSR: |
136 | + g_assert_not_reached(); | 68 | val = s->status; |
137 | } | ||
138 | |||
139 | write_fp_sreg(s, rd, tcg_res); | ||
140 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode, | ||
141 | break; | 69 | break; |
142 | } | 70 | - case 2: /* ID1 */ |
143 | default: | 71 | - val = 0x0007; |
144 | - abort(); | 72 | + case MII_PHYID1: |
145 | + g_assert_not_reached(); | 73 | + val = SMSCLAN9118_PHYID1; |
146 | } | 74 | break; |
147 | } | 75 | - case 3: /* ID2 */ |
148 | 76 | - val = 0xc0d1; | |
149 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | 77 | + case MII_PHYID2: |
150 | index XXXXXXX..XXXXXXX 100644 | 78 | + val = SMSCLAN9118_PHYID2; |
151 | --- a/target/arm/translate-neon.c | 79 | break; |
152 | +++ b/target/arm/translate-neon.c | 80 | - case 4: /* Auto-neg advertisement */ |
153 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) | 81 | + case MII_ANAR: |
82 | val = s->advertise; | ||
83 | break; | ||
84 | - case 5: /* Auto-neg Link Partner Ability */ | ||
85 | - val = 0x0fe1; | ||
86 | + case MII_ANLPAR: | ||
87 | + val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 | | ||
88 | + MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | | ||
89 | + MII_ANLPAR_10 | MII_ANLPAR_CSMACD; | ||
90 | break; | ||
91 | - case 6: /* Auto-neg Expansion */ | ||
92 | - val = 1; | ||
93 | + case MII_ANER: | ||
94 | + val = MII_ANER_NWAY; | ||
95 | break; | ||
96 | case 29: /* Interrupt source. */ | ||
97 | val = s->ints; | ||
98 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
99 | trace_lan9118_phy_write(val, reg); | ||
100 | |||
101 | switch (reg) { | ||
102 | - case 0: /* Basic Control */ | ||
103 | - if (val & 0x8000) { | ||
104 | + case MII_BMCR: | ||
105 | + if (val & MII_BMCR_RESET) { | ||
106 | lan9118_phy_reset(s); | ||
107 | } else { | ||
108 | - s->control = val & 0x7980; | ||
109 | + s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | | ||
110 | + MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD | | ||
111 | + MII_BMCR_CTST); | ||
112 | /* Complete autonegotiation immediately. */ | ||
113 | - if (val & 0x1000) { | ||
114 | - s->status |= 0x0020; | ||
115 | + if (val & MII_BMCR_AUTOEN) { | ||
116 | + s->status |= MII_BMSR_AN_COMP; | ||
117 | } | ||
154 | } | 118 | } |
155 | break; | 119 | break; |
156 | default: | 120 | - case 4: /* Auto-neg advertisement */ |
157 | - abort(); | 121 | - s->advertise = (val & 0x2d7f) | 0x80; |
158 | + g_assert_not_reached(); | 122 | + case MII_ANAR: |
123 | + s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | | ||
124 | + MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | | ||
125 | + MII_ANAR_SELECT)) | ||
126 | + | MII_ANAR_TX; | ||
127 | break; | ||
128 | case 30: /* Interrupt mask */ | ||
129 | s->int_mask = val & 0xff; | ||
130 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
131 | /* Autonegotiation status mirrors link status. */ | ||
132 | if (link_down) { | ||
133 | trace_lan9118_phy_update_link("down"); | ||
134 | - s->status &= ~0x0024; | ||
135 | + s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST); | ||
136 | s->ints |= PHY_INT_DOWN; | ||
137 | } else { | ||
138 | trace_lan9118_phy_update_link("up"); | ||
139 | - s->status |= 0x0024; | ||
140 | + s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST; | ||
141 | s->ints |= PHY_INT_ENERGYON; | ||
142 | s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
159 | } | 143 | } |
160 | if ((vd + a->stride * (nregs - 1)) > 31) { | 144 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s) |
161 | /* | 145 | { |
162 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 146 | trace_lan9118_phy_reset(); |
163 | index XXXXXXX..XXXXXXX 100644 | 147 | |
164 | --- a/target/arm/translate.c | 148 | - s->control = 0x3000; |
165 | +++ b/target/arm/translate.c | 149 | - s->status = 0x7809; |
166 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | 150 | - s->advertise = 0x01e1; |
167 | offset = 4; | 151 | + s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100; |
168 | break; | 152 | + s->status = MII_BMSR_100TX_FD |
169 | default: | 153 | + | MII_BMSR_100TX_HD |
170 | - abort(); | 154 | + | MII_BMSR_10T_FD |
171 | + g_assert_not_reached(); | 155 | + | MII_BMSR_10T_HD |
172 | } | 156 | + | MII_BMSR_AUTONEG |
173 | tcg_gen_addi_i32(addr, addr, offset); | 157 | + | MII_BMSR_EXTCAP; |
174 | tmp = load_reg(s, 14); | 158 | + s->advertise = MII_ANAR_TXFD |
175 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | 159 | + | MII_ANAR_TX |
176 | offset = 0; | 160 | + | MII_ANAR_10FD |
177 | break; | 161 | + | MII_ANAR_10 |
178 | default: | 162 | + | MII_ANAR_CSMACD; |
179 | - abort(); | 163 | s->int_mask = 0; |
180 | + g_assert_not_reached(); | 164 | s->ints = 0; |
181 | } | 165 | lan9118_phy_update_link(s, s->link_down); |
182 | tcg_gen_addi_i32(addr, addr, offset); | ||
183 | gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); | ||
184 | -- | 166 | -- |
185 | 2.25.1 | 167 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Alex Zuepke <alex.zuepke@tum.de> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access | 3 | The real device advertises this mode and the device model already advertises |
4 | to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however, | 4 | 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to |
5 | we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well. | 5 | make the model more realistic. |
6 | 6 | ||
7 | Signed-off-by: Alex Zuepke <alex.zuepke@tum.de> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
9 | Message-id: 20220428132717.84190-1-alex.zuepke@tum.de | 9 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
10 | Message-id: 20241102125724.532843-6-shentey@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | target/arm/helper.c | 4 ++-- | 13 | hw/net/lan9118_phy.c | 4 ++-- |
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 14 | 1 file changed, 2 insertions(+), 2 deletions(-) |
14 | 15 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 18 | --- a/hw/net/lan9118_phy.c |
18 | +++ b/target/arm/helper.c | 19 | +++ b/hw/net/lan9118_phy.c |
19 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | 20 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) |
20 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | 21 | break; |
21 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | 22 | case MII_ANAR: |
22 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | 23 | s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | |
23 | - .accessfn = pmreg_access }, | 24 | - MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | |
24 | + .accessfn = pmreg_access_xevcntr }, | 25 | - MII_ANAR_SELECT)) |
25 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, | 26 | + MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD | |
26 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | 27 | + MII_ANAR_10 | MII_ANAR_SELECT)) |
27 | - .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | 28 | | MII_ANAR_TX; |
28 | + .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, | 29 | break; |
29 | .type = ARM_CP_IO, | 30 | case 30: /* Interrupt mask */ |
30 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | ||
31 | .raw_readfn = pmevcntr_rawread, | ||
32 | -- | 31 | -- |
33 | 2.25.1 | 32 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | For IEEE fused multiply-add, the (0 * inf) + NaN case should raise | ||
2 | Invalid for the multiplication of 0 by infinity. Currently we handle | ||
3 | this in the per-architecture ifdef ladder in pickNaNMulAdd(). | ||
4 | However, since this isn't really architecture specific we can hoist | ||
5 | it up to the generic code. | ||
1 | 6 | ||
7 | For the cases where the infzero test in pickNaNMulAdd was | ||
8 | returning 2, we can delete the check entirely and allow the | ||
9 | code to fall into the normal pick-a-NaN handling, because this | ||
10 | will return 2 anyway (input 'c' being the only NaN in this case). | ||
11 | For the cases where infzero was returning 3 to indicate "return | ||
12 | the default NaN", we must retain that "return 3". | ||
13 | |||
14 | For Arm, this looks like it might be a behaviour change because we | ||
15 | used to set float_flag_invalid | float_flag_invalid_imz only if C is | ||
16 | a quiet NaN. However, it is not, because Arm target code never looks | ||
17 | at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we | ||
18 | already raised float_flag_invalid via the "abc_mask & | ||
19 | float_cmask_snan" check in pick_nan_muladd. | ||
20 | |||
21 | For any target architecture using the "default implementation" at the | ||
22 | bottom of the ifdef, this is a behaviour change but will be fixing a | ||
23 | bug (where we failed to raise the Invalid exception for (0 * inf + | ||
24 | QNaN). The architectures using the default case are: | ||
25 | * hppa | ||
26 | * i386 | ||
27 | * sh4 | ||
28 | * tricore | ||
29 | |||
30 | The x86, Tricore and SH4 CPU architecture manuals are clear that this | ||
31 | should have raised Invalid; HPPA is a bit vaguer but still seems | ||
32 | clear enough. | ||
33 | |||
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
35 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
36 | Message-id: 20241202131347.498124-2-peter.maydell@linaro.org | ||
37 | --- | ||
38 | fpu/softfloat-parts.c.inc | 13 +++++++------ | ||
39 | fpu/softfloat-specialize.c.inc | 29 +---------------------------- | ||
40 | 2 files changed, 8 insertions(+), 34 deletions(-) | ||
41 | |||
42 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/fpu/softfloat-parts.c.inc | ||
45 | +++ b/fpu/softfloat-parts.c.inc | ||
46 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
47 | int ab_mask, int abc_mask) | ||
48 | { | ||
49 | int which; | ||
50 | + bool infzero = (ab_mask == float_cmask_infzero); | ||
51 | |||
52 | if (unlikely(abc_mask & float_cmask_snan)) { | ||
53 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
54 | } | ||
55 | |||
56 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, | ||
57 | - ab_mask == float_cmask_infzero, s); | ||
58 | + if (infzero) { | ||
59 | + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ | ||
60 | + float_raise(float_flag_invalid | float_flag_invalid_imz, s); | ||
61 | + } | ||
62 | + | ||
63 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
64 | |||
65 | if (s->default_nan_mode || which == 3) { | ||
66 | - /* | ||
67 | - * Note that this check is after pickNaNMulAdd so that function | ||
68 | - * has an opportunity to set the Invalid flag for infzero. | ||
69 | - */ | ||
70 | parts_default_nan(a, s); | ||
71 | return a; | ||
72 | } | ||
73 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/fpu/softfloat-specialize.c.inc | ||
76 | +++ b/fpu/softfloat-specialize.c.inc | ||
77 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
78 | * the default NaN | ||
79 | */ | ||
80 | if (infzero && is_qnan(c_cls)) { | ||
81 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
82 | return 3; | ||
83 | } | ||
84 | |||
85 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
86 | * case sets InvalidOp and returns the default NaN | ||
87 | */ | ||
88 | if (infzero) { | ||
89 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
90 | return 3; | ||
91 | } | ||
92 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
93 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
94 | * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
95 | * case sets InvalidOp and returns the input value 'c' | ||
96 | */ | ||
97 | - if (infzero) { | ||
98 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
99 | - return 2; | ||
100 | - } | ||
101 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
102 | if (is_snan(c_cls)) { | ||
103 | return 2; | ||
104 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
105 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
106 | * case sets InvalidOp and returns the input value 'c' | ||
107 | */ | ||
108 | - if (infzero) { | ||
109 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
110 | - return 2; | ||
111 | - } | ||
112 | + | ||
113 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
114 | if (is_snan(c_cls)) { | ||
115 | return 2; | ||
116 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
117 | * to return an input NaN if we have one (ie c) rather than generating | ||
118 | * a default NaN | ||
119 | */ | ||
120 | - if (infzero) { | ||
121 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
122 | - return 2; | ||
123 | - } | ||
124 | |||
125 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
126 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
127 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
128 | return 1; | ||
129 | } | ||
130 | #elif defined(TARGET_RISCV) | ||
131 | - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ | ||
132 | - if (infzero) { | ||
133 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
134 | - } | ||
135 | return 3; /* default NaN */ | ||
136 | #elif defined(TARGET_S390X) | ||
137 | if (infzero) { | ||
138 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
139 | return 3; | ||
140 | } | ||
141 | |||
142 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
143 | return 2; | ||
144 | } | ||
145 | #elif defined(TARGET_SPARC) | ||
146 | - /* For (inf,0,nan) return c. */ | ||
147 | - if (infzero) { | ||
148 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
149 | - return 2; | ||
150 | - } | ||
151 | /* Prefer SNaN over QNaN, order C, B, A. */ | ||
152 | if (is_snan(c_cls)) { | ||
153 | return 2; | ||
154 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
155 | * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
156 | * an input NaN if we have one (ie c). | ||
157 | */ | ||
158 | - if (infzero) { | ||
159 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
160 | - return 2; | ||
161 | - } | ||
162 | if (status->use_first_nan) { | ||
163 | if (is_nan(a_cls)) { | ||
164 | return 0; | ||
165 | -- | ||
166 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | If the target sets default_nan_mode then we're always going to return | ||
2 | the default NaN, and pickNaNMulAdd() no longer has any side effects. | ||
3 | For consistency with pickNaN(), check for default_nan_mode before | ||
4 | calling pickNaNMulAdd(). | ||
1 | 5 | ||
6 | When we convert pickNaNMulAdd() to allow runtime selection of the NaN | ||
7 | propagation rule, this means we won't have to make the targets which | ||
8 | use default_nan_mode also set a propagation rule. | ||
9 | |||
10 | Since RiscV always uses default_nan_mode, this allows us to remove | ||
11 | its ifdef case from pickNaNMulAdd(). | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20241202131347.498124-3-peter.maydell@linaro.org | ||
16 | --- | ||
17 | fpu/softfloat-parts.c.inc | 8 ++++++-- | ||
18 | fpu/softfloat-specialize.c.inc | 9 +++++++-- | ||
19 | 2 files changed, 13 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/fpu/softfloat-parts.c.inc | ||
24 | +++ b/fpu/softfloat-parts.c.inc | ||
25 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
26 | float_raise(float_flag_invalid | float_flag_invalid_imz, s); | ||
27 | } | ||
28 | |||
29 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
30 | + if (s->default_nan_mode) { | ||
31 | + which = 3; | ||
32 | + } else { | ||
33 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
34 | + } | ||
35 | |||
36 | - if (s->default_nan_mode || which == 3) { | ||
37 | + if (which == 3) { | ||
38 | parts_default_nan(a, s); | ||
39 | return a; | ||
40 | } | ||
41 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/fpu/softfloat-specialize.c.inc | ||
44 | +++ b/fpu/softfloat-specialize.c.inc | ||
45 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
46 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
47 | bool infzero, float_status *status) | ||
48 | { | ||
49 | + /* | ||
50 | + * We guarantee not to require the target to tell us how to | ||
51 | + * pick a NaN if we're always returning the default NaN. | ||
52 | + * But if we're not in default-NaN mode then the target must | ||
53 | + * specify. | ||
54 | + */ | ||
55 | + assert(!status->default_nan_mode); | ||
56 | #if defined(TARGET_ARM) | ||
57 | /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
58 | * the default NaN | ||
59 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
60 | } else { | ||
61 | return 1; | ||
62 | } | ||
63 | -#elif defined(TARGET_RISCV) | ||
64 | - return 3; /* default NaN */ | ||
65 | #elif defined(TARGET_S390X) | ||
66 | if (infzero) { | ||
67 | return 3; | ||
68 | -- | ||
69 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | IEEE 758 does not define a fixed rule for what NaN to return in | |
2 | the case of a fused multiply-add of inf * 0 + NaN. Different | ||
3 | architectures thus do different things: | ||
4 | * some return the default NaN | ||
5 | * some return the input NaN | ||
6 | * Arm returns the default NaN if the input NaN is quiet, | ||
7 | and the input NaN if it is signalling | ||
8 | |||
9 | We want to make this logic be runtime selected rather than | ||
10 | hardcoded into the binary, because: | ||
11 | * this will let us have multiple targets in one QEMU binary | ||
12 | * the Arm FEAT_AFP architectural feature includes letting | ||
13 | the guest select a NaN propagation rule at runtime | ||
14 | |||
15 | In this commit we add an enum for the propagation rule, the field in | ||
16 | float_status, and the corresponding getters and setters. We change | ||
17 | pickNaNMulAdd to honour this, but because all targets still leave | ||
18 | this field at its default 0 value, the fallback logic will pick the | ||
19 | rule type with the old ifdef ladder. | ||
20 | |||
21 | Note that four architectures both use the muladd softfloat functions | ||
22 | and did not have a branch of the ifdef ladder to specify their | ||
23 | behaviour (and so were ending up with the "default" case, probably | ||
24 | wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set | ||
25 | default_nan_mode, and so will never get into pickNaNMulAdd(). For | ||
26 | HPPA and i386 we retain the same behaviour as the old default-case, | ||
27 | which is to not ever return the default NaN. This might not be | ||
28 | correct but it is not a behaviour change. | ||
29 | |||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
32 | Message-id: 20241202131347.498124-4-peter.maydell@linaro.org | ||
33 | --- | ||
34 | include/fpu/softfloat-helpers.h | 11 ++++ | ||
35 | include/fpu/softfloat-types.h | 23 +++++++++ | ||
36 | fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- | ||
37 | 3 files changed, 95 insertions(+), 30 deletions(-) | ||
38 | |||
39 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/include/fpu/softfloat-helpers.h | ||
42 | +++ b/include/fpu/softfloat-helpers.h | ||
43 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, | ||
44 | status->float_2nan_prop_rule = rule; | ||
45 | } | ||
46 | |||
47 | +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, | ||
48 | + float_status *status) | ||
49 | +{ | ||
50 | + status->float_infzeronan_rule = rule; | ||
51 | +} | ||
52 | + | ||
53 | static inline void set_flush_to_zero(bool val, float_status *status) | ||
54 | { | ||
55 | status->flush_to_zero = val; | ||
56 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) | ||
57 | return status->float_2nan_prop_rule; | ||
58 | } | ||
59 | |||
60 | +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) | ||
61 | +{ | ||
62 | + return status->float_infzeronan_rule; | ||
63 | +} | ||
64 | + | ||
65 | static inline bool get_flush_to_zero(float_status *status) | ||
66 | { | ||
67 | return status->flush_to_zero; | ||
68 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/include/fpu/softfloat-types.h | ||
71 | +++ b/include/fpu/softfloat-types.h | ||
72 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { | ||
73 | float_2nan_prop_x87, | ||
74 | } Float2NaNPropRule; | ||
75 | |||
76 | +/* | ||
77 | + * Rule for result of fused multiply-add 0 * Inf + NaN. | ||
78 | + * This must be a NaN, but implementations differ on whether this | ||
79 | + * is the input NaN or the default NaN. | ||
80 | + * | ||
81 | + * You don't need to set this if default_nan_mode is enabled. | ||
82 | + * When not in default-NaN mode, it is an error for the target | ||
83 | + * not to set the rule in float_status if it uses muladd, and we | ||
84 | + * will assert if we need to handle an input NaN and no rule was | ||
85 | + * selected. | ||
86 | + */ | ||
87 | +typedef enum __attribute__((__packed__)) { | ||
88 | + /* No propagation rule specified */ | ||
89 | + float_infzeronan_none = 0, | ||
90 | + /* Result is never the default NaN (so always the input NaN) */ | ||
91 | + float_infzeronan_dnan_never, | ||
92 | + /* Result is always the default NaN */ | ||
93 | + float_infzeronan_dnan_always, | ||
94 | + /* Result is the default NaN if the input NaN is quiet */ | ||
95 | + float_infzeronan_dnan_if_qnan, | ||
96 | +} FloatInfZeroNaNRule; | ||
97 | + | ||
98 | /* | ||
99 | * Floating Point Status. Individual architectures may maintain | ||
100 | * several versions of float_status for different functions. The | ||
101 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
102 | FloatRoundMode float_rounding_mode; | ||
103 | FloatX80RoundPrec floatx80_rounding_precision; | ||
104 | Float2NaNPropRule float_2nan_prop_rule; | ||
105 | + FloatInfZeroNaNRule float_infzeronan_rule; | ||
106 | bool tininess_before_rounding; | ||
107 | /* should denormalised results go to zero and set the inexact flag? */ | ||
108 | bool flush_to_zero; | ||
109 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/fpu/softfloat-specialize.c.inc | ||
112 | +++ b/fpu/softfloat-specialize.c.inc | ||
113 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
114 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
115 | bool infzero, float_status *status) | ||
116 | { | ||
117 | + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
118 | + | ||
119 | /* | ||
120 | * We guarantee not to require the target to tell us how to | ||
121 | * pick a NaN if we're always returning the default NaN. | ||
122 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
123 | * specify. | ||
124 | */ | ||
125 | assert(!status->default_nan_mode); | ||
126 | + | ||
127 | + if (rule == float_infzeronan_none) { | ||
128 | + /* | ||
129 | + * Temporarily fall back to ifdef ladder | ||
130 | + */ | ||
131 | #if defined(TARGET_ARM) | ||
132 | - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
133 | - * the default NaN | ||
134 | - */ | ||
135 | - if (infzero && is_qnan(c_cls)) { | ||
136 | - return 3; | ||
137 | + /* | ||
138 | + * For ARM, the (inf,zero,qnan) case returns the default NaN, | ||
139 | + * but (inf,zero,snan) returns the input NaN. | ||
140 | + */ | ||
141 | + rule = float_infzeronan_dnan_if_qnan; | ||
142 | +#elif defined(TARGET_MIPS) | ||
143 | + if (snan_bit_is_one(status)) { | ||
144 | + /* | ||
145 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
146 | + * case sets InvalidOp and returns the default NaN | ||
147 | + */ | ||
148 | + rule = float_infzeronan_dnan_always; | ||
149 | + } else { | ||
150 | + /* | ||
151 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
152 | + * case sets InvalidOp and returns the input value 'c' | ||
153 | + */ | ||
154 | + rule = float_infzeronan_dnan_never; | ||
155 | + } | ||
156 | +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
157 | + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
158 | + defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
159 | + /* | ||
160 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
161 | + * case sets InvalidOp and returns the input value 'c' | ||
162 | + */ | ||
163 | + /* | ||
164 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
165 | + * to return an input NaN if we have one (ie c) rather than generating | ||
166 | + * a default NaN | ||
167 | + */ | ||
168 | + rule = float_infzeronan_dnan_never; | ||
169 | +#elif defined(TARGET_S390X) | ||
170 | + rule = float_infzeronan_dnan_always; | ||
171 | +#endif | ||
172 | } | ||
173 | |||
174 | + if (infzero) { | ||
175 | + /* | ||
176 | + * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
177 | + * and some return the input NaN. | ||
178 | + */ | ||
179 | + switch (rule) { | ||
180 | + case float_infzeronan_dnan_never: | ||
181 | + return 2; | ||
182 | + case float_infzeronan_dnan_always: | ||
183 | + return 3; | ||
184 | + case float_infzeronan_dnan_if_qnan: | ||
185 | + return is_qnan(c_cls) ? 3 : 2; | ||
186 | + default: | ||
187 | + g_assert_not_reached(); | ||
188 | + } | ||
189 | + } | ||
190 | + | ||
191 | +#if defined(TARGET_ARM) | ||
192 | + | ||
193 | /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
194 | * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
195 | */ | ||
196 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
197 | } | ||
198 | #elif defined(TARGET_MIPS) | ||
199 | if (snan_bit_is_one(status)) { | ||
200 | - /* | ||
201 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
202 | - * case sets InvalidOp and returns the default NaN | ||
203 | - */ | ||
204 | - if (infzero) { | ||
205 | - return 3; | ||
206 | - } | ||
207 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
208 | if (is_snan(a_cls)) { | ||
209 | return 0; | ||
210 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
211 | return 2; | ||
212 | } | ||
213 | } else { | ||
214 | - /* | ||
215 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
216 | - * case sets InvalidOp and returns the input value 'c' | ||
217 | - */ | ||
218 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
219 | if (is_snan(c_cls)) { | ||
220 | return 2; | ||
221 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
222 | } | ||
223 | } | ||
224 | #elif defined(TARGET_LOONGARCH64) | ||
225 | - /* | ||
226 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
227 | - * case sets InvalidOp and returns the input value 'c' | ||
228 | - */ | ||
229 | - | ||
230 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
231 | if (is_snan(c_cls)) { | ||
232 | return 2; | ||
233 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
234 | return 1; | ||
235 | } | ||
236 | #elif defined(TARGET_PPC) | ||
237 | - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
238 | - * to return an input NaN if we have one (ie c) rather than generating | ||
239 | - * a default NaN | ||
240 | - */ | ||
241 | - | ||
242 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
243 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
244 | */ | ||
245 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
246 | return 1; | ||
247 | } | ||
248 | #elif defined(TARGET_S390X) | ||
249 | - if (infzero) { | ||
250 | - return 3; | ||
251 | - } | ||
252 | - | ||
253 | if (is_snan(a_cls)) { | ||
254 | return 0; | ||
255 | } else if (is_snan(b_cls)) { | ||
256 | -- | ||
257 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Explicitly set a rule in the softfloat tests for the inf-zero-nan | ||
2 | muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, | ||
3 | and so we should select here the Arm rule of | ||
4 | float_infzeronan_dnan_if_qnan. | ||
1 | 5 | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20241202131347.498124-5-peter.maydell@linaro.org | ||
9 | --- | ||
10 | tests/fp/fp-bench.c | 5 +++++ | ||
11 | tests/fp/fp-test.c | 5 +++++ | ||
12 | 2 files changed, 10 insertions(+) | ||
13 | |||
14 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/tests/fp/fp-bench.c | ||
17 | +++ b/tests/fp/fp-bench.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
19 | { | ||
20 | bench_func_t f; | ||
21 | |||
22 | + /* | ||
23 | + * These implementation-defined choices for various things IEEE | ||
24 | + * doesn't specify match those used by the Arm architecture. | ||
25 | + */ | ||
26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
28 | |||
29 | f = bench_funcs[operation][precision]; | ||
30 | g_assert(f); | ||
31 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/tests/fp/fp-test.c | ||
34 | +++ b/tests/fp/fp-test.c | ||
35 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
36 | { | ||
37 | unsigned int i; | ||
38 | |||
39 | + /* | ||
40 | + * These implementation-defined choices for various things IEEE | ||
41 | + * doesn't specify match those used by the Arm architecture. | ||
42 | + */ | ||
43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
44 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
45 | |||
46 | genCases_setLevel(test_level); | ||
47 | verCases_maxErrorCount = n_max_errors; | ||
48 | -- | ||
49 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the FloatInfZeroNaNRule explicitly for the Arm target, |
---|---|---|---|
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
2 | 3 | ||
3 | Simplify freeing cp_regs hash table entries by using a single | ||
4 | allocation for the entire value. | ||
5 | |||
6 | This fixes a theoretical bug if we were to ever free the entire | ||
7 | hash table, because we've been installing string literal constants | ||
8 | into the cpreg structure in define_arm_vh_e2h_redirects_aliases. | ||
9 | However, at present we only free entries created for AArch32 | ||
10 | wildcard cpregs which get overwritten by more specific cpregs, | ||
11 | so this bug is never exposed. | ||
12 | |||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Message-id: 20220501055028.646596-13-richard.henderson@linaro.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-6-peter.maydell@linaro.org | ||
17 | --- | 7 | --- |
18 | target/arm/cpu.c | 16 +--------------- | 8 | target/arm/cpu.c | 3 +++ |
19 | target/arm/helper.c | 10 ++++++++-- | 9 | fpu/softfloat-specialize.c.inc | 8 +------- |
20 | 2 files changed, 9 insertions(+), 17 deletions(-) | 10 | 2 files changed, 4 insertions(+), 7 deletions(-) |
21 | 11 | ||
22 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
23 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/cpu.c | 14 | --- a/target/arm/cpu.c |
25 | +++ b/target/arm/cpu.c | 15 | +++ b/target/arm/cpu.c |
26 | @@ -XXX,XX +XXX,XX @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) | 16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
27 | return (Aff1 << ARM_AFF1_SHIFT) | Aff0; | 17 | * * tininess-before-rounding |
18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then | ||
19 | * operand A over operand B (see FPProcessNaNs() pseudocode) | ||
20 | + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, | ||
21 | + * and the input NaN if it is signalling | ||
22 | */ | ||
23 | static void arm_set_default_fp_behaviours(float_status *s) | ||
24 | { | ||
25 | set_float_detect_tininess(float_tininess_before_rounding, s); | ||
26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | ||
27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
28 | } | 28 | } |
29 | 29 | ||
30 | -static void cpreg_hashtable_data_destroy(gpointer data) | 30 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
31 | -{ | 31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
32 | - /* | ||
33 | - * Destroy function for cpu->cp_regs hashtable data entries. | ||
34 | - * We must free the name string because it was g_strdup()ed in | ||
35 | - * add_cpreg_to_hashtable(). It's OK to cast away the 'const' | ||
36 | - * from r->name because we know we definitely allocated it. | ||
37 | - */ | ||
38 | - ARMCPRegInfo *r = data; | ||
39 | - | ||
40 | - g_free((void *)r->name); | ||
41 | - g_free(r); | ||
42 | -} | ||
43 | - | ||
44 | static void arm_cpu_initfn(Object *obj) | ||
45 | { | ||
46 | ARMCPU *cpu = ARM_CPU(obj); | ||
47 | |||
48 | cpu_set_cpustate_pointers(cpu); | ||
49 | cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, | ||
50 | - NULL, cpreg_hashtable_data_destroy); | ||
51 | + NULL, g_free); | ||
52 | |||
53 | QLIST_INIT(&cpu->pre_el_change_hooks); | ||
54 | QLIST_INIT(&cpu->el_change_hooks); | ||
55 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
57 | --- a/target/arm/helper.c | 33 | --- a/fpu/softfloat-specialize.c.inc |
58 | +++ b/target/arm/helper.c | 34 | +++ b/fpu/softfloat-specialize.c.inc |
59 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
60 | * add a single reginfo struct to the hash table. | 36 | /* |
61 | */ | 37 | * Temporarily fall back to ifdef ladder |
62 | uint32_t key; | 38 | */ |
63 | - ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | 39 | -#if defined(TARGET_ARM) |
64 | + ARMCPRegInfo *r2; | 40 | - /* |
65 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | 41 | - * For ARM, the (inf,zero,qnan) case returns the default NaN, |
66 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; | 42 | - * but (inf,zero,snan) returns the input NaN. |
67 | + size_t name_len; | 43 | - */ |
68 | + | 44 | - rule = float_infzeronan_dnan_if_qnan; |
69 | + /* Combine cpreg and name into one allocation. */ | 45 | -#elif defined(TARGET_MIPS) |
70 | + name_len = strlen(name) + 1; | 46 | +#if defined(TARGET_MIPS) |
71 | + r2 = g_malloc(sizeof(*r2) + name_len); | 47 | if (snan_bit_is_one(status)) { |
72 | + *r2 = *r; | 48 | /* |
73 | + r2->name = memcpy(r2 + 1, name, name_len); | 49 | * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) |
74 | |||
75 | - r2->name = g_strdup(name); | ||
76 | /* Reset the secure state to the specific incoming state. This is | ||
77 | * necessary as the register may have been defined with both states. | ||
78 | */ | ||
79 | -- | 50 | -- |
80 | 2.25.1 | 51 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for s390, so we | ||
2 | can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-7-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/s390x/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/s390x/cpu.c | ||
15 | +++ b/target/s390x/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_float_detect_tininess(float_tininess_before_rounding, | ||
18 | &env->fpu_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
20 | + set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
21 | + &env->fpu_status); | ||
22 | /* fall through */ | ||
23 | case RESET_TYPE_S390_CPU_NORMAL: | ||
24 | env->psw.mask &= ~PSW_MASK_RI; | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | * a default NaN | ||
31 | */ | ||
32 | rule = float_infzeronan_dnan_never; | ||
33 | -#elif defined(TARGET_S390X) | ||
34 | - rule = float_infzeronan_dnan_always; | ||
35 | #endif | ||
36 | } | ||
37 | |||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the PPC target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/ppc/cpu_init.c | 7 +++++++ | ||
9 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
11 | |||
12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/ppc/cpu_init.c | ||
15 | +++ b/target/ppc/cpu_init.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | ||
20 | + /* | ||
21 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
22 | + * to return an input NaN if we have one (ie c) rather than generating | ||
23 | + * a default NaN | ||
24 | + */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
26 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); | ||
27 | |||
28 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { | ||
29 | ppc_spr_t *spr = &env->spr_cb[i]; | ||
30 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/fpu/softfloat-specialize.c.inc | ||
33 | +++ b/fpu/softfloat-specialize.c.inc | ||
34 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
35 | */ | ||
36 | rule = float_infzeronan_dnan_never; | ||
37 | } | ||
38 | -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
39 | +#elif defined(TARGET_SPARC) || \ | ||
40 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
41 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
42 | /* | ||
43 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
44 | * case sets InvalidOp and returns the input value 'c' | ||
45 | */ | ||
46 | - /* | ||
47 | - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
48 | - * to return an input NaN if we have one (ie c) rather than generating | ||
49 | - * a default NaN | ||
50 | - */ | ||
51 | rule = float_infzeronan_dnan_never; | ||
52 | #endif | ||
53 | } | ||
54 | -- | ||
55 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the MIPS target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-9-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/mips/fpu_helper.h | 9 +++++++++ | ||
9 | target/mips/msa.c | 4 ++++ | ||
10 | fpu/softfloat-specialize.c.inc | 16 +--------------- | ||
11 | 3 files changed, 14 insertions(+), 15 deletions(-) | ||
12 | |||
13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/mips/fpu_helper.h | ||
16 | +++ b/target/mips/fpu_helper.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env) | ||
18 | static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
19 | { | ||
20 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); | ||
21 | + FloatInfZeroNaNRule izn_rule; | ||
22 | |||
23 | /* | ||
24 | * With nan2008, SNaNs are silenced in the usual way. | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
26 | */ | ||
27 | set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); | ||
28 | set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); | ||
29 | + /* | ||
30 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
31 | + * case sets InvalidOp and returns the default NaN. | ||
32 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
33 | + * case sets InvalidOp and returns the input value 'c'. | ||
34 | + */ | ||
35 | + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | ||
36 | + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
37 | } | ||
38 | |||
39 | static inline void restore_fp_status(CPUMIPSState *env) | ||
40 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/mips/msa.c | ||
43 | +++ b/target/mips/msa.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
45 | |||
46 | /* set proper signanling bit meaning ("1" means "quiet") */ | ||
47 | set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); | ||
48 | + | ||
49 | + /* Inf * 0 + NaN returns the input NaN */ | ||
50 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, | ||
51 | + &env->active_tc.msa_fp_status); | ||
52 | } | ||
53 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/fpu/softfloat-specialize.c.inc | ||
56 | +++ b/fpu/softfloat-specialize.c.inc | ||
57 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
58 | /* | ||
59 | * Temporarily fall back to ifdef ladder | ||
60 | */ | ||
61 | -#if defined(TARGET_MIPS) | ||
62 | - if (snan_bit_is_one(status)) { | ||
63 | - /* | ||
64 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
65 | - * case sets InvalidOp and returns the default NaN | ||
66 | - */ | ||
67 | - rule = float_infzeronan_dnan_always; | ||
68 | - } else { | ||
69 | - /* | ||
70 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
71 | - * case sets InvalidOp and returns the input value 'c' | ||
72 | - */ | ||
73 | - rule = float_infzeronan_dnan_never; | ||
74 | - } | ||
75 | -#elif defined(TARGET_SPARC) || \ | ||
76 | +#if defined(TARGET_SPARC) || \ | ||
77 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
78 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
79 | /* | ||
80 | -- | ||
81 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the SPARC target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-10-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | * the CPU state struct so it won't get zeroed on reset. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
22 | |||
23 | cpu_exec_realizefn(cs, &local_err); | ||
24 | if (local_err != NULL) { | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | /* | ||
31 | * Temporarily fall back to ifdef ladder | ||
32 | */ | ||
33 | -#if defined(TARGET_SPARC) || \ | ||
34 | - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
35 | +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
36 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
37 | /* | ||
38 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the xtensa target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-11-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/xtensa/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 +- | ||
10 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
11 | |||
12 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/xtensa/cpu.c | ||
15 | +++ b/target/xtensa/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | reset_mmu(env); | ||
18 | cs->halted = env->runstall; | ||
19 | #endif | ||
20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
22 | set_no_signaling_nans(!dfpu, &env->fp_status); | ||
23 | xtensa_use_first_nan(env, !dfpu); | ||
24 | } | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | /* | ||
31 | * Temporarily fall back to ifdef ladder | ||
32 | */ | ||
33 | -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
34 | +#if defined(TARGET_HPPA) || \ | ||
35 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
36 | /* | ||
37 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the x86 target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-12-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/i386/tcg/fpu_helper.c | 7 +++++++ | ||
8 | fpu/softfloat-specialize.c.inc | 2 +- | ||
9 | 2 files changed, 8 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/i386/tcg/fpu_helper.c | ||
14 | +++ b/target/i386/tcg/fpu_helper.c | ||
15 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); | ||
19 | + /* | ||
20 | + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 | ||
21 | + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is | ||
22 | + * specified -- for 0 * inf + NaN the input NaN is selected, and if | ||
23 | + * there are multiple input NaNs they are selected in the order a, b, c. | ||
24 | + */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
26 | } | ||
27 | |||
28 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/fpu/softfloat-specialize.c.inc | ||
32 | +++ b/fpu/softfloat-specialize.c.inc | ||
33 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
34 | * Temporarily fall back to ifdef ladder | ||
35 | */ | ||
36 | #if defined(TARGET_HPPA) || \ | ||
37 | - defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
38 | + defined(TARGET_LOONGARCH) | ||
39 | /* | ||
40 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
41 | * case sets InvalidOp and returns the input value 'c' | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the loongarch target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-13-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/loongarch/tcg/fpu_helper.c | 5 +++++ | ||
8 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
9 | 2 files changed, 6 insertions(+), 6 deletions(-) | ||
10 | |||
11 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/loongarch/tcg/fpu_helper.c | ||
14 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
15 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
16 | &env->fp_status); | ||
17 | set_flush_to_zero(0, &env->fp_status); | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
19 | + /* | ||
20 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
21 | + * case sets InvalidOp and returns the input value 'c' | ||
22 | + */ | ||
23 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
24 | } | ||
25 | |||
26 | int ieee_ex_to_loongarch(int xcpt) | ||
27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/fpu/softfloat-specialize.c.inc | ||
30 | +++ b/fpu/softfloat-specialize.c.inc | ||
31 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
32 | /* | ||
33 | * Temporarily fall back to ifdef ladder | ||
34 | */ | ||
35 | -#if defined(TARGET_HPPA) || \ | ||
36 | - defined(TARGET_LOONGARCH) | ||
37 | - /* | ||
38 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
39 | - * case sets InvalidOp and returns the input value 'c' | ||
40 | - */ | ||
41 | +#if defined(TARGET_HPPA) | ||
42 | rule = float_infzeronan_dnan_never; | ||
43 | #endif | ||
44 | } | ||
45 | -- | ||
46 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the HPPA target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | As this is the last target to be converted to explicitly setting | ||
5 | the rule, we can remove the fallback code in pickNaNMulAdd() | ||
6 | entirely. | ||
7 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20241202131347.498124-14-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/hppa/fpu_helper.c | 2 ++ | ||
13 | fpu/softfloat-specialize.c.inc | 13 +------------ | ||
14 | 2 files changed, 3 insertions(+), 12 deletions(-) | ||
15 | |||
16 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/hppa/fpu_helper.c | ||
19 | +++ b/target/hppa/fpu_helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
21 | * HPPA does note implement a CPU reset method at all... | ||
22 | */ | ||
23 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
24 | + /* For inf * 0 + NaN, return the input NaN */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
26 | } | ||
27 | |||
28 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) | ||
29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/fpu/softfloat-specialize.c.inc | ||
32 | +++ b/fpu/softfloat-specialize.c.inc | ||
33 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
34 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
35 | bool infzero, float_status *status) | ||
36 | { | ||
37 | - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
38 | - | ||
39 | /* | ||
40 | * We guarantee not to require the target to tell us how to | ||
41 | * pick a NaN if we're always returning the default NaN. | ||
42 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
43 | */ | ||
44 | assert(!status->default_nan_mode); | ||
45 | |||
46 | - if (rule == float_infzeronan_none) { | ||
47 | - /* | ||
48 | - * Temporarily fall back to ifdef ladder | ||
49 | - */ | ||
50 | -#if defined(TARGET_HPPA) | ||
51 | - rule = float_infzeronan_dnan_never; | ||
52 | -#endif | ||
53 | - } | ||
54 | - | ||
55 | if (infzero) { | ||
56 | /* | ||
57 | * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
58 | * and some return the input NaN. | ||
59 | */ | ||
60 | - switch (rule) { | ||
61 | + switch (status->float_infzeronan_rule) { | ||
62 | case float_infzeronan_dnan_never: | ||
63 | return 2; | ||
64 | case float_infzeronan_dnan_always: | ||
65 | -- | ||
66 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The new implementation of pickNaNMulAdd() will find it convenient | ||
2 | to know whether at least one of the three arguments to the muladd | ||
3 | was a signaling NaN. We already calculate that in the caller, | ||
4 | so pass it in as a new bool have_snan. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-15-peter.maydell@linaro.org | ||
9 | --- | ||
10 | fpu/softfloat-parts.c.inc | 5 +++-- | ||
11 | fpu/softfloat-specialize.c.inc | 2 +- | ||
12 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/fpu/softfloat-parts.c.inc | ||
17 | +++ b/fpu/softfloat-parts.c.inc | ||
18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
19 | { | ||
20 | int which; | ||
21 | bool infzero = (ab_mask == float_cmask_infzero); | ||
22 | + bool have_snan = (abc_mask & float_cmask_snan); | ||
23 | |||
24 | - if (unlikely(abc_mask & float_cmask_snan)) { | ||
25 | + if (unlikely(have_snan)) { | ||
26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
27 | } | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
30 | if (s->default_nan_mode) { | ||
31 | which = 3; | ||
32 | } else { | ||
33 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
34 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); | ||
35 | } | ||
36 | |||
37 | if (which == 3) { | ||
38 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/fpu/softfloat-specialize.c.inc | ||
41 | +++ b/fpu/softfloat-specialize.c.inc | ||
42 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
43 | | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | ||
44 | *----------------------------------------------------------------------------*/ | ||
45 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
46 | - bool infzero, float_status *status) | ||
47 | + bool infzero, bool have_snan, float_status *status) | ||
48 | { | ||
49 | /* | ||
50 | * We guarantee not to require the target to tell us how to | ||
51 | -- | ||
52 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | IEEE 758 does not define a fixed rule for which NaN to pick as the |
---|---|---|---|
2 | 2 | result if both operands of a 3-operand fused multiply-add operation | |
3 | Add the aa64 predicate for detecting RAS support from id registers. | 3 | are NaNs. As a result different architectures have ended up with |
4 | We already have the aa32 version from the M-profile work. | 4 | different rules for propagating NaNs. |
5 | Add the 'any' predicate for testing both aa64 and aa32. | 5 | |
6 | 6 | QEMU currently hardcodes the NaN propagation logic into the binary | |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | because pickNaNMulAdd() has an ifdef ladder for different targets. |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | We want to make the propagation rule instead be selectable at |
9 | Message-id: 20220501055028.646596-34-richard.henderson@linaro.org | 9 | runtime, because: |
10 | * this will let us have multiple targets in one QEMU binary | ||
11 | * the Arm FEAT_AFP architectural feature includes letting | ||
12 | the guest select a NaN propagation rule at runtime | ||
13 | |||
14 | In this commit we add an enum for the propagation rule, the field in | ||
15 | float_status, and the corresponding getters and setters. We change | ||
16 | pickNaNMulAdd to honour this, but because all targets still leave | ||
17 | this field at its default 0 value, the fallback logic will pick the | ||
18 | rule type with the old ifdef ladder. | ||
19 | |||
20 | It's valid not to set a propagation rule if default_nan_mode is | ||
21 | enabled, because in that case there's no need to pick a NaN; all the | ||
22 | callers of pickNaNMulAdd() catch this case and skip calling it. | ||
23 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-id: 20241202131347.498124-16-peter.maydell@linaro.org | ||
11 | --- | 27 | --- |
12 | target/arm/cpu.h | 10 ++++++++++ | 28 | include/fpu/softfloat-helpers.h | 11 +++ |
13 | 1 file changed, 10 insertions(+) | 29 | include/fpu/softfloat-types.h | 55 +++++++++++ |
14 | 30 | fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ | |
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 31 | 3 files changed, 107 insertions(+), 126 deletions(-) |
32 | |||
33 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 35 | --- a/include/fpu/softfloat-helpers.h |
18 | +++ b/target/arm/cpu.h | 36 | +++ b/include/fpu/softfloat-helpers.h |
19 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) | 37 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, |
20 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; | 38 | status->float_2nan_prop_rule = rule; |
21 | } | 39 | } |
22 | 40 | ||
23 | +static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) | 41 | +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, |
42 | + float_status *status) | ||
24 | +{ | 43 | +{ |
25 | + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; | 44 | + status->float_3nan_prop_rule = rule; |
26 | +} | 45 | +} |
27 | + | 46 | + |
28 | static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) | 47 | static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, |
48 | float_status *status) | ||
29 | { | 49 | { |
30 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; | 50 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) |
31 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) | 51 | return status->float_2nan_prop_rule; |
32 | return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); | ||
33 | } | 52 | } |
34 | 53 | ||
35 | +static inline bool isar_feature_any_ras(const ARMISARegisters *id) | 54 | +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) |
36 | +{ | 55 | +{ |
37 | + return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); | 56 | + return status->float_3nan_prop_rule; |
38 | +} | 57 | +} |
39 | + | 58 | + |
59 | static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) | ||
60 | { | ||
61 | return status->float_infzeronan_rule; | ||
62 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/include/fpu/softfloat-types.h | ||
65 | +++ b/include/fpu/softfloat-types.h | ||
66 | @@ -XXX,XX +XXX,XX @@ this code that are retained. | ||
67 | #ifndef SOFTFLOAT_TYPES_H | ||
68 | #define SOFTFLOAT_TYPES_H | ||
69 | |||
70 | +#include "hw/registerfields.h" | ||
71 | + | ||
40 | /* | 72 | /* |
41 | * Forward to the above feature tests given an ARMCPU pointer. | 73 | * Software IEC/IEEE floating-point types. |
42 | */ | 74 | */ |
75 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { | ||
76 | float_2nan_prop_x87, | ||
77 | } Float2NaNPropRule; | ||
78 | |||
79 | +/* | ||
80 | + * 3-input NaN propagation rule, for fused multiply-add. Individual | ||
81 | + * architectures have different rules for which input NaN is | ||
82 | + * propagated to the output when there is more than one NaN on the | ||
83 | + * input. | ||
84 | + * | ||
85 | + * If default_nan_mode is enabled then it is valid not to set a NaN | ||
86 | + * propagation rule, because the softfloat code guarantees not to try | ||
87 | + * to pick a NaN to propagate in default NaN mode. When not in | ||
88 | + * default-NaN mode, it is an error for the target not to set the rule | ||
89 | + * in float_status if it uses a muladd, and we will assert if we need | ||
90 | + * to handle an input NaN and no rule was selected. | ||
91 | + * | ||
92 | + * The naming scheme for Float3NaNPropRule values is: | ||
93 | + * float_3nan_prop_s_abc: | ||
94 | + * = "Prefer SNaN over QNaN, then operand A over B over C" | ||
95 | + * float_3nan_prop_abc: | ||
96 | + * = "Prefer A over B over C regardless of SNaN vs QNAN" | ||
97 | + * | ||
98 | + * For QEMU, the multiply-add operation is A * B + C. | ||
99 | + */ | ||
100 | + | ||
101 | +/* | ||
102 | + * We set the Float3NaNPropRule enum values up so we can select the | ||
103 | + * right value in pickNaNMulAdd in a data driven way. | ||
104 | + */ | ||
105 | +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ | ||
106 | +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ | ||
107 | +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ | ||
108 | +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ | ||
109 | + | ||
110 | +#define PROPRULE(X, Y, Z) \ | ||
111 | + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) | ||
112 | + | ||
113 | +typedef enum __attribute__((__packed__)) { | ||
114 | + float_3nan_prop_none = 0, /* No propagation rule specified */ | ||
115 | + float_3nan_prop_abc = PROPRULE(0, 1, 2), | ||
116 | + float_3nan_prop_acb = PROPRULE(0, 2, 1), | ||
117 | + float_3nan_prop_bac = PROPRULE(1, 0, 2), | ||
118 | + float_3nan_prop_bca = PROPRULE(1, 2, 0), | ||
119 | + float_3nan_prop_cab = PROPRULE(2, 0, 1), | ||
120 | + float_3nan_prop_cba = PROPRULE(2, 1, 0), | ||
121 | + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, | ||
122 | + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, | ||
123 | + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, | ||
124 | + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, | ||
125 | + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, | ||
126 | + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, | ||
127 | +} Float3NaNPropRule; | ||
128 | + | ||
129 | +#undef PROPRULE | ||
130 | + | ||
131 | /* | ||
132 | * Rule for result of fused multiply-add 0 * Inf + NaN. | ||
133 | * This must be a NaN, but implementations differ on whether this | ||
134 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
135 | FloatRoundMode float_rounding_mode; | ||
136 | FloatX80RoundPrec floatx80_rounding_precision; | ||
137 | Float2NaNPropRule float_2nan_prop_rule; | ||
138 | + Float3NaNPropRule float_3nan_prop_rule; | ||
139 | FloatInfZeroNaNRule float_infzeronan_rule; | ||
140 | bool tininess_before_rounding; | ||
141 | /* should denormalised results go to zero and set the inexact flag? */ | ||
142 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/fpu/softfloat-specialize.c.inc | ||
145 | +++ b/fpu/softfloat-specialize.c.inc | ||
146 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
147 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
148 | bool infzero, bool have_snan, float_status *status) | ||
149 | { | ||
150 | + FloatClass cls[3] = { a_cls, b_cls, c_cls }; | ||
151 | + Float3NaNPropRule rule = status->float_3nan_prop_rule; | ||
152 | + int which; | ||
153 | + | ||
154 | /* | ||
155 | * We guarantee not to require the target to tell us how to | ||
156 | * pick a NaN if we're always returning the default NaN. | ||
157 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
158 | } | ||
159 | } | ||
160 | |||
161 | + if (rule == float_3nan_prop_none) { | ||
162 | #if defined(TARGET_ARM) | ||
163 | - | ||
164 | - /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
165 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
166 | - */ | ||
167 | - if (is_snan(c_cls)) { | ||
168 | - return 2; | ||
169 | - } else if (is_snan(a_cls)) { | ||
170 | - return 0; | ||
171 | - } else if (is_snan(b_cls)) { | ||
172 | - return 1; | ||
173 | - } else if (is_qnan(c_cls)) { | ||
174 | - return 2; | ||
175 | - } else if (is_qnan(a_cls)) { | ||
176 | - return 0; | ||
177 | - } else { | ||
178 | - return 1; | ||
179 | - } | ||
180 | + /* | ||
181 | + * This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
182 | + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b | ||
183 | + */ | ||
184 | + rule = float_3nan_prop_s_cab; | ||
185 | #elif defined(TARGET_MIPS) | ||
186 | - if (snan_bit_is_one(status)) { | ||
187 | - /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
188 | - if (is_snan(a_cls)) { | ||
189 | - return 0; | ||
190 | - } else if (is_snan(b_cls)) { | ||
191 | - return 1; | ||
192 | - } else if (is_snan(c_cls)) { | ||
193 | - return 2; | ||
194 | - } else if (is_qnan(a_cls)) { | ||
195 | - return 0; | ||
196 | - } else if (is_qnan(b_cls)) { | ||
197 | - return 1; | ||
198 | + if (snan_bit_is_one(status)) { | ||
199 | + rule = float_3nan_prop_s_abc; | ||
200 | } else { | ||
201 | - return 2; | ||
202 | + rule = float_3nan_prop_s_cab; | ||
203 | } | ||
204 | - } else { | ||
205 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
206 | - if (is_snan(c_cls)) { | ||
207 | - return 2; | ||
208 | - } else if (is_snan(a_cls)) { | ||
209 | - return 0; | ||
210 | - } else if (is_snan(b_cls)) { | ||
211 | - return 1; | ||
212 | - } else if (is_qnan(c_cls)) { | ||
213 | - return 2; | ||
214 | - } else if (is_qnan(a_cls)) { | ||
215 | - return 0; | ||
216 | - } else { | ||
217 | - return 1; | ||
218 | - } | ||
219 | - } | ||
220 | #elif defined(TARGET_LOONGARCH64) | ||
221 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
222 | - if (is_snan(c_cls)) { | ||
223 | - return 2; | ||
224 | - } else if (is_snan(a_cls)) { | ||
225 | - return 0; | ||
226 | - } else if (is_snan(b_cls)) { | ||
227 | - return 1; | ||
228 | - } else if (is_qnan(c_cls)) { | ||
229 | - return 2; | ||
230 | - } else if (is_qnan(a_cls)) { | ||
231 | - return 0; | ||
232 | - } else { | ||
233 | - return 1; | ||
234 | - } | ||
235 | + rule = float_3nan_prop_s_cab; | ||
236 | #elif defined(TARGET_PPC) | ||
237 | - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
238 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
239 | - */ | ||
240 | - if (is_nan(a_cls)) { | ||
241 | - return 0; | ||
242 | - } else if (is_nan(c_cls)) { | ||
243 | - return 2; | ||
244 | - } else { | ||
245 | - return 1; | ||
246 | - } | ||
247 | + /* | ||
248 | + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
249 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
250 | + */ | ||
251 | + rule = float_3nan_prop_acb; | ||
252 | #elif defined(TARGET_S390X) | ||
253 | - if (is_snan(a_cls)) { | ||
254 | - return 0; | ||
255 | - } else if (is_snan(b_cls)) { | ||
256 | - return 1; | ||
257 | - } else if (is_snan(c_cls)) { | ||
258 | - return 2; | ||
259 | - } else if (is_qnan(a_cls)) { | ||
260 | - return 0; | ||
261 | - } else if (is_qnan(b_cls)) { | ||
262 | - return 1; | ||
263 | - } else { | ||
264 | - return 2; | ||
265 | - } | ||
266 | + rule = float_3nan_prop_s_abc; | ||
267 | #elif defined(TARGET_SPARC) | ||
268 | - /* Prefer SNaN over QNaN, order C, B, A. */ | ||
269 | - if (is_snan(c_cls)) { | ||
270 | - return 2; | ||
271 | - } else if (is_snan(b_cls)) { | ||
272 | - return 1; | ||
273 | - } else if (is_snan(a_cls)) { | ||
274 | - return 0; | ||
275 | - } else if (is_qnan(c_cls)) { | ||
276 | - return 2; | ||
277 | - } else if (is_qnan(b_cls)) { | ||
278 | - return 1; | ||
279 | - } else { | ||
280 | - return 0; | ||
281 | - } | ||
282 | + rule = float_3nan_prop_s_cba; | ||
283 | #elif defined(TARGET_XTENSA) | ||
284 | - /* | ||
285 | - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
286 | - * an input NaN if we have one (ie c). | ||
287 | - */ | ||
288 | - if (status->use_first_nan) { | ||
289 | - if (is_nan(a_cls)) { | ||
290 | - return 0; | ||
291 | - } else if (is_nan(b_cls)) { | ||
292 | - return 1; | ||
293 | + if (status->use_first_nan) { | ||
294 | + rule = float_3nan_prop_abc; | ||
295 | } else { | ||
296 | - return 2; | ||
297 | + rule = float_3nan_prop_cba; | ||
298 | } | ||
299 | - } else { | ||
300 | - if (is_nan(c_cls)) { | ||
301 | - return 2; | ||
302 | - } else if (is_nan(b_cls)) { | ||
303 | - return 1; | ||
304 | - } else { | ||
305 | - return 0; | ||
306 | - } | ||
307 | - } | ||
308 | #else | ||
309 | - /* A default implementation: prefer a to b to c. | ||
310 | - * This is unlikely to actually match any real implementation. | ||
311 | - */ | ||
312 | - if (is_nan(a_cls)) { | ||
313 | - return 0; | ||
314 | - } else if (is_nan(b_cls)) { | ||
315 | - return 1; | ||
316 | - } else { | ||
317 | - return 2; | ||
318 | - } | ||
319 | + rule = float_3nan_prop_abc; | ||
320 | #endif | ||
321 | + } | ||
322 | + | ||
323 | + assert(rule != float_3nan_prop_none); | ||
324 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
325 | + /* We have at least one SNaN input and should prefer it */ | ||
326 | + do { | ||
327 | + which = rule & R_3NAN_1ST_MASK; | ||
328 | + rule >>= R_3NAN_1ST_LENGTH; | ||
329 | + } while (!is_snan(cls[which])); | ||
330 | + } else { | ||
331 | + do { | ||
332 | + which = rule & R_3NAN_1ST_MASK; | ||
333 | + rule >>= R_3NAN_1ST_LENGTH; | ||
334 | + } while (!is_nan(cls[which])); | ||
335 | + } | ||
336 | + return which; | ||
337 | } | ||
338 | |||
339 | /*---------------------------------------------------------------------------- | ||
43 | -- | 340 | -- |
44 | 2.25.1 | 341 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Explicitly set a rule in the softfloat tests for propagating NaNs in | ||
2 | the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and | ||
3 | so we should select here the Arm rule of float_3nan_prop_s_cab. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-17-peter.maydell@linaro.org | ||
8 | --- | ||
9 | tests/fp/fp-bench.c | 1 + | ||
10 | tests/fp/fp-test.c | 1 + | ||
11 | 2 files changed, 2 insertions(+) | ||
12 | |||
13 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/tests/fp/fp-bench.c | ||
16 | +++ b/tests/fp/fp-bench.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
18 | * doesn't specify match those used by the Arm architecture. | ||
19 | */ | ||
20 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); | ||
22 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
23 | |||
24 | f = bench_funcs[operation][precision]; | ||
25 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/tests/fp/fp-test.c | ||
28 | +++ b/tests/fp/fp-test.c | ||
29 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
30 | * doesn't specify match those used by the Arm architecture. | ||
31 | */ | ||
32 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
33 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); | ||
34 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
35 | |||
36 | genCases_setLevel(test_level); | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the Float3NaNPropRule explicitly for Arm, and remove the |
---|---|---|---|
2 | ifdef from pickNaNMulAdd(). | ||
2 | 3 | ||
3 | This controls whether the PACI{A,B}SP instructions trap with BTYPE=3 | ||
4 | (indirect branch from register other than x16/x17). The linux kernel | ||
5 | sets this in bti_enable(). | ||
6 | |||
7 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20220427042312.294300-1-richard.henderson@linaro.org | ||
11 | [PMM: remove stray change to makefile comment] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-18-peter.maydell@linaro.org | ||
13 | --- | 7 | --- |
14 | target/arm/cpu.c | 2 ++ | 8 | target/arm/cpu.c | 5 +++++ |
15 | tests/tcg/aarch64/bti-3.c | 42 +++++++++++++++++++++++++++++++ | 9 | fpu/softfloat-specialize.c.inc | 8 +------- |
16 | tests/tcg/aarch64/Makefile.target | 6 ++--- | 10 | 2 files changed, 6 insertions(+), 7 deletions(-) |
17 | 3 files changed, 47 insertions(+), 3 deletions(-) | ||
18 | create mode 100644 tests/tcg/aarch64/bti-3.c | ||
19 | 11 | ||
20 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
21 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/cpu.c | 14 | --- a/target/arm/cpu.c |
23 | +++ b/target/arm/cpu.c | 15 | +++ b/target/arm/cpu.c |
24 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | 16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
25 | /* Enable all PAC keys. */ | 17 | * * tininess-before-rounding |
26 | env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | | 18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then |
27 | SCTLR_EnDA | SCTLR_EnDB); | 19 | * operand A over operand B (see FPProcessNaNs() pseudocode) |
28 | + /* Trap on btype=3 for PACIxSP. */ | 20 | + * * 3-input NaN propagation prefers SNaN over QNaN, and then |
29 | + env->cp15.sctlr_el[1] |= SCTLR_BT0; | 21 | + * operand C over A over B (see FPProcessNaNs3() pseudocode, |
30 | /* and to the FP/Neon instructions */ | 22 | + * but note that for QEMU muladd is a * b + c, whereas for |
31 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); | 23 | + * the pseudocode function the arguments are in the order c, a, b. |
32 | /* and to the SVE instructions */ | 24 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, |
33 | diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c | 25 | * and the input NaN if it is signalling |
34 | new file mode 100644 | 26 | */ |
35 | index XXXXXXX..XXXXXXX | 27 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) |
36 | --- /dev/null | 28 | { |
37 | +++ b/tests/tcg/aarch64/bti-3.c | 29 | set_float_detect_tininess(float_tininess_before_rounding, s); |
38 | @@ -XXX,XX +XXX,XX @@ | 30 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); |
39 | +/* | 31 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); |
40 | + * BTI vs PACIASP | 32 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); |
41 | + */ | 33 | } |
42 | + | 34 | |
43 | +#include "bti-crt.inc.c" | 35 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
44 | + | ||
45 | +static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) | ||
46 | +{ | ||
47 | + uc->uc_mcontext.pc += 8; | ||
48 | + uc->uc_mcontext.pstate = 1; | ||
49 | +} | ||
50 | + | ||
51 | +#define BTYPE_1() \ | ||
52 | + asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \ | ||
53 | + : "=r"(skipped) : : "x16", "x30") | ||
54 | + | ||
55 | +#define BTYPE_2() \ | ||
56 | + asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \ | ||
57 | + : "=r"(skipped) : : "x16", "x30") | ||
58 | + | ||
59 | +#define BTYPE_3() \ | ||
60 | + asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \ | ||
61 | + : "=r"(skipped) : : "x15", "x30") | ||
62 | + | ||
63 | +#define TEST(WHICH, EXPECT) \ | ||
64 | + do { WHICH(); fail += skipped ^ EXPECT; } while (0) | ||
65 | + | ||
66 | +int main() | ||
67 | +{ | ||
68 | + int fail = 0; | ||
69 | + int skipped; | ||
70 | + | ||
71 | + /* Signal-like with SA_SIGINFO. */ | ||
72 | + signal_info(SIGILL, skip2_sigill); | ||
73 | + | ||
74 | + /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */ | ||
75 | + TEST(BTYPE_1, 0); | ||
76 | + TEST(BTYPE_2, 0); | ||
77 | + TEST(BTYPE_3, 1); | ||
78 | + | ||
79 | + return fail; | ||
80 | +} | ||
81 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
82 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
83 | --- a/tests/tcg/aarch64/Makefile.target | 37 | --- a/fpu/softfloat-specialize.c.inc |
84 | +++ b/tests/tcg/aarch64/Makefile.target | 38 | +++ b/fpu/softfloat-specialize.c.inc |
85 | @@ -XXX,XX +XXX,XX @@ endif | 39 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
86 | # BTI Tests | 40 | } |
87 | # bti-1 tests the elf notes, so we require special compiler support. | 41 | |
88 | ifneq ($(CROSS_CC_HAS_ARMV8_BTI),) | 42 | if (rule == float_3nan_prop_none) { |
89 | -AARCH64_TESTS += bti-1 | 43 | -#if defined(TARGET_ARM) |
90 | -bti-1: CFLAGS += -mbranch-protection=standard | 44 | - /* |
91 | -bti-1: LDFLAGS += -nostdlib | 45 | - * This looks different from the ARM ARM pseudocode, because the ARM ARM |
92 | +AARCH64_TESTS += bti-1 bti-3 | 46 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b |
93 | +bti-1 bti-3: CFLAGS += -mbranch-protection=standard | 47 | - */ |
94 | +bti-1 bti-3: LDFLAGS += -nostdlib | 48 | - rule = float_3nan_prop_s_cab; |
95 | endif | 49 | -#elif defined(TARGET_MIPS) |
96 | # bti-2 tests PROT_BTI, so no special compiler support required. | 50 | +#if defined(TARGET_MIPS) |
97 | AARCH64_TESTS += bti-2 | 51 | if (snan_bit_is_one(status)) { |
52 | rule = float_3nan_prop_s_abc; | ||
53 | } else { | ||
98 | -- | 54 | -- |
99 | 2.25.1 | 55 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for loongarch, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-19-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/loongarch/tcg/fpu_helper.c | 1 + | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/loongarch/tcg/fpu_helper.c | ||
15 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
17 | * case sets InvalidOp and returns the input value 'c' | ||
18 | */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); | ||
21 | } | ||
22 | |||
23 | int ieee_ex_to_loongarch(int xcpt) | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
29 | } else { | ||
30 | rule = float_3nan_prop_s_cab; | ||
31 | } | ||
32 | -#elif defined(TARGET_LOONGARCH64) | ||
33 | - rule = float_3nan_prop_s_cab; | ||
34 | #elif defined(TARGET_PPC) | ||
35 | /* | ||
36 | * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for PPC, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-20-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/ppc/cpu_init.c | 8 ++++++++ | ||
9 | fpu/softfloat-specialize.c.inc | 6 ------ | ||
10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
11 | |||
12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/ppc/cpu_init.c | ||
15 | +++ b/target/ppc/cpu_init.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | ||
20 | + /* | ||
21 | + * NaN propagation for fused multiply-add: | ||
22 | + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
23 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
24 | + * whereas QEMU labels the operands as (a * b) + c. | ||
25 | + */ | ||
26 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); | ||
27 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); | ||
28 | /* | ||
29 | * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
30 | * to return an input NaN if we have one (ie c) rather than generating | ||
31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/fpu/softfloat-specialize.c.inc | ||
34 | +++ b/fpu/softfloat-specialize.c.inc | ||
35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
36 | } else { | ||
37 | rule = float_3nan_prop_s_cab; | ||
38 | } | ||
39 | -#elif defined(TARGET_PPC) | ||
40 | - /* | ||
41 | - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
42 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
43 | - */ | ||
44 | - rule = float_3nan_prop_acb; | ||
45 | #elif defined(TARGET_S390X) | ||
46 | rule = float_3nan_prop_s_abc; | ||
47 | #elif defined(TARGET_SPARC) | ||
48 | -- | ||
49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for s390x, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-21-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/s390x/cpu.c | 1 + | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/s390x/cpu.c | ||
15 | +++ b/target/s390x/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_float_detect_tininess(float_tininess_before_rounding, | ||
18 | &env->fpu_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
20 | + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
21 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
22 | &env->fpu_status); | ||
23 | /* fall through */ | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
29 | } else { | ||
30 | rule = float_3nan_prop_s_cab; | ||
31 | } | ||
32 | -#elif defined(TARGET_S390X) | ||
33 | - rule = float_3nan_prop_s_abc; | ||
34 | #elif defined(TARGET_SPARC) | ||
35 | rule = float_3nan_prop_s_cba; | ||
36 | #elif defined(TARGET_XTENSA) | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for SPARC, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-22-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | * the CPU state struct so it won't get zeroed on reset. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
20 | + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ | ||
21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | ||
22 | /* For inf * 0 + NaN, return the input NaN */ | ||
23 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
24 | |||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | } else { | ||
31 | rule = float_3nan_prop_s_cab; | ||
32 | } | ||
33 | -#elif defined(TARGET_SPARC) | ||
34 | - rule = float_3nan_prop_s_cba; | ||
35 | #elif defined(TARGET_XTENSA) | ||
36 | if (status->use_first_nan) { | ||
37 | rule = float_3nan_prop_abc; | ||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for Arm, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-23-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/mips/fpu_helper.h | 4 ++++ | ||
9 | target/mips/msa.c | 3 +++ | ||
10 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
11 | 3 files changed, 8 insertions(+), 7 deletions(-) | ||
12 | |||
13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/mips/fpu_helper.h | ||
16 | +++ b/target/mips/fpu_helper.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
18 | { | ||
19 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); | ||
20 | FloatInfZeroNaNRule izn_rule; | ||
21 | + Float3NaNPropRule nan3_rule; | ||
22 | |||
23 | /* | ||
24 | * With nan2008, SNaNs are silenced in the usual way. | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
26 | */ | ||
27 | izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | ||
28 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
29 | + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; | ||
30 | + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); | ||
31 | + | ||
32 | } | ||
33 | |||
34 | static inline void restore_fp_status(CPUMIPSState *env) | ||
35 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/mips/msa.c | ||
38 | +++ b/target/mips/msa.c | ||
39 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
40 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, | ||
41 | &env->active_tc.msa_fp_status); | ||
42 | |||
43 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, | ||
44 | + &env->active_tc.msa_fp_status); | ||
45 | + | ||
46 | /* clear float_status exception flags */ | ||
47 | set_float_exception_flags(0, &env->active_tc.msa_fp_status); | ||
48 | |||
49 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/fpu/softfloat-specialize.c.inc | ||
52 | +++ b/fpu/softfloat-specialize.c.inc | ||
53 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
54 | } | ||
55 | |||
56 | if (rule == float_3nan_prop_none) { | ||
57 | -#if defined(TARGET_MIPS) | ||
58 | - if (snan_bit_is_one(status)) { | ||
59 | - rule = float_3nan_prop_s_abc; | ||
60 | - } else { | ||
61 | - rule = float_3nan_prop_s_cab; | ||
62 | - } | ||
63 | -#elif defined(TARGET_XTENSA) | ||
64 | +#if defined(TARGET_XTENSA) | ||
65 | if (status->use_first_nan) { | ||
66 | rule = float_3nan_prop_abc; | ||
67 | } else { | ||
68 | -- | ||
69 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the Float3NaNPropRule explicitly for xtensa, and remove the |
---|---|---|---|
2 | ifdef from pickNaNMulAdd(). | ||
2 | 3 | ||
3 | Put the block comments into the current coding style. | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-24-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/xtensa/fpu_helper.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 8 -------- | ||
10 | 2 files changed, 2 insertions(+), 8 deletions(-) | ||
4 | 11 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20220501055028.646596-19-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/helper.c | 24 +++++++++++++++--------- | ||
11 | 1 file changed, 15 insertions(+), 9 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 14 | --- a/target/xtensa/fpu_helper.c |
16 | +++ b/target/arm/helper.c | 15 | +++ b/target/xtensa/fpu_helper.c |
17 | @@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) | 16 | @@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) |
18 | return cpu_list; | 17 | set_use_first_nan(use_first, &env->fp_status); |
18 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, | ||
19 | &env->fp_status); | ||
20 | + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, | ||
21 | + &env->fp_status); | ||
19 | } | 22 | } |
20 | 23 | ||
21 | +/* | 24 | void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) |
22 | + * Private utility function for define_one_arm_cp_reg_with_opaque(): | 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
23 | + * add a single reginfo struct to the hash table. | 26 | index XXXXXXX..XXXXXXX 100644 |
24 | + */ | 27 | --- a/fpu/softfloat-specialize.c.inc |
25 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 28 | +++ b/fpu/softfloat-specialize.c.inc |
26 | void *opaque, CPState state, | 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
27 | CPSecureState secstate, | ||
28 | int crm, int opc1, int opc2, | ||
29 | const char *name) | ||
30 | { | ||
31 | - /* Private utility function for define_one_arm_cp_reg_with_opaque(): | ||
32 | - * add a single reginfo struct to the hash table. | ||
33 | - */ | ||
34 | uint32_t key; | ||
35 | ARMCPRegInfo *r2; | ||
36 | bool is64 = r->type & ARM_CP_64BIT; | ||
37 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
38 | |||
39 | isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | ||
40 | if (isbanked) { | ||
41 | - /* Register is banked (using both entries in array). | ||
42 | + /* | ||
43 | + * Register is banked (using both entries in array). | ||
44 | * Overwriting fieldoffset as the array is only used to define | ||
45 | * banked registers but later only fieldoffset is used. | ||
46 | */ | ||
47 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
48 | |||
49 | if (state == ARM_CP_STATE_AA32) { | ||
50 | if (isbanked) { | ||
51 | - /* If the register is banked then we don't need to migrate or | ||
52 | + /* | ||
53 | + * If the register is banked then we don't need to migrate or | ||
54 | * reset the 32-bit instance in certain cases: | ||
55 | * | ||
56 | * 1) If the register has both 32-bit and 64-bit instances then we | ||
57 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
58 | r2->type |= ARM_CP_ALIAS; | ||
59 | } | ||
60 | } else if ((secstate != r->secure) && !ns) { | ||
61 | - /* The register is not banked so we only want to allow migration of | ||
62 | - * the non-secure instance. | ||
63 | + /* | ||
64 | + * The register is not banked so we only want to allow migration | ||
65 | + * of the non-secure instance. | ||
66 | */ | ||
67 | r2->type |= ARM_CP_ALIAS; | ||
68 | } | ||
69 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
70 | } | ||
71 | } | 30 | } |
72 | 31 | ||
73 | - /* By convention, for wildcarded registers only the first | 32 | if (rule == float_3nan_prop_none) { |
74 | + /* | 33 | -#if defined(TARGET_XTENSA) |
75 | + * By convention, for wildcarded registers only the first | 34 | - if (status->use_first_nan) { |
76 | * entry is used for migration; the others are marked as | 35 | - rule = float_3nan_prop_abc; |
77 | * ALIAS so we don't try to transfer the register | 36 | - } else { |
78 | * multiple times. Special registers (ie NOP/WFI) are | 37 | - rule = float_3nan_prop_cba; |
79 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 38 | - } |
80 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; | 39 | -#else |
40 | rule = float_3nan_prop_abc; | ||
41 | -#endif | ||
81 | } | 42 | } |
82 | 43 | ||
83 | - /* Check that raw accesses are either forbidden or handled. Note that | 44 | assert(rule != float_3nan_prop_none); |
84 | + /* | ||
85 | + * Check that raw accesses are either forbidden or handled. Note that | ||
86 | * we can't assert this earlier because the setup of fieldoffset for | ||
87 | * banked registers has to be done first. | ||
88 | */ | ||
89 | -- | 45 | -- |
90 | 2.25.1 | 46 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for i386. We had no | ||
2 | i386-specific behaviour in the old ifdef ladder, so we were using the | ||
3 | default "prefer a then b then c" fallback; this is actually the | ||
4 | correct per-the-spec handling for i386. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-25-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/i386/tcg/fpu_helper.c | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/i386/tcg/fpu_helper.c | ||
16 | +++ b/target/i386/tcg/fpu_helper.c | ||
17 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
18 | * there are multiple input NaNs they are selected in the order a, b, c. | ||
19 | */ | ||
20 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
21 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | ||
22 | } | ||
23 | |||
24 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for HPPA, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | HPPA is the only target that was using the default branch of the | ||
5 | ifdef ladder (other targets either do not use muladd or set | ||
6 | default_nan_mode), so we can remove the ifdef fallback entirely now | ||
7 | (allowing the "rule not set" case to fall into the default of the | ||
8 | switch statement and assert). | ||
9 | |||
10 | We add a TODO note that the HPPA rule is probably wrong; this is | ||
11 | not a behavioural change for this refactoring. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20241202131347.498124-26-peter.maydell@linaro.org | ||
16 | --- | ||
17 | target/hppa/fpu_helper.c | 8 ++++++++ | ||
18 | fpu/softfloat-specialize.c.inc | 4 ---- | ||
19 | 2 files changed, 8 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/hppa/fpu_helper.c | ||
24 | +++ b/target/hppa/fpu_helper.c | ||
25 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
26 | * HPPA does note implement a CPU reset method at all... | ||
27 | */ | ||
28 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
29 | + /* | ||
30 | + * TODO: The HPPA architecture reference only documents its NaN | ||
31 | + * propagation rule for 2-operand operations. Testing on real hardware | ||
32 | + * might be necessary to confirm whether this order for muladd is correct. | ||
33 | + * Not preferring the SNaN is almost certainly incorrect as it diverges | ||
34 | + * from the documented rules for 2-operand operations. | ||
35 | + */ | ||
36 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
37 | /* For inf * 0 + NaN, return the input NaN */ | ||
38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
39 | } | ||
40 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/fpu/softfloat-specialize.c.inc | ||
43 | +++ b/fpu/softfloat-specialize.c.inc | ||
44 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
45 | } | ||
46 | } | ||
47 | |||
48 | - if (rule == float_3nan_prop_none) { | ||
49 | - rule = float_3nan_prop_abc; | ||
50 | - } | ||
51 | - | ||
52 | assert(rule != float_3nan_prop_none); | ||
53 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
54 | /* We have at least one SNaN input and should prefer it */ | ||
55 | -- | ||
56 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The use_first_nan field in float_status was an xtensa-specific way to | ||
2 | select at runtime from two different NaN propagation rules. Now that | ||
3 | xtensa is using the target-agnostic NaN propagation rule selection | ||
4 | that we've just added, we can remove use_first_nan, because there is | ||
5 | no longer any code that reads it. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20241202131347.498124-27-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/fpu/softfloat-helpers.h | 5 ----- | ||
12 | include/fpu/softfloat-types.h | 1 - | ||
13 | target/xtensa/fpu_helper.c | 1 - | ||
14 | 3 files changed, 7 deletions(-) | ||
15 | |||
16 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/fpu/softfloat-helpers.h | ||
19 | +++ b/include/fpu/softfloat-helpers.h | ||
20 | @@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status) | ||
21 | status->snan_bit_is_one = val; | ||
22 | } | ||
23 | |||
24 | -static inline void set_use_first_nan(bool val, float_status *status) | ||
25 | -{ | ||
26 | - status->use_first_nan = val; | ||
27 | -} | ||
28 | - | ||
29 | static inline void set_no_signaling_nans(bool val, float_status *status) | ||
30 | { | ||
31 | status->no_signaling_nans = val; | ||
32 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/include/fpu/softfloat-types.h | ||
35 | +++ b/include/fpu/softfloat-types.h | ||
36 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
37 | * softfloat-specialize.inc.c) | ||
38 | */ | ||
39 | bool snan_bit_is_one; | ||
40 | - bool use_first_nan; | ||
41 | bool no_signaling_nans; | ||
42 | /* should overflowed results subtract re_bias to its exponent? */ | ||
43 | bool rebias_overflow; | ||
44 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/xtensa/fpu_helper.c | ||
47 | +++ b/target/xtensa/fpu_helper.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static const struct { | ||
49 | |||
50 | void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) | ||
51 | { | ||
52 | - set_use_first_nan(use_first, &env->fp_status); | ||
53 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, | ||
54 | &env->fp_status); | ||
55 | set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, | ||
56 | -- | ||
57 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) | ||
2 | to get the NaN bit pattern to reset the FPU registers. This | ||
3 | works because it happens that our implementation of | ||
4 | floatx80_default_nan() doesn't actually look at the float_status | ||
5 | pointer except for TARGET_MIPS. However, this isn't guaranteed, | ||
6 | and to be able to remove the ifdef in floatx80_default_nan() | ||
7 | we're going to need a real float_status here. | ||
1 | 8 | ||
9 | Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status | ||
10 | earlier, and thus can pass it to floatx80_default_nan(). | ||
11 | |||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20241202131347.498124-28-peter.maydell@linaro.org | ||
15 | --- | ||
16 | target/m68k/cpu.c | 12 +++++++----- | ||
17 | 1 file changed, 7 insertions(+), 5 deletions(-) | ||
18 | |||
19 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/m68k/cpu.c | ||
22 | +++ b/target/m68k/cpu.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
24 | CPUState *cs = CPU(obj); | ||
25 | M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); | ||
26 | CPUM68KState *env = cpu_env(cs); | ||
27 | - floatx80 nan = floatx80_default_nan(NULL); | ||
28 | + floatx80 nan; | ||
29 | int i; | ||
30 | |||
31 | if (mcc->parent_phases.hold) { | ||
32 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
33 | #else | ||
34 | cpu_m68k_set_sr(env, SR_S | SR_I); | ||
35 | #endif | ||
36 | - for (i = 0; i < 8; i++) { | ||
37 | - env->fregs[i].d = nan; | ||
38 | - } | ||
39 | - cpu_m68k_set_fpcr(env, 0); | ||
40 | /* | ||
41 | * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL | ||
42 | * 3.4 FLOATING-POINT INSTRUCTION DETAILS | ||
43 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
44 | * preceding paragraph for nonsignaling NaNs. | ||
45 | */ | ||
46 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
47 | + | ||
48 | + nan = floatx80_default_nan(&env->fp_status); | ||
49 | + for (i = 0; i < 8; i++) { | ||
50 | + env->fregs[i].d = nan; | ||
51 | + } | ||
52 | + cpu_m68k_set_fpcr(env, 0); | ||
53 | env->fpsr = 0; | ||
54 | |||
55 | /* TODO: We should set PC from the interrupt vector. */ | ||
56 | -- | ||
57 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | We create our 128-bit default NaN by calling parts64_default_nan() | ||
2 | and then adjusting the result. We can do the same trick for creating | ||
3 | the floatx80 default NaN, which lets us drop a target ifdef. | ||
1 | 4 | ||
5 | floatx80 is used only by: | ||
6 | i386 | ||
7 | m68k | ||
8 | arm nwfpe old floating-point emulation emulation support | ||
9 | (which is essentially dead, especially the parts involving floatx80) | ||
10 | PPC (only in the xsrqpxp instruction, which just rounds an input | ||
11 | value by converting to floatx80 and back, so will never generate | ||
12 | the default NaN) | ||
13 | |||
14 | The floatx80 default NaN as currently implemented is: | ||
15 | m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 | ||
16 | i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 | ||
17 | |||
18 | These are the same as the parts64_default_nan for these architectures. | ||
19 | |||
20 | This is technically a possible behaviour change for arm linux-user | ||
21 | nwfpe emulation emulation, because the default NaN will now have the | ||
22 | sign bit clear. But we were already generating a different floatx80 | ||
23 | default NaN from the real kernel emulation we are supposedly | ||
24 | following, which appears to use an all-bits-1 value: | ||
25 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 | ||
26 | |||
27 | This won't affect the only "real" use of the nwfpe emulation, which | ||
28 | is ancient binaries that used it as part of the old floating point | ||
29 | calling convention; that only uses loads and stores of 32 and 64 bit | ||
30 | floats, not any of the floatx80 behaviour the original hardware had. | ||
31 | We also get the nwfpe float64 default NaN value wrong: | ||
32 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 | ||
33 | so if we ever cared about this obscure corner the right fix would be | ||
34 | to correct that so nwfpe used its own default-NaN setting rather | ||
35 | than the Arm VFP one. | ||
36 | |||
37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
38 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
39 | Message-id: 20241202131347.498124-29-peter.maydell@linaro.org | ||
40 | --- | ||
41 | fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- | ||
42 | 1 file changed, 10 insertions(+), 10 deletions(-) | ||
43 | |||
44 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/fpu/softfloat-specialize.c.inc | ||
47 | +++ b/fpu/softfloat-specialize.c.inc | ||
48 | @@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) | ||
49 | floatx80 floatx80_default_nan(float_status *status) | ||
50 | { | ||
51 | floatx80 r; | ||
52 | + /* | ||
53 | + * Extrapolate from the choices made by parts64_default_nan to fill | ||
54 | + * in the floatx80 format. We assume that floatx80's explicit | ||
55 | + * integer bit is always set (this is true for i386 and m68k, | ||
56 | + * which are the only real users of this format). | ||
57 | + */ | ||
58 | + FloatParts64 p64; | ||
59 | + parts64_default_nan(&p64, status); | ||
60 | |||
61 | - /* None of the targets that have snan_bit_is_one use floatx80. */ | ||
62 | - assert(!snan_bit_is_one(status)); | ||
63 | -#if defined(TARGET_M68K) | ||
64 | - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); | ||
65 | - r.high = 0x7FFF; | ||
66 | -#else | ||
67 | - /* X86 */ | ||
68 | - r.low = UINT64_C(0xC000000000000000); | ||
69 | - r.high = 0xFFFF; | ||
70 | -#endif | ||
71 | + r.high = 0x7FFF | (p64.sign << 15); | ||
72 | + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; | ||
73 | return r; | ||
74 | } | ||
75 | |||
76 | -- | ||
77 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass | ||
2 | a zero-initialized float_status struct to float32_is_quiet_nan() and | ||
3 | float64_is_quiet_nan(), with the cryptic comment "for | ||
4 | snan_bit_is_one". | ||
1 | 5 | ||
6 | This pattern appears to have been copied from target/riscv, where it | ||
7 | is used because the functions there do not have ready access to the | ||
8 | CPU state struct. The comment presumably refers to the fact that the | ||
9 | main reason the is_quiet_nan() functions want the float_state is | ||
10 | because they want to know about the snan_bit_is_one config. | ||
11 | |||
12 | In the loongarch helpers, though, we have the CPU state struct | ||
13 | to hand. Use the usual env->fp_status here. This avoids our needing | ||
14 | to track that we need to update the initializer of the local | ||
15 | float_status structs when the core softfloat code adds new | ||
16 | options for targets to configure their behaviour. | ||
17 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20241202131347.498124-30-peter.maydell@linaro.org | ||
21 | --- | ||
22 | target/loongarch/tcg/fpu_helper.c | 6 ++---- | ||
23 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
24 | |||
25 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/loongarch/tcg/fpu_helper.c | ||
28 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
29 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) | ||
30 | } else if (float32_is_zero_or_denormal(f)) { | ||
31 | return sign ? 1 << 4 : 1 << 8; | ||
32 | } else if (float32_is_any_nan(f)) { | ||
33 | - float_status s = { }; /* for snan_bit_is_one */ | ||
34 | - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
35 | + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
36 | } else { | ||
37 | return sign ? 1 << 3 : 1 << 7; | ||
38 | } | ||
39 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) | ||
40 | } else if (float64_is_zero_or_denormal(f)) { | ||
41 | return sign ? 1 << 4 : 1 << 8; | ||
42 | } else if (float64_is_any_nan(f)) { | ||
43 | - float_status s = { }; /* for snan_bit_is_one */ | ||
44 | - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
45 | + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
46 | } else { | ||
47 | return sign ? 1 << 3 : 1 << 7; | ||
48 | } | ||
49 | -- | ||
50 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the frem helper, we have a local float_status because we want to | ||
2 | execute the floatx80_div() with a custom rounding mode. Instead of | ||
3 | zero-initializing the local float_status and then having to set it up | ||
4 | with the m68k standard behaviour (including the NaN propagation rule | ||
5 | and copying the rounding precision from env->fp_status), initialize | ||
6 | it as a complete copy of env->fp_status. This will avoid our having | ||
7 | to add new code in this function for every new config knob we add | ||
8 | to fp_status. | ||
1 | 9 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-31-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/m68k/fpu_helper.c | 6 ++---- | ||
15 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
16 | |||
17 | diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/m68k/fpu_helper.c | ||
20 | +++ b/target/m68k/fpu_helper.c | ||
21 | @@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) | ||
22 | |||
23 | fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); | ||
24 | if (!floatx80_is_any_nan(fp_rem)) { | ||
25 | - float_status fp_status = { }; | ||
26 | + /* Use local temporary fp_status to set different rounding mode */ | ||
27 | + float_status fp_status = env->fp_status; | ||
28 | uint32_t quotient; | ||
29 | int sign; | ||
30 | |||
31 | /* Calculate quotient directly using round to nearest mode */ | ||
32 | - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); | ||
33 | set_float_rounding_mode(float_round_nearest_even, &fp_status); | ||
34 | - set_floatx80_rounding_precision( | ||
35 | - get_floatx80_rounding_precision(&env->fp_status), &fp_status); | ||
36 | fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); | ||
37 | |||
38 | sign = extractFloatx80Sign(fp_quot.d); | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion | ||
2 | from float64 to floatx80 using a scratch float_status, because we | ||
3 | don't want the conversion to affect the CPU's floating point exception | ||
4 | status. Currently we use a zero-initialized float_status. This will | ||
5 | get steadily more awkward as we add config knobs to float_status | ||
6 | that the target must initialize. Avoid having to add any of that | ||
7 | configuration here by instead initializing our local float_status | ||
8 | from the env->fp_status. | ||
1 | 9 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-32-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/m68k/helper.c | 6 ++++-- | ||
15 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
16 | |||
17 | diff --git a/target/m68k/helper.c b/target/m68k/helper.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/m68k/helper.c | ||
20 | +++ b/target/m68k/helper.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) | ||
22 | CPUM68KState *env = &cpu->env; | ||
23 | |||
24 | if (n < 8) { | ||
25 | - float_status s = {}; | ||
26 | + /* Use scratch float_status so any exceptions don't change CPU state */ | ||
27 | + float_status s = env->fp_status; | ||
28 | return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); | ||
29 | } | ||
30 | switch (n) { | ||
31 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) | ||
32 | CPUM68KState *env = &cpu->env; | ||
33 | |||
34 | if (n < 8) { | ||
35 | - float_status s = {}; | ||
36 | + /* Use scratch float_status so any exceptions don't change CPU state */ | ||
37 | + float_status s = env->fp_status; | ||
38 | env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); | ||
39 | return 8; | ||
40 | } | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the helper functions flcmps and flcmpd we use a scratch float_status | ||
2 | so that we don't change the CPU state if the comparison raises any | ||
3 | floating point exception flags. Instead of zero-initializing this | ||
4 | scratch float_status, initialize it as a copy of env->fp_status. This | ||
5 | avoids the need to explicitly initialize settings like the NaN | ||
6 | propagation rule or others we might add to softfloat in future. | ||
1 | 7 | ||
8 | To do this we need to pass the CPU env pointer in to the helper. | ||
9 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-33-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/sparc/helper.h | 4 ++-- | ||
15 | target/sparc/fop_helper.c | 8 ++++---- | ||
16 | target/sparc/translate.c | 4 ++-- | ||
17 | 3 files changed, 8 insertions(+), 8 deletions(-) | ||
18 | |||
19 | diff --git a/target/sparc/helper.h b/target/sparc/helper.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/sparc/helper.h | ||
22 | +++ b/target/sparc/helper.h | ||
23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) | ||
24 | DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) | ||
25 | DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) | ||
26 | DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) | ||
27 | -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) | ||
28 | -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) | ||
29 | +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) | ||
30 | +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) | ||
31 | DEF_HELPER_2(raise_exception, noreturn, env, int) | ||
32 | |||
33 | DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
34 | diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/sparc/fop_helper.c | ||
37 | +++ b/target/sparc/fop_helper.c | ||
38 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) | ||
39 | return finish_fcmp(env, r, GETPC()); | ||
40 | } | ||
41 | |||
42 | -uint32_t helper_flcmps(float32 src1, float32 src2) | ||
43 | +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) | ||
44 | { | ||
45 | /* | ||
46 | * FLCMP never raises an exception nor modifies any FSR fields. | ||
47 | * Perform the comparison with a dummy fp environment. | ||
48 | */ | ||
49 | - float_status discard = { }; | ||
50 | + float_status discard = env->fp_status; | ||
51 | FloatRelation r; | ||
52 | |||
53 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); | ||
54 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2) | ||
55 | g_assert_not_reached(); | ||
56 | } | ||
57 | |||
58 | -uint32_t helper_flcmpd(float64 src1, float64 src2) | ||
59 | +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) | ||
60 | { | ||
61 | - float_status discard = { }; | ||
62 | + float_status discard = env->fp_status; | ||
63 | FloatRelation r; | ||
64 | |||
65 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); | ||
66 | diff --git a/target/sparc/translate.c b/target/sparc/translate.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/sparc/translate.c | ||
69 | +++ b/target/sparc/translate.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) | ||
71 | |||
72 | src1 = gen_load_fpr_F(dc, a->rs1); | ||
73 | src2 = gen_load_fpr_F(dc, a->rs2); | ||
74 | - gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); | ||
75 | + gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2); | ||
76 | return advance_pc(dc); | ||
77 | } | ||
78 | |||
79 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) | ||
80 | |||
81 | src1 = gen_load_fpr_D(dc, a->rs1); | ||
82 | src2 = gen_load_fpr_D(dc, a->rs2); | ||
83 | - gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); | ||
84 | + gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); | ||
85 | return advance_pc(dc); | ||
86 | } | ||
87 | |||
88 | -- | ||
89 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the helper_compute_fprf functions, we pass a dummy float_status | ||
2 | in to the is_signaling_nan() function. This is unnecessary, because | ||
3 | we have convenient access to the CPU env pointer here and that | ||
4 | is already set up with the correct values for the snan_bit_is_one | ||
5 | and no_signaling_nans config settings. is_signaling_nan() doesn't | ||
6 | ever update the fp_status with any exception flags, so there is | ||
7 | no reason not to use env->fp_status here. | ||
1 | 8 | ||
9 | Use env->fp_status instead of the dummy fp_status. | ||
10 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20241202131347.498124-34-peter.maydell@linaro.org | ||
14 | --- | ||
15 | target/ppc/fpu_helper.c | 3 +-- | ||
16 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
17 | |||
18 | diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/ppc/fpu_helper.c | ||
21 | +++ b/target/ppc/fpu_helper.c | ||
22 | @@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ | ||
23 | } else if (tp##_is_infinity(arg)) { \ | ||
24 | fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ | ||
25 | } else { \ | ||
26 | - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ | ||
27 | - if (tp##_is_signaling_nan(arg, &dummy)) { \ | ||
28 | + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ | ||
29 | fprf = 0x00 << FPSCR_FPRF; \ | ||
30 | } else { \ | ||
31 | fprf = 0x11 << FPSCR_FPRF; \ | ||
32 | -- | ||
33 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Bool is a more appropriate type for these variables. | 3 | Now that float_status has a bunch of fp parameters, |
4 | it is easier to copy an existing structure than create | ||
5 | one from scratch. Begin by copying the structure that | ||
6 | corresponds to the FPSR and make only the adjustments | ||
7 | required for BFloat16 semantics. | ||
4 | 8 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20220501055028.646596-16-richard.henderson@linaro.org | 12 | Message-id: 20241203203949.483774-2-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 14 | --- |
10 | target/arm/helper.c | 4 ++-- | 15 | target/arm/tcg/vec_helper.c | 20 +++++++------------- |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 16 | 1 file changed, 7 insertions(+), 13 deletions(-) |
12 | 17 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 18 | diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c |
14 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 20 | --- a/target/arm/tcg/vec_helper.c |
16 | +++ b/target/arm/helper.c | 21 | +++ b/target/arm/tcg/vec_helper.c |
17 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 22 | @@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) |
23 | * no effect on AArch32 instructions. | ||
18 | */ | 24 | */ |
19 | uint32_t key; | 25 | bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; |
20 | ARMCPRegInfo *r2; | 26 | - *statusp = (float_status){ |
21 | - int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | 27 | - .tininess_before_rounding = float_tininess_before_rounding, |
22 | - int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; | 28 | - .float_rounding_mode = float_round_to_odd_inf, |
23 | + bool is64 = r->type & ARM_CP_64BIT; | 29 | - .flush_to_zero = true, |
24 | + bool ns = secstate & ARM_CP_SECSTATE_NS; | 30 | - .flush_inputs_to_zero = true, |
25 | int cp = r->cp; | 31 | - .default_nan_mode = true, |
26 | size_t name_len; | 32 | - }; |
33 | + | ||
34 | + *statusp = env->vfp.fp_status; | ||
35 | + set_default_nan_mode(true, statusp); | ||
36 | |||
37 | if (ebf) { | ||
38 | - float_status *fpst = &env->vfp.fp_status; | ||
39 | - set_flush_to_zero(get_flush_to_zero(fpst), statusp); | ||
40 | - set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); | ||
41 | - set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); | ||
42 | - | ||
43 | /* EBF=1 needs to do a step with round-to-odd semantics */ | ||
44 | *oddstatusp = *statusp; | ||
45 | set_float_rounding_mode(float_round_to_odd, oddstatusp); | ||
46 | + } else { | ||
47 | + set_flush_to_zero(true, statusp); | ||
48 | + set_flush_inputs_to_zero(true, statusp); | ||
49 | + set_float_rounding_mode(float_round_to_odd_inf, statusp); | ||
50 | } | ||
51 | - | ||
52 | return ebf; | ||
53 | } | ||
27 | 54 | ||
28 | -- | 55 | -- |
29 | 2.25.1 | 56 | 2.34.1 |
57 | |||
58 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Currently we hardcode the default NaN value in parts64_default_nan() |
---|---|---|---|
2 | using a compile-time ifdef ladder. This is awkward for two cases: | ||
3 | * for single-QEMU-binary we can't hard-code target-specifics like this | ||
4 | * for Arm FEAT_AFP the default NaN value depends on FPCR.AH | ||
5 | (specifically the sign bit is different) | ||
2 | 6 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Add a field to float_status to specify the default NaN value; fall |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | back to the old ifdef behaviour if these are not set. |
5 | Message-id: 20220501055028.646596-24-richard.henderson@linaro.org | 9 | |
10 | The default NaN value is specified by setting a uint8_t to a | ||
11 | pattern corresponding to the sign and upper fraction parts of | ||
12 | the NaN; the lower bits of the fraction are set from bit 0 of | ||
13 | the pattern. | ||
14 | |||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20241202131347.498124-35-peter.maydell@linaro.org | ||
7 | --- | 18 | --- |
8 | target/arm/cpu.h | 15 +++++++++++++++ | 19 | include/fpu/softfloat-helpers.h | 11 +++++++ |
9 | 1 file changed, 15 insertions(+) | 20 | include/fpu/softfloat-types.h | 10 ++++++ |
21 | fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- | ||
22 | 3 files changed, 54 insertions(+), 22 deletions(-) | ||
10 | 23 | ||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 24 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h |
12 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/cpu.h | 26 | --- a/include/fpu/softfloat-helpers.h |
14 | +++ b/target/arm/cpu.h | 27 | +++ b/include/fpu/softfloat-helpers.h |
15 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) | 28 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, |
16 | return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; | 29 | status->float_infzeronan_rule = rule; |
17 | } | 30 | } |
18 | 31 | ||
19 | +static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) | 32 | +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, |
33 | + float_status *status) | ||
20 | +{ | 34 | +{ |
21 | + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; | 35 | + status->default_nan_pattern = dnan_pattern; |
22 | +} | 36 | +} |
23 | + | 37 | + |
24 | /* | 38 | static inline void set_flush_to_zero(bool val, float_status *status) |
25 | * 64-bit feature tests via id registers. | 39 | { |
26 | */ | 40 | status->flush_to_zero = val; |
27 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) | 41 | @@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status |
28 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; | 42 | return status->float_infzeronan_rule; |
29 | } | 43 | } |
30 | 44 | ||
31 | +static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) | 45 | +static inline uint8_t get_float_default_nan_pattern(float_status *status) |
32 | +{ | 46 | +{ |
33 | + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; | 47 | + return status->default_nan_pattern; |
34 | +} | 48 | +} |
35 | + | 49 | + |
36 | static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) | 50 | static inline bool get_flush_to_zero(float_status *status) |
37 | { | 51 | { |
38 | return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; | 52 | return status->flush_to_zero; |
39 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) | 53 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h |
40 | return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); | 54 | index XXXXXXX..XXXXXXX 100644 |
41 | } | 55 | --- a/include/fpu/softfloat-types.h |
42 | 56 | +++ b/include/fpu/softfloat-types.h | |
43 | +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) | 57 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { |
44 | +{ | 58 | /* should denormalised inputs go to zero and set the input_denormal flag? */ |
45 | + return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); | 59 | bool flush_inputs_to_zero; |
46 | +} | 60 | bool default_nan_mode; |
61 | + /* | ||
62 | + * The pattern to use for the default NaN. Here the high bit specifies | ||
63 | + * the default NaN's sign bit, and bits 6..0 specify the high bits of the | ||
64 | + * fractional part. The low bits of the fractional part are copies of bit 0. | ||
65 | + * The exponent of the default NaN is (as for any NaN) always all 1s. | ||
66 | + * Note that a value of 0 here is not a valid NaN. The target must set | ||
67 | + * this to the correct non-zero value, or we will assert when trying to | ||
68 | + * create a default NaN. | ||
69 | + */ | ||
70 | + uint8_t default_nan_pattern; | ||
71 | /* | ||
72 | * The flags below are not used on all specializations and may | ||
73 | * constant fold away (see snan_bit_is_one()/no_signalling_nans() in | ||
74 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/fpu/softfloat-specialize.c.inc | ||
77 | +++ b/fpu/softfloat-specialize.c.inc | ||
78 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
79 | { | ||
80 | bool sign = 0; | ||
81 | uint64_t frac; | ||
82 | + uint8_t dnan_pattern = status->default_nan_pattern; | ||
83 | |||
84 | + if (dnan_pattern == 0) { | ||
85 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
86 | - /* !snan_bit_is_one, set all bits */ | ||
87 | - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; | ||
88 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
89 | + /* Sign bit clear, all frac bits set */ | ||
90 | + dnan_pattern = 0b01111111; | ||
91 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
92 | || defined(TARGET_MICROBLAZE) | ||
93 | - /* !snan_bit_is_one, set sign and msb */ | ||
94 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
95 | - sign = 1; | ||
96 | + /* Sign bit set, most significant frac bit set */ | ||
97 | + dnan_pattern = 0b11000000; | ||
98 | #elif defined(TARGET_HPPA) | ||
99 | - /* snan_bit_is_one, set msb-1. */ | ||
100 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); | ||
101 | + /* Sign bit clear, msb-1 frac bit set */ | ||
102 | + dnan_pattern = 0b00100000; | ||
103 | #elif defined(TARGET_HEXAGON) | ||
104 | - sign = 1; | ||
105 | - frac = ~0ULL; | ||
106 | + /* Sign bit set, all frac bits set. */ | ||
107 | + dnan_pattern = 0b11111111; | ||
108 | #else | ||
109 | - /* | ||
110 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
111 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
112 | - * do not have floating-point. | ||
113 | - */ | ||
114 | - if (snan_bit_is_one(status)) { | ||
115 | - /* set all bits other than msb */ | ||
116 | - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; | ||
117 | - } else { | ||
118 | - /* set msb */ | ||
119 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
120 | - } | ||
121 | + /* | ||
122 | + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
123 | + * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
124 | + * do not have floating-point. | ||
125 | + */ | ||
126 | + if (snan_bit_is_one(status)) { | ||
127 | + /* sign bit clear, set all frac bits other than msb */ | ||
128 | + dnan_pattern = 0b00111111; | ||
129 | + } else { | ||
130 | + /* sign bit clear, set frac msb */ | ||
131 | + dnan_pattern = 0b01000000; | ||
132 | + } | ||
133 | #endif | ||
134 | + } | ||
135 | + assert(dnan_pattern != 0); | ||
47 | + | 136 | + |
48 | /* | 137 | + sign = dnan_pattern >> 7; |
49 | * Forward to the above feature tests given an ARMCPU pointer. | 138 | + /* |
50 | */ | 139 | + * Place default_nan_pattern [6:0] into bits [62:56], |
140 | + * and replecate bit [0] down into [55:0] | ||
141 | + */ | ||
142 | + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); | ||
143 | + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); | ||
144 | |||
145 | *p = (FloatParts64) { | ||
146 | .cls = float_class_qnan, | ||
51 | -- | 147 | -- |
52 | 2.25.1 | 148 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for the tests/fp code. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-36-peter.maydell@linaro.org | ||
6 | --- | ||
7 | tests/fp/fp-bench.c | 1 + | ||
8 | tests/fp/fp-test-log2.c | 1 + | ||
9 | tests/fp/fp-test.c | 1 + | ||
10 | 3 files changed, 3 insertions(+) | ||
11 | |||
12 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/tests/fp/fp-bench.c | ||
15 | +++ b/tests/fp/fp-bench.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
18 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
20 | + set_float_default_nan_pattern(0b01000000, &soft_status); | ||
21 | |||
22 | f = bench_funcs[operation][precision]; | ||
23 | g_assert(f); | ||
24 | diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/tests/fp/fp-test-log2.c | ||
27 | +++ b/tests/fp/fp-test-log2.c | ||
28 | @@ -XXX,XX +XXX,XX @@ int main(int ac, char **av) | ||
29 | int i; | ||
30 | |||
31 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
32 | + set_float_default_nan_pattern(0b01000000, &qsf); | ||
33 | set_float_rounding_mode(float_round_nearest_even, &qsf); | ||
34 | |||
35 | test.d = 0.0; | ||
36 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/tests/fp/fp-test.c | ||
39 | +++ b/tests/fp/fp-test.c | ||
40 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
41 | */ | ||
42 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
43 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); | ||
44 | + set_float_default_nan_pattern(0b01000000, &qsf); | ||
45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
46 | |||
47 | genCases_setLevel(test_level); | ||
48 | -- | ||
49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-37-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/microblaze/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/microblaze/cpu.c | ||
15 | +++ b/target/microblaze/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | * this architecture. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
20 | + /* Default NaN: sign bit set, most significant frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | ||
22 | |||
23 | #if defined(CONFIG_USER_ONLY) | ||
24 | /* start in user mode with interrupts enabled. */ | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
31 | /* Sign bit clear, all frac bits set */ | ||
32 | dnan_pattern = 0b01111111; | ||
33 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
34 | - || defined(TARGET_MICROBLAZE) | ||
35 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) | ||
36 | /* Sign bit set, most significant frac bit set */ | ||
37 | dnan_pattern = 0b11000000; | ||
38 | #elif defined(TARGET_HPPA) | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-38-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/i386/tcg/fpu_helper.c | 4 ++++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 --- | ||
10 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/i386/tcg/fpu_helper.c | ||
15 | +++ b/target/i386/tcg/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
17 | */ | ||
18 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
19 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | ||
20 | + /* Default NaN: sign bit set, most significant frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | ||
22 | + set_float_default_nan_pattern(0b11000000, &env->mmx_status); | ||
23 | + set_float_default_nan_pattern(0b11000000, &env->sse_status); | ||
24 | } | ||
25 | |||
26 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/fpu/softfloat-specialize.c.inc | ||
30 | +++ b/fpu/softfloat-specialize.c.inc | ||
31 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
32 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
33 | /* Sign bit clear, all frac bits set */ | ||
34 | dnan_pattern = 0b01111111; | ||
35 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) | ||
36 | - /* Sign bit set, most significant frac bit set */ | ||
37 | - dnan_pattern = 0b11000000; | ||
38 | #elif defined(TARGET_HPPA) | ||
39 | /* Sign bit clear, msb-1 frac bit set */ | ||
40 | dnan_pattern = 0b00100000; | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-39-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/hppa/fpu_helper.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 --- | ||
10 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/hppa/fpu_helper.c | ||
15 | +++ b/target/hppa/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
18 | /* For inf * 0 + NaN, return the input NaN */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + /* Default NaN: sign bit clear, msb-1 frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b00100000, &env->fp_status); | ||
22 | } | ||
23 | |||
24 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
31 | /* Sign bit clear, all frac bits set */ | ||
32 | dnan_pattern = 0b01111111; | ||
33 | -#elif defined(TARGET_HPPA) | ||
34 | - /* Sign bit clear, msb-1 frac bit set */ | ||
35 | - dnan_pattern = 0b00100000; | ||
36 | #elif defined(TARGET_HEXAGON) | ||
37 | /* Sign bit set, all frac bits set. */ | ||
38 | dnan_pattern = 0b11111111; | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for the alpha target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-40-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/alpha/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/alpha/cpu.c | ||
13 | +++ b/target/alpha/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj) | ||
15 | * operand in Fa. That is float_2nan_prop_ba. | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
18 | + /* Default NaN: sign bit clear, msb frac bit set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | #if defined(CONFIG_USER_ONLY) | ||
21 | env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; | ||
22 | cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the default NaN pattern explicitly for the arm target. |
---|---|---|---|
2 | This includes setting it for the old linux-user nwfpe emulation. | ||
3 | For nwfpe, our default doesn't match the real kernel, but we | ||
4 | avoid making a behaviour change in this commit. | ||
2 | 5 | ||
3 | Cast the uint32_t key into a gpointer directly, which | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | allows us to avoid allocating storage for each key. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20241202131347.498124-41-peter.maydell@linaro.org | ||
9 | --- | ||
10 | linux-user/arm/nwfpe/fpa11.c | 5 +++++ | ||
11 | target/arm/cpu.c | 2 ++ | ||
12 | 2 files changed, 7 insertions(+) | ||
5 | 13 | ||
6 | Use g_hash_table_lookup when we already have a gpointer | 14 | diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c |
7 | (e.g. for callbacks like count_cpreg), or when using | 15 | index XXXXXXX..XXXXXXX 100644 |
8 | get_arm_cp_reginfo would require casting away const. | 16 | --- a/linux-user/arm/nwfpe/fpa11.c |
9 | 17 | +++ b/linux-user/arm/nwfpe/fpa11.c | |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 18 | @@ -XXX,XX +XXX,XX @@ void resetFPA11(void) |
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | * this late date. |
12 | Message-id: 20220501055028.646596-12-richard.henderson@linaro.org | 20 | */ |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); |
14 | --- | 22 | + /* |
15 | target/arm/cpu.c | 4 ++-- | 23 | + * Use the same default NaN value as Arm VFP. This doesn't match |
16 | target/arm/gdbstub.c | 2 +- | 24 | + * the Linux kernel's nwfpe emulation, which uses an all-1s value. |
17 | target/arm/helper.c | 41 ++++++++++++++++++----------------------- | 25 | + */ |
18 | 3 files changed, 21 insertions(+), 26 deletions(-) | 26 | + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); |
19 | 27 | } | |
28 | |||
29 | void SetRoundingMode(const unsigned int opcode) | ||
20 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
21 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/cpu.c | 32 | --- a/target/arm/cpu.c |
23 | +++ b/target/arm/cpu.c | 33 | +++ b/target/arm/cpu.c |
24 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj) | 34 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
25 | ARMCPU *cpu = ARM_CPU(obj); | 35 | * the pseudocode function the arguments are in the order c, a, b. |
26 | 36 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, | |
27 | cpu_set_cpustate_pointers(cpu); | 37 | * and the input NaN if it is signalling |
28 | - cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, | 38 | + * * Default NaN has sign bit clear, msb frac bit set |
29 | - g_free, cpreg_hashtable_data_destroy); | 39 | */ |
30 | + cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, | 40 | static void arm_set_default_fp_behaviours(float_status *s) |
31 | + NULL, cpreg_hashtable_data_destroy); | ||
32 | |||
33 | QLIST_INIT(&cpu->pre_el_change_hooks); | ||
34 | QLIST_INIT(&cpu->el_change_hooks); | ||
35 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/gdbstub.c | ||
38 | +++ b/target/arm/gdbstub.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, | ||
40 | static void arm_register_sysreg_for_xml(gpointer key, gpointer value, | ||
41 | gpointer p) | ||
42 | { | 41 | { |
43 | - uint32_t ri_key = *(uint32_t *)key; | 42 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) |
44 | + uint32_t ri_key = (uintptr_t)key; | 43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); |
45 | ARMCPRegInfo *ri = value; | 44 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); |
46 | RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p; | 45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); |
47 | GString *s = param->s; | 46 | + set_float_default_nan_pattern(0b01000000, s); |
48 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/helper.c | ||
51 | +++ b/target/arm/helper.c | ||
52 | @@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu) | ||
53 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | ||
54 | { | ||
55 | ARMCPU *cpu = opaque; | ||
56 | - uint64_t regidx; | ||
57 | - const ARMCPRegInfo *ri; | ||
58 | - | ||
59 | - regidx = *(uint32_t *)key; | ||
60 | - ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | ||
61 | + uint32_t regidx = (uintptr_t)key; | ||
62 | + const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | ||
63 | |||
64 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { | ||
65 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); | ||
66 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque) | ||
67 | static void count_cpreg(gpointer key, gpointer opaque) | ||
68 | { | ||
69 | ARMCPU *cpu = opaque; | ||
70 | - uint64_t regidx; | ||
71 | const ARMCPRegInfo *ri; | ||
72 | |||
73 | - regidx = *(uint32_t *)key; | ||
74 | - ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | ||
75 | + ri = g_hash_table_lookup(cpu->cp_regs, key); | ||
76 | |||
77 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { | ||
78 | cpu->cpreg_array_len++; | ||
79 | @@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque) | ||
80 | |||
81 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | ||
82 | { | ||
83 | - uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); | ||
84 | - uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | ||
85 | + uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a); | ||
86 | + uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b); | ||
87 | |||
88 | if (aidx > bidx) { | ||
89 | return 1; | ||
90 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
91 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | ||
92 | const struct E2HAlias *a = &aliases[i]; | ||
93 | ARMCPRegInfo *src_reg, *dst_reg, *new_reg; | ||
94 | - uint32_t *new_key; | ||
95 | bool ok; | ||
96 | |||
97 | if (a->feature && !a->feature(&cpu->isar)) { | ||
98 | continue; | ||
99 | } | ||
100 | |||
101 | - src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key); | ||
102 | - dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key); | ||
103 | + src_reg = g_hash_table_lookup(cpu->cp_regs, | ||
104 | + (gpointer)(uintptr_t)a->src_key); | ||
105 | + dst_reg = g_hash_table_lookup(cpu->cp_regs, | ||
106 | + (gpointer)(uintptr_t)a->dst_key); | ||
107 | g_assert(src_reg != NULL); | ||
108 | g_assert(dst_reg != NULL); | ||
109 | |||
110 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | ||
111 | |||
112 | /* Create alias before redirection so we dup the right data. */ | ||
113 | new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | ||
114 | - new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | ||
115 | |||
116 | new_reg->name = a->new_name; | ||
117 | new_reg->type |= ARM_CP_ALIAS; | ||
118 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | ||
119 | new_reg->access &= PL2_RW | PL3_RW; | ||
120 | |||
121 | - ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | ||
122 | + ok = g_hash_table_insert(cpu->cp_regs, | ||
123 | + (gpointer)(uintptr_t)a->new_key, new_reg); | ||
124 | g_assert(ok); | ||
125 | |||
126 | src_reg->opaque = dst_reg; | ||
127 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
128 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | ||
129 | * add a single reginfo struct to the hash table. | ||
130 | */ | ||
131 | - uint32_t *key = g_new(uint32_t, 1); | ||
132 | + uint32_t key; | ||
133 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | ||
134 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | ||
135 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; | ||
136 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
137 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { | ||
138 | r2->cp = CP_REG_ARM64_SYSREG_CP; | ||
139 | } | ||
140 | - *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | ||
141 | - r2->opc0, opc1, opc2); | ||
142 | + key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | ||
143 | + r2->opc0, opc1, opc2); | ||
144 | } else { | ||
145 | - *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); | ||
146 | + key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); | ||
147 | } | ||
148 | if (opaque) { | ||
149 | r2->opaque = opaque; | ||
150 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
151 | * requested. | ||
152 | */ | ||
153 | if (!(r->type & ARM_CP_OVERRIDE)) { | ||
154 | - ARMCPRegInfo *oldreg; | ||
155 | - oldreg = g_hash_table_lookup(cpu->cp_regs, key); | ||
156 | + const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); | ||
157 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | ||
158 | fprintf(stderr, "Register redefined: cp=%d %d bit " | ||
159 | "crn=%d crm=%d opc1=%d opc2=%d, " | ||
160 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
161 | g_assert_not_reached(); | ||
162 | } | ||
163 | } | ||
164 | - g_hash_table_insert(cpu->cp_regs, key, r2); | ||
165 | + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); | ||
166 | } | 47 | } |
167 | 48 | ||
168 | 49 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) | |
169 | @@ -XXX,XX +XXX,XX @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, | ||
170 | |||
171 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) | ||
172 | { | ||
173 | - return g_hash_table_lookup(cpregs, &encoded_cp); | ||
174 | + return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); | ||
175 | } | ||
176 | |||
177 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | ||
178 | -- | 50 | -- |
179 | 2.25.1 | 51 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for loongarch. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-42-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/loongarch/tcg/fpu_helper.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/loongarch/tcg/fpu_helper.c | ||
13 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
14 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
15 | */ | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); | ||
18 | + /* Default NaN: sign bit clear, msb frac bit set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | } | ||
21 | |||
22 | int ieee_ex_to_loongarch(int xcpt) | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for m68k. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-43-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/m68k/cpu.c | 2 ++ | ||
8 | fpu/softfloat-specialize.c.inc | 2 +- | ||
9 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/m68k/cpu.c | ||
14 | +++ b/target/m68k/cpu.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
16 | * preceding paragraph for nonsignaling NaNs. | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | + /* Default NaN: sign bit clear, all frac bits set */ | ||
20 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
21 | |||
22 | nan = floatx80_default_nan(&env->fp_status); | ||
23 | for (i = 0; i < 8; i++) { | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
29 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
30 | |||
31 | if (dnan_pattern == 0) { | ||
32 | -#if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
33 | +#if defined(TARGET_SPARC) | ||
34 | /* Sign bit clear, all frac bits set */ | ||
35 | dnan_pattern = 0b01111111; | ||
36 | #elif defined(TARGET_HEXAGON) | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for MIPS. Note that this | ||
2 | is our only target which currently changes the default NaN | ||
3 | at runtime (which it was previously doing indirectly when it | ||
4 | changed the snan_bit_is_one setting). | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-44-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/mips/fpu_helper.h | 7 +++++++ | ||
11 | target/mips/msa.c | 3 +++ | ||
12 | 2 files changed, 10 insertions(+) | ||
13 | |||
14 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/mips/fpu_helper.h | ||
17 | +++ b/target/mips/fpu_helper.h | ||
18 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
19 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
20 | nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; | ||
21 | set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); | ||
22 | + /* | ||
23 | + * With nan2008, the default NaN value has the sign bit clear and the | ||
24 | + * frac msb set; with the older mode, the sign bit is clear, and all | ||
25 | + * frac bits except the msb are set. | ||
26 | + */ | ||
27 | + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, | ||
28 | + &env->active_fpu.fp_status); | ||
29 | |||
30 | } | ||
31 | |||
32 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/mips/msa.c | ||
35 | +++ b/target/mips/msa.c | ||
36 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
37 | /* Inf * 0 + NaN returns the input NaN */ | ||
38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, | ||
39 | &env->active_tc.msa_fp_status); | ||
40 | + /* Default NaN: sign bit clear, frac msb set */ | ||
41 | + set_float_default_nan_pattern(0b01000000, | ||
42 | + &env->active_tc.msa_fp_status); | ||
43 | } | ||
44 | -- | ||
45 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for openrisc. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-45-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/openrisc/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/openrisc/cpu.c | ||
13 | +++ b/target/openrisc/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | */ | ||
16 | set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); | ||
17 | |||
18 | + /* Default NaN: sign bit clear, frac msb set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); | ||
20 | |||
21 | #ifndef CONFIG_USER_ONLY | ||
22 | cpu->env.picmr = 0x00000000; | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for ppc. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-46-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/ppc/cpu_init.c | 4 ++++ | ||
8 | 1 file changed, 4 insertions(+) | ||
9 | |||
10 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/ppc/cpu_init.c | ||
13 | +++ b/target/ppc/cpu_init.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); | ||
17 | |||
18 | + /* Default NaN: sign bit clear, set frac msb */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | + set_float_default_nan_pattern(0b01000000, &env->vec_status); | ||
21 | + | ||
22 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { | ||
23 | ppc_spr_t *spr = &env->spr_cb[i]; | ||
24 | |||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for sh4. Note that sh4 | ||
2 | is one of the only three targets (the others being HPPA and | ||
3 | sometimes MIPS) that has snan_bit_is_one set. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-47-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/sh4/cpu.c | 2 ++ | ||
10 | 1 file changed, 2 insertions(+) | ||
11 | |||
12 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sh4/cpu.c | ||
15 | +++ b/target/sh4/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_flush_to_zero(1, &env->fp_status); | ||
18 | #endif | ||
19 | set_default_nan_mode(1, &env->fp_status); | ||
20 | + /* sign bit clear, set all frac bits other than msb */ | ||
21 | + set_float_default_nan_pattern(0b00111111, &env->fp_status); | ||
22 | } | ||
23 | |||
24 | static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for rx. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-48-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/rx/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/rx/cpu.c | ||
13 | +++ b/target/rx/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | * then prefer dest over source", which is float_2nan_prop_s_ab. | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
18 | + /* Default NaN value: sign bit clear, set frac msb */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | } | ||
21 | |||
22 | static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for s390x. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-49-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/s390x/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/s390x/cpu.c | ||
13 | +++ b/target/s390x/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
17 | &env->fpu_status); | ||
18 | + /* Default NaN value: sign bit clear, frac msb set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fpu_status); | ||
20 | /* fall through */ | ||
21 | case RESET_TYPE_S390_CPU_NORMAL: | ||
22 | env->psw.mask &= ~PSW_MASK_RI; | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for SPARC, and remove | ||
2 | the ifdef from parts64_default_nan. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-50-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 5 +---- | ||
10 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | ||
18 | /* For inf * 0 + NaN, return the input NaN */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + /* Default NaN value: sign bit clear, all frac bits set */ | ||
21 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
22 | |||
23 | cpu_exec_realizefn(cs, &local_err); | ||
24 | if (local_err != NULL) { | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
31 | |||
32 | if (dnan_pattern == 0) { | ||
33 | -#if defined(TARGET_SPARC) | ||
34 | - /* Sign bit clear, all frac bits set */ | ||
35 | - dnan_pattern = 0b01111111; | ||
36 | -#elif defined(TARGET_HEXAGON) | ||
37 | +#if defined(TARGET_HEXAGON) | ||
38 | /* Sign bit set, all frac bits set. */ | ||
39 | dnan_pattern = 0b11111111; | ||
40 | #else | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for xtensa. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-51-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/xtensa/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/xtensa/cpu.c | ||
13 | +++ b/target/xtensa/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | /* For inf * 0 + NaN, return the input NaN */ | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
17 | set_no_signaling_nans(!dfpu, &env->fp_status); | ||
18 | + /* Default NaN value: sign bit clear, set frac msb */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | xtensa_use_first_nan(env, !dfpu); | ||
21 | } | ||
22 | |||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for hexagon. | ||
2 | Remove the ifdef from parts64_default_nan(); the only | ||
3 | remaining unconverted targets all use the default case. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-52-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/hexagon/cpu.c | 2 ++ | ||
10 | fpu/softfloat-specialize.c.inc | 5 ----- | ||
11 | 2 files changed, 2 insertions(+), 5 deletions(-) | ||
12 | |||
13 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/hexagon/cpu.c | ||
16 | +++ b/target/hexagon/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) | ||
18 | |||
19 | set_default_nan_mode(1, &env->fp_status); | ||
20 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); | ||
21 | + /* Default NaN value: sign bit set, all frac bits set */ | ||
22 | + set_float_default_nan_pattern(0b11111111, &env->fp_status); | ||
23 | } | ||
24 | |||
25 | static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) | ||
26 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/fpu/softfloat-specialize.c.inc | ||
29 | +++ b/fpu/softfloat-specialize.c.inc | ||
30 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
31 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
32 | |||
33 | if (dnan_pattern == 0) { | ||
34 | -#if defined(TARGET_HEXAGON) | ||
35 | - /* Sign bit set, all frac bits set. */ | ||
36 | - dnan_pattern = 0b11111111; | ||
37 | -#else | ||
38 | /* | ||
39 | * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
40 | * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
41 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
42 | /* sign bit clear, set frac msb */ | ||
43 | dnan_pattern = 0b01000000; | ||
44 | } | ||
45 | -#endif | ||
46 | } | ||
47 | assert(dnan_pattern != 0); | ||
48 | |||
49 | -- | ||
50 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for riscv. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-53-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/riscv/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/riscv/cpu.c | ||
13 | +++ b/target/riscv/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | cs->exception_index = RISCV_EXCP_NONE; | ||
16 | env->load_res = -1; | ||
17 | set_default_nan_mode(1, &env->fp_status); | ||
18 | + /* Default NaN value: sign bit clear, frac msb set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | env->vill = true; | ||
21 | |||
22 | #ifndef CONFIG_USER_ONLY | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Set the default NaN pattern explicitly for tricore. |
---|---|---|---|
2 | 2 | ||
3 | Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | is handled in define_one_arm_cp_reg_with_opaque. | 5 | Message-id: 20241202131347.498124-54-peter.maydell@linaro.org |
6 | --- | ||
7 | target/tricore/helper.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
6 | 9 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | diff --git a/target/tricore/helper.c b/target/tricore/helper.c |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220501055028.646596-10-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/cpregs.h | 7 ++++--- | ||
13 | target/arm/helper.c | 7 +++++-- | ||
14 | 2 files changed, 9 insertions(+), 5 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpregs.h | 12 | --- a/target/tricore/helper.c |
19 | +++ b/target/arm/cpregs.h | 13 | +++ b/target/tricore/helper.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef enum { | 14 | @@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env) |
21 | * registered entry will only have one to identify whether the entry is secure | 15 | set_flush_to_zero(1, &env->fp_status); |
22 | * or non-secure. | 16 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); |
23 | */ | 17 | set_default_nan_mode(1, &env->fp_status); |
24 | -enum { | 18 | + /* Default NaN pattern: sign bit clear, frac msb set */ |
25 | +typedef enum { | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
26 | + ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */ | ||
27 | ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | ||
28 | ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | ||
29 | -}; | ||
30 | +} CPSecureState; | ||
31 | |||
32 | /* | ||
33 | * Access rights: | ||
34 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { | ||
35 | /* Access rights: PL*_[RW] */ | ||
36 | CPAccessRights access; | ||
37 | /* Security state: ARM_CP_SECSTATE_* bits/values */ | ||
38 | - int secure; | ||
39 | + CPSecureState secure; | ||
40 | /* | ||
41 | * The opaque pointer passed to define_arm_cp_regs_with_opaque() when | ||
42 | * this register was defined: can be used to hand data through to the | ||
43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/helper.c | ||
46 | +++ b/target/arm/helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) | ||
48 | } | 20 | } |
49 | 21 | ||
50 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 22 | uint32_t psw_read(CPUTriCoreState *env) |
51 | - void *opaque, CPState state, int secstate, | ||
52 | + void *opaque, CPState state, | ||
53 | + CPSecureState secstate, | ||
54 | int crm, int opc1, int opc2, | ||
55 | const char *name) | ||
56 | { | ||
57 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
58 | r->secure, crm, opc1, opc2, | ||
59 | r->name); | ||
60 | break; | ||
61 | - default: | ||
62 | + case ARM_CP_SECSTATE_BOTH: | ||
63 | name = g_strdup_printf("%s_S", r->name); | ||
64 | add_cpreg_to_hashtable(cpu, r, opaque, state, | ||
65 | ARM_CP_SECSTATE_S, | ||
66 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
67 | ARM_CP_SECSTATE_NS, | ||
68 | crm, opc1, opc2, r->name); | ||
69 | break; | ||
70 | + default: | ||
71 | + g_assert_not_reached(); | ||
72 | } | ||
73 | } else { | ||
74 | /* AArch64 registers get mapped to non-secure instance | ||
75 | -- | 23 | -- |
76 | 2.25.1 | 24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Now that all our targets have bene converted to explicitly specify | ||
2 | their pattern for the default NaN value we can remove the remaining | ||
3 | fallback code in parts64_default_nan(). | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-55-peter.maydell@linaro.org | ||
8 | --- | ||
9 | fpu/softfloat-specialize.c.inc | 14 -------------- | ||
10 | 1 file changed, 14 deletions(-) | ||
11 | |||
12 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/fpu/softfloat-specialize.c.inc | ||
15 | +++ b/fpu/softfloat-specialize.c.inc | ||
16 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
17 | uint64_t frac; | ||
18 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
19 | |||
20 | - if (dnan_pattern == 0) { | ||
21 | - /* | ||
22 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
23 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
24 | - * do not have floating-point. | ||
25 | - */ | ||
26 | - if (snan_bit_is_one(status)) { | ||
27 | - /* sign bit clear, set all frac bits other than msb */ | ||
28 | - dnan_pattern = 0b00111111; | ||
29 | - } else { | ||
30 | - /* sign bit clear, set frac msb */ | ||
31 | - dnan_pattern = 0b01000000; | ||
32 | - } | ||
33 | - } | ||
34 | assert(dnan_pattern != 0); | ||
35 | |||
36 | sign = dnan_pattern >> 7; | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Perform the override check early, so that it is still done | 3 | Inline pickNaNMulAdd into its only caller. This makes |
4 | even when we decide to discard an unreachable cpreg. | 4 | one assert redundant with the immediately preceding IF. |
5 | |||
6 | Use assert not printf+abort. | ||
7 | 5 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Message-id: 20220501055028.646596-18-richard.henderson@linaro.org | 8 | Message-id: 20241203203949.483774-3-richard.henderson@linaro.org |
9 | [PMM: keep comment from old code in new location] | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | target/arm/helper.c | 22 ++++++++-------------- | 12 | fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++- |
14 | 1 file changed, 8 insertions(+), 14 deletions(-) | 13 | fpu/softfloat-specialize.c.inc | 54 ---------------------------------- |
14 | 2 files changed, 40 insertions(+), 55 deletions(-) | ||
15 | 15 | ||
16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/helper.c | 18 | --- a/fpu/softfloat-parts.c.inc |
19 | +++ b/target/arm/helper.c | 19 | +++ b/fpu/softfloat-parts.c.inc |
20 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
21 | g_assert_not_reached(); | ||
22 | } | 21 | } |
23 | 22 | ||
24 | + /* Overriding of an existing definition must be explicitly requested. */ | 23 | if (s->default_nan_mode) { |
25 | + if (!(r->type & ARM_CP_OVERRIDE)) { | 24 | + /* |
26 | + const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); | 25 | + * We guarantee not to require the target to tell us how to |
27 | + if (oldreg) { | 26 | + * pick a NaN if we're always returning the default NaN. |
28 | + assert(oldreg->type & ARM_CP_OVERRIDE); | 27 | + * But if we're not in default-NaN mode then the target must |
28 | + * specify. | ||
29 | + */ | ||
30 | which = 3; | ||
31 | + } else if (infzero) { | ||
32 | + /* | ||
33 | + * Inf * 0 + NaN -- some implementations return the | ||
34 | + * default NaN here, and some return the input NaN. | ||
35 | + */ | ||
36 | + switch (s->float_infzeronan_rule) { | ||
37 | + case float_infzeronan_dnan_never: | ||
38 | + which = 2; | ||
39 | + break; | ||
40 | + case float_infzeronan_dnan_always: | ||
41 | + which = 3; | ||
42 | + break; | ||
43 | + case float_infzeronan_dnan_if_qnan: | ||
44 | + which = is_qnan(c->cls) ? 3 : 2; | ||
45 | + break; | ||
46 | + default: | ||
47 | + g_assert_not_reached(); | ||
29 | + } | 48 | + } |
30 | + } | 49 | } else { |
50 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); | ||
51 | + FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
52 | + Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
31 | + | 53 | + |
32 | /* Combine cpreg and name into one allocation. */ | 54 | + assert(rule != float_3nan_prop_none); |
33 | name_len = strlen(name) + 1; | 55 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { |
34 | r2 = g_malloc(sizeof(*r2) + name_len); | 56 | + /* We have at least one SNaN input and should prefer it */ |
35 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 57 | + do { |
36 | assert(!raw_accessors_invalid(r2)); | 58 | + which = rule & R_3NAN_1ST_MASK; |
59 | + rule >>= R_3NAN_1ST_LENGTH; | ||
60 | + } while (!is_snan(cls[which])); | ||
61 | + } else { | ||
62 | + do { | ||
63 | + which = rule & R_3NAN_1ST_MASK; | ||
64 | + rule >>= R_3NAN_1ST_LENGTH; | ||
65 | + } while (!is_nan(cls[which])); | ||
66 | + } | ||
37 | } | 67 | } |
38 | 68 | ||
39 | - /* Overriding of an existing definition must be explicitly | 69 | if (which == 3) { |
40 | - * requested. | 70 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/fpu/softfloat-specialize.c.inc | ||
73 | +++ b/fpu/softfloat-specialize.c.inc | ||
74 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
75 | } | ||
76 | } | ||
77 | |||
78 | -/*---------------------------------------------------------------------------- | ||
79 | -| Select which NaN to propagate for a three-input operation. | ||
80 | -| For the moment we assume that no CPU needs the 'larger significand' | ||
81 | -| information. | ||
82 | -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | ||
83 | -*----------------------------------------------------------------------------*/ | ||
84 | -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
85 | - bool infzero, bool have_snan, float_status *status) | ||
86 | -{ | ||
87 | - FloatClass cls[3] = { a_cls, b_cls, c_cls }; | ||
88 | - Float3NaNPropRule rule = status->float_3nan_prop_rule; | ||
89 | - int which; | ||
90 | - | ||
91 | - /* | ||
92 | - * We guarantee not to require the target to tell us how to | ||
93 | - * pick a NaN if we're always returning the default NaN. | ||
94 | - * But if we're not in default-NaN mode then the target must | ||
95 | - * specify. | ||
41 | - */ | 96 | - */ |
42 | - if (!(r->type & ARM_CP_OVERRIDE)) { | 97 | - assert(!status->default_nan_mode); |
43 | - const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); | 98 | - |
44 | - if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | 99 | - if (infzero) { |
45 | - fprintf(stderr, "Register redefined: cp=%d %d bit " | 100 | - /* |
46 | - "crn=%d crm=%d opc1=%d opc2=%d, " | 101 | - * Inf * 0 + NaN -- some implementations return the default NaN here, |
47 | - "was %s, now %s\n", r2->cp, 32 + 32 * is64, | 102 | - * and some return the input NaN. |
48 | - r2->crn, r2->crm, r2->opc1, r2->opc2, | 103 | - */ |
49 | - oldreg->name, r2->name); | 104 | - switch (status->float_infzeronan_rule) { |
105 | - case float_infzeronan_dnan_never: | ||
106 | - return 2; | ||
107 | - case float_infzeronan_dnan_always: | ||
108 | - return 3; | ||
109 | - case float_infzeronan_dnan_if_qnan: | ||
110 | - return is_qnan(c_cls) ? 3 : 2; | ||
111 | - default: | ||
50 | - g_assert_not_reached(); | 112 | - g_assert_not_reached(); |
51 | - } | 113 | - } |
52 | - } | 114 | - } |
53 | g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); | 115 | - |
54 | } | 116 | - assert(rule != float_3nan_prop_none); |
55 | 117 | - if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | |
118 | - /* We have at least one SNaN input and should prefer it */ | ||
119 | - do { | ||
120 | - which = rule & R_3NAN_1ST_MASK; | ||
121 | - rule >>= R_3NAN_1ST_LENGTH; | ||
122 | - } while (!is_snan(cls[which])); | ||
123 | - } else { | ||
124 | - do { | ||
125 | - which = rule & R_3NAN_1ST_MASK; | ||
126 | - rule >>= R_3NAN_1ST_LENGTH; | ||
127 | - } while (!is_nan(cls[which])); | ||
128 | - } | ||
129 | - return which; | ||
130 | -} | ||
131 | - | ||
132 | /*---------------------------------------------------------------------------- | ||
133 | | Returns 1 if the double-precision floating-point value `a' is a quiet | ||
134 | | NaN; otherwise returns 0. | ||
56 | -- | 135 | -- |
57 | 2.25.1 | 136 | 2.34.1 |
137 | |||
138 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Remove a possible source of error by removing REGINFO_SENTINEL | 3 | Remove "3" as a special case for which and simply |
4 | and using ARRAY_SIZE (convinently hidden inside a macro) to | 4 | branch to return the desired value. |
5 | find the end of the set of regs being registered or modified. | ||
6 | 5 | ||
7 | The space saved by not having the extra array element reduces | ||
8 | the executable's .data.rel.ro section by about 9k. | ||
9 | |||
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Message-id: 20220501055028.646596-4-richard.henderson@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20241203203949.483774-4-richard.henderson@linaro.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 10 | --- |
16 | target/arm/cpregs.h | 53 +++++++++--------- | 11 | fpu/softfloat-parts.c.inc | 20 ++++++++++---------- |
17 | hw/arm/pxa2xx.c | 1 - | 12 | 1 file changed, 10 insertions(+), 10 deletions(-) |
18 | hw/arm/pxa2xx_pic.c | 1 - | ||
19 | hw/intc/arm_gicv3_cpuif.c | 5 -- | ||
20 | hw/intc/arm_gicv3_kvm.c | 1 - | ||
21 | target/arm/cpu64.c | 1 - | ||
22 | target/arm/cpu_tcg.c | 4 -- | ||
23 | target/arm/helper.c | 111 ++++++++------------------------------ | ||
24 | 8 files changed, 48 insertions(+), 129 deletions(-) | ||
25 | 13 | ||
26 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
27 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/cpregs.h | 16 | --- a/fpu/softfloat-parts.c.inc |
29 | +++ b/target/arm/cpregs.h | 17 | +++ b/fpu/softfloat-parts.c.inc |
30 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
31 | #define ARM_CP_NO_GDB 0x4000 | 19 | * But if we're not in default-NaN mode then the target must |
32 | #define ARM_CP_RAISES_EXC 0x8000 | 20 | * specify. |
33 | #define ARM_CP_NEWEL 0x10000 | 21 | */ |
34 | -/* Used only as a terminator for ARMCPRegInfo lists */ | 22 | - which = 3; |
35 | -#define ARM_CP_SENTINEL 0xfffff | 23 | + goto default_nan; |
36 | /* Mask of only the flag bits in a type field */ | 24 | } else if (infzero) { |
37 | #define ARM_CP_FLAG_MASK 0x1f0ff | 25 | /* |
38 | 26 | * Inf * 0 + NaN -- some implementations return the | |
39 | @@ -XXX,XX +XXX,XX @@ enum { | 27 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
40 | ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | 28 | */ |
41 | }; | 29 | switch (s->float_infzeronan_rule) { |
42 | 30 | case float_infzeronan_dnan_never: | |
43 | -/* | 31 | - which = 2; |
44 | - * Return true if cptype is a valid type field. This is used to try to | 32 | break; |
45 | - * catch errors where the sentinel has been accidentally left off the end | 33 | case float_infzeronan_dnan_always: |
46 | - * of a list of registers. | 34 | - which = 3; |
47 | - */ | 35 | - break; |
48 | -static inline bool cptype_valid(int cptype) | 36 | + goto default_nan; |
49 | -{ | 37 | case float_infzeronan_dnan_if_qnan: |
50 | - return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | 38 | - which = is_qnan(c->cls) ? 3 : 2; |
51 | - || ((cptype & ARM_CP_SPECIAL) && | 39 | + if (is_qnan(c->cls)) { |
52 | - ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); | 40 | + goto default_nan; |
53 | -} | 41 | + } |
54 | - | 42 | break; |
55 | /* | 43 | default: |
56 | * Access rights: | 44 | g_assert_not_reached(); |
57 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | 45 | } |
58 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { | 46 | + which = 2; |
59 | #define CPREG_FIELD64(env, ri) \ | 47 | } else { |
60 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | 48 | FloatClass cls[3] = { a->cls, b->cls, c->cls }; |
61 | 49 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | |
62 | -#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | 50 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
63 | +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg, | ||
64 | + void *opaque); | ||
65 | |||
66 | -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | ||
67 | - const ARMCPRegInfo *regs, void *opaque); | ||
68 | -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
69 | - const ARMCPRegInfo *regs, void *opaque); | ||
70 | -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
71 | -{ | ||
72 | - define_arm_cp_regs_with_opaque(cpu, regs, 0); | ||
73 | -} | ||
74 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | ||
75 | { | ||
76 | - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | ||
77 | + define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); | ||
78 | } | ||
79 | + | ||
80 | +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, | ||
81 | + void *opaque, size_t len); | ||
82 | + | ||
83 | +#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ | ||
84 | + do { \ | ||
85 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ | ||
86 | + define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ | ||
87 | + ARRAY_SIZE(REGS)); \ | ||
88 | + } while (0) | ||
89 | + | ||
90 | +#define define_arm_cp_regs(CPU, REGS) \ | ||
91 | + define_arm_cp_regs_with_opaque(CPU, REGS, NULL) | ||
92 | + | ||
93 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); | ||
94 | |||
95 | /* | ||
96 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMCPRegUserSpaceInfo { | ||
97 | uint64_t fixed_bits; | ||
98 | } ARMCPRegUserSpaceInfo; | ||
99 | |||
100 | -#define REGUSERINFO_SENTINEL { .name = NULL } | ||
101 | +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, | ||
102 | + const ARMCPRegUserSpaceInfo *mods, | ||
103 | + size_t mods_len); | ||
104 | |||
105 | -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); | ||
106 | +#define modify_arm_cp_regs(REGS, MODS) \ | ||
107 | + do { \ | ||
108 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ | ||
109 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \ | ||
110 | + modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ | ||
111 | + MODS, ARRAY_SIZE(MODS)); \ | ||
112 | + } while (0) | ||
113 | |||
114 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ | ||
115 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, | ||
116 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/hw/arm/pxa2xx.c | ||
119 | +++ b/hw/arm/pxa2xx.c | ||
120 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_cp_reginfo[] = { | ||
121 | { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
122 | .access = PL1_RW, .type = ARM_CP_IO, | ||
123 | .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, | ||
124 | - REGINFO_SENTINEL | ||
125 | }; | ||
126 | |||
127 | static void pxa2xx_setup_cp14(PXA2xxState *s) | ||
128 | diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c | ||
129 | index XXXXXXX..XXXXXXX 100644 | ||
130 | --- a/hw/arm/pxa2xx_pic.c | ||
131 | +++ b/hw/arm/pxa2xx_pic.c | ||
132 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = { | ||
133 | REGINFO_FOR_PIC_CP("ICLR2", 8), | ||
134 | REGINFO_FOR_PIC_CP("ICFP2", 9), | ||
135 | REGINFO_FOR_PIC_CP("ICPR2", 0xa), | ||
136 | - REGINFO_SENTINEL | ||
137 | }; | ||
138 | |||
139 | static const MemoryRegionOps pxa2xx_pic_ops = { | ||
140 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
141 | index XXXXXXX..XXXXXXX 100644 | ||
142 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
143 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
144 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | ||
145 | .readfn = icc_igrpen1_el3_read, | ||
146 | .writefn = icc_igrpen1_el3_write, | ||
147 | }, | ||
148 | - REGINFO_SENTINEL | ||
149 | }; | ||
150 | |||
151 | static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
152 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { | ||
153 | .readfn = ich_vmcr_read, | ||
154 | .writefn = ich_vmcr_write, | ||
155 | }, | ||
156 | - REGINFO_SENTINEL | ||
157 | }; | ||
158 | |||
159 | static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { | ||
160 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { | ||
161 | .readfn = ich_ap_read, | ||
162 | .writefn = ich_ap_write, | ||
163 | }, | ||
164 | - REGINFO_SENTINEL | ||
165 | }; | ||
166 | |||
167 | static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { | ||
168 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { | ||
169 | .readfn = ich_ap_read, | ||
170 | .writefn = ich_ap_write, | ||
171 | }, | ||
172 | - REGINFO_SENTINEL | ||
173 | }; | ||
174 | |||
175 | static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) | ||
176 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) | ||
177 | .readfn = ich_lr_read, | ||
178 | .writefn = ich_lr_write, | ||
179 | }, | ||
180 | - REGINFO_SENTINEL | ||
181 | }; | ||
182 | define_arm_cp_regs(cpu, lr_regset); | ||
183 | } | ||
184 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
185 | index XXXXXXX..XXXXXXX 100644 | ||
186 | --- a/hw/intc/arm_gicv3_kvm.c | ||
187 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
188 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | ||
189 | */ | ||
190 | .resetfn = arm_gicv3_icc_reset, | ||
191 | }, | ||
192 | - REGINFO_SENTINEL | ||
193 | }; | ||
194 | |||
195 | /** | ||
196 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
197 | index XXXXXXX..XXXXXXX 100644 | ||
198 | --- a/target/arm/cpu64.c | ||
199 | +++ b/target/arm/cpu64.c | ||
200 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
201 | { .name = "L2MERRSR", | ||
202 | .cp = 15, .opc1 = 3, .crm = 15, | ||
203 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
204 | - REGINFO_SENTINEL | ||
205 | }; | ||
206 | |||
207 | static void aarch64_a57_initfn(Object *obj) | ||
208 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
209 | index XXXXXXX..XXXXXXX 100644 | ||
210 | --- a/target/arm/cpu_tcg.c | ||
211 | +++ b/target/arm/cpu_tcg.c | ||
212 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = { | ||
213 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
214 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | ||
215 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
216 | - REGINFO_SENTINEL | ||
217 | }; | ||
218 | |||
219 | static void cortex_a8_initfn(Object *obj) | ||
220 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = { | ||
221 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | ||
222 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | ||
223 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | ||
224 | - REGINFO_SENTINEL | ||
225 | }; | ||
226 | |||
227 | static void cortex_a9_initfn(Object *obj) | ||
228 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | ||
229 | #endif | ||
230 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | ||
231 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
232 | - REGINFO_SENTINEL | ||
233 | }; | ||
234 | |||
235 | static void cortex_a7_initfn(Object *obj) | ||
236 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = { | ||
237 | .access = PL1_RW, .type = ARM_CP_CONST }, | ||
238 | { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, | ||
239 | .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, | ||
240 | - REGINFO_SENTINEL | ||
241 | }; | ||
242 | |||
243 | static void cortex_r5_initfn(Object *obj) | ||
244 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
245 | index XXXXXXX..XXXXXXX 100644 | ||
246 | --- a/target/arm/helper.c | ||
247 | +++ b/target/arm/helper.c | ||
248 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = { | ||
249 | .secure = ARM_CP_SECSTATE_S, | ||
250 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | ||
251 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | ||
252 | - REGINFO_SENTINEL | ||
253 | }; | ||
254 | |||
255 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | ||
256 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = { | ||
257 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | ||
258 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | ||
259 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | ||
260 | - REGINFO_SENTINEL | ||
261 | }; | ||
262 | |||
263 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { | ||
264 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = { | ||
265 | */ | ||
266 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | ||
267 | .access = PL1_W, .type = ARM_CP_WFI }, | ||
268 | - REGINFO_SENTINEL | ||
269 | }; | ||
270 | |||
271 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | ||
272 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = { | ||
273 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | ||
274 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | ||
275 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | ||
276 | - REGINFO_SENTINEL | ||
277 | }; | ||
278 | |||
279 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
280 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = { | ||
281 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, | ||
282 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), | ||
283 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, | ||
284 | - REGINFO_SENTINEL | ||
285 | }; | ||
286 | |||
287 | typedef struct pm_event { | ||
288 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
289 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | ||
290 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | ||
291 | .writefn = tlbimvaa_write }, | ||
292 | - REGINFO_SENTINEL | ||
293 | }; | ||
294 | |||
295 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | ||
296 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = { | ||
297 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | ||
298 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | ||
299 | .writefn = tlbimvaa_is_write }, | ||
300 | - REGINFO_SENTINEL | ||
301 | }; | ||
302 | |||
303 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { | ||
304 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = { | ||
305 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | ||
306 | .writefn = pmovsset_write, | ||
307 | .raw_writefn = raw_write }, | ||
308 | - REGINFO_SENTINEL | ||
309 | }; | ||
310 | |||
311 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
312 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = { | ||
313 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | ||
314 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | ||
315 | .accessfn = teehbr_access, .resetvalue = 0 }, | ||
316 | - REGINFO_SENTINEL | ||
317 | }; | ||
318 | |||
319 | static const ARMCPRegInfo v6k_cp_reginfo[] = { | ||
320 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { | ||
321 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | ||
322 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | ||
323 | .resetvalue = 0 }, | ||
324 | - REGINFO_SENTINEL | ||
325 | }; | ||
326 | |||
327 | #ifndef CONFIG_USER_ONLY | ||
328 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | ||
329 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | ||
330 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | ||
331 | }, | ||
332 | - REGINFO_SENTINEL | ||
333 | }; | ||
334 | |||
335 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
336 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { | ||
337 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | ||
338 | .readfn = gt_virt_cnt_read, | ||
339 | }, | ||
340 | - REGINFO_SENTINEL | ||
341 | }; | ||
342 | |||
343 | #endif | ||
344 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = { | ||
345 | .access = PL1_W, .accessfn = ats_access, | ||
346 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, | ||
347 | #endif | ||
348 | - REGINFO_SENTINEL | ||
349 | }; | ||
350 | |||
351 | /* Return basic MPU access permission bits. */ | ||
352 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | ||
353 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), | ||
354 | .writefn = pmsav7_rgnr_write, | ||
355 | .resetfn = arm_cp_reset_ignore }, | ||
356 | - REGINFO_SENTINEL | ||
357 | }; | ||
358 | |||
359 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | ||
360 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = { | ||
361 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | ||
362 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | ||
363 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | ||
364 | - REGINFO_SENTINEL | ||
365 | }; | ||
366 | |||
367 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
368 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { | ||
369 | .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
370 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | ||
371 | .resetvalue = 0, }, | ||
372 | - REGINFO_SENTINEL | ||
373 | }; | ||
374 | |||
375 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | ||
376 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { | ||
377 | /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ | ||
378 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), | ||
379 | offsetof(CPUARMState, cp15.tcr_el[1])} }, | ||
380 | - REGINFO_SENTINEL | ||
381 | }; | ||
382 | |||
383 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing | ||
384 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = { | ||
385 | { .name = "C9", .cp = 15, .crn = 9, | ||
386 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | ||
387 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | ||
388 | - REGINFO_SENTINEL | ||
389 | }; | ||
390 | |||
391 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
392 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = { | ||
393 | { .name = "XSCALE_UNLOCK_DCACHE", | ||
394 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | ||
395 | .access = PL1_W, .type = ARM_CP_NOP }, | ||
396 | - REGINFO_SENTINEL | ||
397 | }; | ||
398 | |||
399 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | ||
400 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | ||
401 | .access = PL1_RW, | ||
402 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, | ||
403 | .resetvalue = 0 }, | ||
404 | - REGINFO_SENTINEL | ||
405 | }; | ||
406 | |||
407 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { | ||
408 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { | ||
409 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | ||
410 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, | ||
411 | .resetvalue = 0 }, | ||
412 | - REGINFO_SENTINEL | ||
413 | }; | ||
414 | |||
415 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | ||
416 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | ||
417 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | ||
418 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | ||
419 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | ||
420 | - REGINFO_SENTINEL | ||
421 | }; | ||
422 | |||
423 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | ||
424 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | ||
425 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, | ||
426 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, | ||
427 | .resetvalue = (1 << 30) }, | ||
428 | - REGINFO_SENTINEL | ||
429 | }; | ||
430 | |||
431 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { | ||
432 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = { | ||
433 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | ||
434 | .access = PL1_RW, .resetvalue = 0, | ||
435 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, | ||
436 | - REGINFO_SENTINEL | ||
437 | }; | ||
438 | |||
439 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
440 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { | ||
441 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | ||
442 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | ||
443 | .writefn = vmsa_ttbr_write, }, | ||
444 | - REGINFO_SENTINEL | ||
445 | }; | ||
446 | |||
447 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
448 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
449 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | ||
450 | .writefn = sdcr_write, | ||
451 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | ||
452 | - REGINFO_SENTINEL | ||
453 | }; | ||
454 | |||
455 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ | ||
456 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | ||
457 | .type = ARM_CP_CONST, | ||
458 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | ||
459 | .access = PL2_RW, .resetvalue = 0 }, | ||
460 | - REGINFO_SENTINEL | ||
461 | }; | ||
462 | |||
463 | /* Ditto, but for registers which exist in ARMv8 but not v7 */ | ||
464 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | ||
465 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | ||
466 | .access = PL2_RW, | ||
467 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
468 | - REGINFO_SENTINEL | ||
469 | }; | ||
470 | |||
471 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
472 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
473 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | ||
474 | .access = PL2_RW, | ||
475 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | ||
476 | - REGINFO_SENTINEL | ||
477 | }; | ||
478 | |||
479 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { | ||
480 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = { | ||
481 | .access = PL2_RW, | ||
482 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | ||
483 | .writefn = hcr_writehigh }, | ||
484 | - REGINFO_SENTINEL | ||
485 | }; | ||
486 | |||
487 | static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
488 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = { | ||
489 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, | ||
490 | .access = PL2_RW, .accessfn = sel2_access, | ||
491 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, | ||
492 | - REGINFO_SENTINEL | ||
493 | }; | ||
494 | |||
495 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
496 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = { | ||
497 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | ||
498 | .access = PL3_W, .type = ARM_CP_NO_RAW, | ||
499 | .writefn = tlbi_aa64_vae3_write }, | ||
500 | - REGINFO_SENTINEL | ||
501 | }; | ||
502 | |||
503 | #ifndef CONFIG_USER_ONLY | ||
504 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
505 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | ||
506 | .access = PL1_RW, .accessfn = access_tda, | ||
507 | .type = ARM_CP_NOP }, | ||
508 | - REGINFO_SENTINEL | ||
509 | }; | ||
510 | |||
511 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
512 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
513 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | ||
514 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | ||
515 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | ||
516 | - REGINFO_SENTINEL | ||
517 | }; | ||
518 | |||
519 | /* Return the exception level to which exceptions should be taken | ||
520 | @@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu) | ||
521 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), | ||
522 | .writefn = dbgbcr_write, .raw_writefn = raw_write | ||
523 | }, | ||
524 | - REGINFO_SENTINEL | ||
525 | }; | ||
526 | define_arm_cp_regs(cpu, dbgregs); | ||
527 | } | ||
528 | @@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu) | ||
529 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), | ||
530 | .writefn = dbgwcr_write, .raw_writefn = raw_write | ||
531 | }, | ||
532 | - REGINFO_SENTINEL | ||
533 | }; | ||
534 | define_arm_cp_regs(cpu, dbgregs); | ||
535 | } | ||
536 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
537 | .type = ARM_CP_IO, | ||
538 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | ||
539 | .raw_writefn = pmevtyper_rawwrite }, | ||
540 | - REGINFO_SENTINEL | ||
541 | }; | ||
542 | define_arm_cp_regs(cpu, pmev_regs); | ||
543 | g_free(pmevcntr_name); | ||
544 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
545 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | ||
546 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
547 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | ||
548 | - REGINFO_SENTINEL | ||
549 | }; | ||
550 | define_arm_cp_regs(cpu, v81_pmu_regs); | ||
551 | } | ||
552 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = { | ||
553 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | ||
554 | .access = PL1_R, .accessfn = access_lor_ns, | ||
555 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
556 | - REGINFO_SENTINEL | ||
557 | }; | ||
558 | |||
559 | #ifdef TARGET_AARCH64 | ||
560 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = { | ||
561 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | ||
562 | .access = PL1_RW, .accessfn = access_pauth, | ||
563 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, | ||
564 | - REGINFO_SENTINEL | ||
565 | }; | ||
566 | |||
567 | static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
568 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
569 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, | ||
570 | .access = PL3_W, .type = ARM_CP_NO_RAW, | ||
571 | .writefn = tlbi_aa64_rvae3_write }, | ||
572 | - REGINFO_SENTINEL | ||
573 | }; | ||
574 | |||
575 | static const ARMCPRegInfo tlbios_reginfo[] = { | ||
576 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
577 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, | ||
578 | .access = PL3_W, .type = ARM_CP_NO_RAW, | ||
579 | .writefn = tlbi_aa64_vae3is_write }, | ||
580 | - REGINFO_SENTINEL | ||
581 | }; | ||
582 | |||
583 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | ||
584 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rndr_reginfo[] = { | ||
585 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | ||
586 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | ||
587 | .access = PL0_R, .readfn = rndr_readfn }, | ||
588 | - REGINFO_SENTINEL | ||
589 | }; | ||
590 | |||
591 | #ifndef CONFIG_USER_ONLY | ||
592 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = { | ||
593 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | ||
594 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | ||
595 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, | ||
596 | - REGINFO_SENTINEL | ||
597 | }; | ||
598 | |||
599 | static const ARMCPRegInfo dcpodp_reg[] = { | ||
600 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = { | ||
601 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | ||
602 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | ||
603 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, | ||
604 | - REGINFO_SENTINEL | ||
605 | }; | ||
606 | #endif /*CONFIG_USER_ONLY*/ | ||
607 | |||
608 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = { | ||
609 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | ||
610 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | ||
611 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
612 | - REGINFO_SENTINEL | ||
613 | }; | ||
614 | |||
615 | static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | ||
616 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | ||
617 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | ||
618 | .type = ARM_CP_CONST, .access = PL0_RW, }, | ||
619 | - REGINFO_SENTINEL | ||
620 | }; | ||
621 | |||
622 | static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
623 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
624 | .accessfn = aa64_zva_access, | ||
625 | #endif | ||
626 | }, | ||
627 | - REGINFO_SENTINEL | ||
628 | }; | ||
629 | |||
630 | #endif | ||
631 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = { | ||
632 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | ||
633 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | ||
634 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
635 | - REGINFO_SENTINEL | ||
636 | }; | ||
637 | |||
638 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
639 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = { | ||
640 | .access = PL1_R, | ||
641 | .accessfn = access_aa64_tid2, | ||
642 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, | ||
643 | - REGINFO_SENTINEL | ||
644 | }; | ||
645 | |||
646 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | ||
647 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = { | ||
648 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | ||
649 | .accessfn = access_joscr_jmcr, | ||
650 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
651 | - REGINFO_SENTINEL | ||
652 | }; | ||
653 | |||
654 | static const ARMCPRegInfo vhe_reginfo[] = { | ||
655 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = { | ||
656 | .access = PL2_RW, .accessfn = e2h_access, | ||
657 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | ||
658 | #endif | ||
659 | - REGINFO_SENTINEL | ||
660 | }; | ||
661 | |||
662 | #ifndef CONFIG_USER_ONLY | ||
663 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = { | ||
664 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | ||
665 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
666 | .writefn = ats_write64 }, | ||
667 | - REGINFO_SENTINEL | ||
668 | }; | ||
669 | |||
670 | static const ARMCPRegInfo ats1cp_reginfo[] = { | ||
671 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = { | ||
672 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | ||
673 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
674 | .writefn = ats_write }, | ||
675 | - REGINFO_SENTINEL | ||
676 | }; | ||
677 | #endif | ||
678 | |||
679 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | ||
680 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | ||
681 | .access = PL2_RW, .type = ARM_CP_CONST, | ||
682 | .resetvalue = 0 }, | ||
683 | - REGINFO_SENTINEL | ||
684 | }; | ||
685 | |||
686 | void register_cp_regs_for_features(ARMCPU *cpu) | ||
687 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
688 | .access = PL1_R, .type = ARM_CP_CONST, | ||
689 | .accessfn = access_aa32_tid3, | ||
690 | .resetvalue = cpu->isar.id_isar6 }, | ||
691 | - REGINFO_SENTINEL | ||
692 | }; | ||
693 | define_arm_cp_regs(cpu, v6_idregs); | ||
694 | define_arm_cp_regs(cpu, v6_cp_reginfo); | ||
695 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
696 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | ||
697 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
698 | .resetvalue = cpu->pmceid1 }, | ||
699 | - REGINFO_SENTINEL | ||
700 | }; | ||
701 | #ifdef CONFIG_USER_ONLY | ||
702 | ARMCPRegUserSpaceInfo v8_user_idregs[] = { | ||
703 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
704 | .exported_bits = 0x000000f0ffffffff }, | ||
705 | { .name = "ID_AA64ISAR*_EL1_RESERVED", | ||
706 | .is_glob = true }, | ||
707 | - REGUSERINFO_SENTINEL | ||
708 | }; | ||
709 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | ||
710 | #endif | ||
711 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
712 | .access = PL2_RW, | ||
713 | .resetvalue = vmpidr_def, | ||
714 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | ||
715 | - REGINFO_SENTINEL | ||
716 | }; | ||
717 | define_arm_cp_regs(cpu, vpidr_regs); | ||
718 | define_arm_cp_regs(cpu, el2_cp_reginfo); | ||
719 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
720 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
721 | .type = ARM_CP_NO_RAW, | ||
722 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | ||
723 | - REGINFO_SENTINEL | ||
724 | }; | ||
725 | define_arm_cp_regs(cpu, vpidr_regs); | ||
726 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); | ||
727 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
728 | .raw_writefn = raw_write, .writefn = sctlr_write, | ||
729 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | ||
730 | .resetvalue = cpu->reset_sctlr }, | ||
731 | - REGINFO_SENTINEL | ||
732 | }; | ||
733 | |||
734 | define_arm_cp_regs(cpu, el3_regs); | ||
735 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
736 | { .name = "DUMMY", | ||
737 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | ||
738 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
739 | - REGINFO_SENTINEL | ||
740 | }; | ||
741 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { | ||
742 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
743 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
744 | .access = PL1_R, | ||
745 | .accessfn = access_aa64_tid1, | ||
746 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, | ||
747 | - REGINFO_SENTINEL | ||
748 | }; | ||
749 | ARMCPRegInfo id_cp_reginfo[] = { | ||
750 | /* These are common to v8 and pre-v8 */ | ||
751 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
752 | .access = PL1_R, | ||
753 | .accessfn = access_aa32_tid1, | ||
754 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
755 | - REGINFO_SENTINEL | ||
756 | }; | ||
757 | /* TLBTR is specific to VMSA */ | ||
758 | ARMCPRegInfo id_tlbtr_reginfo = { | ||
759 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
760 | { .name = "MIDR_EL1", | ||
761 | .exported_bits = 0x00000000ffffffff }, | ||
762 | { .name = "REVIDR_EL1" }, | ||
763 | - REGUSERINFO_SENTINEL | ||
764 | }; | ||
765 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | ||
766 | #endif | ||
767 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | ||
768 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | ||
769 | - ARMCPRegInfo *r; | ||
770 | + size_t i; | ||
771 | /* Register the blanket "writes ignored" value first to cover the | ||
772 | * whole space. Then update the specific ID registers to allow write | ||
773 | * access, so that they ignore writes rather than causing them to | ||
774 | * UNDEF. | ||
775 | */ | ||
776 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | ||
777 | - for (r = id_pre_v8_midr_cp_reginfo; | ||
778 | - r->type != ARM_CP_SENTINEL; r++) { | ||
779 | - r->access = PL1_RW; | ||
780 | + for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { | ||
781 | + id_pre_v8_midr_cp_reginfo[i].access = PL1_RW; | ||
782 | } | ||
783 | - for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { | ||
784 | - r->access = PL1_RW; | ||
785 | + for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { | ||
786 | + id_cp_reginfo[i].access = PL1_RW; | ||
787 | } | ||
788 | id_mpuir_reginfo.access = PL1_RW; | ||
789 | id_tlbtr_reginfo.access = PL1_RW; | ||
790 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
791 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
792 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | ||
793 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | ||
794 | - REGINFO_SENTINEL | ||
795 | }; | ||
796 | #ifdef CONFIG_USER_ONLY | ||
797 | ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | ||
798 | { .name = "MPIDR_EL1", | ||
799 | .fixed_bits = 0x0000000080000000 }, | ||
800 | - REGUSERINFO_SENTINEL | ||
801 | }; | ||
802 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | ||
803 | #endif | ||
804 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
805 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | ||
806 | .access = PL3_RW, .type = ARM_CP_CONST, | ||
807 | .resetvalue = 0 }, | ||
808 | - REGINFO_SENTINEL | ||
809 | }; | ||
810 | define_arm_cp_regs(cpu, auxcr_reginfo); | ||
811 | if (cpu_isar_feature(aa32_ac2, cpu)) { | ||
812 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
813 | .type = ARM_CP_CONST, | ||
814 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | ||
815 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | ||
816 | - REGINFO_SENTINEL | ||
817 | }; | ||
818 | /* We don't implement a r/w 64 bit CBAR currently */ | ||
819 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | ||
820 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
821 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | ||
822 | offsetof(CPUARMState, cp15.vbar_ns) }, | ||
823 | .resetvalue = 0 }, | ||
824 | - REGINFO_SENTINEL | ||
825 | }; | ||
826 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | ||
827 | } | ||
828 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
829 | r->writefn); | ||
830 | } | 51 | } |
831 | } | 52 | } |
832 | - /* Bad type field probably means missing sentinel at end of reg list */ | 53 | |
833 | - assert(cptype_valid(r->type)); | 54 | - if (which == 3) { |
55 | - parts_default_nan(a, s); | ||
56 | - return a; | ||
57 | - } | ||
58 | - | ||
59 | switch (which) { | ||
60 | case 0: | ||
61 | break; | ||
62 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
63 | parts_silence_nan(a, s); | ||
64 | } | ||
65 | return a; | ||
834 | + | 66 | + |
835 | for (crm = crmmin; crm <= crmmax; crm++) { | 67 | + default_nan: |
836 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | 68 | + parts_default_nan(a, s); |
837 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | 69 | + return a; |
838 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
839 | } | ||
840 | } | 70 | } |
841 | 71 | ||
842 | -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | 72 | /* |
843 | - const ARMCPRegInfo *regs, void *opaque) | ||
844 | +/* Define a whole list of registers */ | ||
845 | +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, | ||
846 | + void *opaque, size_t len) | ||
847 | { | ||
848 | - /* Define a whole list of registers */ | ||
849 | - const ARMCPRegInfo *r; | ||
850 | - for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | ||
851 | - define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | ||
852 | + size_t i; | ||
853 | + for (i = 0; i < len; ++i) { | ||
854 | + define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); | ||
855 | } | ||
856 | } | ||
857 | |||
858 | @@ -XXX,XX +XXX,XX @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | ||
859 | * user-space cannot alter any values and dynamic values pertaining to | ||
860 | * execution state are hidden from user space view anyway. | ||
861 | */ | ||
862 | -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) | ||
863 | +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, | ||
864 | + const ARMCPRegUserSpaceInfo *mods, | ||
865 | + size_t mods_len) | ||
866 | { | ||
867 | - const ARMCPRegUserSpaceInfo *m; | ||
868 | - ARMCPRegInfo *r; | ||
869 | - | ||
870 | - for (m = mods; m->name; m++) { | ||
871 | + for (size_t mi = 0; mi < mods_len; ++mi) { | ||
872 | + const ARMCPRegUserSpaceInfo *m = mods + mi; | ||
873 | GPatternSpec *pat = NULL; | ||
874 | + | ||
875 | if (m->is_glob) { | ||
876 | pat = g_pattern_spec_new(m->name); | ||
877 | } | ||
878 | - for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | ||
879 | + for (size_t ri = 0; ri < regs_len; ++ri) { | ||
880 | + ARMCPRegInfo *r = regs + ri; | ||
881 | + | ||
882 | if (pat && g_pattern_match_string(pat, r->name)) { | ||
883 | r->type = ARM_CP_CONST; | ||
884 | r->access = PL0U_R; | ||
885 | -- | 73 | -- |
886 | 2.25.1 | 74 | 2.34.1 |
887 | 75 | ||
888 | 76 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Since e03b56863d2bc, our host endian indicator is unconditionally | 3 | Assign the pointer return value to 'a' directly, |
4 | set, which means that we can use a normal C condition. | 4 | rather than going through an intermediary index. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20220501055028.646596-20-richard.henderson@linaro.org | 8 | Message-id: 20241203203949.483774-5-richard.henderson@linaro.org |
9 | [PMM: quote correct git hash in commit message] | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/helper.c | 9 +++------ | 11 | fpu/softfloat-parts.c.inc | 32 ++++++++++---------------------- |
13 | 1 file changed, 3 insertions(+), 6 deletions(-) | 12 | 1 file changed, 10 insertions(+), 22 deletions(-) |
14 | 13 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 16 | --- a/fpu/softfloat-parts.c.inc |
18 | +++ b/target/arm/helper.c | 17 | +++ b/fpu/softfloat-parts.c.inc |
19 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
20 | r2->type |= ARM_CP_ALIAS; | 19 | FloatPartsN *c, float_status *s, |
20 | int ab_mask, int abc_mask) | ||
21 | { | ||
22 | - int which; | ||
23 | bool infzero = (ab_mask == float_cmask_infzero); | ||
24 | bool have_snan = (abc_mask & float_cmask_snan); | ||
25 | + FloatPartsN *ret; | ||
26 | |||
27 | if (unlikely(have_snan)) { | ||
28 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
30 | default: | ||
31 | g_assert_not_reached(); | ||
21 | } | 32 | } |
22 | 33 | - which = 2; | |
23 | - if (r->state == ARM_CP_STATE_BOTH) { | 34 | + ret = c; |
24 | -#if HOST_BIG_ENDIAN | 35 | } else { |
25 | - if (r2->fieldoffset) { | 36 | - FloatClass cls[3] = { a->cls, b->cls, c->cls }; |
26 | - r2->fieldoffset += sizeof(uint32_t); | 37 | + FloatPartsN *val[3] = { a, b, c }; |
27 | - } | 38 | Float3NaNPropRule rule = s->float_3nan_prop_rule; |
28 | -#endif | 39 | |
29 | + if (HOST_BIG_ENDIAN && | 40 | assert(rule != float_3nan_prop_none); |
30 | + r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | 41 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { |
31 | + r2->fieldoffset += sizeof(uint32_t); | 42 | /* We have at least one SNaN input and should prefer it */ |
43 | do { | ||
44 | - which = rule & R_3NAN_1ST_MASK; | ||
45 | + ret = val[rule & R_3NAN_1ST_MASK]; | ||
46 | rule >>= R_3NAN_1ST_LENGTH; | ||
47 | - } while (!is_snan(cls[which])); | ||
48 | + } while (!is_snan(ret->cls)); | ||
49 | } else { | ||
50 | do { | ||
51 | - which = rule & R_3NAN_1ST_MASK; | ||
52 | + ret = val[rule & R_3NAN_1ST_MASK]; | ||
53 | rule >>= R_3NAN_1ST_LENGTH; | ||
54 | - } while (!is_nan(cls[which])); | ||
55 | + } while (!is_nan(ret->cls)); | ||
32 | } | 56 | } |
33 | } | 57 | } |
34 | 58 | ||
59 | - switch (which) { | ||
60 | - case 0: | ||
61 | - break; | ||
62 | - case 1: | ||
63 | - a = b; | ||
64 | - break; | ||
65 | - case 2: | ||
66 | - a = c; | ||
67 | - break; | ||
68 | - default: | ||
69 | - g_assert_not_reached(); | ||
70 | + if (is_snan(ret->cls)) { | ||
71 | + parts_silence_nan(ret, s); | ||
72 | } | ||
73 | - if (is_snan(a->cls)) { | ||
74 | - parts_silence_nan(a, s); | ||
75 | - } | ||
76 | - return a; | ||
77 | + return ret; | ||
78 | |||
79 | default_nan: | ||
80 | parts_default_nan(a, s); | ||
35 | -- | 81 | -- |
36 | 2.25.1 | 82 | 2.34.1 |
83 | |||
84 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Give this enum a name and use in ARMCPRegInfo, | 3 | While all indices into val[] should be in [0-2], the mask |
4 | add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. | 4 | applied is two bits. To help static analysis see there is |
5 | no possibility of read beyond the end of the array, pad the | ||
6 | array to 4 entries, with the final being (implicitly) NULL. | ||
5 | 7 | ||
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220501055028.646596-9-richard.henderson@linaro.org | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Message-id: 20241203203949.483774-6-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | target/arm/cpregs.h | 6 +++--- | 13 | fpu/softfloat-parts.c.inc | 2 +- |
13 | target/arm/helper.c | 6 ++++-- | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
14 | 2 files changed, 7 insertions(+), 5 deletions(-) | ||
15 | 15 | ||
16 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpregs.h | 18 | --- a/fpu/softfloat-parts.c.inc |
19 | +++ b/target/arm/cpregs.h | 19 | +++ b/fpu/softfloat-parts.c.inc |
20 | @@ -XXX,XX +XXX,XX @@ enum { | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
21 | * Note that we rely on the values of these enums as we iterate through | 21 | } |
22 | * the various states in some places. | 22 | ret = c; |
23 | */ | 23 | } else { |
24 | -enum { | 24 | - FloatPartsN *val[3] = { a, b, c }; |
25 | +typedef enum { | 25 | + FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c }; |
26 | ARM_CP_STATE_AA32 = 0, | 26 | Float3NaNPropRule rule = s->float_3nan_prop_rule; |
27 | ARM_CP_STATE_AA64 = 1, | 27 | |
28 | ARM_CP_STATE_BOTH = 2, | 28 | assert(rule != float_3nan_prop_none); |
29 | -}; | ||
30 | +} CPState; | ||
31 | |||
32 | /* | ||
33 | * ARM CP register secure state flags. These flags identify security state | ||
34 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { | ||
35 | uint8_t opc1; | ||
36 | uint8_t opc2; | ||
37 | /* Execution state in which this register is visible: ARM_CP_STATE_* */ | ||
38 | - int state; | ||
39 | + CPState state; | ||
40 | /* Register type: ARM_CP_* bits/values */ | ||
41 | int type; | ||
42 | /* Access rights: PL*_[RW] */ | ||
43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/helper.c | ||
46 | +++ b/target/arm/helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) | ||
48 | } | ||
49 | |||
50 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
51 | - void *opaque, int state, int secstate, | ||
52 | + void *opaque, CPState state, int secstate, | ||
53 | int crm, int opc1, int opc2, | ||
54 | const char *name) | ||
55 | { | ||
56 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
57 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | ||
58 | * the register, if any. | ||
59 | */ | ||
60 | - int crm, opc1, opc2, state; | ||
61 | + int crm, opc1, opc2; | ||
62 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; | ||
63 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | ||
64 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | ||
65 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | ||
66 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | ||
67 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | ||
68 | + CPState state; | ||
69 | + | ||
70 | /* 64 bit registers have only CRm and Opc1 fields */ | ||
71 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | ||
72 | /* op0 only exists in the AArch64 encodings */ | ||
73 | -- | 29 | -- |
74 | 2.25.1 | 30 | 2.34.1 |
75 | 31 | ||
76 | 32 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Put most of the value writeback to the same place, | 3 | This function is part of the public interface and |
4 | and improve the comment that goes with them. | 4 | is not "specialized" to any target in any way. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20220501055028.646596-15-richard.henderson@linaro.org | 8 | Message-id: 20241203203949.483774-7-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/helper.c | 28 ++++++++++++---------------- | 11 | fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++ |
12 | 1 file changed, 12 insertions(+), 16 deletions(-) | 12 | fpu/softfloat-specialize.c.inc | 52 ---------------------------------- |
13 | 2 files changed, 52 insertions(+), 52 deletions(-) | ||
13 | 14 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 17 | --- a/fpu/softfloat.c |
17 | +++ b/target/arm/helper.c | 18 | +++ b/fpu/softfloat.c |
18 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
19 | *r2 = *r; | 20 | *zExpPtr = 1 - shiftCount; |
20 | r2->name = memcpy(r2 + 1, name, name_len); | 21 | } |
21 | 22 | ||
22 | - /* Reset the secure state to the specific incoming state. This is | 23 | +/*---------------------------------------------------------------------------- |
23 | - * necessary as the register may have been defined with both states. | 24 | +| Takes two extended double-precision floating-point values `a' and `b', one |
24 | + /* | 25 | +| of which is a NaN, and returns the appropriate NaN result. If either `a' or |
25 | + * Update fields to match the instantiation, overwiting wildcards | 26 | +| `b' is a signaling NaN, the invalid exception is raised. |
26 | + * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. | 27 | +*----------------------------------------------------------------------------*/ |
27 | */ | 28 | + |
28 | + r2->cp = cp; | 29 | +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
29 | + r2->crm = crm; | 30 | +{ |
30 | + r2->opc1 = opc1; | 31 | + bool aIsLargerSignificand; |
31 | + r2->opc2 = opc2; | 32 | + FloatClass a_cls, b_cls; |
32 | + r2->state = state; | 33 | + |
33 | r2->secure = secstate; | 34 | + /* This is not complete, but is good enough for pickNaN. */ |
34 | + if (opaque) { | 35 | + a_cls = (!floatx80_is_any_nan(a) |
35 | + r2->opaque = opaque; | 36 | + ? float_class_normal |
37 | + : floatx80_is_signaling_nan(a, status) | ||
38 | + ? float_class_snan | ||
39 | + : float_class_qnan); | ||
40 | + b_cls = (!floatx80_is_any_nan(b) | ||
41 | + ? float_class_normal | ||
42 | + : floatx80_is_signaling_nan(b, status) | ||
43 | + ? float_class_snan | ||
44 | + : float_class_qnan); | ||
45 | + | ||
46 | + if (is_snan(a_cls) || is_snan(b_cls)) { | ||
47 | + float_raise(float_flag_invalid, status); | ||
36 | + } | 48 | + } |
37 | 49 | + | |
38 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | 50 | + if (status->default_nan_mode) { |
39 | /* Register is banked (using both entries in array). | 51 | + return floatx80_default_nan(status); |
40 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 52 | + } |
41 | #endif | 53 | + |
42 | } | 54 | + if (a.low < b.low) { |
43 | } | 55 | + aIsLargerSignificand = 0; |
44 | - if (opaque) { | 56 | + } else if (b.low < a.low) { |
45 | - r2->opaque = opaque; | 57 | + aIsLargerSignificand = 1; |
58 | + } else { | ||
59 | + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
60 | + } | ||
61 | + | ||
62 | + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | ||
63 | + if (is_snan(b_cls)) { | ||
64 | + return floatx80_silence_nan(b, status); | ||
65 | + } | ||
66 | + return b; | ||
67 | + } else { | ||
68 | + if (is_snan(a_cls)) { | ||
69 | + return floatx80_silence_nan(a, status); | ||
70 | + } | ||
71 | + return a; | ||
72 | + } | ||
73 | +} | ||
74 | + | ||
75 | /*---------------------------------------------------------------------------- | ||
76 | | Takes an abstract floating-point value having sign `zSign', exponent `zExp', | ||
77 | | and extended significand formed by the concatenation of `zSig0' and `zSig1', | ||
78 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/fpu/softfloat-specialize.c.inc | ||
81 | +++ b/fpu/softfloat-specialize.c.inc | ||
82 | @@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) | ||
83 | return a; | ||
84 | } | ||
85 | |||
86 | -/*---------------------------------------------------------------------------- | ||
87 | -| Takes two extended double-precision floating-point values `a' and `b', one | ||
88 | -| of which is a NaN, and returns the appropriate NaN result. If either `a' or | ||
89 | -| `b' is a signaling NaN, the invalid exception is raised. | ||
90 | -*----------------------------------------------------------------------------*/ | ||
91 | - | ||
92 | -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) | ||
93 | -{ | ||
94 | - bool aIsLargerSignificand; | ||
95 | - FloatClass a_cls, b_cls; | ||
96 | - | ||
97 | - /* This is not complete, but is good enough for pickNaN. */ | ||
98 | - a_cls = (!floatx80_is_any_nan(a) | ||
99 | - ? float_class_normal | ||
100 | - : floatx80_is_signaling_nan(a, status) | ||
101 | - ? float_class_snan | ||
102 | - : float_class_qnan); | ||
103 | - b_cls = (!floatx80_is_any_nan(b) | ||
104 | - ? float_class_normal | ||
105 | - : floatx80_is_signaling_nan(b, status) | ||
106 | - ? float_class_snan | ||
107 | - : float_class_qnan); | ||
108 | - | ||
109 | - if (is_snan(a_cls) || is_snan(b_cls)) { | ||
110 | - float_raise(float_flag_invalid, status); | ||
46 | - } | 111 | - } |
47 | - /* reginfo passed to helpers is correct for the actual access, | 112 | - |
48 | - * and is never ARM_CP_STATE_BOTH: | 113 | - if (status->default_nan_mode) { |
49 | - */ | 114 | - return floatx80_default_nan(status); |
50 | - r2->state = state; | 115 | - } |
51 | - /* Make sure reginfo passed to helpers for wildcarded regs | 116 | - |
52 | - * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | 117 | - if (a.low < b.low) { |
53 | - */ | 118 | - aIsLargerSignificand = 0; |
54 | - r2->cp = cp; | 119 | - } else if (b.low < a.low) { |
55 | - r2->crm = crm; | 120 | - aIsLargerSignificand = 1; |
56 | - r2->opc1 = opc1; | 121 | - } else { |
57 | - r2->opc2 = opc2; | 122 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; |
58 | + | 123 | - } |
59 | /* By convention, for wildcarded registers only the first | 124 | - |
60 | * entry is used for migration; the others are marked as | 125 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
61 | * ALIAS so we don't try to transfer the register | 126 | - if (is_snan(b_cls)) { |
127 | - return floatx80_silence_nan(b, status); | ||
128 | - } | ||
129 | - return b; | ||
130 | - } else { | ||
131 | - if (is_snan(a_cls)) { | ||
132 | - return floatx80_silence_nan(a, status); | ||
133 | - } | ||
134 | - return a; | ||
135 | - } | ||
136 | -} | ||
137 | - | ||
138 | /*---------------------------------------------------------------------------- | ||
139 | | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | ||
140 | | NaN; otherwise returns 0. | ||
62 | -- | 141 | -- |
63 | 2.25.1 | 142 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Computing isbanked only once makes the code | 3 | Unpacking and repacking the parts may be slightly more work |
4 | a bit easier to read. | 4 | than we did before, but we get to reuse more code. For a |
5 | code path handling exceptional values, this is an improvement. | ||
5 | 6 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20241203203949.483774-8-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20220501055028.646596-17-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | 11 | --- |
11 | target/arm/helper.c | 6 ++++-- | 12 | fpu/softfloat.c | 43 +++++-------------------------------------- |
12 | 1 file changed, 4 insertions(+), 2 deletions(-) | 13 | 1 file changed, 5 insertions(+), 38 deletions(-) |
13 | 14 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 17 | --- a/fpu/softfloat.c |
17 | +++ b/target/arm/helper.c | 18 | +++ b/fpu/softfloat.c |
18 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
19 | bool is64 = r->type & ARM_CP_64BIT; | 20 | |
20 | bool ns = secstate & ARM_CP_SECSTATE_NS; | 21 | floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
21 | int cp = r->cp; | 22 | { |
22 | + bool isbanked; | 23 | - bool aIsLargerSignificand; |
23 | size_t name_len; | 24 | - FloatClass a_cls, b_cls; |
24 | 25 | + FloatParts128 pa, pb, *pr; | |
25 | switch (state) { | 26 | |
26 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 27 | - /* This is not complete, but is good enough for pickNaN. */ |
27 | r2->opaque = opaque; | 28 | - a_cls = (!floatx80_is_any_nan(a) |
29 | - ? float_class_normal | ||
30 | - : floatx80_is_signaling_nan(a, status) | ||
31 | - ? float_class_snan | ||
32 | - : float_class_qnan); | ||
33 | - b_cls = (!floatx80_is_any_nan(b) | ||
34 | - ? float_class_normal | ||
35 | - : floatx80_is_signaling_nan(b, status) | ||
36 | - ? float_class_snan | ||
37 | - : float_class_qnan); | ||
38 | - | ||
39 | - if (is_snan(a_cls) || is_snan(b_cls)) { | ||
40 | - float_raise(float_flag_invalid, status); | ||
41 | - } | ||
42 | - | ||
43 | - if (status->default_nan_mode) { | ||
44 | + if (!floatx80_unpack_canonical(&pa, a, status) || | ||
45 | + !floatx80_unpack_canonical(&pb, b, status)) { | ||
46 | return floatx80_default_nan(status); | ||
28 | } | 47 | } |
29 | 48 | ||
30 | - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | 49 | - if (a.low < b.low) { |
31 | + isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | 50 | - aIsLargerSignificand = 0; |
32 | + if (isbanked) { | 51 | - } else if (b.low < a.low) { |
33 | /* Register is banked (using both entries in array). | 52 | - aIsLargerSignificand = 1; |
34 | * Overwriting fieldoffset as the array is only used to define | 53 | - } else { |
35 | * banked registers but later only fieldoffset is used. | 54 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; |
36 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 55 | - } |
37 | } | 56 | - |
38 | 57 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | |
39 | if (state == ARM_CP_STATE_AA32) { | 58 | - if (is_snan(b_cls)) { |
40 | - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | 59 | - return floatx80_silence_nan(b, status); |
41 | + if (isbanked) { | 60 | - } |
42 | /* If the register is banked then we don't need to migrate or | 61 | - return b; |
43 | * reset the 32-bit instance in certain cases: | 62 | - } else { |
44 | * | 63 | - if (is_snan(a_cls)) { |
64 | - return floatx80_silence_nan(a, status); | ||
65 | - } | ||
66 | - return a; | ||
67 | - } | ||
68 | + pr = parts_pick_nan(&pa, &pb, status); | ||
69 | + return floatx80_round_pack_canonical(pr, status); | ||
70 | } | ||
71 | |||
72 | /*---------------------------------------------------------------------------- | ||
45 | -- | 73 | -- |
46 | 2.25.1 | 74 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Move the computation of key to the top of the function. | 3 | Inline pickNaN into its only caller. This makes one assert |
4 | Hoist the resolution of cp as well, as an input to the | 4 | redundant with the immediately preceding IF. |
5 | computation of key. | ||
6 | |||
7 | This will be required by a subsequent patch. | ||
8 | 5 | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
11 | Message-id: 20220501055028.646596-14-richard.henderson@linaro.org | 8 | Message-id: 20241203203949.483774-9-richard.henderson@linaro.org |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | target/arm/helper.c | 49 +++++++++++++++++++++++++-------------------- | 11 | fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++---- |
15 | 1 file changed, 27 insertions(+), 22 deletions(-) | 12 | fpu/softfloat-specialize.c.inc | 96 ---------------------------------- |
16 | 13 | 2 files changed, 73 insertions(+), 105 deletions(-) | |
17 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | |
15 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/helper.c | 17 | --- a/fpu/softfloat-parts.c.inc |
20 | +++ b/target/arm/helper.c | 18 | +++ b/fpu/softfloat-parts.c.inc |
21 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 19 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) |
22 | ARMCPRegInfo *r2; | 20 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
23 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | 21 | float_status *s) |
24 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; | 22 | { |
25 | + int cp = r->cp; | 23 | + int cmp, which; |
26 | size_t name_len; | 24 | + |
27 | 25 | if (is_snan(a->cls) || is_snan(b->cls)) { | |
28 | + switch (state) { | 26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
29 | + case ARM_CP_STATE_AA32: | 27 | } |
30 | + /* We assume it is a cp15 register if the .cp field is left unset. */ | 28 | |
31 | + if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { | 29 | if (s->default_nan_mode) { |
32 | + cp = 15; | 30 | parts_default_nan(a, s); |
31 | - } else { | ||
32 | - int cmp = frac_cmp(a, b); | ||
33 | - if (cmp == 0) { | ||
34 | - cmp = a->sign < b->sign; | ||
35 | - } | ||
36 | + return a; | ||
37 | + } | ||
38 | |||
39 | - if (pickNaN(a->cls, b->cls, cmp > 0, s)) { | ||
40 | - a = b; | ||
41 | - } | ||
42 | + cmp = frac_cmp(a, b); | ||
43 | + if (cmp == 0) { | ||
44 | + cmp = a->sign < b->sign; | ||
45 | + } | ||
46 | + | ||
47 | + switch (s->float_2nan_prop_rule) { | ||
48 | + case float_2nan_prop_s_ab: | ||
49 | if (is_snan(a->cls)) { | ||
50 | - parts_silence_nan(a, s); | ||
51 | + which = 0; | ||
52 | + } else if (is_snan(b->cls)) { | ||
53 | + which = 1; | ||
54 | + } else if (is_qnan(a->cls)) { | ||
55 | + which = 0; | ||
56 | + } else { | ||
57 | + which = 1; | ||
58 | } | ||
59 | + break; | ||
60 | + case float_2nan_prop_s_ba: | ||
61 | + if (is_snan(b->cls)) { | ||
62 | + which = 1; | ||
63 | + } else if (is_snan(a->cls)) { | ||
64 | + which = 0; | ||
65 | + } else if (is_qnan(b->cls)) { | ||
66 | + which = 1; | ||
67 | + } else { | ||
68 | + which = 0; | ||
33 | + } | 69 | + } |
34 | + key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); | 70 | + break; |
35 | + break; | 71 | + case float_2nan_prop_ab: |
36 | + case ARM_CP_STATE_AA64: | 72 | + which = is_nan(a->cls) ? 0 : 1; |
73 | + break; | ||
74 | + case float_2nan_prop_ba: | ||
75 | + which = is_nan(b->cls) ? 1 : 0; | ||
76 | + break; | ||
77 | + case float_2nan_prop_x87: | ||
37 | + /* | 78 | + /* |
38 | + * To allow abbreviation of ARMCPRegInfo definitions, we treat | 79 | + * This implements x87 NaN propagation rules: |
39 | + * cp == 0 as equivalent to the value for "standard guest-visible | 80 | + * SNaN + QNaN => return the QNaN |
40 | + * sysreg". STATE_BOTH definitions are also always "standard sysreg" | 81 | + * two SNaNs => return the one with the larger significand, silenced |
41 | + * in their AArch64 view (the .cp value may be non-zero for the | 82 | + * two QNaNs => return the one with the larger significand |
42 | + * benefit of the AArch32 view). | 83 | + * SNaN and a non-NaN => return the SNaN, silenced |
84 | + * QNaN and a non-NaN => return the QNaN | ||
85 | + * | ||
86 | + * If we get down to comparing significands and they are the same, | ||
87 | + * return the NaN with the positive sign bit (if any). | ||
43 | + */ | 88 | + */ |
44 | + if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { | 89 | + if (is_snan(a->cls)) { |
45 | + cp = CP_REG_ARM64_SYSREG_CP; | 90 | + if (is_snan(b->cls)) { |
91 | + which = cmp > 0 ? 0 : 1; | ||
92 | + } else { | ||
93 | + which = is_qnan(b->cls) ? 1 : 0; | ||
94 | + } | ||
95 | + } else if (is_qnan(a->cls)) { | ||
96 | + if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
97 | + which = 0; | ||
98 | + } else { | ||
99 | + which = cmp > 0 ? 0 : 1; | ||
100 | + } | ||
101 | + } else { | ||
102 | + which = 1; | ||
46 | + } | 103 | + } |
47 | + key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); | ||
48 | + break; | 104 | + break; |
49 | + default: | 105 | + default: |
50 | + g_assert_not_reached(); | 106 | + g_assert_not_reached(); |
51 | + } | 107 | + } |
52 | + | 108 | + |
53 | /* Combine cpreg and name into one allocation. */ | 109 | + if (which) { |
54 | name_len = strlen(name) + 1; | 110 | + a = b; |
55 | r2 = g_malloc(sizeof(*r2) + name_len); | 111 | + } |
56 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 112 | + if (is_snan(a->cls)) { |
57 | } | 113 | + parts_silence_nan(a, s); |
58 | 114 | } | |
59 | if (r->state == ARM_CP_STATE_BOTH) { | 115 | return a; |
60 | - /* We assume it is a cp15 register if the .cp field is left unset. | 116 | } |
61 | - */ | 117 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
62 | - if (r2->cp == 0) { | 118 | index XXXXXXX..XXXXXXX 100644 |
63 | - r2->cp = 15; | 119 | --- a/fpu/softfloat-specialize.c.inc |
120 | +++ b/fpu/softfloat-specialize.c.inc | ||
121 | @@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status) | ||
122 | } | ||
123 | } | ||
124 | |||
125 | -/*---------------------------------------------------------------------------- | ||
126 | -| Select which NaN to propagate for a two-input operation. | ||
127 | -| IEEE754 doesn't specify all the details of this, so the | ||
128 | -| algorithm is target-specific. | ||
129 | -| The routine is passed various bits of information about the | ||
130 | -| two NaNs and should return 0 to select NaN a and 1 for NaN b. | ||
131 | -| Note that signalling NaNs are always squashed to quiet NaNs | ||
132 | -| by the caller, by calling floatXX_silence_nan() before | ||
133 | -| returning them. | ||
134 | -| | ||
135 | -| aIsLargerSignificand is only valid if both a and b are NaNs | ||
136 | -| of some kind, and is true if a has the larger significand, | ||
137 | -| or if both a and b have the same significand but a is | ||
138 | -| positive but b is negative. It is only needed for the x87 | ||
139 | -| tie-break rule. | ||
140 | -*----------------------------------------------------------------------------*/ | ||
141 | - | ||
142 | -static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
143 | - bool aIsLargerSignificand, float_status *status) | ||
144 | -{ | ||
145 | - /* | ||
146 | - * We guarantee not to require the target to tell us how to | ||
147 | - * pick a NaN if we're always returning the default NaN. | ||
148 | - * But if we're not in default-NaN mode then the target must | ||
149 | - * specify via set_float_2nan_prop_rule(). | ||
150 | - */ | ||
151 | - assert(!status->default_nan_mode); | ||
152 | - | ||
153 | - switch (status->float_2nan_prop_rule) { | ||
154 | - case float_2nan_prop_s_ab: | ||
155 | - if (is_snan(a_cls)) { | ||
156 | - return 0; | ||
157 | - } else if (is_snan(b_cls)) { | ||
158 | - return 1; | ||
159 | - } else if (is_qnan(a_cls)) { | ||
160 | - return 0; | ||
161 | - } else { | ||
162 | - return 1; | ||
163 | - } | ||
164 | - break; | ||
165 | - case float_2nan_prop_s_ba: | ||
166 | - if (is_snan(b_cls)) { | ||
167 | - return 1; | ||
168 | - } else if (is_snan(a_cls)) { | ||
169 | - return 0; | ||
170 | - } else if (is_qnan(b_cls)) { | ||
171 | - return 1; | ||
172 | - } else { | ||
173 | - return 0; | ||
174 | - } | ||
175 | - break; | ||
176 | - case float_2nan_prop_ab: | ||
177 | - if (is_nan(a_cls)) { | ||
178 | - return 0; | ||
179 | - } else { | ||
180 | - return 1; | ||
181 | - } | ||
182 | - break; | ||
183 | - case float_2nan_prop_ba: | ||
184 | - if (is_nan(b_cls)) { | ||
185 | - return 1; | ||
186 | - } else { | ||
187 | - return 0; | ||
188 | - } | ||
189 | - break; | ||
190 | - case float_2nan_prop_x87: | ||
191 | - /* | ||
192 | - * This implements x87 NaN propagation rules: | ||
193 | - * SNaN + QNaN => return the QNaN | ||
194 | - * two SNaNs => return the one with the larger significand, silenced | ||
195 | - * two QNaNs => return the one with the larger significand | ||
196 | - * SNaN and a non-NaN => return the SNaN, silenced | ||
197 | - * QNaN and a non-NaN => return the QNaN | ||
198 | - * | ||
199 | - * If we get down to comparing significands and they are the same, | ||
200 | - * return the NaN with the positive sign bit (if any). | ||
201 | - */ | ||
202 | - if (is_snan(a_cls)) { | ||
203 | - if (is_snan(b_cls)) { | ||
204 | - return aIsLargerSignificand ? 0 : 1; | ||
64 | - } | 205 | - } |
206 | - return is_qnan(b_cls) ? 1 : 0; | ||
207 | - } else if (is_qnan(a_cls)) { | ||
208 | - if (is_snan(b_cls) || !is_qnan(b_cls)) { | ||
209 | - return 0; | ||
210 | - } else { | ||
211 | - return aIsLargerSignificand ? 0 : 1; | ||
212 | - } | ||
213 | - } else { | ||
214 | - return 1; | ||
215 | - } | ||
216 | - default: | ||
217 | - g_assert_not_reached(); | ||
218 | - } | ||
219 | -} | ||
65 | - | 220 | - |
66 | #if HOST_BIG_ENDIAN | 221 | /*---------------------------------------------------------------------------- |
67 | if (r2->fieldoffset) { | 222 | | Returns 1 if the double-precision floating-point value `a' is a quiet |
68 | r2->fieldoffset += sizeof(uint32_t); | 223 | | NaN; otherwise returns 0. |
69 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
70 | #endif | ||
71 | } | ||
72 | } | ||
73 | - if (state == ARM_CP_STATE_AA64) { | ||
74 | - /* To allow abbreviation of ARMCPRegInfo | ||
75 | - * definitions, we treat cp == 0 as equivalent to | ||
76 | - * the value for "standard guest-visible sysreg". | ||
77 | - * STATE_BOTH definitions are also always "standard | ||
78 | - * sysreg" in their AArch64 view (the .cp value may | ||
79 | - * be non-zero for the benefit of the AArch32 view). | ||
80 | - */ | ||
81 | - if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { | ||
82 | - r2->cp = CP_REG_ARM64_SYSREG_CP; | ||
83 | - } | ||
84 | - key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | ||
85 | - r2->opc0, opc1, opc2); | ||
86 | - } else { | ||
87 | - key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); | ||
88 | - } | ||
89 | if (opaque) { | ||
90 | r2->opaque = opaque; | ||
91 | } | ||
92 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
93 | /* Make sure reginfo passed to helpers for wildcarded regs | ||
94 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | ||
95 | */ | ||
96 | + r2->cp = cp; | ||
97 | r2->crm = crm; | ||
98 | r2->opc1 = opc1; | ||
99 | r2->opc2 = opc2; | ||
100 | -- | 224 | -- |
101 | 2.25.1 | 225 | 2.34.1 |
226 | |||
227 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The new_key field is always non-zero -- drop the if. | 3 | Remember if there was an SNaN, and use that to simplify |
4 | float_2nan_prop_s_{ab,ba} to only the snan component. | ||
5 | Then, fall through to the corresponding | ||
6 | float_2nan_prop_{ab,ba} case to handle any remaining | ||
7 | nans, which must be quiet. | ||
4 | 8 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20220501055028.646596-11-richard.henderson@linaro.org | 11 | Message-id: 20241203203949.483774-10-richard.henderson@linaro.org |
8 | [PMM: reinstated dropped PL3_RW mask] | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | target/arm/helper.c | 23 +++++++++++------------ | 14 | fpu/softfloat-parts.c.inc | 32 ++++++++++++-------------------- |
12 | 1 file changed, 11 insertions(+), 12 deletions(-) | 15 | 1 file changed, 12 insertions(+), 20 deletions(-) |
13 | 16 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 19 | --- a/fpu/softfloat-parts.c.inc |
17 | +++ b/target/arm/helper.c | 20 | +++ b/fpu/softfloat-parts.c.inc |
18 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | 21 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) |
19 | 22 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | |
20 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | 23 | float_status *s) |
21 | const struct E2HAlias *a = &aliases[i]; | 24 | { |
22 | - ARMCPRegInfo *src_reg, *dst_reg; | 25 | + bool have_snan = false; |
23 | + ARMCPRegInfo *src_reg, *dst_reg, *new_reg; | 26 | int cmp, which; |
24 | + uint32_t *new_key; | 27 | |
25 | + bool ok; | 28 | if (is_snan(a->cls) || is_snan(b->cls)) { |
26 | 29 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | |
27 | if (a->feature && !a->feature(&cpu->isar)) { | 30 | + have_snan = true; |
28 | continue; | 31 | } |
29 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | 32 | |
30 | g_assert(src_reg->opaque == NULL); | 33 | if (s->default_nan_mode) { |
31 | 34 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | |
32 | /* Create alias before redirection so we dup the right data. */ | 35 | |
33 | - if (a->new_key) { | 36 | switch (s->float_2nan_prop_rule) { |
34 | - ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | 37 | case float_2nan_prop_s_ab: |
35 | - uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | 38 | - if (is_snan(a->cls)) { |
36 | - bool ok; | 39 | - which = 0; |
37 | + new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | 40 | - } else if (is_snan(b->cls)) { |
38 | + new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | 41 | - which = 1; |
39 | 42 | - } else if (is_qnan(a->cls)) { | |
40 | - new_reg->name = a->new_name; | 43 | - which = 0; |
41 | - new_reg->type |= ARM_CP_ALIAS; | 44 | - } else { |
42 | - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | 45 | - which = 1; |
43 | - new_reg->access &= PL2_RW | PL3_RW; | 46 | + if (have_snan) { |
44 | + new_reg->name = a->new_name; | 47 | + which = is_snan(a->cls) ? 0 : 1; |
45 | + new_reg->type |= ARM_CP_ALIAS; | 48 | + break; |
46 | + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | 49 | } |
47 | + new_reg->access &= PL2_RW | PL3_RW; | 50 | - break; |
48 | 51 | - case float_2nan_prop_s_ba: | |
49 | - ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | 52 | - if (is_snan(b->cls)) { |
50 | - g_assert(ok); | 53 | - which = 1; |
54 | - } else if (is_snan(a->cls)) { | ||
55 | - which = 0; | ||
56 | - } else if (is_qnan(b->cls)) { | ||
57 | - which = 1; | ||
58 | - } else { | ||
59 | - which = 0; | ||
51 | - } | 60 | - } |
52 | + ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | 61 | - break; |
53 | + g_assert(ok); | 62 | + /* fall through */ |
54 | 63 | case float_2nan_prop_ab: | |
55 | src_reg->opaque = dst_reg; | 64 | which = is_nan(a->cls) ? 0 : 1; |
56 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | 65 | break; |
66 | + case float_2nan_prop_s_ba: | ||
67 | + if (have_snan) { | ||
68 | + which = is_snan(b->cls) ? 1 : 0; | ||
69 | + break; | ||
70 | + } | ||
71 | + /* fall through */ | ||
72 | case float_2nan_prop_ba: | ||
73 | which = is_nan(b->cls) ? 1 : 0; | ||
74 | break; | ||
57 | -- | 75 | -- |
58 | 2.25.1 | 76 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Instead of defining ARM_CP_FLAG_MASK to remove flags, | 3 | Move the fractional comparison to the end of the |
4 | define ARM_CP_SPECIAL_MASK to isolate special cases. | 4 | float_2nan_prop_x87 case. This is not required for |
5 | Sort the specials to the low bits. Use an enum. | 5 | any other 2nan propagation rule. Reorganize the |
6 | 6 | x87 case itself to break out of the switch when the | |
7 | Split the large comment block so as to document each | 7 | fractional comparison is not required. |
8 | value separately. | ||
9 | 8 | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Message-id: 20220501055028.646596-6-richard.henderson@linaro.org | 11 | Message-id: 20241203203949.483774-11-richard.henderson@linaro.org |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 13 | --- |
15 | target/arm/cpregs.h | 130 +++++++++++++++++++++++-------------- | 14 | fpu/softfloat-parts.c.inc | 19 +++++++++---------- |
16 | target/arm/cpu.c | 4 +- | 15 | 1 file changed, 9 insertions(+), 10 deletions(-) |
17 | target/arm/helper.c | 4 +- | ||
18 | target/arm/translate-a64.c | 6 +- | ||
19 | target/arm/translate.c | 6 +- | ||
20 | 5 files changed, 92 insertions(+), 58 deletions(-) | ||
21 | 16 | ||
22 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
23 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/cpregs.h | 19 | --- a/fpu/softfloat-parts.c.inc |
25 | +++ b/target/arm/cpregs.h | 20 | +++ b/fpu/softfloat-parts.c.inc |
26 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
27 | #define TARGET_ARM_CPREGS_H | 22 | return a; |
28 | |||
29 | /* | ||
30 | - * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a | ||
31 | - * special-behaviour cp reg and bits [11..8] indicate what behaviour | ||
32 | - * it has. Otherwise it is a simple cp reg, where CONST indicates that | ||
33 | - * TCG can assume the value to be constant (ie load at translate time) | ||
34 | - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | ||
35 | - * indicates that the TB should not be ended after a write to this register | ||
36 | - * (the default is that the TB ends after cp writes). OVERRIDE permits | ||
37 | - * a register definition to override a previous definition for the | ||
38 | - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | ||
39 | - * old must have the OVERRIDE bit set. | ||
40 | - * ALIAS indicates that this register is an alias view of some underlying | ||
41 | - * state which is also visible via another register, and that the other | ||
42 | - * register is handling migration and reset; registers marked ALIAS will not be | ||
43 | - * migrated but may have their state set by syncing of register state from KVM. | ||
44 | - * NO_RAW indicates that this register has no underlying state and does not | ||
45 | - * support raw access for state saving/loading; it will not be used for either | ||
46 | - * migration or KVM state synchronization. (Typically this is for "registers" | ||
47 | - * which are actually used as instructions for cache maintenance and so on.) | ||
48 | - * IO indicates that this register does I/O and therefore its accesses | ||
49 | - * need to be marked with gen_io_start() and also end the TB. In particular, | ||
50 | - * registers which implement clocks or timers require this. | ||
51 | - * RAISES_EXC is for when the read or write hook might raise an exception; | ||
52 | - * the generated code will synchronize the CPU state before calling the hook | ||
53 | - * so that it is safe for the hook to call raise_exception(). | ||
54 | - * NEWEL is for writes to registers that might change the exception | ||
55 | - * level - typically on older ARM chips. For those cases we need to | ||
56 | - * re-read the new el when recomputing the translation flags. | ||
57 | + * ARMCPRegInfo type field bits: | ||
58 | */ | ||
59 | -#define ARM_CP_SPECIAL 0x0001 | ||
60 | -#define ARM_CP_CONST 0x0002 | ||
61 | -#define ARM_CP_64BIT 0x0004 | ||
62 | -#define ARM_CP_SUPPRESS_TB_END 0x0008 | ||
63 | -#define ARM_CP_OVERRIDE 0x0010 | ||
64 | -#define ARM_CP_ALIAS 0x0020 | ||
65 | -#define ARM_CP_IO 0x0040 | ||
66 | -#define ARM_CP_NO_RAW 0x0080 | ||
67 | -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) | ||
68 | -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) | ||
69 | -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | ||
70 | -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | ||
71 | -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | ||
72 | -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) | ||
73 | -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) | ||
74 | -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA | ||
75 | -#define ARM_CP_FPU 0x1000 | ||
76 | -#define ARM_CP_SVE 0x2000 | ||
77 | -#define ARM_CP_NO_GDB 0x4000 | ||
78 | -#define ARM_CP_RAISES_EXC 0x8000 | ||
79 | -#define ARM_CP_NEWEL 0x10000 | ||
80 | -/* Mask of only the flag bits in a type field */ | ||
81 | -#define ARM_CP_FLAG_MASK 0x1f0ff | ||
82 | +enum { | ||
83 | + /* | ||
84 | + * Register must be handled specially during translation. | ||
85 | + * The method is one of the values below: | ||
86 | + */ | ||
87 | + ARM_CP_SPECIAL_MASK = 0x000f, | ||
88 | + /* Special: no change to PE state: writes ignored, reads ignored. */ | ||
89 | + ARM_CP_NOP = 0x0001, | ||
90 | + /* Special: sysreg is WFI, for v5 and v6. */ | ||
91 | + ARM_CP_WFI = 0x0002, | ||
92 | + /* Special: sysreg is NZCV. */ | ||
93 | + ARM_CP_NZCV = 0x0003, | ||
94 | + /* Special: sysreg is CURRENTEL. */ | ||
95 | + ARM_CP_CURRENTEL = 0x0004, | ||
96 | + /* Special: sysreg is DC ZVA or similar. */ | ||
97 | + ARM_CP_DC_ZVA = 0x0005, | ||
98 | + ARM_CP_DC_GVA = 0x0006, | ||
99 | + ARM_CP_DC_GZVA = 0x0007, | ||
100 | + | ||
101 | + /* Flag: reads produce resetvalue; writes ignored. */ | ||
102 | + ARM_CP_CONST = 1 << 4, | ||
103 | + /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ | ||
104 | + ARM_CP_64BIT = 1 << 5, | ||
105 | + /* | ||
106 | + * Flag: TB should not be ended after a write to this register | ||
107 | + * (the default is that the TB ends after cp writes). | ||
108 | + */ | ||
109 | + ARM_CP_SUPPRESS_TB_END = 1 << 6, | ||
110 | + /* | ||
111 | + * Flag: Permit a register definition to override a previous definition | ||
112 | + * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new | ||
113 | + * or the old must have the ARM_CP_OVERRIDE bit set. | ||
114 | + */ | ||
115 | + ARM_CP_OVERRIDE = 1 << 7, | ||
116 | + /* | ||
117 | + * Flag: Register is an alias view of some underlying state which is also | ||
118 | + * visible via another register, and that the other register is handling | ||
119 | + * migration and reset; registers marked ARM_CP_ALIAS will not be migrated | ||
120 | + * but may have their state set by syncing of register state from KVM. | ||
121 | + */ | ||
122 | + ARM_CP_ALIAS = 1 << 8, | ||
123 | + /* | ||
124 | + * Flag: Register does I/O and therefore its accesses need to be marked | ||
125 | + * with gen_io_start() and also end the TB. In particular, registers which | ||
126 | + * implement clocks or timers require this. | ||
127 | + */ | ||
128 | + ARM_CP_IO = 1 << 9, | ||
129 | + /* | ||
130 | + * Flag: Register has no underlying state and does not support raw access | ||
131 | + * for state saving/loading; it will not be used for either migration or | ||
132 | + * KVM state synchronization. Typically this is for "registers" which are | ||
133 | + * actually used as instructions for cache maintenance and so on. | ||
134 | + */ | ||
135 | + ARM_CP_NO_RAW = 1 << 10, | ||
136 | + /* | ||
137 | + * Flag: The read or write hook might raise an exception; the generated | ||
138 | + * code will synchronize the CPU state before calling the hook so that it | ||
139 | + * is safe for the hook to call raise_exception(). | ||
140 | + */ | ||
141 | + ARM_CP_RAISES_EXC = 1 << 11, | ||
142 | + /* | ||
143 | + * Flag: Writes to the sysreg might change the exception level - typically | ||
144 | + * on older ARM chips. For those cases we need to re-read the new el when | ||
145 | + * recomputing the translation flags. | ||
146 | + */ | ||
147 | + ARM_CP_NEWEL = 1 << 12, | ||
148 | + /* | ||
149 | + * Flag: Access check for this sysreg is identical to accessing FPU state | ||
150 | + * from an instruction: use translation fp_access_check(). | ||
151 | + */ | ||
152 | + ARM_CP_FPU = 1 << 13, | ||
153 | + /* | ||
154 | + * Flag: Access check for this sysreg is identical to accessing SVE state | ||
155 | + * from an instruction: use translation sve_access_check(). | ||
156 | + */ | ||
157 | + ARM_CP_SVE = 1 << 14, | ||
158 | + /* Flag: Do not expose in gdb sysreg xml. */ | ||
159 | + ARM_CP_NO_GDB = 1 << 15, | ||
160 | +}; | ||
161 | |||
162 | /* | ||
163 | * Valid values for ARMCPRegInfo state field, indicating which of | ||
164 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
165 | index XXXXXXX..XXXXXXX 100644 | ||
166 | --- a/target/arm/cpu.c | ||
167 | +++ b/target/arm/cpu.c | ||
168 | @@ -XXX,XX +XXX,XX @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) | ||
169 | ARMCPRegInfo *ri = value; | ||
170 | ARMCPU *cpu = opaque; | ||
171 | |||
172 | - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { | ||
173 | + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { | ||
174 | return; | ||
175 | } | 23 | } |
176 | 24 | ||
177 | @@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) | 25 | - cmp = frac_cmp(a, b); |
178 | ARMCPU *cpu = opaque; | 26 | - if (cmp == 0) { |
179 | uint64_t oldvalue, newvalue; | 27 | - cmp = a->sign < b->sign; |
180 | 28 | - } | |
181 | - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | 29 | - |
182 | + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | 30 | switch (s->float_2nan_prop_rule) { |
183 | return; | 31 | case float_2nan_prop_s_ab: |
184 | } | 32 | if (have_snan) { |
185 | 33 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | |
186 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 34 | * return the NaN with the positive sign bit (if any). |
187 | index XXXXXXX..XXXXXXX 100644 | 35 | */ |
188 | --- a/target/arm/helper.c | 36 | if (is_snan(a->cls)) { |
189 | +++ b/target/arm/helper.c | 37 | - if (is_snan(b->cls)) { |
190 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | 38 | - which = cmp > 0 ? 0 : 1; |
191 | * multiple times. Special registers (ie NOP/WFI) are | 39 | - } else { |
192 | * never migratable and not even raw-accessible. | 40 | + if (!is_snan(b->cls)) { |
193 | */ | 41 | which = is_qnan(b->cls) ? 1 : 0; |
194 | - if ((r->type & ARM_CP_SPECIAL)) { | 42 | + break; |
195 | + if (r->type & ARM_CP_SPECIAL_MASK) { | 43 | } |
196 | r2->type |= ARM_CP_NO_RAW; | 44 | } else if (is_qnan(a->cls)) { |
197 | } | 45 | if (is_snan(b->cls) || !is_qnan(b->cls)) { |
198 | if (((r->crm == CP_ANY) && crm != 0) || | 46 | which = 0; |
199 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | 47 | - } else { |
200 | /* Check that the register definition has enough info to handle | 48 | - which = cmp > 0 ? 0 : 1; |
201 | * reads and writes if they are permitted. | 49 | + break; |
202 | */ | 50 | } |
203 | - if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | 51 | } else { |
204 | + if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { | 52 | which = 1; |
205 | if (r->access & PL3_R) { | 53 | + break; |
206 | assert((r->fieldoffset || | ||
207 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | ||
208 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
209 | index XXXXXXX..XXXXXXX 100644 | ||
210 | --- a/target/arm/translate-a64.c | ||
211 | +++ b/target/arm/translate-a64.c | ||
212 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
213 | } | ||
214 | |||
215 | /* Handle special cases first */ | ||
216 | - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | ||
217 | + switch (ri->type & ARM_CP_SPECIAL_MASK) { | ||
218 | + case 0: | ||
219 | + break; | ||
220 | case ARM_CP_NOP: | ||
221 | return; | ||
222 | case ARM_CP_NZCV: | ||
223 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
224 | } | 54 | } |
225 | return; | 55 | + cmp = frac_cmp(a, b); |
56 | + if (cmp == 0) { | ||
57 | + cmp = a->sign < b->sign; | ||
58 | + } | ||
59 | + which = cmp > 0 ? 0 : 1; | ||
60 | break; | ||
226 | default: | 61 | default: |
227 | - break; | 62 | g_assert_not_reached(); |
228 | + g_assert_not_reached(); | ||
229 | } | ||
230 | if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { | ||
231 | return; | ||
232 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
233 | index XXXXXXX..XXXXXXX 100644 | ||
234 | --- a/target/arm/translate.c | ||
235 | +++ b/target/arm/translate.c | ||
236 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, | ||
237 | } | ||
238 | |||
239 | /* Handle special cases first */ | ||
240 | - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | ||
241 | + switch (ri->type & ARM_CP_SPECIAL_MASK) { | ||
242 | + case 0: | ||
243 | + break; | ||
244 | case ARM_CP_NOP: | ||
245 | return; | ||
246 | case ARM_CP_WFI: | ||
247 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, | ||
248 | s->base.is_jmp = DISAS_WFI; | ||
249 | return; | ||
250 | default: | ||
251 | - break; | ||
252 | + g_assert_not_reached(); | ||
253 | } | ||
254 | |||
255 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { | ||
256 | -- | 63 | -- |
257 | 2.25.1 | 64 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Rearrange the values of the enumerators of CPAccessResult | 3 | Replace the "index" selecting between A and B with a result variable |
4 | so that we may directly extract the target el. For the two | 4 | of the proper type. This improves clarity within the function. |
5 | special cases in access_check_cp_reg, use CPAccessResult. | ||
6 | 5 | ||
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20220501055028.646596-3-richard.henderson@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20241203203949.483774-12-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 10 | --- |
13 | target/arm/cpregs.h | 26 ++++++++++++-------- | 11 | fpu/softfloat-parts.c.inc | 28 +++++++++++++--------------- |
14 | target/arm/op_helper.c | 56 +++++++++++++++++++++--------------------- | 12 | 1 file changed, 13 insertions(+), 15 deletions(-) |
15 | 2 files changed, 44 insertions(+), 38 deletions(-) | ||
16 | 13 | ||
17 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpregs.h | 16 | --- a/fpu/softfloat-parts.c.inc |
20 | +++ b/target/arm/cpregs.h | 17 | +++ b/fpu/softfloat-parts.c.inc |
21 | @@ -XXX,XX +XXX,XX @@ static inline bool cptype_valid(int cptype) | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
22 | typedef enum CPAccessResult { | 19 | float_status *s) |
23 | /* Access is permitted */ | ||
24 | CP_ACCESS_OK = 0, | ||
25 | + | ||
26 | + /* | ||
27 | + * Combined with one of the following, the low 2 bits indicate the | ||
28 | + * target exception level. If 0, the exception is taken to the usual | ||
29 | + * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). | ||
30 | + */ | ||
31 | + CP_ACCESS_EL_MASK = 3, | ||
32 | + | ||
33 | /* | ||
34 | * Access fails due to a configurable trap or enable which would | ||
35 | * result in a categorized exception syndrome giving information about | ||
36 | * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | ||
37 | - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or | ||
38 | - * PL1 if in EL0, otherwise to the current EL). | ||
39 | + * 0xc or 0x18). | ||
40 | */ | ||
41 | - CP_ACCESS_TRAP = 1, | ||
42 | + CP_ACCESS_TRAP = (1 << 2), | ||
43 | + CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2, | ||
44 | + CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3, | ||
45 | + | ||
46 | /* | ||
47 | * Access fails and results in an exception syndrome 0x0 ("uncategorized"). | ||
48 | * Note that this is not a catch-all case -- the set of cases which may | ||
49 | * result in this failure is specifically defined by the architecture. | ||
50 | */ | ||
51 | - CP_ACCESS_TRAP_UNCATEGORIZED = 2, | ||
52 | - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ | ||
53 | - CP_ACCESS_TRAP_EL2 = 3, | ||
54 | - CP_ACCESS_TRAP_EL3 = 4, | ||
55 | - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ | ||
56 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, | ||
57 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, | ||
58 | + CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2), | ||
59 | + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2, | ||
60 | + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3, | ||
61 | } CPAccessResult; | ||
62 | |||
63 | typedef struct ARMCPRegInfo ARMCPRegInfo; | ||
64 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/op_helper.c | ||
67 | +++ b/target/arm/op_helper.c | ||
68 | @@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, | ||
69 | uint32_t isread) | ||
70 | { | 20 | { |
71 | const ARMCPRegInfo *ri = rip; | 21 | bool have_snan = false; |
72 | + CPAccessResult res = CP_ACCESS_OK; | 22 | - int cmp, which; |
73 | int target_el; | 23 | + FloatPartsN *ret; |
74 | 24 | + int cmp; | |
75 | if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 | 25 | |
76 | && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { | 26 | if (is_snan(a->cls) || is_snan(b->cls)) { |
77 | - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)); | 27 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
78 | + res = CP_ACCESS_TRAP; | 28 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
79 | + goto fail; | 29 | switch (s->float_2nan_prop_rule) { |
80 | } | 30 | case float_2nan_prop_s_ab: |
81 | 31 | if (have_snan) { | |
82 | /* | 32 | - which = is_snan(a->cls) ? 0 : 1; |
83 | @@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, | 33 | + ret = is_snan(a->cls) ? a : b; |
84 | mask &= ~((1 << 4) | (1 << 14)); | 34 | break; |
85 | |||
86 | if (env->cp15.hstr_el2 & mask) { | ||
87 | - target_el = 2; | ||
88 | - goto exept; | ||
89 | + res = CP_ACCESS_TRAP_EL2; | ||
90 | + goto fail; | ||
91 | } | 35 | } |
92 | } | 36 | /* fall through */ |
93 | 37 | case float_2nan_prop_ab: | |
94 | - if (!ri->accessfn) { | 38 | - which = is_nan(a->cls) ? 0 : 1; |
95 | + if (ri->accessfn) { | 39 | + ret = is_nan(a->cls) ? a : b; |
96 | + res = ri->accessfn(env, ri, isread); | ||
97 | + } | ||
98 | + if (likely(res == CP_ACCESS_OK)) { | ||
99 | return; | ||
100 | } | ||
101 | |||
102 | - switch (ri->accessfn(env, ri, isread)) { | ||
103 | - case CP_ACCESS_OK: | ||
104 | - return; | ||
105 | + fail: | ||
106 | + switch (res & ~CP_ACCESS_EL_MASK) { | ||
107 | case CP_ACCESS_TRAP: | ||
108 | - target_el = exception_target_el(env); | ||
109 | - break; | ||
110 | - case CP_ACCESS_TRAP_EL2: | ||
111 | - /* Requesting a trap to EL2 when we're in EL3 is | ||
112 | - * a bug in the access function. | ||
113 | - */ | ||
114 | - assert(arm_current_el(env) != 3); | ||
115 | - target_el = 2; | ||
116 | - break; | ||
117 | - case CP_ACCESS_TRAP_EL3: | ||
118 | - target_el = 3; | ||
119 | break; | 40 | break; |
120 | case CP_ACCESS_TRAP_UNCATEGORIZED: | 41 | case float_2nan_prop_s_ba: |
121 | - target_el = exception_target_el(env); | 42 | if (have_snan) { |
122 | - syndrome = syn_uncategorized(); | 43 | - which = is_snan(b->cls) ? 1 : 0; |
123 | - break; | 44 | + ret = is_snan(b->cls) ? b : a; |
124 | - case CP_ACCESS_TRAP_UNCATEGORIZED_EL2: | 45 | break; |
125 | - target_el = 2; | 46 | } |
126 | - syndrome = syn_uncategorized(); | 47 | /* fall through */ |
127 | - break; | 48 | case float_2nan_prop_ba: |
128 | - case CP_ACCESS_TRAP_UNCATEGORIZED_EL3: | 49 | - which = is_nan(b->cls) ? 1 : 0; |
129 | - target_el = 3; | 50 | + ret = is_nan(b->cls) ? b : a; |
130 | syndrome = syn_uncategorized(); | 51 | break; |
52 | case float_2nan_prop_x87: | ||
53 | /* | ||
54 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
55 | */ | ||
56 | if (is_snan(a->cls)) { | ||
57 | if (!is_snan(b->cls)) { | ||
58 | - which = is_qnan(b->cls) ? 1 : 0; | ||
59 | + ret = is_qnan(b->cls) ? b : a; | ||
60 | break; | ||
61 | } | ||
62 | } else if (is_qnan(a->cls)) { | ||
63 | if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
64 | - which = 0; | ||
65 | + ret = a; | ||
66 | break; | ||
67 | } | ||
68 | } else { | ||
69 | - which = 1; | ||
70 | + ret = b; | ||
71 | break; | ||
72 | } | ||
73 | cmp = frac_cmp(a, b); | ||
74 | if (cmp == 0) { | ||
75 | cmp = a->sign < b->sign; | ||
76 | } | ||
77 | - which = cmp > 0 ? 0 : 1; | ||
78 | + ret = cmp > 0 ? a : b; | ||
131 | break; | 79 | break; |
132 | default: | 80 | default: |
133 | g_assert_not_reached(); | 81 | g_assert_not_reached(); |
134 | } | 82 | } |
135 | 83 | ||
136 | -exept: | 84 | - if (which) { |
137 | + target_el = res & CP_ACCESS_EL_MASK; | 85 | - a = b; |
138 | + switch (target_el) { | 86 | + if (is_snan(ret->cls)) { |
139 | + case 0: | 87 | + parts_silence_nan(ret, s); |
140 | + target_el = exception_target_el(env); | 88 | } |
141 | + break; | 89 | - if (is_snan(a->cls)) { |
142 | + case 2: | 90 | - parts_silence_nan(a, s); |
143 | + assert(arm_current_el(env) != 3); | 91 | - } |
144 | + assert(arm_is_el2_enabled(env)); | 92 | - return a; |
145 | + break; | 93 | + return ret; |
146 | + case 3: | ||
147 | + assert(arm_feature(env, ARM_FEATURE_EL3)); | ||
148 | + break; | ||
149 | + default: | ||
150 | + /* No "direct" traps to EL1 */ | ||
151 | + g_assert_not_reached(); | ||
152 | + } | ||
153 | + | ||
154 | raise_exception(env, EXCP_UDEF, syndrome, target_el); | ||
155 | } | 94 | } |
156 | 95 | ||
96 | static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
157 | -- | 97 | -- |
158 | 2.25.1 | 98 | 2.34.1 |
159 | 99 | ||
160 | 100 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> |
---|---|---|---|
2 | 2 | ||
3 | These particular data structures are not modified at runtime. | 3 | I'm migrating to Qualcomm's new open source email infrastructure, so |
4 | update my email address, and update the mailmap to match. | ||
4 | 5 | ||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> |
8 | Message-id: 20220501055028.646596-5-richard.henderson@linaro.org | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | target/arm/helper.c | 16 ++++++++-------- | 14 | MAINTAINERS | 2 +- |
12 | 1 file changed, 8 insertions(+), 8 deletions(-) | 15 | .mailmap | 5 +++-- |
16 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
13 | 17 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 18 | diff --git a/MAINTAINERS b/MAINTAINERS |
15 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 20 | --- a/MAINTAINERS |
17 | +++ b/target/arm/helper.c | 21 | +++ b/MAINTAINERS |
18 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 22 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h |
19 | .resetvalue = cpu->pmceid1 }, | 23 | SBSA-REF |
20 | }; | 24 | M: Radoslaw Biernacki <rad@semihalf.com> |
21 | #ifdef CONFIG_USER_ONLY | 25 | M: Peter Maydell <peter.maydell@linaro.org> |
22 | - ARMCPRegUserSpaceInfo v8_user_idregs[] = { | 26 | -R: Leif Lindholm <quic_llindhol@quicinc.com> |
23 | + static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { | 27 | +R: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
24 | { .name = "ID_AA64PFR0_EL1", | 28 | R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
25 | .exported_bits = 0x000f000f00ff0000, | 29 | L: qemu-arm@nongnu.org |
26 | .fixed_bits = 0x0000000000000011 }, | 30 | S: Maintained |
27 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 31 | diff --git a/.mailmap b/.mailmap |
28 | */ | 32 | index XXXXXXX..XXXXXXX 100644 |
29 | if (arm_feature(env, ARM_FEATURE_EL3)) { | 33 | --- a/.mailmap |
30 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | 34 | +++ b/.mailmap |
31 | - ARMCPRegInfo nsacr = { | 35 | @@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> |
32 | + static const ARMCPRegInfo nsacr = { | 36 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> |
33 | .name = "NSACR", .type = ARM_CP_CONST, | 37 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> |
34 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | 38 | Juan Quintela <quintela@trasno.org> <quintela@redhat.com> |
35 | .access = PL1_RW, .accessfn = nsacr_access, | 39 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> |
36 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 40 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> |
37 | }; | 41 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com> |
38 | define_one_arm_cp_reg(cpu, &nsacr); | 42 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org> |
39 | } else { | 43 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com> |
40 | - ARMCPRegInfo nsacr = { | 44 | Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr> |
41 | + static const ARMCPRegInfo nsacr = { | 45 | Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com> |
42 | .name = "NSACR", | 46 | Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu> |
43 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | ||
44 | .access = PL3_RW | PL1_R, | ||
45 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
46 | } | ||
47 | } else { | ||
48 | if (arm_feature(env, ARM_FEATURE_V8)) { | ||
49 | - ARMCPRegInfo nsacr = { | ||
50 | + static const ARMCPRegInfo nsacr = { | ||
51 | .name = "NSACR", .type = ARM_CP_CONST, | ||
52 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | ||
53 | .access = PL1_R, | ||
54 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
55 | .access = PL1_R, .type = ARM_CP_CONST, | ||
56 | .resetvalue = cpu->pmsav7_dregion << 8 | ||
57 | }; | ||
58 | - ARMCPRegInfo crn0_wi_reginfo = { | ||
59 | + static const ARMCPRegInfo crn0_wi_reginfo = { | ||
60 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | ||
61 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | ||
62 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | ||
63 | }; | ||
64 | #ifdef CONFIG_USER_ONLY | ||
65 | - ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | ||
66 | + static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | ||
67 | { .name = "MIDR_EL1", | ||
68 | .exported_bits = 0x00000000ffffffff }, | ||
69 | { .name = "REVIDR_EL1" }, | ||
70 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
71 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | ||
72 | }; | ||
73 | #ifdef CONFIG_USER_ONLY | ||
74 | - ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | ||
75 | + static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | ||
76 | { .name = "MPIDR_EL1", | ||
77 | .fixed_bits = 0x0000000080000000 }, | ||
78 | }; | ||
79 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
80 | } | ||
81 | |||
82 | if (arm_feature(env, ARM_FEATURE_VBAR)) { | ||
83 | - ARMCPRegInfo vbar_cp_reginfo[] = { | ||
84 | + static const ARMCPRegInfo vbar_cp_reginfo[] = { | ||
85 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | ||
86 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
87 | .access = PL1_RW, .writefn = vbar_write, | ||
88 | -- | 47 | -- |
89 | 2.25.1 | 48 | 2.34.1 |
90 | 49 | ||
91 | 50 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Vikram Garhwal <vikram.garhwal@bytedance.com> |
---|---|---|---|
2 | 2 | ||
3 | Create a typedef as well, and use it in ARMCPRegInfo. | 3 | Previously, maintainer role was paused due to inactive email id. Commit id: |
4 | This won't be perfect for debugging, but it'll nicely | 4 | c009d715721861984c4987bcc78b7ee183e86d75. |
5 | display the most common cases. | ||
6 | 5 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> |
9 | Message-id: 20220501055028.646596-8-richard.henderson@linaro.org | 8 | Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/cpregs.h | 44 +++++++++++++++++++++++--------------------- | 11 | MAINTAINERS | 2 ++ |
13 | target/arm/helper.c | 2 +- | 12 | 1 file changed, 2 insertions(+) |
14 | 2 files changed, 24 insertions(+), 22 deletions(-) | ||
15 | 13 | ||
16 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 14 | diff --git a/MAINTAINERS b/MAINTAINERS |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpregs.h | 16 | --- a/MAINTAINERS |
19 | +++ b/target/arm/cpregs.h | 17 | +++ b/MAINTAINERS |
20 | @@ -XXX,XX +XXX,XX @@ enum { | 18 | @@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c |
21 | * described with these bits, then use a laxer set of restrictions, and | 19 | |
22 | * do the more restrictive/complex check inside a helper function. | 20 | Xilinx CAN |
23 | */ | 21 | M: Francisco Iglesias <francisco.iglesias@amd.com> |
24 | -#define PL3_R 0x80 | 22 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> |
25 | -#define PL3_W 0x40 | 23 | S: Maintained |
26 | -#define PL2_R (0x20 | PL3_R) | 24 | F: hw/net/can/xlnx-* |
27 | -#define PL2_W (0x10 | PL3_W) | 25 | F: include/hw/net/xlnx-* |
28 | -#define PL1_R (0x08 | PL2_R) | 26 | @@ -XXX,XX +XXX,XX @@ F: include/hw/rx/ |
29 | -#define PL1_W (0x04 | PL2_W) | 27 | CAN bus subsystem and hardware |
30 | -#define PL0_R (0x02 | PL1_R) | 28 | M: Pavel Pisa <pisa@cmp.felk.cvut.cz> |
31 | -#define PL0_W (0x01 | PL1_W) | 29 | M: Francisco Iglesias <francisco.iglesias@amd.com> |
32 | +typedef enum { | 30 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> |
33 | + PL3_R = 0x80, | 31 | S: Maintained |
34 | + PL3_W = 0x40, | 32 | W: https://canbus.pages.fel.cvut.cz/ |
35 | + PL2_R = 0x20 | PL3_R, | 33 | F: net/can/* |
36 | + PL2_W = 0x10 | PL3_W, | ||
37 | + PL1_R = 0x08 | PL2_R, | ||
38 | + PL1_W = 0x04 | PL2_W, | ||
39 | + PL0_R = 0x02 | PL1_R, | ||
40 | + PL0_W = 0x01 | PL1_W, | ||
41 | |||
42 | -/* | ||
43 | - * For user-mode some registers are accessible to EL0 via a kernel | ||
44 | - * trap-and-emulate ABI. In this case we define the read permissions | ||
45 | - * as actually being PL0_R. However some bits of any given register | ||
46 | - * may still be masked. | ||
47 | - */ | ||
48 | + /* | ||
49 | + * For user-mode some registers are accessible to EL0 via a kernel | ||
50 | + * trap-and-emulate ABI. In this case we define the read permissions | ||
51 | + * as actually being PL0_R. However some bits of any given register | ||
52 | + * may still be masked. | ||
53 | + */ | ||
54 | #ifdef CONFIG_USER_ONLY | ||
55 | -#define PL0U_R PL0_R | ||
56 | + PL0U_R = PL0_R, | ||
57 | #else | ||
58 | -#define PL0U_R PL1_R | ||
59 | + PL0U_R = PL1_R, | ||
60 | #endif | ||
61 | |||
62 | -#define PL3_RW (PL3_R | PL3_W) | ||
63 | -#define PL2_RW (PL2_R | PL2_W) | ||
64 | -#define PL1_RW (PL1_R | PL1_W) | ||
65 | -#define PL0_RW (PL0_R | PL0_W) | ||
66 | + PL3_RW = PL3_R | PL3_W, | ||
67 | + PL2_RW = PL2_R | PL2_W, | ||
68 | + PL1_RW = PL1_R | PL1_W, | ||
69 | + PL0_RW = PL0_R | PL0_W, | ||
70 | +} CPAccessRights; | ||
71 | |||
72 | typedef enum CPAccessResult { | ||
73 | /* Access is permitted */ | ||
74 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { | ||
75 | /* Register type: ARM_CP_* bits/values */ | ||
76 | int type; | ||
77 | /* Access rights: PL*_[RW] */ | ||
78 | - int access; | ||
79 | + CPAccessRights access; | ||
80 | /* Security state: ARM_CP_SECSTATE_* bits/values */ | ||
81 | int secure; | ||
82 | /* | ||
83 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/target/arm/helper.c | ||
86 | +++ b/target/arm/helper.c | ||
87 | @@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | ||
88 | * to encompass the generic architectural permission check. | ||
89 | */ | ||
90 | if (r->state != ARM_CP_STATE_AA32) { | ||
91 | - int mask = 0; | ||
92 | + CPAccessRights mask; | ||
93 | switch (r->opc1) { | ||
94 | case 0: | ||
95 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | ||
96 | -- | 34 | -- |
97 | 2.25.1 | 35 | 2.34.1 | diff view generated by jsdifflib |