Series comparison

-[PULL 00/23] target-arm queue
+[PULL 00/10] target-arm queue
-Two small bugfixes, plus most of RTH's refactoring of cpregs
+Hi; not so many patches in this one, but notably it includes the
-handling.
+fix for various Avocado CI tests failing (incorrectly reported by
 Avocado as a timeout, but really a QEMU exit-with-error).
+thanks
 -- PMM
-The following changes since commit 1fba9dc71a170b3a05b9d3272dd8ecfe7f26e215:
+The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
-  Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging (2022-05-04 08:07:02 -0700)
+  Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220505
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930
-for you to fetch changes up to 99a50d1a67c602126fc2b3a4812d3000eba9bf34:
+for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:
-  target/arm: read access to performance counters from EL0 (2022-05-05 09:36:22 +0100)
+  target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Enable read access to performance counters from EL0
+ * Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
- * Enable SCTLR_EL1.BT0 for aarch64-linux-user
+   PMCNTENSET_EL0 or PMCNTENCLR_EL0
- * Refactoring of cpreg handling
+ * Make writes to MDCR_EL3 use PMU start/finish calls
  * Let AArch32 write to SDCR.SCCD
  * Rearrange cpu64.c so all the CPU initfns are together
  * hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
  * hw/arm/virt: fix some minor issues with generated device tree
  * Fix regression where EL3 could not write to SP_EL1 if there is no EL2
 ----------------------------------------------------------------
-Alex Zuepke (1):
+Francisco Iglesias (1):
-      target/arm: read access to performance counters from EL0
+      hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
-Richard Henderson (22):
+Jean-Philippe Brucker (4):
-      target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
+      hw/arm/virt: Fix devicetree warning about the root node
-      target/arm: Split out cpregs.h
+      hw/arm/virt: Fix devicetree warning about the GIC node
-      target/arm: Reorg CPAccessResult and access_check_cp_reg
+      hw/arm/virt: Use "msi-map" devicetree property for PCI
-      target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
+      hw/arm/virt: Fix devicetree warning about the SMMU node
       target/arm: Make some more cpreg data static const
       target/arm: Reorg ARMCPRegInfo type field bits
       target/arm: Avoid bare abort() or assert(0)
       target/arm: Change cpreg access permissions to enum
       target/arm: Name CPState type
       target/arm: Name CPSecureState type
       target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
       target/arm: Store cpregs key in the hash table directly
       target/arm: Merge allocation of the cpreg and its name
       target/arm: Hoist computation of key in add_cpreg_to_hashtable
       target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
       target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
       target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
       target/arm: Perform override check early in add_cpreg_to_hashtable
       target/arm: Reformat comments in add_cpreg_to_hashtable
       target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
       target/arm: Add isar predicates for FEAT_Debugv8p2
       target/arm: Add isar_feature_{aa64,any}_ras
- target/arm/cpregs.h               | 453 ++++++++++++++++++++++++++++++++++++++
+Jerome Forissier (1):
- target/arm/cpu.h                  | 393 +++------------------------------
+      target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
- hw/arm/pxa2xx.c                   |   2 +-
- hw/arm/pxa2xx_pic.c               |   2 +-
+Peter Maydell (4):
- hw/intc/arm_gicv3_cpuif.c         |   6 +-
+      target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
- hw/intc/arm_gicv3_kvm.c           |   3 +-
+      target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
- target/arm/cpu.c                  |  25 +--
+      target/arm: Update SDCR_VALID_MASK to include SCCD
- target/arm/cpu64.c                |   2 +-
+      target/arm: Rearrange cpu64.c so all the CPU initfns are together
- target/arm/cpu_tcg.c              |   5 +-
- target/arm/gdbstub.c              |   5 +-
+ include/hw/arm/xlnx-zynqmp.h |   3 +
- target/arm/helper.c               | 358 +++++++++++++-----------------
+ target/arm/cpu.h             |   8 +-
- target/arm/hvf/hvf.c              |   2 +-
+ hw/arm/virt.c                |   8 +-
- target/arm/kvm-stub.c             |   4 +-
+ hw/arm/xlnx-zynqmp.c         |  36 +++
- target/arm/kvm.c                  |   4 +-
+ target/arm/cpu64.c           | 712 +++++++++++++++++++++----------------------
- target/arm/machine.c              |   4 +-
+ target/arm/helper.c          |  32 +-
- target/arm/op_helper.c            |  57 ++---
+files changed, 427 insertions(+), 372 deletions(-)
  target/arm/translate-a64.c        |  14 +-
  target/arm/translate-neon.c       |   2 +-
  target/arm/translate.c            |  13 +-
  tests/tcg/aarch64/bti-3.c         |  42 ++++
  tests/tcg/aarch64/Makefile.target |   6 +-
 files changed, 738 insertions(+), 664 deletions(-)
  create mode 100644 target/arm/cpregs.h
  create mode 100644 tests/tcg/aarch64/bti-3.c

-[PULL 01/23] target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
-(indirect branch from register other than x16/x17).  The linux kernel
-sets this in bti_enable().
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
-[PMM: remove stray change to makefile comment]
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.c                  |  2 ++
- tests/tcg/aarch64/bti-3.c         | 42 +++++++++++++++++++++++++++++++
- tests/tcg/aarch64/Makefile.target |  6 ++---
-files changed, 47 insertions(+), 3 deletions(-)
- create mode 100644 tests/tcg/aarch64/bti-3.c
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
-         /* Enable all PAC keys.  */
-         env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
-                                   SCTLR_EnDA | SCTLR_EnDB);
-+        /* Trap on btype=3 for PACIxSP. */
-+        env->cp15.sctlr_el[1] |= SCTLR_BT0;
-         /* and to the FP/Neon instructions */
-         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
-         /* and to the SVE instructions */
-diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tests/tcg/aarch64/bti-3.c
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * BTI vs PACIASP
-+ */
-+
-+#include "bti-crt.inc.c"
-+
-+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
-+{
-+    uc->uc_mcontext.pc += 8;
-+    uc->uc_mcontext.pstate = 1;
-+}
-+
-+#define BTYPE_1() \
-+    asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
-+        : "=r"(skipped) : : "x16", "x30")
-+
-+#define BTYPE_2() \
-+    asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
-+        : "=r"(skipped) : : "x16", "x30")
-+
-+#define BTYPE_3() \
-+    asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
-+        : "=r"(skipped) : : "x15", "x30")
-+
-+#define TEST(WHICH, EXPECT) \
-+    do { WHICH(); fail += skipped ^ EXPECT; } while (0)
-+
-+int main()
-+{
-+    int fail = 0;
-+    int skipped;
-+
-+    /* Signal-like with SA_SIGINFO.  */
-+    signal_info(SIGILL, skip2_sigill);
-+
-+    /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
-+    TEST(BTYPE_1, 0);
-+    TEST(BTYPE_2, 0);
-+    TEST(BTYPE_3, 1);
-+
-+    return fail;
-+}
-diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
-index XXXXXXX..XXXXXXX 100644
---- a/tests/tcg/aarch64/Makefile.target
-+++ b/tests/tcg/aarch64/Makefile.target
-@@ -XXX,XX +XXX,XX @@ endif
- # BTI Tests
- # bti-1 tests the elf notes, so we require special compiler support.
- ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
--AARCH64_TESTS += bti-1
--bti-1: CFLAGS += -mbranch-protection=standard
--bti-1: LDFLAGS += -nostdlib
-+AARCH64_TESTS += bti-1 bti-3
-+bti-1 bti-3: CFLAGS += -mbranch-protection=standard
-+bti-1 bti-3: LDFLAGS += -nostdlib
- endif
- # bti-2 tests PROT_BTI, so no special compiler support required.
- AARCH64_TESTS += bti-2
---
-.25.1

-[PULL 02/23] target/arm: Split out cpregs.h
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Move ARMCPRegInfo and all related declarations to a new
-internal header, out of the public cpu.h.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-2-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h        | 413 +++++++++++++++++++++++++++++++++++++
- target/arm/cpu.h           | 368 ---------------------------------
- hw/arm/pxa2xx.c            |   1 +
- hw/arm/pxa2xx_pic.c        |   1 +
- hw/intc/arm_gicv3_cpuif.c  |   1 +
- hw/intc/arm_gicv3_kvm.c    |   2 +
- target/arm/cpu.c           |   1 +
- target/arm/cpu64.c         |   1 +
- target/arm/cpu_tcg.c       |   1 +
- target/arm/gdbstub.c       |   3 +-
- target/arm/helper.c        |   1 +
- target/arm/op_helper.c     |   1 +
- target/arm/translate-a64.c |   4 +-
- target/arm/translate.c     |   3 +-
-files changed, 427 insertions(+), 374 deletions(-)
- create mode 100644 target/arm/cpregs.h
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * QEMU ARM CP Register access and descriptions
-+ *
-+ * Copyright (c) 2022 Linaro Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see
-+ * <http://www.gnu.org/licenses/gpl-2.0.html>
-+ */
-+
-+#ifndef TARGET_ARM_CPREGS_H
-+#define TARGET_ARM_CPREGS_H
-+
-+/*
-+ * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
-+ * special-behaviour cp reg and bits [11..8] indicate what behaviour
-+ * it has. Otherwise it is a simple cp reg, where CONST indicates that
-+ * TCG can assume the value to be constant (ie load at translate time)
-+ * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
-+ * indicates that the TB should not be ended after a write to this register
-+ * (the default is that the TB ends after cp writes). OVERRIDE permits
-+ * a register definition to override a previous definition for the
-+ * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
-+ * old must have the OVERRIDE bit set.
-+ * ALIAS indicates that this register is an alias view of some underlying
-+ * state which is also visible via another register, and that the other
-+ * register is handling migration and reset; registers marked ALIAS will not be
-+ * migrated but may have their state set by syncing of register state from KVM.
-+ * NO_RAW indicates that this register has no underlying state and does not
-+ * support raw access for state saving/loading; it will not be used for either
-+ * migration or KVM state synchronization. (Typically this is for "registers"
-+ * which are actually used as instructions for cache maintenance and so on.)
-+ * IO indicates that this register does I/O and therefore its accesses
-+ * need to be marked with gen_io_start() and also end the TB. In particular,
-+ * registers which implement clocks or timers require this.
-+ * RAISES_EXC is for when the read or write hook might raise an exception;
-+ * the generated code will synchronize the CPU state before calling the hook
-+ * so that it is safe for the hook to call raise_exception().
-+ * NEWEL is for writes to registers that might change the exception
-+ * level - typically on older ARM chips. For those cases we need to
-+ * re-read the new el when recomputing the translation flags.
-+ */
-+#define ARM_CP_SPECIAL           0x0001
-+#define ARM_CP_CONST             0x0002
-+#define ARM_CP_64BIT             0x0004
-+#define ARM_CP_SUPPRESS_TB_END   0x0008
-+#define ARM_CP_OVERRIDE          0x0010
-+#define ARM_CP_ALIAS             0x0020
-+#define ARM_CP_IO                0x0040
-+#define ARM_CP_NO_RAW            0x0080
-+#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
-+#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
-+#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
-+#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
-+#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
-+#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
-+#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
-+#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
-+#define ARM_CP_FPU               0x1000
-+#define ARM_CP_SVE               0x2000
-+#define ARM_CP_NO_GDB            0x4000
-+#define ARM_CP_RAISES_EXC        0x8000
-+#define ARM_CP_NEWEL             0x10000
-+/* Used only as a terminator for ARMCPRegInfo lists */
-+#define ARM_CP_SENTINEL          0xfffff
-+/* Mask of only the flag bits in a type field */
-+#define ARM_CP_FLAG_MASK         0x1f0ff
-+
-+/*
-+ * Valid values for ARMCPRegInfo state field, indicating which of
-+ * the AArch32 and AArch64 execution states this register is visible in.
-+ * If the reginfo doesn't explicitly specify then it is AArch32 only.
-+ * If the reginfo is declared to be visible in both states then a second
-+ * reginfo is synthesised for the AArch32 view of the AArch64 register,
-+ * such that the AArch32 view is the lower 32 bits of the AArch64 one.
-+ * Note that we rely on the values of these enums as we iterate through
-+ * the various states in some places.
-+ */
-+enum {
-+    ARM_CP_STATE_AA32 = 0,
-+    ARM_CP_STATE_AA64 = 1,
-+    ARM_CP_STATE_BOTH = 2,
-+};
-+
-+/*
-+ * ARM CP register secure state flags.  These flags identify security state
-+ * attributes for a given CP register entry.
-+ * The existence of both or neither secure and non-secure flags indicates that
-+ * the register has both a secure and non-secure hash entry.  A single one of
-+ * these flags causes the register to only be hashed for the specified
-+ * security state.
-+ * Although definitions may have any combination of the S/NS bits, each
-+ * registered entry will only have one to identify whether the entry is secure
-+ * or non-secure.
-+ */
-+enum {
-+    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
-+    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
-+};
-+
-+/*
-+ * Return true if cptype is a valid type field. This is used to try to
-+ * catch errors where the sentinel has been accidentally left off the end
-+ * of a list of registers.
-+ */
-+static inline bool cptype_valid(int cptype)
-+{
-+    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
-+        || ((cptype & ARM_CP_SPECIAL) &&
-+            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
-+}
-+
-+/*
-+ * Access rights:
-+ * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
-+ * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
-+ * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
-+ * (ie any of the privileged modes in Secure state, or Monitor mode).
-+ * If a register is accessible in one privilege level it's always accessible
-+ * in higher privilege levels too. Since "Secure PL1" also follows this rule
-+ * (ie anything visible in PL2 is visible in S-PL1, some things are only
-+ * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
-+ * terminology a little and call this PL3.
-+ * In AArch64 things are somewhat simpler as the PLx bits line up exactly
-+ * with the ELx exception levels.
-+ *
-+ * If access permissions for a register are more complex than can be
-+ * described with these bits, then use a laxer set of restrictions, and
-+ * do the more restrictive/complex check inside a helper function.
-+ */
-+#define PL3_R 0x80
-+#define PL3_W 0x40
-+#define PL2_R (0x20 | PL3_R)
-+#define PL2_W (0x10 | PL3_W)
-+#define PL1_R (0x08 | PL2_R)
-+#define PL1_W (0x04 | PL2_W)
-+#define PL0_R (0x02 | PL1_R)
-+#define PL0_W (0x01 | PL1_W)
-+
-+/*
-+ * For user-mode some registers are accessible to EL0 via a kernel
-+ * trap-and-emulate ABI. In this case we define the read permissions
-+ * as actually being PL0_R. However some bits of any given register
-+ * may still be masked.
-+ */
-+#ifdef CONFIG_USER_ONLY
-+#define PL0U_R PL0_R
-+#else
-+#define PL0U_R PL1_R
-+#endif
-+
-+#define PL3_RW (PL3_R | PL3_W)
-+#define PL2_RW (PL2_R | PL2_W)
-+#define PL1_RW (PL1_R | PL1_W)
-+#define PL0_RW (PL0_R | PL0_W)
-+
-+typedef enum CPAccessResult {
-+    /* Access is permitted */
-+    CP_ACCESS_OK = 0,
-+    /*
-+     * Access fails due to a configurable trap or enable which would
-+     * result in a categorized exception syndrome giving information about
-+     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
-+     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
-+     * PL1 if in EL0, otherwise to the current EL).
-+     */
-+    CP_ACCESS_TRAP = 1,
-+    /*
-+     * Access fails and results in an exception syndrome 0x0 ("uncategorized").
-+     * Note that this is not a catch-all case -- the set of cases which may
-+     * result in this failure is specifically defined by the architecture.
-+     */
-+    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
-+    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
-+    CP_ACCESS_TRAP_EL2 = 3,
-+    CP_ACCESS_TRAP_EL3 = 4,
-+    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
-+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
-+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
-+} CPAccessResult;
-+
-+typedef struct ARMCPRegInfo ARMCPRegInfo;
-+
-+/*
-+ * Access functions for coprocessor registers. These cannot fail and
-+ * may not raise exceptions.
-+ */
-+typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-+typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
-+                       uint64_t value);
-+/* Access permission check functions for coprocessor registers. */
-+typedef CPAccessResult CPAccessFn(CPUARMState *env,
-+                                  const ARMCPRegInfo *opaque,
-+                                  bool isread);
-+/* Hook function for register reset */
-+typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-+
-+#define CP_ANY 0xff
-+
-+/* Definition of an ARM coprocessor register */
-+struct ARMCPRegInfo {
-+    /* Name of register (useful mainly for debugging, need not be unique) */
-+    const char *name;
-+    /*
-+     * Location of register: coprocessor number and (crn,crm,opc1,opc2)
-+     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
-+     * 'wildcard' field -- any value of that field in the MRC/MCR insn
-+     * will be decoded to this register. The register read and write
-+     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
-+     * used by the program, so it is possible to register a wildcard and
-+     * then behave differently on read/write if necessary.
-+     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
-+     * must both be zero.
-+     * For AArch64-visible registers, opc0 is also used.
-+     * Since there are no "coprocessors" in AArch64, cp is purely used as a
-+     * way to distinguish (for KVM's benefit) guest-visible system registers
-+     * from demuxed ones provided to preserve the "no side effects on
-+     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
-+     * visible (to match KVM's encoding); cp==0 will be converted to
-+     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
-+     */
-+    uint8_t cp;
-+    uint8_t crn;
-+    uint8_t crm;
-+    uint8_t opc0;
-+    uint8_t opc1;
-+    uint8_t opc2;
-+    /* Execution state in which this register is visible: ARM_CP_STATE_* */
-+    int state;
-+    /* Register type: ARM_CP_* bits/values */
-+    int type;
-+    /* Access rights: PL*_[RW] */
-+    int access;
-+    /* Security state: ARM_CP_SECSTATE_* bits/values */
-+    int secure;
-+    /*
-+     * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
-+     * this register was defined: can be used to hand data through to the
-+     * register read/write functions, since they are passed the ARMCPRegInfo*.
-+     */
-+    void *opaque;
-+    /*
-+     * Value of this register, if it is ARM_CP_CONST. Otherwise, if
-+     * fieldoffset is non-zero, the reset value of the register.
-+     */
-+    uint64_t resetvalue;
-+    /*
-+     * Offset of the field in CPUARMState for this register.
-+     * This is not needed if either:
-+     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
-+     *  2. both readfn and writefn are specified
-+     */
-+    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
-+
-+    /*
-+     * Offsets of the secure and non-secure fields in CPUARMState for the
-+     * register if it is banked.  These fields are only used during the static
-+     * registration of a register.  During hashing the bank associated
-+     * with a given security state is copied to fieldoffset which is used from
-+     * there on out.
-+     *
-+     * It is expected that register definitions use either fieldoffset or
-+     * bank_fieldoffsets in the definition but not both.  It is also expected
-+     * that both bank offsets are set when defining a banked register.  This
-+     * use indicates that a register is banked.
-+     */
-+    ptrdiff_t bank_fieldoffsets[2];
-+
-+    /*
-+     * Function for making any access checks for this register in addition to
-+     * those specified by the 'access' permissions bits. If NULL, no extra
-+     * checks required. The access check is performed at runtime, not at
-+     * translate time.
-+     */
-+    CPAccessFn *accessfn;
-+    /*
-+     * Function for handling reads of this register. If NULL, then reads
-+     * will be done by loading from the offset into CPUARMState specified
-+     * by fieldoffset.
-+     */
-+    CPReadFn *readfn;
-+    /*
-+     * Function for handling writes of this register. If NULL, then writes
-+     * will be done by writing to the offset into CPUARMState specified
-+     * by fieldoffset.
-+     */
-+    CPWriteFn *writefn;
-+    /*
-+     * Function for doing a "raw" read; used when we need to copy
-+     * coprocessor state to the kernel for KVM or out for
-+     * migration. This only needs to be provided if there is also a
-+     * readfn and it has side effects (for instance clear-on-read bits).
-+     */
-+    CPReadFn *raw_readfn;
-+    /*
-+     * Function for doing a "raw" write; used when we need to copy KVM
-+     * kernel coprocessor state into userspace, or for inbound
-+     * migration. This only needs to be provided if there is also a
-+     * writefn and it masks out "unwritable" bits or has write-one-to-clear
-+     * or similar behaviour.
-+     */
-+    CPWriteFn *raw_writefn;
-+    /*
-+     * Function for resetting the register. If NULL, then reset will be done
-+     * by writing resetvalue to the field specified in fieldoffset. If
-+     * fieldoffset is 0 then no reset will be done.
-+     */
-+    CPResetFn *resetfn;
-+
-+    /*
-+     * "Original" writefn and readfn.
-+     * For ARMv8.1-VHE register aliases, we overwrite the read/write
-+     * accessor functions of various EL1/EL0 to perform the runtime
-+     * check for which sysreg should actually be modified, and then
-+     * forwards the operation.  Before overwriting the accessors,
-+     * the original function is copied here, so that accesses that
-+     * really do go to the EL1/EL0 version proceed normally.
-+     * (The corresponding EL2 register is linked via opaque.)
-+     */
-+    CPReadFn *orig_readfn;
-+    CPWriteFn *orig_writefn;
-+};
-+
-+/*
-+ * Macros which are lvalues for the field in CPUARMState for the
-+ * ARMCPRegInfo *ri.
-+ */
-+#define CPREG_FIELD32(env, ri) \
-+    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
-+#define CPREG_FIELD64(env, ri) \
-+    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
-+
-+#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
-+
-+void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-+                                    const ARMCPRegInfo *regs, void *opaque);
-+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-+                                       const ARMCPRegInfo *regs, void *opaque);
-+static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
-+{
-+    define_arm_cp_regs_with_opaque(cpu, regs, 0);
-+}
-+static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
-+{
-+    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
-+}
-+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
-+
-+/*
-+ * Definition of an ARM co-processor register as viewed from
-+ * userspace. This is used for presenting sanitised versions of
-+ * registers to userspace when emulating the Linux AArch64 CPU
-+ * ID/feature ABI (advertised as HWCAP_CPUID).
-+ */
-+typedef struct ARMCPRegUserSpaceInfo {
-+    /* Name of register */
-+    const char *name;
-+
-+    /* Is the name actually a glob pattern */
-+    bool is_glob;
-+
-+    /* Only some bits are exported to user space */
-+    uint64_t exported_bits;
-+
-+    /* Fixed bits are applied after the mask */
-+    uint64_t fixed_bits;
-+} ARMCPRegUserSpaceInfo;
-+
-+#define REGUSERINFO_SENTINEL { .name = NULL }
-+
-+void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
-+
-+/* CPWriteFn that can be used to implement writes-ignored behaviour */
-+void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-+                         uint64_t value);
-+/* CPReadFn that can be used for read-as-zero behaviour */
-+uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
-+
-+/*
-+ * CPResetFn that does nothing, for use if no reset is required even
-+ * if fieldoffset is non zero.
-+ */
-+void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
-+
-+/*
-+ * Return true if this reginfo struct's field in the cpu state struct
-+ * is 64 bits wide.
-+ */
-+static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
-+{
-+    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
-+}
-+
-+static inline bool cp_access_ok(int current_el,
-+                                const ARMCPRegInfo *ri, int isread)
-+{
-+    return (ri->access >> ((current_el * 2) + isread)) & 1;
-+}
-+
-+/* Raw read of a coprocessor register (as needed for migration, etc) */
-+uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
-+
-+#endif /* TARGET_ARM_CPREGS_H */
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
-     return kvmid;
- }
--/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
-- * special-behaviour cp reg and bits [11..8] indicate what behaviour
-- * it has. Otherwise it is a simple cp reg, where CONST indicates that
-- * TCG can assume the value to be constant (ie load at translate time)
-- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
-- * indicates that the TB should not be ended after a write to this register
-- * (the default is that the TB ends after cp writes). OVERRIDE permits
-- * a register definition to override a previous definition for the
-- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
-- * old must have the OVERRIDE bit set.
-- * ALIAS indicates that this register is an alias view of some underlying
-- * state which is also visible via another register, and that the other
-- * register is handling migration and reset; registers marked ALIAS will not be
-- * migrated but may have their state set by syncing of register state from KVM.
-- * NO_RAW indicates that this register has no underlying state and does not
-- * support raw access for state saving/loading; it will not be used for either
-- * migration or KVM state synchronization. (Typically this is for "registers"
-- * which are actually used as instructions for cache maintenance and so on.)
-- * IO indicates that this register does I/O and therefore its accesses
-- * need to be marked with gen_io_start() and also end the TB. In particular,
-- * registers which implement clocks or timers require this.
-- * RAISES_EXC is for when the read or write hook might raise an exception;
-- * the generated code will synchronize the CPU state before calling the hook
-- * so that it is safe for the hook to call raise_exception().
-- * NEWEL is for writes to registers that might change the exception
-- * level - typically on older ARM chips. For those cases we need to
-- * re-read the new el when recomputing the translation flags.
-- */
--#define ARM_CP_SPECIAL           0x0001
--#define ARM_CP_CONST             0x0002
--#define ARM_CP_64BIT             0x0004
--#define ARM_CP_SUPPRESS_TB_END   0x0008
--#define ARM_CP_OVERRIDE          0x0010
--#define ARM_CP_ALIAS             0x0020
--#define ARM_CP_IO                0x0040
--#define ARM_CP_NO_RAW            0x0080
--#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
--#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
--#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
--#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
--#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
--#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
--#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
--#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
--#define ARM_CP_FPU               0x1000
--#define ARM_CP_SVE               0x2000
--#define ARM_CP_NO_GDB            0x4000
--#define ARM_CP_RAISES_EXC        0x8000
--#define ARM_CP_NEWEL             0x10000
--/* Used only as a terminator for ARMCPRegInfo lists */
--#define ARM_CP_SENTINEL          0xfffff
--/* Mask of only the flag bits in a type field */
--#define ARM_CP_FLAG_MASK         0x1f0ff
--
--/* Valid values for ARMCPRegInfo state field, indicating which of
-- * the AArch32 and AArch64 execution states this register is visible in.
-- * If the reginfo doesn't explicitly specify then it is AArch32 only.
-- * If the reginfo is declared to be visible in both states then a second
-- * reginfo is synthesised for the AArch32 view of the AArch64 register,
-- * such that the AArch32 view is the lower 32 bits of the AArch64 one.
-- * Note that we rely on the values of these enums as we iterate through
-- * the various states in some places.
-- */
--enum {
--    ARM_CP_STATE_AA32 = 0,
--    ARM_CP_STATE_AA64 = 1,
--    ARM_CP_STATE_BOTH = 2,
--};
--
--/* ARM CP register secure state flags.  These flags identify security state
-- * attributes for a given CP register entry.
-- * The existence of both or neither secure and non-secure flags indicates that
-- * the register has both a secure and non-secure hash entry.  A single one of
-- * these flags causes the register to only be hashed for the specified
-- * security state.
-- * Although definitions may have any combination of the S/NS bits, each
-- * registered entry will only have one to identify whether the entry is secure
-- * or non-secure.
-- */
--enum {
--    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
--    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
--};
--
--/* Return true if cptype is a valid type field. This is used to try to
-- * catch errors where the sentinel has been accidentally left off the end
-- * of a list of registers.
-- */
--static inline bool cptype_valid(int cptype)
--{
--    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
--        || ((cptype & ARM_CP_SPECIAL) &&
--            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
--}
--
--/* Access rights:
-- * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
-- * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
-- * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
-- * (ie any of the privileged modes in Secure state, or Monitor mode).
-- * If a register is accessible in one privilege level it's always accessible
-- * in higher privilege levels too. Since "Secure PL1" also follows this rule
-- * (ie anything visible in PL2 is visible in S-PL1, some things are only
-- * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
-- * terminology a little and call this PL3.
-- * In AArch64 things are somewhat simpler as the PLx bits line up exactly
-- * with the ELx exception levels.
-- *
-- * If access permissions for a register are more complex than can be
-- * described with these bits, then use a laxer set of restrictions, and
-- * do the more restrictive/complex check inside a helper function.
-- */
--#define PL3_R 0x80
--#define PL3_W 0x40
--#define PL2_R (0x20 | PL3_R)
--#define PL2_W (0x10 | PL3_W)
--#define PL1_R (0x08 | PL2_R)
--#define PL1_W (0x04 | PL2_W)
--#define PL0_R (0x02 | PL1_R)
--#define PL0_W (0x01 | PL1_W)
--
--/*
-- * For user-mode some registers are accessible to EL0 via a kernel
-- * trap-and-emulate ABI. In this case we define the read permissions
-- * as actually being PL0_R. However some bits of any given register
-- * may still be masked.
-- */
--#ifdef CONFIG_USER_ONLY
--#define PL0U_R PL0_R
--#else
--#define PL0U_R PL1_R
--#endif
--
--#define PL3_RW (PL3_R | PL3_W)
--#define PL2_RW (PL2_R | PL2_W)
--#define PL1_RW (PL1_R | PL1_W)
--#define PL0_RW (PL0_R | PL0_W)
--
- /* Return the highest implemented Exception Level */
- static inline int arm_highest_el(CPUARMState *env)
- {
-@@ -XXX,XX +XXX,XX @@ static inline int arm_current_el(CPUARMState *env)
-     }
- }
--typedef struct ARMCPRegInfo ARMCPRegInfo;
--
--typedef enum CPAccessResult {
--    /* Access is permitted */
--    CP_ACCESS_OK = 0,
--    /* Access fails due to a configurable trap or enable which would
--     * result in a categorized exception syndrome giving information about
--     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
--     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
--     * PL1 if in EL0, otherwise to the current EL).
--     */
--    CP_ACCESS_TRAP = 1,
--    /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
--     * Note that this is not a catch-all case -- the set of cases which may
--     * result in this failure is specifically defined by the architecture.
--     */
--    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
--    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
--    CP_ACCESS_TRAP_EL2 = 3,
--    CP_ACCESS_TRAP_EL3 = 4,
--    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
--    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
--    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
--} CPAccessResult;
--
--/* Access functions for coprocessor registers. These cannot fail and
-- * may not raise exceptions.
-- */
--typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
--typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
--                       uint64_t value);
--/* Access permission check functions for coprocessor registers. */
--typedef CPAccessResult CPAccessFn(CPUARMState *env,
--                                  const ARMCPRegInfo *opaque,
--                                  bool isread);
--/* Hook function for register reset */
--typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
--
--#define CP_ANY 0xff
--
--/* Definition of an ARM coprocessor register */
--struct ARMCPRegInfo {
--    /* Name of register (useful mainly for debugging, need not be unique) */
--    const char *name;
--    /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
--     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
--     * 'wildcard' field -- any value of that field in the MRC/MCR insn
--     * will be decoded to this register. The register read and write
--     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
--     * used by the program, so it is possible to register a wildcard and
--     * then behave differently on read/write if necessary.
--     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
--     * must both be zero.
--     * For AArch64-visible registers, opc0 is also used.
--     * Since there are no "coprocessors" in AArch64, cp is purely used as a
--     * way to distinguish (for KVM's benefit) guest-visible system registers
--     * from demuxed ones provided to preserve the "no side effects on
--     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
--     * visible (to match KVM's encoding); cp==0 will be converted to
--     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
--     */
--    uint8_t cp;
--    uint8_t crn;
--    uint8_t crm;
--    uint8_t opc0;
--    uint8_t opc1;
--    uint8_t opc2;
--    /* Execution state in which this register is visible: ARM_CP_STATE_* */
--    int state;
--    /* Register type: ARM_CP_* bits/values */
--    int type;
--    /* Access rights: PL*_[RW] */
--    int access;
--    /* Security state: ARM_CP_SECSTATE_* bits/values */
--    int secure;
--    /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
--     * this register was defined: can be used to hand data through to the
--     * register read/write functions, since they are passed the ARMCPRegInfo*.
--     */
--    void *opaque;
--    /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
--     * fieldoffset is non-zero, the reset value of the register.
--     */
--    uint64_t resetvalue;
--    /* Offset of the field in CPUARMState for this register.
--     *
--     * This is not needed if either:
--     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
--     *  2. both readfn and writefn are specified
--     */
--    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
--
--    /* Offsets of the secure and non-secure fields in CPUARMState for the
--     * register if it is banked.  These fields are only used during the static
--     * registration of a register.  During hashing the bank associated
--     * with a given security state is copied to fieldoffset which is used from
--     * there on out.
--     *
--     * It is expected that register definitions use either fieldoffset or
--     * bank_fieldoffsets in the definition but not both.  It is also expected
--     * that both bank offsets are set when defining a banked register.  This
--     * use indicates that a register is banked.
--     */
--    ptrdiff_t bank_fieldoffsets[2];
--
--    /* Function for making any access checks for this register in addition to
--     * those specified by the 'access' permissions bits. If NULL, no extra
--     * checks required. The access check is performed at runtime, not at
--     * translate time.
--     */
--    CPAccessFn *accessfn;
--    /* Function for handling reads of this register. If NULL, then reads
--     * will be done by loading from the offset into CPUARMState specified
--     * by fieldoffset.
--     */
--    CPReadFn *readfn;
--    /* Function for handling writes of this register. If NULL, then writes
--     * will be done by writing to the offset into CPUARMState specified
--     * by fieldoffset.
--     */
--    CPWriteFn *writefn;
--    /* Function for doing a "raw" read; used when we need to copy
--     * coprocessor state to the kernel for KVM or out for
--     * migration. This only needs to be provided if there is also a
--     * readfn and it has side effects (for instance clear-on-read bits).
--     */
--    CPReadFn *raw_readfn;
--    /* Function for doing a "raw" write; used when we need to copy KVM
--     * kernel coprocessor state into userspace, or for inbound
--     * migration. This only needs to be provided if there is also a
--     * writefn and it masks out "unwritable" bits or has write-one-to-clear
--     * or similar behaviour.
--     */
--    CPWriteFn *raw_writefn;
--    /* Function for resetting the register. If NULL, then reset will be done
--     * by writing resetvalue to the field specified in fieldoffset. If
--     * fieldoffset is 0 then no reset will be done.
--     */
--    CPResetFn *resetfn;
--
--    /*
--     * "Original" writefn and readfn.
--     * For ARMv8.1-VHE register aliases, we overwrite the read/write
--     * accessor functions of various EL1/EL0 to perform the runtime
--     * check for which sysreg should actually be modified, and then
--     * forwards the operation.  Before overwriting the accessors,
--     * the original function is copied here, so that accesses that
--     * really do go to the EL1/EL0 version proceed normally.
--     * (The corresponding EL2 register is linked via opaque.)
--     */
--    CPReadFn *orig_readfn;
--    CPWriteFn *orig_writefn;
--};
--
--/* Macros which are lvalues for the field in CPUARMState for the
-- * ARMCPRegInfo *ri.
-- */
--#define CPREG_FIELD32(env, ri) \
--    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
--#define CPREG_FIELD64(env, ri) \
--    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
--
--#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
--
--void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
--                                    const ARMCPRegInfo *regs, void *opaque);
--void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
--                                       const ARMCPRegInfo *regs, void *opaque);
--static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
--{
--    define_arm_cp_regs_with_opaque(cpu, regs, 0);
--}
--static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
--{
--    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
--}
--const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
--
--/*
-- * Definition of an ARM co-processor register as viewed from
-- * userspace. This is used for presenting sanitised versions of
-- * registers to userspace when emulating the Linux AArch64 CPU
-- * ID/feature ABI (advertised as HWCAP_CPUID).
-- */
--typedef struct ARMCPRegUserSpaceInfo {
--    /* Name of register */
--    const char *name;
--
--    /* Is the name actually a glob pattern */
--    bool is_glob;
--
--    /* Only some bits are exported to user space */
--    uint64_t exported_bits;
--
--    /* Fixed bits are applied after the mask */
--    uint64_t fixed_bits;
--} ARMCPRegUserSpaceInfo;
--
--#define REGUSERINFO_SENTINEL { .name = NULL }
--
--void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
--
--/* CPWriteFn that can be used to implement writes-ignored behaviour */
--void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
--                         uint64_t value);
--/* CPReadFn that can be used for read-as-zero behaviour */
--uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
--
--/* CPResetFn that does nothing, for use if no reset is required even
-- * if fieldoffset is non zero.
-- */
--void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
--
--/* Return true if this reginfo struct's field in the cpu state struct
-- * is 64 bits wide.
-- */
--static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
--{
--    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
--}
--
--static inline bool cp_access_ok(int current_el,
--                                const ARMCPRegInfo *ri, int isread)
--{
--    return (ri->access >> ((current_el * 2) + isread)) & 1;
--}
--
--/* Raw read of a coprocessor register (as needed for migration, etc) */
--uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
--
- /**
-  * write_list_to_cpustate
-  * @cpu: ARMCPU
-diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx.c
-+++ b/hw/arm/pxa2xx.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/cutils.h"
- #include "qemu/log.h"
- #include "qom/object.h"
-+#include "target/arm/cpregs.h"
- static struct {
-     hwaddr io_base;
-diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx_pic.c
-+++ b/hw/arm/pxa2xx_pic.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
- #include "migration/vmstate.h"
- #include "qom/object.h"
-+#include "target/arm/cpregs.h"
- #define ICIP    0x00    /* Interrupt Controller IRQ Pending register */
- #define ICMR    0x04    /* Interrupt Controller Mask register */
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@
- #include "gicv3_internal.h"
- #include "hw/irq.h"
- #include "cpu.h"
-+#include "target/arm/cpregs.h"
- /*
-  * Special case return value from hppvi_index(); must be larger than
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_kvm.c
-+++ b/hw/intc/arm_gicv3_kvm.c
-@@ -XXX,XX +XXX,XX @@
- #include "vgic_common.h"
- #include "migration/blocker.h"
- #include "qom/object.h"
-+#include "target/arm/cpregs.h"
-+
- #ifdef DEBUG_GICV3_KVM
- #define DPRINTF(fmt, ...) \
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@
- #include "kvm_arm.h"
- #include "disas/capstone.h"
- #include "fpu/softfloat.h"
-+#include "cpregs.h"
- static void arm_cpu_set_pc(CPUState *cs, vaddr value)
- {
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@
- #include "hvf_arm.h"
- #include "qapi/visitor.h"
- #include "hw/qdev-properties.h"
-+#include "cpregs.h"
- #ifndef CONFIG_USER_ONLY
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
-+++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@
- #if !defined(CONFIG_USER_ONLY)
- #include "hw/boards.h"
- #endif
-+#include "cpregs.h"
- /* CPU models. These are not needed for the AArch64 linux-user build. */
- #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/gdbstub.c
-+++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@
-  */
- #include "qemu/osdep.h"
- #include "cpu.h"
--#include "internals.h"
- #include "exec/gdbstub.h"
-+#include "internals.h"
-+#include "cpregs.h"
- typedef struct RegisterSysregXmlParam {
-     CPUState *cs;
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
- #include "exec/cpu_ldst.h"
- #include "semihosting/common-semi.h"
- #endif
-+#include "cpregs.h"
- #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
- #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
-diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/op_helper.c
-+++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@
- #include "internals.h"
- #include "exec/exec-all.h"
- #include "exec/cpu_ldst.h"
-+#include "cpregs.h"
- #define SIGNBIT (uint32_t)0x80000000
- #define SIGNBIT64 ((uint64_t)1 << 63)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@
- #include "translate.h"
- #include "internals.h"
- #include "qemu/host-utils.h"
--
- #include "semihosting/semihost.h"
- #include "exec/gen-icount.h"
--
- #include "exec/helper-proto.h"
- #include "exec/helper-gen.h"
- #include "exec/log.h"
--
-+#include "cpregs.h"
- #include "translate-a64.h"
- #include "qemu/atomic128.h"
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/bitops.h"
- #include "arm_ldst.h"
- #include "semihosting/semihost.h"
--
- #include "exec/helper-proto.h"
- #include "exec/helper-gen.h"
--
- #include "exec/log.h"
-+#include "cpregs.h"
- #define ENABLE_ARCH_4T    arm_dc_feature(s, ARM_FEATURE_V4T)
---
-.25.1

-[PULL 03/23] target/arm: Reorg CPAccessResult and access_check_cp_reg
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Rearrange the values of the enumerators of CPAccessResult
-so that we may directly extract the target el. For the two
-special cases in access_check_cp_reg, use CPAccessResult.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-3-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h    | 26 ++++++++++++--------
- target/arm/op_helper.c | 56 +++++++++++++++++++++---------------------
-files changed, 44 insertions(+), 38 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ static inline bool cptype_valid(int cptype)
- typedef enum CPAccessResult {
-     /* Access is permitted */
-     CP_ACCESS_OK = 0,
-+
-+    /*
-+     * Combined with one of the following, the low 2 bits indicate the
-+     * target exception level.  If 0, the exception is taken to the usual
-+     * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
-+     */
-+    CP_ACCESS_EL_MASK = 3,
-+
-     /*
-      * Access fails due to a configurable trap or enable which would
-      * result in a categorized exception syndrome giving information about
-      * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
--     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
--     * PL1 if in EL0, otherwise to the current EL).
-+     * 0xc or 0x18).
-      */
--    CP_ACCESS_TRAP = 1,
-+    CP_ACCESS_TRAP = (1 << 2),
-+    CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
-+    CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
-+
-     /*
-      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
-      * Note that this is not a catch-all case -- the set of cases which may
-      * result in this failure is specifically defined by the architecture.
-      */
--    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
--    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
--    CP_ACCESS_TRAP_EL2 = 3,
--    CP_ACCESS_TRAP_EL3 = 4,
--    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
--    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
--    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
-+    CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
-+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
-+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
- } CPAccessResult;
- typedef struct ARMCPRegInfo ARMCPRegInfo;
-diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/op_helper.c
-+++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
-                                  uint32_t isread)
- {
-     const ARMCPRegInfo *ri = rip;
-+    CPAccessResult res = CP_ACCESS_OK;
-     int target_el;
-     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
-         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
--        raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
-+        res = CP_ACCESS_TRAP;
-+        goto fail;
-     }
-     /*
-@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
-         mask &= ~((1 << 4) | (1 << 14));
-         if (env->cp15.hstr_el2 & mask) {
--            target_el = 2;
--            goto exept;
-+            res = CP_ACCESS_TRAP_EL2;
-+            goto fail;
-         }
-     }
--    if (!ri->accessfn) {
-+    if (ri->accessfn) {
-+        res = ri->accessfn(env, ri, isread);
-+    }
-+    if (likely(res == CP_ACCESS_OK)) {
-         return;
-     }
--    switch (ri->accessfn(env, ri, isread)) {
--    case CP_ACCESS_OK:
--        return;
-+ fail:
-+    switch (res & ~CP_ACCESS_EL_MASK) {
-     case CP_ACCESS_TRAP:
--        target_el = exception_target_el(env);
--        break;
--    case CP_ACCESS_TRAP_EL2:
--        /* Requesting a trap to EL2 when we're in EL3 is
--         * a bug in the access function.
--         */
--        assert(arm_current_el(env) != 3);
--        target_el = 2;
--        break;
--    case CP_ACCESS_TRAP_EL3:
--        target_el = 3;
-         break;
-     case CP_ACCESS_TRAP_UNCATEGORIZED:
--        target_el = exception_target_el(env);
--        syndrome = syn_uncategorized();
--        break;
--    case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
--        target_el = 2;
--        syndrome = syn_uncategorized();
--        break;
--    case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
--        target_el = 3;
-         syndrome = syn_uncategorized();
-         break;
-     default:
-         g_assert_not_reached();
-     }
--exept:
-+    target_el = res & CP_ACCESS_EL_MASK;
-+    switch (target_el) {
-+    case 0:
-+        target_el = exception_target_el(env);
-+        break;
-+    case 2:
-+        assert(arm_current_el(env) != 3);
-+        assert(arm_is_el2_enabled(env));
-+        break;
-+    case 3:
-+        assert(arm_feature(env, ARM_FEATURE_EL3));
-+        break;
-+    default:
-+        /* No "direct" traps to EL1 */
-+        g_assert_not_reached();
-+    }
-+
-     raise_exception(env, EXCP_UDEF, syndrome, target_el);
- }
---
-.25.1

-[PULL 23/23] target/arm: read access to performance counters from EL0
+[PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
-From: Alex Zuepke <alex.zuepke@tum.de>
+In commit 01765386a888 we made some system register write functions
 call pmu_op_start()/pmu_op_finish(). This means that they now touch
 timers, so for icount to work these registers must have the ARM_CP_IO
 flag set.
-The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
+This fixes a bug where when icount is enabled a guest that touches
-to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
+MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
-we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.
+QEMU to print an error message and exit, for example:
-Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
+[    2.495971] TCP: Hash tables configured (established 1024 bind 1024)
 [    2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
 [    2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
 [    2.496917] NET: Registered protocol family 1
 qemu-system-aarch64: Bad icount read
 Reported-by: Thomas Huth <thuth@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
+Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 4 ++--
+ target/arm/helper.c | 12 ++++++------
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 6 insertions(+), 6 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
-               .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
+      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
-               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+      */
-               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
+     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
--              .accessfn = pmreg_access },
+-      .access = PL0_RW, .type = ARM_CP_ALIAS,
-+              .accessfn = pmreg_access_xevcntr },
++      .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
-             { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
+       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
-               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
+       .writefn = pmcntenset_write,
--              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+       .accessfn = pmreg_access,
-+              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
+       .raw_writefn = raw_write },
-               .type = ARM_CP_IO,
+-    { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
-               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
++    { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
-               .raw_readfn = pmevcntr_rawread,
+       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
        .access = PL0_RW, .accessfn = pmreg_access,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
        .accessfn = pmreg_access,
        .writefn = pmcntenclr_write,
 -      .type = ARM_CP_ALIAS },
 +      .type = ARM_CP_ALIAS | ARM_CP_IO },
      { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
        .access = PL0_RW, .accessfn = pmreg_access,
 -      .type = ARM_CP_ALIAS,
 +      .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
        .writefn = pmcntenclr_write },
      { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
        .resetvalue = 0,
        .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
 -    { .name = "SDCR", .type = ARM_CP_ALIAS,
 +    { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
        .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
        .writefn = sdcr_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
           * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
           */
          ARMCPRegInfo mdcr_el2 = {
 -            .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
 +            .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
              .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
              .writefn = mdcr_el2_write,
              .access = PL2_RW, .resetvalue = pmu_num_counters(env),
 --
 .25.1

-[PULL 07/23] target/arm: Avoid bare abort() or assert(0)
+[PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
-From: Richard Henderson <richard.henderson@linaro.org>
+In commit 01765386a88868 we fixed a bug where we weren't correctly
 bracketing changes to some registers with pmu_op_start() and
 pmu_op_finish() calls for changes which affect whether the PMU
 counters might be enabled.  However, we missed the case of writes to
 the AArch64 MDCR_EL3 register, because (unlike its AArch32
 counterpart) they are currently done directly to the CPU state struct
 without going through the sdcr_write() function.
-Standardize on g_assert_not_reached() for "should not happen".
+Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
-Retain abort() when preceeded by fprintf or error_report.
+The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
 masking off the bits which don't exist in the AArch32 register".
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-7-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
 ---
- target/arm/helper.c         | 7 +++----
+ target/arm/helper.c | 18 ++++++++++++++----
- target/arm/hvf/hvf.c        | 2 +-
+file changed, 14 insertions(+), 4 deletions(-)
  target/arm/kvm-stub.c       | 4 ++--
  target/arm/kvm.c            | 4 ++--
  target/arm/machine.c        | 4 ++--
  target/arm/translate-a64.c  | 4 ++--
  target/arm/translate-neon.c | 2 +-
  target/arm/translate.c      | 4 ++--
 files changed, 15 insertions(+), 16 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
              break;
          default:
              /* broken reginfo with out-of-range opc1 */
 -            assert(false);
 -            break;
 +            g_assert_not_reached();
          }
          /* assert our permissions are not too lax (stricter is fine) */
          assert((r->access & ~mask) == 0);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
              break;
          default:
              /* Never happens, but compiler isn't smart enough to tell.  */
 -            abort();
 +            g_assert_not_reached();
          }
      }
      *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
              break;
          default:
              /* Never happens, but compiler isn't smart enough to tell.  */
 -            abort();
 +            g_assert_not_reached();
          }
      }
      if (domain_prot == 3) {
 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/hvf/hvf.c
 +++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
          /* we got kicked, no exit to process */
          return 0;
      default:
 -        assert(0);
 +        g_assert_not_reached();
      }
      hvf_sync_vtimer(cpu);
 diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm-stub.c
 +++ b/target/arm/kvm-stub.c
@@ -XXX,XX +XXX,XX @@
  bool write_kvmstate_to_list(ARMCPU *cpu)
  {
 -    abort();
 +    g_assert_not_reached();
  }
  bool write_list_to_kvmstate(ARMCPU *cpu, int level)
  {
 -    abort();
 +    g_assert_not_reached();
  }
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
              ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
              break;
          default:
 -            abort();
 +            g_assert_not_reached();
          }
          if (ret) {
              ok = false;
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
              r.addr = (uintptr_t)(cpu->cpreg_values + i);
              break;
          default:
 -            abort();
 +            g_assert_not_reached();
          }
          ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
          if (ret) {
 diff --git a/target/arm/machine.c b/target/arm/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/machine.c
 +++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
      if (kvm_enabled()) {
          if (!write_kvmstate_to_list(cpu)) {
              /* This should never fail */
 -            abort();
 +            g_assert_not_reached();
          }
          /*
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
      } else {
          if (!write_cpustate_to_list(cpu, false)) {
              /* This should never fail. */
 -            abort();
 +            g_assert_not_reached();
          }
      }
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
          gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
          break;
      default:
 -        abort();
 +        g_assert_not_reached();
      }
      write_fp_sreg(s, rd, tcg_res);
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
          break;
      }
      default:
 -        abort();
 +        g_assert_not_reached();
      }
  }
-diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
+-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-index XXXXXXX..XXXXXXX 100644
+-                       uint64_t value)
---- a/target/arm/translate-neon.c
++static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-+++ b/target/arm/translate-neon.c
++                           uint64_t value)
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
+ {
-         }
+     /*
-         break;
+      * Some MDCR_EL3 bits affect whether PMU counters are running:
-     default:
+@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
--        abort();
+     if (pmu_op) {
-+        g_assert_not_reached();
+         pmu_op_start(env);
      }
-     if ((vd + a->stride * (nregs - 1)) > 31) {
+-    env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
-         /*
++    env->cp15.mdcr_el3 = value;
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+     if (pmu_op) {
-index XXXXXXX..XXXXXXX 100644
+         pmu_op_finish(env);
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
          offset = 4;
          break;
      default:
 -        abort();
 +        g_assert_not_reached();
      }
-     tcg_gen_addi_i32(addr, addr, offset);
+ }
-     tmp = load_reg(s, 14);
-@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
++static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-             offset = 0;
++                       uint64_t value)
-             break;
++{
-         default:
++    /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
--            abort();
++    mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
-+            g_assert_not_reached();
++}
-         }
++
-         tcg_gen_addi_i32(addr, addr, offset);
+ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
+                            uint64_t value)
  {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .access = PL2_RW,
        .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
      { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
 +      .type = ARM_CP_IO,
        .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
        .resetvalue = 0,
 -      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
 +      .access = PL3_RW,
 +      .writefn = mdcr_el3_write,
 +      .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
      { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
        .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
 --
 .25.1

-[PULL 22/23] target/arm: Add isar_feature_{aa64,any}_ras
+[PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD
-From: Richard Henderson <richard.henderson@linaro.org>
+Our SDCR_VALID_MASK doesn't include all of the bits which are defined
 by the current architecture.  In particular in commit 0b42f4fab9d3 we
 forgot to add SCCD, which meant that an AArch32 guest couldn't
 actually use the SCCD bit to disable counting in Secure state.
-Add the aa64 predicate for detecting RAS support from id registers.
+Add all the currently defined bits; we don't implement all of them,
-We already have the aa32 version from the M-profile work.
+but this makes them be reads-as-written, which is architecturally
-Add the 'any' predicate for testing both aa64 and aa32.
+valid and matches how we currently handle most of the others in the
 mask.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-34-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
 ---
- target/arm/cpu.h | 10 ++++++++++
+ target/arm/cpu.h | 8 +++++++-
-file changed, 10 insertions(+)
+file changed, 7 insertions(+), 1 deletion(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
+ FIELD(CPTR_EL3, TAM, 30, 1)
- }
+ FIELD(CPTR_EL3, TCPAC, 31, 1)
-+static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
++#define MDCR_MTPME    (1U << 28)
-+{
++#define MDCR_TDCC     (1U << 27)
-+    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
+ #define MDCR_HLP      (1U << 26)  /* MDCR_EL2 */
-+}
+ #define MDCR_SCCD     (1U << 23)  /* MDCR_EL3 */
-+
+ #define MDCR_HCCD     (1U << 23)  /* MDCR_EL2 */
- static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
+ #define MDCR_EPMAD    (1U << 21)
- {
+ #define MDCR_EDAD     (1U << 20)
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
++#define MDCR_TTRF     (1U << 19)
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
++#define MDCR_STE      (1U << 18)  /* MDCR_EL3 */
-     return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
+ #define MDCR_SPME     (1U << 17)  /* MDCR_EL3 */
- }
+ #define MDCR_HPMD     (1U << 17)  /* MDCR_EL2 */
+ #define MDCR_SDD      (1U << 16)
-+static inline bool isar_feature_any_ras(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
-+{
+ #define MDCR_HPMN     (0x1fU)
-+    return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
-+}
+ /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
-+
+-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
- /*
++#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
-  * Forward to the above feature tests given an ARMCPU pointer.
++                         MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
-  */
++                         MDCR_STE | MDCR_SPME | MDCR_SPD)
  #define CPSR_M (0x1fU)
  #define CPSR_T (1U << 5)
 --
 .25.1

-[PULL 04/23] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
+[PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together
-From: Richard Henderson <richard.henderson@linaro.org>
+cpu64.c has ended up in a slightly odd order -- it starts with the
 initfns for most of the models-real-hardware CPUs; after that comes a
 bunch of support code for SVE, SME, pauth and LPA2 properties.  Then
 come the initfns for the 'host' and 'max' CPU types, and then after
 that one more models-real-hardware CPU initfn, for a64fx.  (This
 ordering is partly historical and partly required because a64fx needs
 the SVE properties.)
-Remove a possible source of error by removing REGINFO_SENTINEL
+Reorder the file into:
-and using ARRAY_SIZE (convinently hidden inside a macro) to
+ * CPU property support functions
-find the end of the set of regs being registered or modified.
+ * initfns for real hardware CPUs
  * initfns for host and max
  * class boilerplate
-The space saved by not having the extra array element reduces
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-the executable's .data.rel.ro section by about 9k.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
  target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
 file changed, 356 insertions(+), 356 deletions(-)
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-4-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h       |  53 +++++++++---------
- hw/arm/pxa2xx.c           |   1 -
- hw/arm/pxa2xx_pic.c       |   1 -
- hw/intc/arm_gicv3_cpuif.c |   5 --
- hw/intc/arm_gicv3_kvm.c   |   1 -
- target/arm/cpu64.c        |   1 -
- target/arm/cpu_tcg.c      |   4 --
- target/arm/helper.c       | 111 ++++++++------------------------------
-files changed, 48 insertions(+), 129 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@
- #define ARM_CP_NO_GDB            0x4000
- #define ARM_CP_RAISES_EXC        0x8000
- #define ARM_CP_NEWEL             0x10000
--/* Used only as a terminator for ARMCPRegInfo lists */
--#define ARM_CP_SENTINEL          0xfffff
- /* Mask of only the flag bits in a type field */
- #define ARM_CP_FLAG_MASK         0x1f0ff
-@@ -XXX,XX +XXX,XX @@ enum {
-     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
- };
--/*
-- * Return true if cptype is a valid type field. This is used to try to
-- * catch errors where the sentinel has been accidentally left off the end
-- * of a list of registers.
-- */
--static inline bool cptype_valid(int cptype)
--{
--    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
--        || ((cptype & ARM_CP_SPECIAL) &&
--            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
--}
--
- /*
-  * Access rights:
-  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
-@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
- #define CPREG_FIELD64(env, ri) \
-     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
--#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
-+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
-+                                       void *opaque);
--void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
--                                    const ARMCPRegInfo *regs, void *opaque);
--void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
--                                       const ARMCPRegInfo *regs, void *opaque);
--static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
--{
--    define_arm_cp_regs_with_opaque(cpu, regs, 0);
--}
- static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
- {
--    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
-+    define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
- }
-+
-+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
-+                                        void *opaque, size_t len);
-+
-+#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE)               \
-+    do {                                                                \
-+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
-+        define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE,           \
-+                                           ARRAY_SIZE(REGS));           \
-+    } while (0)
-+
-+#define define_arm_cp_regs(CPU, REGS) \
-+    define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
-+
- const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
- /*
-@@ -XXX,XX +XXX,XX @@ typedef struct ARMCPRegUserSpaceInfo {
-     uint64_t fixed_bits;
- } ARMCPRegUserSpaceInfo;
--#define REGUSERINFO_SENTINEL { .name = NULL }
-+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
-+                                 const ARMCPRegUserSpaceInfo *mods,
-+                                 size_t mods_len);
--void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
-+#define modify_arm_cp_regs(REGS, MODS)                                  \
-+    do {                                                                \
-+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
-+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0);                       \
-+        modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS),             \
-+                                    MODS, ARRAY_SIZE(MODS));            \
-+    } while (0)
- /* CPWriteFn that can be used to implement writes-ignored behaviour */
- void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx.c
-+++ b/hw/arm/pxa2xx.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
-     { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
-       .access = PL1_RW, .type = ARM_CP_IO,
-       .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
--    REGINFO_SENTINEL
- };
- static void pxa2xx_setup_cp14(PXA2xxState *s)
-diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx_pic.c
-+++ b/hw/arm/pxa2xx_pic.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
-     REGINFO_FOR_PIC_CP("ICLR2", 8),
-     REGINFO_FOR_PIC_CP("ICFP2", 9),
-     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
--    REGINFO_SENTINEL
- };
- static const MemoryRegionOps pxa2xx_pic_ops = {
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
-       .readfn = icc_igrpen1_el3_read,
-       .writefn = icc_igrpen1_el3_write,
-     },
--    REGINFO_SENTINEL
- };
- static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = {
-       .readfn = ich_vmcr_read,
-       .writefn = ich_vmcr_write,
-     },
--    REGINFO_SENTINEL
- };
- static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
-       .readfn = ich_ap_read,
-       .writefn = ich_ap_write,
-     },
--    REGINFO_SENTINEL
- };
- static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
-       .readfn = ich_ap_read,
-       .writefn = ich_ap_write,
-     },
--    REGINFO_SENTINEL
- };
- static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
-@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
-                       .readfn = ich_lr_read,
-                       .writefn = ich_lr_write,
-                     },
--                    REGINFO_SENTINEL
-                 };
-                 define_arm_cp_regs(cpu, lr_regset);
-             }
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_kvm.c
-+++ b/hw/intc/arm_gicv3_kvm.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
-        */
-       .resetfn = arm_gicv3_icc_reset,
-     },
--    REGINFO_SENTINEL
- };
- /**
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
-     { .name = "L2MERRSR",
+     define_cortex_a72_a57_a53_cp_reginfo(cpu);
        .cp = 15, .opc1 = 3, .crm = 15,
        .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void aarch64_a57_initfn(Object *obj)
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void cortex_a8_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
        .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
      { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
        .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 -    REGINFO_SENTINEL
  };
  static void cortex_a9_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
  #endif
      { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void cortex_a7_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
        .access = PL1_RW, .type = ARM_CP_CONST },
      { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
        .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static void cortex_r5_initfn(Object *obj)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
        .secure = ARM_CP_SECSTATE_S,
        .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
        .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
      { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
        .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
        .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v6_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
       */
      { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
        .access = PL1_W, .type = ARM_CP_WFI },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v7_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
        .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
      { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
        .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
        .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
        .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
        .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
 -    REGINFO_SENTINEL
  };
  typedef struct pm_event {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
        .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
        .writefn = tlbimvaa_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo v7mp_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
      { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
        .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
        .writefn = tlbimvaa_is_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
        .writefn = pmovsset_write,
        .raw_writefn = raw_write },
 -    REGINFO_SENTINEL
  };
  static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
      { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
        .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
        .accessfn = teehbr_access, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo v6k_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
        .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
                               offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
        .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
      },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
        .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .readfn = gt_virt_cnt_read,
      },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
        .access = PL1_W, .accessfn = ats_access,
        .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
  #endif
 -    REGINFO_SENTINEL
  };
  /* Return basic MPU access permission bits.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
        .writefn = pmsav7_rgnr_write,
        .resetfn = arm_cp_reset_ignore },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
      { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
        .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
        .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
 -    REGINFO_SENTINEL
  };
  static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
        .access = PL1_RW, .accessfn = access_tvm_trvm,
        .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
        .resetvalue = 0, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo vmsa_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
        /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
                               offsetof(CPUARMState, cp15.tcr_el[1])} },
 -    REGINFO_SENTINEL
  };
  /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
      { .name = "C9", .cp = 15, .crn = 9,
        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
        .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
      { .name = "XSCALE_UNLOCK_DCACHE",
        .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
        .access = PL1_RW,
        .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
      { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
        .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
        .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
      { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
        .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
      { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
        .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
        .resetvalue = (1 << 30) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo strongarm_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
        .access = PL1_RW, .resetvalue = 0,
        .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
 -    REGINFO_SENTINEL
  };
  static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                               offsetof(CPUARMState, cp15.ttbr1_ns) },
        .writefn = vmsa_ttbr_write, },
 -    REGINFO_SENTINEL
  };
  static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
        .writefn = sdcr_write,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
 -    REGINFO_SENTINEL
  };
  /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
        .type = ARM_CP_CONST,
        .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
        .access = PL2_RW, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  /* Ditto, but for registers which exist in ARMv8 but not v7 */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
        .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
        .access = PL2_RW,
        .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
        .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
        .access = PL2_RW,
        .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
        .access = PL2_RW,
        .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
        .writefn = hcr_writehigh },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
        .access = PL2_RW, .accessfn = sel2_access,
        .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae3_write },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_tda,
        .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
        .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
      { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
        .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  /* Return the exception level to which exceptions should be taken
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
                .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
                .writefn = dbgbcr_write, .raw_writefn = raw_write
              },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, dbgregs);
      }
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
                .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
                .writefn = dbgwcr_write, .raw_writefn = raw_write
              },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, dbgregs);
      }
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
                .type = ARM_CP_IO,
                .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
                .raw_writefn = pmevtyper_rawwrite },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, pmev_regs);
          g_free(pmevcntr_name);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
                .resetvalue = extract64(cpu->pmceid1, 32, 32) },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, v81_pmu_regs);
      }
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
        .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
        .access = PL1_R, .accessfn = access_lor_ns,
        .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  #ifdef TARGET_AARCH64
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
        .access = PL1_RW, .accessfn = access_pauth,
        .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo tlbirange_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae3_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo tlbios_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae3is_write },
 -    REGINFO_SENTINEL
  };
  static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rndr_reginfo[] = {
        .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
        .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
        .access = PL0_R, .readfn = rndr_readfn },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
        .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo dcpodp_reg[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
        .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 -    REGINFO_SENTINEL
  };
  #endif /*CONFIG_USER_ONLY*/
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
      { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
      { .name = "TCO", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
        .type = ARM_CP_CONST, .access = PL0_RW, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
        .accessfn = aa64_zva_access,
  #endif
      },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
      { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
        .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
 -    REGINFO_SENTINEL
  };
  static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
        .access = PL1_R,
        .accessfn = access_aa64_tid2,
        .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
        .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
        .accessfn = access_joscr_jmcr,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo vhe_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
        .access = PL2_RW, .accessfn = e2h_access,
        .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
  #endif
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
        .writefn = ats_write64 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo ats1cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
        .writefn = ats_write },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
        .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
        .access = PL2_RW, .type = ARM_CP_CONST,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  void register_cp_regs_for_features(ARMCPU *cpu)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .type = ARM_CP_CONST,
                .accessfn = access_aa32_tid3,
                .resetvalue = cpu->isar.id_isar6 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, v6_idregs);
          define_arm_cp_regs(cpu, v6_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
                .resetvalue = cpu->pmceid1 },
 -            REGINFO_SENTINEL
          };
  #ifdef CONFIG_USER_ONLY
          ARMCPRegUserSpaceInfo v8_user_idregs[] = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .exported_bits = 0x000000f0ffffffff },
              { .name = "ID_AA64ISAR*_EL1_RESERVED",
                .is_glob = true                     },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(v8_idregs, v8_user_idregs);
  #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL2_RW,
                .resetvalue = vmpidr_def,
                .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, vpidr_regs);
          define_arm_cp_regs(cpu, el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                    .access = PL2_RW, .accessfn = access_el3_aa32ns,
                    .type = ARM_CP_NO_RAW,
                    .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
 -                REGINFO_SENTINEL
              };
              define_arm_cp_regs(cpu, vpidr_regs);
              define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .raw_writefn = raw_write, .writefn = sctlr_write,
                .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
                .resetvalue = cpu->reset_sctlr },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, el3_regs);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "DUMMY",
                .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
                .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
              { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R,
                .accessfn = access_aa64_tid1,
                .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
 -            REGINFO_SENTINEL
          };
          ARMCPRegInfo id_cp_reginfo[] = {
              /* These are common to v8 and pre-v8 */
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R,
                .accessfn = access_aa32_tid1,
                .type = ARM_CP_CONST, .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          /* TLBTR is specific to VMSA */
          ARMCPRegInfo id_tlbtr_reginfo = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "MIDR_EL1",
                .exported_bits = 0x00000000ffffffff },
              { .name = "REVIDR_EL1"                },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
  #endif
          if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
              arm_feature(env, ARM_FEATURE_STRONGARM)) {
 -            ARMCPRegInfo *r;
 +            size_t i;
              /* Register the blanket "writes ignored" value first to cover the
               * whole space. Then update the specific ID registers to allow write
               * access, so that they ignore writes rather than causing them to
               * UNDEF.
               */
              define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
 -            for (r = id_pre_v8_midr_cp_reginfo;
 -                 r->type != ARM_CP_SENTINEL; r++) {
 -                r->access = PL1_RW;
 +            for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) {
 +                id_pre_v8_midr_cp_reginfo[i].access = PL1_RW;
              }
 -            for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
 -                r->access = PL1_RW;
 +            for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) {
 +                id_cp_reginfo[i].access = PL1_RW;
              }
              id_mpuir_reginfo.access = PL1_RW;
              id_tlbtr_reginfo.access = PL1_RW;
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
                .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
                .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
 -            REGINFO_SENTINEL
          };
  #ifdef CONFIG_USER_ONLY
          ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
              { .name = "MPIDR_EL1",
                .fixed_bits = 0x0000000080000000 },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
  #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
                .access = PL3_RW, .type = ARM_CP_CONST,
                .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, auxcr_reginfo);
          if (cpu_isar_feature(aa32_ac2, cpu)) {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                    .type = ARM_CP_CONST,
                    .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
                    .access = PL1_R, .resetvalue = cpu->reset_cbar },
 -                REGINFO_SENTINEL
              };
              /* We don't implement a r/w 64 bit CBAR currently */
              assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                       offsetof(CPUARMState, cp15.vbar_ns) },
                .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, vbar_cp_reginfo);
      }
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                     r->writefn);
          }
      }
 -    /* Bad type field probably means missing sentinel at end of reg list */
 -    assert(cptype_valid(r->type));
 +
      for (crm = crmmin; crm <= crmmax; crm++) {
          for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
              for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      }
  }
--void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
+-static void aarch64_a57_initfn(Object *obj)
--                                    const ARMCPRegInfo *regs, void *opaque)
+-{
-+/* Define a whole list of registers */
+-    ARMCPU *cpu = ARM_CPU(obj);
-+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+-
-+                                        void *opaque, size_t len)
+-    cpu->dtb_compatible = "arm,cortex-a57";
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 -    cpu->midr = 0x411fd070;
 -    cpu->revidr = 0x00000000;
 -    cpu->reset_fpsid = 0x41034070;
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x12111111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -    cpu->ctr = 0x8444c004;
 -    cpu->reset_sctlr = 0x00c50838;
 -    cpu->isar.id_pfr0 = 0x00000131;
 -    cpu->isar.id_pfr1 = 0x00011011;
 -    cpu->isar.id_dfr0 = 0x03010066;
 -    cpu->id_afr0 = 0x00000000;
 -    cpu->isar.id_mmfr0 = 0x10101105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02102211;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00011142;
 -    cpu->isar.id_isar5 = 0x00011121;
 -    cpu->isar.id_isar6 = 0;
 -    cpu->isar.id_aa64pfr0 = 0x00002222;
 -    cpu->isar.id_aa64dfr0 = 0x10305106;
 -    cpu->isar.id_aa64isar0 = 0x00011120;
 -    cpu->isar.id_aa64mmfr0 = 0x00001124;
 -    cpu->isar.dbgdidr = 0x3516d000;
 -    cpu->isar.dbgdevid = 0x01110f13;
 -    cpu->isar.dbgdevid1 = 0x2;
 -    cpu->isar.reset_pmcr_el0 = 0x41013000;
 -    cpu->clidr = 0x0a200023;
 -    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 -    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 -    cpu->dcz_blocksize = 4; /* 64 bytes */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -}
 -
 -static void aarch64_a53_initfn(Object *obj)
 -{
 -    ARMCPU *cpu = ARM_CPU(obj);
 -
 -    cpu->dtb_compatible = "arm,cortex-a53";
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 -    cpu->midr = 0x410fd034;
 -    cpu->revidr = 0x00000000;
 -    cpu->reset_fpsid = 0x41034070;
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x12111111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 -    cpu->reset_sctlr = 0x00c50838;
 -    cpu->isar.id_pfr0 = 0x00000131;
 -    cpu->isar.id_pfr1 = 0x00011011;
 -    cpu->isar.id_dfr0 = 0x03010066;
 -    cpu->id_afr0 = 0x00000000;
 -    cpu->isar.id_mmfr0 = 0x10101105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02102211;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00011142;
 -    cpu->isar.id_isar5 = 0x00011121;
 -    cpu->isar.id_isar6 = 0;
 -    cpu->isar.id_aa64pfr0 = 0x00002222;
 -    cpu->isar.id_aa64dfr0 = 0x10305106;
 -    cpu->isar.id_aa64isar0 = 0x00011120;
 -    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 -    cpu->isar.dbgdidr = 0x3516d000;
 -    cpu->isar.dbgdevid = 0x00110f13;
 -    cpu->isar.dbgdevid1 = 0x1;
 -    cpu->isar.reset_pmcr_el0 = 0x41033000;
 -    cpu->clidr = 0x0a200023;
 -    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 -    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 -    cpu->dcz_blocksize = 4; /* 64 bytes */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -}
 -
 -static void aarch64_a72_initfn(Object *obj)
 -{
 -    ARMCPU *cpu = ARM_CPU(obj);
 -
 -    cpu->dtb_compatible = "arm,cortex-a72";
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -    cpu->midr = 0x410fd083;
 -    cpu->revidr = 0x00000000;
 -    cpu->reset_fpsid = 0x41034080;
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x12111111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -    cpu->ctr = 0x8444c004;
 -    cpu->reset_sctlr = 0x00c50838;
 -    cpu->isar.id_pfr0 = 0x00000131;
 -    cpu->isar.id_pfr1 = 0x00011011;
 -    cpu->isar.id_dfr0 = 0x03010066;
 -    cpu->id_afr0 = 0x00000000;
 -    cpu->isar.id_mmfr0 = 0x10201105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02102211;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00011142;
 -    cpu->isar.id_isar5 = 0x00011121;
 -    cpu->isar.id_aa64pfr0 = 0x00002222;
 -    cpu->isar.id_aa64dfr0 = 0x10305106;
 -    cpu->isar.id_aa64isar0 = 0x00011120;
 -    cpu->isar.id_aa64mmfr0 = 0x00001124;
 -    cpu->isar.dbgdidr = 0x3516d000;
 -    cpu->isar.dbgdevid = 0x01110f13;
 -    cpu->isar.dbgdevid1 = 0x2;
 -    cpu->isar.reset_pmcr_el0 = 0x41023000;
 -    cpu->clidr = 0x0a200023;
 -    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 -    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
 -    cpu->dcz_blocksize = 4; /* 64 bytes */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -}
 -
 -static void aarch64_a76_initfn(Object *obj)
 -{
 -    ARMCPU *cpu = ARM_CPU(obj);
 -
 -    cpu->dtb_compatible = "arm,cortex-a76";
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -
 -    /* Ordered by B2.4 AArch64 registers by functional group */
 -    cpu->clidr = 0x82000023;
 -    cpu->ctr = 0x8444C004;
 -    cpu->dcz_blocksize = 4;
 -    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
 -    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 -    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 -    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
 -    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 -    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 -    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 -    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
 -    cpu->id_afr0       = 0x00000000;
 -    cpu->isar.id_dfr0  = 0x04010088;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00010142;
 -    cpu->isar.id_isar5 = 0x01011121;
 -    cpu->isar.id_isar6 = 0x00000010;
 -    cpu->isar.id_mmfr0 = 0x10201105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02122211;
 -    cpu->isar.id_mmfr4 = 0x00021110;
 -    cpu->isar.id_pfr0  = 0x10010131;
 -    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 -    cpu->isar.id_pfr2  = 0x00000011;
 -    cpu->midr = 0x414fd0b1;          /* r4p1 */
 -    cpu->revidr = 0;
 -
 -    /* From B2.18 CCSIDR_EL1 */
 -    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 -    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
 -
 -    /* From B2.93 SCTLR_EL3 */
 -    cpu->reset_sctlr = 0x30c50838;
 -
 -    /* From B4.23 ICH_VTR_EL2 */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -
 -    /* From B5.1 AdvSIMD AArch64 register summary */
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x13211111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -
 -    /* From D5.1 AArch64 PMU register summary */
 -    cpu->isar.reset_pmcr_el0 = 0x410b3000;
 -}
 -
 -static void aarch64_neoverse_n1_initfn(Object *obj)
 -{
 -    ARMCPU *cpu = ARM_CPU(obj);
 -
 -    cpu->dtb_compatible = "arm,neoverse-n1";
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    set_feature(&cpu->env, ARM_FEATURE_NEON);
 -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 -    set_feature(&cpu->env, ARM_FEATURE_EL2);
 -    set_feature(&cpu->env, ARM_FEATURE_EL3);
 -    set_feature(&cpu->env, ARM_FEATURE_PMU);
 -
 -    /* Ordered by B2.4 AArch64 registers by functional group */
 -    cpu->clidr = 0x82000023;
 -    cpu->ctr = 0x8444c004;
 -    cpu->dcz_blocksize = 4;
 -    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
 -    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 -    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 -    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
 -    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 -    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 -    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 -    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
 -    cpu->id_afr0       = 0x00000000;
 -    cpu->isar.id_dfr0  = 0x04010088;
 -    cpu->isar.id_isar0 = 0x02101110;
 -    cpu->isar.id_isar1 = 0x13112111;
 -    cpu->isar.id_isar2 = 0x21232042;
 -    cpu->isar.id_isar3 = 0x01112131;
 -    cpu->isar.id_isar4 = 0x00010142;
 -    cpu->isar.id_isar5 = 0x01011121;
 -    cpu->isar.id_isar6 = 0x00000010;
 -    cpu->isar.id_mmfr0 = 0x10201105;
 -    cpu->isar.id_mmfr1 = 0x40000000;
 -    cpu->isar.id_mmfr2 = 0x01260000;
 -    cpu->isar.id_mmfr3 = 0x02122211;
 -    cpu->isar.id_mmfr4 = 0x00021110;
 -    cpu->isar.id_pfr0  = 0x10010131;
 -    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 -    cpu->isar.id_pfr2  = 0x00000011;
 -    cpu->midr = 0x414fd0c1;          /* r4p1 */
 -    cpu->revidr = 0;
 -
 -    /* From B2.23 CCSIDR_EL1 */
 -    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 -    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 -    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
 -
 -    /* From B2.98 SCTLR_EL3 */
 -    cpu->reset_sctlr = 0x30c50838;
 -
 -    /* From B4.23 ICH_VTR_EL2 */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -
 -    /* From B5.1 AdvSIMD AArch64 register summary */
 -    cpu->isar.mvfr0 = 0x10110222;
 -    cpu->isar.mvfr1 = 0x13211111;
 -    cpu->isar.mvfr2 = 0x00000043;
 -
 -    /* From D5.1 AArch64 PMU register summary */
 -    cpu->isar.reset_pmcr_el0 = 0x410c3000;
 -}
 -
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
  {
--    /* Define a whole list of registers */
+     /*
--    const ARMCPRegInfo *r;
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
--    for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
+     cpu->isar.id_aa64mmfr0 = t;
 -        define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
 +    size_t i;
 +    for (i = 0; i < len; ++i) {
 +        define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque);
      }
  }
-@@ -XXX,XX +XXX,XX @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
++static void aarch64_a57_initfn(Object *obj)
-  * user-space cannot alter any values and dynamic values pertaining to
++{
-  * execution state are hidden from user space view anyway.
++    ARMCPU *cpu = ARM_CPU(obj);
-  */
++
--void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
++    cpu->dtb_compatible = "arm,cortex-a57";
-+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
++    set_feature(&cpu->env, ARM_FEATURE_V8);
-+                                 const ARMCPRegUserSpaceInfo *mods,
++    set_feature(&cpu->env, ARM_FEATURE_NEON);
-+                                 size_t mods_len)
++    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 +    cpu->midr = 0x411fd070;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034070;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x8444c004;
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10101105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_isar6 = 0;
 +    cpu->isar.id_aa64pfr0 = 0x00002222;
 +    cpu->isar.id_aa64dfr0 = 0x10305106;
 +    cpu->isar.id_aa64isar0 = 0x00011120;
 +    cpu->isar.id_aa64mmfr0 = 0x00001124;
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->isar.dbgdevid = 0x01110f13;
 +    cpu->isar.dbgdevid1 = 0x2;
 +    cpu->isar.reset_pmcr_el0 = 0x41013000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 +    cpu->dcz_blocksize = 4; /* 64 bytes */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 +}
 +
 +static void aarch64_a53_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,cortex-a53";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 +    cpu->midr = 0x410fd034;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034070;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10101105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_isar6 = 0;
 +    cpu->isar.id_aa64pfr0 = 0x00002222;
 +    cpu->isar.id_aa64dfr0 = 0x10305106;
 +    cpu->isar.id_aa64isar0 = 0x00011120;
 +    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->isar.dbgdevid = 0x00110f13;
 +    cpu->isar.dbgdevid1 = 0x1;
 +    cpu->isar.reset_pmcr_el0 = 0x41033000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 +    cpu->dcz_blocksize = 4; /* 64 bytes */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 +}
 +
 +static void aarch64_a72_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,cortex-a72";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->midr = 0x410fd083;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034080;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x8444c004;
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_aa64pfr0 = 0x00002222;
 +    cpu->isar.id_aa64dfr0 = 0x10305106;
 +    cpu->isar.id_aa64isar0 = 0x00011120;
 +    cpu->isar.id_aa64mmfr0 = 0x00001124;
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->isar.dbgdevid = 0x01110f13;
 +    cpu->isar.dbgdevid1 = 0x2;
 +    cpu->isar.reset_pmcr_el0 = 0x41023000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
 +    cpu->dcz_blocksize = 4; /* 64 bytes */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 +}
 +
 +static void aarch64_a76_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,cortex-a76";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444C004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0b1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.18 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
 +
 +    /* From B2.93 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +
 +    /* From D5.1 AArch64 PMU register summary */
 +    cpu->isar.reset_pmcr_el0 = 0x410b3000;
 +}
 +
 +static void aarch64_a64fx_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,a64fx";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->midr = 0x461f0010;
 +    cpu->revidr = 0x00000000;
 +    cpu->ctr = 0x86668006;
 +    cpu->reset_sctlr = 0x30000180;
 +    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
 +    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
 +    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
 +    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
 +    cpu->id_aa64afr0 = 0x0000000000000000;
 +    cpu->id_aa64afr1 = 0x0000000000000000;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
 +    cpu->isar.id_aa64isar0 = 0x0000000010211120;
 +    cpu->isar.id_aa64isar1 = 0x0000000000010001;
 +    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
 +    cpu->clidr = 0x0000000080000023;
 +    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
 +    cpu->dcz_blocksize = 6; /* 256 bytes */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +
 +    /* The A64FX supports only 128, 256 and 512 bit vector lengths */
 +    aarch64_add_sve_properties(obj);
 +    cpu->sve_vq.supported = (1 << 0)  /* 128bit */
 +                          | (1 << 1)  /* 256bit */
 +                          | (1 << 3); /* 512bit */
 +
 +    cpu->isar.reset_pmcr_el0 = 0x46014040;
 +
 +    /* TODO:  Add A64FX specific HPC extension registers */
 +}
 +
 +static void aarch64_neoverse_n1_initfn(Object *obj)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +
 +    cpu->dtb_compatible = "arm,neoverse-n1";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444c004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0c1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.23 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
 +
 +    /* From B2.98 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +
 +    /* From D5.1 AArch64 PMU register summary */
 +    cpu->isar.reset_pmcr_el0 = 0x410c3000;
 +}
 +
  static void aarch64_host_initfn(Object *obj)
  {
--    const ARMCPRegUserSpaceInfo *m;
+ #if defined(CONFIG_KVM)
--    ARMCPRegInfo *r;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
--
+     qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
--    for (m = mods; m->name; m++) {
+ }
-+    for (size_t mi = 0; mi < mods_len; ++mi) {
-+        const ARMCPRegUserSpaceInfo *m = mods + mi;
+-static void aarch64_a64fx_initfn(Object *obj)
-         GPatternSpec *pat = NULL;
+-{
-+
+-    ARMCPU *cpu = ARM_CPU(obj);
-         if (m->is_glob) {
+-
-             pat = g_pattern_spec_new(m->name);
+-    cpu->dtb_compatible = "arm,a64fx";
-         }
+-    set_feature(&cpu->env, ARM_FEATURE_V8);
--        for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
+-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-+        for (size_t ri = 0; ri < regs_len; ++ri) {
+-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+            ARMCPRegInfo *r = regs + ri;
+-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-+
+-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-             if (pat && g_pattern_match_string(pat, r->name)) {
+-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-                 r->type = ARM_CP_CONST;
+-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-                 r->access = PL0U_R;
+-    cpu->midr = 0x461f0010;
 -    cpu->revidr = 0x00000000;
 -    cpu->ctr = 0x86668006;
 -    cpu->reset_sctlr = 0x30000180;
 -    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
 -    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
 -    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
 -    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
 -    cpu->id_aa64afr0 = 0x0000000000000000;
 -    cpu->id_aa64afr1 = 0x0000000000000000;
 -    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
 -    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
 -    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
 -    cpu->isar.id_aa64isar0 = 0x0000000010211120;
 -    cpu->isar.id_aa64isar1 = 0x0000000000010001;
 -    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
 -    cpu->clidr = 0x0000000080000023;
 -    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
 -    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
 -    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
 -    cpu->dcz_blocksize = 6; /* 256 bytes */
 -    cpu->gic_num_lrs = 4;
 -    cpu->gic_vpribits = 5;
 -    cpu->gic_vprebits = 5;
 -    cpu->gic_pribits = 5;
 -
 -    /* The A64FX supports only 128, 256 and 512 bit vector lengths */
 -    aarch64_add_sve_properties(obj);
 -    cpu->sve_vq.supported = (1 << 0)  /* 128bit */
 -                          | (1 << 1)  /* 256bit */
 -                          | (1 << 3); /* 512bit */
 -
 -    cpu->isar.reset_pmcr_el0 = 0x46014040;
 -
 -    /* TODO:  Add A64FX specific HPC extension registers */
 -}
 -
  static const ARMCPUInfo aarch64_cpus[] = {
      { .name = "cortex-a35",         .initfn = aarch64_a35_initfn },
      { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 --
 .25.1

-[PULL 05/23] target/arm: Make some more cpreg data static const
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-These particular data structures are not modified at runtime.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-5-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.c | 16 ++++++++--------
-file changed, 8 insertions(+), 8 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-               .resetvalue = cpu->pmceid1 },
-         };
- #ifdef CONFIG_USER_ONLY
--        ARMCPRegUserSpaceInfo v8_user_idregs[] = {
-+        static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
-             { .name = "ID_AA64PFR0_EL1",
-               .exported_bits = 0x000f000f00ff0000,
-               .fixed_bits    = 0x0000000000000011 },
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-      */
-     if (arm_feature(env, ARM_FEATURE_EL3)) {
-         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
--            ARMCPRegInfo nsacr = {
-+            static const ARMCPRegInfo nsacr = {
-                 .name = "NSACR", .type = ARM_CP_CONST,
-                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
-                 .access = PL1_RW, .accessfn = nsacr_access,
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-             };
-             define_one_arm_cp_reg(cpu, &nsacr);
-         } else {
--            ARMCPRegInfo nsacr = {
-+            static const ARMCPRegInfo nsacr = {
-                 .name = "NSACR",
-                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
-                 .access = PL3_RW | PL1_R,
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-         }
-     } else {
-         if (arm_feature(env, ARM_FEATURE_V8)) {
--            ARMCPRegInfo nsacr = {
-+            static const ARMCPRegInfo nsacr = {
-                 .name = "NSACR", .type = ARM_CP_CONST,
-                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
-                 .access = PL1_R,
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-               .access = PL1_R, .type = ARM_CP_CONST,
-               .resetvalue = cpu->pmsav7_dregion << 8
-         };
--        ARMCPRegInfo crn0_wi_reginfo = {
-+        static const ARMCPRegInfo crn0_wi_reginfo = {
-             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
-             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
-             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
-         };
- #ifdef CONFIG_USER_ONLY
--        ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
-+        static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
-             { .name = "MIDR_EL1",
-               .exported_bits = 0x00000000ffffffff },
-             { .name = "REVIDR_EL1"                },
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
-         };
- #ifdef CONFIG_USER_ONLY
--        ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
-+        static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
-             { .name = "MPIDR_EL1",
-               .fixed_bits = 0x0000000080000000 },
-         };
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-     }
-     if (arm_feature(env, ARM_FEATURE_VBAR)) {
--        ARMCPRegInfo vbar_cp_reginfo[] = {
-+        static const ARMCPRegInfo vbar_cp_reginfo[] = {
-             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
-               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
-               .access = PL1_RW, .writefn = vbar_write,
---
-.25.1

-[PULL 06/23] target/arm: Reorg ARMCPRegInfo type field bits
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Instead of defining ARM_CP_FLAG_MASK to remove flags,
-define ARM_CP_SPECIAL_MASK to isolate special cases.
-Sort the specials to the low bits. Use an enum.
-Split the large comment block so as to document each
-value separately.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-6-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h        | 130 +++++++++++++++++++++++--------------
- target/arm/cpu.c           |   4 +-
- target/arm/helper.c        |   4 +-
- target/arm/translate-a64.c |   6 +-
- target/arm/translate.c     |   6 +-
-files changed, 92 insertions(+), 58 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@
- #define TARGET_ARM_CPREGS_H
- /*
-- * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
-- * special-behaviour cp reg and bits [11..8] indicate what behaviour
-- * it has. Otherwise it is a simple cp reg, where CONST indicates that
-- * TCG can assume the value to be constant (ie load at translate time)
-- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
-- * indicates that the TB should not be ended after a write to this register
-- * (the default is that the TB ends after cp writes). OVERRIDE permits
-- * a register definition to override a previous definition for the
-- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
-- * old must have the OVERRIDE bit set.
-- * ALIAS indicates that this register is an alias view of some underlying
-- * state which is also visible via another register, and that the other
-- * register is handling migration and reset; registers marked ALIAS will not be
-- * migrated but may have their state set by syncing of register state from KVM.
-- * NO_RAW indicates that this register has no underlying state and does not
-- * support raw access for state saving/loading; it will not be used for either
-- * migration or KVM state synchronization. (Typically this is for "registers"
-- * which are actually used as instructions for cache maintenance and so on.)
-- * IO indicates that this register does I/O and therefore its accesses
-- * need to be marked with gen_io_start() and also end the TB. In particular,
-- * registers which implement clocks or timers require this.
-- * RAISES_EXC is for when the read or write hook might raise an exception;
-- * the generated code will synchronize the CPU state before calling the hook
-- * so that it is safe for the hook to call raise_exception().
-- * NEWEL is for writes to registers that might change the exception
-- * level - typically on older ARM chips. For those cases we need to
-- * re-read the new el when recomputing the translation flags.
-+ * ARMCPRegInfo type field bits:
-  */
--#define ARM_CP_SPECIAL           0x0001
--#define ARM_CP_CONST             0x0002
--#define ARM_CP_64BIT             0x0004
--#define ARM_CP_SUPPRESS_TB_END   0x0008
--#define ARM_CP_OVERRIDE          0x0010
--#define ARM_CP_ALIAS             0x0020
--#define ARM_CP_IO                0x0040
--#define ARM_CP_NO_RAW            0x0080
--#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
--#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
--#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
--#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
--#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
--#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
--#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
--#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
--#define ARM_CP_FPU               0x1000
--#define ARM_CP_SVE               0x2000
--#define ARM_CP_NO_GDB            0x4000
--#define ARM_CP_RAISES_EXC        0x8000
--#define ARM_CP_NEWEL             0x10000
--/* Mask of only the flag bits in a type field */
--#define ARM_CP_FLAG_MASK         0x1f0ff
-+enum {
-+    /*
-+     * Register must be handled specially during translation.
-+     * The method is one of the values below:
-+     */
-+    ARM_CP_SPECIAL_MASK          = 0x000f,
-+    /* Special: no change to PE state: writes ignored, reads ignored. */
-+    ARM_CP_NOP                   = 0x0001,
-+    /* Special: sysreg is WFI, for v5 and v6. */
-+    ARM_CP_WFI                   = 0x0002,
-+    /* Special: sysreg is NZCV. */
-+    ARM_CP_NZCV                  = 0x0003,
-+    /* Special: sysreg is CURRENTEL. */
-+    ARM_CP_CURRENTEL             = 0x0004,
-+    /* Special: sysreg is DC ZVA or similar. */
-+    ARM_CP_DC_ZVA                = 0x0005,
-+    ARM_CP_DC_GVA                = 0x0006,
-+    ARM_CP_DC_GZVA               = 0x0007,
-+
-+    /* Flag: reads produce resetvalue; writes ignored. */
-+    ARM_CP_CONST                 = 1 << 4,
-+    /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
-+    ARM_CP_64BIT                 = 1 << 5,
-+    /*
-+     * Flag: TB should not be ended after a write to this register
-+     * (the default is that the TB ends after cp writes).
-+     */
-+    ARM_CP_SUPPRESS_TB_END       = 1 << 6,
-+    /*
-+     * Flag: Permit a register definition to override a previous definition
-+     * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new
-+     * or the old must have the ARM_CP_OVERRIDE bit set.
-+     */
-+    ARM_CP_OVERRIDE              = 1 << 7,
-+    /*
-+     * Flag: Register is an alias view of some underlying state which is also
-+     * visible via another register, and that the other register is handling
-+     * migration and reset; registers marked ARM_CP_ALIAS will not be migrated
-+     * but may have their state set by syncing of register state from KVM.
-+     */
-+    ARM_CP_ALIAS                 = 1 << 8,
-+    /*
-+     * Flag: Register does I/O and therefore its accesses need to be marked
-+     * with gen_io_start() and also end the TB. In particular, registers which
-+     * implement clocks or timers require this.
-+     */
-+    ARM_CP_IO                    = 1 << 9,
-+    /*
-+     * Flag: Register has no underlying state and does not support raw access
-+     * for state saving/loading; it will not be used for either migration or
-+     * KVM state synchronization. Typically this is for "registers" which are
-+     * actually used as instructions for cache maintenance and so on.
-+     */
-+    ARM_CP_NO_RAW                = 1 << 10,
-+    /*
-+     * Flag: The read or write hook might raise an exception; the generated
-+     * code will synchronize the CPU state before calling the hook so that it
-+     * is safe for the hook to call raise_exception().
-+     */
-+    ARM_CP_RAISES_EXC            = 1 << 11,
-+    /*
-+     * Flag: Writes to the sysreg might change the exception level - typically
-+     * on older ARM chips. For those cases we need to re-read the new el when
-+     * recomputing the translation flags.
-+     */
-+    ARM_CP_NEWEL                 = 1 << 12,
-+    /*
-+     * Flag: Access check for this sysreg is identical to accessing FPU state
-+     * from an instruction: use translation fp_access_check().
-+     */
-+    ARM_CP_FPU                   = 1 << 13,
-+    /*
-+     * Flag: Access check for this sysreg is identical to accessing SVE state
-+     * from an instruction: use translation sve_access_check().
-+     */
-+    ARM_CP_SVE                   = 1 << 14,
-+    /* Flag: Do not expose in gdb sysreg xml. */
-+    ARM_CP_NO_GDB                = 1 << 15,
-+};
- /*
-  * Valid values for ARMCPRegInfo state field, indicating which of
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
-     ARMCPRegInfo *ri = value;
-     ARMCPU *cpu = opaque;
--    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
-+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
-         return;
-     }
-@@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
-     ARMCPU *cpu = opaque;
-     uint64_t oldvalue, newvalue;
--    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
-+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
-         return;
-     }
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-      * multiple times. Special registers (ie NOP/WFI) are
-      * never migratable and not even raw-accessible.
-      */
--    if ((r->type & ARM_CP_SPECIAL)) {
-+    if (r->type & ARM_CP_SPECIAL_MASK) {
-         r2->type |= ARM_CP_NO_RAW;
-     }
-     if (((r->crm == CP_ANY) && crm != 0) ||
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-     /* Check that the register definition has enough info to handle
-      * reads and writes if they are permitted.
-      */
--    if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
-+    if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
-         if (r->access & PL3_R) {
-             assert((r->fieldoffset ||
-                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
-     }
-     /* Handle special cases first */
--    switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
-+    switch (ri->type & ARM_CP_SPECIAL_MASK) {
-+    case 0:
-+        break;
-     case ARM_CP_NOP:
-         return;
-     case ARM_CP_NZCV:
-@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
-         }
-         return;
-     default:
--        break;
-+        g_assert_not_reached();
-     }
-     if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
-         return;
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-         }
-         /* Handle special cases first */
--        switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
-+        switch (ri->type & ARM_CP_SPECIAL_MASK) {
-+        case 0:
-+            break;
-         case ARM_CP_NOP:
-             return;
-         case ARM_CP_WFI:
-@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-             s->base.is_jmp = DISAS_WFI;
-             return;
-         default:
--            break;
-+            g_assert_not_reached();
-         }
-         if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
---
-.25.1

-[PULL 08/23] target/arm: Change cpreg access permissions to enum
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Create a typedef as well, and use it in ARMCPRegInfo.
-This won't be perfect for debugging, but it'll nicely
-display the most common cases.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h | 44 +++++++++++++++++++++++---------------------
- target/arm/helper.c |  2 +-
-files changed, 24 insertions(+), 22 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ enum {
-  * described with these bits, then use a laxer set of restrictions, and
-  * do the more restrictive/complex check inside a helper function.
-  */
--#define PL3_R 0x80
--#define PL3_W 0x40
--#define PL2_R (0x20 | PL3_R)
--#define PL2_W (0x10 | PL3_W)
--#define PL1_R (0x08 | PL2_R)
--#define PL1_W (0x04 | PL2_W)
--#define PL0_R (0x02 | PL1_R)
--#define PL0_W (0x01 | PL1_W)
-+typedef enum {
-+    PL3_R = 0x80,
-+    PL3_W = 0x40,
-+    PL2_R = 0x20 | PL3_R,
-+    PL2_W = 0x10 | PL3_W,
-+    PL1_R = 0x08 | PL2_R,
-+    PL1_W = 0x04 | PL2_W,
-+    PL0_R = 0x02 | PL1_R,
-+    PL0_W = 0x01 | PL1_W,
--/*
-- * For user-mode some registers are accessible to EL0 via a kernel
-- * trap-and-emulate ABI. In this case we define the read permissions
-- * as actually being PL0_R. However some bits of any given register
-- * may still be masked.
-- */
-+    /*
-+     * For user-mode some registers are accessible to EL0 via a kernel
-+     * trap-and-emulate ABI. In this case we define the read permissions
-+     * as actually being PL0_R. However some bits of any given register
-+     * may still be masked.
-+     */
- #ifdef CONFIG_USER_ONLY
--#define PL0U_R PL0_R
-+    PL0U_R = PL0_R,
- #else
--#define PL0U_R PL1_R
-+    PL0U_R = PL1_R,
- #endif
--#define PL3_RW (PL3_R | PL3_W)
--#define PL2_RW (PL2_R | PL2_W)
--#define PL1_RW (PL1_R | PL1_W)
--#define PL0_RW (PL0_R | PL0_W)
-+    PL3_RW = PL3_R | PL3_W,
-+    PL2_RW = PL2_R | PL2_W,
-+    PL1_RW = PL1_R | PL1_W,
-+    PL0_RW = PL0_R | PL0_W,
-+} CPAccessRights;
- typedef enum CPAccessResult {
-     /* Access is permitted */
-@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
-     /* Register type: ARM_CP_* bits/values */
-     int type;
-     /* Access rights: PL*_[RW] */
--    int access;
-+    CPAccessRights access;
-     /* Security state: ARM_CP_SECSTATE_* bits/values */
-     int secure;
-     /*
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-      * to encompass the generic architectural permission check.
-      */
-     if (r->state != ARM_CP_STATE_AA32) {
--        int mask = 0;
-+        CPAccessRights mask;
-         switch (r->opc1) {
-         case 0:
-             /* min_EL EL1, but some accessible to EL0 via kernel ABI */
---
-.25.1

-[PULL 09/23] target/arm: Name CPState type
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Give this enum a name and use in ARMCPRegInfo,
-add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-9-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h | 6 +++---
- target/arm/helper.c | 6 ++++--
-files changed, 7 insertions(+), 5 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ enum {
-  * Note that we rely on the values of these enums as we iterate through
-  * the various states in some places.
-  */
--enum {
-+typedef enum {
-     ARM_CP_STATE_AA32 = 0,
-     ARM_CP_STATE_AA64 = 1,
-     ARM_CP_STATE_BOTH = 2,
--};
-+} CPState;
- /*
-  * ARM CP register secure state flags.  These flags identify security state
-@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
-     uint8_t opc1;
-     uint8_t opc2;
-     /* Execution state in which this register is visible: ARM_CP_STATE_* */
--    int state;
-+    CPState state;
-     /* Register type: ARM_CP_* bits/values */
-     int type;
-     /* Access rights: PL*_[RW] */
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
- }
- static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
--                                   void *opaque, int state, int secstate,
-+                                   void *opaque, CPState state, int secstate,
-                                    int crm, int opc1, int opc2,
-                                    const char *name)
- {
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
-      * the register, if any.
-      */
--    int crm, opc1, opc2, state;
-+    int crm, opc1, opc2;
-     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
-     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
-     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
-     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
-     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
-     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
-+    CPState state;
-+
-     /* 64 bit registers have only CRm and Opc1 fields */
-     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
-     /* op0 only exists in the AArch64 encodings */
---
-.25.1

-[PULL 10/23] target/arm: Name CPSecureState type
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
-Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
-is handled in define_one_arm_cp_reg_with_opaque.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-10-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h | 7 ++++---
- target/arm/helper.c | 7 +++++--
-files changed, 9 insertions(+), 5 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
-  * registered entry will only have one to identify whether the entry is secure
-  * or non-secure.
-  */
--enum {
-+typedef enum {
-+    ARM_CP_SECSTATE_BOTH = 0,       /* define one cpreg for each secstate */
-     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
-     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
--};
-+} CPSecureState;
- /*
-  * Access rights:
-@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
-     /* Access rights: PL*_[RW] */
-     CPAccessRights access;
-     /* Security state: ARM_CP_SECSTATE_* bits/values */
--    int secure;
-+    CPSecureState secure;
-     /*
-      * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
-      * this register was defined: can be used to hand data through to the
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
- }
- static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
--                                   void *opaque, CPState state, int secstate,
-+                                   void *opaque, CPState state,
-+                                   CPSecureState secstate,
-                                    int crm, int opc1, int opc2,
-                                    const char *name)
- {
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                                    r->secure, crm, opc1, opc2,
-                                                    r->name);
-                             break;
--                        default:
-+                        case ARM_CP_SECSTATE_BOTH:
-                             name = g_strdup_printf("%s_S", r->name);
-                             add_cpreg_to_hashtable(cpu, r, opaque, state,
-                                                    ARM_CP_SECSTATE_S,
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                                    ARM_CP_SECSTATE_NS,
-                                                    crm, opc1, opc2, r->name);
-                             break;
-+                        default:
-+                            g_assert_not_reached();
-                         }
-                     } else {
-                         /* AArch64 registers get mapped to non-secure instance
---
-.25.1

-[PULL 11/23] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The new_key field is always non-zero -- drop the if.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-11-richard.henderson@linaro.org
-[PMM: reinstated dropped PL3_RW mask]
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.c | 23 +++++++++++------------
-file changed, 11 insertions(+), 12 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
-     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
-         const struct E2HAlias *a = &aliases[i];
--        ARMCPRegInfo *src_reg, *dst_reg;
-+        ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
-+        uint32_t *new_key;
-+        bool ok;
-         if (a->feature && !a->feature(&cpu->isar)) {
-             continue;
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
-         g_assert(src_reg->opaque == NULL);
-         /* Create alias before redirection so we dup the right data. */
--        if (a->new_key) {
--            ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
--            uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
--            bool ok;
-+        new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-+        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
--            new_reg->name = a->new_name;
--            new_reg->type |= ARM_CP_ALIAS;
--            /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
--            new_reg->access &= PL2_RW | PL3_RW;
-+        new_reg->name = a->new_name;
-+        new_reg->type |= ARM_CP_ALIAS;
-+        /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
-+        new_reg->access &= PL2_RW | PL3_RW;
--            ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
--            g_assert(ok);
--        }
-+        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
-+        g_assert(ok);
-         src_reg->opaque = dst_reg;
-         src_reg->orig_readfn = src_reg->readfn ?: raw_read;
---
-.25.1

-[PULL 12/23] target/arm: Store cpregs key in the hash table directly
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Cast the uint32_t key into a gpointer directly, which
-allows us to avoid allocating storage for each key.
-Use g_hash_table_lookup when we already have a gpointer
-(e.g. for callbacks like count_cpreg), or when using
-get_arm_cp_reginfo would require casting away const.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-12-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.c     |  4 ++--
- target/arm/gdbstub.c |  2 +-
- target/arm/helper.c  | 41 ++++++++++++++++++-----------------------
-files changed, 21 insertions(+), 26 deletions(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
-     ARMCPU *cpu = ARM_CPU(obj);
-     cpu_set_cpustate_pointers(cpu);
--    cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
--                                         g_free, cpreg_hashtable_data_destroy);
-+    cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
-+                                         NULL, cpreg_hashtable_data_destroy);
-     QLIST_INIT(&cpu->pre_el_change_hooks);
-     QLIST_INIT(&cpu->el_change_hooks);
-diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/gdbstub.c
-+++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
- static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
-                                         gpointer p)
- {
--    uint32_t ri_key = *(uint32_t *)key;
-+    uint32_t ri_key = (uintptr_t)key;
-     ARMCPRegInfo *ri = value;
-     RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
-     GString *s = param->s;
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
- static void add_cpreg_to_list(gpointer key, gpointer opaque)
- {
-     ARMCPU *cpu = opaque;
--    uint64_t regidx;
--    const ARMCPRegInfo *ri;
--
--    regidx = *(uint32_t *)key;
--    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
-+    uint32_t regidx = (uintptr_t)key;
-+    const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
-     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
-         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
- static void count_cpreg(gpointer key, gpointer opaque)
- {
-     ARMCPU *cpu = opaque;
--    uint64_t regidx;
-     const ARMCPRegInfo *ri;
--    regidx = *(uint32_t *)key;
--    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
-+    ri = g_hash_table_lookup(cpu->cp_regs, key);
-     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
-         cpu->cpreg_array_len++;
-@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
- static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
- {
--    uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
--    uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
-+    uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a);
-+    uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b);
-     if (aidx > bidx) {
-         return 1;
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
-     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
-         const struct E2HAlias *a = &aliases[i];
-         ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
--        uint32_t *new_key;
-         bool ok;
-         if (a->feature && !a->feature(&cpu->isar)) {
-             continue;
-         }
--        src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
--        dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
-+        src_reg = g_hash_table_lookup(cpu->cp_regs,
-+                                      (gpointer)(uintptr_t)a->src_key);
-+        dst_reg = g_hash_table_lookup(cpu->cp_regs,
-+                                      (gpointer)(uintptr_t)a->dst_key);
-         g_assert(src_reg != NULL);
-         g_assert(dst_reg != NULL);
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
-         /* Create alias before redirection so we dup the right data. */
-         new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
--        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
-         new_reg->name = a->new_name;
-         new_reg->type |= ARM_CP_ALIAS;
-         /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
-         new_reg->access &= PL2_RW | PL3_RW;
--        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
-+        ok = g_hash_table_insert(cpu->cp_regs,
-+                                 (gpointer)(uintptr_t)a->new_key, new_reg);
-         g_assert(ok);
-         src_reg->opaque = dst_reg;
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-     /* Private utility function for define_one_arm_cp_reg_with_opaque():
-      * add a single reginfo struct to the hash table.
-      */
--    uint32_t *key = g_new(uint32_t, 1);
-+    uint32_t key;
-     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
-     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
-     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
-             r2->cp = CP_REG_ARM64_SYSREG_CP;
-         }
--        *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
--                                  r2->opc0, opc1, opc2);
-+        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
-+                                 r2->opc0, opc1, opc2);
-     } else {
--        *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
-+        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
-     }
-     if (opaque) {
-         r2->opaque = opaque;
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-      * requested.
-      */
-     if (!(r->type & ARM_CP_OVERRIDE)) {
--        ARMCPRegInfo *oldreg;
--        oldreg = g_hash_table_lookup(cpu->cp_regs, key);
-+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
-         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
-             fprintf(stderr, "Register redefined: cp=%d %d bit "
-                     "crn=%d crm=%d opc1=%d opc2=%d, "
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-             g_assert_not_reached();
-         }
-     }
--    g_hash_table_insert(cpu->cp_regs, key, r2);
-+    g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
- }
-@@ -XXX,XX +XXX,XX @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
- const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
- {
--    return g_hash_table_lookup(cpregs, &encoded_cp);
-+    return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp);
- }
- void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
---
-.25.1

-[PULL 13/23] target/arm: Merge allocation of the cpreg and its name
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Simplify freeing cp_regs hash table entries by using a single
-allocation for the entire value.
-This fixes a theoretical bug if we were to ever free the entire
-hash table, because we've been installing string literal constants
-into the cpreg structure in define_arm_vh_e2h_redirects_aliases.
-However, at present we only free entries created for AArch32
-wildcard cpregs which get overwritten by more specific cpregs,
-so this bug is never exposed.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-13-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.c    | 16 +---------------
- target/arm/helper.c | 10 ++++++++--
-files changed, 9 insertions(+), 17 deletions(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
-     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
- }
--static void cpreg_hashtable_data_destroy(gpointer data)
--{
--    /*
--     * Destroy function for cpu->cp_regs hashtable data entries.
--     * We must free the name string because it was g_strdup()ed in
--     * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
--     * from r->name because we know we definitely allocated it.
--     */
--    ARMCPRegInfo *r = data;
--
--    g_free((void *)r->name);
--    g_free(r);
--}
--
- static void arm_cpu_initfn(Object *obj)
- {
-     ARMCPU *cpu = ARM_CPU(obj);
-     cpu_set_cpustate_pointers(cpu);
-     cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
--                                         NULL, cpreg_hashtable_data_destroy);
-+                                         NULL, g_free);
-     QLIST_INIT(&cpu->pre_el_change_hooks);
-     QLIST_INIT(&cpu->el_change_hooks);
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-      * add a single reginfo struct to the hash table.
-      */
-     uint32_t key;
--    ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
-+    ARMCPRegInfo *r2;
-     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
-     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
-+    size_t name_len;
-+
-+    /* Combine cpreg and name into one allocation. */
-+    name_len = strlen(name) + 1;
-+    r2 = g_malloc(sizeof(*r2) + name_len);
-+    *r2 = *r;
-+    r2->name = memcpy(r2 + 1, name, name_len);
--    r2->name = g_strdup(name);
-     /* Reset the secure state to the specific incoming state.  This is
-      * necessary as the register may have been defined with both states.
-      */
---
-.25.1

-[PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashtable
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Move the computation of key to the top of the function.
-Hoist the resolution of cp as well, as an input to the
-computation of key.
-This will be required by a subsequent patch.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.c | 49 +++++++++++++++++++++++++--------------------
-file changed, 27 insertions(+), 22 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-     ARMCPRegInfo *r2;
-     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
-     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
-+    int cp = r->cp;
-     size_t name_len;
-+    switch (state) {
-+    case ARM_CP_STATE_AA32:
-+        /* We assume it is a cp15 register if the .cp field is left unset. */
-+        if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
-+            cp = 15;
-+        }
-+        key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
-+        break;
-+    case ARM_CP_STATE_AA64:
-+        /*
-+         * To allow abbreviation of ARMCPRegInfo definitions, we treat
-+         * cp == 0 as equivalent to the value for "standard guest-visible
-+         * sysreg".  STATE_BOTH definitions are also always "standard sysreg"
-+         * in their AArch64 view (the .cp value may be non-zero for the
-+         * benefit of the AArch32 view).
-+         */
-+        if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
-+            cp = CP_REG_ARM64_SYSREG_CP;
-+        }
-+        key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
-+        break;
-+    default:
-+        g_assert_not_reached();
-+    }
-+
-     /* Combine cpreg and name into one allocation. */
-     name_len = strlen(name) + 1;
-     r2 = g_malloc(sizeof(*r2) + name_len);
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-         }
-         if (r->state == ARM_CP_STATE_BOTH) {
--            /* We assume it is a cp15 register if the .cp field is left unset.
--             */
--            if (r2->cp == 0) {
--                r2->cp = 15;
--            }
--
- #if HOST_BIG_ENDIAN
-             if (r2->fieldoffset) {
-                 r2->fieldoffset += sizeof(uint32_t);
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
- #endif
-         }
-     }
--    if (state == ARM_CP_STATE_AA64) {
--        /* To allow abbreviation of ARMCPRegInfo
--         * definitions, we treat cp == 0 as equivalent to
--         * the value for "standard guest-visible sysreg".
--         * STATE_BOTH definitions are also always "standard
--         * sysreg" in their AArch64 view (the .cp value may
--         * be non-zero for the benefit of the AArch32 view).
--         */
--        if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
--            r2->cp = CP_REG_ARM64_SYSREG_CP;
--        }
--        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
--                                 r2->opc0, opc1, opc2);
--    } else {
--        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
--    }
-     if (opaque) {
-         r2->opaque = opaque;
-     }
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-     /* Make sure reginfo passed to helpers for wildcarded regs
-      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
-      */
-+    r2->cp = cp;
-     r2->crm = crm;
-     r2->opc1 = opc1;
-     r2->opc2 = opc2;
---
-.25.1

-[PULL 15/23] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Put most of the value writeback to the same place,
-and improve the comment that goes with them.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-15-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.c | 28 ++++++++++++----------------
-file changed, 12 insertions(+), 16 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-     *r2 = *r;
-     r2->name = memcpy(r2 + 1, name, name_len);
--    /* Reset the secure state to the specific incoming state.  This is
--     * necessary as the register may have been defined with both states.
-+    /*
-+     * Update fields to match the instantiation, overwiting wildcards
-+     * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
-      */
-+    r2->cp = cp;
-+    r2->crm = crm;
-+    r2->opc1 = opc1;
-+    r2->opc2 = opc2;
-+    r2->state = state;
-     r2->secure = secstate;
-+    if (opaque) {
-+        r2->opaque = opaque;
-+    }
-     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
-         /* Register is banked (using both entries in array).
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
- #endif
-         }
-     }
--    if (opaque) {
--        r2->opaque = opaque;
--    }
--    /* reginfo passed to helpers is correct for the actual access,
--     * and is never ARM_CP_STATE_BOTH:
--     */
--    r2->state = state;
--    /* Make sure reginfo passed to helpers for wildcarded regs
--     * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
--     */
--    r2->cp = cp;
--    r2->crm = crm;
--    r2->opc1 = opc1;
--    r2->opc2 = opc2;
-+
-     /* By convention, for wildcarded registers only the first
-      * entry is used for migration; the others are marked as
-      * ALIAS so we don't try to transfer the register
---
-.25.1

-[PULL 21/23] target/arm: Add isar predicates for FEAT_Debugv8p2
+[PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Francisco Iglesias <francisco.iglesias@amd.com>
+Connect ZynqMP's USB controllers.
+Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-24-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 15 +++++++++++++++
+ include/hw/arm/xlnx-zynqmp.h |  3 +++
-file changed, 15 insertions(+)
+ hw/arm/xlnx-zynqmp.c         | 36 ++++++++++++++++++++++++++++++++++++
 files changed, 39 insertions(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/include/hw/arm/xlnx-zynqmp.h
-+++ b/target/arm/cpu.h
++++ b/include/hw/arm/xlnx-zynqmp.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@
-     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
+ #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
  #include "hw/misc/xlnx-zynqmp-crf.h"
  #include "hw/timer/cadence_ttc.h"
 +#include "hw/usb/hcd-dwc3.h"
  #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
  OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
  #define XLNX_ZYNQMP_NUM_SPIS 2
  #define XLNX_ZYNQMP_NUM_GDMA_CH 8
  #define XLNX_ZYNQMP_NUM_ADMA_CH 8
 +#define XLNX_ZYNQMP_NUM_USB 2
  #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
  #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
      XlnxZynqMPAPUCtrl apu_ctrl;
      XlnxZynqMPCRF crf;
      CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
 +    USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
      char *boot_cpu;
      ARMCPU *boot_cpu_ptr;
 diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-zynqmp.c
 +++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 , 78, 79, 80, 81, 82, 83, 84
  };
 +static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
 +    0xFE200000, 0xFE300000
 +};
 +
 +static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
 +    65, 70
 +};
 +
  typedef struct XlnxZynqMPGICRegion {
      int region_index;
      uint32_t address;
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
      object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
      object_initialize_child(obj, "qspi-irq-orgate",
                              &s->qspi_irq_orgate, TYPE_OR_IRQ);
 +
 +    for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
 +        object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
 +    }
  }
-+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
+ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
-+{
+@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
-+    return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+         object_property_add_alias(OBJECT(s), bus_name,
-+}
+                                   OBJECT(&s->qspi), target_bus);
      }
 +
- /*
++    for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
-  * 64-bit feature tests via id registers.
++        if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
-  */
++                                      OBJECT(system_memory), errp)) {
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
++            return;
-     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
++        }
 +
 +        qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
 +        qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
 +
 +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
 +            return;
 +        }
 +
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
 +                           gic_spi[usb_intr[i]]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
 +                           gic_spi[usb_intr[i] + 1]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
 +                           gic_spi[usb_intr[i] + 2]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
 +                           gic_spi[usb_intr[i] + 3]);
 +    }
  }
-+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
+ static Property xlnx_zynqmp_props[] = {
 +{
 +    return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
 +}
 +
  static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
  {
      return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
      return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
  }
 +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
 +{
 +    return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
 +}
 +
  /*
   * Forward to the above feature tests given an ARMCPU pointer.
   */
 --
 .25.1

-[PULL 20/23] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
+[PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
-Since e03b56863d2bc, our host endian indicator is unconditionally
+The devicetree specification requires a 'model' property in the root
-set, which means that we can use a normal C condition.
+node. Fix the corresponding dt-validate warning:
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+  /: 'model' is a required property
   From schema: dtschema/schemas/root-node.yaml
 Use the same name for model as for compatible. The specification
 recommends that 'compatible' follows the format 'manufacturer,model' and
 'model' follows the format 'manufacturer,model-number'. Since our
 'compatible' doesn't observe this, 'model' doesn't really need to
 either.
 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-20-richard.henderson@linaro.org
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-[PMM: quote correct git hash in commit message]
+Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 9 +++------
+ hw/arm/virt.c | 1 +
-file changed, 3 insertions(+), 6 deletions(-)
+file changed, 1 insertion(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/virt.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
-             r2->type |= ARM_CP_ALIAS;
+     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
-         }
+     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
+     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
--        if (r->state == ARM_CP_STATE_BOTH) {
++    qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
--#if HOST_BIG_ENDIAN
--            if (r2->fieldoffset) {
+     /* /chosen must exist for load_dtb to fill in necessary properties later */
--                r2->fieldoffset += sizeof(uint32_t);
+     qemu_fdt_add_subnode(fdt, "/chosen");
 -            }
 -#endif
 +        if (HOST_BIG_ENDIAN &&
 +            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
 +            r2->fieldoffset += sizeof(uint32_t);
          }
      }
 --
 .25.1

-[PULL 19/23] target/arm: Reformat comments in add_cpreg_to_hashtable
+[PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
-Put the block comments into the current coding style.
+The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
 the corresponding dt-validate warning:
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+  interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
   From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-19-richard.henderson@linaro.org
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 24 +++++++++++++++---------
+ hw/arm/virt.c | 1 +
-file changed, 15 insertions(+), 9 deletions(-)
+file changed, 1 insertion(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/virt.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
-     return cpu_list;
+     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
- }
+                             "arm,gic-v3-its");
+     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
-+/*
++    qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
-+ * Private utility function for define_one_arm_cp_reg_with_opaque():
+     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
-+ * add a single reginfo struct to the hash table.
+, vms->memmap[VIRT_GIC_ITS].base,
-+ */
+, vms->memmap[VIRT_GIC_ITS].size);
  static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                     void *opaque, CPState state,
                                     CPSecureState secstate,
                                     int crm, int opc1, int opc2,
                                     const char *name)
  {
 -    /* Private utility function for define_one_arm_cp_reg_with_opaque():
 -     * add a single reginfo struct to the hash table.
 -     */
      uint32_t key;
      ARMCPRegInfo *r2;
      bool is64 = r->type & ARM_CP_64BIT;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
      if (isbanked) {
 -        /* Register is banked (using both entries in array).
 +        /*
 +         * Register is banked (using both entries in array).
           * Overwriting fieldoffset as the array is only used to define
           * banked registers but later only fieldoffset is used.
           */
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      if (state == ARM_CP_STATE_AA32) {
          if (isbanked) {
 -            /* If the register is banked then we don't need to migrate or
 +            /*
 +             * If the register is banked then we don't need to migrate or
               * reset the 32-bit instance in certain cases:
               *
               * 1) If the register has both 32-bit and 64-bit instances then we
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                  r2->type |= ARM_CP_ALIAS;
              }
          } else if ((secstate != r->secure) && !ns) {
 -            /* The register is not banked so we only want to allow migration of
 -             * the non-secure instance.
 +            /*
 +             * The register is not banked so we only want to allow migration
 +             * of the non-secure instance.
               */
              r2->type |= ARM_CP_ALIAS;
          }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          }
      }
 -    /* By convention, for wildcarded registers only the first
 +    /*
 +     * By convention, for wildcarded registers only the first
       * entry is used for migration; the others are marked as
       * ALIAS so we don't try to transfer the register
       * multiple times. Special registers (ie NOP/WFI) are
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
      }
 -    /* Check that raw accesses are either forbidden or handled. Note that
 +    /*
 +     * Check that raw accesses are either forbidden or handled. Note that
       * we can't assert this earlier because the setup of fieldoffset for
       * banked registers has to be done first.
       */
 --
 .25.1

-[PULL 18/23] target/arm: Perform override check early in add_cpreg_to_hashtable
+[PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
-Perform the override check early, so that it is still done
+The "msi-parent" property can be used on the PCI node when MSIs do not
-even when we decide to discard an unreachable cpreg.
+contain sideband data (device IDs) [1]. In QEMU, MSI transactions
 contain the requester ID, so the PCI node should use the "msi-map"
 property instead of "msi-parent". In our case the property describes an
 identity map between requester ID and sideband data.
-Use assert not printf+abort.
+This fixes a warning when passing the DTB generated by QEMU to dtc,
 following a recent change to the GICv3 node:
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+  Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1
 [1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt
 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-18-richard.henderson@linaro.org
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 22 ++++++++--------------
+ hw/arm/virt.c | 4 ++--
-file changed, 8 insertions(+), 14 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/virt.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
-         g_assert_not_reached();
+     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
      if (vms->msi_phandle) {
 -        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
 -                               vms->msi_phandle);
 +        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
 +                               0, vms->msi_phandle, 0, 0x10000);
      }
-+    /* Overriding of an existing definition must be explicitly requested. */
+     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 +    if (!(r->type & ARM_CP_OVERRIDE)) {
 +        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
 +        if (oldreg) {
 +            assert(oldreg->type & ARM_CP_OVERRIDE);
 +        }
 +    }
 +
      /* Combine cpreg and name into one allocation. */
      name_len = strlen(name) + 1;
      r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          assert(!raw_accessors_invalid(r2));
      }
 -    /* Overriding of an existing definition must be explicitly
 -     * requested.
 -     */
 -    if (!(r->type & ARM_CP_OVERRIDE)) {
 -        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
 -        if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
 -            fprintf(stderr, "Register redefined: cp=%d %d bit "
 -                    "crn=%d crm=%d opc1=%d opc2=%d, "
 -                    "was %s, now %s\n", r2->cp, 32 + 32 * is64,
 -                    r2->crn, r2->crm, r2->opc1, r2->opc2,
 -                    oldreg->name, r2->name);
 -            g_assert_not_reached();
 -        }
 -    }
      g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
  }
 --
 .25.1

-[PULL 17/23] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
+[PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
-Computing isbanked only once makes the code
+The SMMUv3 node isn't expected to have clock properties
-a bit easier to read.
+(unlike the SMMUv2). Fix the corresponding dt-validate warning:
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+  smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
   From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-17-richard.henderson@linaro.org
+[PMM: tweaked commit message as suggested by Eric]
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 6 ++++--
+ hw/arm/virt.c | 2 --
-file changed, 4 insertions(+), 2 deletions(-)
+file changed, 2 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/virt.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
-     bool is64 = r->type & ARM_CP_64BIT;
+     qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
-     bool ns = secstate & ARM_CP_SECSTATE_NS;
+                      sizeof(irq_names));
-     int cp = r->cp;
-+    bool isbanked;
+-    qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
-     size_t name_len;
+-    qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
+     qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
-     switch (state) {
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
          r2->opaque = opaque;
      }
 -    if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
 +    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 +    if (isbanked) {
          /* Register is banked (using both entries in array).
           * Overwriting fieldoffset as the array is only used to define
           * banked registers but later only fieldoffset is used.
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      }
      if (state == ARM_CP_STATE_AA32) {
 -        if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
 +        if (isbanked) {
              /* If the register is banked then we don't need to migrate or
               * reset the 32-bit instance in certain cases:
               *
 --
 .25.1

-[PULL 16/23] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
+[PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jerome Forissier <jerome.forissier@linaro.org>
-Bool is a more appropriate type for these variables.
+SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
 it with ARM_CP_EL3_NO_EL2_KEEP.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Cc: qemu-stable@nongnu.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
-Message-id: 20220501055028.646596-16-richard.henderson@linaro.org
+Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 4 ++--
+ target/arm/helper.c | 2 +-
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-      */
+       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
-     uint32_t key;
+     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
-     ARMCPRegInfo *r2;
+       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
--    int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
+-      .access = PL2_RW, .type = ARM_CP_ALIAS,
--    int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
++      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
-+    bool is64 = r->type & ARM_CP_64BIT;
+       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
-+    bool ns = secstate & ARM_CP_SECSTATE_NS;
+     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
-     int cp = r->cp;
+       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
      size_t name_len;
 --
 .25.1

Two small bugfixes, plus most of RTH's refactoring of cpregs
handling.

-- PMM

The following changes since commit 1fba9dc71a170b3a05b9d3272dd8ecfe7f26e215:

Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging (2022-05-04 08:07:02 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220505

for you to fetch changes up to 99a50d1a67c602126fc2b3a4812d3000eba9bf34:

target/arm: read access to performance counters from EL0 (2022-05-05 09:36:22 +0100)

----------------------------------------------------------------
target-arm queue:
 * Enable read access to performance counters from EL0
 * Enable SCTLR_EL1.BT0 for aarch64-linux-user
 * Refactoring of cpreg handling

----------------------------------------------------------------
Alex Zuepke (1):
      target/arm: read access to performance counters from EL0

Richard Henderson (22):
      target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
      target/arm: Split out cpregs.h
      target/arm: Reorg CPAccessResult and access_check_cp_reg
      target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
      target/arm: Make some more cpreg data static const
      target/arm: Reorg ARMCPRegInfo type field bits
      target/arm: Avoid bare abort() or assert(0)
      target/arm: Change cpreg access permissions to enum
      target/arm: Name CPState type
      target/arm: Name CPSecureState type
      target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
      target/arm: Store cpregs key in the hash table directly
      target/arm: Merge allocation of the cpreg and its name
      target/arm: Hoist computation of key in add_cpreg_to_hashtable
      target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
      target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
      target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
      target/arm: Perform override check early in add_cpreg_to_hashtable
      target/arm: Reformat comments in add_cpreg_to_hashtable
      target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
      target/arm: Add isar predicates for FEAT_Debugv8p2
      target/arm: Add isar_feature_{aa64,any}_ras

From: Richard Henderson <richard.henderson@linaro.org>

This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17).  The linux kernel
sets this in bti_enable().

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
[PMM: remove stray change to makefile comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c                  |  2 ++
 tests/tcg/aarch64/bti-3.c         | 42 +++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  6 ++---
 3 files changed, 47 insertions(+), 3 deletions(-)
 create mode 100644 tests/tcg/aarch64/bti-3.c

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         /* Enable all PAC keys.  */
         env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
                                   SCTLR_EnDA | SCTLR_EnDB);
+        /* Trap on btype=3 for PACIxSP. */
+        env->cp15.sctlr_el[1] |= SCTLR_BT0;
         /* and to the FP/Neon instructions */
         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
         /* and to the SVE instructions */
diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/aarch64/bti-3.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BTI vs PACIASP
+ */
+
+#include "bti-crt.inc.c"
+
+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
+{
+    uc->uc_mcontext.pc += 8;
+    uc->uc_mcontext.pstate = 1;
+}
+
+#define BTYPE_1() \
+    asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_2() \
+    asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_3() \
+    asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x15", "x30")
+
+#define TEST(WHICH, EXPECT) \
+    do { WHICH(); fail += skipped ^ EXPECT; } while (0)
+
+int main()
+{
+    int fail = 0;
+    int skipped;
+
+    /* Signal-like with SA_SIGINFO.  */
+    signal_info(SIGILL, skip2_sigill);
+
+    /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
+    TEST(BTYPE_1, 0);
+    TEST(BTYPE_2, 0);
+    TEST(BTYPE_3, 1);
+
+    return fail;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ endif
 # BTI Tests
 # bti-1 tests the elf notes, so we require special compiler support.
 ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
-AARCH64_TESTS += bti-1
-bti-1: CFLAGS += -mbranch-protection=standard
-bti-1: LDFLAGS += -nostdlib
+AARCH64_TESTS += bti-1 bti-3
+bti-1 bti-3: CFLAGS += -mbranch-protection=standard
+bti-1 bti-3: LDFLAGS += -nostdlib
 endif
 # bti-2 tests PROT_BTI, so no special compiler support required.
 AARCH64_TESTS += bti-2
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move ARMCPRegInfo and all related declarations to a new
internal header, out of the public cpu.h.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h        | 413 +++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h           | 368 ---------------------------------
 hw/arm/pxa2xx.c            |   1 +
 hw/arm/pxa2xx_pic.c        |   1 +
 hw/intc/arm_gicv3_cpuif.c  |   1 +
 hw/intc/arm_gicv3_kvm.c    |   2 +
 target/arm/cpu.c           |   1 +
 target/arm/cpu64.c         |   1 +
 target/arm/cpu_tcg.c       |   1 +
 target/arm/gdbstub.c       |   3 +-
 target/arm/helper.c        |   1 +
 target/arm/op_helper.c     |   1 +
 target/arm/translate-a64.c |   4 +-
 target/arm/translate.c     |   3 +-
 14 files changed, 427 insertions(+), 374 deletions(-)
 create mode 100644 target/arm/cpregs.h

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU ARM CP Register access and descriptions
+ *
+ * Copyright (c) 2022 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#ifndef TARGET_ARM_CPREGS_H
+#define TARGET_ARM_CPREGS_H
+
+/*
+ * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
+ * special-behaviour cp reg and bits [11..8] indicate what behaviour
+ * it has. Otherwise it is a simple cp reg, where CONST indicates that
+ * TCG can assume the value to be constant (ie load at translate time)
+ * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
+ * indicates that the TB should not be ended after a write to this register
+ * (the default is that the TB ends after cp writes). OVERRIDE permits
+ * a register definition to override a previous definition for the
+ * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
+ * old must have the OVERRIDE bit set.
+ * ALIAS indicates that this register is an alias view of some underlying
+ * state which is also visible via another register, and that the other
+ * register is handling migration and reset; registers marked ALIAS will not be
+ * migrated but may have their state set by syncing of register state from KVM.
+ * NO_RAW indicates that this register has no underlying state and does not
+ * support raw access for state saving/loading; it will not be used for either
+ * migration or KVM state synchronization. (Typically this is for "registers"
+ * which are actually used as instructions for cache maintenance and so on.)
+ * IO indicates that this register does I/O and therefore its accesses
+ * need to be marked with gen_io_start() and also end the TB. In particular,
+ * registers which implement clocks or timers require this.
+ * RAISES_EXC is for when the read or write hook might raise an exception;
+ * the generated code will synchronize the CPU state before calling the hook
+ * so that it is safe for the hook to call raise_exception().
+ * NEWEL is for writes to registers that might change the exception
+ * level - typically on older ARM chips. For those cases we need to
+ * re-read the new el when recomputing the translation flags.
+ */
+#define ARM_CP_SPECIAL           0x0001
+#define ARM_CP_CONST             0x0002
+#define ARM_CP_64BIT             0x0004
+#define ARM_CP_SUPPRESS_TB_END   0x0008
+#define ARM_CP_OVERRIDE          0x0010
+#define ARM_CP_ALIAS             0x0020
+#define ARM_CP_IO                0x0040
+#define ARM_CP_NO_RAW            0x0080
+#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
+#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
+#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
+#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
+#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
+#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
+#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
+#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
+#define ARM_CP_FPU               0x1000
+#define ARM_CP_SVE               0x2000
+#define ARM_CP_NO_GDB            0x4000
+#define ARM_CP_RAISES_EXC        0x8000
+#define ARM_CP_NEWEL             0x10000
+/* Used only as a terminator for ARMCPRegInfo lists */
+#define ARM_CP_SENTINEL          0xfffff
+/* Mask of only the flag bits in a type field */
+#define ARM_CP_FLAG_MASK         0x1f0ff
+
+/*
+ * Valid values for ARMCPRegInfo state field, indicating which of
+ * the AArch32 and AArch64 execution states this register is visible in.
+ * If the reginfo doesn't explicitly specify then it is AArch32 only.
+ * If the reginfo is declared to be visible in both states then a second
+ * reginfo is synthesised for the AArch32 view of the AArch64 register,
+ * such that the AArch32 view is the lower 32 bits of the AArch64 one.
+ * Note that we rely on the values of these enums as we iterate through
+ * the various states in some places.
+ */
+enum {
+    ARM_CP_STATE_AA32 = 0,
+    ARM_CP_STATE_AA64 = 1,
+    ARM_CP_STATE_BOTH = 2,
+};
+
+/*
+ * ARM CP register secure state flags.  These flags identify security state
+ * attributes for a given CP register entry.
+ * The existence of both or neither secure and non-secure flags indicates that
+ * the register has both a secure and non-secure hash entry.  A single one of
+ * these flags causes the register to only be hashed for the specified
+ * security state.
+ * Although definitions may have any combination of the S/NS bits, each
+ * registered entry will only have one to identify whether the entry is secure
+ * or non-secure.
+ */
+enum {
+    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
+    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
+};
+
+/*
+ * Return true if cptype is a valid type field. This is used to try to
+ * catch errors where the sentinel has been accidentally left off the end
+ * of a list of registers.
+ */
+static inline bool cptype_valid(int cptype)
+{
+    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
+        || ((cptype & ARM_CP_SPECIAL) &&
+            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
+}
+
+/*
+ * Access rights:
+ * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
+ * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
+ * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
+ * (ie any of the privileged modes in Secure state, or Monitor mode).
+ * If a register is accessible in one privilege level it's always accessible
+ * in higher privilege levels too. Since "Secure PL1" also follows this rule
+ * (ie anything visible in PL2 is visible in S-PL1, some things are only
+ * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
+ * terminology a little and call this PL3.
+ * In AArch64 things are somewhat simpler as the PLx bits line up exactly
+ * with the ELx exception levels.
+ *
+ * If access permissions for a register are more complex than can be
+ * described with these bits, then use a laxer set of restrictions, and
+ * do the more restrictive/complex check inside a helper function.
+ */
+#define PL3_R 0x80
+#define PL3_W 0x40
+#define PL2_R (0x20 | PL3_R)
+#define PL2_W (0x10 | PL3_W)
+#define PL1_R (0x08 | PL2_R)
+#define PL1_W (0x04 | PL2_W)
+#define PL0_R (0x02 | PL1_R)
+#define PL0_W (0x01 | PL1_W)
+
+/*
+ * For user-mode some registers are accessible to EL0 via a kernel
+ * trap-and-emulate ABI. In this case we define the read permissions
+ * as actually being PL0_R. However some bits of any given register
+ * may still be masked.
+ */
+#ifdef CONFIG_USER_ONLY
+#define PL0U_R PL0_R
+#else
+#define PL0U_R PL1_R
+#endif
+
+#define PL3_RW (PL3_R | PL3_W)
+#define PL2_RW (PL2_R | PL2_W)
+#define PL1_RW (PL1_R | PL1_W)
+#define PL0_RW (PL0_R | PL0_W)
+
+typedef enum CPAccessResult {
+    /* Access is permitted */
+    CP_ACCESS_OK = 0,
+    /*
+     * Access fails due to a configurable trap or enable which would
+     * result in a categorized exception syndrome giving information about
+     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
+     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
+     * PL1 if in EL0, otherwise to the current EL).
+     */
+    CP_ACCESS_TRAP = 1,
+    /*
+     * Access fails and results in an exception syndrome 0x0 ("uncategorized").
+     * Note that this is not a catch-all case -- the set of cases which may
+     * result in this failure is specifically defined by the architecture.
+     */
+    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
+    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
+    CP_ACCESS_TRAP_EL2 = 3,
+    CP_ACCESS_TRAP_EL3 = 4,
+    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
+} CPAccessResult;
+
+typedef struct ARMCPRegInfo ARMCPRegInfo;
+
+/*
+ * Access functions for coprocessor registers. These cannot fail and
+ * may not raise exceptions.
+ */
+typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
+                       uint64_t value);
+/* Access permission check functions for coprocessor registers. */
+typedef CPAccessResult CPAccessFn(CPUARMState *env,
+                                  const ARMCPRegInfo *opaque,
+                                  bool isread);
+/* Hook function for register reset */
+typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+
+#define CP_ANY 0xff
+
+/* Definition of an ARM coprocessor register */
+struct ARMCPRegInfo {
+    /* Name of register (useful mainly for debugging, need not be unique) */
+    const char *name;
+    /*
+     * Location of register: coprocessor number and (crn,crm,opc1,opc2)
+     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
+     * 'wildcard' field -- any value of that field in the MRC/MCR insn
+     * will be decoded to this register. The register read and write
+     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
+     * used by the program, so it is possible to register a wildcard and
+     * then behave differently on read/write if necessary.
+     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
+     * must both be zero.
+     * For AArch64-visible registers, opc0 is also used.
+     * Since there are no "coprocessors" in AArch64, cp is purely used as a
+     * way to distinguish (for KVM's benefit) guest-visible system registers
+     * from demuxed ones provided to preserve the "no side effects on
+     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
+     * visible (to match KVM's encoding); cp==0 will be converted to
+     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
+     */
+    uint8_t cp;
+    uint8_t crn;
+    uint8_t crm;
+    uint8_t opc0;
+    uint8_t opc1;
+    uint8_t opc2;
+    /* Execution state in which this register is visible: ARM_CP_STATE_* */
+    int state;
+    /* Register type: ARM_CP_* bits/values */
+    int type;
+    /* Access rights: PL*_[RW] */
+    int access;
+    /* Security state: ARM_CP_SECSTATE_* bits/values */
+    int secure;
+    /*
+     * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
+     * this register was defined: can be used to hand data through to the
+     * register read/write functions, since they are passed the ARMCPRegInfo*.
+     */
+    void *opaque;
+    /*
+     * Value of this register, if it is ARM_CP_CONST. Otherwise, if
+     * fieldoffset is non-zero, the reset value of the register.
+     */
+    uint64_t resetvalue;
+    /*
+     * Offset of the field in CPUARMState for this register.
+     * This is not needed if either:
+     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
+     *  2. both readfn and writefn are specified
+     */
+    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
+
+    /*
+     * Offsets of the secure and non-secure fields in CPUARMState for the
+     * register if it is banked.  These fields are only used during the static
+     * registration of a register.  During hashing the bank associated
+     * with a given security state is copied to fieldoffset which is used from
+     * there on out.
+     *
+     * It is expected that register definitions use either fieldoffset or
+     * bank_fieldoffsets in the definition but not both.  It is also expected
+     * that both bank offsets are set when defining a banked register.  This
+     * use indicates that a register is banked.
+     */
+    ptrdiff_t bank_fieldoffsets[2];
+
+    /*
+     * Function for making any access checks for this register in addition to
+     * those specified by the 'access' permissions bits. If NULL, no extra
+     * checks required. The access check is performed at runtime, not at
+     * translate time.
+     */
+    CPAccessFn *accessfn;
+    /*
+     * Function for handling reads of this register. If NULL, then reads
+     * will be done by loading from the offset into CPUARMState specified
+     * by fieldoffset.
+     */
+    CPReadFn *readfn;
+    /*
+     * Function for handling writes of this register. If NULL, then writes
+     * will be done by writing to the offset into CPUARMState specified
+     * by fieldoffset.
+     */
+    CPWriteFn *writefn;
+    /*
+     * Function for doing a "raw" read; used when we need to copy
+     * coprocessor state to the kernel for KVM or out for
+     * migration. This only needs to be provided if there is also a
+     * readfn and it has side effects (for instance clear-on-read bits).
+     */
+    CPReadFn *raw_readfn;
+    /*
+     * Function for doing a "raw" write; used when we need to copy KVM
+     * kernel coprocessor state into userspace, or for inbound
+     * migration. This only needs to be provided if there is also a
+     * writefn and it masks out "unwritable" bits or has write-one-to-clear
+     * or similar behaviour.
+     */
+    CPWriteFn *raw_writefn;
+    /*
+     * Function for resetting the register. If NULL, then reset will be done
+     * by writing resetvalue to the field specified in fieldoffset. If
+     * fieldoffset is 0 then no reset will be done.
+     */
+    CPResetFn *resetfn;
+
+    /*
+     * "Original" writefn and readfn.
+     * For ARMv8.1-VHE register aliases, we overwrite the read/write
+     * accessor functions of various EL1/EL0 to perform the runtime
+     * check for which sysreg should actually be modified, and then
+     * forwards the operation.  Before overwriting the accessors,
+     * the original function is copied here, so that accesses that
+     * really do go to the EL1/EL0 version proceed normally.
+     * (The corresponding EL2 register is linked via opaque.)
+     */
+    CPReadFn *orig_readfn;
+    CPWriteFn *orig_writefn;
+};
+
+/*
+ * Macros which are lvalues for the field in CPUARMState for the
+ * ARMCPRegInfo *ri.
+ */
+#define CPREG_FIELD32(env, ri) \
+    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
+#define CPREG_FIELD64(env, ri) \
+    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
+
+#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
+
+void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
+                                    const ARMCPRegInfo *regs, void *opaque);
+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+                                       const ARMCPRegInfo *regs, void *opaque);
+static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
+{
+    define_arm_cp_regs_with_opaque(cpu, regs, 0);
+}
+static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
+{
+    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
+}
+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
+
+/*
+ * Definition of an ARM co-processor register as viewed from
+ * userspace. This is used for presenting sanitised versions of
+ * registers to userspace when emulating the Linux AArch64 CPU
+ * ID/feature ABI (advertised as HWCAP_CPUID).
+ */
+typedef struct ARMCPRegUserSpaceInfo {
+    /* Name of register */
+    const char *name;
+
+    /* Is the name actually a glob pattern */
+    bool is_glob;
+
+    /* Only some bits are exported to user space */
+    uint64_t exported_bits;
+
+    /* Fixed bits are applied after the mask */
+    uint64_t fixed_bits;
+} ARMCPRegUserSpaceInfo;
+
+#define REGUSERINFO_SENTINEL { .name = NULL }
+
+void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
+
+/* CPWriteFn that can be used to implement writes-ignored behaviour */
+void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
+                         uint64_t value);
+/* CPReadFn that can be used for read-as-zero behaviour */
+uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
+
+/*
+ * CPResetFn that does nothing, for use if no reset is required even
+ * if fieldoffset is non zero.
+ */
+void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
+
+/*
+ * Return true if this reginfo struct's field in the cpu state struct
+ * is 64 bits wide.
+ */
+static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
+{
+    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
+}
+
+static inline bool cp_access_ok(int current_el,
+                                const ARMCPRegInfo *ri, int isread)
+{
+    return (ri->access >> ((current_el * 2) + isread)) & 1;
+}
+
+/* Raw read of a coprocessor register (as needed for migration, etc) */
+uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
+
+#endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
     return kvmid;
 }
 
-/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
- * special-behaviour cp reg and bits [11..8] indicate what behaviour
- * it has. Otherwise it is a simple cp reg, where CONST indicates that
- * TCG can assume the value to be constant (ie load at translate time)
- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
- * indicates that the TB should not be ended after a write to this register
- * (the default is that the TB ends after cp writes). OVERRIDE permits
- * a register definition to override a previous definition for the
- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
- * old must have the OVERRIDE bit set.
- * ALIAS indicates that this register is an alias view of some underlying
- * state which is also visible via another register, and that the other
- * register is handling migration and reset; registers marked ALIAS will not be
- * migrated but may have their state set by syncing of register state from KVM.
- * NO_RAW indicates that this register has no underlying state and does not
- * support raw access for state saving/loading; it will not be used for either
- * migration or KVM state synchronization. (Typically this is for "registers"
- * which are actually used as instructions for cache maintenance and so on.)
- * IO indicates that this register does I/O and therefore its accesses
- * need to be marked with gen_io_start() and also end the TB. In particular,
- * registers which implement clocks or timers require this.
- * RAISES_EXC is for when the read or write hook might raise an exception;
- * the generated code will synchronize the CPU state before calling the hook
- * so that it is safe for the hook to call raise_exception().
- * NEWEL is for writes to registers that might change the exception
- * level - typically on older ARM chips. For those cases we need to
- * re-read the new el when recomputing the translation flags.
- */
-#define ARM_CP_SPECIAL           0x0001
-#define ARM_CP_CONST             0x0002
-#define ARM_CP_64BIT             0x0004
-#define ARM_CP_SUPPRESS_TB_END   0x0008
-#define ARM_CP_OVERRIDE          0x0010
-#define ARM_CP_ALIAS             0x0020
-#define ARM_CP_IO                0x0040
-#define ARM_CP_NO_RAW            0x0080
-#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
-#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
-#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
-#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
-#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
-#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
-#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
-#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
-#define ARM_CP_FPU               0x1000
-#define ARM_CP_SVE               0x2000
-#define ARM_CP_NO_GDB            0x4000
-#define ARM_CP_RAISES_EXC        0x8000
-#define ARM_CP_NEWEL             0x10000
-/* Used only as a terminator for ARMCPRegInfo lists */
-#define ARM_CP_SENTINEL          0xfffff
-/* Mask of only the flag bits in a type field */
-#define ARM_CP_FLAG_MASK         0x1f0ff
-
-/* Valid values for ARMCPRegInfo state field, indicating which of
- * the AArch32 and AArch64 execution states this register is visible in.
- * If the reginfo doesn't explicitly specify then it is AArch32 only.
- * If the reginfo is declared to be visible in both states then a second
- * reginfo is synthesised for the AArch32 view of the AArch64 register,
- * such that the AArch32 view is the lower 32 bits of the AArch64 one.
- * Note that we rely on the values of these enums as we iterate through
- * the various states in some places.
- */
-enum {
-    ARM_CP_STATE_AA32 = 0,
-    ARM_CP_STATE_AA64 = 1,
-    ARM_CP_STATE_BOTH = 2,
-};
-
-/* ARM CP register secure state flags.  These flags identify security state
- * attributes for a given CP register entry.
- * The existence of both or neither secure and non-secure flags indicates that
- * the register has both a secure and non-secure hash entry.  A single one of
- * these flags causes the register to only be hashed for the specified
- * security state.
- * Although definitions may have any combination of the S/NS bits, each
- * registered entry will only have one to identify whether the entry is secure
- * or non-secure.
- */
-enum {
-    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
-    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
-};
-
-/* Return true if cptype is a valid type field. This is used to try to
- * catch errors where the sentinel has been accidentally left off the end
- * of a list of registers.
- */
-static inline bool cptype_valid(int cptype)
-{
-    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
-        || ((cptype & ARM_CP_SPECIAL) &&
-            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
-}
-
-/* Access rights:
- * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
- * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
- * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
- * (ie any of the privileged modes in Secure state, or Monitor mode).
- * If a register is accessible in one privilege level it's always accessible
- * in higher privilege levels too. Since "Secure PL1" also follows this rule
- * (ie anything visible in PL2 is visible in S-PL1, some things are only
- * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
- * terminology a little and call this PL3.
- * In AArch64 things are somewhat simpler as the PLx bits line up exactly
- * with the ELx exception levels.
- *
- * If access permissions for a register are more complex than can be
- * described with these bits, then use a laxer set of restrictions, and
- * do the more restrictive/complex check inside a helper function.
- */
-#define PL3_R 0x80
-#define PL3_W 0x40
-#define PL2_R (0x20 | PL3_R)
-#define PL2_W (0x10 | PL3_W)
-#define PL1_R (0x08 | PL2_R)
-#define PL1_W (0x04 | PL2_W)
-#define PL0_R (0x02 | PL1_R)
-#define PL0_W (0x01 | PL1_W)
-
-/*
- * For user-mode some registers are accessible to EL0 via a kernel
- * trap-and-emulate ABI. In this case we define the read permissions
- * as actually being PL0_R. However some bits of any given register
- * may still be masked.
- */
-#ifdef CONFIG_USER_ONLY
-#define PL0U_R PL0_R
-#else
-#define PL0U_R PL1_R
-#endif
-
-#define PL3_RW (PL3_R | PL3_W)
-#define PL2_RW (PL2_R | PL2_W)
-#define PL1_RW (PL1_R | PL1_W)
-#define PL0_RW (PL0_R | PL0_W)
-
 /* Return the highest implemented Exception Level */
 static inline int arm_highest_el(CPUARMState *env)
 {
@@ -XXX,XX +XXX,XX @@ static inline int arm_current_el(CPUARMState *env)
     }
 }
 
-typedef struct ARMCPRegInfo ARMCPRegInfo;
-
-typedef enum CPAccessResult {
-    /* Access is permitted */
-    CP_ACCESS_OK = 0,
-    /* Access fails due to a configurable trap or enable which would
-     * result in a categorized exception syndrome giving information about
-     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
-     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
-     * PL1 if in EL0, otherwise to the current EL).
-     */
-    CP_ACCESS_TRAP = 1,
-    /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
-     * Note that this is not a catch-all case -- the set of cases which may
-     * result in this failure is specifically defined by the architecture.
-     */
-    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
-    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_EL2 = 3,
-    CP_ACCESS_TRAP_EL3 = 4,
-    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
-} CPAccessResult;
-
-/* Access functions for coprocessor registers. These cannot fail and
- * may not raise exceptions.
- */
-typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
-                       uint64_t value);
-/* Access permission check functions for coprocessor registers. */
-typedef CPAccessResult CPAccessFn(CPUARMState *env,
-                                  const ARMCPRegInfo *opaque,
-                                  bool isread);
-/* Hook function for register reset */
-typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-
-#define CP_ANY 0xff
-
-/* Definition of an ARM coprocessor register */
-struct ARMCPRegInfo {
-    /* Name of register (useful mainly for debugging, need not be unique) */
-    const char *name;
-    /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
-     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
-     * 'wildcard' field -- any value of that field in the MRC/MCR insn
-     * will be decoded to this register. The register read and write
-     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
-     * used by the program, so it is possible to register a wildcard and
-     * then behave differently on read/write if necessary.
-     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
-     * must both be zero.
-     * For AArch64-visible registers, opc0 is also used.
-     * Since there are no "coprocessors" in AArch64, cp is purely used as a
-     * way to distinguish (for KVM's benefit) guest-visible system registers
-     * from demuxed ones provided to preserve the "no side effects on
-     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
-     * visible (to match KVM's encoding); cp==0 will be converted to
-     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
-     */
-    uint8_t cp;
-    uint8_t crn;
-    uint8_t crm;
-    uint8_t opc0;
-    uint8_t opc1;
-    uint8_t opc2;
-    /* Execution state in which this register is visible: ARM_CP_STATE_* */
-    int state;
-    /* Register type: ARM_CP_* bits/values */
-    int type;
-    /* Access rights: PL*_[RW] */
-    int access;
-    /* Security state: ARM_CP_SECSTATE_* bits/values */
-    int secure;
-    /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
-     * this register was defined: can be used to hand data through to the
-     * register read/write functions, since they are passed the ARMCPRegInfo*.
-     */
-    void *opaque;
-    /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
-     * fieldoffset is non-zero, the reset value of the register.
-     */
-    uint64_t resetvalue;
-    /* Offset of the field in CPUARMState for this register.
-     *
-     * This is not needed if either:
-     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
-     *  2. both readfn and writefn are specified
-     */
-    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
-
-    /* Offsets of the secure and non-secure fields in CPUARMState for the
-     * register if it is banked.  These fields are only used during the static
-     * registration of a register.  During hashing the bank associated
-     * with a given security state is copied to fieldoffset which is used from
-     * there on out.
-     *
-     * It is expected that register definitions use either fieldoffset or
-     * bank_fieldoffsets in the definition but not both.  It is also expected
-     * that both bank offsets are set when defining a banked register.  This
-     * use indicates that a register is banked.
-     */
-    ptrdiff_t bank_fieldoffsets[2];
-
-    /* Function for making any access checks for this register in addition to
-     * those specified by the 'access' permissions bits. If NULL, no extra
-     * checks required. The access check is performed at runtime, not at
-     * translate time.
-     */
-    CPAccessFn *accessfn;
-    /* Function for handling reads of this register. If NULL, then reads
-     * will be done by loading from the offset into CPUARMState specified
-     * by fieldoffset.
-     */
-    CPReadFn *readfn;
-    /* Function for handling writes of this register. If NULL, then writes
-     * will be done by writing to the offset into CPUARMState specified
-     * by fieldoffset.
-     */
-    CPWriteFn *writefn;
-    /* Function for doing a "raw" read; used when we need to copy
-     * coprocessor state to the kernel for KVM or out for
-     * migration. This only needs to be provided if there is also a
-     * readfn and it has side effects (for instance clear-on-read bits).
-     */
-    CPReadFn *raw_readfn;
-    /* Function for doing a "raw" write; used when we need to copy KVM
-     * kernel coprocessor state into userspace, or for inbound
-     * migration. This only needs to be provided if there is also a
-     * writefn and it masks out "unwritable" bits or has write-one-to-clear
-     * or similar behaviour.
-     */
-    CPWriteFn *raw_writefn;
-    /* Function for resetting the register. If NULL, then reset will be done
-     * by writing resetvalue to the field specified in fieldoffset. If
-     * fieldoffset is 0 then no reset will be done.
-     */
-    CPResetFn *resetfn;
-
-    /*
-     * "Original" writefn and readfn.
-     * For ARMv8.1-VHE register aliases, we overwrite the read/write
-     * accessor functions of various EL1/EL0 to perform the runtime
-     * check for which sysreg should actually be modified, and then
-     * forwards the operation.  Before overwriting the accessors,
-     * the original function is copied here, so that accesses that
-     * really do go to the EL1/EL0 version proceed normally.
-     * (The corresponding EL2 register is linked via opaque.)
-     */
-    CPReadFn *orig_readfn;
-    CPWriteFn *orig_writefn;
-};
-
-/* Macros which are lvalues for the field in CPUARMState for the
- * ARMCPRegInfo *ri.
- */
-#define CPREG_FIELD32(env, ri) \
-    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
-#define CPREG_FIELD64(env, ri) \
-    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
-
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
-
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque);
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                       const ARMCPRegInfo *regs, void *opaque);
-static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_arm_cp_regs_with_opaque(cpu, regs, 0);
-}
-static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
-}
-const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
-
-/*
- * Definition of an ARM co-processor register as viewed from
- * userspace. This is used for presenting sanitised versions of
- * registers to userspace when emulating the Linux AArch64 CPU
- * ID/feature ABI (advertised as HWCAP_CPUID).
- */
-typedef struct ARMCPRegUserSpaceInfo {
-    /* Name of register */
-    const char *name;
-
-    /* Is the name actually a glob pattern */
-    bool is_glob;
-
-    /* Only some bits are exported to user space */
-    uint64_t exported_bits;
-
-    /* Fixed bits are applied after the mask */
-    uint64_t fixed_bits;
-} ARMCPRegUserSpaceInfo;
-
-#define REGUSERINFO_SENTINEL { .name = NULL }
-
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
-
-/* CPWriteFn that can be used to implement writes-ignored behaviour */
-void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-                         uint64_t value);
-/* CPReadFn that can be used for read-as-zero behaviour */
-uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
-
-/* CPResetFn that does nothing, for use if no reset is required even
- * if fieldoffset is non zero.
- */
-void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
-
-/* Return true if this reginfo struct's field in the cpu state struct
- * is 64 bits wide.
- */
-static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
-{
-    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
-}
-
-static inline bool cp_access_ok(int current_el,
-                                const ARMCPRegInfo *ri, int isread)
-{
-    return (ri->access >> ((current_el * 2) + isread)) & 1;
-}
-
-/* Raw read of a coprocessor register (as needed for migration, etc) */
-uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
-
 /**
  * write_list_to_cpustate
  * @cpu: ARMCPU
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/cutils.h"
 #include "qemu/log.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
 
 static struct {
     hwaddr io_base;
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
 
 #define ICIP	0x00	/* Interrupt Controller IRQ Pending register */
 #define ICMR	0x04	/* Interrupt Controller Mask register */
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@
 #include "gicv3_internal.h"
 #include "hw/irq.h"
 #include "cpu.h"
+#include "target/arm/cpregs.h"
 
 /*
  * Special case return value from hppvi_index(); must be larger than
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "vgic_common.h"
 #include "migration/blocker.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
+
 
 #ifdef DEBUG_GICV3_KVM
 #define DPRINTF(fmt, ...) \
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "kvm_arm.h"
 #include "disas/capstone.h"
 #include "fpu/softfloat.h"
+#include "cpregs.h"
 
 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
 {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "hvf_arm.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
+#include "cpregs.h"
 
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/boards.h"
 #endif
+#include "cpregs.h"
 
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@
  */
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "internals.h"
 #include "exec/gdbstub.h"
+#include "internals.h"
+#include "cpregs.h"
 
 typedef struct RegisterSysregXmlParam {
     CPUState *cs;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
+#include "cpregs.h"
 
 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
 #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "internals.h"
 #include "exec/exec-all.h"
 #include "exec/cpu_ldst.h"
+#include "cpregs.h"
 
 #define SIGNBIT (uint32_t)0x80000000
 #define SIGNBIT64 ((uint64_t)1 << 63)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@
 #include "translate.h"
 #include "internals.h"
 #include "qemu/host-utils.h"
-
 #include "semihosting/semihost.h"
 #include "exec/gen-icount.h"
-
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
 #include "exec/log.h"
-
+#include "cpregs.h"
 #include "translate-a64.h"
 #include "qemu/atomic128.h"
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bitops.h"
 #include "arm_ldst.h"
 #include "semihosting/semihost.h"
-
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
-
 #include "exec/log.h"
+#include "cpregs.h"
 
 
 #define ENABLE_ARCH_4T    arm_dc_feature(s, ARM_FEATURE_V4T)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Rearrange the values of the enumerators of CPAccessResult
so that we may directly extract the target el. For the two
special cases in access_check_cp_reg, use CPAccessResult.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ static inline bool cptype_valid(int cptype)
 typedef enum CPAccessResult {
     /* Access is permitted */
     CP_ACCESS_OK = 0,
+
+    /*
+     * Combined with one of the following, the low 2 bits indicate the
+     * target exception level.  If 0, the exception is taken to the usual
+     * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
+     */
+    CP_ACCESS_EL_MASK = 3,
+
     /*
      * Access fails due to a configurable trap or enable which would
      * result in a categorized exception syndrome giving information about
      * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
-     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
-     * PL1 if in EL0, otherwise to the current EL).
+     * 0xc or 0x18).
      */
-    CP_ACCESS_TRAP = 1,
+    CP_ACCESS_TRAP = (1 << 2),
+    CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
+    CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
+
     /*
      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
      * Note that this is not a catch-all case -- the set of cases which may
      * result in this failure is specifically defined by the architecture.
      */
-    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
-    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_EL2 = 3,
-    CP_ACCESS_TRAP_EL3 = 4,
-    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
+    CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
 } CPAccessResult;
 
 typedef struct ARMCPRegInfo ARMCPRegInfo;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
                                  uint32_t isread)
 {
     const ARMCPRegInfo *ri = rip;
+    CPAccessResult res = CP_ACCESS_OK;
     int target_el;
 
     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
-        raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
+        res = CP_ACCESS_TRAP;
+        goto fail;
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
         mask &= ~((1 << 4) | (1 << 14));
 
         if (env->cp15.hstr_el2 & mask) {
-            target_el = 2;
-            goto exept;
+            res = CP_ACCESS_TRAP_EL2;
+            goto fail;
         }
     }
 
-    if (!ri->accessfn) {
+    if (ri->accessfn) {
+        res = ri->accessfn(env, ri, isread);
+    }
+    if (likely(res == CP_ACCESS_OK)) {
         return;
     }
 
-    switch (ri->accessfn(env, ri, isread)) {
-    case CP_ACCESS_OK:
-        return;
+ fail:
+    switch (res & ~CP_ACCESS_EL_MASK) {
     case CP_ACCESS_TRAP:
-        target_el = exception_target_el(env);
-        break;
-    case CP_ACCESS_TRAP_EL2:
-        /* Requesting a trap to EL2 when we're in EL3 is
-         * a bug in the access function.
-         */
-        assert(arm_current_el(env) != 3);
-        target_el = 2;
-        break;
-    case CP_ACCESS_TRAP_EL3:
-        target_el = 3;
         break;
     case CP_ACCESS_TRAP_UNCATEGORIZED:
-        target_el = exception_target_el(env);
-        syndrome = syn_uncategorized();
-        break;
-    case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
-        target_el = 2;
-        syndrome = syn_uncategorized();
-        break;
-    case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
-        target_el = 3;
         syndrome = syn_uncategorized();
         break;
     default:
         g_assert_not_reached();
     }
 
-exept:
+    target_el = res & CP_ACCESS_EL_MASK;
+    switch (target_el) {
+    case 0:
+        target_el = exception_target_el(env);
+        break;
+    case 2:
+        assert(arm_current_el(env) != 3);
+        assert(arm_is_el2_enabled(env));
+        break;
+    case 3:
+        assert(arm_feature(env, ARM_FEATURE_EL3));
+        break;
+    default:
+        /* No "direct" traps to EL1 */
+        g_assert_not_reached();
+    }
+
     raise_exception(env, EXCP_UDEF, syndrome, target_el);
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Remove a possible source of error by removing REGINFO_SENTINEL
and using ARRAY_SIZE (convinently hidden inside a macro) to
find the end of the set of regs being registered or modified.

The space saved by not having the extra array element reduces
the executable's .data.rel.ro section by about 9k.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h       |  53 +++++++++---------
 hw/arm/pxa2xx.c           |   1 -
 hw/arm/pxa2xx_pic.c       |   1 -
 hw/intc/arm_gicv3_cpuif.c |   5 --
 hw/intc/arm_gicv3_kvm.c   |   1 -
 target/arm/cpu64.c        |   1 -
 target/arm/cpu_tcg.c      |   4 --
 target/arm/helper.c       | 111 ++++++++------------------------------
 8 files changed, 48 insertions(+), 129 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
 #define ARM_CP_NO_GDB            0x4000
 #define ARM_CP_RAISES_EXC        0x8000
 #define ARM_CP_NEWEL             0x10000
-/* Used only as a terminator for ARMCPRegInfo lists */
-#define ARM_CP_SENTINEL          0xfffff
 /* Mask of only the flag bits in a type field */
 #define ARM_CP_FLAG_MASK         0x1f0ff
 
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
 };
 
-/*
- * Return true if cptype is a valid type field. This is used to try to
- * catch errors where the sentinel has been accidentally left off the end
- * of a list of registers.
- */
-static inline bool cptype_valid(int cptype)
-{
-    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
-        || ((cptype & ARM_CP_SPECIAL) &&
-            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
-}
-
 /*
  * Access rights:
  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
 #define CPREG_FIELD64(env, ri) \
     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
+                                       void *opaque);
 
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque);
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                       const ARMCPRegInfo *regs, void *opaque);
-static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_arm_cp_regs_with_opaque(cpu, regs, 0);
-}
 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 {
-    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
+    define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
 }
+
+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+                                        void *opaque, size_t len);
+
+#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE)               \
+    do {                                                                \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
+        define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE,           \
+                                           ARRAY_SIZE(REGS));           \
+    } while (0)
+
+#define define_arm_cp_regs(CPU, REGS) \
+    define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
+
 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
 
 /*
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCPRegUserSpaceInfo {
     uint64_t fixed_bits;
 } ARMCPRegUserSpaceInfo;
 
-#define REGUSERINFO_SENTINEL { .name = NULL }
+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+                                 const ARMCPRegUserSpaceInfo *mods,
+                                 size_t mods_len);
 
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
+#define modify_arm_cp_regs(REGS, MODS)                                  \
+    do {                                                                \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0);                       \
+        modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS),             \
+                                    MODS, ARRAY_SIZE(MODS));            \
+    } while (0)
 
 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
     { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .type = ARM_CP_IO,
       .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
-    REGINFO_SENTINEL
 };
 
 static void pxa2xx_setup_cp14(PXA2xxState *s)
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
     REGINFO_FOR_PIC_CP("ICLR2", 8),
     REGINFO_FOR_PIC_CP("ICFP2", 9),
     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
-    REGINFO_SENTINEL
 };
 
 static const MemoryRegionOps pxa2xx_pic_ops = {
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
       .readfn = icc_igrpen1_el3_read,
       .writefn = icc_igrpen1_el3_write,
     },
-    REGINFO_SENTINEL
 };
 
 static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = {
       .readfn = ich_vmcr_read,
       .writefn = ich_vmcr_write,
     },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
       .readfn = ich_ap_read,
       .writefn = ich_ap_write,
     },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
       .readfn = ich_ap_read,
       .writefn = ich_ap_write,
     },
-    REGINFO_SENTINEL
 };
 
 static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
                       .readfn = ich_lr_read,
                       .writefn = ich_lr_write,
                     },
-                    REGINFO_SENTINEL
                 };
                 define_arm_cp_regs(cpu, lr_regset);
             }
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
        */
       .resetfn = arm_gicv3_icc_reset,
     },
-    REGINFO_SENTINEL
 };
 
 /**
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
     { .name = "L2MERRSR",
       .cp = 15, .opc1 = 3, .crm = 15,
       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void aarch64_a57_initfn(Object *obj)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a8_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a9_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 #endif
     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a7_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST },
     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static void cortex_r5_initfn(Object *obj)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
       .secure = ARM_CP_SECSTATE_S,
       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
      */
     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
       .access = PL1_W, .type = ARM_CP_WFI },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
       .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
-    REGINFO_SENTINEL
 };
 
 typedef struct pm_event {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
       .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
       .writefn = tlbimvaa_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
       .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
       .writefn = tlbimvaa_is_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsset_write,
       .raw_writefn = raw_write },
-    REGINFO_SENTINEL
 };
 
 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
       .accessfn = teehbr_access, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo v6k_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
     },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .readfn = gt_virt_cnt_read,
     },
-    REGINFO_SENTINEL
 };
 
 #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
       .access = PL1_W, .accessfn = ats_access,
       .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
 #endif
-    REGINFO_SENTINEL
 };
 
 /* Return basic MPU access permission bits.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
       .writefn = pmsav7_rgnr_write,
       .resetfn = arm_cp_reset_ignore },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
-    REGINFO_SENTINEL
 };
 
 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_tvm_trvm,
       .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
       .resetvalue = 0, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
       /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
                              offsetof(CPUARMState, cp15.tcr_el[1])} },
-    REGINFO_SENTINEL
 };
 
 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
     { .name = "C9", .cp = 15, .crn = 9,
       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
     { .name = "XSCALE_UNLOCK_DCACHE",
       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
       .access = PL1_RW,
       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
       .resetvalue = (1 << 30) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
       .access = PL1_RW, .resetvalue = 0,
       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
-    REGINFO_SENTINEL
 };
 
 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                              offsetof(CPUARMState, cp15.ttbr1_ns) },
       .writefn = vmsa_ttbr_write, },
-    REGINFO_SENTINEL
 };
 
 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
       .writefn = sdcr_write,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
-    REGINFO_SENTINEL
 };
 
 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .type = ARM_CP_CONST,
       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
       .access = PL2_RW, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 /* Ditto, but for registers which exist in ARMv8 but not v7 */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
       .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
       .access = PL2_RW,
       .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
       .access = PL2_RW,
       .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
       .access = PL2_RW,
       .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
       .writefn = hcr_writehigh },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
       .access = PL2_RW, .accessfn = sel2_access,
       .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae3_write },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tda,
       .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 /* Return the exception level to which exceptions should be taken
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
               .writefn = dbgbcr_write, .raw_writefn = raw_write
             },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, dbgregs);
     }
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
               .writefn = dbgwcr_write, .raw_writefn = raw_write
             },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, dbgregs);
     }
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .type = ARM_CP_IO,
               .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
               .raw_writefn = pmevtyper_rawwrite },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, pmev_regs);
         g_free(pmevcntr_name);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
               .resetvalue = extract64(cpu->pmceid1, 32, 32) },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, v81_pmu_regs);
     }
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
       .access = PL1_R, .accessfn = access_lor_ns,
       .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 #ifdef TARGET_AARCH64
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_pauth,
       .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo tlbirange_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae3_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo tlbios_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae3is_write },
-    REGINFO_SENTINEL
 };
 
 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rndr_reginfo[] = {
       .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
       .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
       .access = PL0_R, .readfn = rndr_readfn },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo dcpodp_reg[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
-    REGINFO_SENTINEL
 };
 #endif /*CONFIG_USER_ONLY*/
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
     { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
     { .name = "TCO", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
       .type = ARM_CP_CONST, .access = PL0_RW, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
       .accessfn = aa64_zva_access,
 #endif
     },
-    REGINFO_SENTINEL
 };
 
 #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
     { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-    REGINFO_SENTINEL
 };
 
 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
       .access = PL1_R,
       .accessfn = access_aa64_tid2,
       .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
       .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
       .accessfn = access_joscr_jmcr,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo vhe_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
       .access = PL2_RW, .accessfn = e2h_access,
       .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
 #endif
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write64 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo ats1cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write },
-    REGINFO_SENTINEL
 };
 #endif
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
       .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
       .access = PL2_RW, .type = ARM_CP_CONST,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 void register_cp_regs_for_features(ARMCPU *cpu)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa32_tid3,
               .resetvalue = cpu->isar.id_isar6 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, v6_idregs);
         define_arm_cp_regs(cpu, v6_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
               .resetvalue = cpu->pmceid1 },
-            REGINFO_SENTINEL
         };
 #ifdef CONFIG_USER_ONLY
         ARMCPRegUserSpaceInfo v8_user_idregs[] = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .exported_bits = 0x000000f0ffffffff },
             { .name = "ID_AA64ISAR*_EL1_RESERVED",
               .is_glob = true                     },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(v8_idregs, v8_user_idregs);
 #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL2_RW,
               .resetvalue = vmpidr_def,
               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, vpidr_regs);
         define_arm_cp_regs(cpu, el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                   .access = PL2_RW, .accessfn = access_el3_aa32ns,
                   .type = ARM_CP_NO_RAW,
                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
-                REGINFO_SENTINEL
             };
             define_arm_cp_regs(cpu, vpidr_regs);
             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .raw_writefn = raw_write, .writefn = sctlr_write,
               .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
               .resetvalue = cpu->reset_sctlr },
-            REGINFO_SENTINEL
         };
 
         define_arm_cp_regs(cpu, el3_regs);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "DUMMY",
               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R,
               .accessfn = access_aa64_tid1,
               .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
-            REGINFO_SENTINEL
         };
         ARMCPRegInfo id_cp_reginfo[] = {
             /* These are common to v8 and pre-v8 */
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R,
               .accessfn = access_aa32_tid1,
               .type = ARM_CP_CONST, .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         /* TLBTR is specific to VMSA */
         ARMCPRegInfo id_tlbtr_reginfo = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "MIDR_EL1",
               .exported_bits = 0x00000000ffffffff },
             { .name = "REVIDR_EL1"                },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
 #endif
         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
             arm_feature(env, ARM_FEATURE_STRONGARM)) {
-            ARMCPRegInfo *r;
+            size_t i;
             /* Register the blanket "writes ignored" value first to cover the
              * whole space. Then update the specific ID registers to allow write
              * access, so that they ignore writes rather than causing them to
              * UNDEF.
              */
             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
-            for (r = id_pre_v8_midr_cp_reginfo;
-                 r->type != ARM_CP_SENTINEL; r++) {
-                r->access = PL1_RW;
+            for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) {
+                id_pre_v8_midr_cp_reginfo[i].access = PL1_RW;
             }
-            for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
-                r->access = PL1_RW;
+            for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) {
+                id_cp_reginfo[i].access = PL1_RW;
             }
             id_mpuir_reginfo.access = PL1_RW;
             id_tlbtr_reginfo.access = PL1_RW;
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
-            REGINFO_SENTINEL
         };
 #ifdef CONFIG_USER_ONLY
         ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
             { .name = "MPIDR_EL1",
               .fixed_bits = 0x0000000080000000 },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
 #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
               .access = PL3_RW, .type = ARM_CP_CONST,
               .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, auxcr_reginfo);
         if (cpu_isar_feature(aa32_ac2, cpu)) {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                   .type = ARM_CP_CONST,
                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
-                REGINFO_SENTINEL
             };
             /* We don't implement a r/w 64 bit CBAR currently */
             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                      offsetof(CPUARMState, cp15.vbar_ns) },
               .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, vbar_cp_reginfo);
     }
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                    r->writefn);
         }
     }
-    /* Bad type field probably means missing sentinel at end of reg list */
-    assert(cptype_valid(r->type));
+
     for (crm = crmmin; crm <= crmmax; crm++) {
         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
     }
 }
 
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque)
+/* Define a whole list of registers */
+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+                                        void *opaque, size_t len)
 {
-    /* Define a whole list of registers */
-    const ARMCPRegInfo *r;
-    for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
-        define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
+    size_t i;
+    for (i = 0; i < len; ++i) {
+        define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
  * user-space cannot alter any values and dynamic values pertaining to
  * execution state are hidden from user space view anyway.
  */
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+                                 const ARMCPRegUserSpaceInfo *mods,
+                                 size_t mods_len)
 {
-    const ARMCPRegUserSpaceInfo *m;
-    ARMCPRegInfo *r;
-
-    for (m = mods; m->name; m++) {
+    for (size_t mi = 0; mi < mods_len; ++mi) {
+        const ARMCPRegUserSpaceInfo *m = mods + mi;
         GPatternSpec *pat = NULL;
+
         if (m->is_glob) {
             pat = g_pattern_spec_new(m->name);
         }
-        for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
+        for (size_t ri = 0; ri < regs_len; ++ri) {
+            ARMCPRegInfo *r = regs + ri;
+
             if (pat && g_pattern_match_string(pat, r->name)) {
                 r->type = ARM_CP_CONST;
                 r->access = PL0U_R;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These particular data structures are not modified at runtime.

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .resetvalue = cpu->pmceid1 },
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+        static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
             { .name = "ID_AA64PFR0_EL1",
               .exported_bits = 0x000f000f00ff0000,
               .fixed_bits    = 0x0000000000000011 },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      */
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR", .type = ARM_CP_CONST,
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL1_RW, .accessfn = nsacr_access,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             };
             define_one_arm_cp_reg(cpu, &nsacr);
         } else {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR",
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL3_RW | PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
     } else {
         if (arm_feature(env, ARM_FEATURE_V8)) {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR", .type = ARM_CP_CONST,
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = cpu->pmsav7_dregion << 8
         };
-        ARMCPRegInfo crn0_wi_reginfo = {
+        static const ARMCPRegInfo crn0_wi_reginfo = {
             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
+        static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1",
               .exported_bits = 0x00000000ffffffff },
             { .name = "REVIDR_EL1"                },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
+        static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
             { .name = "MPIDR_EL1",
               .fixed_bits = 0x0000000080000000 },
         };
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (arm_feature(env, ARM_FEATURE_VBAR)) {
-        ARMCPRegInfo vbar_cp_reginfo[] = {
+        static const ARMCPRegInfo vbar_cp_reginfo[] = {
             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
               .access = PL1_RW, .writefn = vbar_write,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Instead of defining ARM_CP_FLAG_MASK to remove flags,
define ARM_CP_SPECIAL_MASK to isolate special cases.
Sort the specials to the low bits. Use an enum.

Split the large comment block so as to document each
value separately.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h        | 130 +++++++++++++++++++++++--------------
 target/arm/cpu.c           |   4 +-
 target/arm/helper.c        |   4 +-
 target/arm/translate-a64.c |   6 +-
 target/arm/translate.c     |   6 +-
 5 files changed, 92 insertions(+), 58 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
 #define TARGET_ARM_CPREGS_H
 
 /*
- * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
- * special-behaviour cp reg and bits [11..8] indicate what behaviour
- * it has. Otherwise it is a simple cp reg, where CONST indicates that
- * TCG can assume the value to be constant (ie load at translate time)
- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
- * indicates that the TB should not be ended after a write to this register
- * (the default is that the TB ends after cp writes). OVERRIDE permits
- * a register definition to override a previous definition for the
- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
- * old must have the OVERRIDE bit set.
- * ALIAS indicates that this register is an alias view of some underlying
- * state which is also visible via another register, and that the other
- * register is handling migration and reset; registers marked ALIAS will not be
- * migrated but may have their state set by syncing of register state from KVM.
- * NO_RAW indicates that this register has no underlying state and does not
- * support raw access for state saving/loading; it will not be used for either
- * migration or KVM state synchronization. (Typically this is for "registers"
- * which are actually used as instructions for cache maintenance and so on.)
- * IO indicates that this register does I/O and therefore its accesses
- * need to be marked with gen_io_start() and also end the TB. In particular,
- * registers which implement clocks or timers require this.
- * RAISES_EXC is for when the read or write hook might raise an exception;
- * the generated code will synchronize the CPU state before calling the hook
- * so that it is safe for the hook to call raise_exception().
- * NEWEL is for writes to registers that might change the exception
- * level - typically on older ARM chips. For those cases we need to
- * re-read the new el when recomputing the translation flags.
+ * ARMCPRegInfo type field bits:
  */
-#define ARM_CP_SPECIAL           0x0001
-#define ARM_CP_CONST             0x0002
-#define ARM_CP_64BIT             0x0004
-#define ARM_CP_SUPPRESS_TB_END   0x0008
-#define ARM_CP_OVERRIDE          0x0010
-#define ARM_CP_ALIAS             0x0020
-#define ARM_CP_IO                0x0040
-#define ARM_CP_NO_RAW            0x0080
-#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
-#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
-#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
-#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
-#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
-#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
-#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
-#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
-#define ARM_CP_FPU               0x1000
-#define ARM_CP_SVE               0x2000
-#define ARM_CP_NO_GDB            0x4000
-#define ARM_CP_RAISES_EXC        0x8000
-#define ARM_CP_NEWEL             0x10000
-/* Mask of only the flag bits in a type field */
-#define ARM_CP_FLAG_MASK         0x1f0ff
+enum {
+    /*
+     * Register must be handled specially during translation.
+     * The method is one of the values below:
+     */
+    ARM_CP_SPECIAL_MASK          = 0x000f,
+    /* Special: no change to PE state: writes ignored, reads ignored. */
+    ARM_CP_NOP                   = 0x0001,
+    /* Special: sysreg is WFI, for v5 and v6. */
+    ARM_CP_WFI                   = 0x0002,
+    /* Special: sysreg is NZCV. */
+    ARM_CP_NZCV                  = 0x0003,
+    /* Special: sysreg is CURRENTEL. */
+    ARM_CP_CURRENTEL             = 0x0004,
+    /* Special: sysreg is DC ZVA or similar. */
+    ARM_CP_DC_ZVA                = 0x0005,
+    ARM_CP_DC_GVA                = 0x0006,
+    ARM_CP_DC_GZVA               = 0x0007,
+
+    /* Flag: reads produce resetvalue; writes ignored. */
+    ARM_CP_CONST                 = 1 << 4,
+    /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
+    ARM_CP_64BIT                 = 1 << 5,
+    /*
+     * Flag: TB should not be ended after a write to this register
+     * (the default is that the TB ends after cp writes).
+     */
+    ARM_CP_SUPPRESS_TB_END       = 1 << 6,
+    /*
+     * Flag: Permit a register definition to override a previous definition
+     * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new
+     * or the old must have the ARM_CP_OVERRIDE bit set.
+     */
+    ARM_CP_OVERRIDE              = 1 << 7,
+    /*
+     * Flag: Register is an alias view of some underlying state which is also
+     * visible via another register, and that the other register is handling
+     * migration and reset; registers marked ARM_CP_ALIAS will not be migrated
+     * but may have their state set by syncing of register state from KVM.
+     */
+    ARM_CP_ALIAS                 = 1 << 8,
+    /*
+     * Flag: Register does I/O and therefore its accesses need to be marked
+     * with gen_io_start() and also end the TB. In particular, registers which
+     * implement clocks or timers require this.
+     */
+    ARM_CP_IO                    = 1 << 9,
+    /*
+     * Flag: Register has no underlying state and does not support raw access
+     * for state saving/loading; it will not be used for either migration or
+     * KVM state synchronization. Typically this is for "registers" which are
+     * actually used as instructions for cache maintenance and so on.
+     */
+    ARM_CP_NO_RAW                = 1 << 10,
+    /*
+     * Flag: The read or write hook might raise an exception; the generated
+     * code will synchronize the CPU state before calling the hook so that it
+     * is safe for the hook to call raise_exception().
+     */
+    ARM_CP_RAISES_EXC            = 1 << 11,
+    /*
+     * Flag: Writes to the sysreg might change the exception level - typically
+     * on older ARM chips. For those cases we need to re-read the new el when
+     * recomputing the translation flags.
+     */
+    ARM_CP_NEWEL                 = 1 << 12,
+    /*
+     * Flag: Access check for this sysreg is identical to accessing FPU state
+     * from an instruction: use translation fp_access_check().
+     */
+    ARM_CP_FPU                   = 1 << 13,
+    /*
+     * Flag: Access check for this sysreg is identical to accessing SVE state
+     * from an instruction: use translation sve_access_check().
+     */
+    ARM_CP_SVE                   = 1 << 14,
+    /* Flag: Do not expose in gdb sysreg xml. */
+    ARM_CP_NO_GDB                = 1 << 15,
+};
 
 /*
  * Valid values for ARMCPRegInfo state field, indicating which of
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
     ARMCPRegInfo *ri = value;
     ARMCPU *cpu = opaque;
 
-    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
     ARMCPU *cpu = opaque;
     uint64_t oldvalue, newvalue;
 
-    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
         return;
     }
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * multiple times. Special registers (ie NOP/WFI) are
      * never migratable and not even raw-accessible.
      */
-    if ((r->type & ARM_CP_SPECIAL)) {
+    if (r->type & ARM_CP_SPECIAL_MASK) {
         r2->type |= ARM_CP_NO_RAW;
     }
     if (((r->crm == CP_ANY) && crm != 0) ||
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
     /* Check that the register definition has enough info to handle
      * reads and writes if they are permitted.
      */
-    if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
+    if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
         if (r->access & PL3_R) {
             assert((r->fieldoffset ||
                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
     }
 
     /* Handle special cases first */
-    switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
+    switch (ri->type & ARM_CP_SPECIAL_MASK) {
+    case 0:
+        break;
     case ARM_CP_NOP:
         return;
     case ARM_CP_NZCV:
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         }
         return;
     default:
-        break;
+        g_assert_not_reached();
     }
     if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
         return;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
         }
 
         /* Handle special cases first */
-        switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
+        switch (ri->type & ARM_CP_SPECIAL_MASK) {
+        case 0:
+            break;
         case ARM_CP_NOP:
             return;
         case ARM_CP_WFI:
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
             s->base.is_jmp = DISAS_WFI;
             return;
         default:
-            break;
+            g_assert_not_reached();
         }
 
         if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Standardize on g_assert_not_reached() for "should not happen".
Retain abort() when preceeded by fprintf or error_report.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c         | 7 +++----
 target/arm/hvf/hvf.c        | 2 +-
 target/arm/kvm-stub.c       | 4 ++--
 target/arm/kvm.c            | 4 ++--
 target/arm/machine.c        | 4 ++--
 target/arm/translate-a64.c  | 4 ++--
 target/arm/translate-neon.c | 2 +-
 target/arm/translate.c      | 4 ++--
 8 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
             break;
         default:
             /* broken reginfo with out-of-range opc1 */
-            assert(false);
-            break;
+            g_assert_not_reached();
         }
         /* assert our permissions are not too lax (stricter is fine) */
         assert((r->access & ~mask) == 0);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
             break;
         default:
             /* Never happens, but compiler isn't smart enough to tell.  */
-            abort();
+            g_assert_not_reached();
         }
     }
     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
             break;
         default:
             /* Never happens, but compiler isn't smart enough to tell.  */
-            abort();
+            g_assert_not_reached();
         }
     }
     if (domain_prot == 3) {
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
         /* we got kicked, no exit to process */
         return 0;
     default:
-        assert(0);
+        g_assert_not_reached();
     }
 
     hvf_sync_vtimer(cpu);
diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm-stub.c
+++ b/target/arm/kvm-stub.c
@@ -XXX,XX +XXX,XX @@
 
 bool write_kvmstate_to_list(ARMCPU *cpu)
 {
-    abort();
+    g_assert_not_reached();
 }
 
 bool write_list_to_kvmstate(ARMCPU *cpu, int level)
 {
-    abort();
+    g_assert_not_reached();
 }
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
             ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         if (ret) {
             ok = false;
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
             r.addr = (uintptr_t)(cpu->cpreg_values + i);
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
         if (ret) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
     if (kvm_enabled()) {
         if (!write_kvmstate_to_list(cpu)) {
             /* This should never fail */
-            abort();
+            g_assert_not_reached();
         }
 
         /*
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
     } else {
         if (!write_cpustate_to_list(cpu, false)) {
             /* This should never fail. */
-            abort();
+            g_assert_not_reached();
         }
     }
 
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
         gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
 
     write_fp_sreg(s, rd, tcg_res);
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
         break;
     }
     default:
-        abort();
+        g_assert_not_reached();
     }
 }
 
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
         }
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
     if ((vd + a->stride * (nregs - 1)) > 31) {
         /*
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
         offset = 4;
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
     tcg_gen_addi_i32(addr, addr, offset);
     tmp = load_reg(s, 14);
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
             offset = 0;
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         tcg_gen_addi_i32(addr, addr, offset);
         gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a typedef as well, and use it in ARMCPRegInfo.
This won't be perfect for debugging, but it'll nicely
display the most common cases.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 44 +++++++++++++++++++++++---------------------
 target/arm/helper.c |  2 +-
 2 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
  * described with these bits, then use a laxer set of restrictions, and
  * do the more restrictive/complex check inside a helper function.
  */
-#define PL3_R 0x80
-#define PL3_W 0x40
-#define PL2_R (0x20 | PL3_R)
-#define PL2_W (0x10 | PL3_W)
-#define PL1_R (0x08 | PL2_R)
-#define PL1_W (0x04 | PL2_W)
-#define PL0_R (0x02 | PL1_R)
-#define PL0_W (0x01 | PL1_W)
+typedef enum {
+    PL3_R = 0x80,
+    PL3_W = 0x40,
+    PL2_R = 0x20 | PL3_R,
+    PL2_W = 0x10 | PL3_W,
+    PL1_R = 0x08 | PL2_R,
+    PL1_W = 0x04 | PL2_W,
+    PL0_R = 0x02 | PL1_R,
+    PL0_W = 0x01 | PL1_W,
 
-/*
- * For user-mode some registers are accessible to EL0 via a kernel
- * trap-and-emulate ABI. In this case we define the read permissions
- * as actually being PL0_R. However some bits of any given register
- * may still be masked.
- */
+    /*
+     * For user-mode some registers are accessible to EL0 via a kernel
+     * trap-and-emulate ABI. In this case we define the read permissions
+     * as actually being PL0_R. However some bits of any given register
+     * may still be masked.
+     */
 #ifdef CONFIG_USER_ONLY
-#define PL0U_R PL0_R
+    PL0U_R = PL0_R,
 #else
-#define PL0U_R PL1_R
+    PL0U_R = PL1_R,
 #endif
 
-#define PL3_RW (PL3_R | PL3_W)
-#define PL2_RW (PL2_R | PL2_W)
-#define PL1_RW (PL1_R | PL1_W)
-#define PL0_RW (PL0_R | PL0_W)
+    PL3_RW = PL3_R | PL3_W,
+    PL2_RW = PL2_R | PL2_W,
+    PL1_RW = PL1_R | PL1_W,
+    PL0_RW = PL0_R | PL0_W,
+} CPAccessRights;
 
 typedef enum CPAccessResult {
     /* Access is permitted */
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     /* Register type: ARM_CP_* bits/values */
     int type;
     /* Access rights: PL*_[RW] */
-    int access;
+    CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
     int secure;
     /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      * to encompass the generic architectural permission check.
      */
     if (r->state != ARM_CP_STATE_AA32) {
-        int mask = 0;
+        CPAccessRights mask;
         switch (r->opc1) {
         case 0:
             /* min_EL EL1, but some accessible to EL0 via kernel ABI */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Give this enum a name and use in ARMCPRegInfo,
add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
  * Note that we rely on the values of these enums as we iterate through
  * the various states in some places.
  */
-enum {
+typedef enum {
     ARM_CP_STATE_AA32 = 0,
     ARM_CP_STATE_AA64 = 1,
     ARM_CP_STATE_BOTH = 2,
-};
+} CPState;
 
 /*
  * ARM CP register secure state flags.  These flags identify security state
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     uint8_t opc1;
     uint8_t opc2;
     /* Execution state in which this register is visible: ARM_CP_STATE_* */
-    int state;
+    CPState state;
     /* Register type: ARM_CP_* bits/values */
     int type;
     /* Access rights: PL*_[RW] */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-                                   void *opaque, int state, int secstate,
+                                   void *opaque, CPState state, int secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
      * the register, if any.
      */
-    int crm, opc1, opc2, state;
+    int crm, opc1, opc2;
     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
+    CPState state;
+
     /* 64 bit registers have only CRm and Opc1 fields */
     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
     /* op0 only exists in the AArch64 encodings */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 7 ++++---
 target/arm/helper.c | 7 +++++--
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  * registered entry will only have one to identify whether the entry is secure
  * or non-secure.
  */
-enum {
+typedef enum {
+    ARM_CP_SECSTATE_BOTH = 0,       /* define one cpreg for each secstate */
     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
-};
+} CPSecureState;
 
 /*
  * Access rights:
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     /* Access rights: PL*_[RW] */
     CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
-    int secure;
+    CPSecureState secure;
     /*
      * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
      * this register was defined: can be used to hand data through to the
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-                                   void *opaque, CPState state, int secstate,
+                                   void *opaque, CPState state,
+                                   CPSecureState secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                                    r->secure, crm, opc1, opc2,
                                                    r->name);
                             break;
-                        default:
+                        case ARM_CP_SECSTATE_BOTH:
                             name = g_strdup_printf("%s_S", r->name);
                             add_cpreg_to_hashtable(cpu, r, opaque, state,
                                                    ARM_CP_SECSTATE_S,
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                                    ARM_CP_SECSTATE_NS,
                                                    crm, opc1, opc2, r->name);
                             break;
+                        default:
+                            g_assert_not_reached();
                         }
                     } else {
                         /* AArch64 registers get mapped to non-secure instance
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The new_key field is always non-zero -- drop the if.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-11-richard.henderson@linaro.org
[PMM: reinstated dropped PL3_RW mask]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
 
     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
         const struct E2HAlias *a = &aliases[i];
-        ARMCPRegInfo *src_reg, *dst_reg;
+        ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
+        uint32_t *new_key;
+        bool ok;
 
         if (a->feature && !a->feature(&cpu->isar)) {
             continue;
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
         g_assert(src_reg->opaque == NULL);
 
         /* Create alias before redirection so we dup the right data. */
-        if (a->new_key) {
-            ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-            uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
-            bool ok;
+        new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
+        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
 
-            new_reg->name = a->new_name;
-            new_reg->type |= ARM_CP_ALIAS;
-            /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
-            new_reg->access &= PL2_RW | PL3_RW;
+        new_reg->name = a->new_name;
+        new_reg->type |= ARM_CP_ALIAS;
+        /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
+        new_reg->access &= PL2_RW | PL3_RW;
 
-            ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
-            g_assert(ok);
-        }
+        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
+        g_assert(ok);
 
         src_reg->opaque = dst_reg;
         src_reg->orig_readfn = src_reg->readfn ?: raw_read;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Cast the uint32_t key into a gpointer directly, which
allows us to avoid allocating storage for each key.

Use g_hash_table_lookup when we already have a gpointer
(e.g. for callbacks like count_cpreg), or when using
get_arm_cp_reginfo would require casting away const.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c     |  4 ++--
 target/arm/gdbstub.c |  2 +-
 target/arm/helper.c  | 41 ++++++++++++++++++-----------------------
 3 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
     ARMCPU *cpu = ARM_CPU(obj);
 
     cpu_set_cpustate_pointers(cpu);
-    cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
-                                         g_free, cpreg_hashtable_data_destroy);
+    cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
+                                         NULL, cpreg_hashtable_data_destroy);
 
     QLIST_INIT(&cpu->pre_el_change_hooks);
     QLIST_INIT(&cpu->el_change_hooks);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
 static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
                                         gpointer p)
 {
-    uint32_t ri_key = *(uint32_t *)key;
+    uint32_t ri_key = (uintptr_t)key;
     ARMCPRegInfo *ri = value;
     RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
     GString *s = param->s;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 {
     ARMCPU *cpu = opaque;
-    uint64_t regidx;
-    const ARMCPRegInfo *ri;
-
-    regidx = *(uint32_t *)key;
-    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+    uint32_t regidx = (uintptr_t)key;
+    const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 
     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
 static void count_cpreg(gpointer key, gpointer opaque)
 {
     ARMCPU *cpu = opaque;
-    uint64_t regidx;
     const ARMCPRegInfo *ri;
 
-    regidx = *(uint32_t *)key;
-    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+    ri = g_hash_table_lookup(cpu->cp_regs, key);
 
     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
         cpu->cpreg_array_len++;
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
 
 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 {
-    uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
-    uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
+    uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a);
+    uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b);
 
     if (aidx > bidx) {
         return 1;
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
         const struct E2HAlias *a = &aliases[i];
         ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
-        uint32_t *new_key;
         bool ok;
 
         if (a->feature && !a->feature(&cpu->isar)) {
             continue;
         }
 
-        src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
-        dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
+        src_reg = g_hash_table_lookup(cpu->cp_regs,
+                                      (gpointer)(uintptr_t)a->src_key);
+        dst_reg = g_hash_table_lookup(cpu->cp_regs,
+                                      (gpointer)(uintptr_t)a->dst_key);
         g_assert(src_reg != NULL);
         g_assert(dst_reg != NULL);
 
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
 
         /* Create alias before redirection so we dup the right data. */
         new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
 
         new_reg->name = a->new_name;
         new_reg->type |= ARM_CP_ALIAS;
         /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
         new_reg->access &= PL2_RW | PL3_RW;
 
-        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
+        ok = g_hash_table_insert(cpu->cp_regs,
+                                 (gpointer)(uintptr_t)a->new_key, new_reg);
         g_assert(ok);
 
         src_reg->opaque = dst_reg;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     /* Private utility function for define_one_arm_cp_reg_with_opaque():
      * add a single reginfo struct to the hash table.
      */
-    uint32_t *key = g_new(uint32_t, 1);
+    uint32_t key;
     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
             r2->cp = CP_REG_ARM64_SYSREG_CP;
         }
-        *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
-                                  r2->opc0, opc1, opc2);
+        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
+                                 r2->opc0, opc1, opc2);
     } else {
-        *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
+        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
     }
     if (opaque) {
         r2->opaque = opaque;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * requested.
      */
     if (!(r->type & ARM_CP_OVERRIDE)) {
-        ARMCPRegInfo *oldreg;
-        oldreg = g_hash_table_lookup(cpu->cp_regs, key);
+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
             fprintf(stderr, "Register redefined: cp=%d %d bit "
                     "crn=%d crm=%d opc1=%d opc2=%d, "
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
             g_assert_not_reached();
         }
     }
-    g_hash_table_insert(cpu->cp_regs, key, r2);
+    g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
 }
 
 
@@ -XXX,XX +XXX,XX @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
 
 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
 {
-    return g_hash_table_lookup(cpregs, &encoded_cp);
+    return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp);
 }
 
 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Simplify freeing cp_regs hash table entries by using a single
allocation for the entire value.

This fixes a theoretical bug if we were to ever free the entire
hash table, because we've been installing string literal constants
into the cpreg structure in define_arm_vh_e2h_redirects_aliases.
However, at present we only free entries created for AArch32
wildcard cpregs which get overwritten by more specific cpregs,
so this bug is never exposed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c    | 16 +---------------
 target/arm/helper.c | 10 ++++++++--
 2 files changed, 9 insertions(+), 17 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 }
 
-static void cpreg_hashtable_data_destroy(gpointer data)
-{
-    /*
-     * Destroy function for cpu->cp_regs hashtable data entries.
-     * We must free the name string because it was g_strdup()ed in
-     * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
-     * from r->name because we know we definitely allocated it.
-     */
-    ARMCPRegInfo *r = data;
-
-    g_free((void *)r->name);
-    g_free(r);
-}
-
 static void arm_cpu_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
     cpu_set_cpustate_pointers(cpu);
     cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
-                                         NULL, cpreg_hashtable_data_destroy);
+                                         NULL, g_free);
 
     QLIST_INIT(&cpu->pre_el_change_hooks);
     QLIST_INIT(&cpu->el_change_hooks);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * add a single reginfo struct to the hash table.
      */
     uint32_t key;
-    ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
+    ARMCPRegInfo *r2;
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+    size_t name_len;
+
+    /* Combine cpreg and name into one allocation. */
+    name_len = strlen(name) + 1;
+    r2 = g_malloc(sizeof(*r2) + name_len);
+    *r2 = *r;
+    r2->name = memcpy(r2 + 1, name, name_len);
 
-    r2->name = g_strdup(name);
     /* Reset the secure state to the specific incoming state.  This is
      * necessary as the register may have been defined with both states.
      */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the computation of key to the top of the function.
Hoist the resolution of cp as well, as an input to the
computation of key.

This will be required by a subsequent patch.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 49 +++++++++++++++++++++++++--------------------
 1 file changed, 27 insertions(+), 22 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     ARMCPRegInfo *r2;
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+    int cp = r->cp;
     size_t name_len;
 
+    switch (state) {
+    case ARM_CP_STATE_AA32:
+        /* We assume it is a cp15 register if the .cp field is left unset. */
+        if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
+            cp = 15;
+        }
+        key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
+        break;
+    case ARM_CP_STATE_AA64:
+        /*
+         * To allow abbreviation of ARMCPRegInfo definitions, we treat
+         * cp == 0 as equivalent to the value for "standard guest-visible
+         * sysreg".  STATE_BOTH definitions are also always "standard sysreg"
+         * in their AArch64 view (the .cp value may be non-zero for the
+         * benefit of the AArch32 view).
+         */
+        if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+            cp = CP_REG_ARM64_SYSREG_CP;
+        }
+        key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
 
         if (r->state == ARM_CP_STATE_BOTH) {
-            /* We assume it is a cp15 register if the .cp field is left unset.
-             */
-            if (r2->cp == 0) {
-                r2->cp = 15;
-            }
-
 #if HOST_BIG_ENDIAN
             if (r2->fieldoffset) {
                 r2->fieldoffset += sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 #endif
         }
     }
-    if (state == ARM_CP_STATE_AA64) {
-        /* To allow abbreviation of ARMCPRegInfo
-         * definitions, we treat cp == 0 as equivalent to
-         * the value for "standard guest-visible sysreg".
-         * STATE_BOTH definitions are also always "standard
-         * sysreg" in their AArch64 view (the .cp value may
-         * be non-zero for the benefit of the AArch32 view).
-         */
-        if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
-            r2->cp = CP_REG_ARM64_SYSREG_CP;
-        }
-        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
-                                 r2->opc0, opc1, opc2);
-    } else {
-        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
-    }
     if (opaque) {
         r2->opaque = opaque;
     }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     /* Make sure reginfo passed to helpers for wildcarded regs
      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
      */
+    r2->cp = cp;
     r2->crm = crm;
     r2->opc1 = opc1;
     r2->opc2 = opc2;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Put most of the value writeback to the same place,
and improve the comment that goes with them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     *r2 = *r;
     r2->name = memcpy(r2 + 1, name, name_len);
 
-    /* Reset the secure state to the specific incoming state.  This is
-     * necessary as the register may have been defined with both states.
+    /*
+     * Update fields to match the instantiation, overwiting wildcards
+     * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
      */
+    r2->cp = cp;
+    r2->crm = crm;
+    r2->opc1 = opc1;
+    r2->opc2 = opc2;
+    r2->state = state;
     r2->secure = secstate;
+    if (opaque) {
+        r2->opaque = opaque;
+    }
 
     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
         /* Register is banked (using both entries in array).
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 #endif
         }
     }
-    if (opaque) {
-        r2->opaque = opaque;
-    }
-    /* reginfo passed to helpers is correct for the actual access,
-     * and is never ARM_CP_STATE_BOTH:
-     */
-    r2->state = state;
-    /* Make sure reginfo passed to helpers for wildcarded regs
-     * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
-     */
-    r2->cp = cp;
-    r2->crm = crm;
-    r2->opc1 = opc1;
-    r2->opc2 = opc2;
+
     /* By convention, for wildcarded registers only the first
      * entry is used for migration; the others are marked as
      * ALIAS so we don't try to transfer the register
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Computing isbanked only once makes the code
a bit easier to read.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Perform the override check early, so that it is still done
even when we decide to discard an unreachable cpreg.

Use assert not printf+abort.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         g_assert_not_reached();
     }
 
+    /* Overriding of an existing definition must be explicitly requested. */
+    if (!(r->type & ARM_CP_OVERRIDE)) {
+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
+        if (oldreg) {
+            assert(oldreg->type & ARM_CP_OVERRIDE);
+        }
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         assert(!raw_accessors_invalid(r2));
     }
 
-    /* Overriding of an existing definition must be explicitly
-     * requested.
-     */
-    if (!(r->type & ARM_CP_OVERRIDE)) {
-        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
-        if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
-            fprintf(stderr, "Register redefined: cp=%d %d bit "
-                    "crn=%d crm=%d opc1=%d opc2=%d, "
-                    "was %s, now %s\n", r2->cp, 32 + 32 * is64,
-                    r2->crn, r2->crm, r2->opc1, r2->opc2,
-                    oldreg->name, r2->name);
-            g_assert_not_reached();
-        }
-    }
     g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Put the block comments into the current coding style.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
     return cpu_list;
 }
 
+/*
+ * Private utility function for define_one_arm_cp_reg_with_opaque():
+ * add a single reginfo struct to the hash table.
+ */
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                    void *opaque, CPState state,
                                    CPSecureState secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
-    /* Private utility function for define_one_arm_cp_reg_with_opaque():
-     * add a single reginfo struct to the hash table.
-     */
     uint32_t key;
     ARMCPRegInfo *r2;
     bool is64 = r->type & ARM_CP_64BIT;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 
     isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
     if (isbanked) {
-        /* Register is banked (using both entries in array).
+        /*
+         * Register is banked (using both entries in array).
          * Overwriting fieldoffset as the array is only used to define
          * banked registers but later only fieldoffset is used.
          */
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 
     if (state == ARM_CP_STATE_AA32) {
         if (isbanked) {
-            /* If the register is banked then we don't need to migrate or
+            /*
+             * If the register is banked then we don't need to migrate or
              * reset the 32-bit instance in certain cases:
              *
              * 1) If the register has both 32-bit and 64-bit instances then we
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                 r2->type |= ARM_CP_ALIAS;
             }
         } else if ((secstate != r->secure) && !ns) {
-            /* The register is not banked so we only want to allow migration of
-             * the non-secure instance.
+            /*
+             * The register is not banked so we only want to allow migration
+             * of the non-secure instance.
              */
             r2->type |= ARM_CP_ALIAS;
         }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
     }
 
-    /* By convention, for wildcarded registers only the first
+    /*
+     * By convention, for wildcarded registers only the first
      * entry is used for migration; the others are marked as
      * ALIAS so we don't try to transfer the register
      * multiple times. Special registers (ie NOP/WFI) are
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
     }
 
-    /* Check that raw accesses are either forbidden or handled. Note that
+    /*
+     * Check that raw accesses are either forbidden or handled. Note that
      * we can't assert this earlier because the setup of fieldoffset for
      * banked registers has to be done first.
      */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Since e03b56863d2bc, our host endian indicator is unconditionally
set, which means that we can use a normal C condition.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-20-richard.henderson@linaro.org
[PMM: quote correct git hash in commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
             r2->type |= ARM_CP_ALIAS;
         }
 
-        if (r->state == ARM_CP_STATE_BOTH) {
-#if HOST_BIG_ENDIAN
-            if (r2->fieldoffset) {
-                r2->fieldoffset += sizeof(uint32_t);
-            }
-#endif
+        if (HOST_BIG_ENDIAN &&
+            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
+            r2->fieldoffset += sizeof(uint32_t);
         }
     }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
 }
 
+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
 }
 
+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
+}
+
 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
 }
 
+static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
+}
+
 /*
  * Forward to the above feature tests given an ARMCPU pointer.
  */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Add the aa64 predicate for detecting RAS support from id registers.
We already have the aa32 version from the M-profile work.
Add the 'any' predicate for testing both aa64 and aa32.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
 }
 
+static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
+}
+
 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
     return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
 }
 
+static inline bool isar_feature_any_ras(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
+}
+
 /*
  * Forward to the above feature tests given an ARMCPU pointer.
  */
-- 
2.25.1

From: Alex Zuepke <alex.zuepke@tum.de>

The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.

Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
-              .accessfn = pmreg_access },
+              .accessfn = pmreg_access_xevcntr },
             { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
-              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
               .type = ARM_CP_IO,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
               .raw_readfn = pmevcntr_rawread,
-- 
2.25.1

Hi; not so many patches in this one, but notably it includes the
fix for various Avocado CI tests failing (incorrectly reported by
Avocado as a timeout, but really a QEMU exit-with-error).

thanks
-- PMM

The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:

Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930

for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:

target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
   PMCNTENSET_EL0 or PMCNTENCLR_EL0
 * Make writes to MDCR_EL3 use PMU start/finish calls
 * Let AArch32 write to SDCR.SCCD
 * Rearrange cpu64.c so all the CPU initfns are together
 * hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
 * hw/arm/virt: fix some minor issues with generated device tree
 * Fix regression where EL3 could not write to SP_EL1 if there is no EL2

----------------------------------------------------------------
Francisco Iglesias (1):
      hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers

Jean-Philippe Brucker (4):
      hw/arm/virt: Fix devicetree warning about the root node
      hw/arm/virt: Fix devicetree warning about the GIC node
      hw/arm/virt: Use "msi-map" devicetree property for PCI
      hw/arm/virt: Fix devicetree warning about the SMMU node

Jerome Forissier (1):
      target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP

Peter Maydell (4):
      target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
      target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
      target/arm: Update SDCR_VALID_MASK to include SCCD
      target/arm: Rearrange cpu64.c so all the CPU initfns are together

In commit 01765386a888 we made some system register write functions
call pmu_op_start()/pmu_op_finish(). This means that they now touch
timers, so for icount to work these registers must have the ARM_CP_IO
flag set.

This fixes a bug where when icount is enabled a guest that touches
MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
QEMU to print an error message and exit, for example:

[    2.495971] TCP: Hash tables configured (established 1024 bind 1024)
[    2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    2.496917] NET: Registered protocol family 1
qemu-system-aarch64: Bad icount read

Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
---
 target/arm/helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
      */
     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
-      .access = PL0_RW, .type = ARM_CP_ALIAS,
+      .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
       .writefn = pmcntenset_write,
       .accessfn = pmreg_access,
       .raw_writefn = raw_write },
-    { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
+    { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
       .access = PL0_RW, .accessfn = pmreg_access,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
       .accessfn = pmreg_access,
       .writefn = pmcntenclr_write,
-      .type = ARM_CP_ALIAS },
+      .type = ARM_CP_ALIAS | ARM_CP_IO },
     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
       .access = PL0_RW, .accessfn = pmreg_access,
-      .type = ARM_CP_ALIAS,
+      .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
       .writefn = pmcntenclr_write },
     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
       .resetvalue = 0,
       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
-    { .name = "SDCR", .type = ARM_CP_ALIAS,
+    { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
       .writefn = sdcr_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
          */
         ARMCPRegInfo mdcr_el2 = {
-            .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
+            .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
             .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
             .writefn = mdcr_el2_write,
             .access = PL2_RW, .resetvalue = pmu_num_counters(env),
-- 
2.25.1

In commit 01765386a88868 we fixed a bug where we weren't correctly
bracketing changes to some registers with pmu_op_start() and
pmu_op_finish() calls for changes which affect whether the PMU
counters might be enabled.  However, we missed the case of writes to
the AArch64 MDCR_EL3 register, because (unlike its AArch32
counterpart) they are currently done directly to the CPU state struct
without going through the sdcr_write() function.

Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
masking off the bits which don't exist in the AArch32 register".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
---
 target/arm/helper.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 }
 
-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                       uint64_t value)
+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                           uint64_t value)
 {
     /*
      * Some MDCR_EL3 bits affect whether PMU counters are running:
@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     if (pmu_op) {
         pmu_op_start(env);
     }
-    env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
+    env->cp15.mdcr_el3 = value;
     if (pmu_op) {
         pmu_op_finish(env);
     }
 }
 
+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                       uint64_t value)
+{
+    /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
+    mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
+}
+
 static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
                            uint64_t value)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL2_RW,
       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
     { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
+      .type = ARM_CP_IO,
       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
       .resetvalue = 0,
-      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
+      .access = PL3_RW,
+      .writefn = mdcr_el3_write,
+      .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
     { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
-- 
2.25.1

Our SDCR_VALID_MASK doesn't include all of the bits which are defined
by the current architecture.  In particular in commit 0b42f4fab9d3 we
forgot to add SCCD, which meant that an AArch32 guest couldn't
actually use the SCCD bit to disable counting in Secure state.

Add all the currently defined bits; we don't implement all of them,
but this makes them be reads-as-written, which is architecturally
valid and matches how we currently handle most of the others in the
mask.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
---
 target/arm/cpu.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
 FIELD(CPTR_EL3, TAM, 30, 1)
 FIELD(CPTR_EL3, TCPAC, 31, 1)
 
+#define MDCR_MTPME    (1U << 28)
+#define MDCR_TDCC     (1U << 27)
 #define MDCR_HLP      (1U << 26)  /* MDCR_EL2 */
 #define MDCR_SCCD     (1U << 23)  /* MDCR_EL3 */
 #define MDCR_HCCD     (1U << 23)  /* MDCR_EL2 */
 #define MDCR_EPMAD    (1U << 21)
 #define MDCR_EDAD     (1U << 20)
+#define MDCR_TTRF     (1U << 19)
+#define MDCR_STE      (1U << 18)  /* MDCR_EL3 */
 #define MDCR_SPME     (1U << 17)  /* MDCR_EL3 */
 #define MDCR_HPMD     (1U << 17)  /* MDCR_EL2 */
 #define MDCR_SDD      (1U << 16)
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
 #define MDCR_HPMN     (0x1fU)
 
 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
+                         MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
+                         MDCR_STE | MDCR_SPME | MDCR_SPD)
 
 #define CPSR_M (0x1fU)
 #define CPSR_T (1U << 5)
-- 
2.25.1

cpu64.c has ended up in a slightly odd order -- it starts with the
initfns for most of the models-real-hardware CPUs; after that comes a
bunch of support code for SVE, SME, pauth and LPA2 properties.  Then
come the initfns for the 'host' and 'max' CPU types, and then after
that one more models-real-hardware CPU initfn, for a64fx.  (This
ordering is partly historical and partly required because a64fx needs
the SVE properties.)

Reorder the file into:
 * CPU property support functions
 * initfns for real hardware CPUs
 * initfns for host and max
 * class boilerplate

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
 1 file changed, 356 insertions(+), 356 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
-static void aarch64_a57_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a57";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
-    cpu->midr = 0x411fd070;
-    cpu->revidr = 0x00000000;
-    cpu->reset_fpsid = 0x41034070;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x12111111;
-    cpu->isar.mvfr2 = 0x00000043;
-    cpu->ctr = 0x8444c004;
-    cpu->reset_sctlr = 0x00c50838;
-    cpu->isar.id_pfr0 = 0x00000131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x03010066;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10101105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00011142;
-    cpu->isar.id_isar5 = 0x00011121;
-    cpu->isar.id_isar6 = 0;
-    cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->isar.id_aa64dfr0 = 0x10305106;
-    cpu->isar.id_aa64isar0 = 0x00011120;
-    cpu->isar.id_aa64mmfr0 = 0x00001124;
-    cpu->isar.dbgdidr = 0x3516d000;
-    cpu->isar.dbgdevid = 0x01110f13;
-    cpu->isar.dbgdevid1 = 0x2;
-    cpu->isar.reset_pmcr_el0 = 0x41013000;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
-    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
-    cpu->dcz_blocksize = 4; /* 64 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-    define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a53_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a53";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
-    cpu->midr = 0x410fd034;
-    cpu->revidr = 0x00000000;
-    cpu->reset_fpsid = 0x41034070;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x12111111;
-    cpu->isar.mvfr2 = 0x00000043;
-    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
-    cpu->reset_sctlr = 0x00c50838;
-    cpu->isar.id_pfr0 = 0x00000131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x03010066;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10101105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00011142;
-    cpu->isar.id_isar5 = 0x00011121;
-    cpu->isar.id_isar6 = 0;
-    cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->isar.id_aa64dfr0 = 0x10305106;
-    cpu->isar.id_aa64isar0 = 0x00011120;
-    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
-    cpu->isar.dbgdidr = 0x3516d000;
-    cpu->isar.dbgdevid = 0x00110f13;
-    cpu->isar.dbgdevid1 = 0x1;
-    cpu->isar.reset_pmcr_el0 = 0x41033000;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
-    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
-    cpu->dcz_blocksize = 4; /* 64 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-    define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a72_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a72";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->midr = 0x410fd083;
-    cpu->revidr = 0x00000000;
-    cpu->reset_fpsid = 0x41034080;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x12111111;
-    cpu->isar.mvfr2 = 0x00000043;
-    cpu->ctr = 0x8444c004;
-    cpu->reset_sctlr = 0x00c50838;
-    cpu->isar.id_pfr0 = 0x00000131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x03010066;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10201105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00011142;
-    cpu->isar.id_isar5 = 0x00011121;
-    cpu->isar.id_aa64pfr0 = 0x00002222;
-    cpu->isar.id_aa64dfr0 = 0x10305106;
-    cpu->isar.id_aa64isar0 = 0x00011120;
-    cpu->isar.id_aa64mmfr0 = 0x00001124;
-    cpu->isar.dbgdidr = 0x3516d000;
-    cpu->isar.dbgdevid = 0x01110f13;
-    cpu->isar.dbgdevid1 = 0x2;
-    cpu->isar.reset_pmcr_el0 = 0x41023000;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
-    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
-    cpu->dcz_blocksize = 4; /* 64 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-    define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a76_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a76";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-
-    /* Ordered by B2.4 AArch64 registers by functional group */
-    cpu->clidr = 0x82000023;
-    cpu->ctr = 0x8444C004;
-    cpu->dcz_blocksize = 4;
-    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
-    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
-    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
-    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
-    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
-    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
-    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
-    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
-    cpu->id_afr0       = 0x00000000;
-    cpu->isar.id_dfr0  = 0x04010088;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00010142;
-    cpu->isar.id_isar5 = 0x01011121;
-    cpu->isar.id_isar6 = 0x00000010;
-    cpu->isar.id_mmfr0 = 0x10201105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02122211;
-    cpu->isar.id_mmfr4 = 0x00021110;
-    cpu->isar.id_pfr0  = 0x10010131;
-    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
-    cpu->isar.id_pfr2  = 0x00000011;
-    cpu->midr = 0x414fd0b1;          /* r4p1 */
-    cpu->revidr = 0;
-
-    /* From B2.18 CCSIDR_EL1 */
-    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
-
-    /* From B2.93 SCTLR_EL3 */
-    cpu->reset_sctlr = 0x30c50838;
-
-    /* From B4.23 ICH_VTR_EL2 */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-
-    /* From B5.1 AdvSIMD AArch64 register summary */
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x13211111;
-    cpu->isar.mvfr2 = 0x00000043;
-
-    /* From D5.1 AArch64 PMU register summary */
-    cpu->isar.reset_pmcr_el0 = 0x410b3000;
-}
-
-static void aarch64_neoverse_n1_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,neoverse-n1";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-
-    /* Ordered by B2.4 AArch64 registers by functional group */
-    cpu->clidr = 0x82000023;
-    cpu->ctr = 0x8444c004;
-    cpu->dcz_blocksize = 4;
-    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
-    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
-    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
-    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
-    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
-    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
-    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
-    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
-    cpu->id_afr0       = 0x00000000;
-    cpu->isar.id_dfr0  = 0x04010088;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232042;
-    cpu->isar.id_isar3 = 0x01112131;
-    cpu->isar.id_isar4 = 0x00010142;
-    cpu->isar.id_isar5 = 0x01011121;
-    cpu->isar.id_isar6 = 0x00000010;
-    cpu->isar.id_mmfr0 = 0x10201105;
-    cpu->isar.id_mmfr1 = 0x40000000;
-    cpu->isar.id_mmfr2 = 0x01260000;
-    cpu->isar.id_mmfr3 = 0x02122211;
-    cpu->isar.id_mmfr4 = 0x00021110;
-    cpu->isar.id_pfr0  = 0x10010131;
-    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
-    cpu->isar.id_pfr2  = 0x00000011;
-    cpu->midr = 0x414fd0c1;          /* r4p1 */
-    cpu->revidr = 0;
-
-    /* From B2.23 CCSIDR_EL1 */
-    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
-
-    /* From B2.98 SCTLR_EL3 */
-    cpu->reset_sctlr = 0x30c50838;
-
-    /* From B4.23 ICH_VTR_EL2 */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-
-    /* From B5.1 AdvSIMD AArch64 register summary */
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x13211111;
-    cpu->isar.mvfr2 = 0x00000043;
-
-    /* From D5.1 AArch64 PMU register summary */
-    cpu->isar.reset_pmcr_el0 = 0x410c3000;
-}
-
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
     cpu->isar.id_aa64mmfr0 = t;
 }
 
+static void aarch64_a57_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a57";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
+    cpu->midr = 0x411fd070;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0;
+    cpu->isar.id_aa64pfr0 = 0x00002222;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64isar0 = 0x00011120;
+    cpu->isar.id_aa64mmfr0 = 0x00001124;
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->isar.dbgdevid = 0x01110f13;
+    cpu->isar.dbgdevid1 = 0x2;
+    cpu->isar.reset_pmcr_el0 = 0x41013000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a53_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a53";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
+    cpu->midr = 0x410fd034;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0;
+    cpu->isar.id_aa64pfr0 = 0x00002222;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64isar0 = 0x00011120;
+    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->isar.dbgdevid = 0x00110f13;
+    cpu->isar.dbgdevid1 = 0x1;
+    cpu->isar.reset_pmcr_el0 = 0x41033000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a72_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a72";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x410fd083;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034080;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_aa64pfr0 = 0x00002222;
+    cpu->isar.id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64isar0 = 0x00011120;
+    cpu->isar.id_aa64mmfr0 = 0x00001124;
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->isar.dbgdevid = 0x01110f13;
+    cpu->isar.dbgdevid1 = 0x2;
+    cpu->isar.reset_pmcr_el0 = 0x41023000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a76_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a76";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444C004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0b1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.18 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+    /* From B2.93 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+
+    /* From D5.1 AArch64 PMU register summary */
+    cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
+static void aarch64_a64fx_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,a64fx";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x461f0010;
+    cpu->revidr = 0x00000000;
+    cpu->ctr = 0x86668006;
+    cpu->reset_sctlr = 0x30000180;
+    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
+    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
+    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
+    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
+    cpu->id_aa64afr0 = 0x0000000000000000;
+    cpu->id_aa64afr1 = 0x0000000000000000;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
+    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
+    cpu->isar.id_aa64isar0 = 0x0000000010211120;
+    cpu->isar.id_aa64isar1 = 0x0000000000010001;
+    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
+    cpu->clidr = 0x0000000080000023;
+    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
+    cpu->dcz_blocksize = 6; /* 256 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+
+    /* The A64FX supports only 128, 256 and 512 bit vector lengths */
+    aarch64_add_sve_properties(obj);
+    cpu->sve_vq.supported = (1 << 0)  /* 128bit */
+                          | (1 << 1)  /* 256bit */
+                          | (1 << 3); /* 512bit */
+
+    cpu->isar.reset_pmcr_el0 = 0x46014040;
+
+    /* TODO:  Add A64FX specific HPC extension registers */
+}
+
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,neoverse-n1";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444c004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0c1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.23 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+    /* From B2.98 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+
+    /* From D5.1 AArch64 PMU register summary */
+    cpu->isar.reset_pmcr_el0 = 0x410c3000;
+}
+
 static void aarch64_host_initfn(Object *obj)
 {
 #if defined(CONFIG_KVM)
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
 }
 
-static void aarch64_a64fx_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,a64fx";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->midr = 0x461f0010;
-    cpu->revidr = 0x00000000;
-    cpu->ctr = 0x86668006;
-    cpu->reset_sctlr = 0x30000180;
-    cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
-    cpu->isar.id_aa64pfr1 = 0x0000000000000000;
-    cpu->isar.id_aa64dfr0 = 0x0000000010305408;
-    cpu->isar.id_aa64dfr1 = 0x0000000000000000;
-    cpu->id_aa64afr0 = 0x0000000000000000;
-    cpu->id_aa64afr1 = 0x0000000000000000;
-    cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
-    cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
-    cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
-    cpu->isar.id_aa64isar0 = 0x0000000010211120;
-    cpu->isar.id_aa64isar1 = 0x0000000000010001;
-    cpu->isar.id_aa64zfr0 = 0x0000000000000000;
-    cpu->clidr = 0x0000000080000023;
-    cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
-    cpu->dcz_blocksize = 6; /* 256 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
-
-    /* The A64FX supports only 128, 256 and 512 bit vector lengths */
-    aarch64_add_sve_properties(obj);
-    cpu->sve_vq.supported = (1 << 0)  /* 128bit */
-                          | (1 << 1)  /* 256bit */
-                          | (1 << 3); /* 512bit */
-
-    cpu->isar.reset_pmcr_el0 = 0x46014040;
-
-    /* TODO:  Add A64FX specific HPC extension registers */
-}
-
 static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a35",         .initfn = aarch64_a35_initfn },
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
-- 
2.25.1

From: Francisco Iglesias <francisco.iglesias@amd.com>

Connect ZynqMP's USB controllers.

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-zynqmp.h |  3 +++
 hw/arm/xlnx-zynqmp.c         | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
 #include "hw/misc/xlnx-zynqmp-crf.h"
 #include "hw/timer/cadence_ttc.h"
+#include "hw/usb/hcd-dwc3.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
 #define XLNX_ZYNQMP_NUM_SPIS 2
 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
 #define XLNX_ZYNQMP_NUM_ADMA_CH 8
+#define XLNX_ZYNQMP_NUM_USB 2
 
 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
     XlnxZynqMPAPUCtrl apu_ctrl;
     XlnxZynqMPCRF crf;
     CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
+    USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
 
     char *boot_cpu;
     ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
     77, 78, 79, 80, 81, 82, 83, 84
 };
 
+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
+    0xFE200000, 0xFE300000
+};
+
+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
+    65, 70
+};
+
 typedef struct XlnxZynqMPGICRegion {
     int region_index;
     uint32_t address;
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
     object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
     object_initialize_child(obj, "qspi-irq-orgate",
                             &s->qspi_irq_orgate, TYPE_OR_IRQ);
+
+    for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
+        object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
+    }
 }
 
 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
         object_property_add_alias(OBJECT(s), bus_name,
                                   OBJECT(&s->qspi), target_bus);
     }
+
+    for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
+        if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
+                                      OBJECT(system_memory), errp)) {
+            return;
+        }
+
+        qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
+        qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
+
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
+            return;
+        }
+
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
+                           gic_spi[usb_intr[i]]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
+                           gic_spi[usb_intr[i] + 1]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
+                           gic_spi[usb_intr[i] + 2]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
+                           gic_spi[usb_intr[i] + 3]);
+    }
 }
 
 static Property xlnx_zynqmp_props[] = {
-- 
2.25.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The devicetree specification requires a 'model' property in the root
node. Fix the corresponding dt-validate warning:

/: 'model' is a required property
  From schema: dtschema/schemas/root-node.yaml

Use the same name for model as for compatible. The specification
recommends that 'compatible' follows the format 'manufacturer,model' and
'model' follows the format 'manufacturer,model-number'. Since our
'compatible' doesn't observe this, 'model' doesn't really need to
either.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
+    qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
 
     /* /chosen must exist for load_dtb to fill in necessary properties later */
     qemu_fdt_add_subnode(fdt, "/chosen");
-- 
2.25.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
the corresponding dt-validate warning:

interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
  From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
                             "arm,gic-v3-its");
     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
                                  2, vms->memmap[VIRT_GIC_ITS].base,
                                  2, vms->memmap[VIRT_GIC_ITS].size);
-- 
2.25.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The "msi-parent" property can be used on the PCI node when MSIs do not
contain sideband data (device IDs) [1]. In QEMU, MSI transactions
contain the requester ID, so the PCI node should use the "msi-map"
property instead of "msi-parent". In our case the property describes an
identity map between requester ID and sideband data.

This fixes a warning when passing the DTB generated by QEMU to dtc,
following a recent change to the GICv3 node:

Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1

[1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
 
     if (vms->msi_phandle) {
-        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
-                               vms->msi_phandle);
+        qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
+                               0, vms->msi_phandle, 0, 0x10000);
     }
 
     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
-- 
2.25.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The SMMUv3 node isn't expected to have clock properties
(unlike the SMMUv2). Fix the corresponding dt-validate warning:

smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
  From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message as suggested by Eric]
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
     qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
                      sizeof(irq_names));
 
-    qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
-    qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
     qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
 
     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
-- 
2.25.1

From: Jerome Forissier <jerome.forissier@linaro.org>

SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
it with ARM_CP_EL3_NO_EL2_KEEP.

Cc: qemu-stable@nongnu.org
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_ALIAS,
+      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
-- 
2.25.1