Series comparison

-[PULL 00/23] target-arm queue
+[PULL 00/21] target-arm queue
-Two small bugfixes, plus most of RTH's refactoring of cpregs
+Arm queue; not huge but I figured I might as well send it out since
-handling.
+I've been doing code review today and there's no queue of unprocessed
 pullreqs...
+thanks
 -- PMM
-The following changes since commit 1fba9dc71a170b3a05b9d3272dd8ecfe7f26e215:
+The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
-  Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging (2022-05-04 08:07:02 -0700)
+  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220505
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
-for you to fetch changes up to 99a50d1a67c602126fc2b3a4812d3000eba9bf34:
+for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
-  target/arm: read access to performance counters from EL0 (2022-05-05 09:36:22 +0100)
+  ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * Enable read access to performance counters from EL0
+ * arm: Support emulation of ARMv8.4-TTST extension
- * Enable SCTLR_EL1.BT0 for aarch64-linux-user
+ * arm: Update cpu.h ID register field definitions
- * Refactoring of cpreg handling
+ * arm: Fix breakage of XScale instruction emulation
  * hw/net/lan9118: Fix RX Status FIFO PEEK value
  * npcm7xx: Add ADC and PWM emulation
  * ui/cocoa: Make "open docs" help menu entry work again when binary
    is run from the build tree
  * ui/cocoa: Fix openFile: deprecation on Big Sur
  * docs: Add qemu-storage-daemon(1) manpage to meson.build
  * docs: Build and install all the docs in a single manual
 ----------------------------------------------------------------
-Alex Zuepke (1):
+Hao Wu (6):
-      target/arm: read access to performance counters from EL0
+      hw/misc: Add clock converter in NPCM7XX CLK module
       hw/timer: Refactor NPCM7XX Timer to use CLK clock
       hw/adc: Add an ADC module for NPCM7XX
       hw/misc: Add a PWM module for NPCM7XX
       hw/misc: Add QTest for NPCM7XX PWM Module
       hw/*: Use type casting for SysBusDevice in NPCM7XX
-Richard Henderson (22):
+Leif Lindholm (6):
-      target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
+      target/arm: fix typo in cpu.h ID_AA64PFR1 field name
-      target/arm: Split out cpregs.h
+      target/arm: make ARMCPU.clidr 64-bit
-      target/arm: Reorg CPAccessResult and access_check_cp_reg
+      target/arm: make ARMCPU.ctr 64-bit
-      target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
+      target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
-      target/arm: Make some more cpreg data static const
+      target/arm: add aarch64 ID register fields to cpu.h
-      target/arm: Reorg ARMCPRegInfo type field bits
+      target/arm: add aarch32 ID register fields to cpu.h
       target/arm: Avoid bare abort() or assert(0)
       target/arm: Change cpreg access permissions to enum
       target/arm: Name CPState type
       target/arm: Name CPSecureState type
       target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
       target/arm: Store cpregs key in the hash table directly
       target/arm: Merge allocation of the cpreg and its name
       target/arm: Hoist computation of key in add_cpreg_to_hashtable
       target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
       target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
       target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
       target/arm: Perform override check early in add_cpreg_to_hashtable
       target/arm: Reformat comments in add_cpreg_to_hashtable
       target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
       target/arm: Add isar predicates for FEAT_Debugv8p2
       target/arm: Add isar_feature_{aa64,any}_ras
- target/arm/cpregs.h               | 453 ++++++++++++++++++++++++++++++++++++++
+Peter Maydell (5):
- target/arm/cpu.h                  | 393 +++------------------------------
+      docs: Add qemu-storage-daemon(1) manpage to meson.build
- hw/arm/pxa2xx.c                   |   2 +-
+      docs: Build and install all the docs in a single manual
- hw/arm/pxa2xx_pic.c               |   2 +-
+      target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
- hw/intc/arm_gicv3_cpuif.c         |   6 +-
+      hw/net/lan9118: Fix RX Status FIFO PEEK value
- hw/intc/arm_gicv3_kvm.c           |   3 +-
+      hw/net/lan9118: Add symbolic constants for register offsets
- target/arm/cpu.c                  |  25 +--
- target/arm/cpu64.c                |   2 +-
+Roman Bolshakov (2):
- target/arm/cpu_tcg.c              |   5 +-
+      ui/cocoa: Update path to docs in build tree
- target/arm/gdbstub.c              |   5 +-
+      ui/cocoa: Fix openFile: deprecation on Big Sur
- target/arm/helper.c               | 358 +++++++++++++-----------------
- target/arm/hvf/hvf.c              |   2 +-
+Rémi Denis-Courmont (2):
- target/arm/kvm-stub.c             |   4 +-
+      target/arm: ARMv8.4-TTST extension
- target/arm/kvm.c                  |   4 +-
+      target/arm: enable Small Translation tables in max CPU
- target/arm/machine.c              |   4 +-
- target/arm/op_helper.c            |  57 ++---
+ docs/conf.py                     |  46 ++-
- target/arm/translate-a64.c        |  14 +-
+ docs/devel/conf.py               |  15 -
- target/arm/translate-neon.c       |   2 +-
+ docs/index.html.in               |  17 -
- target/arm/translate.c            |  13 +-
+ docs/interop/conf.py             |  28 --
- tests/tcg/aarch64/bti-3.c         |  42 ++++
+ docs/meson.build                 |  65 ++--
- tests/tcg/aarch64/Makefile.target |   6 +-
+ docs/specs/conf.py               |  16 -
-files changed, 738 insertions(+), 664 deletions(-)
+ docs/system/arm/nuvoton.rst      |   4 +-
- create mode 100644 target/arm/cpregs.h
+ docs/system/conf.py              |  28 --
- create mode 100644 tests/tcg/aarch64/bti-3.c
+ docs/tools/conf.py               |  37 --
  docs/user/conf.py                |  15 -
  meson.build                      |   1 +
  hw/adc/trace.h                   |   1 +
  include/hw/adc/npcm7xx_adc.h     |  69 ++++
  include/hw/arm/npcm7xx.h         |   4 +
  include/hw/misc/npcm7xx_clk.h    | 146 ++++++-
  include/hw/misc/npcm7xx_pwm.h    | 105 +++++
  include/hw/timer/npcm7xx_timer.h |   1 +
  target/arm/cpu.h                 |  85 ++++-
  hw/adc/npcm7xx_adc.c             | 301 +++++++++++++++
  hw/arm/npcm7xx.c                 |  55 ++-
  hw/arm/npcm7xx_boards.c          |   2 +-
  hw/mem/npcm7xx_mc.c              |   2 +-
  hw/misc/npcm7xx_clk.c            | 807 ++++++++++++++++++++++++++++++++++++++-
  hw/misc/npcm7xx_gcr.c            |   2 +-
  hw/misc/npcm7xx_pwm.c            | 550 ++++++++++++++++++++++++++
  hw/misc/npcm7xx_rng.c            |   2 +-
  hw/net/lan9118.c                 |  26 +-
  hw/nvram/npcm7xx_otp.c           |   2 +-
  hw/ssi/npcm7xx_fiu.c             |   2 +-
  hw/timer/npcm7xx_timer.c         |  39 +-
  target/arm/cpu64.c               |   1 +
  target/arm/helper.c              |  15 +-
  target/arm/translate.c           |   7 +
  tests/qtest/npcm7xx_adc-test.c   | 377 ++++++++++++++++++
  tests/qtest/npcm7xx_pwm-test.c   | 490 ++++++++++++++++++++++++
  hw/adc/meson.build               |   1 +
  hw/adc/trace-events              |   5 +
  hw/misc/meson.build              |   1 +
  hw/misc/trace-events             |   6 +
  tests/qtest/meson.build          |   4 +-
  ui/cocoa.m                       |   7 +-
 files changed, 3124 insertions(+), 263 deletions(-)
  delete mode 100644 docs/devel/conf.py
  delete mode 100644 docs/index.html.in
  delete mode 100644 docs/interop/conf.py
  delete mode 100644 docs/specs/conf.py
  delete mode 100644 docs/system/conf.py
  delete mode 100644 docs/tools/conf.py
  delete mode 100644 docs/user/conf.py
  create mode 100644 hw/adc/trace.h
  create mode 100644 include/hw/adc/npcm7xx_adc.h
  create mode 100644 include/hw/misc/npcm7xx_pwm.h
  create mode 100644 hw/adc/npcm7xx_adc.c
  create mode 100644 hw/misc/npcm7xx_pwm.c
  create mode 100644 tests/qtest/npcm7xx_adc-test.c
  create mode 100644 tests/qtest/npcm7xx_pwm-test.c
  create mode 100644 hw/adc/trace-events

-[PULL 20/23] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
+[PULL 01/21] target/arm: ARMv8.4-TTST extension
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
-Since e03b56863d2bc, our host endian indicator is unconditionally
+This adds for the Small Translation tables extension in AArch64 state.
 set, which means that we can use a normal C condition.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220501055028.646596-20-richard.henderson@linaro.org
 [PMM: quote correct git hash in commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 9 +++------
+ target/arm/cpu.h    |  5 +++++
-file changed, 3 insertions(+), 6 deletions(-)
+ target/arm/helper.c | 15 +++++++++++++--
 files changed, 18 insertions(+), 2 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
+     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
+ }
++static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
++{
++    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
++}
++
+ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
+ {
+     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
-             r2->type |= ARM_CP_ALIAS;
+ {
-         }
+     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
+     bool epd, hpd, using16k, using64k;
--        if (r->state == ARM_CP_STATE_BOTH) {
+-    int select, tsz, tbi;
--#if HOST_BIG_ENDIAN
++    int select, tsz, tbi, max_tsz;
--            if (r2->fieldoffset) {
--                r2->fieldoffset += sizeof(uint32_t);
+     if (!regime_has_2_ranges(mmu_idx)) {
--            }
+         select = 0;
--#endif
+@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
-+        if (HOST_BIG_ENDIAN &&
+             hpd = extract64(tcr, 42, 1);
 +            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
 +            r2->fieldoffset += sizeof(uint32_t);
          }
      }
+-    tsz = MIN(tsz, 39);  /* TODO: ARMv8.4-TTST */
 +
 +    if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
 +        max_tsz = 48 - using64k;
 +    } else {
 +        max_tsz = 39;
 +    }
 +
 +    tsz = MIN(tsz, max_tsz);
      tsz = MAX(tsz, 16);  /* TODO: ARMv8.2-LVA  */
      /* Present TBI as a composite with TBID.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
          if (!aarch64 || stride == 9) {
              /* AArch32 or 4KB pages */
              startlevel = 2 - sl0;
 +
 +            if (cpu_isar_feature(aa64_st, cpu)) {
 +                startlevel &= 3;
 +            }
          } else {
              /* 16KB or 64KB pages */
              startlevel = 3 - sl0;
 --
-.25.1
+.20.1

-[PULL 04/23] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
+[PULL 02/21] target/arm: enable Small Translation tables in max CPU
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
-Remove a possible source of error by removing REGINFO_SENTINEL
+Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
-and using ARRAY_SIZE (convinently hidden inside a macro) to
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 find the end of the set of regs being registered or modified.
 The space saved by not having the extra array element reduces
 the executable's .data.rel.ro section by about 9k.
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220501055028.646596-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h       |  53 +++++++++---------
+ target/arm/cpu64.c | 1 +
- hw/arm/pxa2xx.c           |   1 -
+file changed, 1 insertion(+)
  hw/arm/pxa2xx_pic.c       |   1 -
  hw/intc/arm_gicv3_cpuif.c |   5 --
  hw/intc/arm_gicv3_kvm.c   |   1 -
  target/arm/cpu64.c        |   1 -
  target/arm/cpu_tcg.c      |   4 --
  target/arm/helper.c       | 111 ++++++++------------------------------
 files changed, 48 insertions(+), 129 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@
- #define ARM_CP_NO_GDB            0x4000
- #define ARM_CP_RAISES_EXC        0x8000
- #define ARM_CP_NEWEL             0x10000
--/* Used only as a terminator for ARMCPRegInfo lists */
--#define ARM_CP_SENTINEL          0xfffff
- /* Mask of only the flag bits in a type field */
- #define ARM_CP_FLAG_MASK         0x1f0ff
-@@ -XXX,XX +XXX,XX @@ enum {
-     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
- };
--/*
-- * Return true if cptype is a valid type field. This is used to try to
-- * catch errors where the sentinel has been accidentally left off the end
-- * of a list of registers.
-- */
--static inline bool cptype_valid(int cptype)
--{
--    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
--        || ((cptype & ARM_CP_SPECIAL) &&
--            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
--}
--
- /*
-  * Access rights:
-  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
-@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
- #define CPREG_FIELD64(env, ri) \
-     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
--#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
-+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
-+                                       void *opaque);
--void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
--                                    const ARMCPRegInfo *regs, void *opaque);
--void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
--                                       const ARMCPRegInfo *regs, void *opaque);
--static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
--{
--    define_arm_cp_regs_with_opaque(cpu, regs, 0);
--}
- static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
- {
--    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
-+    define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
- }
-+
-+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
-+                                        void *opaque, size_t len);
-+
-+#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE)               \
-+    do {                                                                \
-+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
-+        define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE,           \
-+                                           ARRAY_SIZE(REGS));           \
-+    } while (0)
-+
-+#define define_arm_cp_regs(CPU, REGS) \
-+    define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
-+
- const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
- /*
-@@ -XXX,XX +XXX,XX @@ typedef struct ARMCPRegUserSpaceInfo {
-     uint64_t fixed_bits;
- } ARMCPRegUserSpaceInfo;
--#define REGUSERINFO_SENTINEL { .name = NULL }
-+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
-+                                 const ARMCPRegUserSpaceInfo *mods,
-+                                 size_t mods_len);
--void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
-+#define modify_arm_cp_regs(REGS, MODS)                                  \
-+    do {                                                                \
-+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
-+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0);                       \
-+        modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS),             \
-+                                    MODS, ARRAY_SIZE(MODS));            \
-+    } while (0)
- /* CPWriteFn that can be used to implement writes-ignored behaviour */
- void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx.c
-+++ b/hw/arm/pxa2xx.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
-     { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
-       .access = PL1_RW, .type = ARM_CP_IO,
-       .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
--    REGINFO_SENTINEL
- };
- static void pxa2xx_setup_cp14(PXA2xxState *s)
-diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx_pic.c
-+++ b/hw/arm/pxa2xx_pic.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
-     REGINFO_FOR_PIC_CP("ICLR2", 8),
-     REGINFO_FOR_PIC_CP("ICFP2", 9),
-     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
--    REGINFO_SENTINEL
- };
- static const MemoryRegionOps pxa2xx_pic_ops = {
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
-       .readfn = icc_igrpen1_el3_read,
-       .writefn = icc_igrpen1_el3_write,
-     },
--    REGINFO_SENTINEL
- };
- static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = {
-       .readfn = ich_vmcr_read,
-       .writefn = ich_vmcr_write,
-     },
--    REGINFO_SENTINEL
- };
- static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
-       .readfn = ich_ap_read,
-       .writefn = ich_ap_write,
-     },
--    REGINFO_SENTINEL
- };
- static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
-       .readfn = ich_ap_read,
-       .writefn = ich_ap_write,
-     },
--    REGINFO_SENTINEL
- };
- static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
-@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
-                       .readfn = ich_lr_read,
-                       .writefn = ich_lr_write,
-                     },
--                    REGINFO_SENTINEL
-                 };
-                 define_arm_cp_regs(cpu, lr_regset);
-             }
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_kvm.c
-+++ b/hw/intc/arm_gicv3_kvm.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
-        */
-       .resetfn = arm_gicv3_icc_reset,
-     },
--    REGINFO_SENTINEL
- };
- /**
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     { .name = "L2MERRSR",
+         t = cpu->isar.id_aa64mmfr2;
-       .cp = 15, .opc1 = 3, .crm = 15,
+         t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
-       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+         t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
--    REGINFO_SENTINEL
++        t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
- };
+         cpu->isar.id_aa64mmfr2 = t;
- static void aarch64_a57_initfn(Object *obj)
+         /* Replicate the same data to the 32-bit id registers.  */
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void cortex_a8_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
        .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
      { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
        .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 -    REGINFO_SENTINEL
  };
  static void cortex_a9_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
  #endif
      { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void cortex_a7_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
        .access = PL1_RW, .type = ARM_CP_CONST },
      { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
        .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static void cortex_r5_initfn(Object *obj)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
        .secure = ARM_CP_SECSTATE_S,
        .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
        .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
      { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
        .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
        .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v6_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
       */
      { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
        .access = PL1_W, .type = ARM_CP_WFI },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v7_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
        .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
      { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
        .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
        .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
        .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
        .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
 -    REGINFO_SENTINEL
  };
  typedef struct pm_event {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
        .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
        .writefn = tlbimvaa_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo v7mp_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
      { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
        .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
        .writefn = tlbimvaa_is_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
        .writefn = pmovsset_write,
        .raw_writefn = raw_write },
 -    REGINFO_SENTINEL
  };
  static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
      { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
        .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
        .accessfn = teehbr_access, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo v6k_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
        .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
                               offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
        .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
      },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
        .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .readfn = gt_virt_cnt_read,
      },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
        .access = PL1_W, .accessfn = ats_access,
        .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
  #endif
 -    REGINFO_SENTINEL
  };
  /* Return basic MPU access permission bits.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
        .writefn = pmsav7_rgnr_write,
        .resetfn = arm_cp_reset_ignore },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
      { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
        .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
        .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
 -    REGINFO_SENTINEL
  };
  static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
        .access = PL1_RW, .accessfn = access_tvm_trvm,
        .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
        .resetvalue = 0, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo vmsa_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
        /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
                               offsetof(CPUARMState, cp15.tcr_el[1])} },
 -    REGINFO_SENTINEL
  };
  /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
      { .name = "C9", .cp = 15, .crn = 9,
        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
        .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
      { .name = "XSCALE_UNLOCK_DCACHE",
        .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
        .access = PL1_RW,
        .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
      { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
        .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
        .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
      { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
        .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
      { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
        .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
        .resetvalue = (1 << 30) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo strongarm_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
        .access = PL1_RW, .resetvalue = 0,
        .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
 -    REGINFO_SENTINEL
  };
  static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                               offsetof(CPUARMState, cp15.ttbr1_ns) },
        .writefn = vmsa_ttbr_write, },
 -    REGINFO_SENTINEL
  };
  static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
        .writefn = sdcr_write,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
 -    REGINFO_SENTINEL
  };
  /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
        .type = ARM_CP_CONST,
        .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
        .access = PL2_RW, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  /* Ditto, but for registers which exist in ARMv8 but not v7 */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
        .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
        .access = PL2_RW,
        .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
        .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
        .access = PL2_RW,
        .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
        .access = PL2_RW,
        .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
        .writefn = hcr_writehigh },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
        .access = PL2_RW, .accessfn = sel2_access,
        .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae3_write },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_tda,
        .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
        .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
      { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
        .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  /* Return the exception level to which exceptions should be taken
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
                .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
                .writefn = dbgbcr_write, .raw_writefn = raw_write
              },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, dbgregs);
      }
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
                .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
                .writefn = dbgwcr_write, .raw_writefn = raw_write
              },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, dbgregs);
      }
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
                .type = ARM_CP_IO,
                .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
                .raw_writefn = pmevtyper_rawwrite },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, pmev_regs);
          g_free(pmevcntr_name);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
                .resetvalue = extract64(cpu->pmceid1, 32, 32) },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, v81_pmu_regs);
      }
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
        .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
        .access = PL1_R, .accessfn = access_lor_ns,
        .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  #ifdef TARGET_AARCH64
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
        .access = PL1_RW, .accessfn = access_pauth,
        .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo tlbirange_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae3_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo tlbios_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae3is_write },
 -    REGINFO_SENTINEL
  };
  static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rndr_reginfo[] = {
        .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
        .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
        .access = PL0_R, .readfn = rndr_readfn },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
        .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo dcpodp_reg[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
        .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 -    REGINFO_SENTINEL
  };
  #endif /*CONFIG_USER_ONLY*/
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
      { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
      { .name = "TCO", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
        .type = ARM_CP_CONST, .access = PL0_RW, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
        .accessfn = aa64_zva_access,
  #endif
      },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
      { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
        .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
 -    REGINFO_SENTINEL
  };
  static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
        .access = PL1_R,
        .accessfn = access_aa64_tid2,
        .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
        .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
        .accessfn = access_joscr_jmcr,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo vhe_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
        .access = PL2_RW, .accessfn = e2h_access,
        .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
  #endif
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
        .writefn = ats_write64 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo ats1cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
        .writefn = ats_write },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
        .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
        .access = PL2_RW, .type = ARM_CP_CONST,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  void register_cp_regs_for_features(ARMCPU *cpu)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .type = ARM_CP_CONST,
                .accessfn = access_aa32_tid3,
                .resetvalue = cpu->isar.id_isar6 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, v6_idregs);
          define_arm_cp_regs(cpu, v6_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
                .resetvalue = cpu->pmceid1 },
 -            REGINFO_SENTINEL
          };
  #ifdef CONFIG_USER_ONLY
          ARMCPRegUserSpaceInfo v8_user_idregs[] = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .exported_bits = 0x000000f0ffffffff },
              { .name = "ID_AA64ISAR*_EL1_RESERVED",
                .is_glob = true                     },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(v8_idregs, v8_user_idregs);
  #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL2_RW,
                .resetvalue = vmpidr_def,
                .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, vpidr_regs);
          define_arm_cp_regs(cpu, el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                    .access = PL2_RW, .accessfn = access_el3_aa32ns,
                    .type = ARM_CP_NO_RAW,
                    .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
 -                REGINFO_SENTINEL
              };
              define_arm_cp_regs(cpu, vpidr_regs);
              define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .raw_writefn = raw_write, .writefn = sctlr_write,
                .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
                .resetvalue = cpu->reset_sctlr },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, el3_regs);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "DUMMY",
                .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
                .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
              { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R,
                .accessfn = access_aa64_tid1,
                .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
 -            REGINFO_SENTINEL
          };
          ARMCPRegInfo id_cp_reginfo[] = {
              /* These are common to v8 and pre-v8 */
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R,
                .accessfn = access_aa32_tid1,
                .type = ARM_CP_CONST, .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          /* TLBTR is specific to VMSA */
          ARMCPRegInfo id_tlbtr_reginfo = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "MIDR_EL1",
                .exported_bits = 0x00000000ffffffff },
              { .name = "REVIDR_EL1"                },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
  #endif
          if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
              arm_feature(env, ARM_FEATURE_STRONGARM)) {
 -            ARMCPRegInfo *r;
 +            size_t i;
              /* Register the blanket "writes ignored" value first to cover the
               * whole space. Then update the specific ID registers to allow write
               * access, so that they ignore writes rather than causing them to
               * UNDEF.
               */
              define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
 -            for (r = id_pre_v8_midr_cp_reginfo;
 -                 r->type != ARM_CP_SENTINEL; r++) {
 -                r->access = PL1_RW;
 +            for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) {
 +                id_pre_v8_midr_cp_reginfo[i].access = PL1_RW;
              }
 -            for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
 -                r->access = PL1_RW;
 +            for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) {
 +                id_cp_reginfo[i].access = PL1_RW;
              }
              id_mpuir_reginfo.access = PL1_RW;
              id_tlbtr_reginfo.access = PL1_RW;
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
                .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
                .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
 -            REGINFO_SENTINEL
          };
  #ifdef CONFIG_USER_ONLY
          ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
              { .name = "MPIDR_EL1",
                .fixed_bits = 0x0000000080000000 },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
  #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
                .access = PL3_RW, .type = ARM_CP_CONST,
                .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, auxcr_reginfo);
          if (cpu_isar_feature(aa32_ac2, cpu)) {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                    .type = ARM_CP_CONST,
                    .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
                    .access = PL1_R, .resetvalue = cpu->reset_cbar },
 -                REGINFO_SENTINEL
              };
              /* We don't implement a r/w 64 bit CBAR currently */
              assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                       offsetof(CPUARMState, cp15.vbar_ns) },
                .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, vbar_cp_reginfo);
      }
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                     r->writefn);
          }
      }
 -    /* Bad type field probably means missing sentinel at end of reg list */
 -    assert(cptype_valid(r->type));
 +
      for (crm = crmmin; crm <= crmmax; crm++) {
          for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
              for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      }
  }
 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 -                                    const ARMCPRegInfo *regs, void *opaque)
 +/* Define a whole list of registers */
 +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
 +                                        void *opaque, size_t len)
  {
 -    /* Define a whole list of registers */
 -    const ARMCPRegInfo *r;
 -    for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
 -        define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
 +    size_t i;
 +    for (i = 0; i < len; ++i) {
 +        define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque);
      }
  }
@@ -XXX,XX +XXX,XX @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
   * user-space cannot alter any values and dynamic values pertaining to
   * execution state are hidden from user space view anyway.
   */
 -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
 +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
 +                                 const ARMCPRegUserSpaceInfo *mods,
 +                                 size_t mods_len)
  {
 -    const ARMCPRegUserSpaceInfo *m;
 -    ARMCPRegInfo *r;
 -
 -    for (m = mods; m->name; m++) {
 +    for (size_t mi = 0; mi < mods_len; ++mi) {
 +        const ARMCPRegUserSpaceInfo *m = mods + mi;
          GPatternSpec *pat = NULL;
 +
          if (m->is_glob) {
              pat = g_pattern_spec_new(m->name);
          }
 -        for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
 +        for (size_t ri = 0; ri < regs_len; ++ri) {
 +            ARMCPRegInfo *r = regs + ri;
 +
              if (pat && g_pattern_match_string(pat, r->name)) {
                  r->type = ARM_CP_CONST;
                  r->access = PL0U_R;
 --
-.25.1
+.20.1

-[PULL 18/23] target/arm: Perform override check early in add_cpreg_to_hashtable
+[PULL 03/21] target/arm: fix typo in cpu.h ID_AA64PFR1 field name
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Leif Lindholm <leif@nuviainc.com>
-Perform the override check early, so that it is still done
+SBSS -> SSBS
 even when we decide to discard an unreachable cpreg.
-Use assert not printf+abort.
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-18-richard.henderson@linaro.org
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20210108185154.8108-2-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 22 ++++++++--------------
+ target/arm/cpu.h | 2 +-
-file changed, 8 insertions(+), 14 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/cpu.h
-+++ b/target/arm/helper.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
-         g_assert_not_reached();
+ FIELD(ID_AA64PFR0, SVE, 32, 4)
-     }
+ FIELD(ID_AA64PFR1, BT, 0, 4)
-+    /* Overriding of an existing definition must be explicitly requested. */
+-FIELD(ID_AA64PFR1, SBSS, 4, 4)
-+    if (!(r->type & ARM_CP_OVERRIDE)) {
++FIELD(ID_AA64PFR1, SSBS, 4, 4)
-+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
+ FIELD(ID_AA64PFR1, MTE, 8, 4)
-+        if (oldreg) {
+ FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
 +            assert(oldreg->type & ARM_CP_OVERRIDE);
 +        }
 +    }
 +
      /* Combine cpreg and name into one allocation. */
      name_len = strlen(name) + 1;
      r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          assert(!raw_accessors_invalid(r2));
      }
 -    /* Overriding of an existing definition must be explicitly
 -     * requested.
 -     */
 -    if (!(r->type & ARM_CP_OVERRIDE)) {
 -        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
 -        if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
 -            fprintf(stderr, "Register redefined: cp=%d %d bit "
 -                    "crn=%d crm=%d opc1=%d opc2=%d, "
 -                    "was %s, now %s\n", r2->cp, 32 + 32 * is64,
 -                    r2->crn, r2->crm, r2->opc1, r2->opc2,
 -                    oldreg->name, r2->name);
 -            g_assert_not_reached();
 -        }
 -    }
      g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
  }
 --
-.25.1
+.20.1

-[PULL 23/23] target/arm: read access to performance counters from EL0
+[PULL 04/21] target/arm: make ARMCPU.clidr 64-bit
-From: Alex Zuepke <alex.zuepke@tum.de>
+From: Leif Lindholm <leif@nuviainc.com>
-The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
+The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
-to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
+, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
-we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.
+Extend the clidr field to be able to hold this context.
-Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20210108185154.8108-3-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 4 ++--
+ target/arm/cpu.h | 2 +-
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/cpu.h
-+++ b/target/arm/helper.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
-               .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
+     uint32_t id_afr0;
-               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+     uint64_t id_aa64afr0;
-               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
+     uint64_t id_aa64afr1;
--              .accessfn = pmreg_access },
+-    uint32_t clidr;
-+              .accessfn = pmreg_access_xevcntr },
++    uint64_t clidr;
-             { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
+     uint64_t mp_affinity; /* MP ID without feature bits */
-               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
+     /* The elements of this array are the CCSIDR values for each cache,
--              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
 +              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
                .type = ARM_CP_IO,
                .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
                .raw_readfn = pmevcntr_rawread,
 --
-.25.1
+.20.1

-[PULL 22/23] target/arm: Add isar_feature_{aa64,any}_ras
+[PULL 05/21] target/arm: make ARMCPU.ctr 64-bit
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Leif Lindholm <leif@nuviainc.com>
-Add the aa64 predicate for detecting RAS support from id registers.
+When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
-We already have the aa32 version from the M-profile work.
+TminLine field in bits [37:32].
-Add the 'any' predicate for testing both aa64 and aa32.
+Extend the ctr field to be able to hold this context.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Hao Wu <wuhaotsh@google.com>
-Message-id: 20220501055028.646596-34-richard.henderson@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20210108185154.8108-4-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 10 ++++++++++
+ target/arm/cpu.h | 2 +-
-file changed, 10 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
+     uint64_t midr;
- }
+     uint32_t revidr;
+     uint32_t reset_fpsid;
-+static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
+-    uint32_t ctr;
-+{
++    uint64_t ctr;
-+    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
+     uint32_t reset_sctlr;
-+}
+     uint64_t pmceid0;
-+
+     uint64_t pmceid1;
  static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
  {
      return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
      return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
  }
 +static inline bool isar_feature_any_ras(const ARMISARegisters *id)
 +{
 +    return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
 +}
 +
  /*
   * Forward to the above feature tests given an ARMCPU pointer.
   */
 --
-.25.1
+.20.1

-[PULL 19/23] target/arm: Reformat comments in add_cpreg_to_hashtable
+[PULL 06/21] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Leif Lindholm <leif@nuviainc.com>
-Put the block comments into the current coding style.
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210108185154.8108-5-leif@nuviainc.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20220501055028.646596-19-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 24 +++++++++++++++---------
+ target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
-file changed, 15 insertions(+), 9 deletions(-)
+file changed, 31 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/cpu.h
-+++ b/target/arm/helper.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
-     return cpu_list;
+ /*
- }
+  * System register ID fields.
+  */
-+/*
++FIELD(CLIDR_EL1, CTYPE1, 0, 3)
-+ * Private utility function for define_one_arm_cp_reg_with_opaque():
++FIELD(CLIDR_EL1, CTYPE2, 3, 3)
-+ * add a single reginfo struct to the hash table.
++FIELD(CLIDR_EL1, CTYPE3, 6, 3)
-+ */
++FIELD(CLIDR_EL1, CTYPE4, 9, 3)
- static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++FIELD(CLIDR_EL1, CTYPE5, 12, 3)
-                                    void *opaque, CPState state,
++FIELD(CLIDR_EL1, CTYPE6, 15, 3)
-                                    CPSecureState secstate,
++FIELD(CLIDR_EL1, CTYPE7, 18, 3)
-                                    int crm, int opc1, int opc2,
++FIELD(CLIDR_EL1, LOUIS, 21, 3)
-                                    const char *name)
++FIELD(CLIDR_EL1, LOC, 24, 3)
- {
++FIELD(CLIDR_EL1, LOUU, 27, 3)
--    /* Private utility function for define_one_arm_cp_reg_with_opaque():
++FIELD(CLIDR_EL1, ICB, 30, 3)
--     * add a single reginfo struct to the hash table.
++
--     */
++/* When FEAT_CCIDX is implemented */
-     uint32_t key;
++FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
-     ARMCPRegInfo *r2;
++FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
-     bool is64 = r->type & ARM_CP_64BIT;
++FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++
++/* When FEAT_CCIDX is not implemented */
-     isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
++FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
-     if (isbanked) {
++FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
--        /* Register is banked (using both entries in array).
++FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
-+        /*
++
-+         * Register is banked (using both entries in array).
++FIELD(CTR_EL0,  IMINLINE, 0, 4)
-          * Overwriting fieldoffset as the array is only used to define
++FIELD(CTR_EL0,  L1IP, 14, 2)
-          * banked registers but later only fieldoffset is used.
++FIELD(CTR_EL0,  DMINLINE, 16, 4)
-          */
++FIELD(CTR_EL0,  ERG, 20, 4)
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++FIELD(CTR_EL0,  CWG, 24, 4)
++FIELD(CTR_EL0,  IDC, 28, 1)
-     if (state == ARM_CP_STATE_AA32) {
++FIELD(CTR_EL0,  DIC, 29, 1)
-         if (isbanked) {
++FIELD(CTR_EL0,  TMINLINE, 32, 6)
--            /* If the register is banked then we don't need to migrate or
++
-+            /*
+ FIELD(MIDR_EL1, REVISION, 0, 4)
-+             * If the register is banked then we don't need to migrate or
+ FIELD(MIDR_EL1, PARTNUM, 4, 12)
-              * reset the 32-bit instance in certain cases:
+ FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
               *
               * 1) If the register has both 32-bit and 64-bit instances then we
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                  r2->type |= ARM_CP_ALIAS;
              }
          } else if ((secstate != r->secure) && !ns) {
 -            /* The register is not banked so we only want to allow migration of
 -             * the non-secure instance.
 +            /*
 +             * The register is not banked so we only want to allow migration
 +             * of the non-secure instance.
               */
              r2->type |= ARM_CP_ALIAS;
          }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          }
      }
 -    /* By convention, for wildcarded registers only the first
 +    /*
 +     * By convention, for wildcarded registers only the first
       * entry is used for migration; the others are marked as
       * ALIAS so we don't try to transfer the register
       * multiple times. Special registers (ie NOP/WFI) are
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
      }
 -    /* Check that raw accesses are either forbidden or handled. Note that
 +    /*
 +     * Check that raw accesses are either forbidden or handled. Note that
       * we can't assert this earlier because the setup of fieldoffset for
       * banked registers has to be done first.
       */
 --
-.25.1
+.20.1

-[PULL 21/23] target/arm: Add isar predicates for FEAT_Debugv8p2
+[PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Leif Lindholm <leif@nuviainc.com>
+Add entries present in ARM DDI 0487F.c (August 2020).
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
-Message-id: 20220501055028.646596-24-richard.henderson@linaro.org
+Message-id: 20210108185154.8108-6-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h | 15 +++++++++++++++
 file changed, 15 insertions(+)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
-     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
+ FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
- }
+ FIELD(ID_AA64ISAR1, SB, 36, 4)
+ FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
-+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
++FIELD(ID_AA64ISAR1, BF16, 44, 4)
-+{
++FIELD(ID_AA64ISAR1, DGH, 48, 4)
-+    return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
++FIELD(ID_AA64ISAR1, I8MM, 52, 4)
-+}
-+
+ FIELD(ID_AA64PFR0, EL0, 0, 4)
- /*
+ FIELD(ID_AA64PFR0, EL1, 4, 4)
-  * 64-bit feature tests via id registers.
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
-  */
+ FIELD(ID_AA64PFR0, GIC, 24, 4)
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
+ FIELD(ID_AA64PFR0, RAS, 28, 4)
-     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
+ FIELD(ID_AA64PFR0, SVE, 32, 4)
- }
++FIELD(ID_AA64PFR0, SEL2, 36, 4)
++FIELD(ID_AA64PFR0, MPAM, 40, 4)
-+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
++FIELD(ID_AA64PFR0, AMU, 44, 4)
-+{
++FIELD(ID_AA64PFR0, DIT, 48, 4)
-+    return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
++FIELD(ID_AA64PFR0, CSV2, 56, 4)
-+}
++FIELD(ID_AA64PFR0, CSV3, 60, 4)
-+
- static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
+ FIELD(ID_AA64PFR1, BT, 0, 4)
- {
+ FIELD(ID_AA64PFR1, SSBS, 4, 4)
-     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
+ FIELD(ID_AA64PFR1, MTE, 8, 4)
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
+ FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
-     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
++FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
- }
+ FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
-+static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
+ FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
-+{
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
-+    return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
+ FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
-+}
+ FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
-+
+ FIELD(ID_AA64MMFR0, EXS, 44, 4)
- /*
++FIELD(ID_AA64MMFR0, FGT, 56, 4)
-  * Forward to the above feature tests given an ARMCPU pointer.
++FIELD(ID_AA64MMFR0, ECV, 60, 4)
-  */
  FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
  FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
  FIELD(ID_AA64MMFR1, PAN, 20, 4)
  FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
  FIELD(ID_AA64MMFR1, XNX, 28, 4)
 +FIELD(ID_AA64MMFR1, TWED, 32, 4)
 +FIELD(ID_AA64MMFR1, ETS, 36, 4)
  FIELD(ID_AA64MMFR2, CNP, 0, 4)
  FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
  FIELD(ID_AA64DFR0, PMSVER, 32, 4)
  FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
  FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
 +FIELD(ID_AA64DFR0, MTPMU, 48, 4)
  FIELD(ID_DFR0, COPDBG, 0, 4)
  FIELD(ID_DFR0, COPSDBG, 4, 4)
 --
-.25.1
+.20.1

-[PULL 17/23] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
+[PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Leif Lindholm <leif@nuviainc.com>
-Computing isbanked only once makes the code
+Add entries present in ARM DDI 0487F.c (August 2020).
 a bit easier to read.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-17-richard.henderson@linaro.org
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20210108185154.8108-7-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 6 ++++--
+ target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
-file changed, 4 insertions(+), 2 deletions(-)
+file changed, 28 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/cpu.h
-+++ b/target/arm/helper.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
-     bool is64 = r->type & ARM_CP_64BIT;
+ FIELD(ID_ISAR6, FHM, 8, 4)
-     bool ns = secstate & ARM_CP_SECSTATE_NS;
+ FIELD(ID_ISAR6, SB, 12, 4)
-     int cp = r->cp;
+ FIELD(ID_ISAR6, SPECRES, 16, 4)
-+    bool isbanked;
++FIELD(ID_ISAR6, BF16, 20, 4)
-     size_t name_len;
++FIELD(ID_ISAR6, I8MM, 24, 4)
-     switch (state) {
+ FIELD(ID_MMFR0, VMSA, 0, 4)
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+ FIELD(ID_MMFR0, PMSA, 4, 4)
-         r2->opaque = opaque;
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
-     }
+ FIELD(ID_MMFR0, FCSE, 24, 4)
+ FIELD(ID_MMFR0, INNERSHR, 28, 4)
--    if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
-+    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
++FIELD(ID_MMFR1, L1HVDVA, 0, 4)
-+    if (isbanked) {
++FIELD(ID_MMFR1, L1UNIVA, 4, 4)
-         /* Register is banked (using both entries in array).
++FIELD(ID_MMFR1, L1HVDSW, 8, 4)
-          * Overwriting fieldoffset as the array is only used to define
++FIELD(ID_MMFR1, L1UNISW, 12, 4)
-          * banked registers but later only fieldoffset is used.
++FIELD(ID_MMFR1, L1HVD, 16, 4)
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++FIELD(ID_MMFR1, L1UNI, 20, 4)
-     }
++FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
++FIELD(ID_MMFR1, BPRED, 28, 4)
-     if (state == ARM_CP_STATE_AA32) {
++
--        if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
++FIELD(ID_MMFR2, L1HVDFG, 0, 4)
-+        if (isbanked) {
++FIELD(ID_MMFR2, L1HVDBG, 4, 4)
-             /* If the register is banked then we don't need to migrate or
++FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
-              * reset the 32-bit instance in certain cases:
++FIELD(ID_MMFR2, HVDTLB, 12, 4)
-              *
++FIELD(ID_MMFR2, UNITLB, 16, 4)
 +FIELD(ID_MMFR2, MEMBARR, 20, 4)
 +FIELD(ID_MMFR2, WFISTALL, 24, 4)
 +FIELD(ID_MMFR2, HWACCFLG, 28, 4)
 +
  FIELD(ID_MMFR3, CMAINTVA, 0, 4)
  FIELD(ID_MMFR3, CMAINTSW, 4, 4)
  FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
  FIELD(ID_MMFR4, CCIDX, 24, 4)
  FIELD(ID_MMFR4, EVT, 28, 4)
 +FIELD(ID_MMFR5, ETS, 0, 4)
 +
  FIELD(ID_PFR0, STATE0, 0, 4)
  FIELD(ID_PFR0, STATE1, 4, 4)
  FIELD(ID_PFR0, STATE2, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
  FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
  FIELD(ID_PFR1, GIC, 28, 4)
 +FIELD(ID_PFR2, CSV3, 0, 4)
 +FIELD(ID_PFR2, SSBS, 4, 4)
 +FIELD(ID_PFR2, RAS_FRAC, 8, 4)
 +
  FIELD(ID_AA64ISAR0, AES, 4, 4)
  FIELD(ID_AA64ISAR0, SHA1, 8, 4)
  FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
  FIELD(ID_DFR0, PERFMON, 24, 4)
  FIELD(ID_DFR0, TRACEFILT, 28, 4)
 +FIELD(ID_DFR1, MTPMU, 0, 4)
 +
  FIELD(DBGDIDR, SE_IMP, 12, 1)
  FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
  FIELD(DBGDIDR, VERSION, 16, 4)
 --
-.25.1
+.20.1

-[PULL 16/23] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
+[PULL 09/21] ui/cocoa: Update path to docs in build tree
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Roman Bolshakov <r.bolshakov@yadro.com>
-Bool is a more appropriate type for these variables.
+QEMU documentation can't be opened if QEMU is run from build tree
 because executables are placed in the top of build tree after conversion
 to meson.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
 Reported-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-16-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 4 ++--
+ ui/cocoa.m | 2 +-
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/ui/cocoa.m b/ui/cocoa.m
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/ui/cocoa.m
-+++ b/target/arm/helper.c
++++ b/ui/cocoa.m
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
-      */
+ - (void) openDocumentation: (NSString *) filename
-     uint32_t key;
+ {
-     ARMCPRegInfo *r2;
+     /* Where to look for local files */
--    int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
+-    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
--    int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
++    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
-+    bool is64 = r->type & ARM_CP_64BIT;
+     NSString *full_file_path;
-+    bool ns = secstate & ARM_CP_SECSTATE_NS;
-     int cp = r->cp;
+     /* iterate thru the possible paths until the file is found */
      size_t name_len;
 --
-.25.1
+.20.1

-[PULL 15/23] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
+[PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build
-From: Richard Henderson <richard.henderson@linaro.org>
+In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
 At the moment new manpages have to be listed both in the conf.py for
 Sphinx and also in docs/meson.build for Meson. We forgot the second
 of those -- correct the omission.
-Put most of the value writeback to the same place,
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-and improve the comment that goes with them.
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
 ---
  docs/meson.build | 1 +
 file changed, 1 insertion(+)
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+diff --git a/docs/meson.build b/docs/meson.build
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+index XXXXXXX..XXXXXXX 100644
-Message-id: 20220501055028.646596-15-richard.henderson@linaro.org
+--- a/docs/meson.build
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
++++ b/docs/meson.build
----
+@@ -XXX,XX +XXX,XX @@ if build_docs
- target/arm/helper.c | 28 ++++++++++++----------------
+         'qemu-img.1': (have_tools ? 'man1' : ''),
-file changed, 12 insertions(+), 16 deletions(-)
+         'qemu-nbd.8': (have_tools ? 'man8' : ''),
          'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
 +        'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
          'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
          'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
          'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
 --
 .20.1
-diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      *r2 = *r;
      r2->name = memcpy(r2 + 1, name, name_len);
 -    /* Reset the secure state to the specific incoming state.  This is
 -     * necessary as the register may have been defined with both states.
 +    /*
 +     * Update fields to match the instantiation, overwiting wildcards
 +     * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
       */
 +    r2->cp = cp;
 +    r2->crm = crm;
 +    r2->opc1 = opc1;
 +    r2->opc2 = opc2;
 +    r2->state = state;
      r2->secure = secstate;
 +    if (opaque) {
 +        r2->opaque = opaque;
 +    }
      if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
          /* Register is banked (using both entries in array).
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
  #endif
          }
      }
 -    if (opaque) {
 -        r2->opaque = opaque;
 -    }
 -    /* reginfo passed to helpers is correct for the actual access,
 -     * and is never ARM_CP_STATE_BOTH:
 -     */
 -    r2->state = state;
 -    /* Make sure reginfo passed to helpers for wildcarded regs
 -     * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
 -     */
 -    r2->cp = cp;
 -    r2->crm = crm;
 -    r2->opc1 = opc1;
 -    r2->opc2 = opc2;
 +
      /* By convention, for wildcarded registers only the first
       * entry is used for migration; the others are marked as
       * ALIAS so we don't try to transfer the register
 --
 .25.1

-[PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashtable
+[PULL 11/21] docs: Build and install all the docs in a single manual
-From: Richard Henderson <richard.henderson@linaro.org>
+When we first converted our documentation to Sphinx, we split it into
+multiple manuals (system, interop, tools, etc), which are all built
-Move the computation of key to the top of the function.
+separately.  The primary driver for this was wanting to be able to
-Hoist the resolution of cp as well, as an input to the
+avoid shipping the 'devel' manual to end-users.  However, this is
-computation of key.
+working against the grain of the way Sphinx wants to be used and
+causes some annoyances:
-This will be required by a subsequent patch.
+ * Cross-references between documents become much harder or
+   possibly impossible
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+ * There is no single index to the whole documentation
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+ * Within one manual there's no links or table-of-contents info
-Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
+   that lets you easily navigate to the others
  * The devel manual doesn't get published on the QEMU website
    (it would be nice to able to refer to it there)
 Merely hiding our developer documentation from end users seems like
 it's not enough benefit for these costs.  Combine all the
 documentation into a single manual (the same way that the readthedocs
 site builds it) and install the whole thing.  The previous manual
 divisions remain as the new top level sections in the manual.
  * The per-manual conf.py files are no longer needed
  * The man_pages[] specifications previously in each per-manual
    conf.py move to the top level conf.py
  * docs/meson.build logic is simplified as we now only need to run
    Sphinx once for the HTML and then once for the manpages5B
  * The old index.html.in that produced the top-level page with
    links to each manual is no longer needed
 Unfortunately this means that we now have to build the HTML
 documentation into docs/manual in the build tree rather than directly
 into docs/; otherwise it is too awkward to ensure we install only the
 built manual and not also the dependency info, stamp file, etc.  The
 manual still ends up in the same place in the final installed
 directory, but anybody who was consulting documentation from within
 the build tree will have to adjust where they're looking.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
+Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 49 +++++++++++++++++++++++++--------------------
+ docs/conf.py         | 46 ++++++++++++++++++++++++++++++-
-file changed, 27 insertions(+), 22 deletions(-)
+ docs/devel/conf.py   | 15 -----------
+ docs/index.html.in   | 17 ------------
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+ docs/interop/conf.py | 28 -------------------
  docs/meson.build     | 64 +++++++++++++++++---------------------------
  docs/specs/conf.py   | 16 -----------
  docs/system/conf.py  | 28 -------------------
  docs/tools/conf.py   | 37 -------------------------
  docs/user/conf.py    | 15 -----------
 files changed, 70 insertions(+), 196 deletions(-)
  delete mode 100644 docs/devel/conf.py
  delete mode 100644 docs/index.html.in
  delete mode 100644 docs/interop/conf.py
  delete mode 100644 docs/specs/conf.py
  delete mode 100644 docs/system/conf.py
  delete mode 100644 docs/tools/conf.py
  delete mode 100644 docs/user/conf.py
 diff --git a/docs/conf.py b/docs/conf.py
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/docs/conf.py
-+++ b/target/arm/helper.c
++++ b/docs/conf.py
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ latex_documents = [
-     ARMCPRegInfo *r2;
-     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
+ # -- Options for manual page output ---------------------------------------
-     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+ # Individual manual/conf.py can override this to create man pages
-+    int cp = r->cp;
+-man_pages = []
-     size_t name_len;
++man_pages = [
++    ('interop/qemu-ga', 'qemu-ga',
-+    switch (state) {
++     'QEMU Guest Agent',
-+    case ARM_CP_STATE_AA32:
++     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
-+        /* We assume it is a cp15 register if the .cp field is left unset. */
++    ('interop/qemu-ga-ref', 'qemu-ga-ref',
-+        if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
++     'QEMU Guest Agent Protocol Reference',
-+            cp = 15;
++     [], 7),
-+        }
++    ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
-+        key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
++     'QEMU QMP Reference Manual',
-+        break;
++     [], 7),
-+    case ARM_CP_STATE_AA64:
++    ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
-+        /*
++     'QEMU Storage Daemon QMP Reference Manual',
-+         * To allow abbreviation of ARMCPRegInfo definitions, we treat
++     [], 7),
-+         * cp == 0 as equivalent to the value for "standard guest-visible
++    ('system/qemu-manpage', 'qemu',
-+         * sysreg".  STATE_BOTH definitions are also always "standard sysreg"
++     'QEMU User Documentation',
-+         * in their AArch64 view (the .cp value may be non-zero for the
++     ['Fabrice Bellard'], 1),
-+         * benefit of the AArch32 view).
++    ('system/qemu-block-drivers', 'qemu-block-drivers',
-+         */
++     'QEMU block drivers reference',
-+        if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
++     ['Fabrice Bellard and the QEMU Project developers'], 7),
-+            cp = CP_REG_ARM64_SYSREG_CP;
++    ('system/qemu-cpu-models', 'qemu-cpu-models',
-+        }
++     'QEMU CPU Models',
-+        key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
++     ['The QEMU Project developers'], 7),
-+        break;
++    ('tools/qemu-img', 'qemu-img',
-+    default:
++     'QEMU disk image utility',
-+        g_assert_not_reached();
++     ['Fabrice Bellard'], 1),
-+    }
++    ('tools/qemu-nbd', 'qemu-nbd',
 +     'QEMU Disk Network Block Device Server',
 +     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
 +    ('tools/qemu-pr-helper', 'qemu-pr-helper',
 +     'QEMU persistent reservation helper',
 +     [], 8),
 +    ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
 +     'QEMU storage daemon',
 +     [], 1),
 +    ('tools/qemu-trace-stap', 'qemu-trace-stap',
 +     'QEMU SystemTap trace tool',
 +     [], 1),
 +    ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
 +     'QEMU 9p virtfs proxy filesystem helper',
 +     ['M. Mohan Kumar'], 1),
 +    ('tools/virtiofsd', 'virtiofsd',
 +     'QEMU virtio-fs shared file system daemon',
 +     ['Stefan Hajnoczi <stefanha@redhat.com>',
 +      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
 +]
  # -- Options for Texinfo output -------------------------------------------
 diff --git a/docs/devel/conf.py b/docs/devel/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/devel/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'devel' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'Developer''s Guide'
 diff --git a/docs/index.html.in b/docs/index.html.in
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/index.html.in
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -<!DOCTYPE html>
 -<html lang="en">
 -    <head>
 -        <meta charset="UTF-8">
 -        <title>QEMU @VERSION@ Documentation</title>
 -    </head>
 -    <body>
 -        <h1>QEMU @VERSION@ Documentation</h1>
 -        <ul>
 -            <li><a href="system/index.html">System Emulation User's Guide</a></li>
 -            <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
 -            <li><a href="tools/index.html">Tools Guide</a></li>
 -            <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
 -            <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
 -        </ul>
 -    </body>
 -</html>
 diff --git a/docs/interop/conf.py b/docs/interop/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/interop/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'interop' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
 -     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
 -    ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
 -     [], 7),
 -    ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
 -     [], 7),
 -    ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
 -     'QEMU Storage Daemon QMP Reference Manual', [], 7),
 -]
 diff --git a/docs/meson.build b/docs/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/meson.build
 +++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
                            meson.source_root() / 'docs/sphinx/qmp_lexer.py',
                            qapi_gen_depends ]
 -  configure_file(output: 'index.html',
 -                 input: files('index.html.in'),
 -                 configuration: {'VERSION': meson.project_version()},
 -                 install_dir: qemu_docdir)
 -  manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
    man_pages = {
 -    'interop' : {
          'qemu-ga.8': (have_tools ? 'man8' : ''),
          'qemu-ga-ref.7': 'man7',
          'qemu-qmp-ref.7': 'man7',
          'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
 -    },
 -    'tools': {
          'qemu-img.1': (have_tools ? 'man1' : ''),
          'qemu-nbd.8': (have_tools ? 'man8' : ''),
          'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
@@ -XXX,XX +XXX,XX @@ if build_docs
          'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
          'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
          'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
 -    },
 -    'system': {
          'qemu.1': 'man1',
          'qemu-block-drivers.7': 'man7',
          'qemu-cpu-models.7': 'man7'
 -    },
    }
    sphinxdocs = []
    sphinxmans = []
 -  foreach manual : manuals
 -    private_dir = meson.current_build_dir() / (manual + '.p')
 -    output_dir = meson.current_build_dir() / manual
 -    input_dir = meson.current_source_dir() / manual
 -    this_manual = custom_target(manual + ' manual',
 +  private_dir = meson.current_build_dir() / 'manual.p'
 +  output_dir = meson.current_build_dir() / 'manual'
 +  input_dir = meson.current_source_dir()
 +
-     /* Combine cpreg and name into one allocation. */
++  this_manual = custom_target('QEMU manual',
-     name_len = strlen(name) + 1;
+                 build_by_default: build_docs,
-     r2 = g_malloc(sizeof(*r2) + name_len);
+-                output: [manual + '.stamp'],
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+-                input: [files('conf.py'), files(manual / 'conf.py')],
-         }
+-                depfile: manual + '.d',
++                output: 'docs.stamp',
-         if (r->state == ARM_CP_STATE_BOTH) {
++                input: files('conf.py'),
--            /* We assume it is a cp15 register if the .cp field is left unset.
++                depfile: 'docs.d',
--             */
+                 depend_files: sphinx_extn_depends,
--            if (r2->cp == 0) {
+                 command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
--                r2->cp = 15;
+                           '-Ddepfile_stamp=@OUTPUT0@',
--            }
+                           '-b', 'html', '-d', private_dir,
--
+                           input_dir, output_dir])
- #if HOST_BIG_ENDIAN
+-    sphinxdocs += this_manual
-             if (r2->fieldoffset) {
+-    if build_docs and manual != 'devel'
-                 r2->fieldoffset += sizeof(uint32_t);
+-      install_subdir(output_dir, install_dir: qemu_docdir)
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+-    endif
- #endif
++  sphinxdocs += this_manual
-         }
++  install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
-     }
--    if (state == ARM_CP_STATE_AA64) {
+-    these_man_pages = []
--        /* To allow abbreviation of ARMCPRegInfo
+-    install_dirs = []
--         * definitions, we treat cp == 0 as equivalent to
+-    foreach page, section : man_pages.get(manual, {})
--         * the value for "standard guest-visible sysreg".
+-      these_man_pages += page
--         * STATE_BOTH definitions are also always "standard
+-      install_dirs += section == '' ? false : get_option('mandir') / section
--         * sysreg" in their AArch64 view (the .cp value may
+-    endforeach
--         * be non-zero for the benefit of the AArch32 view).
+-    if these_man_pages.length() > 0
--         */
+-      sphinxmans += custom_target(manual + ' man pages',
--        if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+-                         build_by_default: build_docs,
--            r2->cp = CP_REG_ARM64_SYSREG_CP;
+-                         output: these_man_pages,
--        }
+-                         input: this_manual,
--        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
+-                         install: build_docs,
--                                 r2->opc0, opc1, opc2);
+-                         install_dir: install_dirs,
--    } else {
+-                         command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
--        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
+-                                   input_dir, meson.current_build_dir()])
--    }
+-    endif
-     if (opaque) {
++  these_man_pages = []
-         r2->opaque = opaque;
++  install_dirs = []
-     }
++  foreach page, section : man_pages
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++    these_man_pages += page
-     /* Make sure reginfo passed to helpers for wildcarded regs
++    install_dirs += section == '' ? false : get_option('mandir') / section
-      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
+   endforeach
-      */
++
-+    r2->cp = cp;
++  sphinxmans += custom_target('QEMU man pages',
-     r2->crm = crm;
++                              build_by_default: build_docs,
-     r2->opc1 = opc1;
++                              output: these_man_pages,
-     r2->opc2 = opc2;
++                              input: this_manual,
 +                              install: build_docs,
 +                              install_dir: install_dirs,
 +                              command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
 +                                        input_dir, meson.current_build_dir()])
 +
    alias_target('sphinxdocs', sphinxdocs)
    alias_target('html', sphinxdocs)
    alias_target('man', sphinxmans)
 diff --git a/docs/specs/conf.py b/docs/specs/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/specs/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'specs' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = \
 -    u'System Emulation Guest Hardware Specifications'
 diff --git a/docs/system/conf.py b/docs/system/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/system/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'system' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'System Emulation User''s Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-manpage', 'qemu', u'QEMU User Documentation',
 -     ['Fabrice Bellard'], 1),
 -    ('qemu-block-drivers', 'qemu-block-drivers',
 -     u'QEMU block drivers reference',
 -     ['Fabrice Bellard and the QEMU Project developers'], 7),
 -    ('qemu-cpu-models', 'qemu-cpu-models',
 -     u'QEMU CPU Models',
 -     ['The QEMU Project developers'], 7)
 -]
 diff --git a/docs/tools/conf.py b/docs/tools/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/tools/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'tools' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = \
 -    u'Tools Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-img', 'qemu-img', u'QEMU disk image utility',
 -     ['Fabrice Bellard'], 1),
 -    ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
 -     [], 1),
 -    ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
 -     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
 -    ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
 -     [], 8),
 -    ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
 -     [], 1),
 -    ('virtfs-proxy-helper', 'virtfs-proxy-helper',
 -     u'QEMU 9p virtfs proxy filesystem helper',
 -     ['M. Mohan Kumar'], 1),
 -    ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
 -     ['Stefan Hajnoczi <stefanha@redhat.com>',
 -      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
 -]
 diff --git a/docs/user/conf.py b/docs/user/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/user/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'user' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'User Mode Emulation User''s Guide'
 --
-.25.1
+.20.1

-[PULL 07/23] target/arm: Avoid bare abort() or assert(0)
+[PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
-From: Richard Henderson <richard.henderson@linaro.org>
+In commit cd8be50e58f63413c0 we converted the A32 coprocessor
 insns to decodetree. This accidentally broke XScale/iWMMXt insns,
 because it moved the handling of "cp insns which are handled
 by looking up the cp register in the hashtable" from after the
 call to the legacy disas_xscale_insn() decode to before it,
 with the result that all XScale/iWMMXt insns now UNDEF.
-Standardize on g_assert_not_reached() for "should not happen".
+Update valid_cp() so that it knows that on XScale cp 0 and 1
-Retain abort() when preceeded by fprintf or error_report.
+are not standard coprocessor instructions; this will cause
 the decodetree trans_ functions to ignore them, so that
 execution will correctly get through to the legacy decode again.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Cc: qemu-stable@nongnu.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reported-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 20220501055028.646596-7-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Guenter Roeck <linux@roeck-us.net>
+Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
 ---
- target/arm/helper.c         | 7 +++----
+ target/arm/translate.c | 7 +++++++
- target/arm/hvf/hvf.c        | 2 +-
+file changed, 7 insertions(+)
  target/arm/kvm-stub.c       | 4 ++--
  target/arm/kvm.c            | 4 ++--
  target/arm/machine.c        | 4 ++--
  target/arm/translate-a64.c  | 4 ++--
  target/arm/translate-neon.c | 2 +-
  target/arm/translate.c      | 4 ++--
 files changed, 15 insertions(+), 16 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-             break;
-         default:
-             /* broken reginfo with out-of-range opc1 */
--            assert(false);
--            break;
-+            g_assert_not_reached();
-         }
-         /* assert our permissions are not too lax (stricter is fine) */
-         assert((r->access & ~mask) == 0);
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
-             break;
-         default:
-             /* Never happens, but compiler isn't smart enough to tell.  */
--            abort();
-+            g_assert_not_reached();
-         }
-     }
-     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
-             break;
-         default:
-             /* Never happens, but compiler isn't smart enough to tell.  */
--            abort();
-+            g_assert_not_reached();
-         }
-     }
-     if (domain_prot == 3) {
-diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/hvf/hvf.c
-+++ b/target/arm/hvf/hvf.c
-@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
-         /* we got kicked, no exit to process */
-         return 0;
-     default:
--        assert(0);
-+        g_assert_not_reached();
-     }
-     hvf_sync_vtimer(cpu);
-diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm-stub.c
-+++ b/target/arm/kvm-stub.c
-@@ -XXX,XX +XXX,XX @@
- bool write_kvmstate_to_list(ARMCPU *cpu)
- {
--    abort();
-+    g_assert_not_reached();
- }
- bool write_list_to_kvmstate(ARMCPU *cpu, int level)
- {
--    abort();
-+    g_assert_not_reached();
- }
-diff --git a/target/arm/kvm.c b/target/arm/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm.c
-+++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
-             ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
-             break;
-         default:
--            abort();
-+            g_assert_not_reached();
-         }
-         if (ret) {
-             ok = false;
-@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
-             r.addr = (uintptr_t)(cpu->cpreg_values + i);
-             break;
-         default:
--            abort();
-+            g_assert_not_reached();
-         }
-         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
-         if (ret) {
-diff --git a/target/arm/machine.c b/target/arm/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/machine.c
-+++ b/target/arm/machine.c
-@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
-     if (kvm_enabled()) {
-         if (!write_kvmstate_to_list(cpu)) {
-             /* This should never fail */
--            abort();
-+            g_assert_not_reached();
-         }
-         /*
-@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
-     } else {
-         if (!write_cpustate_to_list(cpu, false)) {
-             /* This should never fail. */
--            abort();
-+            g_assert_not_reached();
-         }
-     }
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
-         gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
-         break;
-     default:
--        abort();
-+        g_assert_not_reached();
-     }
-     write_fp_sreg(s, rd, tcg_res);
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
-         break;
-     }
-     default:
--        abort();
-+        g_assert_not_reached();
-     }
- }
-diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c
-+++ b/target/arm/translate-neon.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
-         }
-         break;
-     default:
--        abort();
-+        g_assert_not_reached();
-     }
-     if ((vd + a->stride * (nregs - 1)) > 31) {
-         /*
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
+@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
-         offset = 4;
+      * only cp14 and cp15 are valid, and other values aren't considered
-         break;
+      * to be in the coprocessor-instruction space at all. v8M still
-     default:
+      * permits coprocessors 0..7.
--        abort();
++     * For XScale, we must not decode the XScale cp0, cp1 space as
-+        g_assert_not_reached();
++     * a standard coprocessor insn, because we want to fall through to
-     }
++     * the legacy disas_xscale_insn() decoder after decodetree is done.
-     tcg_gen_addi_i32(addr, addr, offset);
+      */
-     tmp = load_reg(s, 14);
++    if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
-@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
++        return false;
-             offset = 0;
++    }
-             break;
++
-         default:
+     if (arm_dc_feature(s, ARM_FEATURE_V8) &&
--            abort();
+         !arm_dc_feature(s, ARM_FEATURE_M)) {
-+            g_assert_not_reached();
+         return cp >= 14;
          }
          tcg_gen_addi_i32(addr, addr, offset);
          gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
 --
-.25.1
+.20.1

-[PULL 05/23] target/arm: Make some more cpreg data static const
+[PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value
-From: Richard Henderson <richard.henderson@linaro.org>
+A copy-and-paste error meant that the return value for register offset 0x44
 (the RX Status FIFO PEEK register) returned a byte from a bogus offset in
 the rx status FIFO. Fix the typo.
-These particular data structures are not modified at runtime.
+Cc: qemu-stable@nongnu.org
 Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
 ---
  hw/net/lan9118.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220501055028.646596-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.c | 16 ++++++++--------
 file changed, 8 insertions(+), 8 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/net/lan9118.c
-+++ b/target/arm/helper.c
++++ b/hw/net/lan9118.c
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
-               .resetvalue = cpu->pmceid1 },
+     case 0x40:
-         };
+         return rx_status_fifo_pop(s);
- #ifdef CONFIG_USER_ONLY
+     case 0x44:
--        ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+-        return s->rx_status_fifo[s->tx_status_fifo_head];
-+        static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
++        return s->rx_status_fifo[s->rx_status_fifo_head];
-             { .name = "ID_AA64PFR0_EL1",
+     case 0x48:
-               .exported_bits = 0x000f000f00ff0000,
+         return tx_status_fifo_pop(s);
-               .fixed_bits    = 0x0000000000000011 },
+     case 0x4c:
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
       */
      if (arm_feature(env, ARM_FEATURE_EL3)) {
          if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 -            ARMCPRegInfo nsacr = {
 +            static const ARMCPRegInfo nsacr = {
                  .name = "NSACR", .type = ARM_CP_CONST,
                  .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                  .access = PL1_RW, .accessfn = nsacr_access,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              };
              define_one_arm_cp_reg(cpu, &nsacr);
          } else {
 -            ARMCPRegInfo nsacr = {
 +            static const ARMCPRegInfo nsacr = {
                  .name = "NSACR",
                  .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                  .access = PL3_RW | PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          }
      } else {
          if (arm_feature(env, ARM_FEATURE_V8)) {
 -            ARMCPRegInfo nsacr = {
 +            static const ARMCPRegInfo nsacr = {
                  .name = "NSACR", .type = ARM_CP_CONST,
                  .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                  .access = PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .type = ARM_CP_CONST,
                .resetvalue = cpu->pmsav7_dregion << 8
          };
 -        ARMCPRegInfo crn0_wi_reginfo = {
 +        static const ARMCPRegInfo crn0_wi_reginfo = {
              .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
              .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
              .type = ARM_CP_NOP | ARM_CP_OVERRIDE
          };
  #ifdef CONFIG_USER_ONLY
 -        ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
 +        static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
              { .name = "MIDR_EL1",
                .exported_bits = 0x00000000ffffffff },
              { .name = "REVIDR_EL1"                },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
          };
  #ifdef CONFIG_USER_ONLY
 -        ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
 +        static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
              { .name = "MPIDR_EL1",
                .fixed_bits = 0x0000000080000000 },
          };
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      }
      if (arm_feature(env, ARM_FEATURE_VBAR)) {
 -        ARMCPRegInfo vbar_cp_reginfo[] = {
 +        static const ARMCPRegInfo vbar_cp_reginfo[] = {
              { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
                .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
                .access = PL1_RW, .writefn = vbar_write,
 --
-.25.1
+.20.1

-[PULL 08/23] target/arm: Change cpreg access permissions to enum
+[PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets
-From: Richard Henderson <richard.henderson@linaro.org>
+The lan9118 code mostly uses symbolic constants for register offsets;
 the exceptions are those which the datasheet doesn't give an official
 symbolic name to.
-Create a typedef as well, and use it in ARMCPRegInfo.
+Add some names for the registers which don't already have them, based
-This won't be perfect for debugging, but it'll nicely
+on the longer names they are given in the memory map.
 display the most common cases.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
 ---
- target/arm/cpregs.h | 44 +++++++++++++++++++++++---------------------
+ hw/net/lan9118.c | 24 ++++++++++++++++++------
- target/arm/helper.c |  2 +-
+file changed, 18 insertions(+), 6 deletions(-)
 files changed, 24 insertions(+), 22 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/hw/net/lan9118.c
-+++ b/target/arm/cpregs.h
++++ b/hw/net/lan9118.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
-  * described with these bits, then use a laxer set of restrictions, and
+ do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
   * do the more restrictive/complex check inside a helper function.
   */
 -#define PL3_R 0x80
 -#define PL3_W 0x40
 -#define PL2_R (0x20 | PL3_R)
 -#define PL2_W (0x10 | PL3_W)
 -#define PL1_R (0x08 | PL2_R)
 -#define PL1_W (0x04 | PL2_W)
 -#define PL0_R (0x02 | PL1_R)
 -#define PL0_W (0x01 | PL1_W)
 +typedef enum {
 +    PL3_R = 0x80,
 +    PL3_W = 0x40,
 +    PL2_R = 0x20 | PL3_R,
 +    PL2_W = 0x10 | PL3_W,
 +    PL1_R = 0x08 | PL2_R,
 +    PL1_W = 0x04 | PL2_W,
 +    PL0_R = 0x02 | PL1_R,
 +    PL0_W = 0x01 | PL1_W,
 -/*
 - * For user-mode some registers are accessible to EL0 via a kernel
 - * trap-and-emulate ABI. In this case we define the read permissions
 - * as actually being PL0_R. However some bits of any given register
 - * may still be masked.
 - */
 +    /*
 +     * For user-mode some registers are accessible to EL0 via a kernel
 +     * trap-and-emulate ABI. In this case we define the read permissions
 +     * as actually being PL0_R. However some bits of any given register
 +     * may still be masked.
 +     */
  #ifdef CONFIG_USER_ONLY
 -#define PL0U_R PL0_R
 +    PL0U_R = PL0_R,
  #else
 -#define PL0U_R PL1_R
 +    PL0U_R = PL1_R,
  #endif
--#define PL3_RW (PL3_R | PL3_W)
++/* The tx and rx fifo ports are a range of aliased 32-bit registers */
--#define PL2_RW (PL2_R | PL2_W)
++#define RX_DATA_FIFO_PORT_FIRST 0x00
--#define PL1_RW (PL1_R | PL1_W)
++#define RX_DATA_FIFO_PORT_LAST 0x1f
--#define PL0_RW (PL0_R | PL0_W)
++#define TX_DATA_FIFO_PORT_FIRST 0x20
-+    PL3_RW = PL3_R | PL3_W,
++#define TX_DATA_FIFO_PORT_LAST 0x3f
-+    PL2_RW = PL2_R | PL2_W,
++
-+    PL1_RW = PL1_R | PL1_W,
++#define RX_STATUS_FIFO_PORT 0x40
-+    PL0_RW = PL0_R | PL0_W,
++#define RX_STATUS_FIFO_PEEK 0x44
-+} CPAccessRights;
++#define TX_STATUS_FIFO_PORT 0x48
++#define TX_STATUS_FIFO_PEEK 0x4c
- typedef enum CPAccessResult {
++
-     /* Access is permitted */
+ #define CSR_ID_REV      0x50
-@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
+ #define CSR_IRQ_CFG     0x54
-     /* Register type: ARM_CP_* bits/values */
+ #define CSR_INT_STS     0x58
-     int type;
+@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
-     /* Access rights: PL*_[RW] */
+     offset &= 0xff;
--    int access;
-+    CPAccessRights access;
+     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
-     /* Security state: ARM_CP_SECSTATE_* bits/values */
+-    if (offset >= 0x20 && offset < 0x40) {
-     int secure;
++    if (offset >= TX_DATA_FIFO_PORT_FIRST &&
-     /*
++        offset <= TX_DATA_FIFO_PORT_LAST) {
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+         /* TX FIFO */
-index XXXXXXX..XXXXXXX 100644
+         tx_fifo_push(s, val);
---- a/target/arm/helper.c
+         return;
-+++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+     lan9118_state *s = (lan9118_state *)opaque;
-      * to encompass the generic architectural permission check.
-      */
+     //DPRINTF("Read reg 0x%02x\n", (int)offset);
-     if (r->state != ARM_CP_STATE_AA32) {
+-    if (offset < 0x20) {
--        int mask = 0;
++    if (offset <= RX_DATA_FIFO_PORT_LAST) {
-+        CPAccessRights mask;
+         /* RX FIFO */
-         switch (r->opc1) {
+         return rx_fifo_pop(s);
-         case 0:
+     }
-             /* min_EL EL1, but some accessible to EL0 via kernel ABI */
+     switch (offset) {
 -    case 0x40:
 +    case RX_STATUS_FIFO_PORT:
          return rx_status_fifo_pop(s);
 -    case 0x44:
 +    case RX_STATUS_FIFO_PEEK:
          return s->rx_status_fifo[s->rx_status_fifo_head];
 -    case 0x48:
 +    case TX_STATUS_FIFO_PORT:
          return tx_status_fifo_pop(s);
 -    case 0x4c:
 +    case TX_STATUS_FIFO_PEEK:
          return s->tx_status_fifo[s->tx_status_fifo_head];
      case CSR_ID_REV:
          return 0x01180001;
 --
-.25.1
+.20.1

-[PULL 06/23] target/arm: Reorg ARMCPRegInfo type field bits
+[PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Hao Wu <wuhaotsh@google.com>
-Instead of defining ARM_CP_FLAG_MASK to remove flags,
+This patch allows NPCM7XX CLK module to compute clocks that are used by
-define ARM_CP_SPECIAL_MASK to isolate special cases.
+other NPCM7XX modules.
 Sort the specials to the low bits. Use an enum.
-Split the large comment block so as to document each
+Add a new struct NPCM7xxClockConverterState which represents a
-value separately.
+single converter.  Each clock converter in CLK module represents one
 converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
 takes one or more input clocks and converts them into one output clock.
 They form a clock hierarchy in the CLK module and are responsible for
 outputing clocks for various other modules in an NPCM7XX SoC.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Each converter has a function pointer called "convert" which represents
 the unique logic for that converter.
 The clock contains two initialization information: ConverterInitInfo and
 ConverterConnectionInfo. They represent the vertices and edges in the
 clock diagram respectively.
 Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-6-richard.henderson@linaro.org
+Message-id: 20210108190945.949196-2-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h        | 130 +++++++++++++++++++++++--------------
+ include/hw/misc/npcm7xx_clk.h | 140 +++++-
- target/arm/cpu.c           |   4 +-
+ hw/misc/npcm7xx_clk.c         | 805 +++++++++++++++++++++++++++++++++-
- target/arm/helper.c        |   4 +-
+files changed, 932 insertions(+), 13 deletions(-)
  target/arm/translate-a64.c |   6 +-
  target/arm/translate.c     |   6 +-
 files changed, 92 insertions(+), 58 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/include/hw/misc/npcm7xx_clk.h
-+++ b/target/arm/cpregs.h
++++ b/include/hw/misc/npcm7xx_clk.h
 @@ -XXX,XX +XXX,XX @@
- #define TARGET_ARM_CPREGS_H
+ #define NPCM7XX_CLK_H
  #include "exec/memory.h"
 +#include "hw/clock.h"
  #include "hw/sysbus.h"
  /*
-- * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
+@@ -XXX,XX +XXX,XX @@
-- * special-behaviour cp reg and bits [11..8] indicate what behaviour
-- * it has. Otherwise it is a simple cp reg, where CONST indicates that
+ #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
-- * TCG can assume the value to be constant (ie load at translate time)
-- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
+-typedef struct NPCM7xxCLKState {
-- * indicates that the TB should not be ended after a write to this register
++/* Maximum amount of clock inputs in a SEL module. */
-- * (the default is that the TB ends after cp writes). OVERRIDE permits
++#define NPCM7XX_CLK_SEL_MAX_INPUT 5
-- * a register definition to override a previous definition for the
++
-- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
++/* PLLs in CLK module. */
-- * old must have the OVERRIDE bit set.
++typedef enum NPCM7xxClockPLL {
-- * ALIAS indicates that this register is an alias view of some underlying
++    NPCM7XX_CLOCK_PLL0,
-- * state which is also visible via another register, and that the other
++    NPCM7XX_CLOCK_PLL1,
-- * register is handling migration and reset; registers marked ALIAS will not be
++    NPCM7XX_CLOCK_PLL2,
-- * migrated but may have their state set by syncing of register state from KVM.
++    NPCM7XX_CLOCK_PLLG,
-- * NO_RAW indicates that this register has no underlying state and does not
++    NPCM7XX_CLOCK_NR_PLLS,
-- * support raw access for state saving/loading; it will not be used for either
++} NPCM7xxClockPLL;
-- * migration or KVM state synchronization. (Typically this is for "registers"
++
-- * which are actually used as instructions for cache maintenance and so on.)
++/* SEL/MUX in CLK module. */
-- * IO indicates that this register does I/O and therefore its accesses
++typedef enum NPCM7xxClockSEL {
-- * need to be marked with gen_io_start() and also end the TB. In particular,
++    NPCM7XX_CLOCK_PIXCKSEL,
-- * registers which implement clocks or timers require this.
++    NPCM7XX_CLOCK_MCCKSEL,
-- * RAISES_EXC is for when the read or write hook might raise an exception;
++    NPCM7XX_CLOCK_CPUCKSEL,
-- * the generated code will synchronize the CPU state before calling the hook
++    NPCM7XX_CLOCK_CLKOUTSEL,
-- * so that it is safe for the hook to call raise_exception().
++    NPCM7XX_CLOCK_UARTCKSEL,
-- * NEWEL is for writes to registers that might change the exception
++    NPCM7XX_CLOCK_TIMCKSEL,
-- * level - typically on older ARM chips. For those cases we need to
++    NPCM7XX_CLOCK_SDCKSEL,
-- * re-read the new el when recomputing the translation flags.
++    NPCM7XX_CLOCK_GFXMSEL,
-+ * ARMCPRegInfo type field bits:
++    NPCM7XX_CLOCK_SUCKSEL,
-  */
++    NPCM7XX_CLOCK_NR_SELS,
--#define ARM_CP_SPECIAL           0x0001
++} NPCM7xxClockSEL;
--#define ARM_CP_CONST             0x0002
++
--#define ARM_CP_64BIT             0x0004
++/* Dividers in CLK module. */
--#define ARM_CP_SUPPRESS_TB_END   0x0008
++typedef enum NPCM7xxClockDivider {
--#define ARM_CP_OVERRIDE          0x0010
++    NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
--#define ARM_CP_ALIAS             0x0020
++    NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
--#define ARM_CP_IO                0x0040
++    NPCM7XX_CLOCK_MC_DIVIDER,
--#define ARM_CP_NO_RAW            0x0080
++    NPCM7XX_CLOCK_AXI_DIVIDER,
--#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
++    NPCM7XX_CLOCK_AHB_DIVIDER,
--#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
++    NPCM7XX_CLOCK_AHB3_DIVIDER,
--#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
++    NPCM7XX_CLOCK_SPI0_DIVIDER,
--#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
++    NPCM7XX_CLOCK_SPIX_DIVIDER,
--#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
++    NPCM7XX_CLOCK_APB1_DIVIDER,
--#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
++    NPCM7XX_CLOCK_APB2_DIVIDER,
--#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
++    NPCM7XX_CLOCK_APB3_DIVIDER,
--#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
++    NPCM7XX_CLOCK_APB4_DIVIDER,
--#define ARM_CP_FPU               0x1000
++    NPCM7XX_CLOCK_APB5_DIVIDER,
--#define ARM_CP_SVE               0x2000
++    NPCM7XX_CLOCK_CLKOUT_DIVIDER,
--#define ARM_CP_NO_GDB            0x4000
++    NPCM7XX_CLOCK_UART_DIVIDER,
--#define ARM_CP_RAISES_EXC        0x8000
++    NPCM7XX_CLOCK_TIMER_DIVIDER,
--#define ARM_CP_NEWEL             0x10000
++    NPCM7XX_CLOCK_ADC_DIVIDER,
--/* Mask of only the flag bits in a type field */
++    NPCM7XX_CLOCK_MMC_DIVIDER,
--#define ARM_CP_FLAG_MASK         0x1f0ff
++    NPCM7XX_CLOCK_SDHC_DIVIDER,
-+enum {
++    NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
-+    /*
++    NPCM7XX_CLOCK_UTMI_DIVIDER,
-+     * Register must be handled specially during translation.
++    NPCM7XX_CLOCK_NR_DIVIDERS,
-+     * The method is one of the values below:
++} NPCM7xxClockConverter;
-+     */
++
-+    ARM_CP_SPECIAL_MASK          = 0x000f,
++typedef struct NPCM7xxCLKState NPCM7xxCLKState;
-+    /* Special: no change to PE state: writes ignored, reads ignored. */
++
-+    ARM_CP_NOP                   = 0x0001,
++/**
-+    /* Special: sysreg is WFI, for v5 and v6. */
++ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
-+    ARM_CP_WFI                   = 0x0002,
++ * @name: The name of the module.
-+    /* Special: sysreg is NZCV. */
++ * @clk: The CLK module that owns this module.
-+    ARM_CP_NZCV                  = 0x0003,
++ * @clock_in: The input clock of this module.
-+    /* Special: sysreg is CURRENTEL. */
++ * @clock_out: The output clock of this module.
-+    ARM_CP_CURRENTEL             = 0x0004,
++ * @reg: The control registers for this PLL module.
-+    /* Special: sysreg is DC ZVA or similar. */
++ */
-+    ARM_CP_DC_ZVA                = 0x0005,
++typedef struct NPCM7xxClockPLLState {
-+    ARM_CP_DC_GVA                = 0x0006,
++    DeviceState parent;
-+    ARM_CP_DC_GZVA               = 0x0007,
++
-+
++    const char *name;
-+    /* Flag: reads produce resetvalue; writes ignored. */
++    NPCM7xxCLKState *clk;
-+    ARM_CP_CONST                 = 1 << 4,
++    Clock *clock_in;
-+    /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
++    Clock *clock_out;
-+    ARM_CP_64BIT                 = 1 << 5,
++
-+    /*
++    int reg;
-+     * Flag: TB should not be ended after a write to this register
++} NPCM7xxClockPLLState;
-+     * (the default is that the TB ends after cp writes).
++
-+     */
++/**
-+    ARM_CP_SUPPRESS_TB_END       = 1 << 6,
++ * struct NPCM7xxClockSELState - A SEL module in CLK module.
-+    /*
++ * @name: The name of the module.
-+     * Flag: Permit a register definition to override a previous definition
++ * @clk: The CLK module that owns this module.
-+     * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new
++ * @input_size: The size of inputs of this module.
-+     * or the old must have the ARM_CP_OVERRIDE bit set.
++ * @clock_in: The input clocks of this module.
-+     */
++ * @clock_out: The output clocks of this module.
-+    ARM_CP_OVERRIDE              = 1 << 7,
++ * @offset: The offset of this module in the control register.
-+    /*
++ * @len: The length of this module in the control register.
-+     * Flag: Register is an alias view of some underlying state which is also
++ */
-+     * visible via another register, and that the other register is handling
++typedef struct NPCM7xxClockSELState {
-+     * migration and reset; registers marked ARM_CP_ALIAS will not be migrated
++    DeviceState parent;
-+     * but may have their state set by syncing of register state from KVM.
++
-+     */
++    const char *name;
-+    ARM_CP_ALIAS                 = 1 << 8,
++    NPCM7xxCLKState *clk;
-+    /*
++    uint8_t input_size;
-+     * Flag: Register does I/O and therefore its accesses need to be marked
++    Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
-+     * with gen_io_start() and also end the TB. In particular, registers which
++    Clock *clock_out;
-+     * implement clocks or timers require this.
++
-+     */
++    int offset;
-+    ARM_CP_IO                    = 1 << 9,
++    int len;
-+    /*
++} NPCM7xxClockSELState;
-+     * Flag: Register has no underlying state and does not support raw access
++
-+     * for state saving/loading; it will not be used for either migration or
++/**
-+     * KVM state synchronization. Typically this is for "registers" which are
++ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
-+     * actually used as instructions for cache maintenance and so on.
++ * @name: The name of the module.
-+     */
++ * @clk: The CLK module that owns this module.
-+    ARM_CP_NO_RAW                = 1 << 10,
++ * @clock_in: The input clock of this module.
-+    /*
++ * @clock_out: The output clock of this module.
-+     * Flag: The read or write hook might raise an exception; the generated
++ * @divide: The function the divider uses to divide the input.
-+     * code will synchronize the CPU state before calling the hook so that it
++ * @reg: The index of the control register that contains the divisor.
-+     * is safe for the hook to call raise_exception().
++ * @offset: The offset of the divisor in the control register.
-+     */
++ * @len: The length of the divisor in the control register.
-+    ARM_CP_RAISES_EXC            = 1 << 11,
++ * @divisor: The divisor for a constant divisor
-+    /*
++ */
-+     * Flag: Writes to the sysreg might change the exception level - typically
++typedef struct NPCM7xxClockDividerState {
-+     * on older ARM chips. For those cases we need to re-read the new el when
++    DeviceState parent;
-+     * recomputing the translation flags.
++
-+     */
++    const char *name;
-+    ARM_CP_NEWEL                 = 1 << 12,
++    NPCM7xxCLKState *clk;
-+    /*
++    Clock *clock_in;
-+     * Flag: Access check for this sysreg is identical to accessing FPU state
++    Clock *clock_out;
-+     * from an instruction: use translation fp_access_check().
++
-+     */
++    uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
-+    ARM_CP_FPU                   = 1 << 13,
++    union {
-+    /*
++        struct {
-+     * Flag: Access check for this sysreg is identical to accessing SVE state
++            int reg;
-+     * from an instruction: use translation sve_access_check().
++            int offset;
-+     */
++            int len;
-+    ARM_CP_SVE                   = 1 << 14,
++        };
-+    /* Flag: Do not expose in gdb sysreg xml. */
++        int divisor;
-+    ARM_CP_NO_GDB                = 1 << 15,
++    };
 +} NPCM7xxClockDividerState;
 +
 +struct NPCM7xxCLKState {
      SysBusDevice parent;
      MemoryRegion iomem;
 +    /* Clock converters */
 +    NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
 +    NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
 +    NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
 +
      uint32_t regs[NPCM7XX_CLK_NR_REGS];
      /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
      int64_t ref_ns;
 -} NPCM7xxCLKState;
 +
 +    /* The incoming reference clock. */
 +    Clock *clkref;
 +};
- /*
+ #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
-  * Valid values for ARMCPRegInfo state field, indicating which of
+ #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/hw/misc/npcm7xx_clk.c
-+++ b/target/arm/cpu.c
++++ b/hw/misc/npcm7xx_clk.c
-@@ -XXX,XX +XXX,XX @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
+@@ -XXX,XX +XXX,XX @@
-     ARMCPRegInfo *ri = value;
-     ARMCPU *cpu = opaque;
+ #include "hw/misc/npcm7xx_clk.h"
+ #include "hw/timer/npcm7xx_timer.h"
--    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
++#include "hw/qdev-clock.h"
-+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
+ #include "migration/vmstate.h"
  #include "qemu/error-report.h"
  #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
  #include "trace.h"
  #include "sysemu/watchdog.h"
 +/*
 + * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
 + * is always 25 MHz.
 + */
 +#define NPCM7XX_CLOCK_REF_HZ            (25000000)
 +
 +/* Register Field Definitions */
 +#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
 +
  #define PLLCON_LOKI     BIT(31)
  #define PLLCON_LOKS     BIT(30)
  #define PLLCON_PWDEN    BIT(12)
 +#define PLLCON_FBDV(con) extract32((con), 16, 12)
 +#define PLLCON_OTDV2(con) extract32((con), 13, 3)
 +#define PLLCON_OTDV1(con) extract32((con), 8, 3)
 +#define PLLCON_INDV(con) extract32((con), 0, 6)
  enum NPCM7xxCLKRegisters {
      NPCM7XX_CLK_CLKEN1,
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
      [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
  };
 -/* Register Field Definitions */
 -#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
 -
  /* The number of watchdogs that can trigger a reset. */
  #define NPCM7XX_NR_WATCHDOGS    (3)
 +/* Clock converter functions */
 +
 +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
 +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_PLL)
 +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
 +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_SEL)
 +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
 +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
 +
 +static void npcm7xx_clk_update_pll(void *opaque)
 +{
 +    NPCM7xxClockPLLState *s = opaque;
 +    uint32_t con = s->clk->regs[s->reg];
 +    uint64_t freq;
 +
 +    /* The PLL is grounded if it is not locked yet. */
 +    if (con & PLLCON_LOKI) {
 +        freq = clock_get_hz(s->clock_in);
 +        freq *= PLLCON_FBDV(con);
 +        freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
 +    } else {
 +        freq = 0;
 +    }
 +
 +    clock_update_hz(s->clock_out, freq);
 +}
 +
 +static void npcm7xx_clk_update_sel(void *opaque)
 +{
 +    NPCM7xxClockSELState *s = opaque;
 +    uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
 +            s->len);
 +
 +    if (index >= s->input_size) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: SEL index: %u out of range\n",
 +                      __func__, index);
 +        index = 0;
 +    }
 +    clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
 +}
 +
 +static void npcm7xx_clk_update_divider(void *opaque)
 +{
 +    NPCM7xxClockDividerState *s = opaque;
 +    uint32_t freq;
 +
 +    freq = s->divide(s);
 +    clock_update_hz(s->clock_out, freq);
 +}
 +
 +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) / s->divisor;
 +}
 +
 +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) /
 +            (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
 +}
 +
 +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
 +{
 +    return divide_by_reg_divisor(s) / 2;
 +}
 +
 +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) >>
 +        extract32(s->clk->regs[s->reg], s->offset, s->len);
 +}
 +
 +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
 +{
 +    switch (reg) {
 +    case NPCM7XX_CLK_PLLCON0:
 +        return NPCM7XX_CLOCK_PLL0;
 +    case NPCM7XX_CLK_PLLCON1:
 +        return NPCM7XX_CLOCK_PLL1;
 +    case NPCM7XX_CLK_PLLCON2:
 +        return NPCM7XX_CLOCK_PLL2;
 +    case NPCM7XX_CLK_PLLCONG:
 +        return NPCM7XX_CLOCK_PLLG;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        npcm7xx_clk_update_pll(&clk->plls[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        npcm7xx_clk_update_sel(&clk->sels[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        npcm7xx_clk_update_divider(&clk->dividers[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
 +{
 +    clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
 +    npcm7xx_clk_update_all_plls(clk);
 +    npcm7xx_clk_update_all_sels(clk);
 +    npcm7xx_clk_update_all_dividers(clk);
 +}
 +
 +/* Types of clock sources. */
 +typedef enum ClockSrcType {
 +    CLKSRC_REF,
 +    CLKSRC_PLL,
 +    CLKSRC_SEL,
 +    CLKSRC_DIV,
 +} ClockSrcType;
 +
 +typedef struct PLLInitInfo {
 +    const char *name;
 +    ClockSrcType src_type;
 +    int src_index;
 +    int reg;
 +    const char *public_name;
 +} PLLInitInfo;
 +
 +typedef struct SELInitInfo {
 +    const char *name;
 +    uint8_t input_size;
 +    ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    int offset;
 +    int len;
 +    const char *public_name;
 +} SELInitInfo;
 +
 +typedef struct DividerInitInfo {
 +    const char *name;
 +    ClockSrcType src_type;
 +    int src_index;
 +    uint32_t (*divide)(NPCM7xxClockDividerState *s);
 +    int reg; /* not used when type == CONSTANT */
 +    int offset; /* not used when type == CONSTANT */
 +    int len; /* not used when type == CONSTANT */
 +    int divisor; /* used only when type == CONSTANT */
 +    const char *public_name;
 +} DividerInitInfo;
 +
 +static const PLLInitInfo pll_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PLL0] = {
 +        .name = "pll0",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON0,
 +    },
 +    [NPCM7XX_CLOCK_PLL1] = {
 +        .name = "pll1",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON1,
 +    },
 +    [NPCM7XX_CLOCK_PLL2] = {
 +        .name = "pll2",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON2,
 +    },
 +    [NPCM7XX_CLOCK_PLLG] = {
 +        .name = "pllg",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCONG,
 +    },
 +};
 +
 +static const SELInitInfo sel_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PIXCKSEL] = {
 +        .name = "pixcksel",
 +        .input_size = 2,
 +        .src_type = {CLKSRC_PLL, CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLLG, 0},
 +        .offset = 5,
 +        .len = 1,
 +        .public_name = "pixel-clock",
 +    },
 +    [NPCM7XX_CLOCK_MCCKSEL] = {
 +        .name = "mccksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
 +            /*MCBPCK, shouldn't be used in normal operation*/
 +            CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
 +        .offset = 12,
 +        .len = 2,
 +        .public_name = "mc-phy-clock",
 +    },
 +    [NPCM7XX_CLOCK_CPUCKSEL] = {
 +        .name = "cpucksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
 +            /*SYSBPCK, shouldn't be used in normal operation*/
 +            CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
 +        .offset = 0,
 +        .len = 2,
 +        .public_name = "system-clock",
 +    },
 +    [NPCM7XX_CLOCK_CLKOUTSEL] = {
 +        .name = "clkoutsel",
 +        .input_size = 5,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
 +            CLKSRC_PLL, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 18,
 +        .len = 3,
 +        .public_name = "tock",
 +    },
 +    [NPCM7XX_CLOCK_UARTCKSEL] = {
 +        .name = "uartcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 8,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_TIMCKSEL] = {
 +        .name = "timcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 14,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_SDCKSEL] = {
 +        .name = "sdcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 6,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_GFXMSEL] = {
 +        .name = "gfxmksel",
 +        .input_size = 2,
 +        .src_type = {CLKSRC_REF, CLKSRC_PLL},
 +        .src_index = {0, NPCM7XX_CLOCK_PLL2},
 +        .offset = 21,
 +        .len = 1,
 +    },
 +    [NPCM7XX_CLOCK_SUCKSEL] = {
 +        .name = "sucksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 10,
 +        .len = 2,
 +    },
 +};
 +
 +static const DividerInitInfo divider_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PLL1D2] = {
 +        .name = "pll1d2",
 +        .src_type = CLKSRC_PLL,
 +        .src_index = NPCM7XX_CLOCK_PLL1,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +    },
 +    [NPCM7XX_CLOCK_PLL2D2] = {
 +        .name = "pll2d2",
 +        .src_type = CLKSRC_PLL,
 +        .src_index = NPCM7XX_CLOCK_PLL2,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +    },
 +    [NPCM7XX_CLOCK_MC_DIVIDER] = {
 +        .name = "mc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_MCCKSEL,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +        .public_name = "mc-clock"
 +    },
 +    [NPCM7XX_CLOCK_AXI_DIVIDER] = {
 +        .name = "axi-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_CPUCKSEL,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 0,
 +        .len = 1,
 +        .public_name = "clk2"
 +    },
 +    [NPCM7XX_CLOCK_AHB_DIVIDER] = {
 +        .name = "ahb-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 26,
 +        .len = 2,
 +        .public_name = "clk4"
 +    },
 +    [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
 +        .name = "ahb3-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 6,
 +        .len = 5,
 +        .public_name = "ahb3-spi3-clock"
 +    },
 +    [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
 +        .name = "spi0-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV3,
 +        .offset = 6,
 +        .len = 5,
 +        .public_name = "spi0-clock",
 +    },
 +    [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
 +        .name = "spix-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV3,
 +        .offset = 1,
 +        .len = 5,
 +        .public_name = "spix-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB1_DIVIDER] = {
 +        .name = "apb1-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 24,
 +        .len = 2,
 +        .public_name = "apb1-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB2_DIVIDER] = {
 +        .name = "apb2-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 26,
 +        .len = 2,
 +        .public_name = "apb2-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB3_DIVIDER] = {
 +        .name = "apb3-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 28,
 +        .len = 2,
 +        .public_name = "apb3-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB4_DIVIDER] = {
 +        .name = "apb4-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 30,
 +        .len = 2,
 +        .public_name = "apb4-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB5_DIVIDER] = {
 +        .name = "apb5-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 22,
 +        .len = 2,
 +        .public_name = "apb5-clock",
 +    },
 +    [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
 +        .name = "clkout-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 16,
 +        .len = 5,
 +        .public_name = "clkout",
 +    },
 +    [NPCM7XX_CLOCK_UART_DIVIDER] = {
 +        .name = "uart-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_UARTCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 16,
 +        .len = 5,
 +        .public_name = "uart-clock",
 +    },
 +    [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
 +        .name = "timer-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_TIMCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 21,
 +        .len = 5,
 +        .public_name = "timer-clock",
 +    },
 +    [NPCM7XX_CLOCK_ADC_DIVIDER] = {
 +        .name = "adc-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 28,
 +        .len = 3,
 +        .public_name = "adc-clock",
 +    },
 +    [NPCM7XX_CLOCK_MMC_DIVIDER] = {
 +        .name = "mmc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SDCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 11,
 +        .len = 5,
 +        .public_name = "mmc-clock",
 +    },
 +    [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
 +        .name = "sdhc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SDCKSEL,
 +        .divide = divide_by_reg_divisor_times_2,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 0,
 +        .len = 4,
 +        .public_name = "sdhc-clock",
 +    },
 +    [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
 +        .name = "gfxm-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_GFXMSEL,
 +        .divide = divide_by_constant,
 +        .divisor = 3,
 +        .public_name = "gfxm-clock",
 +    },
 +    [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
 +        .name = "utmi-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SUCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 8,
 +        .len = 5,
 +        .public_name = "utmi-clock",
 +    },
 +};
 +
 +static void npcm7xx_clk_pll_init(Object *obj)
 +{
 +    NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
 +
 +    pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
 +            npcm7xx_clk_update_pll, pll);
 +    pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
 +}
 +
 +static void npcm7xx_clk_sel_init(Object *obj)
 +{
 +    int i;
 +    NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
 +
 +    for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
 +        sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
 +                g_strdup_printf("clock-in[%d]", i),
 +                npcm7xx_clk_update_sel, sel);
 +    }
 +    sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
 +}
 +static void npcm7xx_clk_divider_init(Object *obj)
 +{
 +    NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
 +
 +    div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
 +            npcm7xx_clk_update_divider, div);
 +    div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
 +}
 +
 +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
 +        NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
 +{
 +    pll->name = init_info->name;
 +    pll->clk = clk;
 +    pll->reg = init_info->reg;
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
 +        NPCM7xxCLKState *clk, const SELInitInfo *init_info)
 +{
 +    int input_size = init_info->input_size;
 +
 +    sel->name = init_info->name;
 +    sel->clk = clk;
 +    sel->input_size = init_info->input_size;
 +    g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
 +    sel->offset = init_info->offset;
 +    sel->len = init_info->len;
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
 +        NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
 +{
 +    div->name = init_info->name;
 +    div->clk = clk;
 +
 +    div->divide = init_info->divide;
 +    if (div->divide == divide_by_constant) {
 +        div->divisor = init_info->divisor;
 +    } else {
 +        div->reg = init_info->reg;
 +        div->offset = init_info->offset;
 +        div->len = init_info->len;
 +    }
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
 +        int index)
 +{
 +    switch (type) {
 +    case CLKSRC_REF:
 +        return clk->clkref;
 +    case CLKSRC_PLL:
 +        return clk->plls[index].clock_out;
 +    case CLKSRC_SEL:
 +        return clk->sels[index].clock_out;
 +    case CLKSRC_DIV:
 +        return clk->dividers[index].clock_out;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
 +{
 +    int i, j;
 +    Clock *src;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
 +                pll_init_info_list[i].src_index);
 +        clock_set_source(clk->plls[i].clock_in, src);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
 +            src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
 +                    sel_init_info_list[i].src_index[j]);
 +            clock_set_source(clk->sels[i].clock_in[j], src);
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
 +                divider_init_info_list[i].src_index);
 +        clock_set_source(clk->dividers[i].clock_in, src);
 +    }
 +}
 +
  static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
  {
      uint32_t reg = offset / sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
           *
           * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
           */
 -        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
 +        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
          break;
      default:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
                  value |= (value & PLLCON_LOKS);
              }
          }
 +        /* Only update PLL when it is locked. */
 +        if (value & PLLCON_LOKI) {
 +            npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
 +        }
 +        break;
 +
 +    case NPCM7XX_CLK_CLKSEL:
 +        npcm7xx_clk_update_all_sels(s);
 +        break;
 +
 +    case NPCM7XX_CLK_CLKDIV1:
 +    case NPCM7XX_CLK_CLKDIV2:
 +    case NPCM7XX_CLK_CLKDIV3:
 +        npcm7xx_clk_update_all_dividers(s);
          break;
      case NPCM7XX_CLK_CNTR25M:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
      case RESET_TYPE_COLD:
          memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
          s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +        npcm7xx_clk_update_all_clocks(s);
          return;
      }
-@@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
-     ARMCPU *cpu = opaque;
+                   __func__, type);
-     uint64_t oldvalue, newvalue;
+ }
--    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
++static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
-+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
++{
-         return;
++    int i;
-     }
++
++    s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
-diff --git a/target/arm/helper.c b/target/arm/helper.c
++
-index XXXXXXX..XXXXXXX 100644
++    /* First pass: init all converter modules */
---- a/target/arm/helper.c
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
-+++ b/target/arm/helper.c
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
-      * multiple times. Special registers (ie NOP/WFI) are
++            != NPCM7XX_CLOCK_NR_DIVIDERS);
-      * never migratable and not even raw-accessible.
++    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
-      */
++        object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
--    if ((r->type & ARM_CP_SPECIAL)) {
++                &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
-+    if (r->type & ARM_CP_SPECIAL_MASK) {
++        npcm7xx_init_clock_pll(&s->plls[i], s,
-         r2->type |= ARM_CP_NO_RAW;
++                &pll_init_info_list[i]);
-     }
++    }
-     if (((r->crm == CP_ANY) && crm != 0) ||
++    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
++        object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
-     /* Check that the register definition has enough info to handle
++                &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
-      * reads and writes if they are permitted.
++        npcm7xx_init_clock_sel(&s->sels[i], s,
-      */
++                &sel_init_info_list[i]);
--    if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
++    }
-+    if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
++    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
-         if (r->access & PL3_R) {
++        object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
-             assert((r->fieldoffset ||
++                &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
-                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
++        npcm7xx_init_clock_divider(&s->dividers[i], s,
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++                &divider_init_info_list[i]);
-index XXXXXXX..XXXXXXX 100644
++    }
---- a/target/arm/translate-a64.c
++
-+++ b/target/arm/translate-a64.c
++    /* Second pass: connect converter modules */
-@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
++    npcm7xx_connect_clocks(s);
-     }
++
++    clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
-     /* Handle special cases first */
++}
--    switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
++
-+    switch (ri->type & ARM_CP_SPECIAL_MASK) {
+ static void npcm7xx_clk_init(Object *obj)
-+    case 0:
+ {
-+        break;
+     NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
-     case ARM_CP_NOP:
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
-         return;
+     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
-     case ARM_CP_NZCV:
+                           TYPE_NPCM7XX_CLK, 4 * KiB);
-@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
+     sysbus_init_mmio(&s->parent, &s->iomem);
-         }
+-    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
-         return;
+-            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
-     default:
+ }
--        break;
-+        g_assert_not_reached();
+-static const VMStateDescription vmstate_npcm7xx_clk = {
-     }
+-    .name = "npcm7xx-clk",
-     if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
++static int npcm7xx_clk_post_load(void *opaque, int version_id)
-         return;
++{
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++    if (version_id >= 1) {
-index XXXXXXX..XXXXXXX 100644
++        NPCM7xxCLKState *clk = opaque;
---- a/target/arm/translate.c
++
-+++ b/target/arm/translate.c
++        npcm7xx_clk_update_all_clocks(clk);
-@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
++    }
-         }
++
++    return 0;
-         /* Handle special cases first */
++}
--        switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
++
-+        switch (ri->type & ARM_CP_SPECIAL_MASK) {
++static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
-+        case 0:
++{
-+            break;
++    int i;
-         case ARM_CP_NOP:
++    NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
-             return;
++
-         case ARM_CP_WFI:
++    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
-@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
++            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
-             s->base.is_jmp = DISAS_WFI;
++    npcm7xx_clk_init_clock_hierarchy(s);
-             return;
++
-         default:
++    /* Realize child devices */
--            break;
++    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
-+            g_assert_not_reached();
++        if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
-         }
++            return;
++        }
-         if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
++    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_clk_pll = {
 +    .name = "npcm7xx-clock-pll",
      .version_id = 0,
      .minimum_version_id = 0,
 -    .fields = (VMStateField[]) {
 -        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
 -        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
          VMSTATE_END_OF_LIST(),
      },
  };
 +static const VMStateDescription vmstate_npcm7xx_clk_sel = {
 +    .name = "npcm7xx-clock-sel",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
 +                NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_clk_divider = {
 +    .name = "npcm7xx-clock-divider",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_clk = {
 +    .name = "npcm7xx-clk",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .post_load = npcm7xx_clk_post_load,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
 +        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
 +        VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock PLL Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_pll;
 +}
 +
 +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock SEL Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_sel;
 +}
 +
 +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock Divider Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_divider;
 +}
 +
  static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
  {
      ResettableClass *rc = RESETTABLE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
      dc->desc = "NPCM7xx Clock Control Registers";
      dc->vmsd = &vmstate_npcm7xx_clk;
 +    dc->realize = npcm7xx_clk_realize;
      rc->phases.enter = npcm7xx_clk_enter_reset;
  }
 +static const TypeInfo npcm7xx_clk_pll_info = {
 +    .name               = TYPE_NPCM7XX_CLOCK_PLL,
 +    .parent             = TYPE_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxClockPLLState),
 +    .instance_init      = npcm7xx_clk_pll_init,
 +    .class_init         = npcm7xx_clk_pll_class_init,
 +};
 +
 +static const TypeInfo npcm7xx_clk_sel_info = {
 +    .name               = TYPE_NPCM7XX_CLOCK_SEL,
 +    .parent             = TYPE_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxClockSELState),
 +    .instance_init      = npcm7xx_clk_sel_init,
 +    .class_init         = npcm7xx_clk_sel_class_init,
 +};
 +
 +static const TypeInfo npcm7xx_clk_divider_info = {
 +    .name               = TYPE_NPCM7XX_CLOCK_DIVIDER,
 +    .parent             = TYPE_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxClockDividerState),
 +    .instance_init      = npcm7xx_clk_divider_init,
 +    .class_init         = npcm7xx_clk_divider_class_init,
 +};
 +
  static const TypeInfo npcm7xx_clk_info = {
      .name               = TYPE_NPCM7XX_CLK,
      .parent             = TYPE_SYS_BUS_DEVICE,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
  static void npcm7xx_clk_register_type(void)
  {
 +    type_register_static(&npcm7xx_clk_pll_info);
 +    type_register_static(&npcm7xx_clk_sel_info);
 +    type_register_static(&npcm7xx_clk_divider_info);
      type_register_static(&npcm7xx_clk_info);
  }
  type_init(npcm7xx_clk_register_type);
 --
-.25.1
+.20.1

-[PULL 13/23] target/arm: Merge allocation of the cpreg and its name
+[PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Hao Wu <wuhaotsh@google.com>
-Simplify freeing cp_regs hash table entries by using a single
+This patch makes NPCM7XX Timer to use a the timer clock generated by the
-allocation for the entire value.
+CLK module instead of the magic number TIMER_REF_HZ.
-This fixes a theoretical bug if we were to ever free the entire
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
-hash table, because we've been installing string literal constants
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
-into the cpreg structure in define_arm_vh_e2h_redirects_aliases.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
-However, at present we only free entries created for AArch32
+Message-id: 20210108190945.949196-3-wuhaotsh@google.com
 wildcard cpregs which get overwritten by more specific cpregs,
 so this bug is never exposed.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-13-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c    | 16 +---------------
+ include/hw/misc/npcm7xx_clk.h    |  6 -----
- target/arm/helper.c | 10 ++++++++--
+ include/hw/timer/npcm7xx_timer.h |  1 +
-files changed, 9 insertions(+), 17 deletions(-)
+ hw/arm/npcm7xx.c                 |  5 ++++
  hw/timer/npcm7xx_timer.c         | 39 +++++++++++++++-----------------
 files changed, 24 insertions(+), 27 deletions(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/include/hw/misc/npcm7xx_clk.h
-+++ b/target/arm/cpu.c
++++ b/include/hw/misc/npcm7xx_clk.h
-@@ -XXX,XX +XXX,XX @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
+@@ -XXX,XX +XXX,XX @@
-     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
+ #include "hw/clock.h"
  #include "hw/sysbus.h"
 -/*
 - * The reference clock frequency for the timer modules, and the SECCNT and
 - * CNTR25M registers in this module, is always 25 MHz.
 - */
 -#define NPCM7XX_TIMER_REF_HZ            (25000000)
 -
  /*
   * Number of registers in our device state structure. Don't change this without
   * incrementing the version_id in the vmstate.
 diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/timer/npcm7xx_timer.h
 +++ b/include/hw/timer/npcm7xx_timer.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
      uint32_t    tisr;
 +    Clock       *clock;
      NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
      NPCM7xxWatchdogTimer watchdog_timer;
  };
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/char/serial.h"
  #include "hw/loader.h"
  #include "hw/misc/unimp.h"
 +#include "hw/qdev-clock.h"
  #include "hw/qdev-properties.h"
  #include "qapi/error.h"
  #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
          int first_irq;
          int j;
 +        /* Connect the timer clock. */
 +        qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
 +                    DEVICE(&s->clk), "timer-clock"));
 +
          sysbus_realize(sbd, &error_abort);
          sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/npcm7xx_timer.c
 +++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "hw/irq.h"
 +#include "hw/qdev-clock.h"
  #include "hw/qdev-properties.h"
 -#include "hw/misc/npcm7xx_clk.h"
  #include "hw/timer/npcm7xx_timer.h"
  #include "migration/vmstate.h"
  #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
  /* Convert a timer cycle count to a time interval in nanoseconds. */
  static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
  {
 -    int64_t ns = count;
 +    int64_t ticks = count;
 -    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
 -    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
 +    ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
 -    return ns;
 +    return clock_ticks_to_ns(t->ctrl->clock, ticks);
  }
--static void cpreg_hashtable_data_destroy(gpointer data)
+ /* Convert a time interval in nanoseconds to a timer cycle count. */
--{
+ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
--    /*
+ {
--     * Destroy function for cpu->cp_regs hashtable data entries.
+-    int64_t count;
 -     * We must free the name string because it was g_strdup()ed in
 -     * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
 -     * from r->name because we know we definitely allocated it.
 -     */
 -    ARMCPRegInfo *r = data;
 -
--    g_free((void *)r->name);
+-    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
--    g_free(r);
+-    count /= npcm7xx_tcsr_prescaler(t->tcsr);
 -}
 -
- static void arm_cpu_initfn(Object *obj)
+-    return count;
 +    return ns / clock_ticks_to_ns(t->ctrl->clock,
 +                                  npcm7xx_tcsr_prescaler(t->tcsr));
  }
  static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
  static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
          int64_t cycles)
  {
-     ARMCPU *cpu = ARM_CPU(obj);
+-    uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
+-    int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
-     cpu_set_cpustate_pointers(cpu);
++    int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
-     cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
++    int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
--                                         NULL, cpreg_hashtable_data_destroy);
-+                                         NULL, g_free);
+     /*
+      * The reset function always clears the current timer. The caller of the
-     QLIST_INIT(&cpu->pre_el_change_hooks);
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
      QLIST_INIT(&cpu->el_change_hooks);
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
       * add a single reginfo struct to the hash table.
       */
-     uint32_t key;
+     npcm7xx_timer_clear(&t->base_timer);
--    ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
-+    ARMCPRegInfo *r2;
+-    ns *= prescaler;
-     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
+     t->base_timer.remaining_ns = ns;
-     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+ }
-+    size_t name_len;
-+
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
-+    /* Combine cpreg and name into one allocation. */
+     qemu_irq_lower(s->watchdog_timer.irq);
-+    name_len = strlen(name) + 1;
+ }
-+    r2 = g_malloc(sizeof(*r2) + name_len);
-+    *r2 = *r;
+-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
-+    r2->name = memcpy(r2 + 1, name, name_len);
++static void npcm7xx_timer_init(Object *obj)
+ {
--    r2->name = g_strdup(name);
+-    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
-     /* Reset the secure state to the specific incoming state.  This is
+-    SysBusDevice *sbd = &s->parent;
-      * necessary as the register may have been defined with both states.
++    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
-      */
++    DeviceState *dev = DEVICE(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
      int i;
      NPCM7xxWatchdogTimer *w;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
              npcm7xx_watchdog_timer_expired, w);
      sysbus_init_irq(sbd, &w->irq);
 -    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
                            TYPE_NPCM7XX_TIMER, 4 * KiB);
      sysbus_init_mmio(sbd, &s->iomem);
      qdev_init_gpio_out_named(dev, &w->reset_signal,
              NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
 +    s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
  }
  static const VMStateDescription vmstate_npcm7xx_base_timer = {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
  static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
      .name = "npcm7xx-timer-ctrl",
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .fields = (VMStateField[]) {
          VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
 +        VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
          VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
                               NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
                               NPCM7xxTimer),
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
      QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
      dc->desc = "NPCM7xx Timer Controller";
 -    dc->realize = npcm7xx_timer_realize;
      dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
      rc->phases.enter = npcm7xx_timer_enter_reset;
      rc->phases.hold = npcm7xx_timer_hold_reset;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
      .parent             = TYPE_SYS_BUS_DEVICE,
      .instance_size      = sizeof(NPCM7xxTimerCtrlState),
      .class_init         = npcm7xx_timer_class_init,
 +    .instance_init      = npcm7xx_timer_init,
  };
  static void npcm7xx_timer_register_type(void)
 --
-.25.1
+.20.1

-[PULL 01/23] target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
+[PULL 17/21] hw/adc: Add an ADC module for NPCM7XX
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Hao Wu <wuhaotsh@google.com>
-This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
+The ADC is part of NPCM7XX Module. Its behavior is controled by the
-(indirect branch from register other than x16/x17).  The linux kernel
+ADC_CON register. It converts one of the eight analog inputs into a
-sets this in bti_enable().
+digital input and stores it in the ADC_DATA register when enabled.
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
+Users can alter input value by using qom-set QMP command.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Message-id: 20210108190945.949196-4-wuhaotsh@google.com
 [PMM: Added missing hw/adc/trace.h file]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
-[PMM: remove stray change to makefile comment]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c                  |  2 ++
+ docs/system/arm/nuvoton.rst    |   2 +-
- tests/tcg/aarch64/bti-3.c         | 42 +++++++++++++++++++++++++++++++
+ meson.build                    |   1 +
- tests/tcg/aarch64/Makefile.target |  6 ++---
+ hw/adc/trace.h                 |   1 +
-files changed, 47 insertions(+), 3 deletions(-)
+ include/hw/adc/npcm7xx_adc.h   |  69 ++++++
- create mode 100644 tests/tcg/aarch64/bti-3.c
+ include/hw/arm/npcm7xx.h       |   2 +
  hw/adc/npcm7xx_adc.c           | 301 ++++++++++++++++++++++++++
  hw/arm/npcm7xx.c               |  24 ++-
  tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
  hw/adc/meson.build             |   1 +
  hw/adc/trace-events            |   5 +
  tests/qtest/meson.build        |   3 +-
 files changed, 783 insertions(+), 3 deletions(-)
  create mode 100644 hw/adc/trace.h
  create mode 100644 include/hw/adc/npcm7xx_adc.h
  create mode 100644 hw/adc/npcm7xx_adc.c
  create mode 100644 tests/qtest/npcm7xx_adc-test.c
  create mode 100644 hw/adc/trace-events
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/docs/system/arm/nuvoton.rst
-+++ b/target/arm/cpu.c
++++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ Supported devices
-         /* Enable all PAC keys.  */
+  * Random Number Generator (RNG)
-         env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
+  * USB host (USBH)
-                                   SCTLR_EnDA | SCTLR_EnDB);
+  * GPIO controller
-+        /* Trap on btype=3 for PACIxSP. */
++ * Analog to Digital Converter (ADC)
-+        env->cp15.sctlr_el[1] |= SCTLR_BT0;
-         /* and to the FP/Neon instructions */
+ Missing devices
-         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
+ ---------------
-         /* and to the SVE instructions */
+@@ -XXX,XX +XXX,XX @@ Missing devices
-diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
+  * USB device (USBD)
   * SMBus controller (SMBF)
   * Peripheral SPI controller (PSPI)
 - * Analog to Digital Converter (ADC)
   * SD/MMC host
   * PECI interface
   * Pulse Width Modulation (PWM)
 diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/meson.build
 +++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
      'chardev',
      'hw/9pfs',
      'hw/acpi',
 +    'hw/adc',
      'hw/alpha',
      'hw/arm',
      'hw/audio',
 diff --git a/hw/adc/trace.h b/hw/adc/trace.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/tests/tcg/aarch64/bti-3.c
++++ b/hw/adc/trace.h
@@ -0,0 +1 @@
 +#include "trace/trace-hw_adc.h"
 diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/adc/npcm7xx_adc.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * BTI vs PACIASP
++ * Nuvoton NPCM7xx ADC Module
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
-+
++#ifndef NPCM7XX_ADC_H
-+#include "bti-crt.inc.c"
++#define NPCM7XX_ADC_H
 +
-+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
++#include "hw/clock.h"
-+{
++#include "hw/irq.h"
-+    uc->uc_mcontext.pc += 8;
++#include "hw/sysbus.h"
-+    uc->uc_mcontext.pstate = 1;
++#include "qemu/timer.h"
-+}
++
-+
++#define NPCM7XX_ADC_NUM_INPUTS      8
-+#define BTYPE_1() \
++/**
-+    asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
++ * This value should not be changed unless write_adc_calibration function in
-+        : "=r"(skipped) : : "x16", "x30")
++ * hw/arm/npcm7xx.c is also changed.
-+
++ */
-+#define BTYPE_2() \
++#define NPCM7XX_ADC_NUM_CALIB       2
-+    asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
++
-+        : "=r"(skipped) : : "x16", "x30")
++/**
-+
++ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
-+#define BTYPE_3() \
++ * @parent: System bus device.
-+    asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
++ * @iomem: Memory region through which registers are accessed.
-+        : "=r"(skipped) : : "x15", "x30")
++ * @conv_timer: The timer counts down remaining cycles for the conversion.
-+
++ * @irq: GIC interrupt line to fire on expiration (if enabled).
-+#define TEST(WHICH, EXPECT) \
++ * @con: The Control Register.
-+    do { WHICH(); fail += skipped ^ EXPECT; } while (0)
++ * @data: The Data Buffer.
-+
++ * @clock: The ADC Clock.
-+int main()
++ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
-+{
++ * @vref: The external reference voltage.
-+    int fail = 0;
++ * @iref: The internal reference voltage, initialized at launch time.
-+    int skipped;
++ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
-+
++ */
-+    /* Signal-like with SA_SIGINFO.  */
++typedef struct {
-+    signal_info(SIGILL, skip2_sigill);
++    SysBusDevice parent;
 +
-+    /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
++    MemoryRegion iomem;
-+    TEST(BTYPE_1, 0);
++
-+    TEST(BTYPE_2, 0);
++    QEMUTimer    conv_timer;
-+    TEST(BTYPE_3, 1);
++
-+
++    qemu_irq     irq;
-+    return fail;
++    uint32_t     con;
-+}
++    uint32_t     data;
-diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
++    Clock       *clock;
 +
 +    /* Voltages are in unit of uV. 1V = 1000000uV. */
 +    uint32_t     adci[NPCM7XX_ADC_NUM_INPUTS];
 +    uint32_t     vref;
 +    uint32_t     iref;
 +
 +    uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
 +} NPCM7xxADCState;
 +
 +#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
 +#define NPCM7XX_ADC(obj) \
 +    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
 +
 +#endif /* NPCM7XX_ADC_H */
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
---- a/tests/tcg/aarch64/Makefile.target
+--- a/include/hw/arm/npcm7xx.h
-+++ b/tests/tcg/aarch64/Makefile.target
++++ b/include/hw/arm/npcm7xx.h
-@@ -XXX,XX +XXX,XX @@ endif
+@@ -XXX,XX +XXX,XX @@
- # BTI Tests
+ #define NPCM7XX_H
- # bti-1 tests the elf notes, so we require special compiler support.
- ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
+ #include "hw/boards.h"
--AARCH64_TESTS += bti-1
++#include "hw/adc/npcm7xx_adc.h"
--bti-1: CFLAGS += -mbranch-protection=standard
+ #include "hw/cpu/a9mpcore.h"
--bti-1: LDFLAGS += -nostdlib
+ #include "hw/gpio/npcm7xx_gpio.h"
-+AARCH64_TESTS += bti-1 bti-3
+ #include "hw/mem/npcm7xx_mc.h"
-+bti-1 bti-3: CFLAGS += -mbranch-protection=standard
+@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
-+bti-1 bti-3: LDFLAGS += -nostdlib
+     NPCM7xxGCRState     gcr;
- endif
+     NPCM7xxCLKState     clk;
- # bti-2 tests PROT_BTI, so no special compiler support required.
+     NPCM7xxTimerCtrlState tim[3];
- AARCH64_TESTS += bti-2
++    NPCM7xxADCState     adc;
      NPCM7xxOTPState     key_storage;
      NPCM7xxOTPState     fuse_array;
      NPCM7xxMCState      mc;
 diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/adc/npcm7xx_adc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx ADC Module
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/adc/npcm7xx_adc.h"
 +#include "hw/qdev-clock.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/registerfields.h"
 +#include "migration/vmstate.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/timer.h"
 +#include "qemu/units.h"
 +#include "trace.h"
 +
 +REG32(NPCM7XX_ADC_CON, 0x0)
 +REG32(NPCM7XX_ADC_DATA, 0x4)
 +
 +/* Register field definitions. */
 +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
 +#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
 +#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
 +#define NPCM7XX_ADC_CON_INT     BIT(18)
 +#define NPCM7XX_ADC_CON_EN      BIT(17)
 +#define NPCM7XX_ADC_CON_RST     BIT(16)
 +#define NPCM7XX_ADC_CON_CONV    BIT(14)
 +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
 +
 +#define NPCM7XX_ADC_MAX_RESULT      1023
 +#define NPCM7XX_ADC_DEFAULT_IREF    2000000
 +#define NPCM7XX_ADC_CONV_CYCLES     20
 +#define NPCM7XX_ADC_RESET_CYCLES    10
 +#define NPCM7XX_ADC_R0_INPUT        500000
 +#define NPCM7XX_ADC_R1_INPUT        1500000
 +
 +static void npcm7xx_adc_reset(NPCM7xxADCState *s)
 +{
 +    timer_del(&s->conv_timer);
 +    s->con = 0x000c0001;
 +    s->data = 0x00000000;
 +}
 +
 +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
 +{
 +    uint32_t result;
 +
 +    result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
 +    if (result > NPCM7XX_ADC_MAX_RESULT) {
 +        result = NPCM7XX_ADC_MAX_RESULT;
 +    }
 +
 +    return result;
 +}
 +
 +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
 +{
 +    return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
 +}
 +
 +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
 +        uint32_t cycles, uint32_t prescaler)
 +{
 +    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    int64_t ticks = cycles;
 +    int64_t ns;
 +
 +    ticks *= prescaler;
 +    ns = clock_ticks_to_ns(clk, ticks);
 +    ns += now;
 +    timer_mod(timer, ns);
 +}
 +
 +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
 +{
 +    uint32_t prescaler = npcm7xx_adc_prescaler(s);
 +
 +    npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
 +            prescaler);
 +}
 +
 +static void npcm7xx_adc_convert_done(void *opaque)
 +{
 +    NPCM7xxADCState *s = opaque;
 +    uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
 +    uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
 +        ? s->iref : s->vref;
 +
 +    if (input >= NPCM7XX_ADC_NUM_INPUTS) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
 +                      __func__, input);
 +        return;
 +    }
 +    s->data = npcm7xx_adc_convert(s->adci[input], ref);
 +    if (s->con & NPCM7XX_ADC_CON_INT_EN) {
 +        s->con |= NPCM7XX_ADC_CON_INT;
 +        qemu_irq_raise(s->irq);
 +    }
 +    s->con &= ~NPCM7XX_ADC_CON_CONV;
 +}
 +
 +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
 +{
 +    adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
 +            adc->iref);
 +    adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
 +            adc->iref);
 +}
 +
 +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
 +{
 +    uint32_t old_con = s->con;
 +
 +    /* Write ADC_INT to 1 to clear it */
 +    if (new_con & NPCM7XX_ADC_CON_INT) {
 +        new_con &= ~NPCM7XX_ADC_CON_INT;
 +        qemu_irq_lower(s->irq);
 +    } else if (old_con & NPCM7XX_ADC_CON_INT) {
 +        new_con |= NPCM7XX_ADC_CON_INT;
 +    }
 +
 +    s->con = new_con;
 +
 +    if (s->con & NPCM7XX_ADC_CON_RST) {
 +        npcm7xx_adc_reset(s);
 +        return;
 +    }
 +
 +    if ((s->con & NPCM7XX_ADC_CON_EN)) {
 +        if (s->con & NPCM7XX_ADC_CON_CONV) {
 +            if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
 +                npcm7xx_adc_start_convert(s);
 +            }
 +        } else {
 +            timer_del(&s->conv_timer);
 +        }
 +    }
 +}
 +
 +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint64_t value = 0;
 +    NPCM7xxADCState *s = opaque;
 +
 +    switch (offset) {
 +    case A_NPCM7XX_ADC_CON:
 +        value = s->con;
 +        break;
 +
 +    case A_NPCM7XX_ADC_DATA:
 +        value = s->data;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
 +    return value;
 +}
 +
 +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
 +        unsigned size)
 +{
 +    NPCM7xxADCState *s = opaque;
 +
 +    trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
 +    switch (offset) {
 +    case A_NPCM7XX_ADC_CON:
 +        npcm7xx_adc_write_con(s, v);
 +        break;
 +
 +    case A_NPCM7XX_ADC_DATA:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_adc_ops = {
 +    .read       = npcm7xx_adc_read,
 +    .write      = npcm7xx_adc_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +
 +    npcm7xx_adc_reset(s);
 +}
 +
 +static void npcm7xx_adc_hold_reset(Object *obj)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +
 +    qemu_irq_lower(s->irq);
 +}
 +
 +static void npcm7xx_adc_init(Object *obj)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +
 +    timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
 +            npcm7xx_adc_convert_done, s);
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
 +                          TYPE_NPCM7XX_ADC, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
 +
 +    for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
 +        object_property_add_uint32_ptr(obj, "adci[*]",
 +                &s->adci[i], OBJ_PROP_FLAG_WRITE);
 +    }
 +    object_property_add_uint32_ptr(obj, "vref",
 +            &s->vref, OBJ_PROP_FLAG_WRITE);
 +    npcm7xx_adc_calibrate(s);
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_adc = {
 +    .name = "npcm7xx-adc",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
 +        VMSTATE_UINT32(con, NPCM7xxADCState),
 +        VMSTATE_UINT32(data, NPCM7xxADCState),
 +        VMSTATE_CLOCK(clock, NPCM7xxADCState),
 +        VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
 +        VMSTATE_UINT32(vref, NPCM7xxADCState),
 +        VMSTATE_UINT32(iref, NPCM7xxADCState),
 +        VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
 +                NPCM7XX_ADC_NUM_CALIB),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static Property npcm7xx_timer_properties[] = {
 +    DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx ADC Module";
 +    dc->vmsd = &vmstate_npcm7xx_adc;
 +    rc->phases.enter = npcm7xx_adc_enter_reset;
 +    rc->phases.hold = npcm7xx_adc_hold_reset;
 +
 +    device_class_set_props(dc, npcm7xx_timer_properties);
 +}
 +
 +static const TypeInfo npcm7xx_adc_info = {
 +    .name               = TYPE_NPCM7XX_ADC,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxADCState),
 +    .class_init         = npcm7xx_adc_class_init,
 +    .instance_init      = npcm7xx_adc_init,
 +};
 +
 +static void npcm7xx_adc_register_types(void)
 +{
 +    type_register_static(&npcm7xx_adc_info);
 +}
 +
 +type_init(npcm7xx_adc_register_types);
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_EHCI_BA         (0xf0806000)
  #define NPCM7XX_OHCI_BA         (0xf0807000)
 +/* ADC Module */
 +#define NPCM7XX_ADC_BA          (0xf000c000)
 +
  /* Internal AHB SRAM */
  #define NPCM7XX_RAM3_BA         (0xc0008000)
  #define NPCM7XX_RAM3_SZ         (4 * KiB)
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_ROM_BA          (0xffff0000)
  #define NPCM7XX_ROM_SZ          (64 * KiB)
 +
  /* Clock configuration values to be fixed up when bypassing bootloader */
  /* Run PLL1 at 1600 MHz */
@@ -XXX,XX +XXX,XX @@
   * interrupts.
   */
  enum NPCM7xxInterrupt {
 +    NPCM7XX_ADC_IRQ             = 0,
      NPCM7XX_UART0_IRQ           = 2,
      NPCM7XX_UART1_IRQ,
      NPCM7XX_UART2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
                              sizeof(value));
  }
 +static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
 +{
 +    /* Both ADC and the fuse array must have realized. */
 +    QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
 +    npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
 +            NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
 +}
 +
  static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
  {
      return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
                              TYPE_NPCM7XX_FUSE_ARRAY);
      object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
      object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
 +    object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
          object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 +    /* ADC Modules. Cannot fail. */
 +    qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
 +                          DEVICE(&s->clk), "adc-clock"));
 +    sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
 +            npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
 +    npcm7xx_write_adc_calibration(s);
 +
      /* Timer Modules (TIM). Cannot fail. */
      QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
      create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
      create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
 diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/npcm7xx_adc-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTests for Nuvoton NPCM7xx ADCModules.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/timer.h"
 +#include "libqos/libqtest.h"
 +#include "qapi/qmp/qdict.h"
 +
 +#define REF_HZ          (25000000)
 +
 +#define CON_OFFSET      0x0
 +#define DATA_OFFSET     0x4
 +
 +#define NUM_INPUTS      8
 +#define DEFAULT_IREF    2000000
 +#define CONV_CYCLES     20
 +#define RESET_CYCLES    10
 +#define R0_INPUT        500000
 +#define R1_INPUT        1500000
 +#define MAX_RESULT      1023
 +
 +#define DEFAULT_CLKDIV  5
 +
 +#define FUSE_ARRAY_BA   0xf018a000
 +#define FCTL_OFFSET     0x14
 +#define FST_OFFSET      0x0
 +#define FADDR_OFFSET    0x4
 +#define FDATA_OFFSET    0x8
 +#define ADC_CALIB_ADDR  24
 +#define FUSE_READ       0x2
 +
 +/* Register field definitions. */
 +#define CON_MUX(rv) ((rv) << 24)
 +#define CON_INT_EN  BIT(21)
 +#define CON_REFSEL  BIT(19)
 +#define CON_INT     BIT(18)
 +#define CON_EN      BIT(17)
 +#define CON_RST     BIT(16)
 +#define CON_CONV    BIT(14)
 +#define CON_DIV(rv) extract32(rv, 1, 8)
 +
 +#define FST_RDST    BIT(1)
 +#define FDATA_MASK  0xff
 +
 +#define MAX_ERROR   10000
 +#define MIN_CALIB_INPUT 100000
 +#define MAX_CALIB_INPUT 1800000
 +
 +static const uint32_t input_list[] = {
 +    100000,
 +    500000,
 +    1000000,
 +    1500000,
 +    1800000,
 +    2000000,
 +};
 +
 +static const uint32_t vref_list[] = {
 +    2000000,
 +    2200000,
 +    2500000,
 +};
 +
 +static const uint32_t iref_list[] = {
 +    1800000,
 +    1900000,
 +    2000000,
 +    2100000,
 +    2200000,
 +};
 +
 +static const uint32_t div_list[] = {0, 1, 3, 7, 15};
 +
 +typedef struct ADC {
 +    int irq;
 +    uint64_t base_addr;
 +} ADC;
 +
 +ADC adc = {
 +    .irq        = 0,
 +    .base_addr  = 0xf000c000
 +};
 +
 +static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
 +{
 +    return qtest_readl(qts, adc->base_addr + CON_OFFSET);
 +}
 +
 +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
 +{
 +    qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
 +}
 +
 +static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
 +{
 +    return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
 +}
 +
 +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
 +{
 +    return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
 +        / (int32_t)(rv[1] - rv[0]);
 +}
 +
 +static void adc_qom_set(QTestState *qts, const ADC *adc,
 +        const char *name, uint32_t value)
 +{
 +    QDict *response;
 +    const char *path = "/machine/soc/adc";
 +
 +    g_test_message("Setting properties %s of %s with value %u",
 +            name, path, value);
 +    response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
 +            " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
 +            path, name, value);
 +    /* The qom set message returns successfully. */
 +    g_assert_true(qdict_haskey(response, "return"));
 +}
 +
 +static void adc_write_input(QTestState *qts, const ADC *adc,
 +        uint32_t index, uint32_t value)
 +{
 +    char name[100];
 +
 +    sprintf(name, "adci[%u]", index);
 +    adc_qom_set(qts, adc, name, value);
 +}
 +
 +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
 +{
 +    adc_qom_set(qts, adc, "vref", value);
 +}
 +
 +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
 +{
 +    uint32_t output;
 +
 +    g_assert_cmpuint(input, <=, ref);
 +    output = (input * (MAX_RESULT + 1)) / ref;
 +    if (output > MAX_RESULT) {
 +        output = MAX_RESULT;
 +    }
 +
 +    return output;
 +}
 +
 +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
 +{
 +    uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
 +
 +    return 2 * (div + 1);
 +}
 +
 +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
 +        uint32_t clkdiv)
 +{
 +    return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
 +}
 +
 +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
 +        uint32_t clkdiv)
 +{
 +    uint32_t prescaler = adc_prescaler(qts, adc);
 +
 +    /*
 +     * ADC should takes roughly 20 cycles to convert one sample. So we assert it
 +     * should take 10~30 cycles here.
 +     */
 +    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
 +                clkdiv));
 +    /* ADC is still converting. */
 +    g_assert_true(adc_read_con(qts, adc) & CON_CONV);
 +    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
 +    /* ADC has finished conversion. */
 +    g_assert_false(adc_read_con(qts, adc) & CON_CONV);
 +}
 +
 +/* Check ADC can be reset to default value. */
 +static void test_init(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    adc_write_con(qts, adc, CON_REFSEL | CON_INT);
 +    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC can convert from an internal reference. */
 +static void test_convert_internal(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +
 +    for (index = 0; index < NUM_INPUTS; ++index) {
 +        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            input = input_list[i];
 +            expected_output = adc_calculate_output(input, DEFAULT_IREF);
 +
 +            adc_write_input(qts, adc, index, input);
 +            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
 +                    CON_EN | CON_CONV);
 +            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +            g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
 +                    CON_REFSEL | CON_EN);
 +            g_assert_false(qtest_get_irq(qts, adc->irq));
 +            output = adc_read_data(qts, adc);
 +            g_assert_cmpuint(output, ==, expected_output);
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC can convert from an external reference. */
 +static void test_convert_external(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, vref, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +
 +    for (index = 0; index < NUM_INPUTS; ++index) {
 +        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
 +                input = input_list[i];
 +                vref = vref_list[j];
 +                expected_output = adc_calculate_output(input, vref);
 +
 +                adc_write_input(qts, adc, index, input);
 +                adc_write_vref(qts, adc, vref);
 +                adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
 +                        CON_CONV);
 +                adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +                g_assert_cmphex(adc_read_con(qts, adc), ==,
 +                        CON_MUX(index) | CON_EN);
 +                g_assert_false(qtest_get_irq(qts, adc->irq));
 +                output = adc_read_data(qts, adc);
 +                g_assert_cmpuint(output, ==, expected_output);
 +            }
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC interrupt files if and only if CON_INT_EN is set. */
 +static void test_interrupt(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +
 +    index = 1;
 +    input = input_list[1];
 +    expected_output = adc_calculate_output(input, DEFAULT_IREF);
 +
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +    adc_write_input(qts, adc, index, input);
 +    g_assert_false(qtest_get_irq(qts, adc->irq));
 +    adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
 +            | CON_EN | CON_CONV);
 +    adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
 +            | CON_REFSEL | CON_INT | CON_EN);
 +    g_assert_true(qtest_get_irq(qts, adc->irq));
 +    output = adc_read_data(qts, adc);
 +    g_assert_cmpuint(output, ==, expected_output);
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
 +static void test_reset(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +
 +    for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
 +        uint32_t div = div_list[i];
 +
 +        adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
 +        qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
 +                    adc_prescaler(qts, adc), DEFAULT_CLKDIV));
 +        g_assert_false(adc_read_con(qts, adc) & CON_EN);
 +    }
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC Calibration works as desired. */
 +static void test_calibrate(gconstpointer adc_p)
 +{
 +    int i, j;
 +    const ADC *adc = adc_p;
 +
 +    for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
 +        uint32_t iref = iref_list[j];
 +        uint32_t expected_rv[] = {
 +            adc_calculate_output(R0_INPUT, iref),
 +            adc_calculate_output(R1_INPUT, iref),
 +        };
 +        char buf[100];
 +        QTestState *qts;
 +
 +        sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
 +        qts = qtest_init(buf);
 +
 +        /* Check the converted value is correct using the calibration value. */
 +        for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            uint32_t input;
 +            uint32_t output;
 +            uint32_t expected_output;
 +            uint32_t calibrated_voltage;
 +            uint32_t index = 0;
 +
 +            input = input_list[i];
 +            /* Calibration only works for input range 0.1V ~ 1.8V. */
 +            if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
 +                continue;
 +            }
 +            expected_output = adc_calculate_output(input, iref);
 +
 +            adc_write_input(qts, adc, index, input);
 +            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
 +                    CON_EN | CON_CONV);
 +            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +            g_assert_cmphex(adc_read_con(qts, adc), ==,
 +                    CON_REFSEL | CON_MUX(index) | CON_EN);
 +            output = adc_read_data(qts, adc);
 +            g_assert_cmpuint(output, ==, expected_output);
 +
 +            calibrated_voltage = adc_calibrate(output, expected_rv);
 +            g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
 +            g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
 +        }
 +
 +        qtest_quit(qts);
 +    }
 +}
 +
 +static void adc_add_test(const char *name, const ADC* wd,
 +        GTestDataFunc fn)
 +{
 +    g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s",  name);
 +    qtest_add_data_func(full_name, wd, fn);
 +}
 +#define add_test(name, td) adc_add_test(#name, td, test_##name)
 +
 +int main(int argc, char **argv)
 +{
 +    g_test_init(&argc, &argv, NULL);
 +
 +    add_test(init, &adc);
 +    add_test(convert_internal, &adc);
 +    add_test(convert_external, &adc);
 +    add_test(interrupt, &adc);
 +    add_test(reset, &adc);
 +    add_test(calibrate, &adc);
 +
 +    return g_test_run();
 +}
 diff --git a/hw/adc/meson.build b/hw/adc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/adc/meson.build
 +++ b/hw/adc/meson.build
@@ -1 +1,2 @@
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
 +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
 diff --git a/hw/adc/trace-events b/hw/adc/trace-events
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/adc/trace-events
@@ -XXX,XX +XXX,XX @@
 +# See docs/devel/tracing.txt for syntax documentation.
 +
 +# npcm7xx_adc.c
 +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
 +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/meson.build
 +++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
    ['prom-env-test', 'boot-serial-test']
  qtests_npcm7xx = \
 -  ['npcm7xx_gpio-test',
 +  ['npcm7xx_adc-test',
 +   'npcm7xx_gpio-test',
     'npcm7xx_rng-test',
     'npcm7xx_timer-test',
     'npcm7xx_watchdog_timer-test']
 --
-.25.1
+.20.1

-[PULL 02/23] target/arm: Split out cpregs.h
+[PULL 18/21] hw/misc: Add a PWM module for NPCM7XX
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Hao Wu <wuhaotsh@google.com>
-Move ARMCPRegInfo and all related declarations to a new
+The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
-internal header, out of the public cpu.h.
+identical PWM modules. Each module contains 4 PWM entries. Each PWM has
 two outputs: frequency and duty_cycle. Both are computed using inputs
 from software side.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+This module does not model detail pulse signals since it is expensive.
 It also does not model interrupts and watchdogs that are dependant on
 the detail models. The interfaces for these are left in the module so
 that anyone in need for these functionalities can implement on their
 own.
 The user can read the duty cycle and frequency using qom-get command.
 Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Message-id: 20210108190945.949196-5-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h        | 413 +++++++++++++++++++++++++++++++++++++
+ docs/system/arm/nuvoton.rst   |   2 +-
- target/arm/cpu.h           | 368 ---------------------------------
+ include/hw/arm/npcm7xx.h      |   2 +
- hw/arm/pxa2xx.c            |   1 +
+ include/hw/misc/npcm7xx_pwm.h | 105 +++++++
- hw/arm/pxa2xx_pic.c        |   1 +
+ hw/arm/npcm7xx.c              |  26 +-
- hw/intc/arm_gicv3_cpuif.c  |   1 +
+ hw/misc/npcm7xx_pwm.c         | 550 ++++++++++++++++++++++++++++++++++
- hw/intc/arm_gicv3_kvm.c    |   2 +
+ hw/misc/meson.build           |   1 +
- target/arm/cpu.c           |   1 +
+ hw/misc/trace-events          |   6 +
- target/arm/cpu64.c         |   1 +
+files changed, 689 insertions(+), 3 deletions(-)
- target/arm/cpu_tcg.c       |   1 +
+ create mode 100644 include/hw/misc/npcm7xx_pwm.h
- target/arm/gdbstub.c       |   3 +-
+ create mode 100644 hw/misc/npcm7xx_pwm.c
  target/arm/helper.c        |   1 +
  target/arm/op_helper.c     |   1 +
  target/arm/translate-a64.c |   4 +-
  target/arm/translate.c     |   3 +-
 files changed, 427 insertions(+), 374 deletions(-)
  create mode 100644 target/arm/cpregs.h
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/nuvoton.rst
 +++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
   * USB host (USBH)
   * GPIO controller
   * Analog to Digital Converter (ADC)
 + * Pulse Width Modulation (PWM)
  Missing devices
  ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
   * Peripheral SPI controller (PSPI)
   * SD/MMC host
   * PECI interface
 - * Pulse Width Modulation (PWM)
   * Tachometer
   * PCI and PCIe root complex and bridges
   * VDM and MCTP support
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/npcm7xx.h
 +++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/mem/npcm7xx_mc.h"
  #include "hw/misc/npcm7xx_clk.h"
  #include "hw/misc/npcm7xx_gcr.h"
 +#include "hw/misc/npcm7xx_pwm.h"
  #include "hw/misc/npcm7xx_rng.h"
  #include "hw/nvram/npcm7xx_otp.h"
  #include "hw/timer/npcm7xx_timer.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
      NPCM7xxCLKState     clk;
      NPCM7xxTimerCtrlState tim[3];
      NPCM7xxADCState     adc;
 +    NPCM7xxPWMState     pwm[2];
      NPCM7xxOTPState     key_storage;
      NPCM7xxOTPState     fuse_array;
      NPCM7xxMCState      mc;
 diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/arm/cpregs.h
++++ b/include/hw/misc/npcm7xx_pwm.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * QEMU ARM CP Register access and descriptions
++ * Nuvoton NPCM7xx PWM Module
 + *
-+ * Copyright (c) 2022 Linaro Ltd
++ * Copyright 2020 Google LLC
 + *
-+ * This program is free software; you can redistribute it and/or
++ * This program is free software; you can redistribute it and/or modify it
-+ * modify it under the terms of the GNU General Public License
++ * under the terms of the GNU General Public License as published by the
-+ * as published by the Free Software Foundation; either version 2
++ * Free Software Foundation; either version 2 of the License, or
-+ * of the License, or (at your option) any later version.
++ * (at your option) any later version.
 + *
-+ * This program is distributed in the hope that it will be useful,
++ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * GNU General Public License for more details.
++ * for more details.
 + */
 +#ifndef NPCM7XX_PWM_H
 +#define NPCM7XX_PWM_H
 +
 +#include "hw/clock.h"
 +#include "hw/sysbus.h"
 +#include "hw/irq.h"
 +
 +/* Each PWM module holds 4 PWM channels. */
 +#define NPCM7XX_PWM_PER_MODULE 4
 +
 +/*
 + * Number of registers in one pwm module. Don't change this without increasing
 + * the version_id in vmstate.
 + */
 +#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
 +
 +/*
 + * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
 + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
 + * value of 100,000 the duty cycle for that PWM is 10%.
 + */
 +#define NPCM7XX_PWM_MAX_DUTY 1000000
 +
 +typedef struct NPCM7xxPWMState NPCM7xxPWMState;
 +
 +/**
 + * struct NPCM7xxPWM - The state of a single PWM channel.
 + * @module: The PWM module that contains this channel.
 + * @irq: GIC interrupt line to fire on expiration if enabled.
 + * @running: Whether this PWM channel is generating output.
 + * @inverted: Whether this PWM channel is inverted.
 + * @index: The index of this PWM channel.
 + * @cnr: The counter register.
 + * @cmr: The comparator register.
 + * @pdr: The data register.
 + * @pwdr: The watchdog register.
 + * @freq: The frequency of this PWM channel.
 + * @duty: The duty cycle of this PWM channel. One unit represents
 + *   1/NPCM7XX_MAX_DUTY cycles.
 + */
 +typedef struct NPCM7xxPWM {
 +    NPCM7xxPWMState         *module;
 +
 +    qemu_irq                irq;
 +
 +    bool                    running;
 +    bool                    inverted;
 +
 +    uint8_t                 index;
 +    uint32_t                cnr;
 +    uint32_t                cmr;
 +    uint32_t                pdr;
 +    uint32_t                pwdr;
 +
 +    uint32_t                freq;
 +    uint32_t                duty;
 +} NPCM7xxPWM;
 +
 +/**
 + * struct NPCM7xxPWMState - Pulse Width Modulation device state.
 + * @parent: System bus device.
 + * @iomem: Memory region through which registers are accessed.
 + * @clock: The PWM clock.
 + * @pwm: The PWM channels owned by this module.
 + * @ppr: The prescaler register.
 + * @csr: The clock selector register.
 + * @pcr: The control register.
 + * @pier: The interrupt enable register.
 + * @piir: The interrupt indication register.
 + */
 +struct NPCM7xxPWMState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    Clock       *clock;
 +    NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
 +
 +    uint32_t    ppr;
 +    uint32_t    csr;
 +    uint32_t    pcr;
 +    uint32_t    pier;
 +    uint32_t    piir;
 +};
 +
 +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
 +#define NPCM7XX_PWM(obj) \
 +    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
 +
 +#endif /* NPCM7XX_PWM_H */
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
      NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
      NPCM7XX_EHCI_IRQ            = 61,
      NPCM7XX_OHCI_IRQ            = 62,
 +    NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
 +    NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
      NPCM7XX_GPIO0_IRQ           = 116,
      NPCM7XX_GPIO1_IRQ,
      NPCM7XX_GPIO2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
 xb8000000, /* CS3 */
  };
 +/* Register base address for each PWM Module */
 +static const hwaddr npcm7xx_pwm_addr[] = {
 +    0xf0103000,
 +    0xf0104000,
 +};
 +
  static const struct {
      hwaddr regs_addr;
      uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
          object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
                                  TYPE_NPCM7XX_FIU);
      }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
 +        object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
 +    }
  }
  static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
                         npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 +    /* PWM Modules. Cannot fail. */
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
 +    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
 +        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
 +
 +        qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
 +                    DEVICE(&s->clk), "apb3-clock"));
 +        sysbus_realize(sbd, &error_abort);
 +        sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
 +        sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
 +    }
 +
      /*
       * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
       * specified, but this is a programming error.
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
      create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
      create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
 diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/npcm7xx_pwm.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx PWM Module
 + *
-+ * You should have received a copy of the GNU General Public License
++ * Copyright 2020 Google LLC
-+ * along with this program; if not, see
++ *
-+ * <http://www.gnu.org/licenses/gpl-2.0.html>
++ * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
-+#ifndef TARGET_ARM_CPREGS_H
++#include "qemu/osdep.h"
-+#define TARGET_ARM_CPREGS_H
++#include "hw/irq.h"
-+
++#include "hw/qdev-clock.h"
-+/*
++#include "hw/qdev-properties.h"
-+ * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
++#include "hw/misc/npcm7xx_pwm.h"
-+ * special-behaviour cp reg and bits [11..8] indicate what behaviour
++#include "hw/registerfields.h"
-+ * it has. Otherwise it is a simple cp reg, where CONST indicates that
++#include "migration/vmstate.h"
-+ * TCG can assume the value to be constant (ie load at translate time)
++#include "qemu/bitops.h"
-+ * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
++#include "qemu/error-report.h"
-+ * indicates that the TB should not be ended after a write to this register
++#include "qemu/log.h"
-+ * (the default is that the TB ends after cp writes). OVERRIDE permits
++#include "qemu/module.h"
-+ * a register definition to override a previous definition for the
++#include "qemu/units.h"
-+ * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
++#include "trace.h"
-+ * old must have the OVERRIDE bit set.
++
-+ * ALIAS indicates that this register is an alias view of some underlying
++REG32(NPCM7XX_PWM_PPR, 0x00);
-+ * state which is also visible via another register, and that the other
++REG32(NPCM7XX_PWM_CSR, 0x04);
-+ * register is handling migration and reset; registers marked ALIAS will not be
++REG32(NPCM7XX_PWM_PCR, 0x08);
-+ * migrated but may have their state set by syncing of register state from KVM.
++REG32(NPCM7XX_PWM_CNR0, 0x0c);
-+ * NO_RAW indicates that this register has no underlying state and does not
++REG32(NPCM7XX_PWM_CMR0, 0x10);
-+ * support raw access for state saving/loading; it will not be used for either
++REG32(NPCM7XX_PWM_PDR0, 0x14);
-+ * migration or KVM state synchronization. (Typically this is for "registers"
++REG32(NPCM7XX_PWM_CNR1, 0x18);
-+ * which are actually used as instructions for cache maintenance and so on.)
++REG32(NPCM7XX_PWM_CMR1, 0x1c);
-+ * IO indicates that this register does I/O and therefore its accesses
++REG32(NPCM7XX_PWM_PDR1, 0x20);
-+ * need to be marked with gen_io_start() and also end the TB. In particular,
++REG32(NPCM7XX_PWM_CNR2, 0x24);
-+ * registers which implement clocks or timers require this.
++REG32(NPCM7XX_PWM_CMR2, 0x28);
-+ * RAISES_EXC is for when the read or write hook might raise an exception;
++REG32(NPCM7XX_PWM_PDR2, 0x2c);
-+ * the generated code will synchronize the CPU state before calling the hook
++REG32(NPCM7XX_PWM_CNR3, 0x30);
-+ * so that it is safe for the hook to call raise_exception().
++REG32(NPCM7XX_PWM_CMR3, 0x34);
-+ * NEWEL is for writes to registers that might change the exception
++REG32(NPCM7XX_PWM_PDR3, 0x38);
-+ * level - typically on older ARM chips. For those cases we need to
++REG32(NPCM7XX_PWM_PIER, 0x3c);
-+ * re-read the new el when recomputing the translation flags.
++REG32(NPCM7XX_PWM_PIIR, 0x40);
-+ */
++REG32(NPCM7XX_PWM_PWDR0, 0x44);
-+#define ARM_CP_SPECIAL           0x0001
++REG32(NPCM7XX_PWM_PWDR1, 0x48);
-+#define ARM_CP_CONST             0x0002
++REG32(NPCM7XX_PWM_PWDR2, 0x4c);
-+#define ARM_CP_64BIT             0x0004
++REG32(NPCM7XX_PWM_PWDR3, 0x50);
-+#define ARM_CP_SUPPRESS_TB_END   0x0008
++
-+#define ARM_CP_OVERRIDE          0x0010
++/* Register field definitions. */
-+#define ARM_CP_ALIAS             0x0020
++#define NPCM7XX_PPR(rv, index)      extract32((rv), npcm7xx_ppr_base[index], 8)
-+#define ARM_CP_IO                0x0040
++#define NPCM7XX_CSR(rv, index)      extract32((rv), npcm7xx_csr_base[index], 3)
-+#define ARM_CP_NO_RAW            0x0080
++#define NPCM7XX_CH(rv, index)       extract32((rv), npcm7xx_ch_base[index], 4)
-+#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
++#define NPCM7XX_CH_EN               BIT(0)
-+#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
++#define NPCM7XX_CH_INV              BIT(2)
-+#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
++#define NPCM7XX_CH_MOD              BIT(3)
-+#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
++
-+#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
++/* Offset of each PWM channel's prescaler in the PPR register. */
-+#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
++static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
-+#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
++/* Offset of each PWM channel's clock selector in the CSR register. */
-+#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
++static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
-+#define ARM_CP_FPU               0x1000
++/* Offset of each PWM channel's control variable in the PCR register. */
-+#define ARM_CP_SVE               0x2000
++static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
-+#define ARM_CP_NO_GDB            0x4000
++
-+#define ARM_CP_RAISES_EXC        0x8000
++static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
-+#define ARM_CP_NEWEL             0x10000
++{
-+/* Used only as a terminator for ARMCPRegInfo lists */
++    uint32_t ppr;
-+#define ARM_CP_SENTINEL          0xfffff
++    uint32_t csr;
-+/* Mask of only the flag bits in a type field */
++    uint32_t freq;
-+#define ARM_CP_FLAG_MASK         0x1f0ff
++
-+
++    if (!p->running) {
-+/*
++        return 0;
-+ * Valid values for ARMCPRegInfo state field, indicating which of
++    }
-+ * the AArch32 and AArch64 execution states this register is visible in.
++
-+ * If the reginfo doesn't explicitly specify then it is AArch32 only.
++    csr = NPCM7XX_CSR(p->module->csr, p->index);
-+ * If the reginfo is declared to be visible in both states then a second
++    ppr = NPCM7XX_PPR(p->module->ppr, p->index);
-+ * reginfo is synthesised for the AArch32 view of the AArch64 register,
++    freq = clock_get_hz(p->module->clock);
-+ * such that the AArch32 view is the lower 32 bits of the AArch64 one.
++    freq /= ppr + 1;
-+ * Note that we rely on the values of these enums as we iterate through
++    /* csr can only be 0~4 */
-+ * the various states in some places.
++    if (csr > 4) {
-+ */
++        qemu_log_mask(LOG_GUEST_ERROR,
-+enum {
++                      "%s: invalid csr value %u\n",
-+    ARM_CP_STATE_AA32 = 0,
++                      __func__, csr);
-+    ARM_CP_STATE_AA64 = 1,
++        csr = 4;
-+    ARM_CP_STATE_BOTH = 2,
++    }
 +    /* freq won't be changed if csr == 4. */
 +    if (csr < 4) {
 +        freq >>= csr + 1;
 +    }
 +
 +    return freq / (p->cnr + 1);
 +}
 +
 +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
 +{
 +    uint64_t duty;
 +
 +    if (p->running) {
 +        if (p->cnr == 0) {
 +            duty = 0;
 +        } else if (p->cmr >= p->cnr) {
 +            duty = NPCM7XX_PWM_MAX_DUTY;
 +        } else {
 +            duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
 +        }
 +    } else {
 +        duty = 0;
 +    }
 +
 +    if (p->inverted) {
 +        duty = NPCM7XX_PWM_MAX_DUTY - duty;
 +    }
 +
 +    return duty;
 +}
 +
 +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
 +{
 +    uint32_t freq = npcm7xx_pwm_calculate_freq(p);
 +
 +    if (freq != p->freq) {
 +        trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
 +                                      p->index, p->freq, freq);
 +        p->freq = freq;
 +    }
 +}
 +
 +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
 +{
 +    uint32_t duty = npcm7xx_pwm_calculate_duty(p);
 +
 +    if (duty != p->duty) {
 +        trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
 +                                      p->index, p->duty, duty);
 +        p->duty = duty;
 +    }
 +}
 +
 +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
 +{
 +    npcm7xx_pwm_update_freq(p);
 +    npcm7xx_pwm_update_duty(p);
 +}
 +
 +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
 +{
 +    int i;
 +    uint32_t old_ppr = s->ppr;
 +
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
 +    s->ppr = new_ppr;
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
 +            npcm7xx_pwm_update_freq(&s->pwm[i]);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
 +{
 +    int i;
 +    uint32_t old_csr = s->csr;
 +
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
 +    s->csr = new_csr;
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
 +            npcm7xx_pwm_update_freq(&s->pwm[i]);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
 +{
 +    int i;
 +    bool inverted;
 +    uint32_t pcr;
 +    NPCM7xxPWM *p;
 +
 +    s->pcr = new_pcr;
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        p = &s->pwm[i];
 +        pcr = NPCM7XX_CH(new_pcr, i);
 +        inverted = pcr & NPCM7XX_CH_INV;
 +
 +        /*
 +         * We only run a PWM channel with toggle mode. Single-shot mode does not
 +         * generate frequency and duty-cycle values.
 +         */
 +        if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
 +            if (p->running) {
 +                /* Re-run this PWM channel if inverted changed. */
 +                if (p->inverted ^ inverted) {
 +                    p->inverted = inverted;
 +                    npcm7xx_pwm_update_duty(p);
 +                }
 +            } else {
 +                /* Run this PWM channel. */
 +                p->running = true;
 +                p->inverted = inverted;
 +                npcm7xx_pwm_update_output(p);
 +            }
 +        } else {
 +            /* Clear this PWM channel. */
 +            p->running = false;
 +            p->inverted = inverted;
 +            npcm7xx_pwm_update_output(p);
 +        }
 +    }
 +
 +}
 +
 +static hwaddr npcm7xx_cnr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_CNR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_CNR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_CNR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_cmr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CMR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_CMR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_CMR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_CMR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_pdr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_PDR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_PDR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_PDR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_PDR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_pwdr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_PWDR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_PWDR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_PWDR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_PWDR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    NPCM7xxPWMState *s = opaque;
 +    uint64_t value = 0;
 +
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +    case A_NPCM7XX_PWM_CNR1:
 +    case A_NPCM7XX_PWM_CNR2:
 +    case A_NPCM7XX_PWM_CNR3:
 +        value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_CMR0:
 +    case A_NPCM7XX_PWM_CMR1:
 +    case A_NPCM7XX_PWM_CMR2:
 +    case A_NPCM7XX_PWM_CMR3:
 +        value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PDR0:
 +    case A_NPCM7XX_PWM_PDR1:
 +    case A_NPCM7XX_PWM_PDR2:
 +    case A_NPCM7XX_PWM_PDR3:
 +        value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PWDR0:
 +    case A_NPCM7XX_PWM_PWDR1:
 +    case A_NPCM7XX_PWM_PWDR2:
 +    case A_NPCM7XX_PWM_PWDR3:
 +        value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PPR:
 +        value = s->ppr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_CSR:
 +        value = s->csr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PCR:
 +        value = s->pcr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIER:
 +        value = s->pier;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIIR:
 +        value = s->piir;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
 +    return value;
 +}
 +
 +static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
 +                                uint64_t v, unsigned size)
 +{
 +    NPCM7xxPWMState *s = opaque;
 +    NPCM7xxPWM *p;
 +    uint32_t value = v;
 +
 +    trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +    case A_NPCM7XX_PWM_CNR1:
 +    case A_NPCM7XX_PWM_CNR2:
 +    case A_NPCM7XX_PWM_CNR3:
 +        p = &s->pwm[npcm7xx_cnr_index(offset)];
 +        p->cnr = value;
 +        npcm7xx_pwm_update_output(p);
 +        break;
 +
 +    case A_NPCM7XX_PWM_CMR0:
 +    case A_NPCM7XX_PWM_CMR1:
 +    case A_NPCM7XX_PWM_CMR2:
 +    case A_NPCM7XX_PWM_CMR3:
 +        p = &s->pwm[npcm7xx_cmr_index(offset)];
 +        p->cmr = value;
 +        npcm7xx_pwm_update_output(p);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PDR0:
 +    case A_NPCM7XX_PWM_PDR1:
 +    case A_NPCM7XX_PWM_PDR2:
 +    case A_NPCM7XX_PWM_PDR3:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PWDR0:
 +    case A_NPCM7XX_PWM_PWDR1:
 +    case A_NPCM7XX_PWM_PWDR2:
 +    case A_NPCM7XX_PWM_PWDR3:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PPR:
 +        npcm7xx_pwm_write_ppr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_CSR:
 +        npcm7xx_pwm_write_csr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PCR:
 +        npcm7xx_pwm_write_pcr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIER:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIIR:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_pwm_ops = {
 +    .read       = npcm7xx_pwm_read,
 +    .write      = npcm7xx_pwm_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
-+/*
++static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
-+ * ARM CP register secure state flags.  These flags identify security state
++{
-+ * attributes for a given CP register entry.
++    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
-+ * The existence of both or neither secure and non-secure flags indicates that
++    int i;
-+ * the register has both a secure and non-secure hash entry.  A single one of
++
-+ * these flags causes the register to only be hashed for the specified
++    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
-+ * security state.
++        NPCM7xxPWM *p = &s->pwm[i];
-+ * Although definitions may have any combination of the S/NS bits, each
++
-+ * registered entry will only have one to identify whether the entry is secure
++        p->cnr = 0x00000000;
-+ * or non-secure.
++        p->cmr = 0x00000000;
-+ */
++        p->pdr = 0x00000000;
-+enum {
++        p->pwdr = 0x00000000;
-+    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
++    }
-+    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
++
 +    s->ppr = 0x00000000;
 +    s->csr = 0x00000000;
 +    s->pcr = 0x00000000;
 +    s->pier = 0x00000000;
 +    s->piir = 0x00000000;
 +}
 +
 +static void npcm7xx_pwm_hold_reset(Object *obj)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        qemu_irq_lower(s->pwm[i].irq);
 +    }
 +}
 +
 +static void npcm7xx_pwm_init(Object *obj)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        NPCM7xxPWM *p = &s->pwm[i];
 +        p->module = s;
 +        p->index = i;
 +        sysbus_init_irq(sbd, &p->irq);
 +    }
 +
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
 +                          TYPE_NPCM7XX_PWM, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        object_property_add_uint32_ptr(obj, "freq[*]",
 +                &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
 +        object_property_add_uint32_ptr(obj, "duty[*]",
 +                &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_pwm = {
 +    .name = "npcm7xx-pwm",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_BOOL(running, NPCM7xxPWM),
 +        VMSTATE_BOOL(inverted, NPCM7xxPWM),
 +        VMSTATE_UINT8(index, NPCM7xxPWM),
 +        VMSTATE_UINT32(cnr, NPCM7xxPWM),
 +        VMSTATE_UINT32(cmr, NPCM7xxPWM),
 +        VMSTATE_UINT32(pdr, NPCM7xxPWM),
 +        VMSTATE_UINT32(pwdr, NPCM7xxPWM),
 +        VMSTATE_UINT32(freq, NPCM7xxPWM),
 +        VMSTATE_UINT32(duty, NPCM7xxPWM),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
-+/*
++static const VMStateDescription vmstate_npcm7xx_pwm_module = {
-+ * Return true if cptype is a valid type field. This is used to try to
++    .name = "npcm7xx-pwm-module",
-+ * catch errors where the sentinel has been accidentally left off the end
++    .version_id = 0,
-+ * of a list of registers.
++    .minimum_version_id = 0,
-+ */
++    .fields = (VMStateField[]) {
-+static inline bool cptype_valid(int cptype)
++        VMSTATE_CLOCK(clock, NPCM7xxPWMState),
-+{
++        VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
-+    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
++                             NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
-+        || ((cptype & ARM_CP_SPECIAL) &&
++                             NPCM7xxPWM),
-+            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
++        VMSTATE_UINT32(ppr, NPCM7xxPWMState),
-+}
++        VMSTATE_UINT32(csr, NPCM7xxPWMState),
-+
++        VMSTATE_UINT32(pcr, NPCM7xxPWMState),
-+/*
++        VMSTATE_UINT32(pier, NPCM7xxPWMState),
-+ * Access rights:
++        VMSTATE_UINT32(piir, NPCM7xxPWMState),
-+ * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
++        VMSTATE_END_OF_LIST(),
-+ * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
++    },
 + * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 + * (ie any of the privileged modes in Secure state, or Monitor mode).
 + * If a register is accessible in one privilege level it's always accessible
 + * in higher privilege levels too. Since "Secure PL1" also follows this rule
 + * (ie anything visible in PL2 is visible in S-PL1, some things are only
 + * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 + * terminology a little and call this PL3.
 + * In AArch64 things are somewhat simpler as the PLx bits line up exactly
 + * with the ELx exception levels.
 + *
 + * If access permissions for a register are more complex than can be
 + * described with these bits, then use a laxer set of restrictions, and
 + * do the more restrictive/complex check inside a helper function.
 + */
 +#define PL3_R 0x80
 +#define PL3_W 0x40
 +#define PL2_R (0x20 | PL3_R)
 +#define PL2_W (0x10 | PL3_W)
 +#define PL1_R (0x08 | PL2_R)
 +#define PL1_W (0x04 | PL2_W)
 +#define PL0_R (0x02 | PL1_R)
 +#define PL0_W (0x01 | PL1_W)
 +
 +/*
 + * For user-mode some registers are accessible to EL0 via a kernel
 + * trap-and-emulate ABI. In this case we define the read permissions
 + * as actually being PL0_R. However some bits of any given register
 + * may still be masked.
 + */
 +#ifdef CONFIG_USER_ONLY
 +#define PL0U_R PL0_R
 +#else
 +#define PL0U_R PL1_R
 +#endif
 +
 +#define PL3_RW (PL3_R | PL3_W)
 +#define PL2_RW (PL2_R | PL2_W)
 +#define PL1_RW (PL1_R | PL1_W)
 +#define PL0_RW (PL0_R | PL0_W)
 +
 +typedef enum CPAccessResult {
 +    /* Access is permitted */
 +    CP_ACCESS_OK = 0,
 +    /*
 +     * Access fails due to a configurable trap or enable which would
 +     * result in a categorized exception syndrome giving information about
 +     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
 +     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
 +     * PL1 if in EL0, otherwise to the current EL).
 +     */
 +    CP_ACCESS_TRAP = 1,
 +    /*
 +     * Access fails and results in an exception syndrome 0x0 ("uncategorized").
 +     * Note that this is not a catch-all case -- the set of cases which may
 +     * result in this failure is specifically defined by the architecture.
 +     */
 +    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
 +    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
 +    CP_ACCESS_TRAP_EL2 = 3,
 +    CP_ACCESS_TRAP_EL3 = 4,
 +    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
 +    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
 +    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
 +} CPAccessResult;
 +
 +typedef struct ARMCPRegInfo ARMCPRegInfo;
 +
 +/*
 + * Access functions for coprocessor registers. These cannot fail and
 + * may not raise exceptions.
 + */
 +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 +                       uint64_t value);
 +/* Access permission check functions for coprocessor registers. */
 +typedef CPAccessResult CPAccessFn(CPUARMState *env,
 +                                  const ARMCPRegInfo *opaque,
 +                                  bool isread);
 +/* Hook function for register reset */
 +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 +
 +#define CP_ANY 0xff
 +
 +/* Definition of an ARM coprocessor register */
 +struct ARMCPRegInfo {
 +    /* Name of register (useful mainly for debugging, need not be unique) */
 +    const char *name;
 +    /*
 +     * Location of register: coprocessor number and (crn,crm,opc1,opc2)
 +     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 +     * 'wildcard' field -- any value of that field in the MRC/MCR insn
 +     * will be decoded to this register. The register read and write
 +     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 +     * used by the program, so it is possible to register a wildcard and
 +     * then behave differently on read/write if necessary.
 +     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 +     * must both be zero.
 +     * For AArch64-visible registers, opc0 is also used.
 +     * Since there are no "coprocessors" in AArch64, cp is purely used as a
 +     * way to distinguish (for KVM's benefit) guest-visible system registers
 +     * from demuxed ones provided to preserve the "no side effects on
 +     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
 +     * visible (to match KVM's encoding); cp==0 will be converted to
 +     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
 +     */
 +    uint8_t cp;
 +    uint8_t crn;
 +    uint8_t crm;
 +    uint8_t opc0;
 +    uint8_t opc1;
 +    uint8_t opc2;
 +    /* Execution state in which this register is visible: ARM_CP_STATE_* */
 +    int state;
 +    /* Register type: ARM_CP_* bits/values */
 +    int type;
 +    /* Access rights: PL*_[RW] */
 +    int access;
 +    /* Security state: ARM_CP_SECSTATE_* bits/values */
 +    int secure;
 +    /*
 +     * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 +     * this register was defined: can be used to hand data through to the
 +     * register read/write functions, since they are passed the ARMCPRegInfo*.
 +     */
 +    void *opaque;
 +    /*
 +     * Value of this register, if it is ARM_CP_CONST. Otherwise, if
 +     * fieldoffset is non-zero, the reset value of the register.
 +     */
 +    uint64_t resetvalue;
 +    /*
 +     * Offset of the field in CPUARMState for this register.
 +     * This is not needed if either:
 +     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 +     *  2. both readfn and writefn are specified
 +     */
 +    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 +
 +    /*
 +     * Offsets of the secure and non-secure fields in CPUARMState for the
 +     * register if it is banked.  These fields are only used during the static
 +     * registration of a register.  During hashing the bank associated
 +     * with a given security state is copied to fieldoffset which is used from
 +     * there on out.
 +     *
 +     * It is expected that register definitions use either fieldoffset or
 +     * bank_fieldoffsets in the definition but not both.  It is also expected
 +     * that both bank offsets are set when defining a banked register.  This
 +     * use indicates that a register is banked.
 +     */
 +    ptrdiff_t bank_fieldoffsets[2];
 +
 +    /*
 +     * Function for making any access checks for this register in addition to
 +     * those specified by the 'access' permissions bits. If NULL, no extra
 +     * checks required. The access check is performed at runtime, not at
 +     * translate time.
 +     */
 +    CPAccessFn *accessfn;
 +    /*
 +     * Function for handling reads of this register. If NULL, then reads
 +     * will be done by loading from the offset into CPUARMState specified
 +     * by fieldoffset.
 +     */
 +    CPReadFn *readfn;
 +    /*
 +     * Function for handling writes of this register. If NULL, then writes
 +     * will be done by writing to the offset into CPUARMState specified
 +     * by fieldoffset.
 +     */
 +    CPWriteFn *writefn;
 +    /*
 +     * Function for doing a "raw" read; used when we need to copy
 +     * coprocessor state to the kernel for KVM or out for
 +     * migration. This only needs to be provided if there is also a
 +     * readfn and it has side effects (for instance clear-on-read bits).
 +     */
 +    CPReadFn *raw_readfn;
 +    /*
 +     * Function for doing a "raw" write; used when we need to copy KVM
 +     * kernel coprocessor state into userspace, or for inbound
 +     * migration. This only needs to be provided if there is also a
 +     * writefn and it masks out "unwritable" bits or has write-one-to-clear
 +     * or similar behaviour.
 +     */
 +    CPWriteFn *raw_writefn;
 +    /*
 +     * Function for resetting the register. If NULL, then reset will be done
 +     * by writing resetvalue to the field specified in fieldoffset. If
 +     * fieldoffset is 0 then no reset will be done.
 +     */
 +    CPResetFn *resetfn;
 +
 +    /*
 +     * "Original" writefn and readfn.
 +     * For ARMv8.1-VHE register aliases, we overwrite the read/write
 +     * accessor functions of various EL1/EL0 to perform the runtime
 +     * check for which sysreg should actually be modified, and then
 +     * forwards the operation.  Before overwriting the accessors,
 +     * the original function is copied here, so that accesses that
 +     * really do go to the EL1/EL0 version proceed normally.
 +     * (The corresponding EL2 register is linked via opaque.)
 +     */
 +    CPReadFn *orig_readfn;
 +    CPWriteFn *orig_writefn;
 +};
 +
-+/*
++static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
-+ * Macros which are lvalues for the field in CPUARMState for the
++{
-+ * ARMCPRegInfo *ri.
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+ */
++    DeviceClass *dc = DEVICE_CLASS(klass);
-+#define CPREG_FIELD32(env, ri) \
++
-+    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
++    dc->desc = "NPCM7xx PWM Controller";
-+#define CPREG_FIELD64(env, ri) \
++    dc->vmsd = &vmstate_npcm7xx_pwm_module;
-+    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
++    rc->phases.enter = npcm7xx_pwm_enter_reset;
-+
++    rc->phases.hold = npcm7xx_pwm_hold_reset;
-+#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
++}
 +
-+void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
++static const TypeInfo npcm7xx_pwm_info = {
-+                                    const ARMCPRegInfo *regs, void *opaque);
++    .name               = TYPE_NPCM7XX_PWM,
-+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
++    .parent             = TYPE_SYS_BUS_DEVICE,
-+                                       const ARMCPRegInfo *regs, void *opaque);
++    .instance_size      = sizeof(NPCM7xxPWMState),
-+static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
++    .class_init         = npcm7xx_pwm_class_init,
-+{
++    .instance_init      = npcm7xx_pwm_init,
-+    define_arm_cp_regs_with_opaque(cpu, regs, 0);
++};
-+}
++
-+static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
++static void npcm7xx_pwm_register_type(void)
 +{
-+    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
++    type_register_static(&npcm7xx_pwm_info);
 +}
-+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
++type_init(npcm7xx_pwm_register_type);
-+
+diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 +/*
 + * Definition of an ARM co-processor register as viewed from
 + * userspace. This is used for presenting sanitised versions of
 + * registers to userspace when emulating the Linux AArch64 CPU
 + * ID/feature ABI (advertised as HWCAP_CPUID).
 + */
 +typedef struct ARMCPRegUserSpaceInfo {
 +    /* Name of register */
 +    const char *name;
 +
 +    /* Is the name actually a glob pattern */
 +    bool is_glob;
 +
 +    /* Only some bits are exported to user space */
 +    uint64_t exported_bits;
 +
 +    /* Fixed bits are applied after the mask */
 +    uint64_t fixed_bits;
 +} ARMCPRegUserSpaceInfo;
 +
 +#define REGUSERINFO_SENTINEL { .name = NULL }
 +
 +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
 +
 +/* CPWriteFn that can be used to implement writes-ignored behaviour */
 +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 +                         uint64_t value);
 +/* CPReadFn that can be used for read-as-zero behaviour */
 +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
 +
 +/*
 + * CPResetFn that does nothing, for use if no reset is required even
 + * if fieldoffset is non zero.
 + */
 +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
 +
 +/*
 + * Return true if this reginfo struct's field in the cpu state struct
 + * is 64 bits wide.
 + */
 +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
 +{
 +    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
 +}
 +
 +static inline bool cp_access_ok(int current_el,
 +                                const ARMCPRegInfo *ri, int isread)
 +{
 +    return (ri->access >> ((current_el * 2) + isread)) & 1;
 +}
 +
 +/* Raw read of a coprocessor register (as needed for migration, etc) */
 +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
 +
 +#endif /* TARGET_ARM_CPREGS_H */
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/misc/meson.build
-+++ b/target/arm/cpu.h
++++ b/hw/misc/meson.build
-@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
+@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
-     return kvmid;
+ softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
- }
+   'npcm7xx_clk.c',
+   'npcm7xx_gcr.c',
--/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
++  'npcm7xx_pwm.c',
-- * special-behaviour cp reg and bits [11..8] indicate what behaviour
+   'npcm7xx_rng.c',
-- * it has. Otherwise it is a simple cp reg, where CONST indicates that
+ ))
-- * TCG can assume the value to be constant (ie load at translate time)
+ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
-- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
+diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 - * indicates that the TB should not be ended after a write to this register
 - * (the default is that the TB ends after cp writes). OVERRIDE permits
 - * a register definition to override a previous definition for the
 - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 - * old must have the OVERRIDE bit set.
 - * ALIAS indicates that this register is an alias view of some underlying
 - * state which is also visible via another register, and that the other
 - * register is handling migration and reset; registers marked ALIAS will not be
 - * migrated but may have their state set by syncing of register state from KVM.
 - * NO_RAW indicates that this register has no underlying state and does not
 - * support raw access for state saving/loading; it will not be used for either
 - * migration or KVM state synchronization. (Typically this is for "registers"
 - * which are actually used as instructions for cache maintenance and so on.)
 - * IO indicates that this register does I/O and therefore its accesses
 - * need to be marked with gen_io_start() and also end the TB. In particular,
 - * registers which implement clocks or timers require this.
 - * RAISES_EXC is for when the read or write hook might raise an exception;
 - * the generated code will synchronize the CPU state before calling the hook
 - * so that it is safe for the hook to call raise_exception().
 - * NEWEL is for writes to registers that might change the exception
 - * level - typically on older ARM chips. For those cases we need to
 - * re-read the new el when recomputing the translation flags.
 - */
 -#define ARM_CP_SPECIAL           0x0001
 -#define ARM_CP_CONST             0x0002
 -#define ARM_CP_64BIT             0x0004
 -#define ARM_CP_SUPPRESS_TB_END   0x0008
 -#define ARM_CP_OVERRIDE          0x0010
 -#define ARM_CP_ALIAS             0x0020
 -#define ARM_CP_IO                0x0040
 -#define ARM_CP_NO_RAW            0x0080
 -#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
 -#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
 -#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
 -#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
 -#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
 -#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
 -#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
 -#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
 -#define ARM_CP_FPU               0x1000
 -#define ARM_CP_SVE               0x2000
 -#define ARM_CP_NO_GDB            0x4000
 -#define ARM_CP_RAISES_EXC        0x8000
 -#define ARM_CP_NEWEL             0x10000
 -/* Used only as a terminator for ARMCPRegInfo lists */
 -#define ARM_CP_SENTINEL          0xfffff
 -/* Mask of only the flag bits in a type field */
 -#define ARM_CP_FLAG_MASK         0x1f0ff
 -
 -/* Valid values for ARMCPRegInfo state field, indicating which of
 - * the AArch32 and AArch64 execution states this register is visible in.
 - * If the reginfo doesn't explicitly specify then it is AArch32 only.
 - * If the reginfo is declared to be visible in both states then a second
 - * reginfo is synthesised for the AArch32 view of the AArch64 register,
 - * such that the AArch32 view is the lower 32 bits of the AArch64 one.
 - * Note that we rely on the values of these enums as we iterate through
 - * the various states in some places.
 - */
 -enum {
 -    ARM_CP_STATE_AA32 = 0,
 -    ARM_CP_STATE_AA64 = 1,
 -    ARM_CP_STATE_BOTH = 2,
 -};
 -
 -/* ARM CP register secure state flags.  These flags identify security state
 - * attributes for a given CP register entry.
 - * The existence of both or neither secure and non-secure flags indicates that
 - * the register has both a secure and non-secure hash entry.  A single one of
 - * these flags causes the register to only be hashed for the specified
 - * security state.
 - * Although definitions may have any combination of the S/NS bits, each
 - * registered entry will only have one to identify whether the entry is secure
 - * or non-secure.
 - */
 -enum {
 -    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
 -    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
 -};
 -
 -/* Return true if cptype is a valid type field. This is used to try to
 - * catch errors where the sentinel has been accidentally left off the end
 - * of a list of registers.
 - */
 -static inline bool cptype_valid(int cptype)
 -{
 -    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 -        || ((cptype & ARM_CP_SPECIAL) &&
 -            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 -}
 -
 -/* Access rights:
 - * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 - * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 - * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 - * (ie any of the privileged modes in Secure state, or Monitor mode).
 - * If a register is accessible in one privilege level it's always accessible
 - * in higher privilege levels too. Since "Secure PL1" also follows this rule
 - * (ie anything visible in PL2 is visible in S-PL1, some things are only
 - * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 - * terminology a little and call this PL3.
 - * In AArch64 things are somewhat simpler as the PLx bits line up exactly
 - * with the ELx exception levels.
 - *
 - * If access permissions for a register are more complex than can be
 - * described with these bits, then use a laxer set of restrictions, and
 - * do the more restrictive/complex check inside a helper function.
 - */
 -#define PL3_R 0x80
 -#define PL3_W 0x40
 -#define PL2_R (0x20 | PL3_R)
 -#define PL2_W (0x10 | PL3_W)
 -#define PL1_R (0x08 | PL2_R)
 -#define PL1_W (0x04 | PL2_W)
 -#define PL0_R (0x02 | PL1_R)
 -#define PL0_W (0x01 | PL1_W)
 -
 -/*
 - * For user-mode some registers are accessible to EL0 via a kernel
 - * trap-and-emulate ABI. In this case we define the read permissions
 - * as actually being PL0_R. However some bits of any given register
 - * may still be masked.
 - */
 -#ifdef CONFIG_USER_ONLY
 -#define PL0U_R PL0_R
 -#else
 -#define PL0U_R PL1_R
 -#endif
 -
 -#define PL3_RW (PL3_R | PL3_W)
 -#define PL2_RW (PL2_R | PL2_W)
 -#define PL1_RW (PL1_R | PL1_W)
 -#define PL0_RW (PL0_R | PL0_W)
 -
  /* Return the highest implemented Exception Level */
  static inline int arm_highest_el(CPUARMState *env)
  {
@@ -XXX,XX +XXX,XX @@ static inline int arm_current_el(CPUARMState *env)
      }
  }
 -typedef struct ARMCPRegInfo ARMCPRegInfo;
 -
 -typedef enum CPAccessResult {
 -    /* Access is permitted */
 -    CP_ACCESS_OK = 0,
 -    /* Access fails due to a configurable trap or enable which would
 -     * result in a categorized exception syndrome giving information about
 -     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
 -     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
 -     * PL1 if in EL0, otherwise to the current EL).
 -     */
 -    CP_ACCESS_TRAP = 1,
 -    /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
 -     * Note that this is not a catch-all case -- the set of cases which may
 -     * result in this failure is specifically defined by the architecture.
 -     */
 -    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
 -    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
 -    CP_ACCESS_TRAP_EL2 = 3,
 -    CP_ACCESS_TRAP_EL3 = 4,
 -    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
 -    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
 -    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
 -} CPAccessResult;
 -
 -/* Access functions for coprocessor registers. These cannot fail and
 - * may not raise exceptions.
 - */
 -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 -                       uint64_t value);
 -/* Access permission check functions for coprocessor registers. */
 -typedef CPAccessResult CPAccessFn(CPUARMState *env,
 -                                  const ARMCPRegInfo *opaque,
 -                                  bool isread);
 -/* Hook function for register reset */
 -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 -
 -#define CP_ANY 0xff
 -
 -/* Definition of an ARM coprocessor register */
 -struct ARMCPRegInfo {
 -    /* Name of register (useful mainly for debugging, need not be unique) */
 -    const char *name;
 -    /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 -     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 -     * 'wildcard' field -- any value of that field in the MRC/MCR insn
 -     * will be decoded to this register. The register read and write
 -     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 -     * used by the program, so it is possible to register a wildcard and
 -     * then behave differently on read/write if necessary.
 -     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 -     * must both be zero.
 -     * For AArch64-visible registers, opc0 is also used.
 -     * Since there are no "coprocessors" in AArch64, cp is purely used as a
 -     * way to distinguish (for KVM's benefit) guest-visible system registers
 -     * from demuxed ones provided to preserve the "no side effects on
 -     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
 -     * visible (to match KVM's encoding); cp==0 will be converted to
 -     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
 -     */
 -    uint8_t cp;
 -    uint8_t crn;
 -    uint8_t crm;
 -    uint8_t opc0;
 -    uint8_t opc1;
 -    uint8_t opc2;
 -    /* Execution state in which this register is visible: ARM_CP_STATE_* */
 -    int state;
 -    /* Register type: ARM_CP_* bits/values */
 -    int type;
 -    /* Access rights: PL*_[RW] */
 -    int access;
 -    /* Security state: ARM_CP_SECSTATE_* bits/values */
 -    int secure;
 -    /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 -     * this register was defined: can be used to hand data through to the
 -     * register read/write functions, since they are passed the ARMCPRegInfo*.
 -     */
 -    void *opaque;
 -    /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 -     * fieldoffset is non-zero, the reset value of the register.
 -     */
 -    uint64_t resetvalue;
 -    /* Offset of the field in CPUARMState for this register.
 -     *
 -     * This is not needed if either:
 -     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 -     *  2. both readfn and writefn are specified
 -     */
 -    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 -
 -    /* Offsets of the secure and non-secure fields in CPUARMState for the
 -     * register if it is banked.  These fields are only used during the static
 -     * registration of a register.  During hashing the bank associated
 -     * with a given security state is copied to fieldoffset which is used from
 -     * there on out.
 -     *
 -     * It is expected that register definitions use either fieldoffset or
 -     * bank_fieldoffsets in the definition but not both.  It is also expected
 -     * that both bank offsets are set when defining a banked register.  This
 -     * use indicates that a register is banked.
 -     */
 -    ptrdiff_t bank_fieldoffsets[2];
 -
 -    /* Function for making any access checks for this register in addition to
 -     * those specified by the 'access' permissions bits. If NULL, no extra
 -     * checks required. The access check is performed at runtime, not at
 -     * translate time.
 -     */
 -    CPAccessFn *accessfn;
 -    /* Function for handling reads of this register. If NULL, then reads
 -     * will be done by loading from the offset into CPUARMState specified
 -     * by fieldoffset.
 -     */
 -    CPReadFn *readfn;
 -    /* Function for handling writes of this register. If NULL, then writes
 -     * will be done by writing to the offset into CPUARMState specified
 -     * by fieldoffset.
 -     */
 -    CPWriteFn *writefn;
 -    /* Function for doing a "raw" read; used when we need to copy
 -     * coprocessor state to the kernel for KVM or out for
 -     * migration. This only needs to be provided if there is also a
 -     * readfn and it has side effects (for instance clear-on-read bits).
 -     */
 -    CPReadFn *raw_readfn;
 -    /* Function for doing a "raw" write; used when we need to copy KVM
 -     * kernel coprocessor state into userspace, or for inbound
 -     * migration. This only needs to be provided if there is also a
 -     * writefn and it masks out "unwritable" bits or has write-one-to-clear
 -     * or similar behaviour.
 -     */
 -    CPWriteFn *raw_writefn;
 -    /* Function for resetting the register. If NULL, then reset will be done
 -     * by writing resetvalue to the field specified in fieldoffset. If
 -     * fieldoffset is 0 then no reset will be done.
 -     */
 -    CPResetFn *resetfn;
 -
 -    /*
 -     * "Original" writefn and readfn.
 -     * For ARMv8.1-VHE register aliases, we overwrite the read/write
 -     * accessor functions of various EL1/EL0 to perform the runtime
 -     * check for which sysreg should actually be modified, and then
 -     * forwards the operation.  Before overwriting the accessors,
 -     * the original function is copied here, so that accesses that
 -     * really do go to the EL1/EL0 version proceed normally.
 -     * (The corresponding EL2 register is linked via opaque.)
 -     */
 -    CPReadFn *orig_readfn;
 -    CPWriteFn *orig_writefn;
 -};
 -
 -/* Macros which are lvalues for the field in CPUARMState for the
 - * ARMCPRegInfo *ri.
 - */
 -#define CPREG_FIELD32(env, ri) \
 -    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 -#define CPREG_FIELD64(env, ri) \
 -    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 -
 -#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 -
 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 -                                    const ARMCPRegInfo *regs, void *opaque);
 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 -                                       const ARMCPRegInfo *regs, void *opaque);
 -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 -{
 -    define_arm_cp_regs_with_opaque(cpu, regs, 0);
 -}
 -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 -{
 -    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 -}
 -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
 -
 -/*
 - * Definition of an ARM co-processor register as viewed from
 - * userspace. This is used for presenting sanitised versions of
 - * registers to userspace when emulating the Linux AArch64 CPU
 - * ID/feature ABI (advertised as HWCAP_CPUID).
 - */
 -typedef struct ARMCPRegUserSpaceInfo {
 -    /* Name of register */
 -    const char *name;
 -
 -    /* Is the name actually a glob pattern */
 -    bool is_glob;
 -
 -    /* Only some bits are exported to user space */
 -    uint64_t exported_bits;
 -
 -    /* Fixed bits are applied after the mask */
 -    uint64_t fixed_bits;
 -} ARMCPRegUserSpaceInfo;
 -
 -#define REGUSERINFO_SENTINEL { .name = NULL }
 -
 -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
 -
 -/* CPWriteFn that can be used to implement writes-ignored behaviour */
 -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 -                         uint64_t value);
 -/* CPReadFn that can be used for read-as-zero behaviour */
 -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
 -
 -/* CPResetFn that does nothing, for use if no reset is required even
 - * if fieldoffset is non zero.
 - */
 -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
 -
 -/* Return true if this reginfo struct's field in the cpu state struct
 - * is 64 bits wide.
 - */
 -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
 -{
 -    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
 -}
 -
 -static inline bool cp_access_ok(int current_el,
 -                                const ARMCPRegInfo *ri, int isread)
 -{
 -    return (ri->access >> ((current_el * 2) + isread)) & 1;
 -}
 -
 -/* Raw read of a coprocessor register (as needed for migration, etc) */
 -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
 -
  /**
   * write_list_to_cpustate
   * @cpu: ARMCPU
 diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx.c
+--- a/hw/misc/trace-events
-+++ b/hw/arm/pxa2xx.c
++++ b/hw/misc/trace-events
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
- #include "qemu/cutils.h"
+ npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
- #include "qemu/log.h"
+ npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
- #include "qom/object.h"
-+#include "target/arm/cpregs.h"
++# npcm7xx_pwm.c
++npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
- static struct {
++npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
-     hwaddr io_base;
++npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
-diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
++npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/arm/pxa2xx_pic.c
+ # stm32f4xx_syscfg.c
-+++ b/hw/arm/pxa2xx_pic.c
+ stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
-@@ -XXX,XX +XXX,XX @@
+ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
  #include "hw/sysbus.h"
  #include "migration/vmstate.h"
  #include "qom/object.h"
 +#include "target/arm/cpregs.h"
  #define ICIP    0x00    /* Interrupt Controller IRQ Pending register */
  #define ICMR    0x04    /* Interrupt Controller Mask register */
 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/arm_gicv3_cpuif.c
 +++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@
  #include "gicv3_internal.h"
  #include "hw/irq.h"
  #include "cpu.h"
 +#include "target/arm/cpregs.h"
  /*
   * Special case return value from hppvi_index(); must be larger than
 diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/arm_gicv3_kvm.c
 +++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "vgic_common.h"
  #include "migration/blocker.h"
  #include "qom/object.h"
 +#include "target/arm/cpregs.h"
 +
  #ifdef DEBUG_GICV3_KVM
  #define DPRINTF(fmt, ...) \
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "kvm_arm.h"
  #include "disas/capstone.h"
  #include "fpu/softfloat.h"
 +#include "cpregs.h"
  static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  {
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
  #include "hvf_arm.h"
  #include "qapi/visitor.h"
  #include "hw/qdev-properties.h"
 +#include "cpregs.h"
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/boards.h"
  #endif
 +#include "cpregs.h"
  /* CPU models. These are not needed for the AArch64 linux-user build. */
  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
  #include "cpu.h"
 -#include "internals.h"
  #include "exec/gdbstub.h"
 +#include "internals.h"
 +#include "cpregs.h"
  typedef struct RegisterSysregXmlParam {
      CPUState *cs;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #include "semihosting/common-semi.h"
  #endif
 +#include "cpregs.h"
  #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/op_helper.c
 +++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "internals.h"
  #include "exec/exec-all.h"
  #include "exec/cpu_ldst.h"
 +#include "cpregs.h"
  #define SIGNBIT (uint32_t)0x80000000
  #define SIGNBIT64 ((uint64_t)1 << 63)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@
  #include "translate.h"
  #include "internals.h"
  #include "qemu/host-utils.h"
 -
  #include "semihosting/semihost.h"
  #include "exec/gen-icount.h"
 -
  #include "exec/helper-proto.h"
  #include "exec/helper-gen.h"
  #include "exec/log.h"
 -
 +#include "cpregs.h"
  #include "translate-a64.h"
  #include "qemu/atomic128.h"
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/bitops.h"
  #include "arm_ldst.h"
  #include "semihosting/semihost.h"
 -
  #include "exec/helper-proto.h"
  #include "exec/helper-gen.h"
 -
  #include "exec/log.h"
 +#include "cpregs.h"
  #define ENABLE_ARCH_4T    arm_dc_feature(s, ARM_FEATURE_V4T)
 --
-.25.1
+.20.1

-[PULL 03/23] target/arm: Reorg CPAccessResult and access_check_cp_reg
+[PULL 19/21] hw/misc: Add QTest for NPCM7XX PWM Module
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Hao Wu <wuhaotsh@google.com>
-Rearrange the values of the enumerators of CPAccessResult
+We add a qtest for the PWM in the previous patch. It proves it works as
-so that we may directly extract the target el. For the two
+expected.
 special cases in access_check_cp_reg, use CPAccessResult.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210108190945.949196-6-wuhaotsh@google.com
 Message-id: 20220501055028.646596-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h    | 26 ++++++++++++--------
+ tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
- target/arm/op_helper.c | 56 +++++++++++++++++++++---------------------
+ tests/qtest/meson.build        |   1 +
-files changed, 44 insertions(+), 38 deletions(-)
+files changed, 491 insertions(+)
  create mode 100644 tests/qtest/npcm7xx_pwm-test.c
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
-index XXXXXXX..XXXXXXX 100644
+new file mode 100644
---- a/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX
-+++ b/target/arm/cpregs.h
+--- /dev/null
-@@ -XXX,XX +XXX,XX @@ static inline bool cptype_valid(int cptype)
++++ b/tests/qtest/npcm7xx_pwm-test.c
- typedef enum CPAccessResult {
+@@ -XXX,XX +XXX,XX @@
-     /* Access is permitted */
++/*
-     CP_ACCESS_OK = 0,
++ * QTests for Nuvoton NPCM7xx PWM Modules.
-+
++ *
-+    /*
++ * Copyright 2020 Google LLC
-+     * Combined with one of the following, the low 2 bits indicate the
++ *
-+     * target exception level.  If 0, the exception is taken to the usual
++ * This program is free software; you can redistribute it and/or modify it
-+     * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
++ * under the terms of the GNU General Public License as published by the
-+     */
++ * Free Software Foundation; either version 2 of the License, or
-+    CP_ACCESS_EL_MASK = 3,
++ * (at your option) any later version.
-+
++ *
-     /*
++ * This program is distributed in the hope that it will be useful, but WITHOUT
-      * Access fails due to a configurable trap or enable which would
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-      * result in a categorized exception syndrome giving information about
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-      * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
++ * for more details.
--     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
++ */
--     * PL1 if in EL0, otherwise to the current EL).
++
-+     * 0xc or 0x18).
++#include "qemu/osdep.h"
-      */
++#include "qemu/bitops.h"
--    CP_ACCESS_TRAP = 1,
++#include "libqos/libqtest.h"
-+    CP_ACCESS_TRAP = (1 << 2),
++#include "qapi/qmp/qdict.h"
-+    CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
++#include "qapi/qmp/qnum.h"
-+    CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
++
-+
++#define REF_HZ          25000000
-     /*
++
-      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
++/* Register field definitions. */
-      * Note that this is not a catch-all case -- the set of cases which may
++#define CH_EN           BIT(0)
-      * result in this failure is specifically defined by the architecture.
++#define CH_INV          BIT(2)
-      */
++#define CH_MOD          BIT(3)
--    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
++
--    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
++/* Registers shared between all PWMs in a module */
--    CP_ACCESS_TRAP_EL2 = 3,
++#define PPR             0x00
--    CP_ACCESS_TRAP_EL3 = 4,
++#define CSR             0x04
--    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
++#define PCR             0x08
--    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
++#define PIER            0x3c
--    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
++#define PIIR            0x40
-+    CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
++
-+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
++/* CLK module related */
-+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
++#define CLK_BA          0xf0801000
- } CPAccessResult;
++#define CLKSEL          0x04
++#define CLKDIV1         0x08
- typedef struct ARMCPRegInfo ARMCPRegInfo;
++#define CLKDIV2         0x2c
-diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
++#define PLLCON0         0x0c
-index XXXXXXX..XXXXXXX 100644
++#define PLLCON1         0x10
---- a/target/arm/op_helper.c
++#define PLL_INDV(rv)    extract32((rv), 0, 6)
-+++ b/target/arm/op_helper.c
++#define PLL_FBDV(rv)    extract32((rv), 16, 12)
-@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
++#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
-                                  uint32_t isread)
++#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
- {
++#define APB3CKDIV(rv)   extract32((rv), 28, 2)
-     const ARMCPRegInfo *ri = rip;
++#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
-+    CPAccessResult res = CP_ACCESS_OK;
++#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
-     int target_el;
++#define CPUCKSEL(rv)    extract32((rv), 0, 2)
++
-     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
++#define MAX_DUTY        1000000
-         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
++
--        raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
++typedef struct PWMModule {
-+        res = CP_ACCESS_TRAP;
++    int irq;
-+        goto fail;
++    uint64_t base_addr;
-     }
++} PWMModule;
++
-     /*
++typedef struct PWM {
-@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
++    uint32_t cnr_offset;
-         mask &= ~((1 << 4) | (1 << 14));
++    uint32_t cmr_offset;
++    uint32_t pdr_offset;
-         if (env->cp15.hstr_el2 & mask) {
++    uint32_t pwdr_offset;
--            target_el = 2;
++} PWM;
--            goto exept;
++
-+            res = CP_ACCESS_TRAP_EL2;
++typedef struct TestData {
-+            goto fail;
++    const PWMModule *module;
-         }
++    const PWM *pwm;
-     }
++} TestData;
++
--    if (!ri->accessfn) {
++static const PWMModule pwm_module_list[] = {
-+    if (ri->accessfn) {
++    {
-+        res = ri->accessfn(env, ri, isread);
++        .irq        = 93,
-+    }
++        .base_addr  = 0xf0103000
-+    if (likely(res == CP_ACCESS_OK)) {
++    },
-         return;
++    {
-     }
++        .irq        = 94,
++        .base_addr  = 0xf0104000
--    switch (ri->accessfn(env, ri, isread)) {
++    }
--    case CP_ACCESS_OK:
++};
--        return;
++
-+ fail:
++static const PWM pwm_list[] = {
-+    switch (res & ~CP_ACCESS_EL_MASK) {
++    {
-     case CP_ACCESS_TRAP:
++        .cnr_offset     = 0x0c,
--        target_el = exception_target_el(env);
++        .cmr_offset     = 0x10,
--        break;
++        .pdr_offset     = 0x14,
--    case CP_ACCESS_TRAP_EL2:
++        .pwdr_offset    = 0x44,
--        /* Requesting a trap to EL2 when we're in EL3 is
++    },
--         * a bug in the access function.
++    {
--         */
++        .cnr_offset     = 0x18,
--        assert(arm_current_el(env) != 3);
++        .cmr_offset     = 0x1c,
--        target_el = 2;
++        .pdr_offset     = 0x20,
--        break;
++        .pwdr_offset    = 0x48,
--    case CP_ACCESS_TRAP_EL3:
++    },
--        target_el = 3;
++    {
-         break;
++        .cnr_offset     = 0x24,
-     case CP_ACCESS_TRAP_UNCATEGORIZED:
++        .cmr_offset     = 0x28,
--        target_el = exception_target_el(env);
++        .pdr_offset     = 0x2c,
--        syndrome = syn_uncategorized();
++        .pwdr_offset    = 0x4c,
--        break;
++    },
--    case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
++    {
--        target_el = 2;
++        .cnr_offset     = 0x30,
--        syndrome = syn_uncategorized();
++        .cmr_offset     = 0x34,
--        break;
++        .pdr_offset     = 0x38,
--    case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
++        .pwdr_offset    = 0x50,
--        target_el = 3;
++    },
-         syndrome = syn_uncategorized();
++};
-         break;
++
-     default:
++static const int ppr_base[] = { 0, 0, 8, 8 };
-         g_assert_not_reached();
++static const int csr_base[] = { 0, 4, 8, 12 };
-     }
++static const int pcr_base[] = { 0, 8, 12, 16 };
++
--exept:
++static const uint32_t ppr_list[] = {
-+    target_el = res & CP_ACCESS_EL_MASK;
++    0,
-+    switch (target_el) {
++    1,
 +    10,
 +    100,
 +    255, /* Max possible value. */
 +};
 +
 +static const uint32_t csr_list[] = {
 +    0,
 +    1,
 +    2,
 +    3,
 +    4, /* Max possible value. */
 +};
 +
 +static const uint32_t cnr_list[] = {
 +    0,
 +    1,
 +    50,
 +    100,
 +    150,
 +    200,
 +    1000,
 +    10000,
 +    65535, /* Max possible value. */
 +};
 +
 +static const uint32_t cmr_list[] = {
 +    0,
 +    1,
 +    10,
 +    50,
 +    100,
 +    150,
 +    200,
 +    1000,
 +    10000,
 +    65535, /* Max possible value. */
 +};
 +
 +/* Returns the index of the PWM module. */
 +static int pwm_module_index(const PWMModule *module)
 +{
 +    ptrdiff_t diff = module - pwm_module_list;
 +
 +    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
 +
 +    return diff;
 +}
 +
 +/* Returns the index of the PWM entry. */
 +static int pwm_index(const PWM *pwm)
 +{
 +    ptrdiff_t diff = pwm - pwm_list;
 +
 +    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
 +
 +    return diff;
 +}
 +
 +static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
 +{
 +    QDict *response;
 +
 +    g_test_message("Getting properties %s from %s", name, path);
 +    response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
 +            " 'arguments': { 'path': %s, 'property': %s}}",
 +            path, name);
 +    /* The qom set message returns successfully. */
 +    g_assert_true(qdict_haskey(response, "return"));
 +    return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
 +}
 +
 +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
 +{
 +    char path[100];
 +    char name[100];
 +
 +    sprintf(path, "/machine/soc/pwm[%d]", module_index);
 +    sprintf(name, "freq[%d]", pwm_index);
 +
 +    return pwm_qom_get(qts, path, name);
 +}
 +
 +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
 +{
 +    char path[100];
 +    char name[100];
 +
 +    sprintf(path, "/machine/soc/pwm[%d]", module_index);
 +    sprintf(name, "duty[%d]", pwm_index);
 +
 +    return pwm_qom_get(qts, path, name);
 +}
 +
 +static uint32_t get_pll(uint32_t con)
 +{
 +    return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
 +            * PLL_OTDV2(con));
 +}
 +
 +static uint64_t read_pclk(QTestState *qts)
 +{
 +    uint64_t freq = REF_HZ;
 +    uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
 +    uint32_t pllcon;
 +    uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
 +    uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
 +
 +    switch (CPUCKSEL(clksel)) {
 +    case 0:
-+        target_el = exception_target_el(env);
++        pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
 +        freq = get_pll(pllcon);
 +        break;
 +    case 1:
 +        pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
 +        freq = get_pll(pllcon);
 +        break;
 +    case 2:
-+        assert(arm_current_el(env) != 3);
-+        assert(arm_is_el2_enabled(env));
 +        break;
 +    case 3:
-+        assert(arm_feature(env, ARM_FEATURE_EL3));
 +        break;
 +    default:
-+        /* No "direct" traps to EL1 */
 +        g_assert_not_reached();
 +    }
 +
-     raise_exception(env, EXCP_UDEF, syndrome, target_el);
++    freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
- }
++
++    return freq;
 +}
 +
 +static uint32_t pwm_selector(uint32_t csr)
 +{
 +    switch (csr) {
 +    case 0:
 +        return 2;
 +    case 1:
 +        return 4;
 +    case 2:
 +        return 8;
 +    case 3:
 +        return 16;
 +    case 4:
 +        return 1;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
 +        uint32_t cnr)
 +{
 +    return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
 +}
 +
 +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
 +{
 +    uint64_t duty;
 +
 +    if (cnr == 0) {
 +        /* PWM is stopped. */
 +        duty = 0;
 +    } else if (cmr >= cnr) {
 +        duty = MAX_DUTY;
 +    } else {
 +        duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
 +    }
 +
 +    if (inverted) {
 +        duty = MAX_DUTY - duty;
 +    }
 +
 +    return duty;
 +}
 +
 +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
 +{
 +    return qtest_readl(qts, td->module->base_addr + offset);
 +}
 +
 +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
 +        uint32_t value)
 +{
 +    qtest_writel(qts, td->module->base_addr + offset, value);
 +}
 +
 +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
 +}
 +
 +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
 +}
 +
 +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
 +}
 +
 +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
 +{
 +    return pwm_read(qts, td, td->pwm->cnr_offset);
 +}
 +
 +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, td->pwm->cnr_offset, value);
 +}
 +
 +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
 +{
 +    return pwm_read(qts, td, td->pwm->cmr_offset);
 +}
 +
 +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, td->pwm->cmr_offset, value);
 +}
 +
 +/* Check pwm registers can be reset to default value */
 +static void test_init(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +
 +    g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
 +    g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
 +
 +    qtest_quit(qts);
 +}
 +
 +/* One-shot mode should not change frequency and duty cycle. */
 +static void test_oneshot(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +    uint32_t ppr, csr, pcr;
 +    int i, j;
 +
 +    pcr = CH_EN;
 +    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
 +        ppr = ppr_list[i];
 +        pwm_write_ppr(qts, td, ppr);
 +
 +        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
 +            csr = csr_list[j];
 +            pwm_write_csr(qts, td, csr);
 +            pwm_write_pcr(qts, td, pcr);
 +
 +            g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
 +            g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
 +            g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
 +            g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
 +            g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* In toggle mode, the PWM generates correct outputs. */
 +static void test_toggle(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +    uint32_t ppr, csr, pcr, cnr, cmr;
 +    int i, j, k, l;
 +    uint64_t expected_freq, expected_duty;
 +
 +    pcr = CH_EN | CH_MOD;
 +    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
 +        ppr = ppr_list[i];
 +        pwm_write_ppr(qts, td, ppr);
 +
 +        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
 +            csr = csr_list[j];
 +            pwm_write_csr(qts, td, csr);
 +
 +            for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
 +                cnr = cnr_list[k];
 +                pwm_write_cnr(qts, td, cnr);
 +
 +                for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
 +                    cmr = cmr_list[l];
 +                    pwm_write_cmr(qts, td, cmr);
 +                    expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
 +                    expected_duty = pwm_compute_duty(cnr, cmr, false);
 +
 +                    pwm_write_pcr(qts, td, pcr);
 +                    g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
 +                    g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
 +                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
 +                    g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
 +                    g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
 +                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
 +                            ==, expected_duty);
 +                    if (expected_duty != 0 && expected_duty != 100) {
 +                        /* Duty cycle with 0 or 100 doesn't need frequency. */
 +                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
 +                                ==, expected_freq);
 +                    }
 +
 +                    /* Test inverted mode */
 +                    expected_duty = pwm_compute_duty(cnr, cmr, true);
 +                    pwm_write_pcr(qts, td, pcr | CH_INV);
 +                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
 +                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
 +                            ==, expected_duty);
 +                    if (expected_duty != 0 && expected_duty != 100) {
 +                        /* Duty cycle with 0 or 100 doesn't need frequency. */
 +                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
 +                                ==, expected_freq);
 +                    }
 +
 +                }
 +            }
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +static void pwm_add_test(const char *name, const TestData* td,
 +        GTestDataFunc fn)
 +{
 +    g_autofree char *full_name = g_strdup_printf(
 +            "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
 +            pwm_index(td->pwm), name);
 +    qtest_add_data_func(full_name, td, fn);
 +}
 +#define add_test(name, td) pwm_add_test(#name, td, test_##name)
 +
 +int main(int argc, char **argv)
 +{
 +    TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
 +
 +    g_test_init(&argc, &argv, NULL);
 +
 +    for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
 +        for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
 +            TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
 +
 +            td->module = &pwm_module_list[i];
 +            td->pwm = &pwm_list[j];
 +
 +            add_test(init, td);
 +            add_test(oneshot, td);
 +            add_test(toggle, td);
 +        }
 +    }
 +
 +    return g_test_run();
 +}
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/meson.build
 +++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
  qtests_npcm7xx = \
    ['npcm7xx_adc-test',
     'npcm7xx_gpio-test',
 +   'npcm7xx_pwm-test',
     'npcm7xx_rng-test',
     'npcm7xx_timer-test',
     'npcm7xx_watchdog_timer-test']
 --
-.25.1
+.20.1

-[PULL 09/23] target/arm: Name CPState type
+[PULL 20/21] hw/*: Use type casting for SysBusDevice in NPCM7XX
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Hao Wu <wuhaotsh@google.com>
-Give this enum a name and use in ARMCPRegInfo,
+A device shouldn't access its parent object which is QOM internal.
-add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.
+Instead it should use type cast for this purporse. This patch fixes this
 issue for all NPCM7XX Devices.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210108190945.949196-7-wuhaotsh@google.com
 Message-id: 20220501055028.646596-9-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h | 6 +++---
+ hw/arm/npcm7xx_boards.c | 2 +-
- target/arm/helper.c | 6 ++++--
+ hw/mem/npcm7xx_mc.c     | 2 +-
-files changed, 7 insertions(+), 5 deletions(-)
+ hw/misc/npcm7xx_clk.c   | 2 +-
  hw/misc/npcm7xx_gcr.c   | 2 +-
  hw/misc/npcm7xx_rng.c   | 2 +-
  hw/nvram/npcm7xx_otp.c  | 2 +-
  hw/ssi/npcm7xx_fiu.c    | 2 +-
 files changed, 7 insertions(+), 7 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/hw/arm/npcm7xx_boards.c
-+++ b/target/arm/cpregs.h
++++ b/hw/arm/npcm7xx_boards.c
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
-  * Note that we rely on the values of these enums as we iterate through
+                                         uint32_t hw_straps)
-  * the various states in some places.
+ {
-  */
+     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
--enum {
+-    MachineClass *mc = &nmc->parent;
-+typedef enum {
++    MachineClass *mc = MACHINE_CLASS(nmc);
-     ARM_CP_STATE_AA32 = 0,
+     Object *obj;
-     ARM_CP_STATE_AA64 = 1,
-     ARM_CP_STATE_BOTH = 2,
+     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
--};
+diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
 +} CPState;
  /*
   * ARM CP register secure state flags.  These flags identify security state
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
      uint8_t opc1;
      uint8_t opc2;
      /* Execution state in which this register is visible: ARM_CP_STATE_* */
 -    int state;
 +    CPState state;
      /* Register type: ARM_CP_* bits/values */
      int type;
      /* Access rights: PL*_[RW] */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/mem/npcm7xx_mc.c
-+++ b/target/arm/helper.c
++++ b/hw/mem/npcm7xx_mc.c
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
      memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
                            NPCM7XX_MC_REGS_SIZE);
 -    sysbus_init_mmio(&s->parent, &s->mmio);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
  }
- static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+ static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
--                                   void *opaque, int state, int secstate,
+diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
-+                                   void *opaque, CPState state, int secstate,
+index XXXXXXX..XXXXXXX 100644
-                                    int crm, int opc1, int opc2,
+--- a/hw/misc/npcm7xx_clk.c
-                                    const char *name)
++++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                            TYPE_NPCM7XX_CLK, 4 * KiB);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
  static int npcm7xx_clk_post_load(void *opaque, int version_id)
 diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_gcr.c
 +++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
                            TYPE_NPCM7XX_GCR, 4 * KiB);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
  static const VMStateDescription vmstate_npcm7xx_gcr = {
 diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_rng.c
 +++ b/hw/misc/npcm7xx_rng.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
                            NPCM7XX_RNG_REGS_SIZE);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
  static const VMStateDescription vmstate_npcm7xx_rng = {
 diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/nvram/npcm7xx_otp.c
 +++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
  {
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+     NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
-      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
+     NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
-      * the register, if any.
+-    SysBusDevice *sbd = &s->parent;
-      */
++    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
--    int crm, opc1, opc2, state;
-+    int crm, opc1, opc2;
+     memset(s->array, 0, sizeof(s->array));
-     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
-     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
+diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
-     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
+index XXXXXXX..XXXXXXX 100644
-     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
+--- a/hw/ssi/npcm7xx_fiu.c
-     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
++++ b/hw/ssi/npcm7xx_fiu.c
-     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
-+    CPState state;
+ static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
-+
+ {
-     /* 64 bit registers have only CRm and Opc1 fields */
+     NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
-     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
+-    SysBusDevice *sbd = &s->parent;
-     /* op0 only exists in the AArch64 encodings */
++    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
      int i;
      if (s->cs_count <= 0) {
 --
-.25.1
+.20.1

-[PULL 10/23] target/arm: Name CPSecureState type
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
-Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
-is handled in define_one_arm_cp_reg_with_opaque.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-10-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpregs.h | 7 ++++---
- target/arm/helper.c | 7 +++++--
-files changed, 9 insertions(+), 5 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
-+++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
-  * registered entry will only have one to identify whether the entry is secure
-  * or non-secure.
-  */
--enum {
-+typedef enum {
-+    ARM_CP_SECSTATE_BOTH = 0,       /* define one cpreg for each secstate */
-     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
-     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
--};
-+} CPSecureState;
- /*
-  * Access rights:
-@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
-     /* Access rights: PL*_[RW] */
-     CPAccessRights access;
-     /* Security state: ARM_CP_SECSTATE_* bits/values */
--    int secure;
-+    CPSecureState secure;
-     /*
-      * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
-      * this register was defined: can be used to hand data through to the
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
- }
- static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
--                                   void *opaque, CPState state, int secstate,
-+                                   void *opaque, CPState state,
-+                                   CPSecureState secstate,
-                                    int crm, int opc1, int opc2,
-                                    const char *name)
- {
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                                    r->secure, crm, opc1, opc2,
-                                                    r->name);
-                             break;
--                        default:
-+                        case ARM_CP_SECSTATE_BOTH:
-                             name = g_strdup_printf("%s_S", r->name);
-                             add_cpreg_to_hashtable(cpu, r, opaque, state,
-                                                    ARM_CP_SECSTATE_S,
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                                    ARM_CP_SECSTATE_NS,
-                                                    crm, opc1, opc2, r->name);
-                             break;
-+                        default:
-+                            g_assert_not_reached();
-                         }
-                     } else {
-                         /* AArch64 registers get mapped to non-secure instance
---
-.25.1

-[PULL 11/23] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The new_key field is always non-zero -- drop the if.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-11-richard.henderson@linaro.org
-[PMM: reinstated dropped PL3_RW mask]
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.c | 23 +++++++++++------------
-file changed, 11 insertions(+), 12 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
-     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
-         const struct E2HAlias *a = &aliases[i];
--        ARMCPRegInfo *src_reg, *dst_reg;
-+        ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
-+        uint32_t *new_key;
-+        bool ok;
-         if (a->feature && !a->feature(&cpu->isar)) {
-             continue;
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
-         g_assert(src_reg->opaque == NULL);
-         /* Create alias before redirection so we dup the right data. */
--        if (a->new_key) {
--            ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
--            uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
--            bool ok;
-+        new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-+        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
--            new_reg->name = a->new_name;
--            new_reg->type |= ARM_CP_ALIAS;
--            /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
--            new_reg->access &= PL2_RW | PL3_RW;
-+        new_reg->name = a->new_name;
-+        new_reg->type |= ARM_CP_ALIAS;
-+        /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
-+        new_reg->access &= PL2_RW | PL3_RW;
--            ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
--            g_assert(ok);
--        }
-+        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
-+        g_assert(ok);
-         src_reg->opaque = dst_reg;
-         src_reg->orig_readfn = src_reg->readfn ?: raw_read;
---
-.25.1

-[PULL 12/23] target/arm: Store cpregs key in the hash table directly
+[PULL 21/21] ui/cocoa: Fix openFile: deprecation on Big Sur
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Roman Bolshakov <r.bolshakov@yadro.com>
-Cast the uint32_t key into a gpointer directly, which
+ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
-allows us to avoid allocating storage for each key.
+      [-Wdeprecated-declarations]
         if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
                                            ^
 /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
       'openFile:' has been explicitly marked deprecated here
 - (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
 ^
-Use g_hash_table_lookup when we already have a gpointer
+Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
 (e.g. for callbacks like count_cpreg), or when using
 get_arm_cp_reginfo would require casting away const.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-12-richard.henderson@linaro.org
+Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c     |  4 ++--
+ ui/cocoa.m | 5 ++++-
- target/arm/gdbstub.c |  2 +-
+file changed, 4 insertions(+), 1 deletion(-)
  target/arm/helper.c  | 41 ++++++++++++++++++-----------------------
 files changed, 21 insertions(+), 26 deletions(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/ui/cocoa.m b/ui/cocoa.m
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/ui/cocoa.m
-+++ b/target/arm/cpu.c
++++ b/ui/cocoa.m
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
-     ARMCPU *cpu = ARM_CPU(obj);
+     /* Where to look for local files */
+     NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
-     cpu_set_cpustate_pointers(cpu);
+     NSString *full_file_path;
--    cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
++    NSURL *full_file_url;
--                                         g_free, cpreg_hashtable_data_destroy);
-+    cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
+     /* iterate thru the possible paths until the file is found */
-+                                         NULL, cpreg_hashtable_data_destroy);
+     int index;
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
-     QLIST_INIT(&cpu->pre_el_change_hooks);
+         full_file_path = [full_file_path stringByDeletingLastPathComponent];
-     QLIST_INIT(&cpu->el_change_hooks);
+         full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
-diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
+                           path_array[index], filename];
-index XXXXXXX..XXXXXXX 100644
+-        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
---- a/target/arm/gdbstub.c
++        full_file_url = [NSURL fileURLWithPath: full_file_path
-+++ b/target/arm/gdbstub.c
++                                   isDirectory: false];
-@@ -XXX,XX +XXX,XX @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
++        if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
- static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
+             return;
                                          gpointer p)
  {
 -    uint32_t ri_key = *(uint32_t *)key;
 +    uint32_t ri_key = (uintptr_t)key;
      ARMCPRegInfo *ri = value;
      RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
      GString *s = param->s;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
  static void add_cpreg_to_list(gpointer key, gpointer opaque)
  {
      ARMCPU *cpu = opaque;
 -    uint64_t regidx;
 -    const ARMCPRegInfo *ri;
 -
 -    regidx = *(uint32_t *)key;
 -    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 +    uint32_t regidx = (uintptr_t)key;
 +    const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
      if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
          cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
  static void count_cpreg(gpointer key, gpointer opaque)
  {
      ARMCPU *cpu = opaque;
 -    uint64_t regidx;
      const ARMCPRegInfo *ri;
 -    regidx = *(uint32_t *)key;
 -    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 +    ri = g_hash_table_lookup(cpu->cp_regs, key);
      if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
          cpu->cpreg_array_len++;
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
  static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
  {
 -    uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 -    uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 +    uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a);
 +    uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b);
      if (aidx > bidx) {
          return 1;
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
      for (i = 0; i < ARRAY_SIZE(aliases); i++) {
          const struct E2HAlias *a = &aliases[i];
          ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
 -        uint32_t *new_key;
          bool ok;
          if (a->feature && !a->feature(&cpu->isar)) {
              continue;
          }
 -        src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
 -        dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
 +        src_reg = g_hash_table_lookup(cpu->cp_regs,
 +                                      (gpointer)(uintptr_t)a->src_key);
 +        dst_reg = g_hash_table_lookup(cpu->cp_regs,
 +                                      (gpointer)(uintptr_t)a->dst_key);
          g_assert(src_reg != NULL);
          g_assert(dst_reg != NULL);
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
          /* Create alias before redirection so we dup the right data. */
          new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
 -        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
          new_reg->name = a->new_name;
          new_reg->type |= ARM_CP_ALIAS;
          /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
          new_reg->access &= PL2_RW | PL3_RW;
 -        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
 +        ok = g_hash_table_insert(cpu->cp_regs,
 +                                 (gpointer)(uintptr_t)a->new_key, new_reg);
          g_assert(ok);
          src_reg->opaque = dst_reg;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      /* Private utility function for define_one_arm_cp_reg_with_opaque():
       * add a single reginfo struct to the hash table.
       */
 -    uint32_t *key = g_new(uint32_t, 1);
 +    uint32_t key;
      ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
      int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
      int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
              r2->cp = CP_REG_ARM64_SYSREG_CP;
          }
 -        *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
 -                                  r2->opc0, opc1, opc2);
 +        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
 +                                 r2->opc0, opc1, opc2);
      } else {
 -        *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
 +        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
      }
      if (opaque) {
          r2->opaque = opaque;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
       * requested.
       */
      if (!(r->type & ARM_CP_OVERRIDE)) {
 -        ARMCPRegInfo *oldreg;
 -        oldreg = g_hash_table_lookup(cpu->cp_regs, key);
 +        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
          if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
              fprintf(stderr, "Register redefined: cp=%d %d bit "
                      "crn=%d crm=%d opc1=%d opc2=%d, "
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
              g_assert_not_reached();
          }
      }
--    g_hash_table_insert(cpu->cp_regs, key, r2);
-+    g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
- }
-@@ -XXX,XX +XXX,XX @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
- const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
- {
--    return g_hash_table_lookup(cpregs, &encoded_cp);
-+    return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp);
- }
- void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 --
-.25.1
+.20.1

Two small bugfixes, plus most of RTH's refactoring of cpregs
handling.

-- PMM

The following changes since commit 1fba9dc71a170b3a05b9d3272dd8ecfe7f26e215:

Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging (2022-05-04 08:07:02 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220505

for you to fetch changes up to 99a50d1a67c602126fc2b3a4812d3000eba9bf34:

target/arm: read access to performance counters from EL0 (2022-05-05 09:36:22 +0100)

----------------------------------------------------------------
target-arm queue:
 * Enable read access to performance counters from EL0
 * Enable SCTLR_EL1.BT0 for aarch64-linux-user
 * Refactoring of cpreg handling

----------------------------------------------------------------
Alex Zuepke (1):
      target/arm: read access to performance counters from EL0

Richard Henderson (22):
      target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
      target/arm: Split out cpregs.h
      target/arm: Reorg CPAccessResult and access_check_cp_reg
      target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
      target/arm: Make some more cpreg data static const
      target/arm: Reorg ARMCPRegInfo type field bits
      target/arm: Avoid bare abort() or assert(0)
      target/arm: Change cpreg access permissions to enum
      target/arm: Name CPState type
      target/arm: Name CPSecureState type
      target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
      target/arm: Store cpregs key in the hash table directly
      target/arm: Merge allocation of the cpreg and its name
      target/arm: Hoist computation of key in add_cpreg_to_hashtable
      target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
      target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
      target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
      target/arm: Perform override check early in add_cpreg_to_hashtable
      target/arm: Reformat comments in add_cpreg_to_hashtable
      target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
      target/arm: Add isar predicates for FEAT_Debugv8p2
      target/arm: Add isar_feature_{aa64,any}_ras

From: Richard Henderson <richard.henderson@linaro.org>

This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17).  The linux kernel
sets this in bti_enable().

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
[PMM: remove stray change to makefile comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c                  |  2 ++
 tests/tcg/aarch64/bti-3.c         | 42 +++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  6 ++---
 3 files changed, 47 insertions(+), 3 deletions(-)
 create mode 100644 tests/tcg/aarch64/bti-3.c

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         /* Enable all PAC keys.  */
         env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
                                   SCTLR_EnDA | SCTLR_EnDB);
+        /* Trap on btype=3 for PACIxSP. */
+        env->cp15.sctlr_el[1] |= SCTLR_BT0;
         /* and to the FP/Neon instructions */
         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
         /* and to the SVE instructions */
diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/aarch64/bti-3.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BTI vs PACIASP
+ */
+
+#include "bti-crt.inc.c"
+
+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
+{
+    uc->uc_mcontext.pc += 8;
+    uc->uc_mcontext.pstate = 1;
+}
+
+#define BTYPE_1() \
+    asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_2() \
+    asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_3() \
+    asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x15", "x30")
+
+#define TEST(WHICH, EXPECT) \
+    do { WHICH(); fail += skipped ^ EXPECT; } while (0)
+
+int main()
+{
+    int fail = 0;
+    int skipped;
+
+    /* Signal-like with SA_SIGINFO.  */
+    signal_info(SIGILL, skip2_sigill);
+
+    /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
+    TEST(BTYPE_1, 0);
+    TEST(BTYPE_2, 0);
+    TEST(BTYPE_3, 1);
+
+    return fail;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ endif
 # BTI Tests
 # bti-1 tests the elf notes, so we require special compiler support.
 ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
-AARCH64_TESTS += bti-1
-bti-1: CFLAGS += -mbranch-protection=standard
-bti-1: LDFLAGS += -nostdlib
+AARCH64_TESTS += bti-1 bti-3
+bti-1 bti-3: CFLAGS += -mbranch-protection=standard
+bti-1 bti-3: LDFLAGS += -nostdlib
 endif
 # bti-2 tests PROT_BTI, so no special compiler support required.
 AARCH64_TESTS += bti-2
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move ARMCPRegInfo and all related declarations to a new
internal header, out of the public cpu.h.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h        | 413 +++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h           | 368 ---------------------------------
 hw/arm/pxa2xx.c            |   1 +
 hw/arm/pxa2xx_pic.c        |   1 +
 hw/intc/arm_gicv3_cpuif.c  |   1 +
 hw/intc/arm_gicv3_kvm.c    |   2 +
 target/arm/cpu.c           |   1 +
 target/arm/cpu64.c         |   1 +
 target/arm/cpu_tcg.c       |   1 +
 target/arm/gdbstub.c       |   3 +-
 target/arm/helper.c        |   1 +
 target/arm/op_helper.c     |   1 +
 target/arm/translate-a64.c |   4 +-
 target/arm/translate.c     |   3 +-
 14 files changed, 427 insertions(+), 374 deletions(-)
 create mode 100644 target/arm/cpregs.h

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU ARM CP Register access and descriptions
+ *
+ * Copyright (c) 2022 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#ifndef TARGET_ARM_CPREGS_H
+#define TARGET_ARM_CPREGS_H
+
+/*
+ * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
+ * special-behaviour cp reg and bits [11..8] indicate what behaviour
+ * it has. Otherwise it is a simple cp reg, where CONST indicates that
+ * TCG can assume the value to be constant (ie load at translate time)
+ * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
+ * indicates that the TB should not be ended after a write to this register
+ * (the default is that the TB ends after cp writes). OVERRIDE permits
+ * a register definition to override a previous definition for the
+ * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
+ * old must have the OVERRIDE bit set.
+ * ALIAS indicates that this register is an alias view of some underlying
+ * state which is also visible via another register, and that the other
+ * register is handling migration and reset; registers marked ALIAS will not be
+ * migrated but may have their state set by syncing of register state from KVM.
+ * NO_RAW indicates that this register has no underlying state and does not
+ * support raw access for state saving/loading; it will not be used for either
+ * migration or KVM state synchronization. (Typically this is for "registers"
+ * which are actually used as instructions for cache maintenance and so on.)
+ * IO indicates that this register does I/O and therefore its accesses
+ * need to be marked with gen_io_start() and also end the TB. In particular,
+ * registers which implement clocks or timers require this.
+ * RAISES_EXC is for when the read or write hook might raise an exception;
+ * the generated code will synchronize the CPU state before calling the hook
+ * so that it is safe for the hook to call raise_exception().
+ * NEWEL is for writes to registers that might change the exception
+ * level - typically on older ARM chips. For those cases we need to
+ * re-read the new el when recomputing the translation flags.
+ */
+#define ARM_CP_SPECIAL           0x0001
+#define ARM_CP_CONST             0x0002
+#define ARM_CP_64BIT             0x0004
+#define ARM_CP_SUPPRESS_TB_END   0x0008
+#define ARM_CP_OVERRIDE          0x0010
+#define ARM_CP_ALIAS             0x0020
+#define ARM_CP_IO                0x0040
+#define ARM_CP_NO_RAW            0x0080
+#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
+#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
+#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
+#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
+#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
+#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
+#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
+#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
+#define ARM_CP_FPU               0x1000
+#define ARM_CP_SVE               0x2000
+#define ARM_CP_NO_GDB            0x4000
+#define ARM_CP_RAISES_EXC        0x8000
+#define ARM_CP_NEWEL             0x10000
+/* Used only as a terminator for ARMCPRegInfo lists */
+#define ARM_CP_SENTINEL          0xfffff
+/* Mask of only the flag bits in a type field */
+#define ARM_CP_FLAG_MASK         0x1f0ff
+
+/*
+ * Valid values for ARMCPRegInfo state field, indicating which of
+ * the AArch32 and AArch64 execution states this register is visible in.
+ * If the reginfo doesn't explicitly specify then it is AArch32 only.
+ * If the reginfo is declared to be visible in both states then a second
+ * reginfo is synthesised for the AArch32 view of the AArch64 register,
+ * such that the AArch32 view is the lower 32 bits of the AArch64 one.
+ * Note that we rely on the values of these enums as we iterate through
+ * the various states in some places.
+ */
+enum {
+    ARM_CP_STATE_AA32 = 0,
+    ARM_CP_STATE_AA64 = 1,
+    ARM_CP_STATE_BOTH = 2,
+};
+
+/*
+ * ARM CP register secure state flags.  These flags identify security state
+ * attributes for a given CP register entry.
+ * The existence of both or neither secure and non-secure flags indicates that
+ * the register has both a secure and non-secure hash entry.  A single one of
+ * these flags causes the register to only be hashed for the specified
+ * security state.
+ * Although definitions may have any combination of the S/NS bits, each
+ * registered entry will only have one to identify whether the entry is secure
+ * or non-secure.
+ */
+enum {
+    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
+    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
+};
+
+/*
+ * Return true if cptype is a valid type field. This is used to try to
+ * catch errors where the sentinel has been accidentally left off the end
+ * of a list of registers.
+ */
+static inline bool cptype_valid(int cptype)
+{
+    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
+        || ((cptype & ARM_CP_SPECIAL) &&
+            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
+}
+
+/*
+ * Access rights:
+ * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
+ * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
+ * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
+ * (ie any of the privileged modes in Secure state, or Monitor mode).
+ * If a register is accessible in one privilege level it's always accessible
+ * in higher privilege levels too. Since "Secure PL1" also follows this rule
+ * (ie anything visible in PL2 is visible in S-PL1, some things are only
+ * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
+ * terminology a little and call this PL3.
+ * In AArch64 things are somewhat simpler as the PLx bits line up exactly
+ * with the ELx exception levels.
+ *
+ * If access permissions for a register are more complex than can be
+ * described with these bits, then use a laxer set of restrictions, and
+ * do the more restrictive/complex check inside a helper function.
+ */
+#define PL3_R 0x80
+#define PL3_W 0x40
+#define PL2_R (0x20 | PL3_R)
+#define PL2_W (0x10 | PL3_W)
+#define PL1_R (0x08 | PL2_R)
+#define PL1_W (0x04 | PL2_W)
+#define PL0_R (0x02 | PL1_R)
+#define PL0_W (0x01 | PL1_W)
+
+/*
+ * For user-mode some registers are accessible to EL0 via a kernel
+ * trap-and-emulate ABI. In this case we define the read permissions
+ * as actually being PL0_R. However some bits of any given register
+ * may still be masked.
+ */
+#ifdef CONFIG_USER_ONLY
+#define PL0U_R PL0_R
+#else
+#define PL0U_R PL1_R
+#endif
+
+#define PL3_RW (PL3_R | PL3_W)
+#define PL2_RW (PL2_R | PL2_W)
+#define PL1_RW (PL1_R | PL1_W)
+#define PL0_RW (PL0_R | PL0_W)
+
+typedef enum CPAccessResult {
+    /* Access is permitted */
+    CP_ACCESS_OK = 0,
+    /*
+     * Access fails due to a configurable trap or enable which would
+     * result in a categorized exception syndrome giving information about
+     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
+     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
+     * PL1 if in EL0, otherwise to the current EL).
+     */
+    CP_ACCESS_TRAP = 1,
+    /*
+     * Access fails and results in an exception syndrome 0x0 ("uncategorized").
+     * Note that this is not a catch-all case -- the set of cases which may
+     * result in this failure is specifically defined by the architecture.
+     */
+    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
+    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
+    CP_ACCESS_TRAP_EL2 = 3,
+    CP_ACCESS_TRAP_EL3 = 4,
+    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
+} CPAccessResult;
+
+typedef struct ARMCPRegInfo ARMCPRegInfo;
+
+/*
+ * Access functions for coprocessor registers. These cannot fail and
+ * may not raise exceptions.
+ */
+typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
+                       uint64_t value);
+/* Access permission check functions for coprocessor registers. */
+typedef CPAccessResult CPAccessFn(CPUARMState *env,
+                                  const ARMCPRegInfo *opaque,
+                                  bool isread);
+/* Hook function for register reset */
+typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+
+#define CP_ANY 0xff
+
+/* Definition of an ARM coprocessor register */
+struct ARMCPRegInfo {
+    /* Name of register (useful mainly for debugging, need not be unique) */
+    const char *name;
+    /*
+     * Location of register: coprocessor number and (crn,crm,opc1,opc2)
+     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
+     * 'wildcard' field -- any value of that field in the MRC/MCR insn
+     * will be decoded to this register. The register read and write
+     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
+     * used by the program, so it is possible to register a wildcard and
+     * then behave differently on read/write if necessary.
+     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
+     * must both be zero.
+     * For AArch64-visible registers, opc0 is also used.
+     * Since there are no "coprocessors" in AArch64, cp is purely used as a
+     * way to distinguish (for KVM's benefit) guest-visible system registers
+     * from demuxed ones provided to preserve the "no side effects on
+     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
+     * visible (to match KVM's encoding); cp==0 will be converted to
+     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
+     */
+    uint8_t cp;
+    uint8_t crn;
+    uint8_t crm;
+    uint8_t opc0;
+    uint8_t opc1;
+    uint8_t opc2;
+    /* Execution state in which this register is visible: ARM_CP_STATE_* */
+    int state;
+    /* Register type: ARM_CP_* bits/values */
+    int type;
+    /* Access rights: PL*_[RW] */
+    int access;
+    /* Security state: ARM_CP_SECSTATE_* bits/values */
+    int secure;
+    /*
+     * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
+     * this register was defined: can be used to hand data through to the
+     * register read/write functions, since they are passed the ARMCPRegInfo*.
+     */
+    void *opaque;
+    /*
+     * Value of this register, if it is ARM_CP_CONST. Otherwise, if
+     * fieldoffset is non-zero, the reset value of the register.
+     */
+    uint64_t resetvalue;
+    /*
+     * Offset of the field in CPUARMState for this register.
+     * This is not needed if either:
+     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
+     *  2. both readfn and writefn are specified
+     */
+    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
+
+    /*
+     * Offsets of the secure and non-secure fields in CPUARMState for the
+     * register if it is banked.  These fields are only used during the static
+     * registration of a register.  During hashing the bank associated
+     * with a given security state is copied to fieldoffset which is used from
+     * there on out.
+     *
+     * It is expected that register definitions use either fieldoffset or
+     * bank_fieldoffsets in the definition but not both.  It is also expected
+     * that both bank offsets are set when defining a banked register.  This
+     * use indicates that a register is banked.
+     */
+    ptrdiff_t bank_fieldoffsets[2];
+
+    /*
+     * Function for making any access checks for this register in addition to
+     * those specified by the 'access' permissions bits. If NULL, no extra
+     * checks required. The access check is performed at runtime, not at
+     * translate time.
+     */
+    CPAccessFn *accessfn;
+    /*
+     * Function for handling reads of this register. If NULL, then reads
+     * will be done by loading from the offset into CPUARMState specified
+     * by fieldoffset.
+     */
+    CPReadFn *readfn;
+    /*
+     * Function for handling writes of this register. If NULL, then writes
+     * will be done by writing to the offset into CPUARMState specified
+     * by fieldoffset.
+     */
+    CPWriteFn *writefn;
+    /*
+     * Function for doing a "raw" read; used when we need to copy
+     * coprocessor state to the kernel for KVM or out for
+     * migration. This only needs to be provided if there is also a
+     * readfn and it has side effects (for instance clear-on-read bits).
+     */
+    CPReadFn *raw_readfn;
+    /*
+     * Function for doing a "raw" write; used when we need to copy KVM
+     * kernel coprocessor state into userspace, or for inbound
+     * migration. This only needs to be provided if there is also a
+     * writefn and it masks out "unwritable" bits or has write-one-to-clear
+     * or similar behaviour.
+     */
+    CPWriteFn *raw_writefn;
+    /*
+     * Function for resetting the register. If NULL, then reset will be done
+     * by writing resetvalue to the field specified in fieldoffset. If
+     * fieldoffset is 0 then no reset will be done.
+     */
+    CPResetFn *resetfn;
+
+    /*
+     * "Original" writefn and readfn.
+     * For ARMv8.1-VHE register aliases, we overwrite the read/write
+     * accessor functions of various EL1/EL0 to perform the runtime
+     * check for which sysreg should actually be modified, and then
+     * forwards the operation.  Before overwriting the accessors,
+     * the original function is copied here, so that accesses that
+     * really do go to the EL1/EL0 version proceed normally.
+     * (The corresponding EL2 register is linked via opaque.)
+     */
+    CPReadFn *orig_readfn;
+    CPWriteFn *orig_writefn;
+};
+
+/*
+ * Macros which are lvalues for the field in CPUARMState for the
+ * ARMCPRegInfo *ri.
+ */
+#define CPREG_FIELD32(env, ri) \
+    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
+#define CPREG_FIELD64(env, ri) \
+    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
+
+#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
+
+void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
+                                    const ARMCPRegInfo *regs, void *opaque);
+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+                                       const ARMCPRegInfo *regs, void *opaque);
+static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
+{
+    define_arm_cp_regs_with_opaque(cpu, regs, 0);
+}
+static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
+{
+    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
+}
+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
+
+/*
+ * Definition of an ARM co-processor register as viewed from
+ * userspace. This is used for presenting sanitised versions of
+ * registers to userspace when emulating the Linux AArch64 CPU
+ * ID/feature ABI (advertised as HWCAP_CPUID).
+ */
+typedef struct ARMCPRegUserSpaceInfo {
+    /* Name of register */
+    const char *name;
+
+    /* Is the name actually a glob pattern */
+    bool is_glob;
+
+    /* Only some bits are exported to user space */
+    uint64_t exported_bits;
+
+    /* Fixed bits are applied after the mask */
+    uint64_t fixed_bits;
+} ARMCPRegUserSpaceInfo;
+
+#define REGUSERINFO_SENTINEL { .name = NULL }
+
+void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
+
+/* CPWriteFn that can be used to implement writes-ignored behaviour */
+void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
+                         uint64_t value);
+/* CPReadFn that can be used for read-as-zero behaviour */
+uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
+
+/*
+ * CPResetFn that does nothing, for use if no reset is required even
+ * if fieldoffset is non zero.
+ */
+void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
+
+/*
+ * Return true if this reginfo struct's field in the cpu state struct
+ * is 64 bits wide.
+ */
+static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
+{
+    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
+}
+
+static inline bool cp_access_ok(int current_el,
+                                const ARMCPRegInfo *ri, int isread)
+{
+    return (ri->access >> ((current_el * 2) + isread)) & 1;
+}
+
+/* Raw read of a coprocessor register (as needed for migration, etc) */
+uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
+
+#endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
     return kvmid;
 }
 
-/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
- * special-behaviour cp reg and bits [11..8] indicate what behaviour
- * it has. Otherwise it is a simple cp reg, where CONST indicates that
- * TCG can assume the value to be constant (ie load at translate time)
- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
- * indicates that the TB should not be ended after a write to this register
- * (the default is that the TB ends after cp writes). OVERRIDE permits
- * a register definition to override a previous definition for the
- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
- * old must have the OVERRIDE bit set.
- * ALIAS indicates that this register is an alias view of some underlying
- * state which is also visible via another register, and that the other
- * register is handling migration and reset; registers marked ALIAS will not be
- * migrated but may have their state set by syncing of register state from KVM.
- * NO_RAW indicates that this register has no underlying state and does not
- * support raw access for state saving/loading; it will not be used for either
- * migration or KVM state synchronization. (Typically this is for "registers"
- * which are actually used as instructions for cache maintenance and so on.)
- * IO indicates that this register does I/O and therefore its accesses
- * need to be marked with gen_io_start() and also end the TB. In particular,
- * registers which implement clocks or timers require this.
- * RAISES_EXC is for when the read or write hook might raise an exception;
- * the generated code will synchronize the CPU state before calling the hook
- * so that it is safe for the hook to call raise_exception().
- * NEWEL is for writes to registers that might change the exception
- * level - typically on older ARM chips. For those cases we need to
- * re-read the new el when recomputing the translation flags.
- */
-#define ARM_CP_SPECIAL           0x0001
-#define ARM_CP_CONST             0x0002
-#define ARM_CP_64BIT             0x0004
-#define ARM_CP_SUPPRESS_TB_END   0x0008
-#define ARM_CP_OVERRIDE          0x0010
-#define ARM_CP_ALIAS             0x0020
-#define ARM_CP_IO                0x0040
-#define ARM_CP_NO_RAW            0x0080
-#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
-#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
-#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
-#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
-#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
-#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
-#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
-#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
-#define ARM_CP_FPU               0x1000
-#define ARM_CP_SVE               0x2000
-#define ARM_CP_NO_GDB            0x4000
-#define ARM_CP_RAISES_EXC        0x8000
-#define ARM_CP_NEWEL             0x10000
-/* Used only as a terminator for ARMCPRegInfo lists */
-#define ARM_CP_SENTINEL          0xfffff
-/* Mask of only the flag bits in a type field */
-#define ARM_CP_FLAG_MASK         0x1f0ff
-
-/* Valid values for ARMCPRegInfo state field, indicating which of
- * the AArch32 and AArch64 execution states this register is visible in.
- * If the reginfo doesn't explicitly specify then it is AArch32 only.
- * If the reginfo is declared to be visible in both states then a second
- * reginfo is synthesised for the AArch32 view of the AArch64 register,
- * such that the AArch32 view is the lower 32 bits of the AArch64 one.
- * Note that we rely on the values of these enums as we iterate through
- * the various states in some places.
- */
-enum {
-    ARM_CP_STATE_AA32 = 0,
-    ARM_CP_STATE_AA64 = 1,
-    ARM_CP_STATE_BOTH = 2,
-};
-
-/* ARM CP register secure state flags.  These flags identify security state
- * attributes for a given CP register entry.
- * The existence of both or neither secure and non-secure flags indicates that
- * the register has both a secure and non-secure hash entry.  A single one of
- * these flags causes the register to only be hashed for the specified
- * security state.
- * Although definitions may have any combination of the S/NS bits, each
- * registered entry will only have one to identify whether the entry is secure
- * or non-secure.
- */
-enum {
-    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
-    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
-};
-
-/* Return true if cptype is a valid type field. This is used to try to
- * catch errors where the sentinel has been accidentally left off the end
- * of a list of registers.
- */
-static inline bool cptype_valid(int cptype)
-{
-    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
-        || ((cptype & ARM_CP_SPECIAL) &&
-            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
-}
-
-/* Access rights:
- * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
- * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
- * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
- * (ie any of the privileged modes in Secure state, or Monitor mode).
- * If a register is accessible in one privilege level it's always accessible
- * in higher privilege levels too. Since "Secure PL1" also follows this rule
- * (ie anything visible in PL2 is visible in S-PL1, some things are only
- * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
- * terminology a little and call this PL3.
- * In AArch64 things are somewhat simpler as the PLx bits line up exactly
- * with the ELx exception levels.
- *
- * If access permissions for a register are more complex than can be
- * described with these bits, then use a laxer set of restrictions, and
- * do the more restrictive/complex check inside a helper function.
- */
-#define PL3_R 0x80
-#define PL3_W 0x40
-#define PL2_R (0x20 | PL3_R)
-#define PL2_W (0x10 | PL3_W)
-#define PL1_R (0x08 | PL2_R)
-#define PL1_W (0x04 | PL2_W)
-#define PL0_R (0x02 | PL1_R)
-#define PL0_W (0x01 | PL1_W)
-
-/*
- * For user-mode some registers are accessible to EL0 via a kernel
- * trap-and-emulate ABI. In this case we define the read permissions
- * as actually being PL0_R. However some bits of any given register
- * may still be masked.
- */
-#ifdef CONFIG_USER_ONLY
-#define PL0U_R PL0_R
-#else
-#define PL0U_R PL1_R
-#endif
-
-#define PL3_RW (PL3_R | PL3_W)
-#define PL2_RW (PL2_R | PL2_W)
-#define PL1_RW (PL1_R | PL1_W)
-#define PL0_RW (PL0_R | PL0_W)
-
 /* Return the highest implemented Exception Level */
 static inline int arm_highest_el(CPUARMState *env)
 {
@@ -XXX,XX +XXX,XX @@ static inline int arm_current_el(CPUARMState *env)
     }
 }
 
-typedef struct ARMCPRegInfo ARMCPRegInfo;
-
-typedef enum CPAccessResult {
-    /* Access is permitted */
-    CP_ACCESS_OK = 0,
-    /* Access fails due to a configurable trap or enable which would
-     * result in a categorized exception syndrome giving information about
-     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
-     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
-     * PL1 if in EL0, otherwise to the current EL).
-     */
-    CP_ACCESS_TRAP = 1,
-    /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
-     * Note that this is not a catch-all case -- the set of cases which may
-     * result in this failure is specifically defined by the architecture.
-     */
-    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
-    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_EL2 = 3,
-    CP_ACCESS_TRAP_EL3 = 4,
-    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
-} CPAccessResult;
-
-/* Access functions for coprocessor registers. These cannot fail and
- * may not raise exceptions.
- */
-typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
-                       uint64_t value);
-/* Access permission check functions for coprocessor registers. */
-typedef CPAccessResult CPAccessFn(CPUARMState *env,
-                                  const ARMCPRegInfo *opaque,
-                                  bool isread);
-/* Hook function for register reset */
-typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-
-#define CP_ANY 0xff
-
-/* Definition of an ARM coprocessor register */
-struct ARMCPRegInfo {
-    /* Name of register (useful mainly for debugging, need not be unique) */
-    const char *name;
-    /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
-     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
-     * 'wildcard' field -- any value of that field in the MRC/MCR insn
-     * will be decoded to this register. The register read and write
-     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
-     * used by the program, so it is possible to register a wildcard and
-     * then behave differently on read/write if necessary.
-     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
-     * must both be zero.
-     * For AArch64-visible registers, opc0 is also used.
-     * Since there are no "coprocessors" in AArch64, cp is purely used as a
-     * way to distinguish (for KVM's benefit) guest-visible system registers
-     * from demuxed ones provided to preserve the "no side effects on
-     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
-     * visible (to match KVM's encoding); cp==0 will be converted to
-     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
-     */
-    uint8_t cp;
-    uint8_t crn;
-    uint8_t crm;
-    uint8_t opc0;
-    uint8_t opc1;
-    uint8_t opc2;
-    /* Execution state in which this register is visible: ARM_CP_STATE_* */
-    int state;
-    /* Register type: ARM_CP_* bits/values */
-    int type;
-    /* Access rights: PL*_[RW] */
-    int access;
-    /* Security state: ARM_CP_SECSTATE_* bits/values */
-    int secure;
-    /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
-     * this register was defined: can be used to hand data through to the
-     * register read/write functions, since they are passed the ARMCPRegInfo*.
-     */
-    void *opaque;
-    /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
-     * fieldoffset is non-zero, the reset value of the register.
-     */
-    uint64_t resetvalue;
-    /* Offset of the field in CPUARMState for this register.
-     *
-     * This is not needed if either:
-     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
-     *  2. both readfn and writefn are specified
-     */
-    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
-
-    /* Offsets of the secure and non-secure fields in CPUARMState for the
-     * register if it is banked.  These fields are only used during the static
-     * registration of a register.  During hashing the bank associated
-     * with a given security state is copied to fieldoffset which is used from
-     * there on out.
-     *
-     * It is expected that register definitions use either fieldoffset or
-     * bank_fieldoffsets in the definition but not both.  It is also expected
-     * that both bank offsets are set when defining a banked register.  This
-     * use indicates that a register is banked.
-     */
-    ptrdiff_t bank_fieldoffsets[2];
-
-    /* Function for making any access checks for this register in addition to
-     * those specified by the 'access' permissions bits. If NULL, no extra
-     * checks required. The access check is performed at runtime, not at
-     * translate time.
-     */
-    CPAccessFn *accessfn;
-    /* Function for handling reads of this register. If NULL, then reads
-     * will be done by loading from the offset into CPUARMState specified
-     * by fieldoffset.
-     */
-    CPReadFn *readfn;
-    /* Function for handling writes of this register. If NULL, then writes
-     * will be done by writing to the offset into CPUARMState specified
-     * by fieldoffset.
-     */
-    CPWriteFn *writefn;
-    /* Function for doing a "raw" read; used when we need to copy
-     * coprocessor state to the kernel for KVM or out for
-     * migration. This only needs to be provided if there is also a
-     * readfn and it has side effects (for instance clear-on-read bits).
-     */
-    CPReadFn *raw_readfn;
-    /* Function for doing a "raw" write; used when we need to copy KVM
-     * kernel coprocessor state into userspace, or for inbound
-     * migration. This only needs to be provided if there is also a
-     * writefn and it masks out "unwritable" bits or has write-one-to-clear
-     * or similar behaviour.
-     */
-    CPWriteFn *raw_writefn;
-    /* Function for resetting the register. If NULL, then reset will be done
-     * by writing resetvalue to the field specified in fieldoffset. If
-     * fieldoffset is 0 then no reset will be done.
-     */
-    CPResetFn *resetfn;
-
-    /*
-     * "Original" writefn and readfn.
-     * For ARMv8.1-VHE register aliases, we overwrite the read/write
-     * accessor functions of various EL1/EL0 to perform the runtime
-     * check for which sysreg should actually be modified, and then
-     * forwards the operation.  Before overwriting the accessors,
-     * the original function is copied here, so that accesses that
-     * really do go to the EL1/EL0 version proceed normally.
-     * (The corresponding EL2 register is linked via opaque.)
-     */
-    CPReadFn *orig_readfn;
-    CPWriteFn *orig_writefn;
-};
-
-/* Macros which are lvalues for the field in CPUARMState for the
- * ARMCPRegInfo *ri.
- */
-#define CPREG_FIELD32(env, ri) \
-    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
-#define CPREG_FIELD64(env, ri) \
-    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
-
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
-
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque);
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                       const ARMCPRegInfo *regs, void *opaque);
-static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_arm_cp_regs_with_opaque(cpu, regs, 0);
-}
-static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
-}
-const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
-
-/*
- * Definition of an ARM co-processor register as viewed from
- * userspace. This is used for presenting sanitised versions of
- * registers to userspace when emulating the Linux AArch64 CPU
- * ID/feature ABI (advertised as HWCAP_CPUID).
- */
-typedef struct ARMCPRegUserSpaceInfo {
-    /* Name of register */
-    const char *name;
-
-    /* Is the name actually a glob pattern */
-    bool is_glob;
-
-    /* Only some bits are exported to user space */
-    uint64_t exported_bits;
-
-    /* Fixed bits are applied after the mask */
-    uint64_t fixed_bits;
-} ARMCPRegUserSpaceInfo;
-
-#define REGUSERINFO_SENTINEL { .name = NULL }
-
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
-
-/* CPWriteFn that can be used to implement writes-ignored behaviour */
-void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-                         uint64_t value);
-/* CPReadFn that can be used for read-as-zero behaviour */
-uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
-
-/* CPResetFn that does nothing, for use if no reset is required even
- * if fieldoffset is non zero.
- */
-void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
-
-/* Return true if this reginfo struct's field in the cpu state struct
- * is 64 bits wide.
- */
-static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
-{
-    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
-}
-
-static inline bool cp_access_ok(int current_el,
-                                const ARMCPRegInfo *ri, int isread)
-{
-    return (ri->access >> ((current_el * 2) + isread)) & 1;
-}
-
-/* Raw read of a coprocessor register (as needed for migration, etc) */
-uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
-
 /**
  * write_list_to_cpustate
  * @cpu: ARMCPU
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/cutils.h"
 #include "qemu/log.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
 
 static struct {
     hwaddr io_base;
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
 
 #define ICIP	0x00	/* Interrupt Controller IRQ Pending register */
 #define ICMR	0x04	/* Interrupt Controller Mask register */
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@
 #include "gicv3_internal.h"
 #include "hw/irq.h"
 #include "cpu.h"
+#include "target/arm/cpregs.h"
 
 /*
  * Special case return value from hppvi_index(); must be larger than
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "vgic_common.h"
 #include "migration/blocker.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
+
 
 #ifdef DEBUG_GICV3_KVM
 #define DPRINTF(fmt, ...) \
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "kvm_arm.h"
 #include "disas/capstone.h"
 #include "fpu/softfloat.h"
+#include "cpregs.h"
 
 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
 {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "hvf_arm.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
+#include "cpregs.h"
 
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/boards.h"
 #endif
+#include "cpregs.h"
 
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@
  */
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "internals.h"
 #include "exec/gdbstub.h"
+#include "internals.h"
+#include "cpregs.h"
 
 typedef struct RegisterSysregXmlParam {
     CPUState *cs;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
+#include "cpregs.h"
 
 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
 #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "internals.h"
 #include "exec/exec-all.h"
 #include "exec/cpu_ldst.h"
+#include "cpregs.h"
 
 #define SIGNBIT (uint32_t)0x80000000
 #define SIGNBIT64 ((uint64_t)1 << 63)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@
 #include "translate.h"
 #include "internals.h"
 #include "qemu/host-utils.h"
-
 #include "semihosting/semihost.h"
 #include "exec/gen-icount.h"
-
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
 #include "exec/log.h"
-
+#include "cpregs.h"
 #include "translate-a64.h"
 #include "qemu/atomic128.h"
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bitops.h"
 #include "arm_ldst.h"
 #include "semihosting/semihost.h"
-
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
-
 #include "exec/log.h"
+#include "cpregs.h"
 
 
 #define ENABLE_ARCH_4T    arm_dc_feature(s, ARM_FEATURE_V4T)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Rearrange the values of the enumerators of CPAccessResult
so that we may directly extract the target el. For the two
special cases in access_check_cp_reg, use CPAccessResult.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ static inline bool cptype_valid(int cptype)
 typedef enum CPAccessResult {
     /* Access is permitted */
     CP_ACCESS_OK = 0,
+
+    /*
+     * Combined with one of the following, the low 2 bits indicate the
+     * target exception level.  If 0, the exception is taken to the usual
+     * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
+     */
+    CP_ACCESS_EL_MASK = 3,
+
     /*
      * Access fails due to a configurable trap or enable which would
      * result in a categorized exception syndrome giving information about
      * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
-     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
-     * PL1 if in EL0, otherwise to the current EL).
+     * 0xc or 0x18).
      */
-    CP_ACCESS_TRAP = 1,
+    CP_ACCESS_TRAP = (1 << 2),
+    CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
+    CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
+
     /*
      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
      * Note that this is not a catch-all case -- the set of cases which may
      * result in this failure is specifically defined by the architecture.
      */
-    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
-    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_EL2 = 3,
-    CP_ACCESS_TRAP_EL3 = 4,
-    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
+    CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
 } CPAccessResult;
 
 typedef struct ARMCPRegInfo ARMCPRegInfo;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
                                  uint32_t isread)
 {
     const ARMCPRegInfo *ri = rip;
+    CPAccessResult res = CP_ACCESS_OK;
     int target_el;
 
     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
-        raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
+        res = CP_ACCESS_TRAP;
+        goto fail;
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
         mask &= ~((1 << 4) | (1 << 14));
 
         if (env->cp15.hstr_el2 & mask) {
-            target_el = 2;
-            goto exept;
+            res = CP_ACCESS_TRAP_EL2;
+            goto fail;
         }
     }
 
-    if (!ri->accessfn) {
+    if (ri->accessfn) {
+        res = ri->accessfn(env, ri, isread);
+    }
+    if (likely(res == CP_ACCESS_OK)) {
         return;
     }
 
-    switch (ri->accessfn(env, ri, isread)) {
-    case CP_ACCESS_OK:
-        return;
+ fail:
+    switch (res & ~CP_ACCESS_EL_MASK) {
     case CP_ACCESS_TRAP:
-        target_el = exception_target_el(env);
-        break;
-    case CP_ACCESS_TRAP_EL2:
-        /* Requesting a trap to EL2 when we're in EL3 is
-         * a bug in the access function.
-         */
-        assert(arm_current_el(env) != 3);
-        target_el = 2;
-        break;
-    case CP_ACCESS_TRAP_EL3:
-        target_el = 3;
         break;
     case CP_ACCESS_TRAP_UNCATEGORIZED:
-        target_el = exception_target_el(env);
-        syndrome = syn_uncategorized();
-        break;
-    case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
-        target_el = 2;
-        syndrome = syn_uncategorized();
-        break;
-    case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
-        target_el = 3;
         syndrome = syn_uncategorized();
         break;
     default:
         g_assert_not_reached();
     }
 
-exept:
+    target_el = res & CP_ACCESS_EL_MASK;
+    switch (target_el) {
+    case 0:
+        target_el = exception_target_el(env);
+        break;
+    case 2:
+        assert(arm_current_el(env) != 3);
+        assert(arm_is_el2_enabled(env));
+        break;
+    case 3:
+        assert(arm_feature(env, ARM_FEATURE_EL3));
+        break;
+    default:
+        /* No "direct" traps to EL1 */
+        g_assert_not_reached();
+    }
+
     raise_exception(env, EXCP_UDEF, syndrome, target_el);
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Remove a possible source of error by removing REGINFO_SENTINEL
and using ARRAY_SIZE (convinently hidden inside a macro) to
find the end of the set of regs being registered or modified.

The space saved by not having the extra array element reduces
the executable's .data.rel.ro section by about 9k.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h       |  53 +++++++++---------
 hw/arm/pxa2xx.c           |   1 -
 hw/arm/pxa2xx_pic.c       |   1 -
 hw/intc/arm_gicv3_cpuif.c |   5 --
 hw/intc/arm_gicv3_kvm.c   |   1 -
 target/arm/cpu64.c        |   1 -
 target/arm/cpu_tcg.c      |   4 --
 target/arm/helper.c       | 111 ++++++++------------------------------
 8 files changed, 48 insertions(+), 129 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
 #define ARM_CP_NO_GDB            0x4000
 #define ARM_CP_RAISES_EXC        0x8000
 #define ARM_CP_NEWEL             0x10000
-/* Used only as a terminator for ARMCPRegInfo lists */
-#define ARM_CP_SENTINEL          0xfffff
 /* Mask of only the flag bits in a type field */
 #define ARM_CP_FLAG_MASK         0x1f0ff
 
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
 };
 
-/*
- * Return true if cptype is a valid type field. This is used to try to
- * catch errors where the sentinel has been accidentally left off the end
- * of a list of registers.
- */
-static inline bool cptype_valid(int cptype)
-{
-    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
-        || ((cptype & ARM_CP_SPECIAL) &&
-            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
-}
-
 /*
  * Access rights:
  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
 #define CPREG_FIELD64(env, ri) \
     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
+                                       void *opaque);
 
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque);
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                       const ARMCPRegInfo *regs, void *opaque);
-static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_arm_cp_regs_with_opaque(cpu, regs, 0);
-}
 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 {
-    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
+    define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
 }
+
+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+                                        void *opaque, size_t len);
+
+#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE)               \
+    do {                                                                \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
+        define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE,           \
+                                           ARRAY_SIZE(REGS));           \
+    } while (0)
+
+#define define_arm_cp_regs(CPU, REGS) \
+    define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
+
 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
 
 /*
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCPRegUserSpaceInfo {
     uint64_t fixed_bits;
 } ARMCPRegUserSpaceInfo;
 
-#define REGUSERINFO_SENTINEL { .name = NULL }
+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+                                 const ARMCPRegUserSpaceInfo *mods,
+                                 size_t mods_len);
 
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
+#define modify_arm_cp_regs(REGS, MODS)                                  \
+    do {                                                                \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0);                       \
+        modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS),             \
+                                    MODS, ARRAY_SIZE(MODS));            \
+    } while (0)
 
 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
     { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .type = ARM_CP_IO,
       .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
-    REGINFO_SENTINEL
 };
 
 static void pxa2xx_setup_cp14(PXA2xxState *s)
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
     REGINFO_FOR_PIC_CP("ICLR2", 8),
     REGINFO_FOR_PIC_CP("ICFP2", 9),
     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
-    REGINFO_SENTINEL
 };
 
 static const MemoryRegionOps pxa2xx_pic_ops = {
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
       .readfn = icc_igrpen1_el3_read,
       .writefn = icc_igrpen1_el3_write,
     },
-    REGINFO_SENTINEL
 };
 
 static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = {
       .readfn = ich_vmcr_read,
       .writefn = ich_vmcr_write,
     },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
       .readfn = ich_ap_read,
       .writefn = ich_ap_write,
     },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
       .readfn = ich_ap_read,
       .writefn = ich_ap_write,
     },
-    REGINFO_SENTINEL
 };
 
 static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
                       .readfn = ich_lr_read,
                       .writefn = ich_lr_write,
                     },
-                    REGINFO_SENTINEL
                 };
                 define_arm_cp_regs(cpu, lr_regset);
             }
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
        */
       .resetfn = arm_gicv3_icc_reset,
     },
-    REGINFO_SENTINEL
 };
 
 /**
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
     { .name = "L2MERRSR",
       .cp = 15, .opc1 = 3, .crm = 15,
       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void aarch64_a57_initfn(Object *obj)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a8_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a9_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 #endif
     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a7_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST },
     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static void cortex_r5_initfn(Object *obj)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
       .secure = ARM_CP_SECSTATE_S,
       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
      */
     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
       .access = PL1_W, .type = ARM_CP_WFI },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
       .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
-    REGINFO_SENTINEL
 };
 
 typedef struct pm_event {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
       .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
       .writefn = tlbimvaa_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
       .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
       .writefn = tlbimvaa_is_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsset_write,
       .raw_writefn = raw_write },
-    REGINFO_SENTINEL
 };
 
 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
       .accessfn = teehbr_access, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo v6k_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
     },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .readfn = gt_virt_cnt_read,
     },
-    REGINFO_SENTINEL
 };
 
 #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
       .access = PL1_W, .accessfn = ats_access,
       .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
 #endif
-    REGINFO_SENTINEL
 };
 
 /* Return basic MPU access permission bits.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
       .writefn = pmsav7_rgnr_write,
       .resetfn = arm_cp_reset_ignore },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
-    REGINFO_SENTINEL
 };
 
 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_tvm_trvm,
       .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
       .resetvalue = 0, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
       /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
                              offsetof(CPUARMState, cp15.tcr_el[1])} },
-    REGINFO_SENTINEL
 };
 
 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
     { .name = "C9", .cp = 15, .crn = 9,
       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
     { .name = "XSCALE_UNLOCK_DCACHE",
       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
       .access = PL1_RW,
       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
       .resetvalue = (1 << 30) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
       .access = PL1_RW, .resetvalue = 0,
       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
-    REGINFO_SENTINEL
 };
 
 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                              offsetof(CPUARMState, cp15.ttbr1_ns) },
       .writefn = vmsa_ttbr_write, },
-    REGINFO_SENTINEL
 };
 
 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
       .writefn = sdcr_write,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
-    REGINFO_SENTINEL
 };
 
 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .type = ARM_CP_CONST,
       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
       .access = PL2_RW, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 /* Ditto, but for registers which exist in ARMv8 but not v7 */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
       .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
       .access = PL2_RW,
       .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
       .access = PL2_RW,
       .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
       .access = PL2_RW,
       .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
       .writefn = hcr_writehigh },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
       .access = PL2_RW, .accessfn = sel2_access,
       .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae3_write },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tda,
       .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 /* Return the exception level to which exceptions should be taken
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
               .writefn = dbgbcr_write, .raw_writefn = raw_write
             },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, dbgregs);
     }
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
               .writefn = dbgwcr_write, .raw_writefn = raw_write
             },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, dbgregs);
     }
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .type = ARM_CP_IO,
               .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
               .raw_writefn = pmevtyper_rawwrite },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, pmev_regs);
         g_free(pmevcntr_name);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
               .resetvalue = extract64(cpu->pmceid1, 32, 32) },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, v81_pmu_regs);
     }
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
       .access = PL1_R, .accessfn = access_lor_ns,
       .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 #ifdef TARGET_AARCH64
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_pauth,
       .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo tlbirange_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae3_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo tlbios_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae3is_write },
-    REGINFO_SENTINEL
 };
 
 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rndr_reginfo[] = {
       .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
       .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
       .access = PL0_R, .readfn = rndr_readfn },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo dcpodp_reg[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
-    REGINFO_SENTINEL
 };
 #endif /*CONFIG_USER_ONLY*/
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
     { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
     { .name = "TCO", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
       .type = ARM_CP_CONST, .access = PL0_RW, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
       .accessfn = aa64_zva_access,
 #endif
     },
-    REGINFO_SENTINEL
 };
 
 #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
     { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-    REGINFO_SENTINEL
 };
 
 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
       .access = PL1_R,
       .accessfn = access_aa64_tid2,
       .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
       .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
       .accessfn = access_joscr_jmcr,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo vhe_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
       .access = PL2_RW, .accessfn = e2h_access,
       .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
 #endif
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write64 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo ats1cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write },
-    REGINFO_SENTINEL
 };
 #endif
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
       .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
       .access = PL2_RW, .type = ARM_CP_CONST,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 void register_cp_regs_for_features(ARMCPU *cpu)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa32_tid3,
               .resetvalue = cpu->isar.id_isar6 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, v6_idregs);
         define_arm_cp_regs(cpu, v6_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
               .resetvalue = cpu->pmceid1 },
-            REGINFO_SENTINEL
         };
 #ifdef CONFIG_USER_ONLY
         ARMCPRegUserSpaceInfo v8_user_idregs[] = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .exported_bits = 0x000000f0ffffffff },
             { .name = "ID_AA64ISAR*_EL1_RESERVED",
               .is_glob = true                     },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(v8_idregs, v8_user_idregs);
 #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL2_RW,
               .resetvalue = vmpidr_def,
               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, vpidr_regs);
         define_arm_cp_regs(cpu, el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                   .access = PL2_RW, .accessfn = access_el3_aa32ns,
                   .type = ARM_CP_NO_RAW,
                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
-                REGINFO_SENTINEL
             };
             define_arm_cp_regs(cpu, vpidr_regs);
             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .raw_writefn = raw_write, .writefn = sctlr_write,
               .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
               .resetvalue = cpu->reset_sctlr },
-            REGINFO_SENTINEL
         };
 
         define_arm_cp_regs(cpu, el3_regs);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "DUMMY",
               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R,
               .accessfn = access_aa64_tid1,
               .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
-            REGINFO_SENTINEL
         };
         ARMCPRegInfo id_cp_reginfo[] = {
             /* These are common to v8 and pre-v8 */
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R,
               .accessfn = access_aa32_tid1,
               .type = ARM_CP_CONST, .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         /* TLBTR is specific to VMSA */
         ARMCPRegInfo id_tlbtr_reginfo = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "MIDR_EL1",
               .exported_bits = 0x00000000ffffffff },
             { .name = "REVIDR_EL1"                },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
 #endif
         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
             arm_feature(env, ARM_FEATURE_STRONGARM)) {
-            ARMCPRegInfo *r;
+            size_t i;
             /* Register the blanket "writes ignored" value first to cover the
              * whole space. Then update the specific ID registers to allow write
              * access, so that they ignore writes rather than causing them to
              * UNDEF.
              */
             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
-            for (r = id_pre_v8_midr_cp_reginfo;
-                 r->type != ARM_CP_SENTINEL; r++) {
-                r->access = PL1_RW;
+            for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) {
+                id_pre_v8_midr_cp_reginfo[i].access = PL1_RW;
             }
-            for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
-                r->access = PL1_RW;
+            for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) {
+                id_cp_reginfo[i].access = PL1_RW;
             }
             id_mpuir_reginfo.access = PL1_RW;
             id_tlbtr_reginfo.access = PL1_RW;
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
-            REGINFO_SENTINEL
         };
 #ifdef CONFIG_USER_ONLY
         ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
             { .name = "MPIDR_EL1",
               .fixed_bits = 0x0000000080000000 },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
 #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
               .access = PL3_RW, .type = ARM_CP_CONST,
               .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, auxcr_reginfo);
         if (cpu_isar_feature(aa32_ac2, cpu)) {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                   .type = ARM_CP_CONST,
                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
-                REGINFO_SENTINEL
             };
             /* We don't implement a r/w 64 bit CBAR currently */
             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                      offsetof(CPUARMState, cp15.vbar_ns) },
               .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, vbar_cp_reginfo);
     }
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                    r->writefn);
         }
     }
-    /* Bad type field probably means missing sentinel at end of reg list */
-    assert(cptype_valid(r->type));
+
     for (crm = crmmin; crm <= crmmax; crm++) {
         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
     }
 }
 
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque)
+/* Define a whole list of registers */
+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+                                        void *opaque, size_t len)
 {
-    /* Define a whole list of registers */
-    const ARMCPRegInfo *r;
-    for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
-        define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
+    size_t i;
+    for (i = 0; i < len; ++i) {
+        define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
  * user-space cannot alter any values and dynamic values pertaining to
  * execution state are hidden from user space view anyway.
  */
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+                                 const ARMCPRegUserSpaceInfo *mods,
+                                 size_t mods_len)
 {
-    const ARMCPRegUserSpaceInfo *m;
-    ARMCPRegInfo *r;
-
-    for (m = mods; m->name; m++) {
+    for (size_t mi = 0; mi < mods_len; ++mi) {
+        const ARMCPRegUserSpaceInfo *m = mods + mi;
         GPatternSpec *pat = NULL;
+
         if (m->is_glob) {
             pat = g_pattern_spec_new(m->name);
         }
-        for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
+        for (size_t ri = 0; ri < regs_len; ++ri) {
+            ARMCPRegInfo *r = regs + ri;
+
             if (pat && g_pattern_match_string(pat, r->name)) {
                 r->type = ARM_CP_CONST;
                 r->access = PL0U_R;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These particular data structures are not modified at runtime.

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .resetvalue = cpu->pmceid1 },
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+        static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
             { .name = "ID_AA64PFR0_EL1",
               .exported_bits = 0x000f000f00ff0000,
               .fixed_bits    = 0x0000000000000011 },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      */
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR", .type = ARM_CP_CONST,
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL1_RW, .accessfn = nsacr_access,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             };
             define_one_arm_cp_reg(cpu, &nsacr);
         } else {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR",
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL3_RW | PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
     } else {
         if (arm_feature(env, ARM_FEATURE_V8)) {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR", .type = ARM_CP_CONST,
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = cpu->pmsav7_dregion << 8
         };
-        ARMCPRegInfo crn0_wi_reginfo = {
+        static const ARMCPRegInfo crn0_wi_reginfo = {
             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
+        static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1",
               .exported_bits = 0x00000000ffffffff },
             { .name = "REVIDR_EL1"                },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
+        static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
             { .name = "MPIDR_EL1",
               .fixed_bits = 0x0000000080000000 },
         };
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (arm_feature(env, ARM_FEATURE_VBAR)) {
-        ARMCPRegInfo vbar_cp_reginfo[] = {
+        static const ARMCPRegInfo vbar_cp_reginfo[] = {
             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
               .access = PL1_RW, .writefn = vbar_write,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Instead of defining ARM_CP_FLAG_MASK to remove flags,
define ARM_CP_SPECIAL_MASK to isolate special cases.
Sort the specials to the low bits. Use an enum.

Split the large comment block so as to document each
value separately.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h        | 130 +++++++++++++++++++++++--------------
 target/arm/cpu.c           |   4 +-
 target/arm/helper.c        |   4 +-
 target/arm/translate-a64.c |   6 +-
 target/arm/translate.c     |   6 +-
 5 files changed, 92 insertions(+), 58 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
 #define TARGET_ARM_CPREGS_H
 
 /*
- * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
- * special-behaviour cp reg and bits [11..8] indicate what behaviour
- * it has. Otherwise it is a simple cp reg, where CONST indicates that
- * TCG can assume the value to be constant (ie load at translate time)
- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
- * indicates that the TB should not be ended after a write to this register
- * (the default is that the TB ends after cp writes). OVERRIDE permits
- * a register definition to override a previous definition for the
- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
- * old must have the OVERRIDE bit set.
- * ALIAS indicates that this register is an alias view of some underlying
- * state which is also visible via another register, and that the other
- * register is handling migration and reset; registers marked ALIAS will not be
- * migrated but may have their state set by syncing of register state from KVM.
- * NO_RAW indicates that this register has no underlying state and does not
- * support raw access for state saving/loading; it will not be used for either
- * migration or KVM state synchronization. (Typically this is for "registers"
- * which are actually used as instructions for cache maintenance and so on.)
- * IO indicates that this register does I/O and therefore its accesses
- * need to be marked with gen_io_start() and also end the TB. In particular,
- * registers which implement clocks or timers require this.
- * RAISES_EXC is for when the read or write hook might raise an exception;
- * the generated code will synchronize the CPU state before calling the hook
- * so that it is safe for the hook to call raise_exception().
- * NEWEL is for writes to registers that might change the exception
- * level - typically on older ARM chips. For those cases we need to
- * re-read the new el when recomputing the translation flags.
+ * ARMCPRegInfo type field bits:
  */
-#define ARM_CP_SPECIAL           0x0001
-#define ARM_CP_CONST             0x0002
-#define ARM_CP_64BIT             0x0004
-#define ARM_CP_SUPPRESS_TB_END   0x0008
-#define ARM_CP_OVERRIDE          0x0010
-#define ARM_CP_ALIAS             0x0020
-#define ARM_CP_IO                0x0040
-#define ARM_CP_NO_RAW            0x0080
-#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
-#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
-#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
-#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
-#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
-#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
-#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
-#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
-#define ARM_CP_FPU               0x1000
-#define ARM_CP_SVE               0x2000
-#define ARM_CP_NO_GDB            0x4000
-#define ARM_CP_RAISES_EXC        0x8000
-#define ARM_CP_NEWEL             0x10000
-/* Mask of only the flag bits in a type field */
-#define ARM_CP_FLAG_MASK         0x1f0ff
+enum {
+    /*
+     * Register must be handled specially during translation.
+     * The method is one of the values below:
+     */
+    ARM_CP_SPECIAL_MASK          = 0x000f,
+    /* Special: no change to PE state: writes ignored, reads ignored. */
+    ARM_CP_NOP                   = 0x0001,
+    /* Special: sysreg is WFI, for v5 and v6. */
+    ARM_CP_WFI                   = 0x0002,
+    /* Special: sysreg is NZCV. */
+    ARM_CP_NZCV                  = 0x0003,
+    /* Special: sysreg is CURRENTEL. */
+    ARM_CP_CURRENTEL             = 0x0004,
+    /* Special: sysreg is DC ZVA or similar. */
+    ARM_CP_DC_ZVA                = 0x0005,
+    ARM_CP_DC_GVA                = 0x0006,
+    ARM_CP_DC_GZVA               = 0x0007,
+
+    /* Flag: reads produce resetvalue; writes ignored. */
+    ARM_CP_CONST                 = 1 << 4,
+    /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
+    ARM_CP_64BIT                 = 1 << 5,
+    /*
+     * Flag: TB should not be ended after a write to this register
+     * (the default is that the TB ends after cp writes).
+     */
+    ARM_CP_SUPPRESS_TB_END       = 1 << 6,
+    /*
+     * Flag: Permit a register definition to override a previous definition
+     * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new
+     * or the old must have the ARM_CP_OVERRIDE bit set.
+     */
+    ARM_CP_OVERRIDE              = 1 << 7,
+    /*
+     * Flag: Register is an alias view of some underlying state which is also
+     * visible via another register, and that the other register is handling
+     * migration and reset; registers marked ARM_CP_ALIAS will not be migrated
+     * but may have their state set by syncing of register state from KVM.
+     */
+    ARM_CP_ALIAS                 = 1 << 8,
+    /*
+     * Flag: Register does I/O and therefore its accesses need to be marked
+     * with gen_io_start() and also end the TB. In particular, registers which
+     * implement clocks or timers require this.
+     */
+    ARM_CP_IO                    = 1 << 9,
+    /*
+     * Flag: Register has no underlying state and does not support raw access
+     * for state saving/loading; it will not be used for either migration or
+     * KVM state synchronization. Typically this is for "registers" which are
+     * actually used as instructions for cache maintenance and so on.
+     */
+    ARM_CP_NO_RAW                = 1 << 10,
+    /*
+     * Flag: The read or write hook might raise an exception; the generated
+     * code will synchronize the CPU state before calling the hook so that it
+     * is safe for the hook to call raise_exception().
+     */
+    ARM_CP_RAISES_EXC            = 1 << 11,
+    /*
+     * Flag: Writes to the sysreg might change the exception level - typically
+     * on older ARM chips. For those cases we need to re-read the new el when
+     * recomputing the translation flags.
+     */
+    ARM_CP_NEWEL                 = 1 << 12,
+    /*
+     * Flag: Access check for this sysreg is identical to accessing FPU state
+     * from an instruction: use translation fp_access_check().
+     */
+    ARM_CP_FPU                   = 1 << 13,
+    /*
+     * Flag: Access check for this sysreg is identical to accessing SVE state
+     * from an instruction: use translation sve_access_check().
+     */
+    ARM_CP_SVE                   = 1 << 14,
+    /* Flag: Do not expose in gdb sysreg xml. */
+    ARM_CP_NO_GDB                = 1 << 15,
+};
 
 /*
  * Valid values for ARMCPRegInfo state field, indicating which of
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
     ARMCPRegInfo *ri = value;
     ARMCPU *cpu = opaque;
 
-    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
     ARMCPU *cpu = opaque;
     uint64_t oldvalue, newvalue;
 
-    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
         return;
     }
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * multiple times. Special registers (ie NOP/WFI) are
      * never migratable and not even raw-accessible.
      */
-    if ((r->type & ARM_CP_SPECIAL)) {
+    if (r->type & ARM_CP_SPECIAL_MASK) {
         r2->type |= ARM_CP_NO_RAW;
     }
     if (((r->crm == CP_ANY) && crm != 0) ||
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
     /* Check that the register definition has enough info to handle
      * reads and writes if they are permitted.
      */
-    if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
+    if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
         if (r->access & PL3_R) {
             assert((r->fieldoffset ||
                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
     }
 
     /* Handle special cases first */
-    switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
+    switch (ri->type & ARM_CP_SPECIAL_MASK) {
+    case 0:
+        break;
     case ARM_CP_NOP:
         return;
     case ARM_CP_NZCV:
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         }
         return;
     default:
-        break;
+        g_assert_not_reached();
     }
     if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
         return;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
         }
 
         /* Handle special cases first */
-        switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
+        switch (ri->type & ARM_CP_SPECIAL_MASK) {
+        case 0:
+            break;
         case ARM_CP_NOP:
             return;
         case ARM_CP_WFI:
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
             s->base.is_jmp = DISAS_WFI;
             return;
         default:
-            break;
+            g_assert_not_reached();
         }
 
         if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Standardize on g_assert_not_reached() for "should not happen".
Retain abort() when preceeded by fprintf or error_report.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c         | 7 +++----
 target/arm/hvf/hvf.c        | 2 +-
 target/arm/kvm-stub.c       | 4 ++--
 target/arm/kvm.c            | 4 ++--
 target/arm/machine.c        | 4 ++--
 target/arm/translate-a64.c  | 4 ++--
 target/arm/translate-neon.c | 2 +-
 target/arm/translate.c      | 4 ++--
 8 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
             break;
         default:
             /* broken reginfo with out-of-range opc1 */
-            assert(false);
-            break;
+            g_assert_not_reached();
         }
         /* assert our permissions are not too lax (stricter is fine) */
         assert((r->access & ~mask) == 0);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
             break;
         default:
             /* Never happens, but compiler isn't smart enough to tell.  */
-            abort();
+            g_assert_not_reached();
         }
     }
     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
             break;
         default:
             /* Never happens, but compiler isn't smart enough to tell.  */
-            abort();
+            g_assert_not_reached();
         }
     }
     if (domain_prot == 3) {
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
         /* we got kicked, no exit to process */
         return 0;
     default:
-        assert(0);
+        g_assert_not_reached();
     }
 
     hvf_sync_vtimer(cpu);
diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm-stub.c
+++ b/target/arm/kvm-stub.c
@@ -XXX,XX +XXX,XX @@
 
 bool write_kvmstate_to_list(ARMCPU *cpu)
 {
-    abort();
+    g_assert_not_reached();
 }
 
 bool write_list_to_kvmstate(ARMCPU *cpu, int level)
 {
-    abort();
+    g_assert_not_reached();
 }
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
             ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         if (ret) {
             ok = false;
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
             r.addr = (uintptr_t)(cpu->cpreg_values + i);
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
         if (ret) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
     if (kvm_enabled()) {
         if (!write_kvmstate_to_list(cpu)) {
             /* This should never fail */
-            abort();
+            g_assert_not_reached();
         }
 
         /*
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
     } else {
         if (!write_cpustate_to_list(cpu, false)) {
             /* This should never fail. */
-            abort();
+            g_assert_not_reached();
         }
     }
 
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
         gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
 
     write_fp_sreg(s, rd, tcg_res);
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
         break;
     }
     default:
-        abort();
+        g_assert_not_reached();
     }
 }
 
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
         }
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
     if ((vd + a->stride * (nregs - 1)) > 31) {
         /*
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
         offset = 4;
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
     tcg_gen_addi_i32(addr, addr, offset);
     tmp = load_reg(s, 14);
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
             offset = 0;
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         tcg_gen_addi_i32(addr, addr, offset);
         gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a typedef as well, and use it in ARMCPRegInfo.
This won't be perfect for debugging, but it'll nicely
display the most common cases.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 44 +++++++++++++++++++++++---------------------
 target/arm/helper.c |  2 +-
 2 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
  * described with these bits, then use a laxer set of restrictions, and
  * do the more restrictive/complex check inside a helper function.
  */
-#define PL3_R 0x80
-#define PL3_W 0x40
-#define PL2_R (0x20 | PL3_R)
-#define PL2_W (0x10 | PL3_W)
-#define PL1_R (0x08 | PL2_R)
-#define PL1_W (0x04 | PL2_W)
-#define PL0_R (0x02 | PL1_R)
-#define PL0_W (0x01 | PL1_W)
+typedef enum {
+    PL3_R = 0x80,
+    PL3_W = 0x40,
+    PL2_R = 0x20 | PL3_R,
+    PL2_W = 0x10 | PL3_W,
+    PL1_R = 0x08 | PL2_R,
+    PL1_W = 0x04 | PL2_W,
+    PL0_R = 0x02 | PL1_R,
+    PL0_W = 0x01 | PL1_W,
 
-/*
- * For user-mode some registers are accessible to EL0 via a kernel
- * trap-and-emulate ABI. In this case we define the read permissions
- * as actually being PL0_R. However some bits of any given register
- * may still be masked.
- */
+    /*
+     * For user-mode some registers are accessible to EL0 via a kernel
+     * trap-and-emulate ABI. In this case we define the read permissions
+     * as actually being PL0_R. However some bits of any given register
+     * may still be masked.
+     */
 #ifdef CONFIG_USER_ONLY
-#define PL0U_R PL0_R
+    PL0U_R = PL0_R,
 #else
-#define PL0U_R PL1_R
+    PL0U_R = PL1_R,
 #endif
 
-#define PL3_RW (PL3_R | PL3_W)
-#define PL2_RW (PL2_R | PL2_W)
-#define PL1_RW (PL1_R | PL1_W)
-#define PL0_RW (PL0_R | PL0_W)
+    PL3_RW = PL3_R | PL3_W,
+    PL2_RW = PL2_R | PL2_W,
+    PL1_RW = PL1_R | PL1_W,
+    PL0_RW = PL0_R | PL0_W,
+} CPAccessRights;
 
 typedef enum CPAccessResult {
     /* Access is permitted */
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     /* Register type: ARM_CP_* bits/values */
     int type;
     /* Access rights: PL*_[RW] */
-    int access;
+    CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
     int secure;
     /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      * to encompass the generic architectural permission check.
      */
     if (r->state != ARM_CP_STATE_AA32) {
-        int mask = 0;
+        CPAccessRights mask;
         switch (r->opc1) {
         case 0:
             /* min_EL EL1, but some accessible to EL0 via kernel ABI */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Give this enum a name and use in ARMCPRegInfo,
add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
  * Note that we rely on the values of these enums as we iterate through
  * the various states in some places.
  */
-enum {
+typedef enum {
     ARM_CP_STATE_AA32 = 0,
     ARM_CP_STATE_AA64 = 1,
     ARM_CP_STATE_BOTH = 2,
-};
+} CPState;
 
 /*
  * ARM CP register secure state flags.  These flags identify security state
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     uint8_t opc1;
     uint8_t opc2;
     /* Execution state in which this register is visible: ARM_CP_STATE_* */
-    int state;
+    CPState state;
     /* Register type: ARM_CP_* bits/values */
     int type;
     /* Access rights: PL*_[RW] */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-                                   void *opaque, int state, int secstate,
+                                   void *opaque, CPState state, int secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
      * the register, if any.
      */
-    int crm, opc1, opc2, state;
+    int crm, opc1, opc2;
     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
+    CPState state;
+
     /* 64 bit registers have only CRm and Opc1 fields */
     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
     /* op0 only exists in the AArch64 encodings */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 7 ++++---
 target/arm/helper.c | 7 +++++--
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  * registered entry will only have one to identify whether the entry is secure
  * or non-secure.
  */
-enum {
+typedef enum {
+    ARM_CP_SECSTATE_BOTH = 0,       /* define one cpreg for each secstate */
     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
-};
+} CPSecureState;
 
 /*
  * Access rights:
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     /* Access rights: PL*_[RW] */
     CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
-    int secure;
+    CPSecureState secure;
     /*
      * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
      * this register was defined: can be used to hand data through to the
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-                                   void *opaque, CPState state, int secstate,
+                                   void *opaque, CPState state,
+                                   CPSecureState secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                                    r->secure, crm, opc1, opc2,
                                                    r->name);
                             break;
-                        default:
+                        case ARM_CP_SECSTATE_BOTH:
                             name = g_strdup_printf("%s_S", r->name);
                             add_cpreg_to_hashtable(cpu, r, opaque, state,
                                                    ARM_CP_SECSTATE_S,
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                                    ARM_CP_SECSTATE_NS,
                                                    crm, opc1, opc2, r->name);
                             break;
+                        default:
+                            g_assert_not_reached();
                         }
                     } else {
                         /* AArch64 registers get mapped to non-secure instance
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The new_key field is always non-zero -- drop the if.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-11-richard.henderson@linaro.org
[PMM: reinstated dropped PL3_RW mask]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
 
     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
         const struct E2HAlias *a = &aliases[i];
-        ARMCPRegInfo *src_reg, *dst_reg;
+        ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
+        uint32_t *new_key;
+        bool ok;
 
         if (a->feature && !a->feature(&cpu->isar)) {
             continue;
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
         g_assert(src_reg->opaque == NULL);
 
         /* Create alias before redirection so we dup the right data. */
-        if (a->new_key) {
-            ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-            uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
-            bool ok;
+        new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
+        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
 
-            new_reg->name = a->new_name;
-            new_reg->type |= ARM_CP_ALIAS;
-            /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
-            new_reg->access &= PL2_RW | PL3_RW;
+        new_reg->name = a->new_name;
+        new_reg->type |= ARM_CP_ALIAS;
+        /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
+        new_reg->access &= PL2_RW | PL3_RW;
 
-            ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
-            g_assert(ok);
-        }
+        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
+        g_assert(ok);
 
         src_reg->opaque = dst_reg;
         src_reg->orig_readfn = src_reg->readfn ?: raw_read;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Cast the uint32_t key into a gpointer directly, which
allows us to avoid allocating storage for each key.

Use g_hash_table_lookup when we already have a gpointer
(e.g. for callbacks like count_cpreg), or when using
get_arm_cp_reginfo would require casting away const.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c     |  4 ++--
 target/arm/gdbstub.c |  2 +-
 target/arm/helper.c  | 41 ++++++++++++++++++-----------------------
 3 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
     ARMCPU *cpu = ARM_CPU(obj);
 
     cpu_set_cpustate_pointers(cpu);
-    cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
-                                         g_free, cpreg_hashtable_data_destroy);
+    cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
+                                         NULL, cpreg_hashtable_data_destroy);
 
     QLIST_INIT(&cpu->pre_el_change_hooks);
     QLIST_INIT(&cpu->el_change_hooks);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
 static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
                                         gpointer p)
 {
-    uint32_t ri_key = *(uint32_t *)key;
+    uint32_t ri_key = (uintptr_t)key;
     ARMCPRegInfo *ri = value;
     RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
     GString *s = param->s;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 {
     ARMCPU *cpu = opaque;
-    uint64_t regidx;
-    const ARMCPRegInfo *ri;
-
-    regidx = *(uint32_t *)key;
-    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+    uint32_t regidx = (uintptr_t)key;
+    const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 
     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
 static void count_cpreg(gpointer key, gpointer opaque)
 {
     ARMCPU *cpu = opaque;
-    uint64_t regidx;
     const ARMCPRegInfo *ri;
 
-    regidx = *(uint32_t *)key;
-    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+    ri = g_hash_table_lookup(cpu->cp_regs, key);
 
     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
         cpu->cpreg_array_len++;
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
 
 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 {
-    uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
-    uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
+    uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a);
+    uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b);
 
     if (aidx > bidx) {
         return 1;
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
         const struct E2HAlias *a = &aliases[i];
         ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
-        uint32_t *new_key;
         bool ok;
 
         if (a->feature && !a->feature(&cpu->isar)) {
             continue;
         }
 
-        src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
-        dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
+        src_reg = g_hash_table_lookup(cpu->cp_regs,
+                                      (gpointer)(uintptr_t)a->src_key);
+        dst_reg = g_hash_table_lookup(cpu->cp_regs,
+                                      (gpointer)(uintptr_t)a->dst_key);
         g_assert(src_reg != NULL);
         g_assert(dst_reg != NULL);
 
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
 
         /* Create alias before redirection so we dup the right data. */
         new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
 
         new_reg->name = a->new_name;
         new_reg->type |= ARM_CP_ALIAS;
         /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
         new_reg->access &= PL2_RW | PL3_RW;
 
-        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
+        ok = g_hash_table_insert(cpu->cp_regs,
+                                 (gpointer)(uintptr_t)a->new_key, new_reg);
         g_assert(ok);
 
         src_reg->opaque = dst_reg;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     /* Private utility function for define_one_arm_cp_reg_with_opaque():
      * add a single reginfo struct to the hash table.
      */
-    uint32_t *key = g_new(uint32_t, 1);
+    uint32_t key;
     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
             r2->cp = CP_REG_ARM64_SYSREG_CP;
         }
-        *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
-                                  r2->opc0, opc1, opc2);
+        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
+                                 r2->opc0, opc1, opc2);
     } else {
-        *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
+        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
     }
     if (opaque) {
         r2->opaque = opaque;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * requested.
      */
     if (!(r->type & ARM_CP_OVERRIDE)) {
-        ARMCPRegInfo *oldreg;
-        oldreg = g_hash_table_lookup(cpu->cp_regs, key);
+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
             fprintf(stderr, "Register redefined: cp=%d %d bit "
                     "crn=%d crm=%d opc1=%d opc2=%d, "
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
             g_assert_not_reached();
         }
     }
-    g_hash_table_insert(cpu->cp_regs, key, r2);
+    g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
 }
 
 
@@ -XXX,XX +XXX,XX @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
 
 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
 {
-    return g_hash_table_lookup(cpregs, &encoded_cp);
+    return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp);
 }
 
 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Simplify freeing cp_regs hash table entries by using a single
allocation for the entire value.

This fixes a theoretical bug if we were to ever free the entire
hash table, because we've been installing string literal constants
into the cpreg structure in define_arm_vh_e2h_redirects_aliases.
However, at present we only free entries created for AArch32
wildcard cpregs which get overwritten by more specific cpregs,
so this bug is never exposed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c    | 16 +---------------
 target/arm/helper.c | 10 ++++++++--
 2 files changed, 9 insertions(+), 17 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 }
 
-static void cpreg_hashtable_data_destroy(gpointer data)
-{
-    /*
-     * Destroy function for cpu->cp_regs hashtable data entries.
-     * We must free the name string because it was g_strdup()ed in
-     * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
-     * from r->name because we know we definitely allocated it.
-     */
-    ARMCPRegInfo *r = data;
-
-    g_free((void *)r->name);
-    g_free(r);
-}
-
 static void arm_cpu_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
     cpu_set_cpustate_pointers(cpu);
     cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
-                                         NULL, cpreg_hashtable_data_destroy);
+                                         NULL, g_free);
 
     QLIST_INIT(&cpu->pre_el_change_hooks);
     QLIST_INIT(&cpu->el_change_hooks);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * add a single reginfo struct to the hash table.
      */
     uint32_t key;
-    ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
+    ARMCPRegInfo *r2;
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+    size_t name_len;
+
+    /* Combine cpreg and name into one allocation. */
+    name_len = strlen(name) + 1;
+    r2 = g_malloc(sizeof(*r2) + name_len);
+    *r2 = *r;
+    r2->name = memcpy(r2 + 1, name, name_len);
 
-    r2->name = g_strdup(name);
     /* Reset the secure state to the specific incoming state.  This is
      * necessary as the register may have been defined with both states.
      */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the computation of key to the top of the function.
Hoist the resolution of cp as well, as an input to the
computation of key.

This will be required by a subsequent patch.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 49 +++++++++++++++++++++++++--------------------
 1 file changed, 27 insertions(+), 22 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     ARMCPRegInfo *r2;
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+    int cp = r->cp;
     size_t name_len;
 
+    switch (state) {
+    case ARM_CP_STATE_AA32:
+        /* We assume it is a cp15 register if the .cp field is left unset. */
+        if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
+            cp = 15;
+        }
+        key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
+        break;
+    case ARM_CP_STATE_AA64:
+        /*
+         * To allow abbreviation of ARMCPRegInfo definitions, we treat
+         * cp == 0 as equivalent to the value for "standard guest-visible
+         * sysreg".  STATE_BOTH definitions are also always "standard sysreg"
+         * in their AArch64 view (the .cp value may be non-zero for the
+         * benefit of the AArch32 view).
+         */
+        if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+            cp = CP_REG_ARM64_SYSREG_CP;
+        }
+        key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
 
         if (r->state == ARM_CP_STATE_BOTH) {
-            /* We assume it is a cp15 register if the .cp field is left unset.
-             */
-            if (r2->cp == 0) {
-                r2->cp = 15;
-            }
-
 #if HOST_BIG_ENDIAN
             if (r2->fieldoffset) {
                 r2->fieldoffset += sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 #endif
         }
     }
-    if (state == ARM_CP_STATE_AA64) {
-        /* To allow abbreviation of ARMCPRegInfo
-         * definitions, we treat cp == 0 as equivalent to
-         * the value for "standard guest-visible sysreg".
-         * STATE_BOTH definitions are also always "standard
-         * sysreg" in their AArch64 view (the .cp value may
-         * be non-zero for the benefit of the AArch32 view).
-         */
-        if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
-            r2->cp = CP_REG_ARM64_SYSREG_CP;
-        }
-        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
-                                 r2->opc0, opc1, opc2);
-    } else {
-        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
-    }
     if (opaque) {
         r2->opaque = opaque;
     }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     /* Make sure reginfo passed to helpers for wildcarded regs
      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
      */
+    r2->cp = cp;
     r2->crm = crm;
     r2->opc1 = opc1;
     r2->opc2 = opc2;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Put most of the value writeback to the same place,
and improve the comment that goes with them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     *r2 = *r;
     r2->name = memcpy(r2 + 1, name, name_len);
 
-    /* Reset the secure state to the specific incoming state.  This is
-     * necessary as the register may have been defined with both states.
+    /*
+     * Update fields to match the instantiation, overwiting wildcards
+     * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
      */
+    r2->cp = cp;
+    r2->crm = crm;
+    r2->opc1 = opc1;
+    r2->opc2 = opc2;
+    r2->state = state;
     r2->secure = secstate;
+    if (opaque) {
+        r2->opaque = opaque;
+    }
 
     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
         /* Register is banked (using both entries in array).
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 #endif
         }
     }
-    if (opaque) {
-        r2->opaque = opaque;
-    }
-    /* reginfo passed to helpers is correct for the actual access,
-     * and is never ARM_CP_STATE_BOTH:
-     */
-    r2->state = state;
-    /* Make sure reginfo passed to helpers for wildcarded regs
-     * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
-     */
-    r2->cp = cp;
-    r2->crm = crm;
-    r2->opc1 = opc1;
-    r2->opc2 = opc2;
+
     /* By convention, for wildcarded registers only the first
      * entry is used for migration; the others are marked as
      * ALIAS so we don't try to transfer the register
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Computing isbanked only once makes the code
a bit easier to read.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Perform the override check early, so that it is still done
even when we decide to discard an unreachable cpreg.

Use assert not printf+abort.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         g_assert_not_reached();
     }
 
+    /* Overriding of an existing definition must be explicitly requested. */
+    if (!(r->type & ARM_CP_OVERRIDE)) {
+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
+        if (oldreg) {
+            assert(oldreg->type & ARM_CP_OVERRIDE);
+        }
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         assert(!raw_accessors_invalid(r2));
     }
 
-    /* Overriding of an existing definition must be explicitly
-     * requested.
-     */
-    if (!(r->type & ARM_CP_OVERRIDE)) {
-        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
-        if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
-            fprintf(stderr, "Register redefined: cp=%d %d bit "
-                    "crn=%d crm=%d opc1=%d opc2=%d, "
-                    "was %s, now %s\n", r2->cp, 32 + 32 * is64,
-                    r2->crn, r2->crm, r2->opc1, r2->opc2,
-                    oldreg->name, r2->name);
-            g_assert_not_reached();
-        }
-    }
     g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Put the block comments into the current coding style.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
     return cpu_list;
 }
 
+/*
+ * Private utility function for define_one_arm_cp_reg_with_opaque():
+ * add a single reginfo struct to the hash table.
+ */
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                    void *opaque, CPState state,
                                    CPSecureState secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
-    /* Private utility function for define_one_arm_cp_reg_with_opaque():
-     * add a single reginfo struct to the hash table.
-     */
     uint32_t key;
     ARMCPRegInfo *r2;
     bool is64 = r->type & ARM_CP_64BIT;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 
     isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
     if (isbanked) {
-        /* Register is banked (using both entries in array).
+        /*
+         * Register is banked (using both entries in array).
          * Overwriting fieldoffset as the array is only used to define
          * banked registers but later only fieldoffset is used.
          */
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 
     if (state == ARM_CP_STATE_AA32) {
         if (isbanked) {
-            /* If the register is banked then we don't need to migrate or
+            /*
+             * If the register is banked then we don't need to migrate or
              * reset the 32-bit instance in certain cases:
              *
              * 1) If the register has both 32-bit and 64-bit instances then we
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                 r2->type |= ARM_CP_ALIAS;
             }
         } else if ((secstate != r->secure) && !ns) {
-            /* The register is not banked so we only want to allow migration of
-             * the non-secure instance.
+            /*
+             * The register is not banked so we only want to allow migration
+             * of the non-secure instance.
              */
             r2->type |= ARM_CP_ALIAS;
         }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
     }
 
-    /* By convention, for wildcarded registers only the first
+    /*
+     * By convention, for wildcarded registers only the first
      * entry is used for migration; the others are marked as
      * ALIAS so we don't try to transfer the register
      * multiple times. Special registers (ie NOP/WFI) are
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
     }
 
-    /* Check that raw accesses are either forbidden or handled. Note that
+    /*
+     * Check that raw accesses are either forbidden or handled. Note that
      * we can't assert this earlier because the setup of fieldoffset for
      * banked registers has to be done first.
      */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Since e03b56863d2bc, our host endian indicator is unconditionally
set, which means that we can use a normal C condition.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-20-richard.henderson@linaro.org
[PMM: quote correct git hash in commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
             r2->type |= ARM_CP_ALIAS;
         }
 
-        if (r->state == ARM_CP_STATE_BOTH) {
-#if HOST_BIG_ENDIAN
-            if (r2->fieldoffset) {
-                r2->fieldoffset += sizeof(uint32_t);
-            }
-#endif
+        if (HOST_BIG_ENDIAN &&
+            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
+            r2->fieldoffset += sizeof(uint32_t);
         }
     }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
 }
 
+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
 }
 
+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
+}
+
 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
 }
 
+static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
+}
+
 /*
  * Forward to the above feature tests given an ARMCPU pointer.
  */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Add the aa64 predicate for detecting RAS support from id registers.
We already have the aa32 version from the M-profile work.
Add the 'any' predicate for testing both aa64 and aa32.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

From: Alex Zuepke <alex.zuepke@tum.de>

The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.

Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
-              .accessfn = pmreg_access },
+              .accessfn = pmreg_access_xevcntr },
             { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
-              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
               .type = ARM_CP_IO,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
               .raw_readfn = pmevcntr_rawread,
-- 
2.25.1

Arm queue; not huge but I figured I might as well send it out since
I've been doing code review today and there's no queue of unprocessed
pullreqs...

thanks
-- PMM

The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112

for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:

ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)

----------------------------------------------------------------
target-arm queue:
 * arm: Support emulation of ARMv8.4-TTST extension
 * arm: Update cpu.h ID register field definitions
 * arm: Fix breakage of XScale instruction emulation
 * hw/net/lan9118: Fix RX Status FIFO PEEK value
 * npcm7xx: Add ADC and PWM emulation
 * ui/cocoa: Make "open docs" help menu entry work again when binary
   is run from the build tree
 * ui/cocoa: Fix openFile: deprecation on Big Sur
 * docs: Add qemu-storage-daemon(1) manpage to meson.build
 * docs: Build and install all the docs in a single manual

----------------------------------------------------------------
Hao Wu (6):
      hw/misc: Add clock converter in NPCM7XX CLK module
      hw/timer: Refactor NPCM7XX Timer to use CLK clock
      hw/adc: Add an ADC module for NPCM7XX
      hw/misc: Add a PWM module for NPCM7XX
      hw/misc: Add QTest for NPCM7XX PWM Module
      hw/*: Use type casting for SysBusDevice in NPCM7XX

Leif Lindholm (6):
      target/arm: fix typo in cpu.h ID_AA64PFR1 field name
      target/arm: make ARMCPU.clidr 64-bit
      target/arm: make ARMCPU.ctr 64-bit
      target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
      target/arm: add aarch64 ID register fields to cpu.h
      target/arm: add aarch32 ID register fields to cpu.h

Peter Maydell (5):
      docs: Add qemu-storage-daemon(1) manpage to meson.build
      docs: Build and install all the docs in a single manual
      target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
      hw/net/lan9118: Fix RX Status FIFO PEEK value
      hw/net/lan9118: Add symbolic constants for register offsets

Roman Bolshakov (2):
      ui/cocoa: Update path to docs in build tree
      ui/cocoa: Fix openFile: deprecation on Big Sur

Rémi Denis-Courmont (2):
      target/arm: ARMv8.4-TTST extension
      target/arm: enable Small Translation tables in max CPU

docs/conf.py                     |  46 ++-
 docs/devel/conf.py               |  15 -
 docs/index.html.in               |  17 -
 docs/interop/conf.py             |  28 --
 docs/meson.build                 |  65 ++--
 docs/specs/conf.py               |  16 -
 docs/system/arm/nuvoton.rst      |   4 +-
 docs/system/conf.py              |  28 --
 docs/tools/conf.py               |  37 --
 docs/user/conf.py                |  15 -
 meson.build                      |   1 +
 hw/adc/trace.h                   |   1 +
 include/hw/adc/npcm7xx_adc.h     |  69 ++++
 include/hw/arm/npcm7xx.h         |   4 +
 include/hw/misc/npcm7xx_clk.h    | 146 ++++++-
 include/hw/misc/npcm7xx_pwm.h    | 105 +++++
 include/hw/timer/npcm7xx_timer.h |   1 +
 target/arm/cpu.h                 |  85 ++++-
 hw/adc/npcm7xx_adc.c             | 301 +++++++++++++++
 hw/arm/npcm7xx.c                 |  55 ++-
 hw/arm/npcm7xx_boards.c          |   2 +-
 hw/mem/npcm7xx_mc.c              |   2 +-
 hw/misc/npcm7xx_clk.c            | 807 ++++++++++++++++++++++++++++++++++++++-
 hw/misc/npcm7xx_gcr.c            |   2 +-
 hw/misc/npcm7xx_pwm.c            | 550 ++++++++++++++++++++++++++
 hw/misc/npcm7xx_rng.c            |   2 +-
 hw/net/lan9118.c                 |  26 +-
 hw/nvram/npcm7xx_otp.c           |   2 +-
 hw/ssi/npcm7xx_fiu.c             |   2 +-
 hw/timer/npcm7xx_timer.c         |  39 +-
 target/arm/cpu64.c               |   1 +
 target/arm/helper.c              |  15 +-
 target/arm/translate.c           |   7 +
 tests/qtest/npcm7xx_adc-test.c   | 377 ++++++++++++++++++
 tests/qtest/npcm7xx_pwm-test.c   | 490 ++++++++++++++++++++++++
 hw/adc/meson.build               |   1 +
 hw/adc/trace-events              |   5 +
 hw/misc/meson.build              |   1 +
 hw/misc/trace-events             |   6 +
 tests/qtest/meson.build          |   4 +-
 ui/cocoa.m                       |   7 +-
 41 files changed, 3124 insertions(+), 263 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 include/hw/misc/npcm7xx_pwm.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 hw/misc/npcm7xx_pwm.c
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c
 create mode 100644 hw/adc/trace-events

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

This adds for the Small Translation tables extension in AArch64 state.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  5 +++++
 target/arm/helper.c | 15 +++++++++++++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
 }
 
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
+}
+
 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
 {
     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
     bool epd, hpd, using16k, using64k;
-    int select, tsz, tbi;
+    int select, tsz, tbi, max_tsz;
 
     if (!regime_has_2_ranges(mmu_idx)) {
         select = 0;
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
             hpd = extract64(tcr, 42, 1);
         }
     }
-    tsz = MIN(tsz, 39);  /* TODO: ARMv8.4-TTST */
+
+    if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
+        max_tsz = 48 - using64k;
+    } else {
+        max_tsz = 39;
+    }
+
+    tsz = MIN(tsz, max_tsz);
     tsz = MAX(tsz, 16);  /* TODO: ARMv8.2-LVA  */
 
     /* Present TBI as a composite with TBID.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
         if (!aarch64 || stride == 9) {
             /* AArch32 or 4KB pages */
             startlevel = 2 - sl0;
+
+            if (cpu_isar_feature(aa64_st, cpu)) {
+                startlevel &= 3;
+            }
         } else {
             /* 16KB or 64KB pages */
             startlevel = 3 - sl0;
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-3-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     uint32_t id_afr0;
     uint64_t id_aa64afr0;
     uint64_t id_aa64afr1;
-    uint32_t clidr;
+    uint64_t clidr;
     uint64_t mp_affinity; /* MP ID without feature bits */
     /* The elements of this array are the CCSIDR values for each cache,
      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-5-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
 /*
  * System register ID fields.
  */
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
+FIELD(CLIDR_EL1, LOC, 24, 3)
+FIELD(CLIDR_EL1, LOUU, 27, 3)
+FIELD(CLIDR_EL1, ICB, 30, 3)
+
+/* When FEAT_CCIDX is implemented */
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
+
+/* When FEAT_CCIDX is not implemented */
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
+
+FIELD(CTR_EL0,  IMINLINE, 0, 4)
+FIELD(CTR_EL0,  L1IP, 14, 2)
+FIELD(CTR_EL0,  DMINLINE, 16, 4)
+FIELD(CTR_EL0,  ERG, 20, 4)
+FIELD(CTR_EL0,  CWG, 24, 4)
+FIELD(CTR_EL0,  IDC, 28, 1)
+FIELD(CTR_EL0,  DIC, 29, 1)
+FIELD(CTR_EL0,  TMINLINE, 32, 6)
+
 FIELD(MIDR_EL1, REVISION, 0, 4)
 FIELD(MIDR_EL1, PARTNUM, 4, 12)
 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-6-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
 FIELD(ID_AA64ISAR1, SB, 36, 4)
 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
 
 FIELD(ID_AA64PFR0, EL0, 0, 4)
 FIELD(ID_AA64PFR0, EL1, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SSBS, 4, 4)
 FIELD(ID_AA64PFR1, MTE, 8, 4)
 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
 
 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
 FIELD(ID_AA64MMFR0, EXS, 44, 4)
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
 
 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
 FIELD(ID_AA64MMFR1, PAN, 20, 4)
 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
 FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
 
 FIELD(ID_AA64MMFR2, CNP, 0, 4)
 FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
 
 FIELD(ID_DFR0, COPDBG, 0, 4)
 FIELD(ID_DFR0, COPSDBG, 4, 4)
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-7-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
 FIELD(ID_ISAR6, FHM, 8, 4)
 FIELD(ID_ISAR6, SB, 12, 4)
 FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_ISAR6, BF16, 20, 4)
+FIELD(ID_ISAR6, I8MM, 24, 4)
 
 FIELD(ID_MMFR0, VMSA, 0, 4)
 FIELD(ID_MMFR0, PMSA, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
 FIELD(ID_MMFR0, FCSE, 24, 4)
 FIELD(ID_MMFR0, INNERSHR, 28, 4)
 
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
+FIELD(ID_MMFR1, L1HVD, 16, 4)
+FIELD(ID_MMFR1, L1UNI, 20, 4)
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
+FIELD(ID_MMFR1, BPRED, 28, 4)
+
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
+FIELD(ID_MMFR2, UNITLB, 16, 4)
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
+
 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
 FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
 FIELD(ID_MMFR4, CCIDX, 24, 4)
 FIELD(ID_MMFR4, EVT, 28, 4)
 
+FIELD(ID_MMFR5, ETS, 0, 4)
+
 FIELD(ID_PFR0, STATE0, 0, 4)
 FIELD(ID_PFR0, STATE1, 4, 4)
 FIELD(ID_PFR0, STATE2, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
 FIELD(ID_PFR1, GIC, 28, 4)
 
+FIELD(ID_PFR2, CSV3, 0, 4)
+FIELD(ID_PFR2, SSBS, 4, 4)
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
+
 FIELD(ID_AA64ISAR0, AES, 4, 4)
 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
 FIELD(ID_DFR0, PERFMON, 24, 4)
 FIELD(ID_DFR0, TRACEFILT, 28, 4)
 
+FIELD(ID_DFR1, MTPMU, 0, 4)
+
 FIELD(DBGDIDR, SE_IMP, 12, 1)
 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
 FIELD(DBGDIDR, VERSION, 16, 4)
-- 
2.20.1

From: Roman Bolshakov <r.bolshakov@yadro.com>

QEMU documentation can't be opened if QEMU is run from build tree
because executables are placed in the top of build tree after conversion
to meson.

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 ui/cocoa.m | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ui/cocoa.m b/ui/cocoa.m
index XXXXXXX..XXXXXXX 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
 - (void) openDocumentation: (NSString *) filename
 {
     /* Where to look for local files */
-    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
+    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
     NSString *full_file_path;
 
     /* iterate thru the possible paths until the file is found */
-- 
2.20.1

In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
At the moment new manpages have to be listed both in the conf.py for
Sphinx and also in docs/meson.build for Meson. We forgot the second
of those -- correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
---
 docs/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/meson.build b/docs/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
         'qemu-img.1': (have_tools ? 'man1' : ''),
         'qemu-nbd.8': (have_tools ? 'man8' : ''),
         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
+        'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
-- 
2.20.1

When we first converted our documentation to Sphinx, we split it into
multiple manuals (system, interop, tools, etc), which are all built
separately.  The primary driver for this was wanting to be able to
avoid shipping the 'devel' manual to end-users.  However, this is
working against the grain of the way Sphinx wants to be used and
causes some annoyances:
 * Cross-references between documents become much harder or
   possibly impossible
 * There is no single index to the whole documentation
 * Within one manual there's no links or table-of-contents info
   that lets you easily navigate to the others
 * The devel manual doesn't get published on the QEMU website
   (it would be nice to able to refer to it there)

Merely hiding our developer documentation from end users seems like
it's not enough benefit for these costs.  Combine all the
documentation into a single manual (the same way that the readthedocs
site builds it) and install the whole thing.  The previous manual
divisions remain as the new top level sections in the manual.

* The per-manual conf.py files are no longer needed
 * The man_pages[] specifications previously in each per-manual
   conf.py move to the top level conf.py
 * docs/meson.build logic is simplified as we now only need to run
   Sphinx once for the HTML and then once for the manpages5B
 * The old index.html.in that produced the top-level page with
   links to each manual is no longer needed

Unfortunately this means that we now have to build the HTML
documentation into docs/manual in the build tree rather than directly
into docs/; otherwise it is too awkward to ensure we install only the
built manual and not also the dependency info, stamp file, etc.  The
manual still ends up in the same place in the final installed
directory, but anybody who was consulting documentation from within
the build tree will have to adjust where they're looking.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
---
 docs/conf.py         | 46 ++++++++++++++++++++++++++++++-
 docs/devel/conf.py   | 15 -----------
 docs/index.html.in   | 17 ------------
 docs/interop/conf.py | 28 -------------------
 docs/meson.build     | 64 +++++++++++++++++---------------------------
 docs/specs/conf.py   | 16 -----------
 docs/system/conf.py  | 28 -------------------
 docs/tools/conf.py   | 37 -------------------------
 docs/user/conf.py    | 15 -----------
 9 files changed, 70 insertions(+), 196 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py

diff --git a/docs/conf.py b/docs/conf.py
index XXXXXXX..XXXXXXX 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -XXX,XX +XXX,XX @@ latex_documents = [
 
 # -- Options for manual page output ---------------------------------------
 # Individual manual/conf.py can override this to create man pages
-man_pages = []
+man_pages = [
+    ('interop/qemu-ga', 'qemu-ga',
+     'QEMU Guest Agent',
+     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
+    ('interop/qemu-ga-ref', 'qemu-ga-ref',
+     'QEMU Guest Agent Protocol Reference',
+     [], 7),
+    ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
+     'QEMU QMP Reference Manual',
+     [], 7),
+    ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
+     'QEMU Storage Daemon QMP Reference Manual',
+     [], 7),
+    ('system/qemu-manpage', 'qemu',
+     'QEMU User Documentation',
+     ['Fabrice Bellard'], 1),
+    ('system/qemu-block-drivers', 'qemu-block-drivers',
+     'QEMU block drivers reference',
+     ['Fabrice Bellard and the QEMU Project developers'], 7),
+    ('system/qemu-cpu-models', 'qemu-cpu-models',
+     'QEMU CPU Models',
+     ['The QEMU Project developers'], 7),
+    ('tools/qemu-img', 'qemu-img',
+     'QEMU disk image utility',
+     ['Fabrice Bellard'], 1),
+    ('tools/qemu-nbd', 'qemu-nbd',
+     'QEMU Disk Network Block Device Server',
+     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
+    ('tools/qemu-pr-helper', 'qemu-pr-helper',
+     'QEMU persistent reservation helper',
+     [], 8),
+    ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
+     'QEMU storage daemon',
+     [], 1),
+    ('tools/qemu-trace-stap', 'qemu-trace-stap',
+     'QEMU SystemTap trace tool',
+     [], 1),
+    ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
+     'QEMU 9p virtfs proxy filesystem helper',
+     ['M. Mohan Kumar'], 1),
+    ('tools/virtiofsd', 'virtiofsd',
+     'QEMU virtio-fs shared file system daemon',
+     ['Stefan Hajnoczi <stefanha@redhat.com>',
+      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
+]
 
 # -- Options for Texinfo output -------------------------------------------
 
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/devel/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'devel' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'Developer''s Guide'
diff --git a/docs/index.html.in b/docs/index.html.in
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/index.html.in
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-<!DOCTYPE html>
-<html lang="en">
-    <head>
-        <meta charset="UTF-8">
-        <title>QEMU @VERSION@ Documentation</title>
-    </head>
-    <body>
-        <h1>QEMU @VERSION@ Documentation</h1>
-        <ul>
-            <li><a href="system/index.html">System Emulation User's Guide</a></li>
-            <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
-            <li><a href="tools/index.html">Tools Guide</a></li>
-            <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
-            <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
-        </ul>
-    </body>
-</html>
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/interop/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'interop' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
-     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
-    ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
-     [], 7),
-    ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
-     [], 7),
-    ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
-     'QEMU Storage Daemon QMP Reference Manual', [], 7),
-]
diff --git a/docs/meson.build b/docs/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
                           meson.source_root() / 'docs/sphinx/qmp_lexer.py',
                           qapi_gen_depends ]
 
-  configure_file(output: 'index.html',
-                 input: files('index.html.in'),
-                 configuration: {'VERSION': meson.project_version()},
-                 install_dir: qemu_docdir)
-  manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
   man_pages = {
-    'interop' : {
         'qemu-ga.8': (have_tools ? 'man8' : ''),
         'qemu-ga-ref.7': 'man7',
         'qemu-qmp-ref.7': 'man7',
         'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
-    },
-    'tools': {
         'qemu-img.1': (have_tools ? 'man1' : ''),
         'qemu-nbd.8': (have_tools ? 'man8' : ''),
         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
@@ -XXX,XX +XXX,XX @@ if build_docs
         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
-    },
-    'system': {
         'qemu.1': 'man1',
         'qemu-block-drivers.7': 'man7',
         'qemu-cpu-models.7': 'man7'
-    },
   }
 
   sphinxdocs = []
   sphinxmans = []
-  foreach manual : manuals
-    private_dir = meson.current_build_dir() / (manual + '.p')
-    output_dir = meson.current_build_dir() / manual
-    input_dir = meson.current_source_dir() / manual
 
-    this_manual = custom_target(manual + ' manual',
+  private_dir = meson.current_build_dir() / 'manual.p'
+  output_dir = meson.current_build_dir() / 'manual'
+  input_dir = meson.current_source_dir()
+
+  this_manual = custom_target('QEMU manual',
                 build_by_default: build_docs,
-                output: [manual + '.stamp'],
-                input: [files('conf.py'), files(manual / 'conf.py')],
-                depfile: manual + '.d',
+                output: 'docs.stamp',
+                input: files('conf.py'),
+                depfile: 'docs.d',
                 depend_files: sphinx_extn_depends,
                 command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
                           '-Ddepfile_stamp=@OUTPUT0@',
                           '-b', 'html', '-d', private_dir,
                           input_dir, output_dir])
-    sphinxdocs += this_manual
-    if build_docs and manual != 'devel'
-      install_subdir(output_dir, install_dir: qemu_docdir)
-    endif
+  sphinxdocs += this_manual
+  install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
 
-    these_man_pages = []
-    install_dirs = []
-    foreach page, section : man_pages.get(manual, {})
-      these_man_pages += page
-      install_dirs += section == '' ? false : get_option('mandir') / section
-    endforeach
-    if these_man_pages.length() > 0
-      sphinxmans += custom_target(manual + ' man pages',
-                         build_by_default: build_docs,
-                         output: these_man_pages,
-                         input: this_manual,
-                         install: build_docs,
-                         install_dir: install_dirs,
-                         command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
-                                   input_dir, meson.current_build_dir()])
-    endif
+  these_man_pages = []
+  install_dirs = []
+  foreach page, section : man_pages
+    these_man_pages += page
+    install_dirs += section == '' ? false : get_option('mandir') / section
   endforeach
+
+  sphinxmans += custom_target('QEMU man pages',
+                              build_by_default: build_docs,
+                              output: these_man_pages,
+                              input: this_manual,
+                              install: build_docs,
+                              install_dir: install_dirs,
+                              command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
+                                        input_dir, meson.current_build_dir()])
+
   alias_target('sphinxdocs', sphinxdocs)
   alias_target('html', sphinxdocs)
   alias_target('man', sphinxmans)
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/specs/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'specs' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = \
-    u'System Emulation Guest Hardware Specifications'
diff --git a/docs/system/conf.py b/docs/system/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/system/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'system' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'System Emulation User''s Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-manpage', 'qemu', u'QEMU User Documentation',
-     ['Fabrice Bellard'], 1),
-    ('qemu-block-drivers', 'qemu-block-drivers',
-     u'QEMU block drivers reference',
-     ['Fabrice Bellard and the QEMU Project developers'], 7),
-    ('qemu-cpu-models', 'qemu-cpu-models',
-     u'QEMU CPU Models',
-     ['The QEMU Project developers'], 7)
-]
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/tools/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'tools' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = \
-    u'Tools Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-img', 'qemu-img', u'QEMU disk image utility',
-     ['Fabrice Bellard'], 1),
-    ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
-     [], 1),
-    ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
-     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
-    ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
-     [], 8),
-    ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
-     [], 1),
-    ('virtfs-proxy-helper', 'virtfs-proxy-helper',
-     u'QEMU 9p virtfs proxy filesystem helper',
-     ['M. Mohan Kumar'], 1),
-    ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
-     ['Stefan Hajnoczi <stefanha@redhat.com>',
-      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
-]
diff --git a/docs/user/conf.py b/docs/user/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/user/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'user' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
-- 
2.20.1

In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.

Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.

Cc: qemu-stable@nongnu.org
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
---
 target/arm/translate.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
      * only cp14 and cp15 are valid, and other values aren't considered
      * to be in the coprocessor-instruction space at all. v8M still
      * permits coprocessors 0..7.
+     * For XScale, we must not decode the XScale cp0, cp1 space as
+     * a standard coprocessor insn, because we want to fall through to
+     * the legacy disas_xscale_insn() decoder after decodetree is done.
      */
+    if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
+        return false;
+    }
+
     if (arm_dc_feature(s, ARM_FEATURE_V8) &&
         !arm_dc_feature(s, ARM_FEATURE_M)) {
         return cp >= 14;
-- 
2.20.1

The lan9118 code mostly uses symbolic constants for register offsets;
the exceptions are those which the datasheet doesn't give an official
symbolic name to.

Add some names for the registers which don't already have them, based
on the longer names they are given in the memory map.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
---
 hw/net/lan9118.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
 #endif
 
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
+#define RX_DATA_FIFO_PORT_FIRST 0x00
+#define RX_DATA_FIFO_PORT_LAST 0x1f
+#define TX_DATA_FIFO_PORT_FIRST 0x20
+#define TX_DATA_FIFO_PORT_LAST 0x3f
+
+#define RX_STATUS_FIFO_PORT 0x40
+#define RX_STATUS_FIFO_PEEK 0x44
+#define TX_STATUS_FIFO_PORT 0x48
+#define TX_STATUS_FIFO_PEEK 0x4c
+
 #define CSR_ID_REV      0x50
 #define CSR_IRQ_CFG     0x54
 #define CSR_INT_STS     0x58
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
     offset &= 0xff;
 
     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
-    if (offset >= 0x20 && offset < 0x40) {
+    if (offset >= TX_DATA_FIFO_PORT_FIRST &&
+        offset <= TX_DATA_FIFO_PORT_LAST) {
         /* TX FIFO */
         tx_fifo_push(s, val);
         return;
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
     lan9118_state *s = (lan9118_state *)opaque;
 
     //DPRINTF("Read reg 0x%02x\n", (int)offset);
-    if (offset < 0x20) {
+    if (offset <= RX_DATA_FIFO_PORT_LAST) {
         /* RX FIFO */
         return rx_fifo_pop(s);
     }
     switch (offset) {
-    case 0x40:
+    case RX_STATUS_FIFO_PORT:
         return rx_status_fifo_pop(s);
-    case 0x44:
+    case RX_STATUS_FIFO_PEEK:
         return s->rx_status_fifo[s->rx_status_fifo_head];
-    case 0x48:
+    case TX_STATUS_FIFO_PORT:
         return tx_status_fifo_pop(s);
-    case 0x4c:
+    case TX_STATUS_FIFO_PEEK:
         return s->tx_status_fifo[s->tx_status_fifo_head];
     case CSR_ID_REV:
         return 0x01180001;
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.

Add a new struct NPCM7xxClockConverterState which represents a
single converter.  Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
takes one or more input clocks and converts them into one output clock.
They form a clock hierarchy in the CLK module and are responsible for
outputing clocks for various other modules in an NPCM7XX SoC.

Each converter has a function pointer called "convert" which represents
the unique logic for that converter.

The clock contains two initialization information: ConverterInitInfo and
ConverterConnectionInfo. They represent the vertices and edges in the
clock diagram respectively.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/npcm7xx_clk.h | 140 +++++-
 hw/misc/npcm7xx_clk.c         | 805 +++++++++++++++++++++++++++++++++-
 2 files changed, 932 insertions(+), 13 deletions(-)

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_CLK_H
 
 #include "exec/memory.h"
+#include "hw/clock.h"
 #include "hw/sysbus.h"
 
 /*
@@ -XXX,XX +XXX,XX @@
 
 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
 
-typedef struct NPCM7xxCLKState {
+/* Maximum amount of clock inputs in a SEL module. */
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
+
+/* PLLs in CLK module. */
+typedef enum NPCM7xxClockPLL {
+    NPCM7XX_CLOCK_PLL0,
+    NPCM7XX_CLOCK_PLL1,
+    NPCM7XX_CLOCK_PLL2,
+    NPCM7XX_CLOCK_PLLG,
+    NPCM7XX_CLOCK_NR_PLLS,
+} NPCM7xxClockPLL;
+
+/* SEL/MUX in CLK module. */
+typedef enum NPCM7xxClockSEL {
+    NPCM7XX_CLOCK_PIXCKSEL,
+    NPCM7XX_CLOCK_MCCKSEL,
+    NPCM7XX_CLOCK_CPUCKSEL,
+    NPCM7XX_CLOCK_CLKOUTSEL,
+    NPCM7XX_CLOCK_UARTCKSEL,
+    NPCM7XX_CLOCK_TIMCKSEL,
+    NPCM7XX_CLOCK_SDCKSEL,
+    NPCM7XX_CLOCK_GFXMSEL,
+    NPCM7XX_CLOCK_SUCKSEL,
+    NPCM7XX_CLOCK_NR_SELS,
+} NPCM7xxClockSEL;
+
+/* Dividers in CLK module. */
+typedef enum NPCM7xxClockDivider {
+    NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
+    NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
+    NPCM7XX_CLOCK_MC_DIVIDER,
+    NPCM7XX_CLOCK_AXI_DIVIDER,
+    NPCM7XX_CLOCK_AHB_DIVIDER,
+    NPCM7XX_CLOCK_AHB3_DIVIDER,
+    NPCM7XX_CLOCK_SPI0_DIVIDER,
+    NPCM7XX_CLOCK_SPIX_DIVIDER,
+    NPCM7XX_CLOCK_APB1_DIVIDER,
+    NPCM7XX_CLOCK_APB2_DIVIDER,
+    NPCM7XX_CLOCK_APB3_DIVIDER,
+    NPCM7XX_CLOCK_APB4_DIVIDER,
+    NPCM7XX_CLOCK_APB5_DIVIDER,
+    NPCM7XX_CLOCK_CLKOUT_DIVIDER,
+    NPCM7XX_CLOCK_UART_DIVIDER,
+    NPCM7XX_CLOCK_TIMER_DIVIDER,
+    NPCM7XX_CLOCK_ADC_DIVIDER,
+    NPCM7XX_CLOCK_MMC_DIVIDER,
+    NPCM7XX_CLOCK_SDHC_DIVIDER,
+    NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
+    NPCM7XX_CLOCK_UTMI_DIVIDER,
+    NPCM7XX_CLOCK_NR_DIVIDERS,
+} NPCM7xxClockConverter;
+
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
+
+/**
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @clock_in: The input clock of this module.
+ * @clock_out: The output clock of this module.
+ * @reg: The control registers for this PLL module.
+ */
+typedef struct NPCM7xxClockPLLState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    Clock *clock_in;
+    Clock *clock_out;
+
+    int reg;
+} NPCM7xxClockPLLState;
+
+/**
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @input_size: The size of inputs of this module.
+ * @clock_in: The input clocks of this module.
+ * @clock_out: The output clocks of this module.
+ * @offset: The offset of this module in the control register.
+ * @len: The length of this module in the control register.
+ */
+typedef struct NPCM7xxClockSELState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    uint8_t input_size;
+    Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
+    Clock *clock_out;
+
+    int offset;
+    int len;
+} NPCM7xxClockSELState;
+
+/**
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @clock_in: The input clock of this module.
+ * @clock_out: The output clock of this module.
+ * @divide: The function the divider uses to divide the input.
+ * @reg: The index of the control register that contains the divisor.
+ * @offset: The offset of the divisor in the control register.
+ * @len: The length of the divisor in the control register.
+ * @divisor: The divisor for a constant divisor
+ */
+typedef struct NPCM7xxClockDividerState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    Clock *clock_in;
+    Clock *clock_out;
+
+    uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
+    union {
+        struct {
+            int reg;
+            int offset;
+            int len;
+        };
+        int divisor;
+    };
+} NPCM7xxClockDividerState;
+
+struct NPCM7xxCLKState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
 
+    /* Clock converters */
+    NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
+    NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
+    NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
+
     uint32_t regs[NPCM7XX_CLK_NR_REGS];
 
     /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
     int64_t ref_ns;
-} NPCM7xxCLKState;
+
+    /* The incoming reference clock. */
+    Clock *clkref;
+};
 
 #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
 #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
+#include "hw/qdev-clock.h"
 #include "migration/vmstate.h"
 #include "qemu/error-report.h"
 #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
 #include "trace.h"
 #include "sysemu/watchdog.h"
 
+/*
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
+ * is always 25 MHz.
+ */
+#define NPCM7XX_CLOCK_REF_HZ            (25000000)
+
+/* Register Field Definitions */
+#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
+
 #define PLLCON_LOKI     BIT(31)
 #define PLLCON_LOKS     BIT(30)
 #define PLLCON_PWDEN    BIT(12)
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
+#define PLLCON_INDV(con) extract32((con), 0, 6)
 
 enum NPCM7xxCLKRegisters {
     NPCM7XX_CLK_CLKEN1,
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
     [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
 };
 
-/* Register Field Definitions */
-#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
-
 /* The number of watchdogs that can trigger a reset. */
 #define NPCM7XX_NR_WATCHDOGS    (3)
 
+/* Clock converter functions */
+
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
+        (obj), TYPE_NPCM7XX_CLOCK_PLL)
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
+        (obj), TYPE_NPCM7XX_CLOCK_SEL)
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
+        (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
+
+static void npcm7xx_clk_update_pll(void *opaque)
+{
+    NPCM7xxClockPLLState *s = opaque;
+    uint32_t con = s->clk->regs[s->reg];
+    uint64_t freq;
+
+    /* The PLL is grounded if it is not locked yet. */
+    if (con & PLLCON_LOKI) {
+        freq = clock_get_hz(s->clock_in);
+        freq *= PLLCON_FBDV(con);
+        freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
+    } else {
+        freq = 0;
+    }
+
+    clock_update_hz(s->clock_out, freq);
+}
+
+static void npcm7xx_clk_update_sel(void *opaque)
+{
+    NPCM7xxClockSELState *s = opaque;
+    uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
+            s->len);
+
+    if (index >= s->input_size) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: SEL index: %u out of range\n",
+                      __func__, index);
+        index = 0;
+    }
+    clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
+}
+
+static void npcm7xx_clk_update_divider(void *opaque)
+{
+    NPCM7xxClockDividerState *s = opaque;
+    uint32_t freq;
+
+    freq = s->divide(s);
+    clock_update_hz(s->clock_out, freq);
+}
+
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) / s->divisor;
+}
+
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) /
+            (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
+}
+
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
+{
+    return divide_by_reg_divisor(s) / 2;
+}
+
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) >>
+        extract32(s->clk->regs[s->reg], s->offset, s->len);
+}
+
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
+{
+    switch (reg) {
+    case NPCM7XX_CLK_PLLCON0:
+        return NPCM7XX_CLOCK_PLL0;
+    case NPCM7XX_CLK_PLLCON1:
+        return NPCM7XX_CLOCK_PLL1;
+    case NPCM7XX_CLK_PLLCON2:
+        return NPCM7XX_CLOCK_PLL2;
+    case NPCM7XX_CLK_PLLCONG:
+        return NPCM7XX_CLOCK_PLLG;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        npcm7xx_clk_update_pll(&clk->plls[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        npcm7xx_clk_update_sel(&clk->sels[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        npcm7xx_clk_update_divider(&clk->dividers[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
+{
+    clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
+    npcm7xx_clk_update_all_plls(clk);
+    npcm7xx_clk_update_all_sels(clk);
+    npcm7xx_clk_update_all_dividers(clk);
+}
+
+/* Types of clock sources. */
+typedef enum ClockSrcType {
+    CLKSRC_REF,
+    CLKSRC_PLL,
+    CLKSRC_SEL,
+    CLKSRC_DIV,
+} ClockSrcType;
+
+typedef struct PLLInitInfo {
+    const char *name;
+    ClockSrcType src_type;
+    int src_index;
+    int reg;
+    const char *public_name;
+} PLLInitInfo;
+
+typedef struct SELInitInfo {
+    const char *name;
+    uint8_t input_size;
+    ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
+    int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
+    int offset;
+    int len;
+    const char *public_name;
+} SELInitInfo;
+
+typedef struct DividerInitInfo {
+    const char *name;
+    ClockSrcType src_type;
+    int src_index;
+    uint32_t (*divide)(NPCM7xxClockDividerState *s);
+    int reg; /* not used when type == CONSTANT */
+    int offset; /* not used when type == CONSTANT */
+    int len; /* not used when type == CONSTANT */
+    int divisor; /* used only when type == CONSTANT */
+    const char *public_name;
+} DividerInitInfo;
+
+static const PLLInitInfo pll_init_info_list[] = {
+    [NPCM7XX_CLOCK_PLL0] = {
+        .name = "pll0",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON0,
+    },
+    [NPCM7XX_CLOCK_PLL1] = {
+        .name = "pll1",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON1,
+    },
+    [NPCM7XX_CLOCK_PLL2] = {
+        .name = "pll2",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON2,
+    },
+    [NPCM7XX_CLOCK_PLLG] = {
+        .name = "pllg",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCONG,
+    },
+};
+
+static const SELInitInfo sel_init_info_list[] = {
+    [NPCM7XX_CLOCK_PIXCKSEL] = {
+        .name = "pixcksel",
+        .input_size = 2,
+        .src_type = {CLKSRC_PLL, CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLLG, 0},
+        .offset = 5,
+        .len = 1,
+        .public_name = "pixel-clock",
+    },
+    [NPCM7XX_CLOCK_MCCKSEL] = {
+        .name = "mccksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
+            /*MCBPCK, shouldn't be used in normal operation*/
+            CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
+        .offset = 12,
+        .len = 2,
+        .public_name = "mc-phy-clock",
+    },
+    [NPCM7XX_CLOCK_CPUCKSEL] = {
+        .name = "cpucksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
+            /*SYSBPCK, shouldn't be used in normal operation*/
+            CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
+        .offset = 0,
+        .len = 2,
+        .public_name = "system-clock",
+    },
+    [NPCM7XX_CLOCK_CLKOUTSEL] = {
+        .name = "clkoutsel",
+        .input_size = 5,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
+            CLKSRC_PLL, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
+        .offset = 18,
+        .len = 3,
+        .public_name = "tock",
+    },
+    [NPCM7XX_CLOCK_UARTCKSEL] = {
+        .name = "uartcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 8,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_TIMCKSEL] = {
+        .name = "timcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 14,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_SDCKSEL] = {
+        .name = "sdcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 6,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_GFXMSEL] = {
+        .name = "gfxmksel",
+        .input_size = 2,
+        .src_type = {CLKSRC_REF, CLKSRC_PLL},
+        .src_index = {0, NPCM7XX_CLOCK_PLL2},
+        .offset = 21,
+        .len = 1,
+    },
+    [NPCM7XX_CLOCK_SUCKSEL] = {
+        .name = "sucksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 10,
+        .len = 2,
+    },
+};
+
+static const DividerInitInfo divider_init_info_list[] = {
+    [NPCM7XX_CLOCK_PLL1D2] = {
+        .name = "pll1d2",
+        .src_type = CLKSRC_PLL,
+        .src_index = NPCM7XX_CLOCK_PLL1,
+        .divide = divide_by_constant,
+        .divisor = 2,
+    },
+    [NPCM7XX_CLOCK_PLL2D2] = {
+        .name = "pll2d2",
+        .src_type = CLKSRC_PLL,
+        .src_index = NPCM7XX_CLOCK_PLL2,
+        .divide = divide_by_constant,
+        .divisor = 2,
+    },
+    [NPCM7XX_CLOCK_MC_DIVIDER] = {
+        .name = "mc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_MCCKSEL,
+        .divide = divide_by_constant,
+        .divisor = 2,
+        .public_name = "mc-clock"
+    },
+    [NPCM7XX_CLOCK_AXI_DIVIDER] = {
+        .name = "axi-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_CPUCKSEL,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 0,
+        .len = 1,
+        .public_name = "clk2"
+    },
+    [NPCM7XX_CLOCK_AHB_DIVIDER] = {
+        .name = "ahb-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 26,
+        .len = 2,
+        .public_name = "clk4"
+    },
+    [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
+        .name = "ahb3-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 6,
+        .len = 5,
+        .public_name = "ahb3-spi3-clock"
+    },
+    [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
+        .name = "spi0-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV3,
+        .offset = 6,
+        .len = 5,
+        .public_name = "spi0-clock",
+    },
+    [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
+        .name = "spix-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV3,
+        .offset = 1,
+        .len = 5,
+        .public_name = "spix-clock",
+    },
+    [NPCM7XX_CLOCK_APB1_DIVIDER] = {
+        .name = "apb1-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 24,
+        .len = 2,
+        .public_name = "apb1-clock",
+    },
+    [NPCM7XX_CLOCK_APB2_DIVIDER] = {
+        .name = "apb2-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 26,
+        .len = 2,
+        .public_name = "apb2-clock",
+    },
+    [NPCM7XX_CLOCK_APB3_DIVIDER] = {
+        .name = "apb3-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 28,
+        .len = 2,
+        .public_name = "apb3-clock",
+    },
+    [NPCM7XX_CLOCK_APB4_DIVIDER] = {
+        .name = "apb4-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 30,
+        .len = 2,
+        .public_name = "apb4-clock",
+    },
+    [NPCM7XX_CLOCK_APB5_DIVIDER] = {
+        .name = "apb5-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 22,
+        .len = 2,
+        .public_name = "apb5-clock",
+    },
+    [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
+        .name = "clkout-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 16,
+        .len = 5,
+        .public_name = "clkout",
+    },
+    [NPCM7XX_CLOCK_UART_DIVIDER] = {
+        .name = "uart-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_UARTCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 16,
+        .len = 5,
+        .public_name = "uart-clock",
+    },
+    [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
+        .name = "timer-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_TIMCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 21,
+        .len = 5,
+        .public_name = "timer-clock",
+    },
+    [NPCM7XX_CLOCK_ADC_DIVIDER] = {
+        .name = "adc-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 28,
+        .len = 3,
+        .public_name = "adc-clock",
+    },
+    [NPCM7XX_CLOCK_MMC_DIVIDER] = {
+        .name = "mmc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SDCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 11,
+        .len = 5,
+        .public_name = "mmc-clock",
+    },
+    [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
+        .name = "sdhc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SDCKSEL,
+        .divide = divide_by_reg_divisor_times_2,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 0,
+        .len = 4,
+        .public_name = "sdhc-clock",
+    },
+    [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
+        .name = "gfxm-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_GFXMSEL,
+        .divide = divide_by_constant,
+        .divisor = 3,
+        .public_name = "gfxm-clock",
+    },
+    [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
+        .name = "utmi-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SUCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 8,
+        .len = 5,
+        .public_name = "utmi-clock",
+    },
+};
+
+static void npcm7xx_clk_pll_init(Object *obj)
+{
+    NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
+
+    pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
+            npcm7xx_clk_update_pll, pll);
+    pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
+}
+
+static void npcm7xx_clk_sel_init(Object *obj)
+{
+    int i;
+    NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
+
+    for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
+        sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
+                g_strdup_printf("clock-in[%d]", i),
+                npcm7xx_clk_update_sel, sel);
+    }
+    sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
+}
+static void npcm7xx_clk_divider_init(Object *obj)
+{
+    NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
+
+    div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
+            npcm7xx_clk_update_divider, div);
+    div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
+}
+
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
+        NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
+{
+    pll->name = init_info->name;
+    pll->clk = clk;
+    pll->reg = init_info->reg;
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
+        NPCM7xxCLKState *clk, const SELInitInfo *init_info)
+{
+    int input_size = init_info->input_size;
+
+    sel->name = init_info->name;
+    sel->clk = clk;
+    sel->input_size = init_info->input_size;
+    g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
+    sel->offset = init_info->offset;
+    sel->len = init_info->len;
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
+        NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
+{
+    div->name = init_info->name;
+    div->clk = clk;
+
+    div->divide = init_info->divide;
+    if (div->divide == divide_by_constant) {
+        div->divisor = init_info->divisor;
+    } else {
+        div->reg = init_info->reg;
+        div->offset = init_info->offset;
+        div->len = init_info->len;
+    }
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
+        int index)
+{
+    switch (type) {
+    case CLKSRC_REF:
+        return clk->clkref;
+    case CLKSRC_PLL:
+        return clk->plls[index].clock_out;
+    case CLKSRC_SEL:
+        return clk->sels[index].clock_out;
+    case CLKSRC_DIV:
+        return clk->dividers[index].clock_out;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
+{
+    int i, j;
+    Clock *src;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
+                pll_init_info_list[i].src_index);
+        clock_set_source(clk->plls[i].clock_in, src);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
+            src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
+                    sel_init_info_list[i].src_index[j]);
+            clock_set_source(clk->sels[i].clock_in[j], src);
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
+                divider_init_info_list[i].src_index);
+        clock_set_source(clk->dividers[i].clock_in, src);
+    }
+}
+
 static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
 {
     uint32_t reg = offset / sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
          *
          * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
          */
-        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
+        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
         break;
 
     default:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
                 value |= (value & PLLCON_LOKS);
             }
         }
+        /* Only update PLL when it is locked. */
+        if (value & PLLCON_LOKI) {
+            npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
+        }
+        break;
+
+    case NPCM7XX_CLK_CLKSEL:
+        npcm7xx_clk_update_all_sels(s);
+        break;
+
+    case NPCM7XX_CLK_CLKDIV1:
+    case NPCM7XX_CLK_CLKDIV2:
+    case NPCM7XX_CLK_CLKDIV3:
+        npcm7xx_clk_update_all_dividers(s);
         break;
 
     case NPCM7XX_CLK_CNTR25M:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
     case RESET_TYPE_COLD:
         memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
         s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+        npcm7xx_clk_update_all_clocks(s);
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
                   __func__, type);
 }
 
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
+{
+    int i;
+
+    s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
+
+    /* First pass: init all converter modules */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
+            != NPCM7XX_CLOCK_NR_DIVIDERS);
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
+                &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
+        npcm7xx_init_clock_pll(&s->plls[i], s,
+                &pll_init_info_list[i]);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
+                &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
+        npcm7xx_init_clock_sel(&s->sels[i], s,
+                &sel_init_info_list[i]);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
+                &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
+        npcm7xx_init_clock_divider(&s->dividers[i], s,
+                &divider_init_info_list[i]);
+    }
+
+    /* Second pass: connect converter modules */
+    npcm7xx_connect_clocks(s);
+
+    clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
+}
+
 static void npcm7xx_clk_init(Object *obj)
 {
     NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                           TYPE_NPCM7XX_CLK, 4 * KiB);
     sysbus_init_mmio(&s->parent, &s->iomem);
-    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
-            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
 }
 
-static const VMStateDescription vmstate_npcm7xx_clk = {
-    .name = "npcm7xx-clk",
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
+{
+    if (version_id >= 1) {
+        NPCM7xxCLKState *clk = opaque;
+
+        npcm7xx_clk_update_all_clocks(clk);
+    }
+
+    return 0;
+}
+
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
+{
+    int i;
+    NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
+
+    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
+            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
+    npcm7xx_clk_init_clock_hierarchy(s);
+
+    /* Realize child devices */
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
+            return;
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
+            return;
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
+            return;
+        }
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
+    .name = "npcm7xx-clock-pll",
     .version_id = 0,
     .minimum_version_id = 0,
-    .fields = (VMStateField[]) {
-        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
-        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+    .fields =  (VMStateField[]) {
+        VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
         VMSTATE_END_OF_LIST(),
     },
 };
 
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
+    .name = "npcm7xx-clock-sel",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields =  (VMStateField[]) {
+        VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
+                NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
+    .name = "npcm7xx-clock-divider",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields =  (VMStateField[]) {
+        VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_clk = {
+    .name = "npcm7xx-clk",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .post_load = npcm7xx_clk_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
+        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+        VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock PLL Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_pll;
+}
+
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock SEL Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_sel;
+}
+
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock Divider Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_divider;
+}
+
 static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 {
     ResettableClass *rc = RESETTABLE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 
     dc->desc = "NPCM7xx Clock Control Registers";
     dc->vmsd = &vmstate_npcm7xx_clk;
+    dc->realize = npcm7xx_clk_realize;
     rc->phases.enter = npcm7xx_clk_enter_reset;
 }
 
+static const TypeInfo npcm7xx_clk_pll_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_PLL,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockPLLState),
+    .instance_init      = npcm7xx_clk_pll_init,
+    .class_init         = npcm7xx_clk_pll_class_init,
+};
+
+static const TypeInfo npcm7xx_clk_sel_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_SEL,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockSELState),
+    .instance_init      = npcm7xx_clk_sel_init,
+    .class_init         = npcm7xx_clk_sel_class_init,
+};
+
+static const TypeInfo npcm7xx_clk_divider_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_DIVIDER,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockDividerState),
+    .instance_init      = npcm7xx_clk_divider_init,
+    .class_init         = npcm7xx_clk_divider_class_init,
+};
+
 static const TypeInfo npcm7xx_clk_info = {
     .name               = TYPE_NPCM7XX_CLK,
     .parent             = TYPE_SYS_BUS_DEVICE,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
 
 static void npcm7xx_clk_register_type(void)
 {
+    type_register_static(&npcm7xx_clk_pll_info);
+    type_register_static(&npcm7xx_clk_sel_info);
+    type_register_static(&npcm7xx_clk_divider_info);
     type_register_static(&npcm7xx_clk_info);
 }
 type_init(npcm7xx_clk_register_type);
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/clock.h"
 #include "hw/sysbus.h"
 
-/*
- * The reference clock frequency for the timer modules, and the SECCNT and
- * CNTR25M registers in this module, is always 25 MHz.
- */
-#define NPCM7XX_TIMER_REF_HZ            (25000000)
-
 /*
  * Number of registers in our device state structure. Don't change this without
  * incrementing the version_id in the vmstate.
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/npcm7xx_timer.h
+++ b/include/hw/timer/npcm7xx_timer.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
 
     uint32_t    tisr;
 
+    Clock       *clock;
     NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
     NPCM7xxWatchdogTimer watchdog_timer;
 };
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 #include "hw/loader.h"
 #include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
 #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
         int first_irq;
         int j;
 
+        /* Connect the timer clock. */
+        qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
+                    DEVICE(&s->clk), "timer-clock"));
+
         sysbus_realize(sbd, &error_abort);
         sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/npcm7xx_timer.c
+++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 
 #include "hw/irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
-#include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "migration/vmstate.h"
 #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
 /* Convert a timer cycle count to a time interval in nanoseconds. */
 static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
 {
-    int64_t ns = count;
+    int64_t ticks = count;
 
-    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
-    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
+    ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
 
-    return ns;
+    return clock_ticks_to_ns(t->ctrl->clock, ticks);
 }
 
 /* Convert a time interval in nanoseconds to a timer cycle count. */
 static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
 {
-    int64_t count;
-
-    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
-    count /= npcm7xx_tcsr_prescaler(t->tcsr);
-
-    return count;
+    return ns / clock_ticks_to_ns(t->ctrl->clock,
+                                  npcm7xx_tcsr_prescaler(t->tcsr));
 }
 
 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
 static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
         int64_t cycles)
 {
-    uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
-    int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
+    int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
+    int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
 
     /*
      * The reset function always clears the current timer. The caller of the
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
      */
     npcm7xx_timer_clear(&t->base_timer);
 
-    ns *= prescaler;
     t->base_timer.remaining_ns = ns;
 }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
     qemu_irq_lower(s->watchdog_timer.irq);
 }
 
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
+static void npcm7xx_timer_init(Object *obj)
 {
-    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
-    SysBusDevice *sbd = &s->parent;
+    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
+    DeviceState *dev = DEVICE(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     int i;
     NPCM7xxWatchdogTimer *w;
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
             npcm7xx_watchdog_timer_expired, w);
     sysbus_init_irq(sbd, &w->irq);
 
-    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
                           TYPE_NPCM7XX_TIMER, 4 * KiB);
     sysbus_init_mmio(sbd, &s->iomem);
     qdev_init_gpio_out_named(dev, &w->reset_signal,
             NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
+    s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
 }
 
 static const VMStateDescription vmstate_npcm7xx_base_timer = {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
 
 static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
     .name = "npcm7xx-timer-ctrl",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
+        VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
         VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
                              NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
                              NPCM7xxTimer),
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
     QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
 
     dc->desc = "NPCM7xx Timer Controller";
-    dc->realize = npcm7xx_timer_realize;
     dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
     rc->phases.enter = npcm7xx_timer_enter_reset;
     rc->phases.hold = npcm7xx_timer_hold_reset;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
     .parent             = TYPE_SYS_BUS_DEVICE,
     .instance_size      = sizeof(NPCM7xxTimerCtrlState),
     .class_init         = npcm7xx_timer_class_init,
+    .instance_init      = npcm7xx_timer_init,
 };
 
 static void npcm7xx_timer_register_type(void)
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.

Users can alter input value by using qom-set QMP command.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
[PMM: Added missing hw/adc/trace.h file]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst    |   2 +-
 meson.build                    |   1 +
 hw/adc/trace.h                 |   1 +
 include/hw/adc/npcm7xx_adc.h   |  69 ++++++
 include/hw/arm/npcm7xx.h       |   2 +
 hw/adc/npcm7xx_adc.c           | 301 ++++++++++++++++++++++++++
 hw/arm/npcm7xx.c               |  24 ++-
 tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
 hw/adc/meson.build             |   1 +
 hw/adc/trace-events            |   5 +
 tests/qtest/meson.build        |   3 +-
 11 files changed, 783 insertions(+), 3 deletions(-)
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 hw/adc/trace-events

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * Random Number Generator (RNG)
  * USB host (USBH)
  * GPIO controller
+ * Analog to Digital Converter (ADC)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
  * USB device (USBD)
  * SMBus controller (SMBF)
  * Peripheral SPI controller (PSPI)
- * Analog to Digital Converter (ADC)
  * SD/MMC host
  * PECI interface
  * Pulse Width Modulation (PWM)
diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
     'chardev',
     'hw/9pfs',
     'hw/acpi',
+    'hw/adc',
     'hw/alpha',
     'hw/arm',
     'hw/audio',
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_adc.h"
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/adc/npcm7xx_adc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_ADC_H
+#define NPCM7XX_ADC_H
+
+#include "hw/clock.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+#define NPCM7XX_ADC_NUM_INPUTS      8
+/**
+ * This value should not be changed unless write_adc_calibration function in
+ * hw/arm/npcm7xx.c is also changed.
+ */
+#define NPCM7XX_ADC_NUM_CALIB       2
+
+/**
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * @con: The Control Register.
+ * @data: The Data Buffer.
+ * @clock: The ADC Clock.
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
+ * @vref: The external reference voltage.
+ * @iref: The internal reference voltage, initialized at launch time.
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
+ */
+typedef struct {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    QEMUTimer    conv_timer;
+
+    qemu_irq     irq;
+    uint32_t     con;
+    uint32_t     data;
+    Clock       *clock;
+
+    /* Voltages are in unit of uV. 1V = 1000000uV. */
+    uint32_t     adci[NPCM7XX_ADC_NUM_INPUTS];
+    uint32_t     vref;
+    uint32_t     iref;
+
+    uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
+} NPCM7xxADCState;
+
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
+#define NPCM7XX_ADC(obj) \
+    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
+
+#endif /* NPCM7XX_ADC_H */
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_H
 
 #include "hw/boards.h"
+#include "hw/adc/npcm7xx_adc.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/gpio/npcm7xx_gpio.h"
 #include "hw/mem/npcm7xx_mc.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxGCRState     gcr;
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
+    NPCM7xxADCState     adc;
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/npcm7xx_adc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/adc/npcm7xx_adc.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+REG32(NPCM7XX_ADC_CON, 0x0)
+REG32(NPCM7XX_ADC_DATA, 0x4)
+
+/* Register field definitions. */
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
+#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
+#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
+#define NPCM7XX_ADC_CON_INT     BIT(18)
+#define NPCM7XX_ADC_CON_EN      BIT(17)
+#define NPCM7XX_ADC_CON_RST     BIT(16)
+#define NPCM7XX_ADC_CON_CONV    BIT(14)
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
+
+#define NPCM7XX_ADC_MAX_RESULT      1023
+#define NPCM7XX_ADC_DEFAULT_IREF    2000000
+#define NPCM7XX_ADC_CONV_CYCLES     20
+#define NPCM7XX_ADC_RESET_CYCLES    10
+#define NPCM7XX_ADC_R0_INPUT        500000
+#define NPCM7XX_ADC_R1_INPUT        1500000
+
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
+{
+    timer_del(&s->conv_timer);
+    s->con = 0x000c0001;
+    s->data = 0x00000000;
+}
+
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
+{
+    uint32_t result;
+
+    result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
+    if (result > NPCM7XX_ADC_MAX_RESULT) {
+        result = NPCM7XX_ADC_MAX_RESULT;
+    }
+
+    return result;
+}
+
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
+{
+    return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
+}
+
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
+        uint32_t cycles, uint32_t prescaler)
+{
+    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    int64_t ticks = cycles;
+    int64_t ns;
+
+    ticks *= prescaler;
+    ns = clock_ticks_to_ns(clk, ticks);
+    ns += now;
+    timer_mod(timer, ns);
+}
+
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
+{
+    uint32_t prescaler = npcm7xx_adc_prescaler(s);
+
+    npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
+            prescaler);
+}
+
+static void npcm7xx_adc_convert_done(void *opaque)
+{
+    NPCM7xxADCState *s = opaque;
+    uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
+    uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
+        ? s->iref : s->vref;
+
+    if (input >= NPCM7XX_ADC_NUM_INPUTS) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
+                      __func__, input);
+        return;
+    }
+    s->data = npcm7xx_adc_convert(s->adci[input], ref);
+    if (s->con & NPCM7XX_ADC_CON_INT_EN) {
+        s->con |= NPCM7XX_ADC_CON_INT;
+        qemu_irq_raise(s->irq);
+    }
+    s->con &= ~NPCM7XX_ADC_CON_CONV;
+}
+
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
+{
+    adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
+            adc->iref);
+    adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
+            adc->iref);
+}
+
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
+{
+    uint32_t old_con = s->con;
+
+    /* Write ADC_INT to 1 to clear it */
+    if (new_con & NPCM7XX_ADC_CON_INT) {
+        new_con &= ~NPCM7XX_ADC_CON_INT;
+        qemu_irq_lower(s->irq);
+    } else if (old_con & NPCM7XX_ADC_CON_INT) {
+        new_con |= NPCM7XX_ADC_CON_INT;
+    }
+
+    s->con = new_con;
+
+    if (s->con & NPCM7XX_ADC_CON_RST) {
+        npcm7xx_adc_reset(s);
+        return;
+    }
+
+    if ((s->con & NPCM7XX_ADC_CON_EN)) {
+        if (s->con & NPCM7XX_ADC_CON_CONV) {
+            if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
+                npcm7xx_adc_start_convert(s);
+            }
+        } else {
+            timer_del(&s->conv_timer);
+        }
+    }
+}
+
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
+{
+    uint64_t value = 0;
+    NPCM7xxADCState *s = opaque;
+
+    switch (offset) {
+    case A_NPCM7XX_ADC_CON:
+        value = s->con;
+        break;
+
+    case A_NPCM7XX_ADC_DATA:
+        value = s->data;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
+    return value;
+}
+
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
+        unsigned size)
+{
+    NPCM7xxADCState *s = opaque;
+
+    trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
+    switch (offset) {
+    case A_NPCM7XX_ADC_CON:
+        npcm7xx_adc_write_con(s, v);
+        break;
+
+    case A_NPCM7XX_ADC_DATA:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+}
+
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
+    .read       = npcm7xx_adc_read,
+    .write      = npcm7xx_adc_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+
+    npcm7xx_adc_reset(s);
+}
+
+static void npcm7xx_adc_hold_reset(Object *obj)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+
+    qemu_irq_lower(s->irq);
+}
+
+static void npcm7xx_adc_init(Object *obj)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    sysbus_init_irq(sbd, &s->irq);
+
+    timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
+            npcm7xx_adc_convert_done, s);
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
+                          TYPE_NPCM7XX_ADC, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
+
+    for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
+        object_property_add_uint32_ptr(obj, "adci[*]",
+                &s->adci[i], OBJ_PROP_FLAG_WRITE);
+    }
+    object_property_add_uint32_ptr(obj, "vref",
+            &s->vref, OBJ_PROP_FLAG_WRITE);
+    npcm7xx_adc_calibrate(s);
+}
+
+static const VMStateDescription vmstate_npcm7xx_adc = {
+    .name = "npcm7xx-adc",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
+        VMSTATE_UINT32(con, NPCM7xxADCState),
+        VMSTATE_UINT32(data, NPCM7xxADCState),
+        VMSTATE_CLOCK(clock, NPCM7xxADCState),
+        VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
+        VMSTATE_UINT32(vref, NPCM7xxADCState),
+        VMSTATE_UINT32(iref, NPCM7xxADCState),
+        VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
+                NPCM7XX_ADC_NUM_CALIB),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static Property npcm7xx_timer_properties[] = {
+    DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx ADC Module";
+    dc->vmsd = &vmstate_npcm7xx_adc;
+    rc->phases.enter = npcm7xx_adc_enter_reset;
+    rc->phases.hold = npcm7xx_adc_hold_reset;
+
+    device_class_set_props(dc, npcm7xx_timer_properties);
+}
+
+static const TypeInfo npcm7xx_adc_info = {
+    .name               = TYPE_NPCM7XX_ADC,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxADCState),
+    .class_init         = npcm7xx_adc_class_init,
+    .instance_init      = npcm7xx_adc_init,
+};
+
+static void npcm7xx_adc_register_types(void)
+{
+    type_register_static(&npcm7xx_adc_info);
+}
+
+type_init(npcm7xx_adc_register_types);
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_EHCI_BA         (0xf0806000)
 #define NPCM7XX_OHCI_BA         (0xf0807000)
 
+/* ADC Module */
+#define NPCM7XX_ADC_BA          (0xf000c000)
+
 /* Internal AHB SRAM */
 #define NPCM7XX_RAM3_BA         (0xc0008000)
 #define NPCM7XX_RAM3_SZ         (4 * KiB)
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_ROM_BA          (0xffff0000)
 #define NPCM7XX_ROM_SZ          (64 * KiB)
 
+
 /* Clock configuration values to be fixed up when bypassing bootloader */
 
 /* Run PLL1 at 1600 MHz */
@@ -XXX,XX +XXX,XX @@
  * interrupts.
  */
 enum NPCM7xxInterrupt {
+    NPCM7XX_ADC_IRQ             = 0,
     NPCM7XX_UART0_IRQ           = 2,
     NPCM7XX_UART1_IRQ,
     NPCM7XX_UART2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
                             sizeof(value));
 }
 
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
+{
+    /* Both ADC and the fuse array must have realized. */
+    QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
+    npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
+            NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
+}
+
 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
 {
     return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
                             TYPE_NPCM7XX_FUSE_ARRAY);
     object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
     object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
+    object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
 
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
         object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 
+    /* ADC Modules. Cannot fail. */
+    qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
+                          DEVICE(&s->clk), "adc-clock"));
+    sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
+            npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
+    npcm7xx_write_adc_calibration(s);
+
     /* Timer Modules (TIM). Cannot fail. */
     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
     create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/npcm7xx_adc-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for Nuvoton NPCM7xx ADCModules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/timer.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+
+#define REF_HZ          (25000000)
+
+#define CON_OFFSET      0x0
+#define DATA_OFFSET     0x4
+
+#define NUM_INPUTS      8
+#define DEFAULT_IREF    2000000
+#define CONV_CYCLES     20
+#define RESET_CYCLES    10
+#define R0_INPUT        500000
+#define R1_INPUT        1500000
+#define MAX_RESULT      1023
+
+#define DEFAULT_CLKDIV  5
+
+#define FUSE_ARRAY_BA   0xf018a000
+#define FCTL_OFFSET     0x14
+#define FST_OFFSET      0x0
+#define FADDR_OFFSET    0x4
+#define FDATA_OFFSET    0x8
+#define ADC_CALIB_ADDR  24
+#define FUSE_READ       0x2
+
+/* Register field definitions. */
+#define CON_MUX(rv) ((rv) << 24)
+#define CON_INT_EN  BIT(21)
+#define CON_REFSEL  BIT(19)
+#define CON_INT     BIT(18)
+#define CON_EN      BIT(17)
+#define CON_RST     BIT(16)
+#define CON_CONV    BIT(14)
+#define CON_DIV(rv) extract32(rv, 1, 8)
+
+#define FST_RDST    BIT(1)
+#define FDATA_MASK  0xff
+
+#define MAX_ERROR   10000
+#define MIN_CALIB_INPUT 100000
+#define MAX_CALIB_INPUT 1800000
+
+static const uint32_t input_list[] = {
+    100000,
+    500000,
+    1000000,
+    1500000,
+    1800000,
+    2000000,
+};
+
+static const uint32_t vref_list[] = {
+    2000000,
+    2200000,
+    2500000,
+};
+
+static const uint32_t iref_list[] = {
+    1800000,
+    1900000,
+    2000000,
+    2100000,
+    2200000,
+};
+
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
+
+typedef struct ADC {
+    int irq;
+    uint64_t base_addr;
+} ADC;
+
+ADC adc = {
+    .irq        = 0,
+    .base_addr  = 0xf000c000
+};
+
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
+{
+    return qtest_readl(qts, adc->base_addr + CON_OFFSET);
+}
+
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
+{
+    qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
+}
+
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
+{
+    return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
+}
+
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
+{
+    return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
+        / (int32_t)(rv[1] - rv[0]);
+}
+
+static void adc_qom_set(QTestState *qts, const ADC *adc,
+        const char *name, uint32_t value)
+{
+    QDict *response;
+    const char *path = "/machine/soc/adc";
+
+    g_test_message("Setting properties %s of %s with value %u",
+            name, path, value);
+    response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
+            " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
+            path, name, value);
+    /* The qom set message returns successfully. */
+    g_assert_true(qdict_haskey(response, "return"));
+}
+
+static void adc_write_input(QTestState *qts, const ADC *adc,
+        uint32_t index, uint32_t value)
+{
+    char name[100];
+
+    sprintf(name, "adci[%u]", index);
+    adc_qom_set(qts, adc, name, value);
+}
+
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
+{
+    adc_qom_set(qts, adc, "vref", value);
+}
+
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
+{
+    uint32_t output;
+
+    g_assert_cmpuint(input, <=, ref);
+    output = (input * (MAX_RESULT + 1)) / ref;
+    if (output > MAX_RESULT) {
+        output = MAX_RESULT;
+    }
+
+    return output;
+}
+
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
+{
+    uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
+
+    return 2 * (div + 1);
+}
+
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
+        uint32_t clkdiv)
+{
+    return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
+}
+
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
+        uint32_t clkdiv)
+{
+    uint32_t prescaler = adc_prescaler(qts, adc);
+
+    /*
+     * ADC should takes roughly 20 cycles to convert one sample. So we assert it
+     * should take 10~30 cycles here.
+     */
+    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
+                clkdiv));
+    /* ADC is still converting. */
+    g_assert_true(adc_read_con(qts, adc) & CON_CONV);
+    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
+    /* ADC has finished conversion. */
+    g_assert_false(adc_read_con(qts, adc) & CON_CONV);
+}
+
+/* Check ADC can be reset to default value. */
+static void test_init(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    adc_write_con(qts, adc, CON_REFSEL | CON_INT);
+    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
+    qtest_quit(qts);
+}
+
+/* Check ADC can convert from an internal reference. */
+static void test_convert_internal(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+    for (index = 0; index < NUM_INPUTS; ++index) {
+        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            input = input_list[i];
+            expected_output = adc_calculate_output(input, DEFAULT_IREF);
+
+            adc_write_input(qts, adc, index, input);
+            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
+                    CON_EN | CON_CONV);
+            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+            g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
+                    CON_REFSEL | CON_EN);
+            g_assert_false(qtest_get_irq(qts, adc->irq));
+            output = adc_read_data(qts, adc);
+            g_assert_cmpuint(output, ==, expected_output);
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* Check ADC can convert from an external reference. */
+static void test_convert_external(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, vref, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+    for (index = 0; index < NUM_INPUTS; ++index) {
+        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
+                input = input_list[i];
+                vref = vref_list[j];
+                expected_output = adc_calculate_output(input, vref);
+
+                adc_write_input(qts, adc, index, input);
+                adc_write_vref(qts, adc, vref);
+                adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
+                        CON_CONV);
+                adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+                g_assert_cmphex(adc_read_con(qts, adc), ==,
+                        CON_MUX(index) | CON_EN);
+                g_assert_false(qtest_get_irq(qts, adc->irq));
+                output = adc_read_data(qts, adc);
+                g_assert_cmpuint(output, ==, expected_output);
+            }
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
+static void test_interrupt(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+
+    index = 1;
+    input = input_list[1];
+    expected_output = adc_calculate_output(input, DEFAULT_IREF);
+
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+    adc_write_input(qts, adc, index, input);
+    g_assert_false(qtest_get_irq(qts, adc->irq));
+    adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
+            | CON_EN | CON_CONV);
+    adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
+            | CON_REFSEL | CON_INT | CON_EN);
+    g_assert_true(qtest_get_irq(qts, adc->irq));
+    output = adc_read_data(qts, adc);
+    g_assert_cmpuint(output, ==, expected_output);
+
+    qtest_quit(qts);
+}
+
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
+static void test_reset(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+
+    for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
+        uint32_t div = div_list[i];
+
+        adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
+        qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
+                    adc_prescaler(qts, adc), DEFAULT_CLKDIV));
+        g_assert_false(adc_read_con(qts, adc) & CON_EN);
+    }
+    qtest_quit(qts);
+}
+
+/* Check ADC Calibration works as desired. */
+static void test_calibrate(gconstpointer adc_p)
+{
+    int i, j;
+    const ADC *adc = adc_p;
+
+    for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
+        uint32_t iref = iref_list[j];
+        uint32_t expected_rv[] = {
+            adc_calculate_output(R0_INPUT, iref),
+            adc_calculate_output(R1_INPUT, iref),
+        };
+        char buf[100];
+        QTestState *qts;
+
+        sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
+        qts = qtest_init(buf);
+
+        /* Check the converted value is correct using the calibration value. */
+        for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            uint32_t input;
+            uint32_t output;
+            uint32_t expected_output;
+            uint32_t calibrated_voltage;
+            uint32_t index = 0;
+
+            input = input_list[i];
+            /* Calibration only works for input range 0.1V ~ 1.8V. */
+            if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
+                continue;
+            }
+            expected_output = adc_calculate_output(input, iref);
+
+            adc_write_input(qts, adc, index, input);
+            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
+                    CON_EN | CON_CONV);
+            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+            g_assert_cmphex(adc_read_con(qts, adc), ==,
+                    CON_REFSEL | CON_MUX(index) | CON_EN);
+            output = adc_read_data(qts, adc);
+            g_assert_cmpuint(output, ==, expected_output);
+
+            calibrated_voltage = adc_calibrate(output, expected_rv);
+            g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
+            g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
+        }
+
+        qtest_quit(qts);
+    }
+}
+
+static void adc_add_test(const char *name, const ADC* wd,
+        GTestDataFunc fn)
+{
+    g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s",  name);
+    qtest_add_data_func(full_name, wd, fn);
+}
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    add_test(init, &adc);
+    add_test(convert_internal, &adc);
+    add_test(convert_external, &adc);
+    add_test(interrupt, &adc);
+    add_test(reset, &adc);
+    add_test(calibrate, &adc);
+
+    return g_test_run();
+}
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/adc/meson.build
+++ b/hw/adc/meson.build
@@ -1 +1,2 @@
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/trace-events
@@ -XXX,XX +XXX,XX @@
+# See docs/devel/tracing.txt for syntax documentation.
+
+# npcm7xx_adc.c
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
   ['prom-env-test', 'boot-serial-test']
 
 qtests_npcm7xx = \
-  ['npcm7xx_gpio-test',
+  ['npcm7xx_adc-test',
+   'npcm7xx_gpio-test',
    'npcm7xx_rng-test',
    'npcm7xx_timer-test',
    'npcm7xx_watchdog_timer-test']
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.

This module does not model detail pulse signals since it is expensive.
It also does not model interrupts and watchdogs that are dependant on
the detail models. The interfaces for these are left in the module so
that anyone in need for these functionalities can implement on their
own.

The user can read the duty cycle and frequency using qom-get command.

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * USB host (USBH)
  * GPIO controller
  * Analog to Digital Converter (ADC)
+ * Pulse Width Modulation (PWM)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
  * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
- * Pulse Width Modulation (PWM)
  * Tachometer
  * PCI and PCIe root complex and bridges
  * VDM and MCTP support
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/mem/npcm7xx_mc.h"
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/misc/npcm7xx_gcr.h"
+#include "hw/misc/npcm7xx_pwm.h"
 #include "hw/misc/npcm7xx_rng.h"
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
     NPCM7xxADCState     adc;
+    NPCM7xxPWMState     pwm[2];
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/npcm7xx_pwm.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx PWM Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_PWM_H
+#define NPCM7XX_PWM_H
+
+#include "hw/clock.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+
+/* Each PWM module holds 4 PWM channels. */
+#define NPCM7XX_PWM_PER_MODULE 4
+
+/*
+ * Number of registers in one pwm module. Don't change this without increasing
+ * the version_id in vmstate.
+ */
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
+
+/*
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
+ * value of 100,000 the duty cycle for that PWM is 10%.
+ */
+#define NPCM7XX_PWM_MAX_DUTY 1000000
+
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
+
+/**
+ * struct NPCM7xxPWM - The state of a single PWM channel.
+ * @module: The PWM module that contains this channel.
+ * @irq: GIC interrupt line to fire on expiration if enabled.
+ * @running: Whether this PWM channel is generating output.
+ * @inverted: Whether this PWM channel is inverted.
+ * @index: The index of this PWM channel.
+ * @cnr: The counter register.
+ * @cmr: The comparator register.
+ * @pdr: The data register.
+ * @pwdr: The watchdog register.
+ * @freq: The frequency of this PWM channel.
+ * @duty: The duty cycle of this PWM channel. One unit represents
+ *   1/NPCM7XX_MAX_DUTY cycles.
+ */
+typedef struct NPCM7xxPWM {
+    NPCM7xxPWMState         *module;
+
+    qemu_irq                irq;
+
+    bool                    running;
+    bool                    inverted;
+
+    uint8_t                 index;
+    uint32_t                cnr;
+    uint32_t                cmr;
+    uint32_t                pdr;
+    uint32_t                pwdr;
+
+    uint32_t                freq;
+    uint32_t                duty;
+} NPCM7xxPWM;
+
+/**
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @clock: The PWM clock.
+ * @pwm: The PWM channels owned by this module.
+ * @ppr: The prescaler register.
+ * @csr: The clock selector register.
+ * @pcr: The control register.
+ * @pier: The interrupt enable register.
+ * @piir: The interrupt indication register.
+ */
+struct NPCM7xxPWMState {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    Clock       *clock;
+    NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
+
+    uint32_t    ppr;
+    uint32_t    csr;
+    uint32_t    pcr;
+    uint32_t    pier;
+    uint32_t    piir;
+};
+
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
+#define NPCM7XX_PWM(obj) \
+    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
+
+#endif /* NPCM7XX_PWM_H */
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
     NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
     NPCM7XX_EHCI_IRQ            = 61,
     NPCM7XX_OHCI_IRQ            = 62,
+    NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
+    NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
     NPCM7XX_GPIO0_IRQ           = 116,
     NPCM7XX_GPIO1_IRQ,
     NPCM7XX_GPIO2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
     0xb8000000, /* CS3 */
 };
 
+/* Register base address for each PWM Module */
+static const hwaddr npcm7xx_pwm_addr[] = {
+    0xf0103000,
+    0xf0104000,
+};
+
 static const struct {
     hwaddr regs_addr;
     uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
         object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
                                 TYPE_NPCM7XX_FIU);
     }
+
+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+        object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
+    }
 }
 
 static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
                        npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 
+    /* PWM Modules. Cannot fail. */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
+
+        qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
+                    DEVICE(&s->clk), "apb3-clock"));
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
+        sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
+    }
+
     /*
      * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
      * specified, but this is a programming error.
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/npcm7xx_pwm.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx PWM Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/npcm7xx_pwm.h"
+#include "hw/registerfields.h"
+#include "migration/vmstate.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+REG32(NPCM7XX_PWM_PPR, 0x00);
+REG32(NPCM7XX_PWM_CSR, 0x04);
+REG32(NPCM7XX_PWM_PCR, 0x08);
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
+REG32(NPCM7XX_PWM_CMR0, 0x10);
+REG32(NPCM7XX_PWM_PDR0, 0x14);
+REG32(NPCM7XX_PWM_CNR1, 0x18);
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
+REG32(NPCM7XX_PWM_PDR1, 0x20);
+REG32(NPCM7XX_PWM_CNR2, 0x24);
+REG32(NPCM7XX_PWM_CMR2, 0x28);
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
+REG32(NPCM7XX_PWM_CNR3, 0x30);
+REG32(NPCM7XX_PWM_CMR3, 0x34);
+REG32(NPCM7XX_PWM_PDR3, 0x38);
+REG32(NPCM7XX_PWM_PIER, 0x3c);
+REG32(NPCM7XX_PWM_PIIR, 0x40);
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
+
+/* Register field definitions. */
+#define NPCM7XX_PPR(rv, index)      extract32((rv), npcm7xx_ppr_base[index], 8)
+#define NPCM7XX_CSR(rv, index)      extract32((rv), npcm7xx_csr_base[index], 3)
+#define NPCM7XX_CH(rv, index)       extract32((rv), npcm7xx_ch_base[index], 4)
+#define NPCM7XX_CH_EN               BIT(0)
+#define NPCM7XX_CH_INV              BIT(2)
+#define NPCM7XX_CH_MOD              BIT(3)
+
+/* Offset of each PWM channel's prescaler in the PPR register. */
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
+/* Offset of each PWM channel's clock selector in the CSR register. */
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
+/* Offset of each PWM channel's control variable in the PCR register. */
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
+
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
+{
+    uint32_t ppr;
+    uint32_t csr;
+    uint32_t freq;
+
+    if (!p->running) {
+        return 0;
+    }
+
+    csr = NPCM7XX_CSR(p->module->csr, p->index);
+    ppr = NPCM7XX_PPR(p->module->ppr, p->index);
+    freq = clock_get_hz(p->module->clock);
+    freq /= ppr + 1;
+    /* csr can only be 0~4 */
+    if (csr > 4) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid csr value %u\n",
+                      __func__, csr);
+        csr = 4;
+    }
+    /* freq won't be changed if csr == 4. */
+    if (csr < 4) {
+        freq >>= csr + 1;
+    }
+
+    return freq / (p->cnr + 1);
+}
+
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
+{
+    uint64_t duty;
+
+    if (p->running) {
+        if (p->cnr == 0) {
+            duty = 0;
+        } else if (p->cmr >= p->cnr) {
+            duty = NPCM7XX_PWM_MAX_DUTY;
+        } else {
+            duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
+        }
+    } else {
+        duty = 0;
+    }
+
+    if (p->inverted) {
+        duty = NPCM7XX_PWM_MAX_DUTY - duty;
+    }
+
+    return duty;
+}
+
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
+{
+    uint32_t freq = npcm7xx_pwm_calculate_freq(p);
+
+    if (freq != p->freq) {
+        trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
+                                      p->index, p->freq, freq);
+        p->freq = freq;
+    }
+}
+
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
+{
+    uint32_t duty = npcm7xx_pwm_calculate_duty(p);
+
+    if (duty != p->duty) {
+        trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
+                                      p->index, p->duty, duty);
+        p->duty = duty;
+    }
+}
+
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
+{
+    npcm7xx_pwm_update_freq(p);
+    npcm7xx_pwm_update_duty(p);
+}
+
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
+{
+    int i;
+    uint32_t old_ppr = s->ppr;
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
+    s->ppr = new_ppr;
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
+            npcm7xx_pwm_update_freq(&s->pwm[i]);
+        }
+    }
+}
+
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
+{
+    int i;
+    uint32_t old_csr = s->csr;
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
+    s->csr = new_csr;
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
+            npcm7xx_pwm_update_freq(&s->pwm[i]);
+        }
+    }
+}
+
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
+{
+    int i;
+    bool inverted;
+    uint32_t pcr;
+    NPCM7xxPWM *p;
+
+    s->pcr = new_pcr;
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        p = &s->pwm[i];
+        pcr = NPCM7XX_CH(new_pcr, i);
+        inverted = pcr & NPCM7XX_CH_INV;
+
+        /*
+         * We only run a PWM channel with toggle mode. Single-shot mode does not
+         * generate frequency and duty-cycle values.
+         */
+        if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
+            if (p->running) {
+                /* Re-run this PWM channel if inverted changed. */
+                if (p->inverted ^ inverted) {
+                    p->inverted = inverted;
+                    npcm7xx_pwm_update_duty(p);
+                }
+            } else {
+                /* Run this PWM channel. */
+                p->running = true;
+                p->inverted = inverted;
+                npcm7xx_pwm_update_output(p);
+            }
+        } else {
+            /* Clear this PWM channel. */
+            p->running = false;
+            p->inverted = inverted;
+            npcm7xx_pwm_update_output(p);
+        }
+    }
+
+}
+
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+        return 0;
+    case A_NPCM7XX_PWM_CNR1:
+        return 1;
+    case A_NPCM7XX_PWM_CNR2:
+        return 2;
+    case A_NPCM7XX_PWM_CNR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_CMR0:
+        return 0;
+    case A_NPCM7XX_PWM_CMR1:
+        return 1;
+    case A_NPCM7XX_PWM_CMR2:
+        return 2;
+    case A_NPCM7XX_PWM_CMR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_PDR0:
+        return 0;
+    case A_NPCM7XX_PWM_PDR1:
+        return 1;
+    case A_NPCM7XX_PWM_PDR2:
+        return 2;
+    case A_NPCM7XX_PWM_PDR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_PWDR0:
+        return 0;
+    case A_NPCM7XX_PWM_PWDR1:
+        return 1;
+    case A_NPCM7XX_PWM_PWDR2:
+        return 2;
+    case A_NPCM7XX_PWM_PWDR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
+{
+    NPCM7xxPWMState *s = opaque;
+    uint64_t value = 0;
+
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+    case A_NPCM7XX_PWM_CNR1:
+    case A_NPCM7XX_PWM_CNR2:
+    case A_NPCM7XX_PWM_CNR3:
+        value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
+        break;
+
+    case A_NPCM7XX_PWM_CMR0:
+    case A_NPCM7XX_PWM_CMR1:
+    case A_NPCM7XX_PWM_CMR2:
+    case A_NPCM7XX_PWM_CMR3:
+        value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
+        break;
+
+    case A_NPCM7XX_PWM_PDR0:
+    case A_NPCM7XX_PWM_PDR1:
+    case A_NPCM7XX_PWM_PDR2:
+    case A_NPCM7XX_PWM_PDR3:
+        value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
+        break;
+
+    case A_NPCM7XX_PWM_PWDR0:
+    case A_NPCM7XX_PWM_PWDR1:
+    case A_NPCM7XX_PWM_PWDR2:
+    case A_NPCM7XX_PWM_PWDR3:
+        value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
+        break;
+
+    case A_NPCM7XX_PWM_PPR:
+        value = s->ppr;
+        break;
+
+    case A_NPCM7XX_PWM_CSR:
+        value = s->csr;
+        break;
+
+    case A_NPCM7XX_PWM_PCR:
+        value = s->pcr;
+        break;
+
+    case A_NPCM7XX_PWM_PIER:
+        value = s->pier;
+        break;
+
+    case A_NPCM7XX_PWM_PIIR:
+        value = s->piir;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
+    return value;
+}
+
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
+                                uint64_t v, unsigned size)
+{
+    NPCM7xxPWMState *s = opaque;
+    NPCM7xxPWM *p;
+    uint32_t value = v;
+
+    trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+    case A_NPCM7XX_PWM_CNR1:
+    case A_NPCM7XX_PWM_CNR2:
+    case A_NPCM7XX_PWM_CNR3:
+        p = &s->pwm[npcm7xx_cnr_index(offset)];
+        p->cnr = value;
+        npcm7xx_pwm_update_output(p);
+        break;
+
+    case A_NPCM7XX_PWM_CMR0:
+    case A_NPCM7XX_PWM_CMR1:
+    case A_NPCM7XX_PWM_CMR2:
+    case A_NPCM7XX_PWM_CMR3:
+        p = &s->pwm[npcm7xx_cmr_index(offset)];
+        p->cmr = value;
+        npcm7xx_pwm_update_output(p);
+        break;
+
+    case A_NPCM7XX_PWM_PDR0:
+    case A_NPCM7XX_PWM_PDR1:
+    case A_NPCM7XX_PWM_PDR2:
+    case A_NPCM7XX_PWM_PDR3:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PWDR0:
+    case A_NPCM7XX_PWM_PWDR1:
+    case A_NPCM7XX_PWM_PWDR2:
+    case A_NPCM7XX_PWM_PWDR3:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PPR:
+        npcm7xx_pwm_write_ppr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_CSR:
+        npcm7xx_pwm_write_csr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_PCR:
+        npcm7xx_pwm_write_pcr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_PIER:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PIIR:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+}
+
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
+    .read       = npcm7xx_pwm_read,
+    .write      = npcm7xx_pwm_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        NPCM7xxPWM *p = &s->pwm[i];
+
+        p->cnr = 0x00000000;
+        p->cmr = 0x00000000;
+        p->pdr = 0x00000000;
+        p->pwdr = 0x00000000;
+    }
+
+    s->ppr = 0x00000000;
+    s->csr = 0x00000000;
+    s->pcr = 0x00000000;
+    s->pier = 0x00000000;
+    s->piir = 0x00000000;
+}
+
+static void npcm7xx_pwm_hold_reset(Object *obj)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        qemu_irq_lower(s->pwm[i].irq);
+    }
+}
+
+static void npcm7xx_pwm_init(Object *obj)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        NPCM7xxPWM *p = &s->pwm[i];
+        p->module = s;
+        p->index = i;
+        sysbus_init_irq(sbd, &p->irq);
+    }
+
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
+                          TYPE_NPCM7XX_PWM, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        object_property_add_uint32_ptr(obj, "freq[*]",
+                &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
+        object_property_add_uint32_ptr(obj, "duty[*]",
+                &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_pwm = {
+    .name = "npcm7xx-pwm",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_BOOL(running, NPCM7xxPWM),
+        VMSTATE_BOOL(inverted, NPCM7xxPWM),
+        VMSTATE_UINT8(index, NPCM7xxPWM),
+        VMSTATE_UINT32(cnr, NPCM7xxPWM),
+        VMSTATE_UINT32(cmr, NPCM7xxPWM),
+        VMSTATE_UINT32(pdr, NPCM7xxPWM),
+        VMSTATE_UINT32(pwdr, NPCM7xxPWM),
+        VMSTATE_UINT32(freq, NPCM7xxPWM),
+        VMSTATE_UINT32(duty, NPCM7xxPWM),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
+    .name = "npcm7xx-pwm-module",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_CLOCK(clock, NPCM7xxPWMState),
+        VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
+                             NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
+                             NPCM7xxPWM),
+        VMSTATE_UINT32(ppr, NPCM7xxPWMState),
+        VMSTATE_UINT32(csr, NPCM7xxPWMState),
+        VMSTATE_UINT32(pcr, NPCM7xxPWMState),
+        VMSTATE_UINT32(pier, NPCM7xxPWMState),
+        VMSTATE_UINT32(piir, NPCM7xxPWMState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx PWM Controller";
+    dc->vmsd = &vmstate_npcm7xx_pwm_module;
+    rc->phases.enter = npcm7xx_pwm_enter_reset;
+    rc->phases.hold = npcm7xx_pwm_hold_reset;
+}
+
+static const TypeInfo npcm7xx_pwm_info = {
+    .name               = TYPE_NPCM7XX_PWM,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxPWMState),
+    .class_init         = npcm7xx_pwm_class_init,
+    .instance_init      = npcm7xx_pwm_init,
+};
+
+static void npcm7xx_pwm_register_type(void)
+{
+    type_register_static(&npcm7xx_pwm_info);
+}
+type_init(npcm7xx_pwm_register_type);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
 softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
   'npcm7xx_clk.c',
   'npcm7xx_gcr.c',
+  'npcm7xx_pwm.c',
   'npcm7xx_rng.c',
 ))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
 npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 
+# npcm7xx_pwm.c
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
+
 # stm32f4xx_syscfg.c
 stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
 stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

We add a qtest for the PWM in the previous patch. It proves it works as
expected.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
 tests/qtest/meson.build        |   1 +
 2 files changed, 491 insertions(+)
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c

diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/npcm7xx_pwm-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for Nuvoton NPCM7xx PWM Modules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/qmp/qnum.h"
+
+#define REF_HZ          25000000
+
+/* Register field definitions. */
+#define CH_EN           BIT(0)
+#define CH_INV          BIT(2)
+#define CH_MOD          BIT(3)
+
+/* Registers shared between all PWMs in a module */
+#define PPR             0x00
+#define CSR             0x04
+#define PCR             0x08
+#define PIER            0x3c
+#define PIIR            0x40
+
+/* CLK module related */
+#define CLK_BA          0xf0801000
+#define CLKSEL          0x04
+#define CLKDIV1         0x08
+#define CLKDIV2         0x2c
+#define PLLCON0         0x0c
+#define PLLCON1         0x10
+#define PLL_INDV(rv)    extract32((rv), 0, 6)
+#define PLL_FBDV(rv)    extract32((rv), 16, 12)
+#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
+#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
+#define APB3CKDIV(rv)   extract32((rv), 28, 2)
+#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
+#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
+#define CPUCKSEL(rv)    extract32((rv), 0, 2)
+
+#define MAX_DUTY        1000000
+
+typedef struct PWMModule {
+    int irq;
+    uint64_t base_addr;
+} PWMModule;
+
+typedef struct PWM {
+    uint32_t cnr_offset;
+    uint32_t cmr_offset;
+    uint32_t pdr_offset;
+    uint32_t pwdr_offset;
+} PWM;
+
+typedef struct TestData {
+    const PWMModule *module;
+    const PWM *pwm;
+} TestData;
+
+static const PWMModule pwm_module_list[] = {
+    {
+        .irq        = 93,
+        .base_addr  = 0xf0103000
+    },
+    {
+        .irq        = 94,
+        .base_addr  = 0xf0104000
+    }
+};
+
+static const PWM pwm_list[] = {
+    {
+        .cnr_offset     = 0x0c,
+        .cmr_offset     = 0x10,
+        .pdr_offset     = 0x14,
+        .pwdr_offset    = 0x44,
+    },
+    {
+        .cnr_offset     = 0x18,
+        .cmr_offset     = 0x1c,
+        .pdr_offset     = 0x20,
+        .pwdr_offset    = 0x48,
+    },
+    {
+        .cnr_offset     = 0x24,
+        .cmr_offset     = 0x28,
+        .pdr_offset     = 0x2c,
+        .pwdr_offset    = 0x4c,
+    },
+    {
+        .cnr_offset     = 0x30,
+        .cmr_offset     = 0x34,
+        .pdr_offset     = 0x38,
+        .pwdr_offset    = 0x50,
+    },
+};
+
+static const int ppr_base[] = { 0, 0, 8, 8 };
+static const int csr_base[] = { 0, 4, 8, 12 };
+static const int pcr_base[] = { 0, 8, 12, 16 };
+
+static const uint32_t ppr_list[] = {
+    0,
+    1,
+    10,
+    100,
+    255, /* Max possible value. */
+};
+
+static const uint32_t csr_list[] = {
+    0,
+    1,
+    2,
+    3,
+    4, /* Max possible value. */
+};
+
+static const uint32_t cnr_list[] = {
+    0,
+    1,
+    50,
+    100,
+    150,
+    200,
+    1000,
+    10000,
+    65535, /* Max possible value. */
+};
+
+static const uint32_t cmr_list[] = {
+    0,
+    1,
+    10,
+    50,
+    100,
+    150,
+    200,
+    1000,
+    10000,
+    65535, /* Max possible value. */
+};
+
+/* Returns the index of the PWM module. */
+static int pwm_module_index(const PWMModule *module)
+{
+    ptrdiff_t diff = module - pwm_module_list;
+
+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
+
+    return diff;
+}
+
+/* Returns the index of the PWM entry. */
+static int pwm_index(const PWM *pwm)
+{
+    ptrdiff_t diff = pwm - pwm_list;
+
+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
+
+    return diff;
+}
+
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
+{
+    QDict *response;
+
+    g_test_message("Getting properties %s from %s", name, path);
+    response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
+            " 'arguments': { 'path': %s, 'property': %s}}",
+            path, name);
+    /* The qom set message returns successfully. */
+    g_assert_true(qdict_haskey(response, "return"));
+    return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
+}
+
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
+{
+    char path[100];
+    char name[100];
+
+    sprintf(path, "/machine/soc/pwm[%d]", module_index);
+    sprintf(name, "freq[%d]", pwm_index);
+
+    return pwm_qom_get(qts, path, name);
+}
+
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
+{
+    char path[100];
+    char name[100];
+
+    sprintf(path, "/machine/soc/pwm[%d]", module_index);
+    sprintf(name, "duty[%d]", pwm_index);
+
+    return pwm_qom_get(qts, path, name);
+}
+
+static uint32_t get_pll(uint32_t con)
+{
+    return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
+            * PLL_OTDV2(con));
+}
+
+static uint64_t read_pclk(QTestState *qts)
+{
+    uint64_t freq = REF_HZ;
+    uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
+    uint32_t pllcon;
+    uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
+    uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
+
+    switch (CPUCKSEL(clksel)) {
+    case 0:
+        pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
+        freq = get_pll(pllcon);
+        break;
+    case 1:
+        pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
+        freq = get_pll(pllcon);
+        break;
+    case 2:
+        break;
+    case 3:
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
+
+    return freq;
+}
+
+static uint32_t pwm_selector(uint32_t csr)
+{
+    switch (csr) {
+    case 0:
+        return 2;
+    case 1:
+        return 4;
+    case 2:
+        return 8;
+    case 3:
+        return 16;
+    case 4:
+        return 1;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
+        uint32_t cnr)
+{
+    return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
+}
+
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
+{
+    uint64_t duty;
+
+    if (cnr == 0) {
+        /* PWM is stopped. */
+        duty = 0;
+    } else if (cmr >= cnr) {
+        duty = MAX_DUTY;
+    } else {
+        duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
+    }
+
+    if (inverted) {
+        duty = MAX_DUTY - duty;
+    }
+
+    return duty;
+}
+
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
+{
+    return qtest_readl(qts, td->module->base_addr + offset);
+}
+
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
+        uint32_t value)
+{
+    qtest_writel(qts, td->module->base_addr + offset, value);
+}
+
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
+}
+
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
+}
+
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
+}
+
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
+{
+    return pwm_read(qts, td, td->pwm->cnr_offset);
+}
+
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, td->pwm->cnr_offset, value);
+}
+
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
+{
+    return pwm_read(qts, td, td->pwm->cmr_offset);
+}
+
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, td->pwm->cmr_offset, value);
+}
+
+/* Check pwm registers can be reset to default value */
+static void test_init(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+
+    g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
+    g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
+
+    qtest_quit(qts);
+}
+
+/* One-shot mode should not change frequency and duty cycle. */
+static void test_oneshot(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+    uint32_t ppr, csr, pcr;
+    int i, j;
+
+    pcr = CH_EN;
+    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
+        ppr = ppr_list[i];
+        pwm_write_ppr(qts, td, ppr);
+
+        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
+            csr = csr_list[j];
+            pwm_write_csr(qts, td, csr);
+            pwm_write_pcr(qts, td, pcr);
+
+            g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
+            g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
+            g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
+            g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
+            g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* In toggle mode, the PWM generates correct outputs. */
+static void test_toggle(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+    uint32_t ppr, csr, pcr, cnr, cmr;
+    int i, j, k, l;
+    uint64_t expected_freq, expected_duty;
+
+    pcr = CH_EN | CH_MOD;
+    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
+        ppr = ppr_list[i];
+        pwm_write_ppr(qts, td, ppr);
+
+        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
+            csr = csr_list[j];
+            pwm_write_csr(qts, td, csr);
+
+            for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
+                cnr = cnr_list[k];
+                pwm_write_cnr(qts, td, cnr);
+
+                for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
+                    cmr = cmr_list[l];
+                    pwm_write_cmr(qts, td, cmr);
+                    expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
+                    expected_duty = pwm_compute_duty(cnr, cmr, false);
+
+                    pwm_write_pcr(qts, td, pcr);
+                    g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
+                    g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
+                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
+                    g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
+                    g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
+                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
+                            ==, expected_duty);
+                    if (expected_duty != 0 && expected_duty != 100) {
+                        /* Duty cycle with 0 or 100 doesn't need frequency. */
+                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
+                                ==, expected_freq);
+                    }
+
+                    /* Test inverted mode */
+                    expected_duty = pwm_compute_duty(cnr, cmr, true);
+                    pwm_write_pcr(qts, td, pcr | CH_INV);
+                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
+                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
+                            ==, expected_duty);
+                    if (expected_duty != 0 && expected_duty != 100) {
+                        /* Duty cycle with 0 or 100 doesn't need frequency. */
+                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
+                                ==, expected_freq);
+                    }
+
+                }
+            }
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+static void pwm_add_test(const char *name, const TestData* td,
+        GTestDataFunc fn)
+{
+    g_autofree char *full_name = g_strdup_printf(
+            "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
+            pwm_index(td->pwm), name);
+    qtest_add_data_func(full_name, td, fn);
+}
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+    TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
+
+    g_test_init(&argc, &argv, NULL);
+
+    for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
+        for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
+            TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
+
+            td->module = &pwm_module_list[i];
+            td->pwm = &pwm_list[j];
+
+            add_test(init, td);
+            add_test(oneshot, td);
+            add_test(toggle, td);
+        }
+    }
+
+    return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
 qtests_npcm7xx = \
   ['npcm7xx_adc-test',
    'npcm7xx_gpio-test',
+   'npcm7xx_pwm-test',
    'npcm7xx_rng-test',
    'npcm7xx_timer-test',
    'npcm7xx_watchdog_timer-test']
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

A device shouldn't access its parent object which is QOM internal.
Instead it should use type cast for this purporse. This patch fixes this
issue for all NPCM7XX Devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx_boards.c | 2 +-
 hw/mem/npcm7xx_mc.c     | 2 +-
 hw/misc/npcm7xx_clk.c   | 2 +-
 hw/misc/npcm7xx_gcr.c   | 2 +-
 hw/misc/npcm7xx_rng.c   | 2 +-
 hw/nvram/npcm7xx_otp.c  | 2 +-
 hw/ssi/npcm7xx_fiu.c    | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
                                         uint32_t hw_straps)
 {
     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
-    MachineClass *mc = &nmc->parent;
+    MachineClass *mc = MACHINE_CLASS(nmc);
     Object *obj;
 
     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/mem/npcm7xx_mc.c
+++ b/hw/mem/npcm7xx_mc.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
 
     memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
                           NPCM7XX_MC_REGS_SIZE);
-    sysbus_init_mmio(&s->parent, &s->mmio);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
 }
 
 static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                           TYPE_NPCM7XX_CLK, 4 * KiB);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static int npcm7xx_clk_post_load(void *opaque, int version_id)
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_gcr.c
+++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
                           TYPE_NPCM7XX_GCR, 4 * KiB);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static const VMStateDescription vmstate_npcm7xx_gcr = {
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_rng.c
+++ b/hw/misc/npcm7xx_rng.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
                           NPCM7XX_RNG_REGS_SIZE);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static const VMStateDescription vmstate_npcm7xx_rng = {
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/npcm7xx_otp.c
+++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
 {
     NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
     NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
-    SysBusDevice *sbd = &s->parent;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
     memset(s->array, 0, sizeof(s->array));
 
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/npcm7xx_fiu.c
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
 static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
 {
     NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
-    SysBusDevice *sbd = &s->parent;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     int i;
 
     if (s->cs_count <= 0) {
-- 
2.20.1

From: Roman Bolshakov <r.bolshakov@yadro.com>

ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
      [-Wdeprecated-declarations]
        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
                                           ^
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
      'openFile:' has been explicitly marked deprecated here
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
^

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 ui/cocoa.m | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/ui/cocoa.m b/ui/cocoa.m
index XXXXXXX..XXXXXXX 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
     /* Where to look for local files */
     NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
     NSString *full_file_path;
+    NSURL *full_file_url;
 
     /* iterate thru the possible paths until the file is found */
     int index;
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
         full_file_path = [full_file_path stringByDeletingLastPathComponent];
         full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
                           path_array[index], filename];
-        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
+        full_file_url = [NSURL fileURLWithPath: full_file_path
+                                   isDirectory: false];
+        if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
             return;
         }
     }
-- 
2.20.1