Series comparison

-[PULL 00/23] target-arm queue
+[PULL 00/34] target-arm queue
-Two small bugfixes, plus most of RTH's refactoring of cpregs
+I might squeeze in another pullreq before softfreeze, but the
-handling.
+queue was already big enough that I wanted to send this lot out now.
 -- PMM
-The following changes since commit 1fba9dc71a170b3a05b9d3272dd8ecfe7f26e215:
+The following changes since commit 4abf70a661a5df3886ac9d7c19c3617fa92b922a:
-  Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging (2022-05-04 08:07:02 -0700)
+  Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging (2020-07-03 15:34:45 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220505
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200703
-for you to fetch changes up to 99a50d1a67c602126fc2b3a4812d3000eba9bf34:
+for you to fetch changes up to 0f10bf84a9d489259a5b11c6aa1b05c1175b76ea:
-  target/arm: read access to performance counters from EL0 (2022-05-05 09:36:22 +0100)
+  Deprecate TileGX port (2020-07-03 16:59:46 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Enable read access to performance counters from EL0
+ * i.MX6UL EVK board: put PHYs in the correct places
- * Enable SCTLR_EL1.BT0 for aarch64-linux-user
+ * hw/arm/virt: Let the virtio-iommu bypass MSIs
- * Refactoring of cpreg handling
+ * target/arm: kvm: Handle DABT with no valid ISS
  * hw/arm/virt-acpi-build: Only expose flash on older machine types
  * target/arm: Fix temp double-free in sve ldr/str
  * hw/display/bcm2835_fb.c: Initialize all fields of struct
  * hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak
  * Deprecate TileGX port
 ----------------------------------------------------------------
-Alex Zuepke (1):
+Andrew Jones (4):
-      target/arm: read access to performance counters from EL0
+      tests/acpi: remove stale allowed tables
       tests/acpi: virt: allow DSDT acpi table changes
       hw/arm/virt-acpi-build: Only expose flash on older machine types
       tests/acpi: virt: update golden masters for DSDT
-Richard Henderson (22):
+Beata Michalska (2):
-      target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
+      target/arm: kvm: Handle DABT with no valid ISS
-      target/arm: Split out cpregs.h
+      target/arm: kvm: Handle misconfigured dabt injection
       target/arm: Reorg CPAccessResult and access_check_cp_reg
       target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
       target/arm: Make some more cpreg data static const
       target/arm: Reorg ARMCPRegInfo type field bits
       target/arm: Avoid bare abort() or assert(0)
       target/arm: Change cpreg access permissions to enum
       target/arm: Name CPState type
       target/arm: Name CPSecureState type
       target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
       target/arm: Store cpregs key in the hash table directly
       target/arm: Merge allocation of the cpreg and its name
       target/arm: Hoist computation of key in add_cpreg_to_hashtable
       target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
       target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
       target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
       target/arm: Perform override check early in add_cpreg_to_hashtable
       target/arm: Reformat comments in add_cpreg_to_hashtable
       target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
       target/arm: Add isar predicates for FEAT_Debugv8p2
       target/arm: Add isar_feature_{aa64,any}_ras
- target/arm/cpregs.h               | 453 ++++++++++++++++++++++++++++++++++++++
+Eric Auger (5):
- target/arm/cpu.h                  | 393 +++------------------------------
+      qdev: Introduce DEFINE_PROP_RESERVED_REGION
- hw/arm/pxa2xx.c                   |   2 +-
+      virtio-iommu: Implement RESV_MEM probe request
- hw/arm/pxa2xx_pic.c               |   2 +-
+      virtio-iommu: Handle reserved regions in the translation process
- hw/intc/arm_gicv3_cpuif.c         |   6 +-
+      virtio-iommu-pci: Add array of Interval properties
- hw/intc/arm_gicv3_kvm.c           |   3 +-
+      hw/arm/virt: Let the virtio-iommu bypass MSIs
- target/arm/cpu.c                  |  25 +--
- target/arm/cpu64.c                |   2 +-
+Jean-Christophe Dubois (3):
- target/arm/cpu_tcg.c              |   5 +-
+      Add a phy-num property to the i.MX FEC emulator
- target/arm/gdbstub.c              |   5 +-
+      Add the ability to select a different PHY for each i.MX6UL FEC interface
- target/arm/helper.c               | 358 +++++++++++++-----------------
+      Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.
- target/arm/hvf/hvf.c              |   2 +-
- target/arm/kvm-stub.c             |   4 +-
+Peter Maydell (19):
- target/arm/kvm.c                  |   4 +-
+      hw/display/bcm2835_fb.c: Initialize all fields of struct
- target/arm/machine.c              |   4 +-
+      hw/arm/spitz: Detabify
- target/arm/op_helper.c            |  57 ++---
+      hw/arm/spitz: Create SpitzMachineClass abstract base class
- target/arm/translate-a64.c        |  14 +-
+      hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
- target/arm/translate-neon.c       |   2 +-
+      hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
- target/arm/translate.c            |  13 +-
+      hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
- tests/tcg/aarch64/bti-3.c         |  42 ++++
+      hw/misc/max111x: provide QOM properties for setting initial values
- tests/tcg/aarch64/Makefile.target |   6 +-
+      hw/misc/max111x: Don't use vmstate_register()
-files changed, 738 insertions(+), 664 deletions(-)
+      ssi: Add ssi_realize_and_unref()
- create mode 100644 target/arm/cpregs.h
+      hw/arm/spitz: Use max111x properties to set initial values
- create mode 100644 tests/tcg/aarch64/bti-3.c
+      hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
       hw/misc/max111x: Create header file for documentation, TYPE_ macros
       hw/arm/spitz: Encapsulate misc GPIO handling in a device
       hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
       hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
       hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
       hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
       Replace uses of FROM_SSI_SLAVE() macro with QOM casts
       Deprecate TileGX port
 Richard Henderson (1):
       target/arm: Fix temp double-free in sve ldr/str
  docs/system/deprecated.rst                  |  11 +
  include/exec/memory.h                       |   6 +
  include/hw/arm/fsl-imx6ul.h                 |   2 +
  include/hw/arm/pxa.h                        |   1 -
  include/hw/arm/sharpsl.h                    |   3 -
  include/hw/arm/virt.h                       |   8 +
  include/hw/misc/max111x.h                   |  56 +++
  include/hw/net/imx_fec.h                    |   1 +
  include/hw/qdev-properties.h                |   3 +
  include/hw/ssi/ssi.h                        |  31 +-
  include/hw/virtio/virtio-iommu.h            |   2 +
  include/qemu/typedefs.h                     |   1 +
  target/arm/cpu.h                            |   2 +
  target/arm/kvm_arm.h                        |  10 +
  target/arm/translate-a64.h                  |   1 +
  tests/qtest/bios-tables-test-allowed-diff.h |  18 -
  hw/arm/fsl-imx6ul.c                         |  10 +
  hw/arm/mcimx6ul-evk.c                       |   2 +
  hw/arm/pxa2xx_pic.c                         |   9 +-
  hw/arm/spitz.c                              | 507 ++++++++++++++++------------
  hw/arm/virt-acpi-build.c                    |   5 +-
  hw/arm/virt.c                               |  33 ++
  hw/arm/z2.c                                 |  11 +-
  hw/core/qdev-properties.c                   |  89 +++++
  hw/display/ads7846.c                        |   9 +-
  hw/display/bcm2835_fb.c                     |   4 +
  hw/display/ssd0323.c                        |  10 +-
  hw/gpio/zaurus.c                            |  12 +-
  hw/misc/max111x.c                           |  86 +++--
  hw/net/imx_fec.c                            |  24 +-
  hw/sd/ssi-sd.c                              |   4 +-
  hw/ssi/ssi.c                                |   7 +-
  hw/virtio/virtio-iommu-pci.c                |  11 +
  hw/virtio/virtio-iommu.c                    | 114 ++++++-
  target/arm/kvm.c                            |  80 +++++
  target/arm/kvm32.c                          |  34 ++
  target/arm/kvm64.c                          |  49 +++
  target/arm/translate-a64.c                  |   6 +
  target/arm/translate-sve.c                  |   8 +-
  MAINTAINERS                                 |   1 +
  hw/net/trace-events                         |   4 +-
  hw/virtio/trace-events                      |   1 +
  tests/data/acpi/virt/DSDT                   | Bin 5307 -> 5205 bytes
  tests/data/acpi/virt/DSDT.memhp             | Bin 6668 -> 6566 bytes
  tests/data/acpi/virt/DSDT.numamem           | Bin 5307 -> 5205 bytes
 files changed, 974 insertions(+), 312 deletions(-)
  create mode 100644 include/hw/misc/max111x.h

-[PULL 17/23] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
+[PULL 01/34] Add a phy-num property to the i.MX FEC emulator
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Computing isbanked only once makes the code
+We need a solution to use an Ethernet PHY that is not the first device
-a bit easier to read.
+on the MDIO bus (device 0 on MDIO bus).
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but
 only one MDIO bus on which the 2 related PHY are connected but at unique
 addresses.
 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
 Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-17-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 6 ++++--
+ include/hw/net/imx_fec.h |  1 +
-file changed, 4 insertions(+), 2 deletions(-)
+ hw/net/imx_fec.c         | 24 +++++++++++++++++-------
  hw/net/trace-events      |  4 ++--
 files changed, 20 insertions(+), 9 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/include/hw/net/imx_fec.h
-+++ b/target/arm/helper.c
++++ b/include/hw/net/imx_fec.h
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ typedef struct IMXFECState {
-     bool is64 = r->type & ARM_CP_64BIT;
+     uint32_t phy_advertise;
-     bool ns = secstate & ARM_CP_SECSTATE_NS;
+     uint32_t phy_int;
-     int cp = r->cp;
+     uint32_t phy_int_mask;
-+    bool isbanked;
++    uint32_t phy_num;
-     size_t name_len;
+     bool is_fec;
-     switch (state) {
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
-         r2->opaque = opaque;
+index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/imx_fec.c
 +++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_phy_reset(IMXFECState *s)
  static uint32_t imx_phy_read(IMXFECState *s, int reg)
  {
      uint32_t val;
 +    uint32_t phy = reg / 32;
 -    if (reg > 31) {
 -        /* we only advertise one phy */
 +    if (phy != s->phy_num) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
 +                      TYPE_IMX_FEC, __func__, phy);
          return 0;
      }
--    if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
++    reg %= 32;
-+    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
++
-+    if (isbanked) {
+     switch (reg) {
-         /* Register is banked (using both entries in array).
+     case 0:     /* Basic Control */
-          * Overwriting fieldoffset as the array is only used to define
+         val = s->phy_control;
-          * banked registers but later only fieldoffset is used.
+@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+         break;
      }
-     if (state == ARM_CP_STATE_AA32) {
+-    trace_imx_phy_read(val, reg);
--        if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
++    trace_imx_phy_read(val, phy, reg);
-+        if (isbanked) {
-             /* If the register is banked then we don't need to migrate or
+     return val;
-              * reset the 32-bit instance in certain cases:
+ }
-              *
  static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
  {
 -    trace_imx_phy_write(val, reg);
 +    uint32_t phy = reg / 32;
 -    if (reg > 31) {
 -        /* we only advertise one phy */
 +    if (phy != s->phy_num) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
 +                      TYPE_IMX_FEC, __func__, phy);
          return;
      }
 +    reg %= 32;
 +
 +    trace_imx_phy_write(val, phy, reg);
 +
      switch (reg) {
      case 0:     /* Basic Control */
          if (val & 0x8000) {
@@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
                                                         extract32(value,
 , 10)));
          } else {
 -            /* This a write operation */
 +            /* This is a write operation */
              imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
          }
          /* raise the interrupt as the PHY operation is done */
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
  static Property imx_eth_properties[] = {
      DEFINE_NIC_PROPERTIES(IMXFECState, conf),
      DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
 +    DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
      DEFINE_PROP_END_OF_LIST(),
  };
 diff --git a/hw/net/trace-events b/hw/net/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/trace-events
 +++ b/hw/net/trace-events
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
  i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
  # imx_fec.c
 -imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
 -imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
 +imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
 +imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
  imx_phy_update_link(const char *s) "%s"
  imx_phy_reset(void) ""
  imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
 --
-.25.1
+.20.1

-[PULL 10/23] target/arm: Name CPSecureState type
+[PULL 02/34] Add the ability to select a different PHY for each i.MX6UL FEC interface
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
+Add properties to the i.MX6UL processor to be able to select a
-Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
+particular PHY on the MDIO bus for each FEC device.
 is handled in define_one_arm_cp_reg_with_opaque.
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-10-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h | 7 ++++---
+ include/hw/arm/fsl-imx6ul.h |  2 ++
- target/arm/helper.c | 7 +++++--
+ hw/arm/fsl-imx6ul.c         | 10 ++++++++++
-files changed, 9 insertions(+), 5 deletions(-)
+files changed, 12 insertions(+)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/target/arm/cpregs.h
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
-  * registered entry will only have one to identify whether the entry is secure
+     MemoryRegion       caam;
-  * or non-secure.
+     MemoryRegion       ocram;
-  */
+     MemoryRegion       ocram_alias;
--enum {
++
-+typedef enum {
++    uint32_t           phy_num[FSL_IMX6UL_NUM_ETHS];
-+    ARM_CP_SECSTATE_BOTH = 0,       /* define one cpreg for each secstate */
+ } FslIMX6ULState;
-     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
-     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
+ enum FslIMX6ULMemoryMap {
--};
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
 +} CPSecureState;
  /*
   * Access rights:
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
      /* Access rights: PL*_[RW] */
      CPAccessRights access;
      /* Security state: ARM_CP_SECSTATE_* bits/values */
 -    int secure;
 +    CPSecureState secure;
      /*
       * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
       * this register was defined: can be used to hand data through to the
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/fsl-imx6ul.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/fsl-imx6ul.c
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
              FSL_IMX6UL_ENET2_TIMER_IRQ,
          };
 +        object_property_set_uint(OBJECT(&s->eth[i]),
 +                                 s->phy_num[i],
 +                                 "phy-num", &error_abort);
          object_property_set_uint(OBJECT(&s->eth[i]),
                                   FSL_IMX6UL_ETH_NUM_TX_RINGS,
                                   "tx-ring-num", &error_abort);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                  FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
  }
- static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++static Property fsl_imx6ul_properties[] = {
--                                   void *opaque, CPState state, int secstate,
++    DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
-+                                   void *opaque, CPState state,
++    DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
-+                                   CPSecureState secstate,
++    DEFINE_PROP_END_OF_LIST(),
-                                    int crm, int opc1, int opc2,
++};
-                                    const char *name)
++
  static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
  {
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+     DeviceClass *dc = DEVICE_CLASS(oc);
-                                                    r->secure, crm, opc1, opc2,
-                                                    r->name);
++    device_class_set_props(dc, fsl_imx6ul_properties);
-                             break;
+     dc->realize = fsl_imx6ul_realize;
--                        default:
+     dc->desc = "i.MX6UL SOC";
-+                        case ARM_CP_SECSTATE_BOTH:
+     /* Reason: Uses serial_hds and nd_table in realize() directly */
                              name = g_strdup_printf("%s_S", r->name);
                              add_cpreg_to_hashtable(cpu, r, opaque, state,
                                                     ARM_CP_SECSTATE_S,
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                                     ARM_CP_SECSTATE_NS,
                                                     crm, opc1, opc2, r->name);
                              break;
 +                        default:
 +                            g_assert_not_reached();
                          }
                      } else {
                          /* AArch64 registers get mapped to non-secure instance
 --
-.25.1
+.20.1

-New patch
+[PULL 03/34] Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+The i.MX6UL EVK 14x14 board uses:
+- PHY 2 for FEC 1
+- PHY 1 for FEC 2
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: fb41992126c091a71d76ab3d1898959091f60583.1593296112.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/mcimx6ul-evk.c | 2 ++
+file changed, 2 insertions(+)
+diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mcimx6ul-evk.c
++++ b/hw/arm/mcimx6ul-evk.c
+@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
+     s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
+     object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
++    object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal);
++    object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal);
+     qdev_realize(DEVICE(s), NULL, &error_fatal);
+     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
+--
+.20.1

-[PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashtable
+[PULL 04/34] qdev: Introduce DEFINE_PROP_RESERVED_REGION
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Eric Auger <eric.auger@redhat.com>
-Move the computation of key to the top of the function.
+Introduce a new property defining a reserved region:
-Hoist the resolution of cp as well, as an input to the
+<low address>:<high address>:<type>.
 computation of key.
-This will be required by a subsequent patch.
+This will be used to encode reserved IOVA regions.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+For instance, in virtio-iommu use case, reserved IOVA regions
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+will be passed by the machine code to the virtio-iommu-pci
-Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
+device (an array of those). The type of the reserved region
 will match the virtio_iommu_probe_resv_mem subtype value:
 - VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0)
 - VIRTIO_IOMMU_RESV_MEM_T_MSI (1)
 on PC/Q35 machine, this will be used to inform the
 virtio-iommu-pci device it should bypass the MSI region.
 The reserved region will be: 0xfee00000:0xfeefffff:1.
 On ARM, we can declare the ITS MSI doorbell as an MSI
 region to prevent MSIs from being mapped on guest side.
 Signed-off-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Markus Armbruster <armbru@redhat.com>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Message-id: 20200629070404.10969-2-eric.auger@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 49 +++++++++++++++++++++++++--------------------
+ include/exec/memory.h        |  6 +++
-file changed, 27 insertions(+), 22 deletions(-)
+ include/hw/qdev-properties.h |  3 ++
  include/qemu/typedefs.h      |  1 +
  hw/core/qdev-properties.c    | 89 ++++++++++++++++++++++++++++++++++++
 files changed, 99 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/include/exec/memory.h b/include/exec/memory.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/include/exec/memory.h
-+++ b/target/arm/helper.c
++++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ extern bool global_dirty_log;
-     ARMCPRegInfo *r2;
-     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
+ typedef struct MemoryRegionOps MemoryRegionOps;
-     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
-+    int cp = r->cp;
++struct ReservedRegion {
-     size_t name_len;
++    hwaddr low;
++    hwaddr high;
-+    switch (state) {
++    unsigned type;
-+    case ARM_CP_STATE_AA32:
++};
-+        /* We assume it is a cp15 register if the .cp field is left unset. */
++
-+        if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
+ typedef struct IOMMUTLBEntry IOMMUTLBEntry;
-+            cp = 15;
-+        }
+ /* See address_space_translate: bit 0 is read, bit 1 is write.  */
-+        key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
+diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
-+        break;
+index XXXXXXX..XXXXXXX 100644
-+    case ARM_CP_STATE_AA64:
+--- a/include/hw/qdev-properties.h
-+        /*
++++ b/include/hw/qdev-properties.h
-+         * To allow abbreviation of ARMCPRegInfo definitions, we treat
+@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_string;
-+         * cp == 0 as equivalent to the value for "standard guest-visible
+ extern const PropertyInfo qdev_prop_chr;
-+         * sysreg".  STATE_BOTH definitions are also always "standard sysreg"
+ extern const PropertyInfo qdev_prop_tpm;
-+         * in their AArch64 view (the .cp value may be non-zero for the
+ extern const PropertyInfo qdev_prop_macaddr;
-+         * benefit of the AArch32 view).
++extern const PropertyInfo qdev_prop_reserved_region;
-+         */
+ extern const PropertyInfo qdev_prop_on_off_auto;
-+        if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+ extern const PropertyInfo qdev_prop_multifd_compression;
-+            cp = CP_REG_ARM64_SYSREG_CP;
+ extern const PropertyInfo qdev_prop_losttickpolicy;
-+        }
+@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_width;
-+        key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
+     DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *)
-+        break;
+ #define DEFINE_PROP_MACADDR(_n, _s, _f)         \
-+    default:
+     DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
-+        g_assert_not_reached();
++#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f)         \
 +    DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion)
  #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
      DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
  #define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \
 diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/qemu/typedefs.h
 +++ b/include/qemu/typedefs.h
@@ -XXX,XX +XXX,XX @@ typedef struct ISABus ISABus;
  typedef struct ISADevice ISADevice;
  typedef struct IsaDma IsaDma;
  typedef struct MACAddr MACAddr;
 +typedef struct ReservedRegion ReservedRegion;
  typedef struct MachineClass MachineClass;
  typedef struct MachineState MachineState;
  typedef struct MemoryListener MemoryListener;
 diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/qdev-properties.c
 +++ b/hw/core/qdev-properties.c
@@ -XXX,XX +XXX,XX @@
  #include "chardev/char.h"
  #include "qemu/uuid.h"
  #include "qemu/units.h"
 +#include "qemu/cutils.h"
  void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
                                    Error **errp)
@@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_macaddr = {
      .set   = set_mac,
  };
 +/* --- Reserved Region --- */
 +
 +/*
 + * Accepted syntax:
 + *   <low address>:<high address>:<type>
 + *   where low/high addresses are uint64_t in hexadecimal
 + *   and type is a non-negative decimal integer
 + */
 +static void get_reserved_region(Object *obj, Visitor *v, const char *name,
 +                                void *opaque, Error **errp)
 +{
 +    DeviceState *dev = DEVICE(obj);
 +    Property *prop = opaque;
 +    ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
 +    char buffer[64];
 +    char *p = buffer;
 +    int rc;
 +
 +    rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u",
 +                  rr->low, rr->high, rr->type);
 +    assert(rc < sizeof(buffer));
 +
 +    visit_type_str(v, name, &p, errp);
 +}
 +
 +static void set_reserved_region(Object *obj, Visitor *v, const char *name,
 +                                void *opaque, Error **errp)
 +{
 +    DeviceState *dev = DEVICE(obj);
 +    Property *prop = opaque;
 +    ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
 +    Error *local_err = NULL;
 +    const char *endptr;
 +    char *str;
 +    int ret;
 +
 +    if (dev->realized) {
 +        qdev_prop_set_after_realize(dev, name, errp);
 +        return;
 +    }
 +
-     /* Combine cpreg and name into one allocation. */
++    visit_type_str(v, name, &str, &local_err);
-     name_len = strlen(name) + 1;
++    if (local_err) {
-     r2 = g_malloc(sizeof(*r2) + name_len);
++        error_propagate(errp, local_err);
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++        return;
-         }
++    }
++
-         if (r->state == ARM_CP_STATE_BOTH) {
++    ret = qemu_strtou64(str, &endptr, 16, &rr->low);
--            /* We assume it is a cp15 register if the .cp field is left unset.
++    if (ret) {
--             */
++        error_setg(errp, "start address of '%s'"
--            if (r2->cp == 0) {
++                   " must be a hexadecimal integer", name);
--                r2->cp = 15;
++        goto out;
--            }
++    }
--
++    if (*endptr != ':') {
- #if HOST_BIG_ENDIAN
++        goto separator_error;
-             if (r2->fieldoffset) {
++    }
-                 r2->fieldoffset += sizeof(uint32_t);
++
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++    ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high);
- #endif
++    if (ret) {
-         }
++        error_setg(errp, "end address of '%s'"
-     }
++                   " must be a hexadecimal integer", name);
--    if (state == ARM_CP_STATE_AA64) {
++        goto out;
--        /* To allow abbreviation of ARMCPRegInfo
++    }
--         * definitions, we treat cp == 0 as equivalent to
++    if (*endptr != ':') {
--         * the value for "standard guest-visible sysreg".
++        goto separator_error;
--         * STATE_BOTH definitions are also always "standard
++    }
--         * sysreg" in their AArch64 view (the .cp value may
++
--         * be non-zero for the benefit of the AArch32 view).
++    ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type);
--         */
++    if (ret) {
--        if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
++        error_setg(errp, "type of '%s'"
--            r2->cp = CP_REG_ARM64_SYSREG_CP;
++                   " must be a non-negative decimal integer", name);
--        }
++    }
--        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
++    goto out;
--                                 r2->opc0, opc1, opc2);
++
--    } else {
++separator_error:
--        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
++    error_setg(errp, "reserved region fields must be separated with ':'");
--    }
++out:
-     if (opaque) {
++    g_free(str);
-         r2->opaque = opaque;
++    return;
-     }
++}
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++
-     /* Make sure reginfo passed to helpers for wildcarded regs
++const PropertyInfo qdev_prop_reserved_region = {
-      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
++    .name  = "reserved_region",
-      */
++    .description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0",
-+    r2->cp = cp;
++    .get   = get_reserved_region,
-     r2->crm = crm;
++    .set   = set_reserved_region,
-     r2->opc1 = opc1;
++};
-     r2->opc2 = opc2;
++
  /* --- on/off/auto --- */
  const PropertyInfo qdev_prop_on_off_auto = {
 --
-.25.1
+.20.1

-[PULL 22/23] target/arm: Add isar_feature_{aa64,any}_ras
+[PULL 05/34] virtio-iommu: Implement RESV_MEM probe request
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Eric Auger <eric.auger@redhat.com>
-Add the aa64 predicate for detecting RAS support from id registers.
+This patch implements the PROBE request. At the moment,
-We already have the aa32 version from the M-profile work.
+only THE RESV_MEM property is handled. The first goal is
-Add the 'any' predicate for testing both aa64 and aa32.
+to report iommu wide reserved regions such as the MSI regions
+set by the machine code. On x86 this will be the IOAPIC MSI
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+region, [0xFEE00000 - 0xFEEFFFFF], on ARM this may be the ITS
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+doorbell.
-Message-id: 20220501055028.646596-34-richard.henderson@linaro.org
 In the future we may introduce per device reserved regions.
 This will be useful when protecting host assigned devices
 which may expose their own reserved regions
 Signed-off-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Message-id: 20200629070404.10969-3-eric.auger@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 10 ++++++++++
+ include/hw/virtio/virtio-iommu.h |  2 +
-file changed, 10 insertions(+)
+ hw/virtio/virtio-iommu.c         | 94 ++++++++++++++++++++++++++++++--
+ hw/virtio/trace-events           |  1 +
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+files changed, 93 insertions(+), 4 deletions(-)
 diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/include/hw/virtio/virtio-iommu.h
-+++ b/target/arm/cpu.h
++++ b/include/hw/virtio/virtio-iommu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ typedef struct VirtIOIOMMU {
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
+     GHashTable *as_by_busptr;
      IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX];
      PCIBus *primary_bus;
 +    ReservedRegion *reserved_regions;
 +    uint32_t nb_reserved_regions;
      GTree *domains;
      QemuMutex mutex;
      GTree *endpoints;
 diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/virtio/virtio-iommu.c
 +++ b/hw/virtio/virtio-iommu.c
@@ -XXX,XX +XXX,XX @@
  /* Max size */
  #define VIOMMU_DEFAULT_QUEUE_SIZE 256
 +#define VIOMMU_PROBE_SIZE 512
  typedef struct VirtIOIOMMUDomain {
      uint32_t id;
@@ -XXX,XX +XXX,XX @@ static int virtio_iommu_unmap(VirtIOIOMMU *s,
      return ret;
  }
-+static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
++static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep,
 +                                               uint8_t *buf, size_t free)
 +{
-+    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
++    struct virtio_iommu_probe_resv_mem prop = {};
 +    size_t size = sizeof(prop), length = size - sizeof(prop.head), total;
 +    int i;
 +
 +    total = size * s->nb_reserved_regions;
 +
 +    if (total > free) {
 +        return -ENOSPC;
 +    }
 +
 +    for (i = 0; i < s->nb_reserved_regions; i++) {
 +        unsigned subtype = s->reserved_regions[i].type;
 +
 +        assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED ||
 +               subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI);
 +        prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM);
 +        prop.head.length = cpu_to_le16(length);
 +        prop.subtype = subtype;
 +        prop.start = cpu_to_le64(s->reserved_regions[i].low);
 +        prop.end = cpu_to_le64(s->reserved_regions[i].high);
 +
 +        memcpy(buf, &prop, size);
 +
 +        trace_virtio_iommu_fill_resv_property(ep, prop.subtype,
 +                                              prop.start, prop.end);
 +        buf += size;
 +    }
 +    return total;
 +}
 +
- static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
++/**
 + * virtio_iommu_probe - Fill the probe request buffer with
 + * the properties the device is able to return
 + */
 +static int virtio_iommu_probe(VirtIOIOMMU *s,
 +                              struct virtio_iommu_req_probe *req,
 +                              uint8_t *buf)
 +{
 +    uint32_t ep_id = le32_to_cpu(req->endpoint);
 +    size_t free = VIOMMU_PROBE_SIZE;
 +    ssize_t count;
 +
 +    if (!virtio_iommu_mr(s, ep_id)) {
 +        return VIRTIO_IOMMU_S_NOENT;
 +    }
 +
 +    count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free);
 +    if (count < 0) {
 +        return VIRTIO_IOMMU_S_INVAL;
 +    }
 +    buf += count;
 +    free -= count;
 +
 +    return VIRTIO_IOMMU_S_OK;
 +}
 +
  static int virtio_iommu_iov_to_req(struct iovec *iov,
                                     unsigned int iov_cnt,
                                     void *req, size_t req_sz)
@@ -XXX,XX +XXX,XX @@ virtio_iommu_handle_req(detach)
  virtio_iommu_handle_req(map)
  virtio_iommu_handle_req(unmap)
 +static int virtio_iommu_handle_probe(VirtIOIOMMU *s,
 +                                     struct iovec *iov,
 +                                     unsigned int iov_cnt,
 +                                     uint8_t *buf)
 +{
 +    struct virtio_iommu_req_probe req;
 +    int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req));
 +
 +    return ret ? ret : virtio_iommu_probe(s, &req, buf);
 +}
 +
  static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
  {
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
+     VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
+     struct virtio_iommu_req_head head;
-     return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
+     struct virtio_iommu_req_tail tail = {};
 +    size_t output_size = sizeof(tail), sz;
      VirtQueueElement *elem;
      unsigned int iov_cnt;
      struct iovec *iov;
 -    size_t sz;
 +    void *buf = NULL;
      for (;;) {
          elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
          case VIRTIO_IOMMU_T_UNMAP:
              tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
              break;
 +        case VIRTIO_IOMMU_T_PROBE:
 +        {
 +            struct virtio_iommu_req_tail *ptail;
 +
 +            output_size = s->config.probe_size + sizeof(tail);
 +            buf = g_malloc0(output_size);
 +
 +            ptail = (struct virtio_iommu_req_tail *)
 +                        (buf + s->config.probe_size);
 +            ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf);
 +        }
          default:
              tail.status = VIRTIO_IOMMU_S_UNSUPP;
          }
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
  out:
          sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
 -                          &tail, sizeof(tail));
 -        assert(sz == sizeof(tail));
 +                          buf ? buf : &tail, output_size);
 +        assert(sz == output_size);
 -        virtqueue_push(vq, elem, sizeof(tail));
 +        virtqueue_push(vq, elem, sz);
          virtio_notify(vdev, vq);
          g_free(elem);
 +        g_free(buf);
      }
  }
-+static inline bool isar_feature_any_ras(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
-+{
+     s->config.page_size_mask = TARGET_PAGE_MASK;
-+    return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
+     s->config.input_range.end = -1UL;
-+}
+     s->config.domain_range.end = 32;
-+
++    s->config.probe_size = VIOMMU_PROBE_SIZE;
- /*
-  * Forward to the above feature tests given an ARMCPU pointer.
+     virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX);
-  */
+     virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC);
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
      virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP);
      virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS);
      virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO);
 +    virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE);
      qemu_mutex_init(&s->mutex);
 diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/virtio/trace-events
 +++ b/hw/virtio/trace-events
@@ -XXX,XX +XXX,XX @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d"
  virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d"
  virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d"
  virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64
 +virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64
 --
-.25.1
+.20.1

-[PULL 05/23] target/arm: Make some more cpreg data static const
+[PULL 06/34] virtio-iommu: Handle reserved regions in the translation process
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Eric Auger <eric.auger@redhat.com>
-These particular data structures are not modified at runtime.
+When translating an address we need to check if it belongs to
 a reserved virtual address range. If it does, there are 2 cases:
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+- it belongs to a RESERVED region: the guest should neither use
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+  this address in a MAP not instruct the end-point to DMA on
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+  them. We report an error
-Message-id: 20220501055028.646596-5-richard.henderson@linaro.org
 - It belongs to an MSI region: we bypass the translation.
 Signed-off-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Peter Xu <peterx@redhat.com>
 Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Message-id: 20200629070404.10969-4-eric.auger@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 16 ++++++++--------
+ hw/virtio/virtio-iommu.c | 20 ++++++++++++++++++++
-file changed, 8 insertions(+), 8 deletions(-)
+file changed, 20 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/virtio/virtio-iommu.c
-+++ b/target/arm/helper.c
++++ b/hw/virtio/virtio-iommu.c
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
-               .resetvalue = cpu->pmceid1 },
+     uint32_t sid, flags;
-         };
+     bool bypass_allowed;
- #ifdef CONFIG_USER_ONLY
+     bool found;
--        ARMCPRegUserSpaceInfo v8_user_idregs[] = {
++    int i;
-+        static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
-             { .name = "ID_AA64PFR0_EL1",
+     interval.low = addr;
-               .exported_bits = 0x000f000f00ff0000,
+     interval.high = addr + 1;
-               .fixed_bits    = 0x0000000000000011 },
+@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+         goto unlock;
       */
      if (arm_feature(env, ARM_FEATURE_EL3)) {
          if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 -            ARMCPRegInfo nsacr = {
 +            static const ARMCPRegInfo nsacr = {
                  .name = "NSACR", .type = ARM_CP_CONST,
                  .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                  .access = PL1_RW, .accessfn = nsacr_access,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              };
              define_one_arm_cp_reg(cpu, &nsacr);
          } else {
 -            ARMCPRegInfo nsacr = {
 +            static const ARMCPRegInfo nsacr = {
                  .name = "NSACR",
                  .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                  .access = PL3_RW | PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          }
      } else {
          if (arm_feature(env, ARM_FEATURE_V8)) {
 -            ARMCPRegInfo nsacr = {
 +            static const ARMCPRegInfo nsacr = {
                  .name = "NSACR", .type = ARM_CP_CONST,
                  .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                  .access = PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .type = ARM_CP_CONST,
                .resetvalue = cpu->pmsav7_dregion << 8
          };
 -        ARMCPRegInfo crn0_wi_reginfo = {
 +        static const ARMCPRegInfo crn0_wi_reginfo = {
              .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
              .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
              .type = ARM_CP_NOP | ARM_CP_OVERRIDE
          };
  #ifdef CONFIG_USER_ONLY
 -        ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
 +        static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
              { .name = "MIDR_EL1",
                .exported_bits = 0x00000000ffffffff },
              { .name = "REVIDR_EL1"                },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
          };
  #ifdef CONFIG_USER_ONLY
 -        ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
 +        static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
              { .name = "MPIDR_EL1",
                .fixed_bits = 0x0000000080000000 },
          };
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      }
-     if (arm_feature(env, ARM_FEATURE_VBAR)) {
++    for (i = 0; i < s->nb_reserved_regions; i++) {
--        ARMCPRegInfo vbar_cp_reginfo[] = {
++        ReservedRegion *reg = &s->reserved_regions[i];
-+        static const ARMCPRegInfo vbar_cp_reginfo[] = {
++
-             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
++        if (addr >= reg->low && addr <= reg->high) {
-               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
++            switch (reg->type) {
-               .access = PL1_RW, .writefn = vbar_write,
++            case VIRTIO_IOMMU_RESV_MEM_T_MSI:
 +                entry.perm = flag;
 +                break;
 +            case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:
 +            default:
 +                virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING,
 +                                          VIRTIO_IOMMU_FAULT_F_ADDRESS,
 +                                          sid, addr);
 +                break;
 +            }
 +            goto unlock;
 +        }
 +    }
 +
      if (!ep->domain) {
          if (!bypass_allowed) {
              error_report_once("%s %02x:%02x.%01x not attached to any domain",
 --
-.25.1
+.20.1

-New patch
+[PULL 07/34] virtio-iommu-pci: Add array of Interval properties
+From: Eric Auger <eric.auger@redhat.com>
+The machine may need to pass reserved regions to the
+virtio-iommu-pci device (such as the MSI window on x86
+or the MSI doorbells on ARM).
+So let's add an array of Interval properties.
+Note: if some reserved regions are already set by the
+machine code - which should be the case in general -,
+the length of the property array is already set and
+prevents the end-user from modifying them. For example,
+attempting to use:
+-device virtio-iommu-pci,\
+ len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1
+would result in the following error message:
+qemu-system-aarch64: -device virtio-iommu-pci,addr=0xa,
+len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1:
+array size property len-reserved-regions may not be set more than once
+Otherwise, for example, adding two reserved regions is achieved
+using the following options:
+-device virtio-iommu-pci,addr=0xa,len-reserved-regions=2,\
+ reserved-regions[0]=0xfee00000:0xfeefffff:1,\
+ reserved-regions[1]=0x1000000:100ffff:1
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
+Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Reviewed-by: Peter Xu <peterx@redhat.com>
+Message-id: 20200629070404.10969-5-eric.auger@redhat.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/virtio/virtio-iommu-pci.c | 11 +++++++++++
+file changed, 11 insertions(+)
+diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/virtio/virtio-iommu-pci.c
++++ b/hw/virtio/virtio-iommu-pci.c
+@@ -XXX,XX +XXX,XX @@ struct VirtIOIOMMUPCI {
+ static Property virtio_iommu_pci_properties[] = {
+     DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
++    DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI,
++                      vdev.nb_reserved_regions, vdev.reserved_regions,
++                      qdev_prop_reserved_region, ReservedRegion),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
+ {
+     VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev);
+     DeviceState *vdev = DEVICE(&dev->vdev);
++    VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
+     if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
+         MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
+@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
+                           "-no-acpi\n");
+         return;
+     }
++    for (int i = 0; i < s->nb_reserved_regions; i++) {
++        if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED &&
++            s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) {
++            error_setg(errp, "reserved region %d has an invalid type", i);
++            error_append_hint(errp, "Valid values are 0 and 1\n");
++        }
++    }
+     object_property_set_link(OBJECT(dev),
+                              OBJECT(pci_get_bus(&vpci_dev->pci_dev)),
+                              "primary-bus", &error_abort);
+--
+.20.1

-[PULL 18/23] target/arm: Perform override check early in add_cpreg_to_hashtable
+[PULL 08/34] hw/arm/virt: Let the virtio-iommu bypass MSIs
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Eric Auger <eric.auger@redhat.com>
-Perform the override check early, so that it is still done
+At the moment the virtio-iommu translates MSI transactions.
-even when we decide to discard an unreachable cpreg.
+This behavior is inherited from ARM SMMU. The virt machine
 code knows where the guest MSI doorbells are so we can easily
 declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
 setting the guest will not map MSIs through the IOMMU and those
 transactions will be simply bypassed.
-Use assert not printf+abort.
+Depending on which MSI controller is in use (ITS or GICV2M),
 we declare either:
 - the ITS interrupt translation space (ITS_base + 0x10000),
   containing the GITS_TRANSLATOR or
 - The GICV2M single frame, containing the MSI_SETSP_NS register.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20200629070404.10969-6-eric.auger@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-18-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 22 ++++++++--------------
+ include/hw/arm/virt.h |  7 +++++++
-file changed, 8 insertions(+), 14 deletions(-)
+ hw/arm/virt.c         | 30 ++++++++++++++++++++++++++++++
 files changed, 37 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/include/hw/arm/virt.h
-+++ b/target/arm/helper.c
++++ b/include/hw/arm/virt.h
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
-         g_assert_not_reached();
+     VIRT_IOMMU_VIRTIO,
  } VirtIOMMUType;
 +typedef enum VirtMSIControllerType {
 +    VIRT_MSI_CTRL_NONE,
 +    VIRT_MSI_CTRL_GICV2M,
 +    VIRT_MSI_CTRL_ITS,
 +} VirtMSIControllerType;
 +
  typedef enum VirtGICType {
      VIRT_GIC_VERSION_MAX,
      VIRT_GIC_VERSION_HOST,
@@ -XXX,XX +XXX,XX @@ typedef struct {
      OnOffAuto acpi;
      VirtGICType gic_version;
      VirtIOMMUType iommu;
 +    VirtMSIControllerType msi_controller;
      uint16_t virtio_iommu_bdf;
      struct arm_boot_info bootinfo;
      MemMapEntry *memmap;
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_its(VirtMachineState *vms)
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
      fdt_add_its_gic_node(vms);
 +    vms->msi_controller = VIRT_MSI_CTRL_ITS;
  }
  static void create_v2m(VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms)
      }
-+    /* Overriding of an existing definition must be explicitly requested. */
+     fdt_add_v2m_gic_node(vms);
-+    if (!(r->type & ARM_CP_OVERRIDE)) {
++    vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
-+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
+ }
-+        if (oldreg) {
-+            assert(oldreg->type & ARM_CP_OVERRIDE);
+ static void create_gic(VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ out:
  static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
                                              DeviceState *dev, Error **errp)
  {
 +    VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
 +
      if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
          virt_memory_pre_plug(hotplug_dev, dev, errp);
 +    } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
 +        hwaddr db_start = 0, db_end = 0;
 +        char *resv_prop_str;
 +
 +        switch (vms->msi_controller) {
 +        case VIRT_MSI_CTRL_NONE:
 +            return;
 +        case VIRT_MSI_CTRL_ITS:
 +            /* GITS_TRANSLATER page */
 +            db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
 +            db_end = base_memmap[VIRT_GIC_ITS].base +
 +                     base_memmap[VIRT_GIC_ITS].size - 1;
 +            break;
 +        case VIRT_MSI_CTRL_GICV2M:
 +            /* MSI_SETSPI_NS page */
 +            db_start = base_memmap[VIRT_GIC_V2M].base;
 +            db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
 +            break;
 +        }
-+    }
++        resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
 +                                        db_start, db_end,
 +                                        VIRTIO_IOMMU_RESV_MEM_T_MSI);
 +
-     /* Combine cpreg and name into one allocation. */
++        qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
-     name_len = strlen(name) + 1;
++        qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
-     r2 = g_malloc(sizeof(*r2) + name_len);
++        g_free(resv_prop_str);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          assert(!raw_accessors_invalid(r2));
      }
--    /* Overriding of an existing definition must be explicitly
--     * requested.
--     */
--    if (!(r->type & ARM_CP_OVERRIDE)) {
--        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
--        if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
--            fprintf(stderr, "Register redefined: cp=%d %d bit "
--                    "crn=%d crm=%d opc1=%d opc2=%d, "
--                    "was %s, now %s\n", r2->cp, 32 + 32 * is64,
--                    r2->crn, r2->crm, r2->opc1, r2->opc2,
--                    oldreg->name, r2->name);
--            g_assert_not_reached();
--        }
--    }
-     g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
  }
 --
-.25.1
+.20.1

-[PULL 07/23] target/arm: Avoid bare abort() or assert(0)
+[PULL 09/34] target/arm: kvm: Handle DABT with no valid ISS
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Beata Michalska <beata.michalska@linaro.org>
-Standardize on g_assert_not_reached() for "should not happen".
+On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
-Retain abort() when preceeded by fprintf or error_report.
+exception with no valid ISS info to be decoded. The lack of decode info
 makes it at least tricky to emulate those instruction which is one of the
 (many) reasons why KVM will not even try to do so.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Add support for handling those by requesting KVM to inject external
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+dabt into the quest.
-Message-id: 20220501055028.646596-7-richard.henderson@linaro.org
 Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
 Reviewed-by: Andrew Jones <drjones@redhat.com>
 Message-id: 20200629114110.30723-2-beata.michalska@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c         | 7 +++----
+ target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
- target/arm/hvf/hvf.c        | 2 +-
+file changed, 52 insertions(+)
  target/arm/kvm-stub.c       | 4 ++--
  target/arm/kvm.c            | 4 ++--
  target/arm/machine.c        | 4 ++--
  target/arm/translate-a64.c  | 4 ++--
  target/arm/translate-neon.c | 2 +-
  target/arm/translate.c      | 4 ++--
 files changed, 15 insertions(+), 16 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-             break;
-         default:
-             /* broken reginfo with out-of-range opc1 */
--            assert(false);
--            break;
-+            g_assert_not_reached();
-         }
-         /* assert our permissions are not too lax (stricter is fine) */
-         assert((r->access & ~mask) == 0);
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
-             break;
-         default:
-             /* Never happens, but compiler isn't smart enough to tell.  */
--            abort();
-+            g_assert_not_reached();
-         }
-     }
-     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
-             break;
-         default:
-             /* Never happens, but compiler isn't smart enough to tell.  */
--            abort();
-+            g_assert_not_reached();
-         }
-     }
-     if (domain_prot == 3) {
-diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/hvf/hvf.c
-+++ b/target/arm/hvf/hvf.c
-@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
-         /* we got kicked, no exit to process */
-         return 0;
-     default:
--        assert(0);
-+        g_assert_not_reached();
-     }
-     hvf_sync_vtimer(cpu);
-diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm-stub.c
-+++ b/target/arm/kvm-stub.c
-@@ -XXX,XX +XXX,XX @@
- bool write_kvmstate_to_list(ARMCPU *cpu)
- {
--    abort();
-+    g_assert_not_reached();
- }
- bool write_list_to_kvmstate(ARMCPU *cpu, int level)
- {
--    abort();
-+    g_assert_not_reached();
- }
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
-             ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
-             break;
+ static bool cap_has_mp_state;
-         default:
+ static bool cap_has_inject_serror_esr;
--            abort();
++static bool cap_has_inject_ext_dabt;
-+            g_assert_not_reached();
-         }
+ static ARMHostCPUFeatures arm_host_cpu_features;
-         if (ret) {
-             ok = false;
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
-@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
+         ret = -EINVAL;
              r.addr = (uintptr_t)(cpu->cpreg_values + i);
              break;
          default:
 -            abort();
 +            g_assert_not_reached();
          }
          ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
          if (ret) {
 diff --git a/target/arm/machine.c b/target/arm/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/machine.c
 +++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
      if (kvm_enabled()) {
          if (!write_kvmstate_to_list(cpu)) {
              /* This should never fail */
 -            abort();
 +            g_assert_not_reached();
          }
          /*
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
      } else {
          if (!write_cpustate_to_list(cpu, false)) {
              /* This should never fail. */
 -            abort();
 +            g_assert_not_reached();
          }
      }
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++    if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
-index XXXXXXX..XXXXXXX 100644
++        if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) {
---- a/target/arm/translate-a64.c
++            error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap");
-+++ b/target/arm/translate-a64.c
++        } else {
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
++            /* Set status for supporting the external dabt injection */
-         gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
++            cap_has_inject_ext_dabt = kvm_check_extension(s,
-         break;
++                                    KVM_CAP_ARM_INJECT_EXT_DABT);
-     default:
++        }
--        abort();
++    }
-+        g_assert_not_reached();
++
-     }
+     return ret;
+ }
-     write_fp_sreg(s, rd, tcg_res);
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
+@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
          break;
      }
      default:
 -        abort();
 +        g_assert_not_reached();
      }
  }
-diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
++/**
-index XXXXXXX..XXXXXXX 100644
++ * kvm_arm_handle_dabt_nisv:
---- a/target/arm/translate-neon.c
++ * @cs: CPUState
-+++ b/target/arm/translate-neon.c
++ * @esr_iss: ISS encoding (limited) for the exception from Data Abort
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
++ *           ISV bit set to '0b0' -> no valid instruction syndrome
-         }
++ * @fault_ipa: faulting address for the synchronous data abort
 + *
 + * Returns: 0 if the exception has been handled, < 0 otherwise
 + */
 +static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
 +                                    uint64_t fault_ipa)
 +{
 +    /*
 +     * Request KVM to inject the external data abort into the guest
 +     */
 +    if (cap_has_inject_ext_dabt) {
 +        struct kvm_vcpu_events events = { };
 +        /*
 +         * The external data abort event will be handled immediately by KVM
 +         * using the address fault that triggered the exit on given VCPU.
 +         * Requesting injection of the external data abort does not rely
 +         * on any other VCPU state. Therefore, in this particular case, the VCPU
 +         * synchronization can be exceptionally skipped.
 +         */
 +        events.exception.ext_dabt_pending = 1;
 +        /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
 +        return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
 +    } else {
 +        error_report("Data abort exception triggered by guest memory access "
 +                     "at physical address: 0x"  TARGET_FMT_lx,
 +                     (target_ulong)fault_ipa);
 +        error_printf("KVM unable to emulate faulting instruction.\n");
 +    }
 +    return -1;
 +}
 +
  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
              ret = EXCP_DEBUG;
          } /* otherwise return to guest */
          break;
++    case KVM_EXIT_ARM_NISV:
++        /* External DABT with no valid iss to decode */
++        ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss,
++                                       run->arm_nisv.fault_ipa);
++        break;
      default:
--        abort();
+         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
-+        g_assert_not_reached();
+                       __func__, run->exit_reason);
      }
      if ((vd + a->stride * (nregs - 1)) > 31) {
          /*
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
          offset = 4;
          break;
      default:
 -        abort();
 +        g_assert_not_reached();
      }
      tcg_gen_addi_i32(addr, addr, offset);
      tmp = load_reg(s, 14);
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
              offset = 0;
              break;
          default:
 -            abort();
 +            g_assert_not_reached();
          }
          tcg_gen_addi_i32(addr, addr, offset);
          gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
 --
-.25.1
+.20.1

-[PULL 21/23] target/arm: Add isar predicates for FEAT_Debugv8p2
+[PULL 10/34] target/arm: kvm: Handle misconfigured dabt injection
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Beata Michalska <beata.michalska@linaro.org>
 Injecting external data abort through KVM might trigger
 an issue on kernels that do not get updated to include the KVM fix.
 For those and aarch32 guests, the injected abort gets misconfigured
 to be an implementation defined exception. This leads to the guest
 repeatedly re-running the faulting instruction.
 Add support for handling that case.
 [
   Fixed-by: 018f22f95e8a
     ('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
   Fixed-by: 21aecdbd7f3a
     ('KVM: arm: Make inject_abt32() inject an external abort instead')
 ]
 Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
 Acked-by: Andrew Jones <drjones@redhat.com>
 Message-id: 20200629114110.30723-3-beata.michalska@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-24-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 15 +++++++++++++++
+ target/arm/cpu.h     |  2 ++
-file changed, 15 insertions(+)
+ target/arm/kvm_arm.h | 10 +++++++++
  target/arm/kvm.c     | 30 ++++++++++++++++++++++++++-
  target/arm/kvm32.c   | 34 ++++++++++++++++++++++++++++++
  target/arm/kvm64.c   | 49 ++++++++++++++++++++++++++++++++++++++++++++
 files changed, 124 insertions(+), 1 deletion(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
-     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
+         uint64_t esr;
      } serror;
 +    uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
 +
      /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
      uint32_t irq_line_state;
 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm_arm.h
 +++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_hw_debug_active(CPUState *cs);
  struct kvm_guest_debug_arch;
  void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
 +/**
 + * kvm_arm_verify_ext_dabt_pending:
 + * @cs: CPUState
 + *
 + * Verify the fault status code wrt the Ext DABT injection
 + *
 + * Returns: true if the fault status code is as expected, false otherwise
 + */
 +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
 +
  /**
   * its_class_name:
   *
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu)
  void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
  {
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +
 +    if (unlikely(env->ext_dabt_raised)) {
 +        /*
 +         * Verifying that the ext DABT has been properly injected,
 +         * otherwise risking indefinitely re-running the faulting instruction
 +         * Covering a very narrow case for kernels 5.5..5.5.4
 +         * when injected abort was misconfigured to be
 +         * an IMPLEMENTATION DEFINED exception (for 32-bit EL1)
 +         */
 +        if (!arm_feature(env, ARM_FEATURE_AARCH64) &&
 +            unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) {
 +
 +            error_report("Data abort exception with no valid ISS generated by "
 +                   "guest memory access. KVM unable to emulate faulting "
 +                   "instruction. Failed to inject an external data abort "
 +                   "into the guest.");
 +            abort();
 +       }
 +       /* Clear the status */
 +       env->ext_dabt_raised = 0;
 +    }
  }
-+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
+ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
  static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
                                      uint64_t fault_ipa)
  {
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
      /*
       * Request KVM to inject the external data abort into the guest
       */
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
           */
          events.exception.ext_dabt_pending = 1;
          /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
 -        return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
 +        if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) {
 +            env->ext_dabt_raised = 1;
 +            return 0;
 +        }
      } else {
          error_report("Data abort exception triggered by guest memory access "
                       "at physical address: 0x"  TARGET_FMT_lx,
 diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm32.c
 +++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
  {
      qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
  }
 +
 +#define ARM_REG_DFSR  ARM_CP15_REG32(0, 5, 0, 0)
 +#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
 +/*
 + *DFSR:
 + *      TTBCR.EAE == 0
 + *          FS[4]   - DFSR[10]
 + *          FS[3:0] - DFSR[3:0]
 + *      TTBCR.EAE == 1
 + *          FS, bits [5:0]
 + */
 +#define DFSR_FSC(lpae, v) \
 +    ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
 +
 +#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
 +
 +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
 +{
-+    return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
++    uint32_t dfsr_val;
 +
 +    if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
 +        ARMCPU *cpu = ARM_CPU(cs);
 +        CPUARMState *env = &cpu->env;
 +        uint32_t ttbcr;
 +        int lpae = 0;
 +
 +        if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
 +            lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
 +        }
 +        /* The verification is based on FS filed of the DFSR reg only*/
 +        return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
 +    }
 +    return false;
 +}
-+
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
- /*
+index XXXXXXX..XXXXXXX 100644
-  * 64-bit feature tests via id registers.
+--- a/target/arm/kvm64.c
-  */
++++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
-     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
      return false;
  }
++
-+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
++#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
 +#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
 +
 +/*
 + * ESR_EL1
 + * ISS encoding
 + * AARCH64: DFSC,   bits [5:0]
 + * AARCH32:
 + *      TTBCR.EAE == 0
 + *          FS[4]   - DFSR[10]
 + *          FS[3:0] - DFSR[3:0]
 + *      TTBCR.EAE == 1
 + *          FS, bits [5:0]
 + */
 +#define ESR_DFSC(aarch64, lpae, v)        \
 +    ((aarch64 || (lpae)) ? ((v) & 0x3F)   \
 +               : (((v) >> 6) | ((v) & 0x1F)))
 +
 +#define ESR_DFSC_EXTABT(aarch64, lpae) \
 +    ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
 +
 +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
 +{
-+    return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
++    uint64_t dfsr_val;
 +
 +    if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
 +        ARMCPU *cpu = ARM_CPU(cs);
 +        CPUARMState *env = &cpu->env;
 +        int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
 +        int lpae = 0;
 +
 +        if (!aarch64_mode) {
 +            uint64_t ttbcr;
 +
 +            if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
 +                lpae = arm_feature(env, ARM_FEATURE_LPAE)
 +                        && (ttbcr & TTBCR_EAE);
 +            }
 +        }
 +        /*
 +         * The verification here is based on the DFSC bits
 +         * of the ESR_EL1 reg only
 +         */
 +         return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
 +                ESR_DFSC_EXTABT(aarch64_mode, lpae));
 +    }
 +    return false;
 +}
-+
- static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
- {
-     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
-     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
- }
-+static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
-+{
-+    return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
-+}
-+
- /*
-  * Forward to the above feature tests given an ARMCPU pointer.
-  */
 --
-.25.1
+.20.1

-[PULL 23/23] target/arm: read access to performance counters from EL0
+[PULL 11/34] tests/acpi: remove stale allowed tables
-From: Alex Zuepke <alex.zuepke@tum.de>
+From: Andrew Jones <drjones@redhat.com>
-The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
+Fixes: 93dd625f8bf7 ("tests/acpi: update expected data files")
-to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.
+Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
+Message-id: 20200629140938.17566-2-drjones@redhat.com
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 4 ++--
+ tests/qtest/bios-tables-test-allowed-diff.h | 18 ------------------
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 18 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
-+++ b/target/arm/helper.c
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
-@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
+@@ -1,19 +1 @@
-               .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
+ /* List of comma-separated changed AML files to ignore */
-               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+-"tests/data/acpi/pc/DSDT",
-               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
+-"tests/data/acpi/pc/DSDT.acpihmat",
--              .accessfn = pmreg_access },
+-"tests/data/acpi/pc/DSDT.bridge",
-+              .accessfn = pmreg_access_xevcntr },
+-"tests/data/acpi/pc/DSDT.cphp",
-             { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
+-"tests/data/acpi/pc/DSDT.dimmpxm",
-               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
+-"tests/data/acpi/pc/DSDT.ipmikcs",
--              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+-"tests/data/acpi/pc/DSDT.memhp",
-+              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
+-"tests/data/acpi/pc/DSDT.numamem",
-               .type = ARM_CP_IO,
+-"tests/data/acpi/q35/DSDT",
-               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
+-"tests/data/acpi/q35/DSDT.acpihmat",
-               .raw_readfn = pmevcntr_rawread,
+-"tests/data/acpi/q35/DSDT.bridge",
 -"tests/data/acpi/q35/DSDT.cphp",
 -"tests/data/acpi/q35/DSDT.dimmpxm",
 -"tests/data/acpi/q35/DSDT.ipmibt",
 -"tests/data/acpi/q35/DSDT.memhp",
 -"tests/data/acpi/q35/DSDT.mmio64",
 -"tests/data/acpi/q35/DSDT.numamem",
 -"tests/data/acpi/q35/DSDT.tis",
 --
-.25.1
+.20.1

-[PULL 11/23] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
+[PULL 12/34] tests/acpi: virt: allow DSDT acpi table changes
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-The new_key field is always non-zero -- drop the if.
+Signed-off-by: Andrew Jones <drjones@redhat.com>
+Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20200629140938.17566-3-drjones@redhat.com
 Message-id: 20220501055028.646596-11-richard.henderson@linaro.org
 [PMM: reinstated dropped PL3_RW mask]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 23 +++++++++++------------
+ tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
-file changed, 11 insertions(+), 12 deletions(-)
+file changed, 3 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
-+++ b/target/arm/helper.c
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
+@@ -1 +1,4 @@
+ /* List of comma-separated changed AML files to ignore */
-     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
++"tests/data/acpi/virt/DSDT",
-         const struct E2HAlias *a = &aliases[i];
++"tests/data/acpi/virt/DSDT.memhp",
--        ARMCPRegInfo *src_reg, *dst_reg;
++"tests/data/acpi/virt/DSDT.numamem",
 +        ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
 +        uint32_t *new_key;
 +        bool ok;
          if (a->feature && !a->feature(&cpu->isar)) {
              continue;
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
          g_assert(src_reg->opaque == NULL);
          /* Create alias before redirection so we dup the right data. */
 -        if (a->new_key) {
 -            ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
 -            uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
 -            bool ok;
 +        new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
 +        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
 -            new_reg->name = a->new_name;
 -            new_reg->type |= ARM_CP_ALIAS;
 -            /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
 -            new_reg->access &= PL2_RW | PL3_RW;
 +        new_reg->name = a->new_name;
 +        new_reg->type |= ARM_CP_ALIAS;
 +        /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
 +        new_reg->access &= PL2_RW | PL3_RW;
 -            ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
 -            g_assert(ok);
 -        }
 +        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
 +        g_assert(ok);
          src_reg->opaque = dst_reg;
          src_reg->orig_readfn = src_reg->readfn ?: raw_read;
 --
-.25.1
+.20.1

-[PULL 20/23] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
+[PULL 13/34] hw/arm/virt-acpi-build: Only expose flash on older machine types
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-Since e03b56863d2bc, our host endian indicator is unconditionally
+The flash device is exclusively for the host-controlled firmware, so
-set, which means that we can use a normal C condition.
+we should not expose it to the OS. Exposing it risks the OS messing
 with it, which could break firmware runtime services and surprise the
 OS when all its changes disappear after reboot.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+As firmware needs the device and uses DT, we leave the device exposed
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+there. It's up to firmware to remove the nodes from DT before sending
-Message-id: 20220501055028.646596-20-richard.henderson@linaro.org
+it on to the OS. However, there's no need to force firmware to remove
-[PMM: quote correct git hash in commit message]
+tables from ACPI (which it doesn't know how to do anyway), so we
 simply don't add the tables in the first place. But, as we've been
 adding the tables for quite some time and don't want to change the
 default hardware exposed to versioned machines, then we only stop
 exposing the flash device tables for 5.1 and later machine types.
 Suggested-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
 Suggested-by: Laszlo Ersek <lersek@redhat.com>
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 Message-id: 20200629140938.17566-4-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 9 +++------
+ include/hw/arm/virt.h    | 1 +
-file changed, 3 insertions(+), 6 deletions(-)
+ hw/arm/virt-acpi-build.c | 5 ++++-
  hw/arm/virt.c            | 3 +++
 files changed, 8 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/include/hw/arm/virt.h
-+++ b/target/arm/helper.c
++++ b/include/hw/arm/virt.h
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ typedef struct {
-             r2->type |= ARM_CP_ALIAS;
+     bool no_highmem_ecam;
-         }
+     bool no_ged;   /* Machines < 4.2 has no support for ACPI GED device */
+     bool kvm_no_adjvtime;
--        if (r->state == ARM_CP_STATE_BOTH) {
++    bool acpi_expose_flash;
--#if HOST_BIG_ENDIAN
+ } VirtMachineClass;
--            if (r2->fieldoffset) {
--                r2->fieldoffset += sizeof(uint32_t);
+ typedef struct {
--            }
+diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
--#endif
+index XXXXXXX..XXXXXXX 100644
-+        if (HOST_BIG_ENDIAN &&
+--- a/hw/arm/virt-acpi-build.c
-+            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
++++ b/hw/arm/virt-acpi-build.c
-+            r2->fieldoffset += sizeof(uint32_t);
+@@ -XXX,XX +XXX,XX @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
-         }
+ static void
-     }
+ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
  {
 +    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
      Aml *scope, *dsdt;
      MachineState *ms = MACHINE(vms);
      const MemMapEntry *memmap = vms->memmap;
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
      acpi_dsdt_add_cpus(scope, vms->smp_cpus);
      acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
                         (irqmap[VIRT_UART] + ARM_SPI_BASE));
 -    acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
 +    if (vmc->acpi_expose_flash) {
 +        acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
 +    }
      acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
      acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
                      (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
  static void virt_machine_5_0_options(MachineClass *mc)
  {
 +    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
 +
      virt_machine_5_1_options(mc);
      compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
      mc->numa_mem_supported = true;
 +    vmc->acpi_expose_flash = true;
  }
  DEFINE_VIRT_MACHINE(5, 0)
 --
-.25.1
+.20.1

-[PULL 08/23] target/arm: Change cpreg access permissions to enum
+[PULL 14/34] tests/acpi: virt: update golden masters for DSDT
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-Create a typedef as well, and use it in ARMCPRegInfo.
+Differences between disassembled ASL files for DSDT:
 This won't be perfect for debugging, but it'll nicely
 display the most common cases.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+@@ -XXX,XX +XXX,XX @@
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+  *
-Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
+  * Disassembling to symbolic ASL+ operators
   *
 - * Disassembly of a, Mon Jun 29 09:50:01 2020
 + * Disassembly of b, Mon Jun 29 09:50:03 2020
   *
   * Original Table Header:
   *     Signature        "DSDT"
 - *     Length           0x000014BB (5307)
 + *     Length           0x00001455 (5205)
   *     Revision         0x02
 - *     Checksum         0xD1
 + *     Checksum         0xE1
   *     OEM ID           "BOCHS "
   *     OEM Table ID     "BXPCDSDT"
   *     OEM Revision     0x00000001 (1)
@@ -XXX,XX +XXX,XX @@
              })
          }
 -        Device (FLS0)
 -        {
 -            Name (_HID, "LNRO0015")  // _HID: Hardware ID
 -            Name (_UID, Zero)  // _UID: Unique ID
 -            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
 -            {
 -                Memory32Fixed (ReadWrite,
 -                    0x00000000,         // Address Base
 -                    0x04000000,         // Address Length
 -                    )
 -            })
 -        }
 -
 -        Device (FLS1)
 -        {
 -            Name (_HID, "LNRO0015")  // _HID: Hardware ID
 -            Name (_UID, One)  // _UID: Unique ID
 -            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
 -            {
 -                Memory32Fixed (ReadWrite,
 -                    0x04000000,         // Address Base
 -                    0x04000000,         // Address Length
 -                    )
 -            })
 -        }
 -
          Device (FWCF)
          {
              Name (_HID, "QEMU0002")  // _HID: Hardware ID
 The other two binaries have the same changes (the removal of the
 flash devices).
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 Message-id: 20200629140938.17566-5-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h | 44 +++++++++++++++++++++++---------------------
+ tests/qtest/bios-tables-test-allowed-diff.h |   3 ---
- target/arm/helper.c |  2 +-
+ tests/data/acpi/virt/DSDT                   | Bin 5307 -> 5205 bytes
-files changed, 24 insertions(+), 22 deletions(-)
+ tests/data/acpi/virt/DSDT.memhp             | Bin 6668 -> 6566 bytes
  tests/data/acpi/virt/DSDT.numamem           | Bin 5307 -> 5205 bytes
 files changed, 3 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
-+++ b/target/arm/cpregs.h
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -1,4 +1 @@
-  * described with these bits, then use a laxer set of restrictions, and
+ /* List of comma-separated changed AML files to ignore */
-  * do the more restrictive/complex check inside a helper function.
+-"tests/data/acpi/virt/DSDT",
-  */
+-"tests/data/acpi/virt/DSDT.memhp",
--#define PL3_R 0x80
+-"tests/data/acpi/virt/DSDT.numamem",
--#define PL3_W 0x40
+diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT
 -#define PL2_R (0x20 | PL3_R)
 -#define PL2_W (0x10 | PL3_W)
 -#define PL1_R (0x08 | PL2_R)
 -#define PL1_W (0x04 | PL2_W)
 -#define PL0_R (0x02 | PL1_R)
 -#define PL0_W (0x01 | PL1_W)
 +typedef enum {
 +    PL3_R = 0x80,
 +    PL3_W = 0x40,
 +    PL2_R = 0x20 | PL3_R,
 +    PL2_W = 0x10 | PL3_W,
 +    PL1_R = 0x08 | PL2_R,
 +    PL1_W = 0x04 | PL2_W,
 +    PL0_R = 0x02 | PL1_R,
 +    PL0_W = 0x01 | PL1_W,
 -/*
 - * For user-mode some registers are accessible to EL0 via a kernel
 - * trap-and-emulate ABI. In this case we define the read permissions
 - * as actually being PL0_R. However some bits of any given register
 - * may still be masked.
 - */
 +    /*
 +     * For user-mode some registers are accessible to EL0 via a kernel
 +     * trap-and-emulate ABI. In this case we define the read permissions
 +     * as actually being PL0_R. However some bits of any given register
 +     * may still be masked.
 +     */
  #ifdef CONFIG_USER_ONLY
 -#define PL0U_R PL0_R
 +    PL0U_R = PL0_R,
  #else
 -#define PL0U_R PL1_R
 +    PL0U_R = PL1_R,
  #endif
 -#define PL3_RW (PL3_R | PL3_W)
 -#define PL2_RW (PL2_R | PL2_W)
 -#define PL1_RW (PL1_R | PL1_W)
 -#define PL0_RW (PL0_R | PL0_W)
 +    PL3_RW = PL3_R | PL3_W,
 +    PL2_RW = PL2_R | PL2_W,
 +    PL1_RW = PL1_R | PL1_W,
 +    PL0_RW = PL0_R | PL0_W,
 +} CPAccessRights;
  typedef enum CPAccessResult {
      /* Access is permitted */
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
      /* Register type: ARM_CP_* bits/values */
      int type;
      /* Access rights: PL*_[RW] */
 -    int access;
 +    CPAccessRights access;
      /* Security state: ARM_CP_SECSTATE_* bits/values */
      int secure;
      /*
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+GIT binary patch
-+++ b/target/arm/helper.c
+delta 28
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a
-      * to encompass the generic architectural permission check.
-      */
+delta 156
-     if (r->state != ARM_CP_STATE_AA32) {
+zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
--        int mask = 0;
+zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
-+        CPAccessRights mask;
+LaERl^1zUvy_;n(J
-         switch (r->opc1) {
-         case 0:
+diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
-             /* min_EL EL1, but some accessible to EL0 via kernel ABI */
+index XXXXXXX..XXXXXXX 100644
 GIT binary patch
 delta 28
 kcmeA%S!T@T66_MPOp<|tiD@F2G*jb@iRuX(-^xn@0CHUjRR910
 delta 156
 zcmZ2x++)J!66_MfBgMeL^l>7WG*kP$iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^
 zE<n;bC|FRCi?5B7fsp|MSSlH!n?PC&v1wsM*TMqS1=eEW7Vhi@(GuwD8){%+U<5Qj
 LIK*+|0yaqism~!^
 diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem
 index XXXXXXX..XXXXXXX 100644
 GIT binary patch
 delta 28
 kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a
 delta 156
 zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
 zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
 LaERl^1zUvy_;n(J
 --
-.25.1
+.20.1

-[PULL 06/23] target/arm: Reorg ARMCPRegInfo type field bits
+[PULL 15/34] target/arm: Fix temp double-free in sve ldr/str
 From: Richard Henderson <richard.henderson@linaro.org>
-Instead of defining ARM_CP_FLAG_MASK to remove flags,
+The temp that gets assigned to clean_addr has been allocated with
-define ARM_CP_SPECIAL_MASK to isolate special cases.
+new_tmp_a64, which means that it will be freed at the end of the
-Sort the specials to the low bits. Use an enum.
+instruction.  Freeing it earlier leads to assertion failure.
-Split the large comment block so as to document each
+The loop creates a complication, in which we allocate a new local
-value separately.
+temp, which does need freeing, and the final code path is shared
 between the loop and non-loop.
+Fix this complication by adding new_tmp_a64_local so that the new
+local temp is freed at the end, and can be treated exactly like
+the non-loop path.
+Fixes: bba87d0a0f4
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20220501055028.646596-6-richard.henderson@linaro.org
+Message-id: 20200702175605.1987125-1-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpregs.h        | 130 +++++++++++++++++++++++--------------
+ target/arm/translate-a64.h | 1 +
- target/arm/cpu.c           |   4 +-
+ target/arm/translate-a64.c | 6 ++++++
- target/arm/helper.c        |   4 +-
+ target/arm/translate-sve.c | 8 ++------
- target/arm/translate-a64.c |   6 +-
+files changed, 9 insertions(+), 6 deletions(-)
  target/arm/translate.c     |   6 +-
 files changed, 92 insertions(+), 58 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/target/arm/translate-a64.h
-+++ b/target/arm/cpregs.h
++++ b/target/arm/translate-a64.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
- #define TARGET_ARM_CPREGS_H
+     } while (0)
- /*
+ TCGv_i64 new_tmp_a64(DisasContext *s);
-- * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
++TCGv_i64 new_tmp_a64_local(DisasContext *s);
-- * special-behaviour cp reg and bits [11..8] indicate what behaviour
+ TCGv_i64 new_tmp_a64_zero(DisasContext *s);
-- * it has. Otherwise it is a simple cp reg, where CONST indicates that
+ TCGv_i64 cpu_reg(DisasContext *s, int reg);
-- * TCG can assume the value to be constant (ie load at translate time)
+ TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
 - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 - * indicates that the TB should not be ended after a write to this register
 - * (the default is that the TB ends after cp writes). OVERRIDE permits
 - * a register definition to override a previous definition for the
 - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 - * old must have the OVERRIDE bit set.
 - * ALIAS indicates that this register is an alias view of some underlying
 - * state which is also visible via another register, and that the other
 - * register is handling migration and reset; registers marked ALIAS will not be
 - * migrated but may have their state set by syncing of register state from KVM.
 - * NO_RAW indicates that this register has no underlying state and does not
 - * support raw access for state saving/loading; it will not be used for either
 - * migration or KVM state synchronization. (Typically this is for "registers"
 - * which are actually used as instructions for cache maintenance and so on.)
 - * IO indicates that this register does I/O and therefore its accesses
 - * need to be marked with gen_io_start() and also end the TB. In particular,
 - * registers which implement clocks or timers require this.
 - * RAISES_EXC is for when the read or write hook might raise an exception;
 - * the generated code will synchronize the CPU state before calling the hook
 - * so that it is safe for the hook to call raise_exception().
 - * NEWEL is for writes to registers that might change the exception
 - * level - typically on older ARM chips. For those cases we need to
 - * re-read the new el when recomputing the translation flags.
 + * ARMCPRegInfo type field bits:
   */
 -#define ARM_CP_SPECIAL           0x0001
 -#define ARM_CP_CONST             0x0002
 -#define ARM_CP_64BIT             0x0004
 -#define ARM_CP_SUPPRESS_TB_END   0x0008
 -#define ARM_CP_OVERRIDE          0x0010
 -#define ARM_CP_ALIAS             0x0020
 -#define ARM_CP_IO                0x0040
 -#define ARM_CP_NO_RAW            0x0080
 -#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
 -#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
 -#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
 -#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
 -#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
 -#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
 -#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
 -#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
 -#define ARM_CP_FPU               0x1000
 -#define ARM_CP_SVE               0x2000
 -#define ARM_CP_NO_GDB            0x4000
 -#define ARM_CP_RAISES_EXC        0x8000
 -#define ARM_CP_NEWEL             0x10000
 -/* Mask of only the flag bits in a type field */
 -#define ARM_CP_FLAG_MASK         0x1f0ff
 +enum {
 +    /*
 +     * Register must be handled specially during translation.
 +     * The method is one of the values below:
 +     */
 +    ARM_CP_SPECIAL_MASK          = 0x000f,
 +    /* Special: no change to PE state: writes ignored, reads ignored. */
 +    ARM_CP_NOP                   = 0x0001,
 +    /* Special: sysreg is WFI, for v5 and v6. */
 +    ARM_CP_WFI                   = 0x0002,
 +    /* Special: sysreg is NZCV. */
 +    ARM_CP_NZCV                  = 0x0003,
 +    /* Special: sysreg is CURRENTEL. */
 +    ARM_CP_CURRENTEL             = 0x0004,
 +    /* Special: sysreg is DC ZVA or similar. */
 +    ARM_CP_DC_ZVA                = 0x0005,
 +    ARM_CP_DC_GVA                = 0x0006,
 +    ARM_CP_DC_GZVA               = 0x0007,
 +
 +    /* Flag: reads produce resetvalue; writes ignored. */
 +    ARM_CP_CONST                 = 1 << 4,
 +    /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
 +    ARM_CP_64BIT                 = 1 << 5,
 +    /*
 +     * Flag: TB should not be ended after a write to this register
 +     * (the default is that the TB ends after cp writes).
 +     */
 +    ARM_CP_SUPPRESS_TB_END       = 1 << 6,
 +    /*
 +     * Flag: Permit a register definition to override a previous definition
 +     * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new
 +     * or the old must have the ARM_CP_OVERRIDE bit set.
 +     */
 +    ARM_CP_OVERRIDE              = 1 << 7,
 +    /*
 +     * Flag: Register is an alias view of some underlying state which is also
 +     * visible via another register, and that the other register is handling
 +     * migration and reset; registers marked ARM_CP_ALIAS will not be migrated
 +     * but may have their state set by syncing of register state from KVM.
 +     */
 +    ARM_CP_ALIAS                 = 1 << 8,
 +    /*
 +     * Flag: Register does I/O and therefore its accesses need to be marked
 +     * with gen_io_start() and also end the TB. In particular, registers which
 +     * implement clocks or timers require this.
 +     */
 +    ARM_CP_IO                    = 1 << 9,
 +    /*
 +     * Flag: Register has no underlying state and does not support raw access
 +     * for state saving/loading; it will not be used for either migration or
 +     * KVM state synchronization. Typically this is for "registers" which are
 +     * actually used as instructions for cache maintenance and so on.
 +     */
 +    ARM_CP_NO_RAW                = 1 << 10,
 +    /*
 +     * Flag: The read or write hook might raise an exception; the generated
 +     * code will synchronize the CPU state before calling the hook so that it
 +     * is safe for the hook to call raise_exception().
 +     */
 +    ARM_CP_RAISES_EXC            = 1 << 11,
 +    /*
 +     * Flag: Writes to the sysreg might change the exception level - typically
 +     * on older ARM chips. For those cases we need to re-read the new el when
 +     * recomputing the translation flags.
 +     */
 +    ARM_CP_NEWEL                 = 1 << 12,
 +    /*
 +     * Flag: Access check for this sysreg is identical to accessing FPU state
 +     * from an instruction: use translation fp_access_check().
 +     */
 +    ARM_CP_FPU                   = 1 << 13,
 +    /*
 +     * Flag: Access check for this sysreg is identical to accessing SVE state
 +     * from an instruction: use translation sve_access_check().
 +     */
 +    ARM_CP_SVE                   = 1 << 14,
 +    /* Flag: Do not expose in gdb sysreg xml. */
 +    ARM_CP_NO_GDB                = 1 << 15,
 +};
  /*
   * Valid values for ARMCPRegInfo state field, indicating which of
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
      ARMCPRegInfo *ri = value;
      ARMCPU *cpu = opaque;
 -    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
 +    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
      ARMCPU *cpu = opaque;
      uint64_t oldvalue, newvalue;
 -    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 +    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
          return;
      }
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
       * multiple times. Special registers (ie NOP/WFI) are
       * never migratable and not even raw-accessible.
       */
 -    if ((r->type & ARM_CP_SPECIAL)) {
 +    if (r->type & ARM_CP_SPECIAL_MASK) {
          r2->type |= ARM_CP_NO_RAW;
      }
      if (((r->crm == CP_ANY) && crm != 0) ||
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      /* Check that the register definition has enough info to handle
       * reads and writes if they are permitted.
       */
 -    if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
 +    if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
          if (r->access & PL3_R) {
              assert((r->fieldoffset ||
                     (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
+@@ -XXX,XX +XXX,XX @@ TCGv_i64 new_tmp_a64(DisasContext *s)
      return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
  }
 +TCGv_i64 new_tmp_a64_local(DisasContext *s)
 +{
 +    assert(s->tmp_a64_count < TMP_A64_MAX);
 +    return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64();
 +}
 +
  TCGv_i64 new_tmp_a64_zero(DisasContext *s)
  {
      TCGv_i64 t = new_tmp_a64(s);
 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-sve.c
 +++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          /* Copy the clean address into a local temp, live across the loop. */
          t0 = clean_addr;
 -        clean_addr = tcg_temp_local_new_i64();
 +        clean_addr = new_tmp_a64_local(s);
          tcg_gen_mov_i64(clean_addr, t0);
 -        tcg_temp_free_i64(t0);
          gen_set_label(loop);
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
          tcg_temp_free_i64(t0);
      }
+-    tcg_temp_free_i64(clean_addr);
-     /* Handle special cases first */
+ }
--    switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
-+    switch (ri->type & ARM_CP_SPECIAL_MASK) {
+ /* Similarly for stores.  */
-+    case 0:
+@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
-+        break;
-     case ARM_CP_NOP:
+         /* Copy the clean address into a local temp, live across the loop. */
-         return;
+         t0 = clean_addr;
-     case ARM_CP_NZCV:
+-        clean_addr = tcg_temp_local_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
++        clean_addr = new_tmp_a64_local(s);
          tcg_gen_mov_i64(clean_addr, t0);
 -        tcg_temp_free_i64(t0);
          gen_set_label(loop);
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          }
-         return;
+         tcg_temp_free_i64(t0);
      default:
 -        break;
 +        g_assert_not_reached();
      }
-     if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
+-    tcg_temp_free_i64(clean_addr);
-         return;
+ }
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
+ static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
          }
          /* Handle special cases first */
 -        switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
 +        switch (ri->type & ARM_CP_SPECIAL_MASK) {
 +        case 0:
 +            break;
          case ARM_CP_NOP:
              return;
          case ARM_CP_WFI:
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
              s->base.is_jmp = DISAS_WFI;
              return;
          default:
 -            break;
 +            g_assert_not_reached();
          }
          if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
 --
-.25.1
+.20.1

-New patch
+[PULL 16/34] hw/display/bcm2835_fb.c: Initialize all fields of struct
+In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we
+pass a pointer to a local struct to another function without
+initializing all its fields.  This is a real bug:
+bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig
+struct into s->config, so any fields we don't initialize will corrupt
+the state of the device.
+Copy the two fields which we don't want to update (pixo and alpha)
+from the existing config so we don't accidentally change them.
+Fixes: cfb7ba983857e40e88
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200628195436.27582-1-peter.maydell@linaro.org
+---
+ hw/display/bcm2835_fb.c | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/display/bcm2835_fb.c
++++ b/hw/display/bcm2835_fb.c
+@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
+     newconf.base = s->vcram_base | (value & 0xc0000000);
+     newconf.base += BCM2835_FB_OFFSET;
++    /* Copy fields which we don't want to change from the existing config */
++    newconf.pixo = s->config.pixo;
++    newconf.alpha = s->config.alpha;
++
+     bcm2835_fb_validate_config(&newconf);
+     pitch = bcm2835_fb_get_pitch(&newconf);
+--
+.20.1

-New patch
+[PULL 17/34] hw/arm/spitz: Detabify
+The spitz board has been around a long time, and still has a fair number
 of hard-coded tab characters in it. We're about to do some work on
 this source file, so start out by expanding out the tabs.
 This commit is a pure whitespace only change.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20200628142429.17111-2-peter.maydell@linaro.org
 ---
  hw/arm/spitz.c | 156 ++++++++++++++++++++++++-------------------------
 file changed, 78 insertions(+), 78 deletions(-)
 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/spitz.c
 +++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
  #include "cpu.h"
  #undef REG_FMT
 -#define REG_FMT            "0x%02lx"
 +#define REG_FMT                         "0x%02lx"
  /* Spitz Flash */
 -#define FLASH_BASE        0x0c000000
 -#define FLASH_ECCLPLB        0x00    /* Line parity 7 - 0 bit */
 -#define FLASH_ECCLPUB        0x04    /* Line parity 15 - 8 bit */
 -#define FLASH_ECCCP        0x08    /* Column parity 5 - 0 bit */
 -#define FLASH_ECCCNTR        0x0c    /* ECC byte counter */
 -#define FLASH_ECCCLRR        0x10    /* Clear ECC */
 -#define FLASH_FLASHIO        0x14    /* Flash I/O */
 -#define FLASH_FLASHCTL        0x18    /* Flash Control */
 +#define FLASH_BASE              0x0c000000
 +#define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
 +#define FLASH_ECCLPUB           0x04    /* Line parity 15 - 8 bit */
 +#define FLASH_ECCCP             0x08    /* Column parity 5 - 0 bit */
 +#define FLASH_ECCCNTR           0x0c    /* ECC byte counter */
 +#define FLASH_ECCCLRR           0x10    /* Clear ECC */
 +#define FLASH_FLASHIO           0x14    /* Flash I/O */
 +#define FLASH_FLASHCTL          0x18    /* Flash Control */
 -#define FLASHCTL_CE0        (1 << 0)
 -#define FLASHCTL_CLE        (1 << 1)
 -#define FLASHCTL_ALE        (1 << 2)
 -#define FLASHCTL_WP        (1 << 3)
 -#define FLASHCTL_CE1        (1 << 4)
 -#define FLASHCTL_RYBY        (1 << 5)
 -#define FLASHCTL_NCE        (FLASHCTL_CE0 | FLASHCTL_CE1)
 +#define FLASHCTL_CE0            (1 << 0)
 +#define FLASHCTL_CLE            (1 << 1)
 +#define FLASHCTL_ALE            (1 << 2)
 +#define FLASHCTL_WP             (1 << 3)
 +#define FLASHCTL_CE1            (1 << 4)
 +#define FLASHCTL_RYBY           (1 << 5)
 +#define FLASHCTL_NCE            (FLASHCTL_CE0 | FLASHCTL_CE1)
  #define TYPE_SL_NAND "sl-nand"
  #define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
      int ryby;
      switch (addr) {
 -#define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
 +#define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
      case FLASH_ECCLPLB:
          return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
                  BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
 -#define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
 +#define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
      case FLASH_ECCLPUB:
          return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
                  BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
@@ -XXX,XX +XXX,XX @@ static void sl_nand_realize(DeviceState *dev, Error **errp)
  /* Spitz Keyboard */
 -#define SPITZ_KEY_STROBE_NUM    11
 -#define SPITZ_KEY_SENSE_NUM    7
 +#define SPITZ_KEY_STROBE_NUM    11
 +#define SPITZ_KEY_SENSE_NUM     7
  static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
 , 17, 91, 34, 36, 38, 39
@@ -XXX,XX +XXX,XX @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
      { 0x52, 0x43, 0x01, 0x47, 0x49,  -1 ,  -1 ,  -1 ,  -1 ,  -1 ,  -1  },
  };
 -#define SPITZ_GPIO_AK_INT    13    /* Remote control */
 -#define SPITZ_GPIO_SYNC        16    /* Sync button */
 -#define SPITZ_GPIO_ON_KEY    95    /* Power button */
 -#define SPITZ_GPIO_SWA        97    /* Lid */
 -#define SPITZ_GPIO_SWB        96    /* Tablet mode */
 +#define SPITZ_GPIO_AK_INT       13      /* Remote control */
 +#define SPITZ_GPIO_SYNC                 16      /* Sync button */
 +#define SPITZ_GPIO_ON_KEY       95      /* Power button */
 +#define SPITZ_GPIO_SWA          97      /* Lid */
 +#define SPITZ_GPIO_SWB          96      /* Tablet mode */
  /* The special buttons are mapped to unused keys */
  static const int spitz_gpiomap[5] = {
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
  #define SPITZ_MOD_CTRL    (1 << 8)
  #define SPITZ_MOD_FN      (1 << 9)
 -#define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
 +#define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
  static void spitz_keyboard_handler(void *opaque, int keycode)
  {
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_handler(void *opaque, int keycode)
      uint16_t code;
      int mapcode;
      switch (keycode) {
 -    case 0x2a:    /* Left Shift */
 +    case 0x2a:  /* Left Shift */
          s->modifiers |= 1;
          break;
      case 0xaa:
          s->modifiers &= ~1;
          break;
 -    case 0x36:    /* Right Shift */
 +    case 0x36:  /* Right Shift */
          s->modifiers |= 2;
          break;
      case 0xb6:
          s->modifiers &= ~2;
          break;
 -    case 0x1d:    /* Control */
 +    case 0x1d:  /* Control */
          s->modifiers |= 4;
          break;
      case 0x9d:
          s->modifiers &= ~4;
          break;
 -    case 0x38:    /* Alt */
 +    case 0x38:  /* Alt */
          s->modifiers |= 8;
          break;
      case 0xb8:
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
  /* LCD backlight controller */
 -#define LCDTG_RESCTL    0x00
 -#define LCDTG_PHACTRL    0x01
 -#define LCDTG_DUTYCTRL    0x02
 -#define LCDTG_POWERREG0    0x03
 -#define LCDTG_POWERREG1    0x04
 -#define LCDTG_GPOR3    0x05
 -#define LCDTG_PICTRL    0x06
 -#define LCDTG_POLCTRL    0x07
 +#define LCDTG_RESCTL    0x00
 +#define LCDTG_PHACTRL   0x01
 +#define LCDTG_DUTYCTRL  0x02
 +#define LCDTG_POWERREG0         0x03
 +#define LCDTG_POWERREG1         0x04
 +#define LCDTG_GPOR3     0x05
 +#define LCDTG_PICTRL    0x06
 +#define LCDTG_POLCTRL   0x07
  typedef struct {
      SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
  /* SSP devices */
 -#define CORGI_SSP_PORT        2
 +#define CORGI_SSP_PORT          2
 -#define SPITZ_GPIO_LCDCON_CS    53
 -#define SPITZ_GPIO_ADS7846_CS    14
 -#define SPITZ_GPIO_MAX1111_CS    20
 -#define SPITZ_GPIO_TP_INT    11
 +#define SPITZ_GPIO_LCDCON_CS    53
 +#define SPITZ_GPIO_ADS7846_CS   14
 +#define SPITZ_GPIO_MAX1111_CS   20
 +#define SPITZ_GPIO_TP_INT       11
  static DeviceState *max1111;
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
      s->enable[line] = !level;
  }
 -#define MAX1111_BATT_VOLT    1
 -#define MAX1111_BATT_TEMP    2
 -#define MAX1111_ACIN_VOLT    3
 +#define MAX1111_BATT_VOLT       1
 +#define MAX1111_BATT_TEMP       2
 +#define MAX1111_ACIN_VOLT       3
 -#define SPITZ_BATTERY_TEMP    0xe0    /* About 2.9V */
 -#define SPITZ_BATTERY_VOLT    0xd0    /* About 4.0V */
 -#define SPITZ_CHARGEON_ACIN    0x80    /* About 5.0V */
 +#define SPITZ_BATTERY_TEMP      0xe0    /* About 2.9V */
 +#define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
 +#define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
  static void spitz_adc_temp_on(void *opaque, int line, int level)
  {
@@ -XXX,XX +XXX,XX @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
  /* Wm8750 and Max7310 on I2C */
 -#define AKITA_MAX_ADDR    0x18
 -#define SPITZ_WM_ADDRL    0x1b
 -#define SPITZ_WM_ADDRH    0x1a
 +#define AKITA_MAX_ADDR  0x18
 +#define SPITZ_WM_ADDRL  0x1b
 +#define SPITZ_WM_ADDRH  0x1a
 -#define SPITZ_GPIO_WM    5
 +#define SPITZ_GPIO_WM   5
  static void spitz_wm8750_addr(void *opaque, int line, int level)
  {
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
      }
  }
 -#define SPITZ_SCP_LED_GREEN        1
 -#define SPITZ_SCP_JK_B            2
 -#define SPITZ_SCP_CHRG_ON        3
 -#define SPITZ_SCP_MUTE_L        4
 -#define SPITZ_SCP_MUTE_R        5
 -#define SPITZ_SCP_CF_POWER        6
 -#define SPITZ_SCP_LED_ORANGE        7
 -#define SPITZ_SCP_JK_A            8
 -#define SPITZ_SCP_ADC_TEMP_ON        9
 -#define SPITZ_SCP2_IR_ON        1
 -#define SPITZ_SCP2_AKIN_PULLUP        2
 -#define SPITZ_SCP2_BACKLIGHT_CONT    7
 -#define SPITZ_SCP2_BACKLIGHT_ON        8
 -#define SPITZ_SCP2_MIC_BIAS        9
 +#define SPITZ_SCP_LED_GREEN             1
 +#define SPITZ_SCP_JK_B                  2
 +#define SPITZ_SCP_CHRG_ON               3
 +#define SPITZ_SCP_MUTE_L                4
 +#define SPITZ_SCP_MUTE_R                5
 +#define SPITZ_SCP_CF_POWER              6
 +#define SPITZ_SCP_LED_ORANGE            7
 +#define SPITZ_SCP_JK_A                  8
 +#define SPITZ_SCP_ADC_TEMP_ON           9
 +#define SPITZ_SCP2_IR_ON                1
 +#define SPITZ_SCP2_AKIN_PULLUP          2
 +#define SPITZ_SCP2_BACKLIGHT_CONT       7
 +#define SPITZ_SCP2_BACKLIGHT_ON                 8
 +#define SPITZ_SCP2_MIC_BIAS             9
  static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
                  DeviceState *scp0, DeviceState *scp1)
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
      qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
  }
 -#define SPITZ_GPIO_HSYNC        22
 -#define SPITZ_GPIO_SD_DETECT        9
 -#define SPITZ_GPIO_SD_WP        81
 -#define SPITZ_GPIO_ON_RESET        89
 -#define SPITZ_GPIO_BAT_COVER        90
 -#define SPITZ_GPIO_CF1_IRQ        105
 -#define SPITZ_GPIO_CF1_CD        94
 -#define SPITZ_GPIO_CF2_IRQ        106
 -#define SPITZ_GPIO_CF2_CD        93
 +#define SPITZ_GPIO_HSYNC                22
 +#define SPITZ_GPIO_SD_DETECT            9
 +#define SPITZ_GPIO_SD_WP                81
 +#define SPITZ_GPIO_ON_RESET             89
 +#define SPITZ_GPIO_BAT_COVER            90
 +#define SPITZ_GPIO_CF1_IRQ              105
 +#define SPITZ_GPIO_CF1_CD               94
 +#define SPITZ_GPIO_CF2_IRQ              106
 +#define SPITZ_GPIO_CF2_CD               93
  static int spitz_hsync;
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
  /* Board init.  */
  enum spitz_model_e { spitz, akita, borzoi, terrier };
 -#define SPITZ_RAM    0x04000000
 -#define SPITZ_ROM    0x00800000
 +#define SPITZ_RAM       0x04000000
 +#define SPITZ_ROM       0x00800000
  static struct arm_boot_info spitz_binfo = {
      .loader_start = PXA2XX_SDRAM_BASE,
 --
 .20.1

-New patch
+[PULL 18/34] hw/arm/spitz: Create SpitzMachineClass abstract base class
+For the four Spitz-family machines (akita, borzoi, spitz, terrier)
 create a proper abstract class SpitzMachineClass which encapsulates
 the common behaviour, rather than having them all derive directly
 from TYPE_MACHINE:
  * instead of each machine class setting mc->init to a wrapper
    function which calls spitz_common_init() with parameters,
    put that data in the SpitzMachineClass and make spitz_common_init
    the SpitzMachineClass machine-init function
  * move the settings of mc->block_default_type and
    mc->ignore_memory_transaction_failures into the SpitzMachineClass
    class init rather than repeating them in each machine's class init
 (The motivation is that we're going to want to keep some state in
 the SpitzMachineState so we can connect GPIOs between devices created
 in one sub-function of the machine init to devices created in a
 different sub-function.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200628142429.17111-3-peter.maydell@linaro.org
 ---
  hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++--------------------
 file changed, 55 insertions(+), 36 deletions(-)
 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/spitz.c
 +++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/address-spaces.h"
  #include "cpu.h"
 +enum spitz_model_e { spitz, akita, borzoi, terrier };
 +
 +typedef struct {
 +    MachineClass parent;
 +    enum spitz_model_e model;
 +    int arm_id;
 +} SpitzMachineClass;
 +
 +typedef struct {
 +    MachineState parent;
 +} SpitzMachineState;
 +
 +#define TYPE_SPITZ_MACHINE "spitz-common"
 +#define SPITZ_MACHINE(obj) \
 +    OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE)
 +#define SPITZ_MACHINE_GET_CLASS(obj) \
 +    OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE)
 +#define SPITZ_MACHINE_CLASS(klass) \
 +    OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
 +
  #undef REG_FMT
  #define REG_FMT                         "0x%02lx"
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
  }
  /* Board init.  */
 -enum spitz_model_e { spitz, akita, borzoi, terrier };
 -
  #define SPITZ_RAM       0x04000000
  #define SPITZ_ROM       0x00800000
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
      .ram_size = 0x04000000,
  };
 -static void spitz_common_init(MachineState *machine,
 -                              enum spitz_model_e model, int arm_id)
 +static void spitz_common_init(MachineState *machine)
  {
 +    SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
 +    enum spitz_model_e model = smc->model;
      PXA2xxState *mpu;
      DeviceState *scp0, *scp1 = NULL;
      MemoryRegion *address_space_mem = get_system_memory();
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine,
          /* A 4.0 GB microdrive is permanently sitting in CF slot 0.  */
          spitz_microdrive_attach(mpu, 0);
 -    spitz_binfo.board_id = arm_id;
 +    spitz_binfo.board_id = smc->arm_id;
      arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
      sl_bootparam_write(SL_PXA_PARAM_BASE);
  }
 -static void spitz_init(MachineState *machine)
 +static void spitz_common_class_init(ObjectClass *oc, void *data)
  {
 -    spitz_common_init(machine, spitz, 0x2c9);
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +
 +    mc->block_default_type = IF_IDE;
 +    mc->ignore_memory_transaction_failures = true;
 +    mc->init = spitz_common_init;
  }
 -static void borzoi_init(MachineState *machine)
 -{
 -    spitz_common_init(machine, borzoi, 0x33f);
 -}
 -
 -static void akita_init(MachineState *machine)
 -{
 -    spitz_common_init(machine, akita, 0x2e8);
 -}
 -
 -static void terrier_init(MachineState *machine)
 -{
 -    spitz_common_init(machine, terrier, 0x33f);
 -}
 +static const TypeInfo spitz_common_info = {
 +    .name = TYPE_SPITZ_MACHINE,
 +    .parent = TYPE_MACHINE,
 +    .abstract = true,
 +    .instance_size = sizeof(SpitzMachineState),
 +    .class_size = sizeof(SpitzMachineClass),
 +    .class_init = spitz_common_class_init,
 +};
  static void akitapda_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
      mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
 -    mc->init = akita_init;
 -    mc->ignore_memory_transaction_failures = true;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
 +    smc->model = akita;
 +    smc->arm_id = 0x2e8;
  }
  static const TypeInfo akitapda_type = {
      .name = MACHINE_TYPE_NAME("akita"),
 -    .parent = TYPE_MACHINE,
 +    .parent = TYPE_SPITZ_MACHINE,
      .class_init = akitapda_class_init,
  };
  static void spitzpda_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
      mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
 -    mc->init = spitz_init;
 -    mc->block_default_type = IF_IDE;
 -    mc->ignore_memory_transaction_failures = true;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
 +    smc->model = spitz;
 +    smc->arm_id = 0x2c9;
  }
  static const TypeInfo spitzpda_type = {
      .name = MACHINE_TYPE_NAME("spitz"),
 -    .parent = TYPE_MACHINE,
 +    .parent = TYPE_SPITZ_MACHINE,
      .class_init = spitzpda_class_init,
  };
  static void borzoipda_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
      mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
 -    mc->init = borzoi_init;
 -    mc->block_default_type = IF_IDE;
 -    mc->ignore_memory_transaction_failures = true;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
 +    smc->model = borzoi;
 +    smc->arm_id = 0x33f;
  }
  static const TypeInfo borzoipda_type = {
      .name = MACHINE_TYPE_NAME("borzoi"),
 -    .parent = TYPE_MACHINE,
 +    .parent = TYPE_SPITZ_MACHINE,
      .class_init = borzoipda_class_init,
  };
  static void terrierpda_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
 +    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
      mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
 -    mc->init = terrier_init;
 -    mc->block_default_type = IF_IDE;
 -    mc->ignore_memory_transaction_failures = true;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
 +    smc->model = terrier;
 +    smc->arm_id = 0x33f;
  }
  static const TypeInfo terrierpda_type = {
      .name = MACHINE_TYPE_NAME("terrier"),
 -    .parent = TYPE_MACHINE,
 +    .parent = TYPE_SPITZ_MACHINE,
      .class_init = terrierpda_class_init,
  };
  static void spitz_machine_init(void)
  {
 +    type_register_static(&spitz_common_info);
      type_register_static(&akitapda_type);
      type_register_static(&spitzpda_type);
      type_register_static(&borzoipda_type);
 --
 .20.1

-New patch
+[PULL 19/34] hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
+Keep pointers to the MPU and the SSI devices in SpitzMachineState.
+We're going to want to make GPIO connections between some of the
+SSI devices and the SCPs, so we want to keep hold of a pointer to
+those; putting the MPU into the struct allows us to pass just
+one thing to spitz_ssp_attach() rather than two.
+We have to retain the setting of the global "max1111" variable
+for the moment as it is used in spitz_adc_temp_on(); later in
+this series of commits we will be able to remove it.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-4-peter.maydell@linaro.org
+---
+ hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++----------------------
+file changed, 28 insertions(+), 22 deletions(-)
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+ typedef struct {
+     MachineState parent;
++    PXA2xxState *mpu;
++    DeviceState *mux;
++    DeviceState *lcdtg;
++    DeviceState *ads7846;
++    DeviceState *max1111;
+ } SpitzMachineState;
+ #define TYPE_SPITZ_MACHINE "spitz-common"
+@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_realize(SSISlave *d, Error **errp)
+     s->bus[2] = ssi_create_bus(dev, "ssi2");
+ }
+-static void spitz_ssp_attach(PXA2xxState *cpu)
++static void spitz_ssp_attach(SpitzMachineState *sms)
+ {
+-    DeviceState *mux;
+-    DeviceState *dev;
+     void *bus;
+-    mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
++    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
+-    bus = qdev_get_child_bus(mux, "ssi0");
+-    ssi_create_slave(bus, "spitz-lcdtg");
++    bus = qdev_get_child_bus(sms->mux, "ssi0");
++    sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
+-    bus = qdev_get_child_bus(mux, "ssi1");
+-    dev = ssi_create_slave(bus, "ads7846");
+-    qdev_connect_gpio_out(dev, 0,
+-                          qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
++    bus = qdev_get_child_bus(sms->mux, "ssi1");
++    sms->ads7846 = ssi_create_slave(bus, "ads7846");
++    qdev_connect_gpio_out(sms->ads7846, 0,
++                          qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
+-    bus = qdev_get_child_bus(mux, "ssi2");
+-    max1111 = ssi_create_slave(bus, "max1111");
+-    max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
+-    max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
+-    max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
++    bus = qdev_get_child_bus(sms->mux, "ssi2");
++    sms->max1111 = ssi_create_slave(bus, "max1111");
++    max1111 = sms->max1111;
++    max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
++    max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
++    max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
+-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
+-                        qdev_get_gpio_in(mux, 0));
+-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
+-                        qdev_get_gpio_in(mux, 1));
+-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
+-                        qdev_get_gpio_in(mux, 2));
++    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
++                        qdev_get_gpio_in(sms->mux, 0));
++    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS,
++                        qdev_get_gpio_in(sms->mux, 1));
++    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS,
++                        qdev_get_gpio_in(sms->mux, 2));
+ }
+ /* CF Microdrive */
+@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
+ static void spitz_common_init(MachineState *machine)
+ {
+     SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
++    SpitzMachineState *sms = SPITZ_MACHINE(machine);
+     enum spitz_model_e model = smc->model;
+     PXA2xxState *mpu;
+     DeviceState *scp0, *scp1 = NULL;
+@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
+     /* Setup CPU & memory */
+     mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
+                       machine->cpu_type);
++    sms->mpu = mpu;
+     sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
+@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
+     /* Setup peripherals */
+     spitz_keyboard_register(mpu);
+-    spitz_ssp_attach(mpu);
++    spitz_ssp_attach(sms);
+     scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
+     if (model != akita) {
+--
+.20.1

-[PULL 19/23] target/arm: Reformat comments in add_cpreg_to_hashtable
+[PULL 20/34] hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
-From: Richard Henderson <richard.henderson@linaro.org>
+Keep pointers to scp0, scp1 in SpitzMachineState, and just pass
 that to spitz_scoop_gpio_setup().
-Put the block comments into the current coding style.
+(We'll want to use some of the other fields in SpitzMachineState
 in that function in the next commit.)
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-19-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-5-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 24 +++++++++++++++---------
+ hw/arm/spitz.c | 34 +++++++++++++++++++---------------
-file changed, 15 insertions(+), 9 deletions(-)
+file changed, 19 insertions(+), 15 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/spitz.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+@@ -XXX,XX +XXX,XX @@ typedef struct {
-     return cpu_list;
+     DeviceState *lcdtg;
      DeviceState *ads7846;
      DeviceState *max1111;
 +    DeviceState *scp0;
 +    DeviceState *scp1;
  } SpitzMachineState;
  #define TYPE_SPITZ_MACHINE "spitz-common"
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
  #define SPITZ_SCP2_BACKLIGHT_ON                 8
  #define SPITZ_SCP2_MIC_BIAS             9
 -static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
 -                DeviceState *scp0, DeviceState *scp1)
 +static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
  {
 -    qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
 +    qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
 -    if (scp1) {
 -        qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
 -        qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
 +    if (sms->scp1) {
 +        qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
 +                              outsignals[4]);
 +        qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
 +                              outsignals[5]);
      }
 -    qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
  }
-+/*
+ #define SPITZ_GPIO_HSYNC                22
-+ * Private utility function for define_one_arm_cp_reg_with_opaque():
+@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
-+ * add a single reginfo struct to the hash table.
+     SpitzMachineState *sms = SPITZ_MACHINE(machine);
-+ */
+     enum spitz_model_e model = smc->model;
- static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+     PXA2xxState *mpu;
-                                    void *opaque, CPState state,
+-    DeviceState *scp0, *scp1 = NULL;
-                                    CPSecureState secstate,
+     MemoryRegion *address_space_mem = get_system_memory();
-                                    int crm, int opc1, int opc2,
+     MemoryRegion *rom = g_new(MemoryRegion, 1);
-                                    const char *name)
- {
+@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
--    /* Private utility function for define_one_arm_cp_reg_with_opaque():
--     * add a single reginfo struct to the hash table.
+     spitz_ssp_attach(sms);
--     */
-     uint32_t key;
+-    scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
-     ARMCPRegInfo *r2;
++    sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
-     bool is64 = r->type & ARM_CP_64BIT;
+     if (model != akita) {
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+-        scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
++        sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
-     isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
++    } else {
-     if (isbanked) {
++        sms->scp1 = NULL;
 -        /* Register is banked (using both entries in array).
 +        /*
 +         * Register is banked (using both entries in array).
           * Overwriting fieldoffset as the array is only used to define
           * banked registers but later only fieldoffset is used.
           */
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      if (state == ARM_CP_STATE_AA32) {
          if (isbanked) {
 -            /* If the register is banked then we don't need to migrate or
 +            /*
 +             * If the register is banked then we don't need to migrate or
               * reset the 32-bit instance in certain cases:
               *
               * 1) If the register has both 32-bit and 64-bit instances then we
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                  r2->type |= ARM_CP_ALIAS;
              }
          } else if ((secstate != r->secure) && !ns) {
 -            /* The register is not banked so we only want to allow migration of
 -             * the non-secure instance.
 +            /*
 +             * The register is not banked so we only want to allow migration
 +             * of the non-secure instance.
               */
              r2->type |= ARM_CP_ALIAS;
          }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          }
      }
--    /* By convention, for wildcarded registers only the first
+-    spitz_scoop_gpio_setup(mpu, scp0, scp1);
-+    /*
++    spitz_scoop_gpio_setup(sms);
-+     * By convention, for wildcarded registers only the first
-      * entry is used for migration; the others are marked as
+     spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
-      * ALIAS so we don't try to transfer the register
       * multiple times. Special registers (ie NOP/WFI) are
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
      }
 -    /* Check that raw accesses are either forbidden or handled. Note that
 +    /*
 +     * Check that raw accesses are either forbidden or handled. Note that
       * we can't assert this earlier because the setup of fieldoffset for
       * banked registers has to be done first.
       */
 --
-.25.1
+.20.1

-[PULL 15/23] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
+[PULL 21/34] hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
-From: Richard Henderson <richard.henderson@linaro.org>
+Currently the Spitz board uses a nasty hack for the GPIO lines
 that pass "bit5" and "power" information to the LCD controller:
 the lcdtg realize function sets a global variable to point to
 the instance it just realized, and then the functions spitz_bl_power()
 and spitz_bl_bit5() use that to find the device they are changing
 the internal state of. There is a comment reading:
  FIXME: Implement GPIO properly and remove this hack.
 which was added in 2009.
-Put most of the value writeback to the same place,
+Implement GPIO properly and remove this hack.
 and improve the comment that goes with them.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-15-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-6-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 28 ++++++++++++----------------
+ hw/arm/spitz.c | 28 ++++++++++++----------------
 file changed, 12 insertions(+), 16 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/spitz.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ static void spitz_bl_update(SpitzLCDTG *s)
-     *r2 = *r;
+         zaurus_printf("LCD Backlight now off\n");
-     r2->name = memcpy(r2 + 1, name, name_len);
+ }
--    /* Reset the secure state to the specific incoming state.  This is
+-/* FIXME: Implement GPIO properly and remove this hack.  */
--     * necessary as the register may have been defined with both states.
+-static SpitzLCDTG *spitz_lcdtg;
-+    /*
+-
-+     * Update fields to match the instantiation, overwiting wildcards
+ static inline void spitz_bl_bit5(void *opaque, int line, int level)
-+     * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
+ {
-      */
+-    SpitzLCDTG *s = spitz_lcdtg;
-+    r2->cp = cp;
++    SpitzLCDTG *s = opaque;
-+    r2->crm = crm;
+     int prev = s->bl_intensity;
-+    r2->opc1 = opc1;
-+    r2->opc2 = opc2;
+     if (level)
-+    r2->state = state;
+@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_bit5(void *opaque, int line, int level)
-     r2->secure = secstate;
-+    if (opaque) {
+ static inline void spitz_bl_power(void *opaque, int line, int level)
-+        r2->opaque = opaque;
+ {
-+    }
+-    SpitzLCDTG *s = spitz_lcdtg;
++    SpitzLCDTG *s = opaque;
-     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
+     s->bl_power = !!level;
-         /* Register is banked (using both entries in array).
+     spitz_bl_update(s);
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+ }
- #endif
+@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
-         }
+     return 0;
  }
 -static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
 +static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
  {
 -    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
 +    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
 +    DeviceState *dev = DEVICE(s);
 -    spitz_lcdtg = s;
      s->bl_power = 0;
      s->bl_intensity = 0x20;
 +
 +    qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1);
 +    qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1);
  }
  /* SSP devices */
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
      case 3:
          zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
          break;
 -    case 4:
 -        spitz_bl_bit5(opaque, line, level);
 -        break;
 -    case 5:
 -        spitz_bl_power(opaque, line, level);
 -        break;
      case 6:
          spitz_adc_temp_on(opaque, line, level);
          break;
 +    default:
 +        g_assert_not_reached();
      }
--    if (opaque) {
+ }
--        r2->opaque = opaque;
--    }
+@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
--    /* reginfo passed to helpers is correct for the actual access,
--     * and is never ARM_CP_STATE_BOTH:
+     if (sms->scp1) {
--     */
+         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
--    r2->state = state;
+-                              outsignals[4]);
--    /* Make sure reginfo passed to helpers for wildcarded regs
++                              qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0));
--     * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
+         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
--     */
+-                              outsignals[5]);
--    r2->cp = cp;
++                              qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
--    r2->crm = crm;
+     }
--    r2->opc1 = opc1;
--    r2->opc2 = opc2;
+     qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 +
      /* By convention, for wildcarded registers only the first
       * entry is used for migration; the others are marked as
       * ALIAS so we don't try to transfer the register
 --
-.25.1
+.20.1

-[PULL 02/23] target/arm: Split out cpregs.h
+[PULL 22/34] hw/misc/max111x: provide QOM properties for setting initial values
-From: Richard Henderson <richard.henderson@linaro.org>
+Add some QOM properties to the max111x ADC device to allow the
 initial values to be configured. Currently this is done by
 board code calling max111x_set_input() after it creates the
 device, which doesn't work on system reset.
-Move ARMCPRegInfo and all related declarations to a new
+This requires us to implement a reset method for this device,
-internal header, out of the public cpu.h.
+so while we're doing that make sure we reset the other parts
 of the device state.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-7-peter.maydell@linaro.org
 ---
- target/arm/cpregs.h        | 413 +++++++++++++++++++++++++++++++++++++
+ hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++---------
- target/arm/cpu.h           | 368 ---------------------------------
+file changed, 47 insertions(+), 10 deletions(-)
  hw/arm/pxa2xx.c            |   1 +
  hw/arm/pxa2xx_pic.c        |   1 +
  hw/intc/arm_gicv3_cpuif.c  |   1 +
  hw/intc/arm_gicv3_kvm.c    |   2 +
  target/arm/cpu.c           |   1 +
  target/arm/cpu64.c         |   1 +
  target/arm/cpu_tcg.c       |   1 +
  target/arm/gdbstub.c       |   3 +-
  target/arm/helper.c        |   1 +
  target/arm/op_helper.c     |   1 +
  target/arm/translate-a64.c |   4 +-
  target/arm/translate.c     |   3 +-
 files changed, 427 insertions(+), 374 deletions(-)
  create mode 100644 target/arm/cpregs.h
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/hw/misc/max111x.c
---- /dev/null
++++ b/hw/misc/max111x.c
 +++ b/target/arm/cpregs.h
 @@ -XXX,XX +XXX,XX @@
-+/*
+ #include "hw/ssi/ssi.h"
-+ * QEMU ARM CP Register access and descriptions
+ #include "migration/vmstate.h"
-+ *
+ #include "qemu/module.h"
-+ * Copyright (c) 2022 Linaro Ltd
++#include "hw/qdev-properties.h"
-+ *
-+ * This program is free software; you can redistribute it and/or
+ typedef struct {
-+ * modify it under the terms of the GNU General Public License
+     SSISlave parent_obj;
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
+     qemu_irq interrupt;
-+ *
++    /* Values of inputs at system reset (settable by QOM property) */
-+ * This program is distributed in the hope that it will be useful,
++    uint8_t reset_input[8];
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, see
 + * <http://www.gnu.org/licenses/gpl-2.0.html>
 + */
 +
-+#ifndef TARGET_ARM_CPREGS_H
+     uint8_t tb1, rb2, rb3;
-+#define TARGET_ARM_CPREGS_H
+     int cycle;
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
      qdev_init_gpio_out(dev, &s->interrupt, 1);
      s->inputs = inputs;
 -    /* TODO: add a user interface for setting these */
 -    s->input[0] = 0xf0;
 -    s->input[1] = 0xe0;
 -    s->input[2] = 0xd0;
 -    s->input[3] = 0xc0;
 -    s->input[4] = 0xb0;
 -    s->input[5] = 0xa0;
 -    s->input[6] = 0x90;
 -    s->input[7] = 0x80;
 -    s->com = 0;
      vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
                       &vmstate_max111x, s);
@@ -XXX,XX +XXX,XX @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value)
      s->input[line] = value;
  }
 +static void max111x_reset(DeviceState *dev)
 +{
 +    MAX111xState *s = MAX_111X(dev);
 +    int i;
 +
-+/*
++    for (i = 0; i < s->inputs; i++) {
-+ * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
++        s->input[i] = s->reset_input[i];
-+ * special-behaviour cp reg and bits [11..8] indicate what behaviour
++    }
-+ * it has. Otherwise it is a simple cp reg, where CONST indicates that
++    s->com = 0;
-+ * TCG can assume the value to be constant (ie load at translate time)
++    s->tb1 = 0;
-+ * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
++    s->rb2 = 0;
-+ * indicates that the TB should not be ended after a write to this register
++    s->rb3 = 0;
-+ * (the default is that the TB ends after cp writes). OVERRIDE permits
++    s->cycle = 0;
-+ * a register definition to override a previous definition for the
++}
 + * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 + * old must have the OVERRIDE bit set.
 + * ALIAS indicates that this register is an alias view of some underlying
 + * state which is also visible via another register, and that the other
 + * register is handling migration and reset; registers marked ALIAS will not be
 + * migrated but may have their state set by syncing of register state from KVM.
 + * NO_RAW indicates that this register has no underlying state and does not
 + * support raw access for state saving/loading; it will not be used for either
 + * migration or KVM state synchronization. (Typically this is for "registers"
 + * which are actually used as instructions for cache maintenance and so on.)
 + * IO indicates that this register does I/O and therefore its accesses
 + * need to be marked with gen_io_start() and also end the TB. In particular,
 + * registers which implement clocks or timers require this.
 + * RAISES_EXC is for when the read or write hook might raise an exception;
 + * the generated code will synchronize the CPU state before calling the hook
 + * so that it is safe for the hook to call raise_exception().
 + * NEWEL is for writes to registers that might change the exception
 + * level - typically on older ARM chips. For those cases we need to
 + * re-read the new el when recomputing the translation flags.
 + */
 +#define ARM_CP_SPECIAL           0x0001
 +#define ARM_CP_CONST             0x0002
 +#define ARM_CP_64BIT             0x0004
 +#define ARM_CP_SUPPRESS_TB_END   0x0008
 +#define ARM_CP_OVERRIDE          0x0010
 +#define ARM_CP_ALIAS             0x0020
 +#define ARM_CP_IO                0x0040
 +#define ARM_CP_NO_RAW            0x0080
 +#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
 +#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
 +#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
 +#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
 +#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
 +#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
 +#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
 +#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
 +#define ARM_CP_FPU               0x1000
 +#define ARM_CP_SVE               0x2000
 +#define ARM_CP_NO_GDB            0x4000
 +#define ARM_CP_RAISES_EXC        0x8000
 +#define ARM_CP_NEWEL             0x10000
 +/* Used only as a terminator for ARMCPRegInfo lists */
 +#define ARM_CP_SENTINEL          0xfffff
 +/* Mask of only the flag bits in a type field */
 +#define ARM_CP_FLAG_MASK         0x1f0ff
 +
-+/*
++static Property max1110_properties[] = {
-+ * Valid values for ARMCPRegInfo state field, indicating which of
++    /* Reset values for ADC inputs */
-+ * the AArch32 and AArch64 execution states this register is visible in.
++    DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
-+ * If the reginfo doesn't explicitly specify then it is AArch32 only.
++    DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
-+ * If the reginfo is declared to be visible in both states then a second
++    DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
-+ * reginfo is synthesised for the AArch32 view of the AArch64 register,
++    DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
-+ * such that the AArch32 view is the lower 32 bits of the AArch64 one.
++    DEFINE_PROP_END_OF_LIST(),
 + * Note that we rely on the values of these enums as we iterate through
 + * the various states in some places.
 + */
 +enum {
 +    ARM_CP_STATE_AA32 = 0,
 +    ARM_CP_STATE_AA64 = 1,
 +    ARM_CP_STATE_BOTH = 2,
 +};
 +
-+/*
++static Property max1111_properties[] = {
-+ * ARM CP register secure state flags.  These flags identify security state
++    /* Reset values for ADC inputs */
-+ * attributes for a given CP register entry.
++    DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
-+ * The existence of both or neither secure and non-secure flags indicates that
++    DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
-+ * the register has both a secure and non-secure hash entry.  A single one of
++    DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
-+ * these flags causes the register to only be hashed for the specified
++    DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
-+ * security state.
++    DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0),
-+ * Although definitions may have any combination of the S/NS bits, each
++    DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0),
-+ * registered entry will only have one to identify whether the entry is secure
++    DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90),
-+ * or non-secure.
++    DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80),
-+ */
++    DEFINE_PROP_END_OF_LIST(),
 +enum {
 +    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
 +    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
 +};
 +
-+/*
+ static void max111x_class_init(ObjectClass *klass, void *data)
-+ * Return true if cptype is a valid type field. This is used to try to
+ {
-+ * catch errors where the sentinel has been accidentally left off the end
+     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
-+ * of a list of registers.
++    DeviceClass *dc = DEVICE_CLASS(klass);
-+ */
-+static inline bool cptype_valid(int cptype)
+     k->transfer = max111x_transfer;
-+{
++    dc->reset = max111x_reset;
 +    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 +        || ((cptype & ARM_CP_SPECIAL) &&
 +            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 +}
 +
 +/*
 + * Access rights:
 + * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 + * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 + * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 + * (ie any of the privileged modes in Secure state, or Monitor mode).
 + * If a register is accessible in one privilege level it's always accessible
 + * in higher privilege levels too. Since "Secure PL1" also follows this rule
 + * (ie anything visible in PL2 is visible in S-PL1, some things are only
 + * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 + * terminology a little and call this PL3.
 + * In AArch64 things are somewhat simpler as the PLx bits line up exactly
 + * with the ELx exception levels.
 + *
 + * If access permissions for a register are more complex than can be
 + * described with these bits, then use a laxer set of restrictions, and
 + * do the more restrictive/complex check inside a helper function.
 + */
 +#define PL3_R 0x80
 +#define PL3_W 0x40
 +#define PL2_R (0x20 | PL3_R)
 +#define PL2_W (0x10 | PL3_W)
 +#define PL1_R (0x08 | PL2_R)
 +#define PL1_W (0x04 | PL2_W)
 +#define PL0_R (0x02 | PL1_R)
 +#define PL0_W (0x01 | PL1_W)
 +
 +/*
 + * For user-mode some registers are accessible to EL0 via a kernel
 + * trap-and-emulate ABI. In this case we define the read permissions
 + * as actually being PL0_R. However some bits of any given register
 + * may still be masked.
 + */
 +#ifdef CONFIG_USER_ONLY
 +#define PL0U_R PL0_R
 +#else
 +#define PL0U_R PL1_R
 +#endif
 +
 +#define PL3_RW (PL3_R | PL3_W)
 +#define PL2_RW (PL2_R | PL2_W)
 +#define PL1_RW (PL1_R | PL1_W)
 +#define PL0_RW (PL0_R | PL0_W)
 +
 +typedef enum CPAccessResult {
 +    /* Access is permitted */
 +    CP_ACCESS_OK = 0,
 +    /*
 +     * Access fails due to a configurable trap or enable which would
 +     * result in a categorized exception syndrome giving information about
 +     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
 +     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
 +     * PL1 if in EL0, otherwise to the current EL).
 +     */
 +    CP_ACCESS_TRAP = 1,
 +    /*
 +     * Access fails and results in an exception syndrome 0x0 ("uncategorized").
 +     * Note that this is not a catch-all case -- the set of cases which may
 +     * result in this failure is specifically defined by the architecture.
 +     */
 +    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
 +    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
 +    CP_ACCESS_TRAP_EL2 = 3,
 +    CP_ACCESS_TRAP_EL3 = 4,
 +    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
 +    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
 +    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
 +} CPAccessResult;
 +
 +typedef struct ARMCPRegInfo ARMCPRegInfo;
 +
 +/*
 + * Access functions for coprocessor registers. These cannot fail and
 + * may not raise exceptions.
 + */
 +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 +                       uint64_t value);
 +/* Access permission check functions for coprocessor registers. */
 +typedef CPAccessResult CPAccessFn(CPUARMState *env,
 +                                  const ARMCPRegInfo *opaque,
 +                                  bool isread);
 +/* Hook function for register reset */
 +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 +
 +#define CP_ANY 0xff
 +
 +/* Definition of an ARM coprocessor register */
 +struct ARMCPRegInfo {
 +    /* Name of register (useful mainly for debugging, need not be unique) */
 +    const char *name;
 +    /*
 +     * Location of register: coprocessor number and (crn,crm,opc1,opc2)
 +     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 +     * 'wildcard' field -- any value of that field in the MRC/MCR insn
 +     * will be decoded to this register. The register read and write
 +     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 +     * used by the program, so it is possible to register a wildcard and
 +     * then behave differently on read/write if necessary.
 +     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 +     * must both be zero.
 +     * For AArch64-visible registers, opc0 is also used.
 +     * Since there are no "coprocessors" in AArch64, cp is purely used as a
 +     * way to distinguish (for KVM's benefit) guest-visible system registers
 +     * from demuxed ones provided to preserve the "no side effects on
 +     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
 +     * visible (to match KVM's encoding); cp==0 will be converted to
 +     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
 +     */
 +    uint8_t cp;
 +    uint8_t crn;
 +    uint8_t crm;
 +    uint8_t opc0;
 +    uint8_t opc1;
 +    uint8_t opc2;
 +    /* Execution state in which this register is visible: ARM_CP_STATE_* */
 +    int state;
 +    /* Register type: ARM_CP_* bits/values */
 +    int type;
 +    /* Access rights: PL*_[RW] */
 +    int access;
 +    /* Security state: ARM_CP_SECSTATE_* bits/values */
 +    int secure;
 +    /*
 +     * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 +     * this register was defined: can be used to hand data through to the
 +     * register read/write functions, since they are passed the ARMCPRegInfo*.
 +     */
 +    void *opaque;
 +    /*
 +     * Value of this register, if it is ARM_CP_CONST. Otherwise, if
 +     * fieldoffset is non-zero, the reset value of the register.
 +     */
 +    uint64_t resetvalue;
 +    /*
 +     * Offset of the field in CPUARMState for this register.
 +     * This is not needed if either:
 +     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 +     *  2. both readfn and writefn are specified
 +     */
 +    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 +
 +    /*
 +     * Offsets of the secure and non-secure fields in CPUARMState for the
 +     * register if it is banked.  These fields are only used during the static
 +     * registration of a register.  During hashing the bank associated
 +     * with a given security state is copied to fieldoffset which is used from
 +     * there on out.
 +     *
 +     * It is expected that register definitions use either fieldoffset or
 +     * bank_fieldoffsets in the definition but not both.  It is also expected
 +     * that both bank offsets are set when defining a banked register.  This
 +     * use indicates that a register is banked.
 +     */
 +    ptrdiff_t bank_fieldoffsets[2];
 +
 +    /*
 +     * Function for making any access checks for this register in addition to
 +     * those specified by the 'access' permissions bits. If NULL, no extra
 +     * checks required. The access check is performed at runtime, not at
 +     * translate time.
 +     */
 +    CPAccessFn *accessfn;
 +    /*
 +     * Function for handling reads of this register. If NULL, then reads
 +     * will be done by loading from the offset into CPUARMState specified
 +     * by fieldoffset.
 +     */
 +    CPReadFn *readfn;
 +    /*
 +     * Function for handling writes of this register. If NULL, then writes
 +     * will be done by writing to the offset into CPUARMState specified
 +     * by fieldoffset.
 +     */
 +    CPWriteFn *writefn;
 +    /*
 +     * Function for doing a "raw" read; used when we need to copy
 +     * coprocessor state to the kernel for KVM or out for
 +     * migration. This only needs to be provided if there is also a
 +     * readfn and it has side effects (for instance clear-on-read bits).
 +     */
 +    CPReadFn *raw_readfn;
 +    /*
 +     * Function for doing a "raw" write; used when we need to copy KVM
 +     * kernel coprocessor state into userspace, or for inbound
 +     * migration. This only needs to be provided if there is also a
 +     * writefn and it masks out "unwritable" bits or has write-one-to-clear
 +     * or similar behaviour.
 +     */
 +    CPWriteFn *raw_writefn;
 +    /*
 +     * Function for resetting the register. If NULL, then reset will be done
 +     * by writing resetvalue to the field specified in fieldoffset. If
 +     * fieldoffset is 0 then no reset will be done.
 +     */
 +    CPResetFn *resetfn;
 +
 +    /*
 +     * "Original" writefn and readfn.
 +     * For ARMv8.1-VHE register aliases, we overwrite the read/write
 +     * accessor functions of various EL1/EL0 to perform the runtime
 +     * check for which sysreg should actually be modified, and then
 +     * forwards the operation.  Before overwriting the accessors,
 +     * the original function is copied here, so that accesses that
 +     * really do go to the EL1/EL0 version proceed normally.
 +     * (The corresponding EL2 register is linked via opaque.)
 +     */
 +    CPReadFn *orig_readfn;
 +    CPWriteFn *orig_writefn;
 +};
 +
 +/*
 + * Macros which are lvalues for the field in CPUARMState for the
 + * ARMCPRegInfo *ri.
 + */
 +#define CPREG_FIELD32(env, ri) \
 +    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 +#define CPREG_FIELD64(env, ri) \
 +    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 +
 +#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 +
 +void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 +                                    const ARMCPRegInfo *regs, void *opaque);
 +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 +                                       const ARMCPRegInfo *regs, void *opaque);
 +static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 +{
 +    define_arm_cp_regs_with_opaque(cpu, regs, 0);
 +}
 +static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 +{
 +    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 +}
 +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
 +
 +/*
 + * Definition of an ARM co-processor register as viewed from
 + * userspace. This is used for presenting sanitised versions of
 + * registers to userspace when emulating the Linux AArch64 CPU
 + * ID/feature ABI (advertised as HWCAP_CPUID).
 + */
 +typedef struct ARMCPRegUserSpaceInfo {
 +    /* Name of register */
 +    const char *name;
 +
 +    /* Is the name actually a glob pattern */
 +    bool is_glob;
 +
 +    /* Only some bits are exported to user space */
 +    uint64_t exported_bits;
 +
 +    /* Fixed bits are applied after the mask */
 +    uint64_t fixed_bits;
 +} ARMCPRegUserSpaceInfo;
 +
 +#define REGUSERINFO_SENTINEL { .name = NULL }
 +
 +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
 +
 +/* CPWriteFn that can be used to implement writes-ignored behaviour */
 +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 +                         uint64_t value);
 +/* CPReadFn that can be used for read-as-zero behaviour */
 +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
 +
 +/*
 + * CPResetFn that does nothing, for use if no reset is required even
 + * if fieldoffset is non zero.
 + */
 +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
 +
 +/*
 + * Return true if this reginfo struct's field in the cpu state struct
 + * is 64 bits wide.
 + */
 +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
 +{
 +    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
 +}
 +
 +static inline bool cp_access_ok(int current_el,
 +                                const ARMCPRegInfo *ri, int isread)
 +{
 +    return (ri->access >> ((current_el * 2) + isread)) & 1;
 +}
 +
 +/* Raw read of a coprocessor register (as needed for migration, etc) */
 +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
 +
 +#endif /* TARGET_ARM_CPREGS_H */
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
      return kvmid;
  }
--/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
+ static const TypeInfo max111x_info = {
-- * special-behaviour cp reg and bits [11..8] indicate what behaviour
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo max111x_info = {
-- * it has. Otherwise it is a simple cp reg, where CONST indicates that
+ static void max1110_class_init(ObjectClass *klass, void *data)
 - * TCG can assume the value to be constant (ie load at translate time)
 - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 - * indicates that the TB should not be ended after a write to this register
 - * (the default is that the TB ends after cp writes). OVERRIDE permits
 - * a register definition to override a previous definition for the
 - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 - * old must have the OVERRIDE bit set.
 - * ALIAS indicates that this register is an alias view of some underlying
 - * state which is also visible via another register, and that the other
 - * register is handling migration and reset; registers marked ALIAS will not be
 - * migrated but may have their state set by syncing of register state from KVM.
 - * NO_RAW indicates that this register has no underlying state and does not
 - * support raw access for state saving/loading; it will not be used for either
 - * migration or KVM state synchronization. (Typically this is for "registers"
 - * which are actually used as instructions for cache maintenance and so on.)
 - * IO indicates that this register does I/O and therefore its accesses
 - * need to be marked with gen_io_start() and also end the TB. In particular,
 - * registers which implement clocks or timers require this.
 - * RAISES_EXC is for when the read or write hook might raise an exception;
 - * the generated code will synchronize the CPU state before calling the hook
 - * so that it is safe for the hook to call raise_exception().
 - * NEWEL is for writes to registers that might change the exception
 - * level - typically on older ARM chips. For those cases we need to
 - * re-read the new el when recomputing the translation flags.
 - */
 -#define ARM_CP_SPECIAL           0x0001
 -#define ARM_CP_CONST             0x0002
 -#define ARM_CP_64BIT             0x0004
 -#define ARM_CP_SUPPRESS_TB_END   0x0008
 -#define ARM_CP_OVERRIDE          0x0010
 -#define ARM_CP_ALIAS             0x0020
 -#define ARM_CP_IO                0x0040
 -#define ARM_CP_NO_RAW            0x0080
 -#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
 -#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
 -#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
 -#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
 -#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
 -#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
 -#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
 -#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
 -#define ARM_CP_FPU               0x1000
 -#define ARM_CP_SVE               0x2000
 -#define ARM_CP_NO_GDB            0x4000
 -#define ARM_CP_RAISES_EXC        0x8000
 -#define ARM_CP_NEWEL             0x10000
 -/* Used only as a terminator for ARMCPRegInfo lists */
 -#define ARM_CP_SENTINEL          0xfffff
 -/* Mask of only the flag bits in a type field */
 -#define ARM_CP_FLAG_MASK         0x1f0ff
 -
 -/* Valid values for ARMCPRegInfo state field, indicating which of
 - * the AArch32 and AArch64 execution states this register is visible in.
 - * If the reginfo doesn't explicitly specify then it is AArch32 only.
 - * If the reginfo is declared to be visible in both states then a second
 - * reginfo is synthesised for the AArch32 view of the AArch64 register,
 - * such that the AArch32 view is the lower 32 bits of the AArch64 one.
 - * Note that we rely on the values of these enums as we iterate through
 - * the various states in some places.
 - */
 -enum {
 -    ARM_CP_STATE_AA32 = 0,
 -    ARM_CP_STATE_AA64 = 1,
 -    ARM_CP_STATE_BOTH = 2,
 -};
 -
 -/* ARM CP register secure state flags.  These flags identify security state
 - * attributes for a given CP register entry.
 - * The existence of both or neither secure and non-secure flags indicates that
 - * the register has both a secure and non-secure hash entry.  A single one of
 - * these flags causes the register to only be hashed for the specified
 - * security state.
 - * Although definitions may have any combination of the S/NS bits, each
 - * registered entry will only have one to identify whether the entry is secure
 - * or non-secure.
 - */
 -enum {
 -    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
 -    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
 -};
 -
 -/* Return true if cptype is a valid type field. This is used to try to
 - * catch errors where the sentinel has been accidentally left off the end
 - * of a list of registers.
 - */
 -static inline bool cptype_valid(int cptype)
 -{
 -    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 -        || ((cptype & ARM_CP_SPECIAL) &&
 -            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 -}
 -
 -/* Access rights:
 - * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 - * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 - * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 - * (ie any of the privileged modes in Secure state, or Monitor mode).
 - * If a register is accessible in one privilege level it's always accessible
 - * in higher privilege levels too. Since "Secure PL1" also follows this rule
 - * (ie anything visible in PL2 is visible in S-PL1, some things are only
 - * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 - * terminology a little and call this PL3.
 - * In AArch64 things are somewhat simpler as the PLx bits line up exactly
 - * with the ELx exception levels.
 - *
 - * If access permissions for a register are more complex than can be
 - * described with these bits, then use a laxer set of restrictions, and
 - * do the more restrictive/complex check inside a helper function.
 - */
 -#define PL3_R 0x80
 -#define PL3_W 0x40
 -#define PL2_R (0x20 | PL3_R)
 -#define PL2_W (0x10 | PL3_W)
 -#define PL1_R (0x08 | PL2_R)
 -#define PL1_W (0x04 | PL2_W)
 -#define PL0_R (0x02 | PL1_R)
 -#define PL0_W (0x01 | PL1_W)
 -
 -/*
 - * For user-mode some registers are accessible to EL0 via a kernel
 - * trap-and-emulate ABI. In this case we define the read permissions
 - * as actually being PL0_R. However some bits of any given register
 - * may still be masked.
 - */
 -#ifdef CONFIG_USER_ONLY
 -#define PL0U_R PL0_R
 -#else
 -#define PL0U_R PL1_R
 -#endif
 -
 -#define PL3_RW (PL3_R | PL3_W)
 -#define PL2_RW (PL2_R | PL2_W)
 -#define PL1_RW (PL1_R | PL1_W)
 -#define PL0_RW (PL0_R | PL0_W)
 -
  /* Return the highest implemented Exception Level */
  static inline int arm_highest_el(CPUARMState *env)
  {
-@@ -XXX,XX +XXX,XX @@ static inline int arm_current_el(CPUARMState *env)
+     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
-     }
++    DeviceClass *dc = DEVICE_CLASS(klass);
      k->realize = max1110_realize;
 +    device_class_set_props(dc, max1110_properties);
  }
--typedef struct ARMCPRegInfo ARMCPRegInfo;
+ static const TypeInfo max1110_info = {
--
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo max1110_info = {
--typedef enum CPAccessResult {
+ static void max1111_class_init(ObjectClass *klass, void *data)
 -    /* Access is permitted */
 -    CP_ACCESS_OK = 0,
 -    /* Access fails due to a configurable trap or enable which would
 -     * result in a categorized exception syndrome giving information about
 -     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
 -     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
 -     * PL1 if in EL0, otherwise to the current EL).
 -     */
 -    CP_ACCESS_TRAP = 1,
 -    /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
 -     * Note that this is not a catch-all case -- the set of cases which may
 -     * result in this failure is specifically defined by the architecture.
 -     */
 -    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
 -    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
 -    CP_ACCESS_TRAP_EL2 = 3,
 -    CP_ACCESS_TRAP_EL3 = 4,
 -    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
 -    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
 -    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
 -} CPAccessResult;
 -
 -/* Access functions for coprocessor registers. These cannot fail and
 - * may not raise exceptions.
 - */
 -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 -                       uint64_t value);
 -/* Access permission check functions for coprocessor registers. */
 -typedef CPAccessResult CPAccessFn(CPUARMState *env,
 -                                  const ARMCPRegInfo *opaque,
 -                                  bool isread);
 -/* Hook function for register reset */
 -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 -
 -#define CP_ANY 0xff
 -
 -/* Definition of an ARM coprocessor register */
 -struct ARMCPRegInfo {
 -    /* Name of register (useful mainly for debugging, need not be unique) */
 -    const char *name;
 -    /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 -     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 -     * 'wildcard' field -- any value of that field in the MRC/MCR insn
 -     * will be decoded to this register. The register read and write
 -     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 -     * used by the program, so it is possible to register a wildcard and
 -     * then behave differently on read/write if necessary.
 -     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 -     * must both be zero.
 -     * For AArch64-visible registers, opc0 is also used.
 -     * Since there are no "coprocessors" in AArch64, cp is purely used as a
 -     * way to distinguish (for KVM's benefit) guest-visible system registers
 -     * from demuxed ones provided to preserve the "no side effects on
 -     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
 -     * visible (to match KVM's encoding); cp==0 will be converted to
 -     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
 -     */
 -    uint8_t cp;
 -    uint8_t crn;
 -    uint8_t crm;
 -    uint8_t opc0;
 -    uint8_t opc1;
 -    uint8_t opc2;
 -    /* Execution state in which this register is visible: ARM_CP_STATE_* */
 -    int state;
 -    /* Register type: ARM_CP_* bits/values */
 -    int type;
 -    /* Access rights: PL*_[RW] */
 -    int access;
 -    /* Security state: ARM_CP_SECSTATE_* bits/values */
 -    int secure;
 -    /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 -     * this register was defined: can be used to hand data through to the
 -     * register read/write functions, since they are passed the ARMCPRegInfo*.
 -     */
 -    void *opaque;
 -    /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 -     * fieldoffset is non-zero, the reset value of the register.
 -     */
 -    uint64_t resetvalue;
 -    /* Offset of the field in CPUARMState for this register.
 -     *
 -     * This is not needed if either:
 -     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 -     *  2. both readfn and writefn are specified
 -     */
 -    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 -
 -    /* Offsets of the secure and non-secure fields in CPUARMState for the
 -     * register if it is banked.  These fields are only used during the static
 -     * registration of a register.  During hashing the bank associated
 -     * with a given security state is copied to fieldoffset which is used from
 -     * there on out.
 -     *
 -     * It is expected that register definitions use either fieldoffset or
 -     * bank_fieldoffsets in the definition but not both.  It is also expected
 -     * that both bank offsets are set when defining a banked register.  This
 -     * use indicates that a register is banked.
 -     */
 -    ptrdiff_t bank_fieldoffsets[2];
 -
 -    /* Function for making any access checks for this register in addition to
 -     * those specified by the 'access' permissions bits. If NULL, no extra
 -     * checks required. The access check is performed at runtime, not at
 -     * translate time.
 -     */
 -    CPAccessFn *accessfn;
 -    /* Function for handling reads of this register. If NULL, then reads
 -     * will be done by loading from the offset into CPUARMState specified
 -     * by fieldoffset.
 -     */
 -    CPReadFn *readfn;
 -    /* Function for handling writes of this register. If NULL, then writes
 -     * will be done by writing to the offset into CPUARMState specified
 -     * by fieldoffset.
 -     */
 -    CPWriteFn *writefn;
 -    /* Function for doing a "raw" read; used when we need to copy
 -     * coprocessor state to the kernel for KVM or out for
 -     * migration. This only needs to be provided if there is also a
 -     * readfn and it has side effects (for instance clear-on-read bits).
 -     */
 -    CPReadFn *raw_readfn;
 -    /* Function for doing a "raw" write; used when we need to copy KVM
 -     * kernel coprocessor state into userspace, or for inbound
 -     * migration. This only needs to be provided if there is also a
 -     * writefn and it masks out "unwritable" bits or has write-one-to-clear
 -     * or similar behaviour.
 -     */
 -    CPWriteFn *raw_writefn;
 -    /* Function for resetting the register. If NULL, then reset will be done
 -     * by writing resetvalue to the field specified in fieldoffset. If
 -     * fieldoffset is 0 then no reset will be done.
 -     */
 -    CPResetFn *resetfn;
 -
 -    /*
 -     * "Original" writefn and readfn.
 -     * For ARMv8.1-VHE register aliases, we overwrite the read/write
 -     * accessor functions of various EL1/EL0 to perform the runtime
 -     * check for which sysreg should actually be modified, and then
 -     * forwards the operation.  Before overwriting the accessors,
 -     * the original function is copied here, so that accesses that
 -     * really do go to the EL1/EL0 version proceed normally.
 -     * (The corresponding EL2 register is linked via opaque.)
 -     */
 -    CPReadFn *orig_readfn;
 -    CPWriteFn *orig_writefn;
 -};
 -
 -/* Macros which are lvalues for the field in CPUARMState for the
 - * ARMCPRegInfo *ri.
 - */
 -#define CPREG_FIELD32(env, ri) \
 -    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 -#define CPREG_FIELD64(env, ri) \
 -    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 -
 -#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 -
 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 -                                    const ARMCPRegInfo *regs, void *opaque);
 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 -                                       const ARMCPRegInfo *regs, void *opaque);
 -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 -{
 -    define_arm_cp_regs_with_opaque(cpu, regs, 0);
 -}
 -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 -{
 -    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 -}
 -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
 -
 -/*
 - * Definition of an ARM co-processor register as viewed from
 - * userspace. This is used for presenting sanitised versions of
 - * registers to userspace when emulating the Linux AArch64 CPU
 - * ID/feature ABI (advertised as HWCAP_CPUID).
 - */
 -typedef struct ARMCPRegUserSpaceInfo {
 -    /* Name of register */
 -    const char *name;
 -
 -    /* Is the name actually a glob pattern */
 -    bool is_glob;
 -
 -    /* Only some bits are exported to user space */
 -    uint64_t exported_bits;
 -
 -    /* Fixed bits are applied after the mask */
 -    uint64_t fixed_bits;
 -} ARMCPRegUserSpaceInfo;
 -
 -#define REGUSERINFO_SENTINEL { .name = NULL }
 -
 -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
 -
 -/* CPWriteFn that can be used to implement writes-ignored behaviour */
 -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 -                         uint64_t value);
 -/* CPReadFn that can be used for read-as-zero behaviour */
 -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
 -
 -/* CPResetFn that does nothing, for use if no reset is required even
 - * if fieldoffset is non zero.
 - */
 -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
 -
 -/* Return true if this reginfo struct's field in the cpu state struct
 - * is 64 bits wide.
 - */
 -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
 -{
 -    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
 -}
 -
 -static inline bool cp_access_ok(int current_el,
 -                                const ARMCPRegInfo *ri, int isread)
 -{
 -    return (ri->access >> ((current_el * 2) + isread)) & 1;
 -}
 -
 -/* Raw read of a coprocessor register (as needed for migration, etc) */
 -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
 -
  /**
   * write_list_to_cpustate
   * @cpu: ARMCPU
 diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/pxa2xx.c
 +++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/cutils.h"
  #include "qemu/log.h"
  #include "qom/object.h"
 +#include "target/arm/cpregs.h"
  static struct {
      hwaddr io_base;
 diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/pxa2xx_pic.c
 +++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/sysbus.h"
  #include "migration/vmstate.h"
  #include "qom/object.h"
 +#include "target/arm/cpregs.h"
  #define ICIP    0x00    /* Interrupt Controller IRQ Pending register */
  #define ICMR    0x04    /* Interrupt Controller Mask register */
 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/arm_gicv3_cpuif.c
 +++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@
  #include "gicv3_internal.h"
  #include "hw/irq.h"
  #include "cpu.h"
 +#include "target/arm/cpregs.h"
  /*
   * Special case return value from hppvi_index(); must be larger than
 diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/arm_gicv3_kvm.c
 +++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "vgic_common.h"
  #include "migration/blocker.h"
  #include "qom/object.h"
 +#include "target/arm/cpregs.h"
 +
  #ifdef DEBUG_GICV3_KVM
  #define DPRINTF(fmt, ...) \
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "kvm_arm.h"
  #include "disas/capstone.h"
  #include "fpu/softfloat.h"
 +#include "cpregs.h"
  static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  {
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
-index XXXXXXX..XXXXXXX 100644
++    DeviceClass *dc = DEVICE_CLASS(klass);
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
+     k->realize = max1111_realize;
-@@ -XXX,XX +XXX,XX @@
++    device_class_set_props(dc, max1111_properties);
- #include "hvf_arm.h"
+ }
- #include "qapi/visitor.h"
- #include "hw/qdev-properties.h"
+ static const TypeInfo max1111_info = {
 +#include "cpregs.h"
  #ifndef CONFIG_USER_ONLY
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/boards.h"
  #endif
 +#include "cpregs.h"
  /* CPU models. These are not needed for the AArch64 linux-user build. */
  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
  #include "cpu.h"
 -#include "internals.h"
  #include "exec/gdbstub.h"
 +#include "internals.h"
 +#include "cpregs.h"
  typedef struct RegisterSysregXmlParam {
      CPUState *cs;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #include "semihosting/common-semi.h"
  #endif
 +#include "cpregs.h"
  #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/op_helper.c
 +++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "internals.h"
  #include "exec/exec-all.h"
  #include "exec/cpu_ldst.h"
 +#include "cpregs.h"
  #define SIGNBIT (uint32_t)0x80000000
  #define SIGNBIT64 ((uint64_t)1 << 63)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@
  #include "translate.h"
  #include "internals.h"
  #include "qemu/host-utils.h"
 -
  #include "semihosting/semihost.h"
  #include "exec/gen-icount.h"
 -
  #include "exec/helper-proto.h"
  #include "exec/helper-gen.h"
  #include "exec/log.h"
 -
 +#include "cpregs.h"
  #include "translate-a64.h"
  #include "qemu/atomic128.h"
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/bitops.h"
  #include "arm_ldst.h"
  #include "semihosting/semihost.h"
 -
  #include "exec/helper-proto.h"
  #include "exec/helper-gen.h"
 -
  #include "exec/log.h"
 +#include "cpregs.h"
  #define ENABLE_ARCH_4T    arm_dc_feature(s, ARM_FEATURE_V4T)
 --
-.25.1
+.20.1

-New patch
+[PULL 23/34] hw/misc/max111x: Don't use vmstate_register()
+The max111x is a proper qdev device; we can use dc->vmsd rather than
+directly calling vmstate_register().
+It's possible that this is a migration compat break, but the only
+boards that use this device are the spitz-family ('akita', 'borzoi',
+'spitz', 'terrier').
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-8-peter.maydell@linaro.org
+---
+ hw/misc/max111x.c | 3 +--
+file changed, 1 insertion(+), 2 deletions(-)
+diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/misc/max111x.c
++++ b/hw/misc/max111x.c
+@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
+     s->inputs = inputs;
+-    vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
+-                     &vmstate_max111x, s);
+     return 0;
+ }
+@@ -XXX,XX +XXX,XX @@ static void max111x_class_init(ObjectClass *klass, void *data)
+     k->transfer = max111x_transfer;
+     dc->reset = max111x_reset;
++    dc->vmsd = &vmstate_max111x;
+ }
+ static const TypeInfo max111x_info = {
+--
+.20.1

-New patch
+[PULL 24/34] ssi: Add ssi_realize_and_unref()
+Add an ssi_realize_and_unref(), for the benefit of callers
+who want to be able to create an SSI device, set QOM properties
+on it, and then do the realize-and-unref afterwards.
+The API works on the same principle as the recently added
+qdev_realize_and_undef(), sysbus_realize_and_undef(), etc.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-9-peter.maydell@linaro.org
+---
+ include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++
+ hw/ssi/ssi.c         |  7 ++++++-
+files changed, 32 insertions(+), 1 deletion(-)
+diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/ssi/ssi.h
++++ b/include/hw/ssi/ssi.h
+@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ssi_slave;
+ }
+ DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
++/**
++ * ssi_realize_and_unref: realize and unref an SSI slave device
++ * @dev: SSI slave device to realize
++ * @bus: SSI bus to put it on
++ * @errp: error pointer
++ *
++ * Call 'realize' on @dev, put it on the specified @bus, and drop the
++ * reference to it. Errors are reported via @errp and by returning
++ * false.
++ *
++ * This function is useful if you have created @dev via qdev_new()
++ * (which takes a reference to the device it returns to you), so that
++ * you can set properties on it before realizing it. If you don't need
++ * to set properties then ssi_create_slave() is probably better (as it
++ * does the create, init and realize in one step).
++ *
++ * If you are embedding the SSI slave into another QOM device and
++ * initialized it via some variant on object_initialize_child() then
++ * do not use this function, because that family of functions arrange
++ * for the only reference to the child device to be held by the parent
++ * via the child<> property, and so the reference-count-drop done here
++ * would be incorrect.  (Instead you would want ssi_realize(), which
++ * doesn't currently exist but would be trivial to create if we had
++ * any code that wanted it.)
++ */
++bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
+ /* Master interface.  */
+ SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
+diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/ssi.c
++++ b/hw/ssi/ssi.c
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo ssi_slave_info = {
+     .abstract = true,
+ };
++bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
++{
++    return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
++}
++
+ DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
+ {
+     DeviceState *dev = qdev_new(name);
+-    qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal);
++    ssi_realize_and_unref(dev, bus, &error_fatal);
+     return dev;
+ }
+--
+.20.1

-New patch
+[PULL 25/34] hw/arm/spitz: Use max111x properties to set initial values
+Use the new max111x qdev properties to set the initial input
+values rather than calling max111x_set_input(); this means that
+on system reset the inputs will correctly return to their initial
+values.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200628142429.17111-10-peter.maydell@linaro.org
+---
+ hw/arm/spitz.c | 11 +++++++----
+file changed, 7 insertions(+), 4 deletions(-)
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
+                           qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
+     bus = qdev_get_child_bus(sms->mux, "ssi2");
+-    sms->max1111 = ssi_create_slave(bus, "max1111");
++    sms->max1111 = qdev_new("max1111");
+     max1111 = sms->max1111;
+-    max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
+-    max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
+-    max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
++    qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
++                        SPITZ_BATTERY_VOLT);
++    qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
++    qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */,
++                        SPITZ_CHARGEON_ACIN);
++    ssi_realize_and_unref(sms->max1111, bus, &error_fatal);
+     qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
+                         qdev_get_gpio_in(sms->mux, 0));
+--
+.20.1

-[PULL 13/23] target/arm: Merge allocation of the cpreg and its name
+[PULL 26/34] hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
-From: Richard Henderson <richard.henderson@linaro.org>
+The max111x ADC device model allows other code to set the level on
 the 8 ADC inputs using the max111x_set_input() function.  Replace
 this with generic qdev GPIO inputs, which also allow inputs to be set
 to arbitrary values.
-Simplify freeing cp_regs hash table entries by using a single
+Using GPIO lines will make it easier for board code to wire things
-allocation for the entire value.
+up, so that if device A wants to set the ADC input it doesn't need to
 have a direct pointer to the max111x but can just set that value on
 its output GPIO, which is then wired up by the board to the
 appropriate max111x input.
-This fixes a theoretical bug if we were to ever free the entire
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-hash table, because we've been installing string literal constants
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-into the cpreg structure in define_arm_vh_e2h_redirects_aliases.
+Message-id: 20200628142429.17111-11-peter.maydell@linaro.org
-However, at present we only free entries created for AArch32
+---
-wildcard cpregs which get overwritten by more specific cpregs,
+ include/hw/ssi/ssi.h |  3 ---
-so this bug is never exposed.
+ hw/arm/spitz.c       |  9 +++++----
  hw/misc/max111x.c    | 16 +++++++++-------
 files changed, 14 insertions(+), 14 deletions(-)
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20220501055028.646596-13-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.c    | 16 +---------------
  target/arm/helper.c | 10 ++++++++--
 files changed, 9 insertions(+), 17 deletions(-)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/include/hw/ssi/ssi.h
-+++ b/target/arm/cpu.c
++++ b/include/hw/ssi/ssi.h
-@@ -XXX,XX +XXX,XX @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
+@@ -XXX,XX +XXX,XX @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
-     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
  uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
 -/* max111x.c */
 -void max111x_set_input(DeviceState *dev, int line, uint8_t value);
 -
  #endif
 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/spitz.c
 +++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  static void spitz_adc_temp_on(void *opaque, int line, int level)
  {
 +    int batt_temp;
 +
      if (!max1111)
          return;
 -    if (level)
 -        max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
 -    else
 -        max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
 +    batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
 +
 +    qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
  }
--static void cpreg_hashtable_data_destroy(gpointer data)
+ static void corgi_ssp_realize(SSISlave *d, Error **errp)
 diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/max111x.c
 +++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_max111x = {
      }
  };
 +static void max111x_input_set(void *opaque, int line, int value)
 +{
 +    MAX111xState *s = MAX_111X(opaque);
 +
 +    assert(line >= 0 && line < s->inputs);
 +    s->input[line] = value;
 +}
 +
  static int max111x_init(SSISlave *d, int inputs)
  {
      DeviceState *dev = DEVICE(d);
      MAX111xState *s = MAX_111X(dev);
      qdev_init_gpio_out(dev, &s->interrupt, 1);
 +    qdev_init_gpio_in(dev, max111x_input_set, inputs);
      s->inputs = inputs;
@@ -XXX,XX +XXX,XX @@ static void max1111_realize(SSISlave *dev, Error **errp)
      max111x_init(dev, 4);
  }
 -void max111x_set_input(DeviceState *dev, int line, uint8_t value)
 -{
--    /*
+-    MAX111xState *s = MAX_111X(dev);
--     * Destroy function for cpu->cp_regs hashtable data entries.
+-    assert(line >= 0 && line < s->inputs);
--     * We must free the name string because it was g_strdup()ed in
+-    s->input[line] = value;
 -     * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
 -     * from r->name because we know we definitely allocated it.
 -     */
 -    ARMCPRegInfo *r = data;
 -
 -    g_free((void *)r->name);
 -    g_free(r);
 -}
 -
- static void arm_cpu_initfn(Object *obj)
+ static void max111x_reset(DeviceState *dev)
  {
-     ARMCPU *cpu = ARM_CPU(obj);
+     MAX111xState *s = MAX_111X(dev);
      cpu_set_cpustate_pointers(cpu);
      cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
 -                                         NULL, cpreg_hashtable_data_destroy);
 +                                         NULL, g_free);
      QLIST_INIT(&cpu->pre_el_change_hooks);
      QLIST_INIT(&cpu->el_change_hooks);
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
       * add a single reginfo struct to the hash table.
       */
      uint32_t key;
 -    ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
 +    ARMCPRegInfo *r2;
      int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
      int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
 +    size_t name_len;
 +
 +    /* Combine cpreg and name into one allocation. */
 +    name_len = strlen(name) + 1;
 +    r2 = g_malloc(sizeof(*r2) + name_len);
 +    *r2 = *r;
 +    r2->name = memcpy(r2 + 1, name, name_len);
 -    r2->name = g_strdup(name);
      /* Reset the secure state to the specific incoming state.  This is
       * necessary as the register may have been defined with both states.
       */
 --
-.25.1
+.20.1

-[PULL 01/23] target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
+[PULL 27/34] hw/misc/max111x: Create header file for documentation, TYPE_ macros
-From: Richard Henderson <richard.henderson@linaro.org>
+Create a header file for the hw/misc/max111x device, in the
 usual modern style for QOM devices:
  * definition of the TYPE_ constants and macros
  * definition of the device's state struct so that it can
    be embedded in other structs if desired
  * documentation of the interface
-This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
+This allows us to use TYPE_MAX_1111 in the spitz.c code rather
-(indirect branch from register other than x16/x17).  The linux kernel
+than the string "max1111".
 sets this in bti_enable().
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
-[PMM: remove stray change to makefile comment]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200628142429.17111-12-peter.maydell@linaro.org
 ---
- target/arm/cpu.c                  |  2 ++
+ include/hw/misc/max111x.h | 56 +++++++++++++++++++++++++++++++++++++++
- tests/tcg/aarch64/bti-3.c         | 42 +++++++++++++++++++++++++++++++
+ hw/arm/spitz.c            |  3 ++-
- tests/tcg/aarch64/Makefile.target |  6 ++---
+ hw/misc/max111x.c         | 24 +----------------
-files changed, 47 insertions(+), 3 deletions(-)
+ MAINTAINERS               |  1 +
- create mode 100644 tests/tcg/aarch64/bti-3.c
+files changed, 60 insertions(+), 24 deletions(-)
  create mode 100644 include/hw/misc/max111x.h
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
          /* Enable all PAC keys.  */
          env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
                                    SCTLR_EnDA | SCTLR_EnDB);
 +        /* Trap on btype=3 for PACIxSP. */
 +        env->cp15.sctlr_el[1] |= SCTLR_BT0;
          /* and to the FP/Neon instructions */
          env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
          /* and to the SVE instructions */
 diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/tests/tcg/aarch64/bti-3.c
++++ b/include/hw/misc/max111x.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * BTI vs PACIASP
++ * Maxim MAX1110/1111 ADC chip emulation.
 + *
 + * Copyright (c) 2006 Openedhand Ltd.
 + * Written by Andrzej Zaborowski <balrog@zabor.org>
 + *
 + * This code is licensed under the GNU GPLv2.
 + *
 + * Contributions after 2012-01-13 are licensed under the terms of the
 + * GNU GPL, version 2 or (at your option) any later version.
 + */
 +
-+#include "bti-crt.inc.c"
++#ifndef HW_MISC_MAX111X_H
 +#define HW_MISC_MAX111X_H
 +
-+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
++#include "hw/ssi/ssi.h"
 +{
 +    uc->uc_mcontext.pc += 8;
 +    uc->uc_mcontext.pstate = 1;
 +}
 +
-+#define BTYPE_1() \
++/*
-+    asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
++ * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
-+        : "=r"(skipped) : : "x16", "x30")
++ * is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
 + * 8-bit ADC channels.
 + *
 + * QEMU interface:
 + *  + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
 + *    of each ADC input, as an unsigned 8-bit value
 + *  + GPIO output 0: interrupt line
 + *  + Properties "input0" to "input3" (max1110) or "input0" to "input7"
 + *    (max1111): initial reset values for ADC inputs.
 + *
 + * Known bugs:
 + *  + the interrupt line is not correctly implemented, and will never
 + *    be lowered once it has been asserted.
 + */
 +typedef struct {
 +    SSISlave parent_obj;
 +
-+#define BTYPE_2() \
++    qemu_irq interrupt;
-+    asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
++    /* Values of inputs at system reset (settable by QOM property) */
-+        : "=r"(skipped) : : "x16", "x30")
++    uint8_t reset_input[8];
 +
-+#define BTYPE_3() \
++    uint8_t tb1, rb2, rb3;
-+    asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
++    int cycle;
 +        : "=r"(skipped) : : "x15", "x30")
 +
-+#define TEST(WHICH, EXPECT) \
++    uint8_t input[8];
-+    do { WHICH(); fail += skipped ^ EXPECT; } while (0)
++    int inputs, com;
 +} MAX111xState;
 +
-+int main()
++#define TYPE_MAX_111X "max111x"
 +{
 +    int fail = 0;
 +    int skipped;
 +
-+    /* Signal-like with SA_SIGINFO.  */
++#define MAX_111X(obj) \
-+    signal_info(SIGILL, skip2_sigill);
++    OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
 +
-+    /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
++#define TYPE_MAX_1110 "max1110"
-+    TEST(BTYPE_1, 0);
++#define TYPE_MAX_1111 "max1111"
 +    TEST(BTYPE_2, 0);
 +    TEST(BTYPE_3, 1);
 +
-+    return fail;
++#endif
-+}
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
 index XXXXXXX..XXXXXXX 100644
---- a/tests/tcg/aarch64/Makefile.target
+--- a/hw/arm/spitz.c
-+++ b/tests/tcg/aarch64/Makefile.target
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ endif
+@@ -XXX,XX +XXX,XX @@
- # BTI Tests
+ #include "audio/audio.h"
- # bti-1 tests the elf notes, so we require special compiler support.
+ #include "hw/boards.h"
- ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
+ #include "hw/sysbus.h"
--AARCH64_TESTS += bti-1
++#include "hw/misc/max111x.h"
--bti-1: CFLAGS += -mbranch-protection=standard
+ #include "migration/vmstate.h"
--bti-1: LDFLAGS += -nostdlib
+ #include "exec/address-spaces.h"
-+AARCH64_TESTS += bti-1 bti-3
+ #include "cpu.h"
-+bti-1 bti-3: CFLAGS += -mbranch-protection=standard
+@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
-+bti-1 bti-3: LDFLAGS += -nostdlib
+                           qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
- endif
- # bti-2 tests PROT_BTI, so no special compiler support required.
+     bus = qdev_get_child_bus(sms->mux, "ssi2");
- AARCH64_TESTS += bti-2
+-    sms->max1111 = qdev_new("max1111");
 +    sms->max1111 = qdev_new(TYPE_MAX_1111);
      max1111 = sms->max1111;
      qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
                          SPITZ_BATTERY_VOLT);
 diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/max111x.c
 +++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
 +#include "hw/misc/max111x.h"
  #include "hw/irq.h"
 -#include "hw/ssi/ssi.h"
  #include "migration/vmstate.h"
  #include "qemu/module.h"
  #include "hw/qdev-properties.h"
 -typedef struct {
 -    SSISlave parent_obj;
 -
 -    qemu_irq interrupt;
 -    /* Values of inputs at system reset (settable by QOM property) */
 -    uint8_t reset_input[8];
 -
 -    uint8_t tb1, rb2, rb3;
 -    int cycle;
 -
 -    uint8_t input[8];
 -    int inputs, com;
 -} MAX111xState;
 -
 -#define TYPE_MAX_111X "max111x"
 -
 -#define MAX_111X(obj) \
 -    OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
 -
 -#define TYPE_MAX_1110 "max1110"
 -#define TYPE_MAX_1111 "max1111"
 -
  /* Control-byte bitfields */
  #define CB_PD0        (1 << 0)
  #define CB_PD1        (1 << 1)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/gpio/max7310.c
  F: hw/gpio/zaurus.c
  F: hw/misc/mst_fpga.c
  F: hw/misc/max111x.c
 +F: include/hw/misc/max111x.h
  F: include/hw/arm/pxa.h
  F: include/hw/arm/sharpsl.h
  F: include/hw/display/tc6393xb.h
 --
-.25.1
+.20.1

-[PULL 12/23] target/arm: Store cpregs key in the hash table directly
+[PULL 28/34] hw/arm/spitz: Encapsulate misc GPIO handling in a device
-From: Richard Henderson <richard.henderson@linaro.org>
+Currently we have a free-floating set of IRQs and a function
+spitz_out_switch() which handle some miscellaneous GPIO lines for the
-Cast the uint32_t key into a gpointer directly, which
+spitz board.  Encapsulate this behaviour in a simple QOM device.
-allows us to avoid allocating storage for each key.
+At this point we can finally remove the 'max1111' global, because the
-Use g_hash_table_lookup when we already have a gpointer
+ADC battery-temperature value is now handled by the misc-gpio device
-(e.g. for callbacks like count_cpreg), or when using
+writing the value to its outbound "adc-temp" GPIO, which the board
-get_arm_cp_reginfo would require casting away const.
+code wires up to the appropriate inbound GPIO line on the max1111.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+This commit also fixes Coverity issue CID 1421913 (which pointed out
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+that the 'outsignals' in spitz_scoop_gpio_setup() were leaked),
-Message-id: 20220501055028.646596-12-richard.henderson@linaro.org
+because it removes the use of the qemu_allocate_irqs() API from this
 code entirely.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-13-peter.maydell@linaro.org
 ---
- target/arm/cpu.c     |  4 ++--
+ hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++----------------
- target/arm/gdbstub.c |  2 +-
+file changed, 87 insertions(+), 42 deletions(-)
- target/arm/helper.c  | 41 ++++++++++++++++++-----------------------
-files changed, 21 insertions(+), 26 deletions(-)
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/hw/arm/spitz.c
-+++ b/target/arm/cpu.c
++++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ typedef struct {
-     ARMCPU *cpu = ARM_CPU(obj);
+     DeviceState *max1111;
+     DeviceState *scp0;
-     cpu_set_cpustate_pointers(cpu);
+     DeviceState *scp1;
--    cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
++    DeviceState *misc_gpio;
--                                         g_free, cpreg_hashtable_data_destroy);
+ } SpitzMachineState;
-+    cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
-+                                         NULL, cpreg_hashtable_data_destroy);
+ #define TYPE_SPITZ_MACHINE "spitz-common"
+@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
-     QLIST_INIT(&cpu->pre_el_change_hooks);
+ #define SPITZ_GPIO_MAX1111_CS   20
-     QLIST_INIT(&cpu->el_change_hooks);
+ #define SPITZ_GPIO_TP_INT       11
-diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
-index XXXXXXX..XXXXXXX 100644
+-static DeviceState *max1111;
---- a/target/arm/gdbstub.c
+-
-+++ b/target/arm/gdbstub.c
+ /* "Demux" the signal based on current chipselect */
-@@ -XXX,XX +XXX,XX @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
+ typedef struct {
- static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
+     SSISlave ssidev;
-                                         gpointer p)
+@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
- {
+ #define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
--    uint32_t ri_key = *(uint32_t *)key;
+ #define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
-+    uint32_t ri_key = (uintptr_t)key;
-     ARMCPRegInfo *ri = value;
+-static void spitz_adc_temp_on(void *opaque, int line, int level)
-     RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
+-{
-     GString *s = param->s;
+-    int batt_temp;
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+-
-index XXXXXXX..XXXXXXX 100644
+-    if (!max1111)
---- a/target/arm/helper.c
+-        return;
-+++ b/target/arm/helper.c
+-
-@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
+-    batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
- static void add_cpreg_to_list(gpointer key, gpointer opaque)
+-
- {
+-    qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
-     ARMCPU *cpu = opaque;
+-}
--    uint64_t regidx;
+-
--    const ARMCPRegInfo *ri;
+ static void corgi_ssp_realize(SSISlave *d, Error **errp)
--
+ {
--    regidx = *(uint32_t *)key;
+     DeviceState *dev = DEVICE(d);
--    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
-+    uint32_t regidx = (uintptr_t)key;
-+    const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+     bus = qdev_get_child_bus(sms->mux, "ssi2");
+     sms->max1111 = qdev_new(TYPE_MAX_1111);
-     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
+-    max1111 = sms->max1111;
-         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
+     qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
+                         SPITZ_BATTERY_VOLT);
- static void count_cpreg(gpointer key, gpointer opaque)
+     qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
- {
+@@ -XXX,XX +XXX,XX @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu)
-     ARMCPU *cpu = opaque;
--    uint64_t regidx;
+ /* Other peripherals */
-     const ARMCPRegInfo *ri;
+-static void spitz_out_switch(void *opaque, int line, int level)
--    regidx = *(uint32_t *)key;
++/*
--    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
++ * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards.
-+    ri = g_hash_table_lookup(cpu->cp_regs, key);
++ *
++ * QEMU interface:
-     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
++ *  + named GPIO inputs "green-led", "orange-led", "charging", "discharging":
-         cpu->cpreg_array_len++;
++ *    these currently just print messages that the line has been signalled
-@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
++ *  + named GPIO input "adc-temp-on": set to cause the battery-temperature
++ *    value to be passed to the max111x ADC
- static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
++ *  + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
- {
++ */
--    uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
++#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
--    uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
++#define SPITZ_MISC_GPIO(obj) \
-+    uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a);
++    OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
-+    uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b);
++
++typedef struct SpitzMiscGPIOState {
-     if (aidx > bidx) {
++    SysBusDevice parent_obj;
-         return 1;
++
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
++    qemu_irq adc_value;
-     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
++} SpitzMiscGPIOState;
-         const struct E2HAlias *a = &aliases[i];
++
-         ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
++static void spitz_misc_charging(void *opaque, int n, int level)
--        uint32_t *new_key;
+ {
-         bool ok;
+-    switch (line) {
+-    case 0:
-         if (a->feature && !a->feature(&cpu->isar)) {
+-        zaurus_printf("Charging %s.\n", level ? "off" : "on");
-             continue;
+-        break;
-         }
+-    case 1:
+-        zaurus_printf("Discharging %s.\n", level ? "on" : "off");
--        src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
+-        break;
--        dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
+-    case 2:
-+        src_reg = g_hash_table_lookup(cpu->cp_regs,
+-        zaurus_printf("Green LED %s.\n", level ? "on" : "off");
-+                                      (gpointer)(uintptr_t)a->src_key);
+-        break;
-+        dst_reg = g_hash_table_lookup(cpu->cp_regs,
+-    case 3:
-+                                      (gpointer)(uintptr_t)a->dst_key);
+-        zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
-         g_assert(src_reg != NULL);
+-        break;
-         g_assert(dst_reg != NULL);
+-    case 6:
+-        spitz_adc_temp_on(opaque, line, level);
-@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
+-        break;
+-    default:
-         /* Create alias before redirection so we dup the right data. */
+-        g_assert_not_reached();
-         new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
+-    }
--        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
++    zaurus_printf("Charging %s.\n", level ? "off" : "on");
++}
-         new_reg->name = a->new_name;
++
-         new_reg->type |= ARM_CP_ALIAS;
++static void spitz_misc_discharging(void *opaque, int n, int level)
-         /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
++{
-         new_reg->access &= PL2_RW | PL3_RW;
++    zaurus_printf("Discharging %s.\n", level ? "off" : "on");
++}
--        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
++
-+        ok = g_hash_table_insert(cpu->cp_regs,
++static void spitz_misc_green_led(void *opaque, int n, int level)
-+                                 (gpointer)(uintptr_t)a->new_key, new_reg);
++{
-         g_assert(ok);
++    zaurus_printf("Green LED %s.\n", level ? "off" : "on");
++}
-         src_reg->opaque = dst_reg;
++
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++static void spitz_misc_orange_led(void *opaque, int n, int level)
-     /* Private utility function for define_one_arm_cp_reg_with_opaque():
++{
-      * add a single reginfo struct to the hash table.
++    zaurus_printf("Orange LED %s.\n", level ? "off" : "on");
-      */
++}
--    uint32_t *key = g_new(uint32_t, 1);
++
-+    uint32_t key;
++static void spitz_misc_adc_temp(void *opaque, int n, int level)
-     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
++{
-     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
++    SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque);
-     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
++    int batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
++
-         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
++    qemu_set_irq(s->adc_value, batt_temp);
-             r2->cp = CP_REG_ARM64_SYSREG_CP;
++}
-         }
++
--        *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
++static void spitz_misc_gpio_init(Object *obj)
--                                  r2->opc0, opc1, opc2);
++{
-+        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
++    SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj);
-+                                 r2->opc0, opc1, opc2);
++    DeviceState *dev = DEVICE(obj);
-     } else {
++
--        *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
++    qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1);
-+        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
++    qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1);
 +    qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1);
 +    qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1);
 +    qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1);
 +
 +    qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1);
  }
  #define SPITZ_SCP_LED_GREEN             1
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
  static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
  {
 -    qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
 +    DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL);
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
 -    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
 +    sms->misc_gpio = miscdev;
 +
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON,
 +                          qdev_get_gpio_in_named(miscdev, "charging", 0));
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B,
 +                          qdev_get_gpio_in_named(miscdev, "discharging", 0));
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN,
 +                          qdev_get_gpio_in_named(miscdev, "green-led", 0));
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE,
 +                          qdev_get_gpio_in_named(miscdev, "orange-led", 0));
 +    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON,
 +                          qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0));
 +    qdev_connect_gpio_out_named(miscdev, "adc-temp", 0,
 +                                qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP));
      if (sms->scp1) {
          qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
          qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
                                qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
      }
-     if (opaque) {
+-
-         r2->opaque = opaque;
+-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
       * requested.
       */
      if (!(r->type & ARM_CP_OVERRIDE)) {
 -        ARMCPRegInfo *oldreg;
 -        oldreg = g_hash_table_lookup(cpu->cp_regs, key);
 +        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
          if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
              fprintf(stderr, "Register redefined: cp=%d %d bit "
                      "crn=%d crm=%d opc1=%d opc2=%d, "
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
              g_assert_not_reached();
          }
      }
 -    g_hash_table_insert(cpu->cp_regs, key, r2);
 +    g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
  }
+ #define SPITZ_GPIO_HSYNC                22
-@@ -XXX,XX +XXX,XX @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo spitz_lcdtg_info = {
+     .class_init    = spitz_lcdtg_class_init,
- const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
+ };
- {
--    return g_hash_table_lookup(cpregs, &encoded_cp);
++static const TypeInfo spitz_misc_gpio_info = {
-+    return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp);
++    .name = TYPE_SPITZ_MISC_GPIO,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(SpitzMiscGPIOState),
 +    .instance_init = spitz_misc_gpio_init,
 +    /*
 +     * No class_init required: device has no internal state so does not
 +     * need to set up reset or vmstate, and does not have a realize method.
 +     */
 +};
 +
  static void spitz_register_types(void)
  {
      type_register_static(&corgi_ssp_info);
      type_register_static(&spitz_lcdtg_info);
      type_register_static(&spitz_keyboard_info);
      type_register_static(&sl_nand_info);
 +    type_register_static(&spitz_misc_gpio_info);
  }
- void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
+ type_init(spitz_register_types)
 --
-.25.1
+.20.1

-[PULL 03/23] target/arm: Reorg CPAccessResult and access_check_cp_reg
+[PULL 29/34] hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
-From: Richard Henderson <richard.henderson@linaro.org>
+Instead of logging guest accesses to invalid register offsets in this
 device using zaurus_printf() (which just prints to stderr), use the
 usual qemu_log_mask(LOG_GUEST_ERROR,...).
-Rearrange the values of the enumerators of CPAccessResult
+Since this was the only use of the zaurus_printf() macro outside
-so that we may directly extract the target el. For the two
+spitz.c, we can move the definition of that macro from sharpsl.h
-special cases in access_check_cp_reg, use CPAccessResult.
+to spitz.c.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220501055028.646596-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-14-peter.maydell@linaro.org
 ---
- target/arm/cpregs.h    | 26 ++++++++++++--------
+ include/hw/arm/sharpsl.h |  3 ---
- target/arm/op_helper.c | 56 +++++++++++++++++++++---------------------
+ hw/arm/spitz.c           |  3 +++
-files changed, 44 insertions(+), 38 deletions(-)
+ hw/gpio/zaurus.c         | 12 +++++++-----
 files changed, 10 insertions(+), 8 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/include/hw/arm/sharpsl.h
-+++ b/target/arm/cpregs.h
++++ b/include/hw/arm/sharpsl.h
-@@ -XXX,XX +XXX,XX @@ static inline bool cptype_valid(int cptype)
+@@ -XXX,XX +XXX,XX @@
- typedef enum CPAccessResult {
-     /* Access is permitted */
+ #include "exec/hwaddr.h"
-     CP_ACCESS_OK = 0,
 -#define zaurus_printf(format, ...)    \
 -    fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
 -
  /* zaurus.c */
  #define SL_PXA_PARAM_BASE    0xa0000a00
 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/spitz.c
 +++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
  #define SPITZ_MACHINE_CLASS(klass) \
      OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
 +#define zaurus_printf(format, ...)                              \
 +    fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
 +
-+    /*
+ #undef REG_FMT
-+     * Combined with one of the following, the low 2 bits indicate the
+ #define REG_FMT                         "0x%02lx"
-+     * target exception level.  If 0, the exception is taken to the usual
-+     * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
+diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c
 +     */
 +    CP_ACCESS_EL_MASK = 3,
 +
      /*
       * Access fails due to a configurable trap or enable which would
       * result in a categorized exception syndrome giving information about
       * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
 -     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
 -     * PL1 if in EL0, otherwise to the current EL).
 +     * 0xc or 0x18).
       */
 -    CP_ACCESS_TRAP = 1,
 +    CP_ACCESS_TRAP = (1 << 2),
 +    CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
 +    CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
 +
      /*
       * Access fails and results in an exception syndrome 0x0 ("uncategorized").
       * Note that this is not a catch-all case -- the set of cases which may
       * result in this failure is specifically defined by the architecture.
       */
 -    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
 -    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
 -    CP_ACCESS_TRAP_EL2 = 3,
 -    CP_ACCESS_TRAP_EL3 = 4,
 -    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
 -    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
 -    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
 +    CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
 +    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
 +    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
  } CPAccessResult;
  typedef struct ARMCPRegInfo ARMCPRegInfo;
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/op_helper.c
+--- a/hw/gpio/zaurus.c
-+++ b/target/arm/op_helper.c
++++ b/hw/gpio/zaurus.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
+@@ -XXX,XX +XXX,XX @@
-                                  uint32_t isread)
+ #include "hw/sysbus.h"
- {
+ #include "migration/vmstate.h"
-     const ARMCPRegInfo *ri = rip;
+ #include "qemu/module.h"
-+    CPAccessResult res = CP_ACCESS_OK;
+-
-     int target_el;
+-#undef REG_FMT
+-#define REG_FMT            "0x%02lx"
-     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
++#include "qemu/log.h"
-         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
--        raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
+ /* SCOOP devices */
-+        res = CP_ACCESS_TRAP;
-+        goto fail;
+@@ -XXX,XX +XXX,XX @@ static uint64_t scoop_read(void *opaque, hwaddr addr,
      case SCOOP_GPRR:
          return s->gpio_level;
      default:
 -        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n",
 +                      addr);
      }
-     /*
+     return 0;
-@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
+@@ -XXX,XX +XXX,XX @@ static void scoop_write(void *opaque, hwaddr addr,
-         mask &= ~((1 << 4) | (1 << 14));
+         scoop_gpio_handler_update(s);
          if (env->cp15.hstr_el2 & mask) {
 -            target_el = 2;
 -            goto exept;
 +            res = CP_ACCESS_TRAP_EL2;
 +            goto fail;
          }
      }
 -    if (!ri->accessfn) {
 +    if (ri->accessfn) {
 +        res = ri->accessfn(env, ri, isread);
 +    }
 +    if (likely(res == CP_ACCESS_OK)) {
          return;
      }
 -    switch (ri->accessfn(env, ri, isread)) {
 -    case CP_ACCESS_OK:
 -        return;
 + fail:
 +    switch (res & ~CP_ACCESS_EL_MASK) {
      case CP_ACCESS_TRAP:
 -        target_el = exception_target_el(env);
 -        break;
 -    case CP_ACCESS_TRAP_EL2:
 -        /* Requesting a trap to EL2 when we're in EL3 is
 -         * a bug in the access function.
 -         */
 -        assert(arm_current_el(env) != 3);
 -        target_el = 2;
 -        break;
 -    case CP_ACCESS_TRAP_EL3:
 -        target_el = 3;
          break;
      case CP_ACCESS_TRAP_UNCATEGORIZED:
 -        target_el = exception_target_el(env);
 -        syndrome = syn_uncategorized();
 -        break;
 -    case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
 -        target_el = 2;
 -        syndrome = syn_uncategorized();
 -        break;
 -    case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
 -        target_el = 3;
          syndrome = syn_uncategorized();
          break;
      default:
-         g_assert_not_reached();
+-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n",
 +                      addr);
      }
--exept:
-+    target_el = res & CP_ACCESS_EL_MASK;
-+    switch (target_el) {
-+    case 0:
-+        target_el = exception_target_el(env);
-+        break;
-+    case 2:
-+        assert(arm_current_el(env) != 3);
-+        assert(arm_is_el2_enabled(env));
-+        break;
-+    case 3:
-+        assert(arm_feature(env, ARM_FEATURE_EL3));
-+        break;
-+    default:
-+        /* No "direct" traps to EL1 */
-+        g_assert_not_reached();
-+    }
-+
-     raise_exception(env, EXCP_UDEF, syndrome, target_el);
  }
 --
-.25.1
+.20.1

-New patch
+[PULL 30/34] hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
+Instead of logging guest accesses to invalid register offsets in the
+Spitz flash device with zaurus_printf() (which just prints to stderr),
+use the usual qemu_log_mask(LOG_GUEST_ERROR,...).
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-15-peter.maydell@linaro.org
+---
+ hw/arm/spitz.c | 12 +++++++-----
+file changed, 7 insertions(+), 5 deletions(-)
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/ssi/ssi.h"
+ #include "hw/block/flash.h"
+ #include "qemu/timer.h"
++#include "qemu/log.h"
+ #include "hw/arm/sharpsl.h"
+ #include "ui/console.h"
+ #include "hw/audio/wm8750.h"
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+ #define zaurus_printf(format, ...)                              \
+     fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
+-#undef REG_FMT
+-#define REG_FMT                         "0x%02lx"
+-
+ /* Spitz Flash */
+ #define FLASH_BASE              0x0c000000
+ #define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
+@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
+         return ecc_digest(&s->ecc, nand_getio(s->nand));
+     default:
+-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n",
++                      addr);
+     }
+     return 0;
+ }
+@@ -XXX,XX +XXX,XX @@ static void sl_write(void *opaque, hwaddr addr,
+         break;
+     default:
+-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n",
++                      addr);
+     }
+ }
+--
+.20.1

-[PULL 04/23] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
+[PULL 31/34] hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
-From: Richard Henderson <richard.henderson@linaro.org>
+Instead of using printf() for logging guest accesses to invalid
 register offsets in the pxa2xx PIC device, use the usual
 qemu_log_mask(LOG_GUEST_ERROR,...).
-Remove a possible source of error by removing REGINFO_SENTINEL
+This was the only user of the REG_FMT macro in pxa.h, so we can
-and using ARRAY_SIZE (convinently hidden inside a macro) to
+remove that.
 find the end of the set of regs being registered or modified.
-The space saved by not having the extra array element reduces
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-the executable's .data.rel.ro section by about 9k.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20200628142429.17111-16-peter.maydell@linaro.org
 ---
  include/hw/arm/pxa.h | 1 -
  hw/arm/pxa2xx_pic.c  | 9 +++++++--
 files changed, 7 insertions(+), 3 deletions(-)
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220501055028.646596-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpregs.h       |  53 +++++++++---------
  hw/arm/pxa2xx.c           |   1 -
  hw/arm/pxa2xx_pic.c       |   1 -
  hw/intc/arm_gicv3_cpuif.c |   5 --
  hw/intc/arm_gicv3_kvm.c   |   1 -
  target/arm/cpu64.c        |   1 -
  target/arm/cpu_tcg.c      |   4 --
  target/arm/helper.c       | 111 ++++++++------------------------------
 files changed, 48 insertions(+), 129 deletions(-)
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/include/hw/arm/pxa.h
-+++ b/target/arm/cpregs.h
++++ b/include/hw/arm/pxa.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
  #define ARM_CP_NO_GDB            0x4000
  #define ARM_CP_RAISES_EXC        0x8000
  #define ARM_CP_NEWEL             0x10000
 -/* Used only as a terminator for ARMCPRegInfo lists */
 -#define ARM_CP_SENTINEL          0xfffff
  /* Mask of only the flag bits in a type field */
  #define ARM_CP_FLAG_MASK         0x1f0ff
@@ -XXX,XX +XXX,XX @@ enum {
      ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
  };
--/*
+ # define PA_FMT            "0x%08lx"
-- * Return true if cptype is a valid type field. This is used to try to
+-# define REG_FMT        "0x" TARGET_FMT_plx
-- * catch errors where the sentinel has been accidentally left off the end
-- * of a list of registers.
+ PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
-- */
+                          const char *revision);
 -static inline bool cptype_valid(int cptype)
 -{
 -    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 -        || ((cptype & ARM_CP_SPECIAL) &&
 -            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 -}
 -
  /*
   * Access rights:
   * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
  #define CPREG_FIELD64(env, ri) \
      (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 -#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
 +                                       void *opaque);
 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 -                                    const ARMCPRegInfo *regs, void *opaque);
 -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 -                                       const ARMCPRegInfo *regs, void *opaque);
 -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 -{
 -    define_arm_cp_regs_with_opaque(cpu, regs, 0);
 -}
  static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
  {
 -    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 +    define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
  }
 +
 +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
 +                                        void *opaque, size_t len);
 +
 +#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE)               \
 +    do {                                                                \
 +        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
 +        define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE,           \
 +                                           ARRAY_SIZE(REGS));           \
 +    } while (0)
 +
 +#define define_arm_cp_regs(CPU, REGS) \
 +    define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
 +
  const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
  /*
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCPRegUserSpaceInfo {
      uint64_t fixed_bits;
  } ARMCPRegUserSpaceInfo;
 -#define REGUSERINFO_SENTINEL { .name = NULL }
 +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
 +                                 const ARMCPRegUserSpaceInfo *mods,
 +                                 size_t mods_len);
 -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
 +#define modify_arm_cp_regs(REGS, MODS)                                  \
 +    do {                                                                \
 +        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
 +        QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0);                       \
 +        modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS),             \
 +                                    MODS, ARRAY_SIZE(MODS));            \
 +    } while (0)
  /* CPWriteFn that can be used to implement writes-ignored behaviour */
  void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/pxa2xx.c
 +++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
      { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
        .access = PL1_RW, .type = ARM_CP_IO,
        .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
 -    REGINFO_SENTINEL
  };
  static void pxa2xx_setup_cp14(PXA2xxState *s)
 diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/pxa2xx_pic.c
 +++ b/hw/arm/pxa2xx_pic.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@
-     REGINFO_FOR_PIC_CP("ICLR2", 8),
+ #include "qemu/osdep.h"
-     REGINFO_FOR_PIC_CP("ICFP2", 9),
+ #include "qapi/error.h"
-     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
+ #include "qemu/module.h"
--    REGINFO_SENTINEL
++#include "qemu/log.h"
- };
+ #include "cpu.h"
+ #include "hw/arm/pxa.h"
- static const MemoryRegionOps pxa2xx_pic_ops = {
+ #include "hw/sysbus.h"
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
-index XXXXXXX..XXXXXXX 100644
+     case ICHP:    /* Highest Priority register */
---- a/hw/intc/arm_gicv3_cpuif.c
+         return pxa2xx_pic_highest(s);
-+++ b/hw/intc/arm_gicv3_cpuif.c
+     default:
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
+-        printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
-       .readfn = icc_igrpen1_el3_read,
++        qemu_log_mask(LOG_GUEST_ERROR,
-       .writefn = icc_igrpen1_el3_write,
++                      "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
-     },
++                      "\n", offset);
--    REGINFO_SENTINEL
+         return 0;
  };
  static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = {
        .readfn = ich_vmcr_read,
        .writefn = ich_vmcr_write,
      },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
        .readfn = ich_ap_read,
        .writefn = ich_ap_write,
      },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
        .readfn = ich_ap_read,
        .writefn = ich_ap_write,
      },
 -    REGINFO_SENTINEL
  };
  static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
                        .readfn = ich_lr_read,
                        .writefn = ich_lr_write,
                      },
 -                    REGINFO_SENTINEL
                  };
                  define_arm_cp_regs(cpu, lr_regset);
              }
 diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/arm_gicv3_kvm.c
 +++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
         */
        .resetfn = arm_gicv3_icc_reset,
      },
 -    REGINFO_SENTINEL
  };
  /**
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
      { .name = "L2MERRSR",
        .cp = 15, .opc1 = 3, .crm = 15,
        .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void aarch64_a57_initfn(Object *obj)
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void cortex_a8_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
        .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
      { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
        .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 -    REGINFO_SENTINEL
  };
  static void cortex_a9_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
  #endif
      { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void cortex_a7_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
        .access = PL1_RW, .type = ARM_CP_CONST },
      { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
        .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static void cortex_r5_initfn(Object *obj)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
        .secure = ARM_CP_SECSTATE_S,
        .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
        .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
      { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
        .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
        .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v6_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
       */
      { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
        .access = PL1_W, .type = ARM_CP_WFI },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo not_v7_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
        .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
      { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
        .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
        .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
        .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
        .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
 -    REGINFO_SENTINEL
  };
  typedef struct pm_event {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
        .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
        .writefn = tlbimvaa_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo v7mp_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
      { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
        .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
        .writefn = tlbimvaa_is_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
        .writefn = pmovsset_write,
        .raw_writefn = raw_write },
 -    REGINFO_SENTINEL
  };
  static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
      { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
        .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
        .accessfn = teehbr_access, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo v6k_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
        .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
                               offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
        .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
      },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
        .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .readfn = gt_virt_cnt_read,
      },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
        .access = PL1_W, .accessfn = ats_access,
        .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
  #endif
 -    REGINFO_SENTINEL
  };
  /* Return basic MPU access permission bits.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
        .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
        .writefn = pmsav7_rgnr_write,
        .resetfn = arm_cp_reset_ignore },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
      { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
        .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
        .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
 -    REGINFO_SENTINEL
  };
  static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
        .access = PL1_RW, .accessfn = access_tvm_trvm,
        .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
        .resetvalue = 0, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo vmsa_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
        /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
                               offsetof(CPUARMState, cp15.tcr_el[1])} },
 -    REGINFO_SENTINEL
  };
  /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
      { .name = "C9", .cp = 15, .crn = 9,
        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
        .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
      { .name = "XSCALE_UNLOCK_DCACHE",
        .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
        .access = PL1_RW,
        .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
      { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
        .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
        .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
      { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
        .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
      { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
        .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
        .resetvalue = (1 << 30) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo strongarm_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
        .access = PL1_RW, .resetvalue = 0,
        .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
 -    REGINFO_SENTINEL
  };
  static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                               offsetof(CPUARMState, cp15.ttbr1_ns) },
        .writefn = vmsa_ttbr_write, },
 -    REGINFO_SENTINEL
  };
  static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
        .writefn = sdcr_write,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
 -    REGINFO_SENTINEL
  };
  /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
        .type = ARM_CP_CONST,
        .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
        .access = PL2_RW, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  /* Ditto, but for registers which exist in ARMv8 but not v7 */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
        .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
        .access = PL2_RW,
        .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
        .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
        .access = PL2_RW,
        .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
        .access = PL2_RW,
        .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
        .writefn = hcr_writehigh },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
        .access = PL2_RW, .accessfn = sel2_access,
        .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae3_write },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_tda,
        .type = ARM_CP_NOP },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
        .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
      { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
        .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  /* Return the exception level to which exceptions should be taken
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
                .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
                .writefn = dbgbcr_write, .raw_writefn = raw_write
              },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, dbgregs);
      }
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
                .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
                .writefn = dbgwcr_write, .raw_writefn = raw_write
              },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, dbgregs);
      }
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
                .type = ARM_CP_IO,
                .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
                .raw_writefn = pmevtyper_rawwrite },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, pmev_regs);
          g_free(pmevcntr_name);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
                .resetvalue = extract64(cpu->pmceid1, 32, 32) },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, v81_pmu_regs);
      }
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
        .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
        .access = PL1_R, .accessfn = access_lor_ns,
        .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  #ifdef TARGET_AARCH64
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
        .access = PL1_RW, .accessfn = access_pauth,
        .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo tlbirange_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae3_write },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo tlbios_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
        .access = PL3_W, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae3is_write },
 -    REGINFO_SENTINEL
  };
  static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rndr_reginfo[] = {
        .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
        .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
        .access = PL0_R, .readfn = rndr_readfn },
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
        .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo dcpodp_reg[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
        .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 -    REGINFO_SENTINEL
  };
  #endif /*CONFIG_USER_ONLY*/
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
      { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
      { .name = "TCO", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
        .type = ARM_CP_CONST, .access = PL0_RW, },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
        .accessfn = aa64_zva_access,
  #endif
      },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
      { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
        .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
 -    REGINFO_SENTINEL
  };
  static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
        .access = PL1_R,
        .accessfn = access_aa64_tid2,
        .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
 -    REGINFO_SENTINEL
  };
  static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
        .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
        .accessfn = access_joscr_jmcr,
        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo vhe_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
        .access = PL2_RW, .accessfn = e2h_access,
        .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
  #endif
 -    REGINFO_SENTINEL
  };
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
        .writefn = ats_write64 },
 -    REGINFO_SENTINEL
  };
  static const ARMCPRegInfo ats1cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
        .writefn = ats_write },
 -    REGINFO_SENTINEL
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
        .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
        .access = PL2_RW, .type = ARM_CP_CONST,
        .resetvalue = 0 },
 -    REGINFO_SENTINEL
  };
  void register_cp_regs_for_features(ARMCPU *cpu)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .type = ARM_CP_CONST,
                .accessfn = access_aa32_tid3,
                .resetvalue = cpu->isar.id_isar6 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, v6_idregs);
          define_arm_cp_regs(cpu, v6_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
                .resetvalue = cpu->pmceid1 },
 -            REGINFO_SENTINEL
          };
  #ifdef CONFIG_USER_ONLY
          ARMCPRegUserSpaceInfo v8_user_idregs[] = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .exported_bits = 0x000000f0ffffffff },
              { .name = "ID_AA64ISAR*_EL1_RESERVED",
                .is_glob = true                     },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(v8_idregs, v8_user_idregs);
  #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL2_RW,
                .resetvalue = vmpidr_def,
                .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, vpidr_regs);
          define_arm_cp_regs(cpu, el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                    .access = PL2_RW, .accessfn = access_el3_aa32ns,
                    .type = ARM_CP_NO_RAW,
                    .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
 -                REGINFO_SENTINEL
              };
              define_arm_cp_regs(cpu, vpidr_regs);
              define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .raw_writefn = raw_write, .writefn = sctlr_write,
                .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
                .resetvalue = cpu->reset_sctlr },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, el3_regs);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "DUMMY",
                .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
                .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
              { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R,
                .accessfn = access_aa64_tid1,
                .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
 -            REGINFO_SENTINEL
          };
          ARMCPRegInfo id_cp_reginfo[] = {
              /* These are common to v8 and pre-v8 */
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R,
                .accessfn = access_aa32_tid1,
                .type = ARM_CP_CONST, .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          /* TLBTR is specific to VMSA */
          ARMCPRegInfo id_tlbtr_reginfo = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "MIDR_EL1",
                .exported_bits = 0x00000000ffffffff },
              { .name = "REVIDR_EL1"                },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
  #endif
          if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
              arm_feature(env, ARM_FEATURE_STRONGARM)) {
 -            ARMCPRegInfo *r;
 +            size_t i;
              /* Register the blanket "writes ignored" value first to cover the
               * whole space. Then update the specific ID registers to allow write
               * access, so that they ignore writes rather than causing them to
               * UNDEF.
               */
              define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
 -            for (r = id_pre_v8_midr_cp_reginfo;
 -                 r->type != ARM_CP_SENTINEL; r++) {
 -                r->access = PL1_RW;
 +            for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) {
 +                id_pre_v8_midr_cp_reginfo[i].access = PL1_RW;
              }
 -            for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
 -                r->access = PL1_RW;
 +            for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) {
 +                id_cp_reginfo[i].access = PL1_RW;
              }
              id_mpuir_reginfo.access = PL1_RW;
              id_tlbtr_reginfo.access = PL1_RW;
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
                .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
                .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
 -            REGINFO_SENTINEL
          };
  #ifdef CONFIG_USER_ONLY
          ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
              { .name = "MPIDR_EL1",
                .fixed_bits = 0x0000000080000000 },
 -            REGUSERINFO_SENTINEL
          };
          modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
  #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
                .access = PL3_RW, .type = ARM_CP_CONST,
                .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, auxcr_reginfo);
          if (cpu_isar_feature(aa32_ac2, cpu)) {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                    .type = ARM_CP_CONST,
                    .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
                    .access = PL1_R, .resetvalue = cpu->reset_cbar },
 -                REGINFO_SENTINEL
              };
              /* We don't implement a r/w 64 bit CBAR currently */
              assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                       offsetof(CPUARMState, cp15.vbar_ns) },
                .resetvalue = 0 },
 -            REGINFO_SENTINEL
          };
          define_arm_cp_regs(cpu, vbar_cp_reginfo);
      }
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                     r->writefn);
          }
      }
 -    /* Bad type field probably means missing sentinel at end of reg list */
 -    assert(cptype_valid(r->type));
 +
      for (crm = crmmin; crm <= crmmax; crm++) {
          for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
              for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      }
  }
+@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
--void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
+         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
--                                    const ARMCPRegInfo *regs, void *opaque)
+         break;
-+/* Define a whole list of registers */
+     default:
-+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+-        printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
-+                                        void *opaque, size_t len)
++        qemu_log_mask(LOG_GUEST_ERROR,
- {
++                      "pxa2xx_pic_mem_write: bad register offset 0x%"
--    /* Define a whole list of registers */
++                      HWADDR_PRIx "\n", offset);
--    const ARMCPRegInfo *r;
+         return;
 -    for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
 -        define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
 +    size_t i;
 +    for (i = 0; i < len; ++i) {
 +        define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque);
      }
- }
+     pxa2xx_pic_update(opaque);
@@ -XXX,XX +XXX,XX @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
   * user-space cannot alter any values and dynamic values pertaining to
   * execution state are hidden from user space view anyway.
   */
 -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
 +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
 +                                 const ARMCPRegUserSpaceInfo *mods,
 +                                 size_t mods_len)
  {
 -    const ARMCPRegUserSpaceInfo *m;
 -    ARMCPRegInfo *r;
 -
 -    for (m = mods; m->name; m++) {
 +    for (size_t mi = 0; mi < mods_len; ++mi) {
 +        const ARMCPRegUserSpaceInfo *m = mods + mi;
          GPatternSpec *pat = NULL;
 +
          if (m->is_glob) {
              pat = g_pattern_spec_new(m->name);
          }
 -        for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
 +        for (size_t ri = 0; ri < regs_len; ++ri) {
 +            ARMCPRegInfo *r = regs + ri;
 +
              if (pat && g_pattern_match_string(pat, r->name)) {
                  r->type = ARM_CP_CONST;
                  r->access = PL0U_R;
 --
-.25.1
+.20.1

-New patch
+[PULL 32/34] hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
+The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the
+usual QOM TYPE and casting macros; provide and use them.
+In particular, we can safely use the QOM cast macros instead of
+FROM_SSI_SLAVE() because in both cases the 'ssidev' field of
+the instance state struct is the first field in it.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-17-peter.maydell@linaro.org
+---
+ hw/arm/spitz.c | 23 +++++++++++++++--------
+file changed, 15 insertions(+), 8 deletions(-)
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
+ #define LCDTG_PICTRL    0x06
+ #define LCDTG_POLCTRL   0x07
++#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
++#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
++
+ typedef struct {
+     SSISlave ssidev;
+     uint32_t bl_intensity;
+@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_power(void *opaque, int line, int level)
+ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
+ {
+-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
++    SpitzLCDTG *s = SPITZ_LCDTG(dev);
+     int addr;
+     addr = value >> 5;
+     value &= 0x1f;
+@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
+ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
+ {
+-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
++    SpitzLCDTG *s = SPITZ_LCDTG(ssi);
+     DeviceState *dev = DEVICE(s);
+     s->bl_power = 0;
+@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
+ #define SPITZ_GPIO_MAX1111_CS   20
+ #define SPITZ_GPIO_TP_INT       11
++#define TYPE_CORGI_SSP "corgi-ssp"
++#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
++
+ /* "Demux" the signal based on current chipselect */
+ typedef struct {
+     SSISlave ssidev;
+@@ -XXX,XX +XXX,XX @@ typedef struct {
+ static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
+ {
+-    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
++    CorgiSSPState *s = CORGI_SSP(dev);
+     int i;
+     for (i = 0; i < 3; i++) {
+@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
+ static void corgi_ssp_realize(SSISlave *d, Error **errp)
+ {
+     DeviceState *dev = DEVICE(d);
+-    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d);
++    CorgiSSPState *s = CORGI_SSP(d);
+     qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
+     s->bus[0] = ssi_create_bus(dev, "ssi0");
+@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
+ {
+     void *bus;
+-    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
++    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
++                                TYPE_CORGI_SSP);
+     bus = qdev_get_child_bus(sms->mux, "ssi0");
+-    sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
++    sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
+     bus = qdev_get_child_bus(sms->mux, "ssi1");
+     sms->ads7846 = ssi_create_slave(bus, "ads7846");
+@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data)
+ }
+ static const TypeInfo corgi_ssp_info = {
+-    .name          = "corgi-ssp",
++    .name          = TYPE_CORGI_SSP,
+     .parent        = TYPE_SSI_SLAVE,
+     .instance_size = sizeof(CorgiSSPState),
+     .class_init    = corgi_ssp_class_init,
+@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
+ }
+ static const TypeInfo spitz_lcdtg_info = {
+-    .name          = "spitz-lcdtg",
++    .name          = TYPE_SPITZ_LCDTG,
+     .parent        = TYPE_SSI_SLAVE,
+     .instance_size = sizeof(SpitzLCDTG),
+     .class_init    = spitz_lcdtg_class_init,
+--
+.20.1

-[PULL 09/23] target/arm: Name CPState type
+[PULL 33/34] Replace uses of FROM_SSI_SLAVE() macro with QOM casts
-From: Richard Henderson <richard.henderson@linaro.org>
+The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way
 to cast from an SSISlave* to the instance struct of a subtype of
 TYPE_SSI_SLAVE.  Switch to using the QOM cast macros instead, which
 have the same effect (by writing the QOM macros if the types were
 previously missing them.)
-Give this enum a name and use in ARMCPRegInfo,
+(The FROM_SSI_SLAVE() macro allows the SSISlave member of the
-add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.
+subtype's struct to be anywhere as long as it is named "ssidev",
 whereas a QOM cast macro insists that it is the first thing in the
 subtype's struct.  This is true for all the types we convert here.)
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+This removes all the uses of FROM_SSI_SLAVE() so we can delete the
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+definition.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220501055028.646596-9-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20200628142429.17111-18-peter.maydell@linaro.org
 ---
- target/arm/cpregs.h | 6 +++---
+ include/hw/ssi/ssi.h |  2 --
- target/arm/helper.c | 6 ++++--
+ hw/arm/z2.c          | 11 +++++++----
-files changed, 7 insertions(+), 5 deletions(-)
+ hw/display/ads7846.c |  9 ++++++---
  hw/display/ssd0323.c | 10 +++++++---
  hw/sd/ssi-sd.c       |  4 ++--
 files changed, 22 insertions(+), 14 deletions(-)
-diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpregs.h
+--- a/include/hw/ssi/ssi.h
-+++ b/target/arm/cpregs.h
++++ b/include/hw/ssi/ssi.h
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ struct SSISlave {
-  * Note that we rely on the values of these enums as we iterate through
+     bool cs;
-  * the various states in some places.
+ };
-  */
--enum {
+-#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
-+typedef enum {
+-
-     ARM_CP_STATE_AA32 = 0,
+ extern const VMStateDescription vmstate_ssi_slave;
-     ARM_CP_STATE_AA64 = 1,
-     ARM_CP_STATE_BOTH = 2,
+ #define VMSTATE_SSI_SLAVE(_field, _state) {                          \
--};
+diff --git a/hw/arm/z2.c b/hw/arm/z2.c
 +} CPState;
  /*
   * ARM CP register secure state flags.  These flags identify security state
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
      uint8_t opc1;
      uint8_t opc2;
      /* Execution state in which this register is visible: ARM_CP_STATE_* */
 -    int state;
 +    CPState state;
      /* Register type: ARM_CP_* bits/values */
      int type;
      /* Access rights: PL*_[RW] */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/z2.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/z2.c
-@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+@@ -XXX,XX +XXX,XX @@ typedef struct {
      int pos;
  } ZipitLCD;
 +#define TYPE_ZIPIT_LCD "zipit-lcd"
 +#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD)
 +
  static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
  {
 -    ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
 +    ZipitLCD *z = ZIPIT_LCD(dev);
      uint16_t val;
      if (z->selected) {
          z->buf[z->pos] = value & 0xff;
@@ -XXX,XX +XXX,XX @@ static void z2_lcd_cs(void *opaque, int line, int level)
  static void zipit_lcd_realize(SSISlave *dev, Error **errp)
  {
 -    ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
 +    ZipitLCD *z = ZIPIT_LCD(dev);
      z->selected = 0;
      z->enabled = 0;
      z->pos = 0;
@@ -XXX,XX +XXX,XX @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data)
  }
- static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+ static const TypeInfo zipit_lcd_info = {
--                                   void *opaque, int state, int secstate,
+-    .name          = "zipit-lcd",
-+                                   void *opaque, CPState state, int secstate,
++    .name          = TYPE_ZIPIT_LCD,
-                                    int crm, int opc1, int opc2,
+     .parent        = TYPE_SSI_SLAVE,
-                                    const char *name)
+     .instance_size = sizeof(ZipitLCD),
      .class_init    = zipit_lcd_class_init,
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
      type_register_static(&zipit_lcd_info);
      type_register_static(&aer915_info);
 -    z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd");
 +    z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD);
      bus = pxa2xx_i2c_bus(mpu->i2c[0]);
      i2c_create_slave(bus, TYPE_AER915, 0x55);
      wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b);
 diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/display/ads7846.c
 +++ b/hw/display/ads7846.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
      int output;
  } ADS7846State;
 +#define TYPE_ADS7846 "ads7846"
 +#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846)
 +
  /* Control-byte bitfields */
  #define CB_PD0        (1 << 0)
  #define CB_PD1        (1 << 1)
@@ -XXX,XX +XXX,XX @@ static void ads7846_int_update(ADS7846State *s)
  static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value)
  {
-@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+-    ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev);
-      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
++    ADS7846State *s = ADS7846(dev);
-      * the register, if any.
-      */
+     switch (s->cycle ++) {
--    int crm, opc1, opc2, state;
+     case 0:
-+    int crm, opc1, opc2;
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ads7846 = {
-     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
+ static void ads7846_realize(SSISlave *d, Error **errp)
-     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
+ {
-     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
+     DeviceState *dev = DEVICE(d);
-     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
+-    ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d);
-     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
++    ADS7846State *s = ADS7846(d);
-     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
-+    CPState state;
+     qdev_init_gpio_out(dev, &s->interrupt, 1);
@@ -XXX,XX +XXX,XX @@ static void ads7846_class_init(ObjectClass *klass, void *data)
  }
  static const TypeInfo ads7846_info = {
 -    .name          = "ads7846",
 +    .name          = TYPE_ADS7846,
      .parent        = TYPE_SSI_SLAVE,
      .instance_size = sizeof(ADS7846State),
      .class_init    = ads7846_class_init,
 diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/display/ssd0323.c
 +++ b/hw/display/ssd0323.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
      uint8_t framebuffer[128 * 80 / 2];
  } ssd0323_state;
 +#define TYPE_SSD0323 "ssd0323"
 +#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323)
 +
-     /* 64 bit registers have only CRm and Opc1 fields */
++
-     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
+ static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
-     /* op0 only exists in the AArch64 encodings */
+ {
 -    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
 +    ssd0323_state *s = SSD0323(dev);
      switch (s->mode) {
      case SSD0323_DATA:
@@ -XXX,XX +XXX,XX @@ static const GraphicHwOps ssd0323_ops = {
  static void ssd0323_realize(SSISlave *d, Error **errp)
  {
      DeviceState *dev = DEVICE(d);
 -    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
 +    ssd0323_state *s = SSD0323(d);
      s->col_end = 63;
      s->row_end = 79;
@@ -XXX,XX +XXX,XX @@ static void ssd0323_class_init(ObjectClass *klass, void *data)
  }
  static const TypeInfo ssd0323_info = {
 -    .name          = "ssd0323",
 +    .name          = TYPE_SSD0323,
      .parent        = TYPE_SSI_SLAVE,
      .instance_size = sizeof(ssd0323_state),
      .class_init    = ssd0323_class_init,
 diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/ssi-sd.c
 +++ b/hw/sd/ssi-sd.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
  static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
  {
 -    ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev);
 +    ssi_sd_state *s = SSI_SD(dev);
      /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data.  */
      if (s->mode == SSI_SD_DATA_READ && val == 0x4d) {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ssi_sd = {
  static void ssi_sd_realize(SSISlave *d, Error **errp)
  {
 -    ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
 +    ssi_sd_state *s = SSI_SD(d);
      DeviceState *carddev;
      DriveInfo *dinfo;
      Error *err = NULL;
 --
-.25.1
+.20.1

-[PULL 16/23] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
+[PULL 34/34] Deprecate TileGX port
-From: Richard Henderson <richard.henderson@linaro.org>
+Deprecate our TileGX target support:
  * we have no active maintainer for it
  * it has had essentially no contributions (other than tree-wide cleanups
    and similar) since it was first added
  * the Linux kernel dropped support in 2018, as has glibc
-Bool is a more appropriate type for these variables.
+Note the deprecation in the manual, but don't try to print a warning
 when QEMU runs -- printing unsuppressable messages is more obtrusive
 for linux-user mode than it would be for system-emulation mode, and
 it doesn't seem worth trying to invent a new suppressible-error
 system for linux-user just for this.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20220501055028.646596-16-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Message-id: 20200619154831.26319-1-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 4 ++--
+ docs/system/deprecated.rst | 11 +++++++++++
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 11 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/docs/system/deprecated.rst
-+++ b/target/arm/helper.c
++++ b/docs/system/deprecated.rst
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
-      */
-     uint32_t key;
+   json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
-     ARMCPRegInfo *r2;
--    int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
++linux-user mode CPUs
--    int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
++--------------------
-+    bool is64 = r->type & ARM_CP_64BIT;
++
-+    bool ns = secstate & ARM_CP_SECSTATE_NS;
++``tilegx`` CPUs (since 5.1.0)
-     int cp = r->cp;
++'''''''''''''''''''''''''''''
-     size_t name_len;
++
 +The ``tilegx`` guest CPU support (which was only implemented in
 +linux-user mode) is deprecated and will be removed in a future version
 +of QEMU. Support for this CPU was removed from the upstream Linux
 +kernel in 2018, and has also been dropped from glibc.
 +
  Related binaries
  ----------------
 --
-.25.1
+.20.1

Two small bugfixes, plus most of RTH's refactoring of cpregs
handling.

-- PMM

The following changes since commit 1fba9dc71a170b3a05b9d3272dd8ecfe7f26e215:

Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging (2022-05-04 08:07:02 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220505

for you to fetch changes up to 99a50d1a67c602126fc2b3a4812d3000eba9bf34:

target/arm: read access to performance counters from EL0 (2022-05-05 09:36:22 +0100)

----------------------------------------------------------------
target-arm queue:
 * Enable read access to performance counters from EL0
 * Enable SCTLR_EL1.BT0 for aarch64-linux-user
 * Refactoring of cpreg handling

----------------------------------------------------------------
Alex Zuepke (1):
      target/arm: read access to performance counters from EL0

Richard Henderson (22):
      target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
      target/arm: Split out cpregs.h
      target/arm: Reorg CPAccessResult and access_check_cp_reg
      target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
      target/arm: Make some more cpreg data static const
      target/arm: Reorg ARMCPRegInfo type field bits
      target/arm: Avoid bare abort() or assert(0)
      target/arm: Change cpreg access permissions to enum
      target/arm: Name CPState type
      target/arm: Name CPSecureState type
      target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases
      target/arm: Store cpregs key in the hash table directly
      target/arm: Merge allocation of the cpreg and its name
      target/arm: Hoist computation of key in add_cpreg_to_hashtable
      target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable
      target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable
      target/arm: Hoist isbanked computation in add_cpreg_to_hashtable
      target/arm: Perform override check early in add_cpreg_to_hashtable
      target/arm: Reformat comments in add_cpreg_to_hashtable
      target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable
      target/arm: Add isar predicates for FEAT_Debugv8p2
      target/arm: Add isar_feature_{aa64,any}_ras

From: Richard Henderson <richard.henderson@linaro.org>

This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17).  The linux kernel
sets this in bti_enable().

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
[PMM: remove stray change to makefile comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c                  |  2 ++
 tests/tcg/aarch64/bti-3.c         | 42 +++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  6 ++---
 3 files changed, 47 insertions(+), 3 deletions(-)
 create mode 100644 tests/tcg/aarch64/bti-3.c

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         /* Enable all PAC keys.  */
         env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
                                   SCTLR_EnDA | SCTLR_EnDB);
+        /* Trap on btype=3 for PACIxSP. */
+        env->cp15.sctlr_el[1] |= SCTLR_BT0;
         /* and to the FP/Neon instructions */
         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
         /* and to the SVE instructions */
diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/aarch64/bti-3.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BTI vs PACIASP
+ */
+
+#include "bti-crt.inc.c"
+
+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
+{
+    uc->uc_mcontext.pc += 8;
+    uc->uc_mcontext.pstate = 1;
+}
+
+#define BTYPE_1() \
+    asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_2() \
+    asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_3() \
+    asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
+        : "=r"(skipped) : : "x15", "x30")
+
+#define TEST(WHICH, EXPECT) \
+    do { WHICH(); fail += skipped ^ EXPECT; } while (0)
+
+int main()
+{
+    int fail = 0;
+    int skipped;
+
+    /* Signal-like with SA_SIGINFO.  */
+    signal_info(SIGILL, skip2_sigill);
+
+    /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
+    TEST(BTYPE_1, 0);
+    TEST(BTYPE_2, 0);
+    TEST(BTYPE_3, 1);
+
+    return fail;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ endif
 # BTI Tests
 # bti-1 tests the elf notes, so we require special compiler support.
 ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
-AARCH64_TESTS += bti-1
-bti-1: CFLAGS += -mbranch-protection=standard
-bti-1: LDFLAGS += -nostdlib
+AARCH64_TESTS += bti-1 bti-3
+bti-1 bti-3: CFLAGS += -mbranch-protection=standard
+bti-1 bti-3: LDFLAGS += -nostdlib
 endif
 # bti-2 tests PROT_BTI, so no special compiler support required.
 AARCH64_TESTS += bti-2
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move ARMCPRegInfo and all related declarations to a new
internal header, out of the public cpu.h.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h        | 413 +++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h           | 368 ---------------------------------
 hw/arm/pxa2xx.c            |   1 +
 hw/arm/pxa2xx_pic.c        |   1 +
 hw/intc/arm_gicv3_cpuif.c  |   1 +
 hw/intc/arm_gicv3_kvm.c    |   2 +
 target/arm/cpu.c           |   1 +
 target/arm/cpu64.c         |   1 +
 target/arm/cpu_tcg.c       |   1 +
 target/arm/gdbstub.c       |   3 +-
 target/arm/helper.c        |   1 +
 target/arm/op_helper.c     |   1 +
 target/arm/translate-a64.c |   4 +-
 target/arm/translate.c     |   3 +-
 14 files changed, 427 insertions(+), 374 deletions(-)
 create mode 100644 target/arm/cpregs.h

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU ARM CP Register access and descriptions
+ *
+ * Copyright (c) 2022 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#ifndef TARGET_ARM_CPREGS_H
+#define TARGET_ARM_CPREGS_H
+
+/*
+ * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
+ * special-behaviour cp reg and bits [11..8] indicate what behaviour
+ * it has. Otherwise it is a simple cp reg, where CONST indicates that
+ * TCG can assume the value to be constant (ie load at translate time)
+ * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
+ * indicates that the TB should not be ended after a write to this register
+ * (the default is that the TB ends after cp writes). OVERRIDE permits
+ * a register definition to override a previous definition for the
+ * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
+ * old must have the OVERRIDE bit set.
+ * ALIAS indicates that this register is an alias view of some underlying
+ * state which is also visible via another register, and that the other
+ * register is handling migration and reset; registers marked ALIAS will not be
+ * migrated but may have their state set by syncing of register state from KVM.
+ * NO_RAW indicates that this register has no underlying state and does not
+ * support raw access for state saving/loading; it will not be used for either
+ * migration or KVM state synchronization. (Typically this is for "registers"
+ * which are actually used as instructions for cache maintenance and so on.)
+ * IO indicates that this register does I/O and therefore its accesses
+ * need to be marked with gen_io_start() and also end the TB. In particular,
+ * registers which implement clocks or timers require this.
+ * RAISES_EXC is for when the read or write hook might raise an exception;
+ * the generated code will synchronize the CPU state before calling the hook
+ * so that it is safe for the hook to call raise_exception().
+ * NEWEL is for writes to registers that might change the exception
+ * level - typically on older ARM chips. For those cases we need to
+ * re-read the new el when recomputing the translation flags.
+ */
+#define ARM_CP_SPECIAL           0x0001
+#define ARM_CP_CONST             0x0002
+#define ARM_CP_64BIT             0x0004
+#define ARM_CP_SUPPRESS_TB_END   0x0008
+#define ARM_CP_OVERRIDE          0x0010
+#define ARM_CP_ALIAS             0x0020
+#define ARM_CP_IO                0x0040
+#define ARM_CP_NO_RAW            0x0080
+#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
+#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
+#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
+#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
+#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
+#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
+#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
+#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
+#define ARM_CP_FPU               0x1000
+#define ARM_CP_SVE               0x2000
+#define ARM_CP_NO_GDB            0x4000
+#define ARM_CP_RAISES_EXC        0x8000
+#define ARM_CP_NEWEL             0x10000
+/* Used only as a terminator for ARMCPRegInfo lists */
+#define ARM_CP_SENTINEL          0xfffff
+/* Mask of only the flag bits in a type field */
+#define ARM_CP_FLAG_MASK         0x1f0ff
+
+/*
+ * Valid values for ARMCPRegInfo state field, indicating which of
+ * the AArch32 and AArch64 execution states this register is visible in.
+ * If the reginfo doesn't explicitly specify then it is AArch32 only.
+ * If the reginfo is declared to be visible in both states then a second
+ * reginfo is synthesised for the AArch32 view of the AArch64 register,
+ * such that the AArch32 view is the lower 32 bits of the AArch64 one.
+ * Note that we rely on the values of these enums as we iterate through
+ * the various states in some places.
+ */
+enum {
+    ARM_CP_STATE_AA32 = 0,
+    ARM_CP_STATE_AA64 = 1,
+    ARM_CP_STATE_BOTH = 2,
+};
+
+/*
+ * ARM CP register secure state flags.  These flags identify security state
+ * attributes for a given CP register entry.
+ * The existence of both or neither secure and non-secure flags indicates that
+ * the register has both a secure and non-secure hash entry.  A single one of
+ * these flags causes the register to only be hashed for the specified
+ * security state.
+ * Although definitions may have any combination of the S/NS bits, each
+ * registered entry will only have one to identify whether the entry is secure
+ * or non-secure.
+ */
+enum {
+    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
+    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
+};
+
+/*
+ * Return true if cptype is a valid type field. This is used to try to
+ * catch errors where the sentinel has been accidentally left off the end
+ * of a list of registers.
+ */
+static inline bool cptype_valid(int cptype)
+{
+    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
+        || ((cptype & ARM_CP_SPECIAL) &&
+            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
+}
+
+/*
+ * Access rights:
+ * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
+ * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
+ * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
+ * (ie any of the privileged modes in Secure state, or Monitor mode).
+ * If a register is accessible in one privilege level it's always accessible
+ * in higher privilege levels too. Since "Secure PL1" also follows this rule
+ * (ie anything visible in PL2 is visible in S-PL1, some things are only
+ * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
+ * terminology a little and call this PL3.
+ * In AArch64 things are somewhat simpler as the PLx bits line up exactly
+ * with the ELx exception levels.
+ *
+ * If access permissions for a register are more complex than can be
+ * described with these bits, then use a laxer set of restrictions, and
+ * do the more restrictive/complex check inside a helper function.
+ */
+#define PL3_R 0x80
+#define PL3_W 0x40
+#define PL2_R (0x20 | PL3_R)
+#define PL2_W (0x10 | PL3_W)
+#define PL1_R (0x08 | PL2_R)
+#define PL1_W (0x04 | PL2_W)
+#define PL0_R (0x02 | PL1_R)
+#define PL0_W (0x01 | PL1_W)
+
+/*
+ * For user-mode some registers are accessible to EL0 via a kernel
+ * trap-and-emulate ABI. In this case we define the read permissions
+ * as actually being PL0_R. However some bits of any given register
+ * may still be masked.
+ */
+#ifdef CONFIG_USER_ONLY
+#define PL0U_R PL0_R
+#else
+#define PL0U_R PL1_R
+#endif
+
+#define PL3_RW (PL3_R | PL3_W)
+#define PL2_RW (PL2_R | PL2_W)
+#define PL1_RW (PL1_R | PL1_W)
+#define PL0_RW (PL0_R | PL0_W)
+
+typedef enum CPAccessResult {
+    /* Access is permitted */
+    CP_ACCESS_OK = 0,
+    /*
+     * Access fails due to a configurable trap or enable which would
+     * result in a categorized exception syndrome giving information about
+     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
+     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
+     * PL1 if in EL0, otherwise to the current EL).
+     */
+    CP_ACCESS_TRAP = 1,
+    /*
+     * Access fails and results in an exception syndrome 0x0 ("uncategorized").
+     * Note that this is not a catch-all case -- the set of cases which may
+     * result in this failure is specifically defined by the architecture.
+     */
+    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
+    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
+    CP_ACCESS_TRAP_EL2 = 3,
+    CP_ACCESS_TRAP_EL3 = 4,
+    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
+} CPAccessResult;
+
+typedef struct ARMCPRegInfo ARMCPRegInfo;
+
+/*
+ * Access functions for coprocessor registers. These cannot fail and
+ * may not raise exceptions.
+ */
+typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
+                       uint64_t value);
+/* Access permission check functions for coprocessor registers. */
+typedef CPAccessResult CPAccessFn(CPUARMState *env,
+                                  const ARMCPRegInfo *opaque,
+                                  bool isread);
+/* Hook function for register reset */
+typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+
+#define CP_ANY 0xff
+
+/* Definition of an ARM coprocessor register */
+struct ARMCPRegInfo {
+    /* Name of register (useful mainly for debugging, need not be unique) */
+    const char *name;
+    /*
+     * Location of register: coprocessor number and (crn,crm,opc1,opc2)
+     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
+     * 'wildcard' field -- any value of that field in the MRC/MCR insn
+     * will be decoded to this register. The register read and write
+     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
+     * used by the program, so it is possible to register a wildcard and
+     * then behave differently on read/write if necessary.
+     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
+     * must both be zero.
+     * For AArch64-visible registers, opc0 is also used.
+     * Since there are no "coprocessors" in AArch64, cp is purely used as a
+     * way to distinguish (for KVM's benefit) guest-visible system registers
+     * from demuxed ones provided to preserve the "no side effects on
+     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
+     * visible (to match KVM's encoding); cp==0 will be converted to
+     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
+     */
+    uint8_t cp;
+    uint8_t crn;
+    uint8_t crm;
+    uint8_t opc0;
+    uint8_t opc1;
+    uint8_t opc2;
+    /* Execution state in which this register is visible: ARM_CP_STATE_* */
+    int state;
+    /* Register type: ARM_CP_* bits/values */
+    int type;
+    /* Access rights: PL*_[RW] */
+    int access;
+    /* Security state: ARM_CP_SECSTATE_* bits/values */
+    int secure;
+    /*
+     * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
+     * this register was defined: can be used to hand data through to the
+     * register read/write functions, since they are passed the ARMCPRegInfo*.
+     */
+    void *opaque;
+    /*
+     * Value of this register, if it is ARM_CP_CONST. Otherwise, if
+     * fieldoffset is non-zero, the reset value of the register.
+     */
+    uint64_t resetvalue;
+    /*
+     * Offset of the field in CPUARMState for this register.
+     * This is not needed if either:
+     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
+     *  2. both readfn and writefn are specified
+     */
+    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
+
+    /*
+     * Offsets of the secure and non-secure fields in CPUARMState for the
+     * register if it is banked.  These fields are only used during the static
+     * registration of a register.  During hashing the bank associated
+     * with a given security state is copied to fieldoffset which is used from
+     * there on out.
+     *
+     * It is expected that register definitions use either fieldoffset or
+     * bank_fieldoffsets in the definition but not both.  It is also expected
+     * that both bank offsets are set when defining a banked register.  This
+     * use indicates that a register is banked.
+     */
+    ptrdiff_t bank_fieldoffsets[2];
+
+    /*
+     * Function for making any access checks for this register in addition to
+     * those specified by the 'access' permissions bits. If NULL, no extra
+     * checks required. The access check is performed at runtime, not at
+     * translate time.
+     */
+    CPAccessFn *accessfn;
+    /*
+     * Function for handling reads of this register. If NULL, then reads
+     * will be done by loading from the offset into CPUARMState specified
+     * by fieldoffset.
+     */
+    CPReadFn *readfn;
+    /*
+     * Function for handling writes of this register. If NULL, then writes
+     * will be done by writing to the offset into CPUARMState specified
+     * by fieldoffset.
+     */
+    CPWriteFn *writefn;
+    /*
+     * Function for doing a "raw" read; used when we need to copy
+     * coprocessor state to the kernel for KVM or out for
+     * migration. This only needs to be provided if there is also a
+     * readfn and it has side effects (for instance clear-on-read bits).
+     */
+    CPReadFn *raw_readfn;
+    /*
+     * Function for doing a "raw" write; used when we need to copy KVM
+     * kernel coprocessor state into userspace, or for inbound
+     * migration. This only needs to be provided if there is also a
+     * writefn and it masks out "unwritable" bits or has write-one-to-clear
+     * or similar behaviour.
+     */
+    CPWriteFn *raw_writefn;
+    /*
+     * Function for resetting the register. If NULL, then reset will be done
+     * by writing resetvalue to the field specified in fieldoffset. If
+     * fieldoffset is 0 then no reset will be done.
+     */
+    CPResetFn *resetfn;
+
+    /*
+     * "Original" writefn and readfn.
+     * For ARMv8.1-VHE register aliases, we overwrite the read/write
+     * accessor functions of various EL1/EL0 to perform the runtime
+     * check for which sysreg should actually be modified, and then
+     * forwards the operation.  Before overwriting the accessors,
+     * the original function is copied here, so that accesses that
+     * really do go to the EL1/EL0 version proceed normally.
+     * (The corresponding EL2 register is linked via opaque.)
+     */
+    CPReadFn *orig_readfn;
+    CPWriteFn *orig_writefn;
+};
+
+/*
+ * Macros which are lvalues for the field in CPUARMState for the
+ * ARMCPRegInfo *ri.
+ */
+#define CPREG_FIELD32(env, ri) \
+    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
+#define CPREG_FIELD64(env, ri) \
+    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
+
+#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
+
+void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
+                                    const ARMCPRegInfo *regs, void *opaque);
+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+                                       const ARMCPRegInfo *regs, void *opaque);
+static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
+{
+    define_arm_cp_regs_with_opaque(cpu, regs, 0);
+}
+static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
+{
+    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
+}
+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
+
+/*
+ * Definition of an ARM co-processor register as viewed from
+ * userspace. This is used for presenting sanitised versions of
+ * registers to userspace when emulating the Linux AArch64 CPU
+ * ID/feature ABI (advertised as HWCAP_CPUID).
+ */
+typedef struct ARMCPRegUserSpaceInfo {
+    /* Name of register */
+    const char *name;
+
+    /* Is the name actually a glob pattern */
+    bool is_glob;
+
+    /* Only some bits are exported to user space */
+    uint64_t exported_bits;
+
+    /* Fixed bits are applied after the mask */
+    uint64_t fixed_bits;
+} ARMCPRegUserSpaceInfo;
+
+#define REGUSERINFO_SENTINEL { .name = NULL }
+
+void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
+
+/* CPWriteFn that can be used to implement writes-ignored behaviour */
+void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
+                         uint64_t value);
+/* CPReadFn that can be used for read-as-zero behaviour */
+uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
+
+/*
+ * CPResetFn that does nothing, for use if no reset is required even
+ * if fieldoffset is non zero.
+ */
+void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
+
+/*
+ * Return true if this reginfo struct's field in the cpu state struct
+ * is 64 bits wide.
+ */
+static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
+{
+    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
+}
+
+static inline bool cp_access_ok(int current_el,
+                                const ARMCPRegInfo *ri, int isread)
+{
+    return (ri->access >> ((current_el * 2) + isread)) & 1;
+}
+
+/* Raw read of a coprocessor register (as needed for migration, etc) */
+uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
+
+#endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
     return kvmid;
 }
 
-/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
- * special-behaviour cp reg and bits [11..8] indicate what behaviour
- * it has. Otherwise it is a simple cp reg, where CONST indicates that
- * TCG can assume the value to be constant (ie load at translate time)
- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
- * indicates that the TB should not be ended after a write to this register
- * (the default is that the TB ends after cp writes). OVERRIDE permits
- * a register definition to override a previous definition for the
- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
- * old must have the OVERRIDE bit set.
- * ALIAS indicates that this register is an alias view of some underlying
- * state which is also visible via another register, and that the other
- * register is handling migration and reset; registers marked ALIAS will not be
- * migrated but may have their state set by syncing of register state from KVM.
- * NO_RAW indicates that this register has no underlying state and does not
- * support raw access for state saving/loading; it will not be used for either
- * migration or KVM state synchronization. (Typically this is for "registers"
- * which are actually used as instructions for cache maintenance and so on.)
- * IO indicates that this register does I/O and therefore its accesses
- * need to be marked with gen_io_start() and also end the TB. In particular,
- * registers which implement clocks or timers require this.
- * RAISES_EXC is for when the read or write hook might raise an exception;
- * the generated code will synchronize the CPU state before calling the hook
- * so that it is safe for the hook to call raise_exception().
- * NEWEL is for writes to registers that might change the exception
- * level - typically on older ARM chips. For those cases we need to
- * re-read the new el when recomputing the translation flags.
- */
-#define ARM_CP_SPECIAL           0x0001
-#define ARM_CP_CONST             0x0002
-#define ARM_CP_64BIT             0x0004
-#define ARM_CP_SUPPRESS_TB_END   0x0008
-#define ARM_CP_OVERRIDE          0x0010
-#define ARM_CP_ALIAS             0x0020
-#define ARM_CP_IO                0x0040
-#define ARM_CP_NO_RAW            0x0080
-#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
-#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
-#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
-#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
-#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
-#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
-#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
-#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
-#define ARM_CP_FPU               0x1000
-#define ARM_CP_SVE               0x2000
-#define ARM_CP_NO_GDB            0x4000
-#define ARM_CP_RAISES_EXC        0x8000
-#define ARM_CP_NEWEL             0x10000
-/* Used only as a terminator for ARMCPRegInfo lists */
-#define ARM_CP_SENTINEL          0xfffff
-/* Mask of only the flag bits in a type field */
-#define ARM_CP_FLAG_MASK         0x1f0ff
-
-/* Valid values for ARMCPRegInfo state field, indicating which of
- * the AArch32 and AArch64 execution states this register is visible in.
- * If the reginfo doesn't explicitly specify then it is AArch32 only.
- * If the reginfo is declared to be visible in both states then a second
- * reginfo is synthesised for the AArch32 view of the AArch64 register,
- * such that the AArch32 view is the lower 32 bits of the AArch64 one.
- * Note that we rely on the values of these enums as we iterate through
- * the various states in some places.
- */
-enum {
-    ARM_CP_STATE_AA32 = 0,
-    ARM_CP_STATE_AA64 = 1,
-    ARM_CP_STATE_BOTH = 2,
-};
-
-/* ARM CP register secure state flags.  These flags identify security state
- * attributes for a given CP register entry.
- * The existence of both or neither secure and non-secure flags indicates that
- * the register has both a secure and non-secure hash entry.  A single one of
- * these flags causes the register to only be hashed for the specified
- * security state.
- * Although definitions may have any combination of the S/NS bits, each
- * registered entry will only have one to identify whether the entry is secure
- * or non-secure.
- */
-enum {
-    ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
-    ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
-};
-
-/* Return true if cptype is a valid type field. This is used to try to
- * catch errors where the sentinel has been accidentally left off the end
- * of a list of registers.
- */
-static inline bool cptype_valid(int cptype)
-{
-    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
-        || ((cptype & ARM_CP_SPECIAL) &&
-            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
-}
-
-/* Access rights:
- * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
- * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
- * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
- * (ie any of the privileged modes in Secure state, or Monitor mode).
- * If a register is accessible in one privilege level it's always accessible
- * in higher privilege levels too. Since "Secure PL1" also follows this rule
- * (ie anything visible in PL2 is visible in S-PL1, some things are only
- * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
- * terminology a little and call this PL3.
- * In AArch64 things are somewhat simpler as the PLx bits line up exactly
- * with the ELx exception levels.
- *
- * If access permissions for a register are more complex than can be
- * described with these bits, then use a laxer set of restrictions, and
- * do the more restrictive/complex check inside a helper function.
- */
-#define PL3_R 0x80
-#define PL3_W 0x40
-#define PL2_R (0x20 | PL3_R)
-#define PL2_W (0x10 | PL3_W)
-#define PL1_R (0x08 | PL2_R)
-#define PL1_W (0x04 | PL2_W)
-#define PL0_R (0x02 | PL1_R)
-#define PL0_W (0x01 | PL1_W)
-
-/*
- * For user-mode some registers are accessible to EL0 via a kernel
- * trap-and-emulate ABI. In this case we define the read permissions
- * as actually being PL0_R. However some bits of any given register
- * may still be masked.
- */
-#ifdef CONFIG_USER_ONLY
-#define PL0U_R PL0_R
-#else
-#define PL0U_R PL1_R
-#endif
-
-#define PL3_RW (PL3_R | PL3_W)
-#define PL2_RW (PL2_R | PL2_W)
-#define PL1_RW (PL1_R | PL1_W)
-#define PL0_RW (PL0_R | PL0_W)
-
 /* Return the highest implemented Exception Level */
 static inline int arm_highest_el(CPUARMState *env)
 {
@@ -XXX,XX +XXX,XX @@ static inline int arm_current_el(CPUARMState *env)
     }
 }
 
-typedef struct ARMCPRegInfo ARMCPRegInfo;
-
-typedef enum CPAccessResult {
-    /* Access is permitted */
-    CP_ACCESS_OK = 0,
-    /* Access fails due to a configurable trap or enable which would
-     * result in a categorized exception syndrome giving information about
-     * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
-     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
-     * PL1 if in EL0, otherwise to the current EL).
-     */
-    CP_ACCESS_TRAP = 1,
-    /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
-     * Note that this is not a catch-all case -- the set of cases which may
-     * result in this failure is specifically defined by the architecture.
-     */
-    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
-    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_EL2 = 3,
-    CP_ACCESS_TRAP_EL3 = 4,
-    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
-} CPAccessResult;
-
-/* Access functions for coprocessor registers. These cannot fail and
- * may not raise exceptions.
- */
-typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
-                       uint64_t value);
-/* Access permission check functions for coprocessor registers. */
-typedef CPAccessResult CPAccessFn(CPUARMState *env,
-                                  const ARMCPRegInfo *opaque,
-                                  bool isread);
-/* Hook function for register reset */
-typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-
-#define CP_ANY 0xff
-
-/* Definition of an ARM coprocessor register */
-struct ARMCPRegInfo {
-    /* Name of register (useful mainly for debugging, need not be unique) */
-    const char *name;
-    /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
-     * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
-     * 'wildcard' field -- any value of that field in the MRC/MCR insn
-     * will be decoded to this register. The register read and write
-     * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
-     * used by the program, so it is possible to register a wildcard and
-     * then behave differently on read/write if necessary.
-     * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
-     * must both be zero.
-     * For AArch64-visible registers, opc0 is also used.
-     * Since there are no "coprocessors" in AArch64, cp is purely used as a
-     * way to distinguish (for KVM's benefit) guest-visible system registers
-     * from demuxed ones provided to preserve the "no side effects on
-     * KVM register read/write from QEMU" semantics. cp==0x13 is guest
-     * visible (to match KVM's encoding); cp==0 will be converted to
-     * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
-     */
-    uint8_t cp;
-    uint8_t crn;
-    uint8_t crm;
-    uint8_t opc0;
-    uint8_t opc1;
-    uint8_t opc2;
-    /* Execution state in which this register is visible: ARM_CP_STATE_* */
-    int state;
-    /* Register type: ARM_CP_* bits/values */
-    int type;
-    /* Access rights: PL*_[RW] */
-    int access;
-    /* Security state: ARM_CP_SECSTATE_* bits/values */
-    int secure;
-    /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
-     * this register was defined: can be used to hand data through to the
-     * register read/write functions, since they are passed the ARMCPRegInfo*.
-     */
-    void *opaque;
-    /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
-     * fieldoffset is non-zero, the reset value of the register.
-     */
-    uint64_t resetvalue;
-    /* Offset of the field in CPUARMState for this register.
-     *
-     * This is not needed if either:
-     *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
-     *  2. both readfn and writefn are specified
-     */
-    ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
-
-    /* Offsets of the secure and non-secure fields in CPUARMState for the
-     * register if it is banked.  These fields are only used during the static
-     * registration of a register.  During hashing the bank associated
-     * with a given security state is copied to fieldoffset which is used from
-     * there on out.
-     *
-     * It is expected that register definitions use either fieldoffset or
-     * bank_fieldoffsets in the definition but not both.  It is also expected
-     * that both bank offsets are set when defining a banked register.  This
-     * use indicates that a register is banked.
-     */
-    ptrdiff_t bank_fieldoffsets[2];
-
-    /* Function for making any access checks for this register in addition to
-     * those specified by the 'access' permissions bits. If NULL, no extra
-     * checks required. The access check is performed at runtime, not at
-     * translate time.
-     */
-    CPAccessFn *accessfn;
-    /* Function for handling reads of this register. If NULL, then reads
-     * will be done by loading from the offset into CPUARMState specified
-     * by fieldoffset.
-     */
-    CPReadFn *readfn;
-    /* Function for handling writes of this register. If NULL, then writes
-     * will be done by writing to the offset into CPUARMState specified
-     * by fieldoffset.
-     */
-    CPWriteFn *writefn;
-    /* Function for doing a "raw" read; used when we need to copy
-     * coprocessor state to the kernel for KVM or out for
-     * migration. This only needs to be provided if there is also a
-     * readfn and it has side effects (for instance clear-on-read bits).
-     */
-    CPReadFn *raw_readfn;
-    /* Function for doing a "raw" write; used when we need to copy KVM
-     * kernel coprocessor state into userspace, or for inbound
-     * migration. This only needs to be provided if there is also a
-     * writefn and it masks out "unwritable" bits or has write-one-to-clear
-     * or similar behaviour.
-     */
-    CPWriteFn *raw_writefn;
-    /* Function for resetting the register. If NULL, then reset will be done
-     * by writing resetvalue to the field specified in fieldoffset. If
-     * fieldoffset is 0 then no reset will be done.
-     */
-    CPResetFn *resetfn;
-
-    /*
-     * "Original" writefn and readfn.
-     * For ARMv8.1-VHE register aliases, we overwrite the read/write
-     * accessor functions of various EL1/EL0 to perform the runtime
-     * check for which sysreg should actually be modified, and then
-     * forwards the operation.  Before overwriting the accessors,
-     * the original function is copied here, so that accesses that
-     * really do go to the EL1/EL0 version proceed normally.
-     * (The corresponding EL2 register is linked via opaque.)
-     */
-    CPReadFn *orig_readfn;
-    CPWriteFn *orig_writefn;
-};
-
-/* Macros which are lvalues for the field in CPUARMState for the
- * ARMCPRegInfo *ri.
- */
-#define CPREG_FIELD32(env, ri) \
-    (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
-#define CPREG_FIELD64(env, ri) \
-    (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
-
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
-
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque);
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                       const ARMCPRegInfo *regs, void *opaque);
-static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_arm_cp_regs_with_opaque(cpu, regs, 0);
-}
-static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
-}
-const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
-
-/*
- * Definition of an ARM co-processor register as viewed from
- * userspace. This is used for presenting sanitised versions of
- * registers to userspace when emulating the Linux AArch64 CPU
- * ID/feature ABI (advertised as HWCAP_CPUID).
- */
-typedef struct ARMCPRegUserSpaceInfo {
-    /* Name of register */
-    const char *name;
-
-    /* Is the name actually a glob pattern */
-    bool is_glob;
-
-    /* Only some bits are exported to user space */
-    uint64_t exported_bits;
-
-    /* Fixed bits are applied after the mask */
-    uint64_t fixed_bits;
-} ARMCPRegUserSpaceInfo;
-
-#define REGUSERINFO_SENTINEL { .name = NULL }
-
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
-
-/* CPWriteFn that can be used to implement writes-ignored behaviour */
-void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-                         uint64_t value);
-/* CPReadFn that can be used for read-as-zero behaviour */
-uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
-
-/* CPResetFn that does nothing, for use if no reset is required even
- * if fieldoffset is non zero.
- */
-void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
-
-/* Return true if this reginfo struct's field in the cpu state struct
- * is 64 bits wide.
- */
-static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
-{
-    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
-}
-
-static inline bool cp_access_ok(int current_el,
-                                const ARMCPRegInfo *ri, int isread)
-{
-    return (ri->access >> ((current_el * 2) + isread)) & 1;
-}
-
-/* Raw read of a coprocessor register (as needed for migration, etc) */
-uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
-
 /**
  * write_list_to_cpustate
  * @cpu: ARMCPU
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/cutils.h"
 #include "qemu/log.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
 
 static struct {
     hwaddr io_base;
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
 
 #define ICIP	0x00	/* Interrupt Controller IRQ Pending register */
 #define ICMR	0x04	/* Interrupt Controller Mask register */
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@
 #include "gicv3_internal.h"
 #include "hw/irq.h"
 #include "cpu.h"
+#include "target/arm/cpregs.h"
 
 /*
  * Special case return value from hppvi_index(); must be larger than
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "vgic_common.h"
 #include "migration/blocker.h"
 #include "qom/object.h"
+#include "target/arm/cpregs.h"
+
 
 #ifdef DEBUG_GICV3_KVM
 #define DPRINTF(fmt, ...) \
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "kvm_arm.h"
 #include "disas/capstone.h"
 #include "fpu/softfloat.h"
+#include "cpregs.h"
 
 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
 {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "hvf_arm.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
+#include "cpregs.h"
 
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/boards.h"
 #endif
+#include "cpregs.h"
 
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@
  */
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "internals.h"
 #include "exec/gdbstub.h"
+#include "internals.h"
+#include "cpregs.h"
 
 typedef struct RegisterSysregXmlParam {
     CPUState *cs;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
+#include "cpregs.h"
 
 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
 #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "internals.h"
 #include "exec/exec-all.h"
 #include "exec/cpu_ldst.h"
+#include "cpregs.h"
 
 #define SIGNBIT (uint32_t)0x80000000
 #define SIGNBIT64 ((uint64_t)1 << 63)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@
 #include "translate.h"
 #include "internals.h"
 #include "qemu/host-utils.h"
-
 #include "semihosting/semihost.h"
 #include "exec/gen-icount.h"
-
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
 #include "exec/log.h"
-
+#include "cpregs.h"
 #include "translate-a64.h"
 #include "qemu/atomic128.h"
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bitops.h"
 #include "arm_ldst.h"
 #include "semihosting/semihost.h"
-
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
-
 #include "exec/log.h"
+#include "cpregs.h"
 
 
 #define ENABLE_ARCH_4T    arm_dc_feature(s, ARM_FEATURE_V4T)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Rearrange the values of the enumerators of CPAccessResult
so that we may directly extract the target el. For the two
special cases in access_check_cp_reg, use CPAccessResult.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ static inline bool cptype_valid(int cptype)
 typedef enum CPAccessResult {
     /* Access is permitted */
     CP_ACCESS_OK = 0,
+
+    /*
+     * Combined with one of the following, the low 2 bits indicate the
+     * target exception level.  If 0, the exception is taken to the usual
+     * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
+     */
+    CP_ACCESS_EL_MASK = 3,
+
     /*
      * Access fails due to a configurable trap or enable which would
      * result in a categorized exception syndrome giving information about
      * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
-     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
-     * PL1 if in EL0, otherwise to the current EL).
+     * 0xc or 0x18).
      */
-    CP_ACCESS_TRAP = 1,
+    CP_ACCESS_TRAP = (1 << 2),
+    CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
+    CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
+
     /*
      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
      * Note that this is not a catch-all case -- the set of cases which may
      * result in this failure is specifically defined by the architecture.
      */
-    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
-    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_EL2 = 3,
-    CP_ACCESS_TRAP_EL3 = 4,
-    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
+    CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
 } CPAccessResult;
 
 typedef struct ARMCPRegInfo ARMCPRegInfo;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
                                  uint32_t isread)
 {
     const ARMCPRegInfo *ri = rip;
+    CPAccessResult res = CP_ACCESS_OK;
     int target_el;
 
     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
-        raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
+        res = CP_ACCESS_TRAP;
+        goto fail;
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
         mask &= ~((1 << 4) | (1 << 14));
 
         if (env->cp15.hstr_el2 & mask) {
-            target_el = 2;
-            goto exept;
+            res = CP_ACCESS_TRAP_EL2;
+            goto fail;
         }
     }
 
-    if (!ri->accessfn) {
+    if (ri->accessfn) {
+        res = ri->accessfn(env, ri, isread);
+    }
+    if (likely(res == CP_ACCESS_OK)) {
         return;
     }
 
-    switch (ri->accessfn(env, ri, isread)) {
-    case CP_ACCESS_OK:
-        return;
+ fail:
+    switch (res & ~CP_ACCESS_EL_MASK) {
     case CP_ACCESS_TRAP:
-        target_el = exception_target_el(env);
-        break;
-    case CP_ACCESS_TRAP_EL2:
-        /* Requesting a trap to EL2 when we're in EL3 is
-         * a bug in the access function.
-         */
-        assert(arm_current_el(env) != 3);
-        target_el = 2;
-        break;
-    case CP_ACCESS_TRAP_EL3:
-        target_el = 3;
         break;
     case CP_ACCESS_TRAP_UNCATEGORIZED:
-        target_el = exception_target_el(env);
-        syndrome = syn_uncategorized();
-        break;
-    case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
-        target_el = 2;
-        syndrome = syn_uncategorized();
-        break;
-    case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
-        target_el = 3;
         syndrome = syn_uncategorized();
         break;
     default:
         g_assert_not_reached();
     }
 
-exept:
+    target_el = res & CP_ACCESS_EL_MASK;
+    switch (target_el) {
+    case 0:
+        target_el = exception_target_el(env);
+        break;
+    case 2:
+        assert(arm_current_el(env) != 3);
+        assert(arm_is_el2_enabled(env));
+        break;
+    case 3:
+        assert(arm_feature(env, ARM_FEATURE_EL3));
+        break;
+    default:
+        /* No "direct" traps to EL1 */
+        g_assert_not_reached();
+    }
+
     raise_exception(env, EXCP_UDEF, syndrome, target_el);
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Remove a possible source of error by removing REGINFO_SENTINEL
and using ARRAY_SIZE (convinently hidden inside a macro) to
find the end of the set of regs being registered or modified.

The space saved by not having the extra array element reduces
the executable's .data.rel.ro section by about 9k.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h       |  53 +++++++++---------
 hw/arm/pxa2xx.c           |   1 -
 hw/arm/pxa2xx_pic.c       |   1 -
 hw/intc/arm_gicv3_cpuif.c |   5 --
 hw/intc/arm_gicv3_kvm.c   |   1 -
 target/arm/cpu64.c        |   1 -
 target/arm/cpu_tcg.c      |   4 --
 target/arm/helper.c       | 111 ++++++++------------------------------
 8 files changed, 48 insertions(+), 129 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
 #define ARM_CP_NO_GDB            0x4000
 #define ARM_CP_RAISES_EXC        0x8000
 #define ARM_CP_NEWEL             0x10000
-/* Used only as a terminator for ARMCPRegInfo lists */
-#define ARM_CP_SENTINEL          0xfffff
 /* Mask of only the flag bits in a type field */
 #define ARM_CP_FLAG_MASK         0x1f0ff
 
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
 };
 
-/*
- * Return true if cptype is a valid type field. This is used to try to
- * catch errors where the sentinel has been accidentally left off the end
- * of a list of registers.
- */
-static inline bool cptype_valid(int cptype)
-{
-    return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
-        || ((cptype & ARM_CP_SPECIAL) &&
-            ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
-}
-
 /*
  * Access rights:
  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
 #define CPREG_FIELD64(env, ri) \
     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
+                                       void *opaque);
 
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque);
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
-                                       const ARMCPRegInfo *regs, void *opaque);
-static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
-    define_arm_cp_regs_with_opaque(cpu, regs, 0);
-}
 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 {
-    define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
+    define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
 }
+
+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+                                        void *opaque, size_t len);
+
+#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE)               \
+    do {                                                                \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
+        define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE,           \
+                                           ARRAY_SIZE(REGS));           \
+    } while (0)
+
+#define define_arm_cp_regs(CPU, REGS) \
+    define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
+
 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
 
 /*
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCPRegUserSpaceInfo {
     uint64_t fixed_bits;
 } ARMCPRegUserSpaceInfo;
 
-#define REGUSERINFO_SENTINEL { .name = NULL }
+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+                                 const ARMCPRegUserSpaceInfo *mods,
+                                 size_t mods_len);
 
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
+#define modify_arm_cp_regs(REGS, MODS)                                  \
+    do {                                                                \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0);                       \
+        QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0);                       \
+        modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS),             \
+                                    MODS, ARRAY_SIZE(MODS));            \
+    } while (0)
 
 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
     { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .type = ARM_CP_IO,
       .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
-    REGINFO_SENTINEL
 };
 
 static void pxa2xx_setup_cp14(PXA2xxState *s)
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
     REGINFO_FOR_PIC_CP("ICLR2", 8),
     REGINFO_FOR_PIC_CP("ICFP2", 9),
     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
-    REGINFO_SENTINEL
 };
 
 static const MemoryRegionOps pxa2xx_pic_ops = {
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
       .readfn = icc_igrpen1_el3_read,
       .writefn = icc_igrpen1_el3_write,
     },
-    REGINFO_SENTINEL
 };
 
 static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = {
       .readfn = ich_vmcr_read,
       .writefn = ich_vmcr_write,
     },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
       .readfn = ich_ap_read,
       .writefn = ich_ap_write,
     },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
       .readfn = ich_ap_read,
       .writefn = ich_ap_write,
     },
-    REGINFO_SENTINEL
 };
 
 static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
                       .readfn = ich_lr_read,
                       .writefn = ich_lr_write,
                     },
-                    REGINFO_SENTINEL
                 };
                 define_arm_cp_regs(cpu, lr_regset);
             }
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
        */
       .resetfn = arm_gicv3_icc_reset,
     },
-    REGINFO_SENTINEL
 };
 
 /**
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
     { .name = "L2MERRSR",
       .cp = 15, .opc1 = 3, .crm = 15,
       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void aarch64_a57_initfn(Object *obj)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a8_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a9_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 #endif
     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void cortex_a7_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST },
     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static void cortex_r5_initfn(Object *obj)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
       .secure = ARM_CP_SECSTATE_S,
       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
      */
     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
       .access = PL1_W, .type = ARM_CP_WFI },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
       .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
-    REGINFO_SENTINEL
 };
 
 typedef struct pm_event {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
       .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
       .writefn = tlbimvaa_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
       .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
       .writefn = tlbimvaa_is_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsset_write,
       .raw_writefn = raw_write },
-    REGINFO_SENTINEL
 };
 
 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
       .accessfn = teehbr_access, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo v6k_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
     },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .readfn = gt_virt_cnt_read,
     },
-    REGINFO_SENTINEL
 };
 
 #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
       .access = PL1_W, .accessfn = ats_access,
       .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
 #endif
-    REGINFO_SENTINEL
 };
 
 /* Return basic MPU access permission bits.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
       .writefn = pmsav7_rgnr_write,
       .resetfn = arm_cp_reset_ignore },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
-    REGINFO_SENTINEL
 };
 
 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_tvm_trvm,
       .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
       .resetvalue = 0, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
       /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
                              offsetof(CPUARMState, cp15.tcr_el[1])} },
-    REGINFO_SENTINEL
 };
 
 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
     { .name = "C9", .cp = 15, .crn = 9,
       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
     { .name = "XSCALE_UNLOCK_DCACHE",
       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
       .access = PL1_RW,
       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
       .resetvalue = (1 << 30) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
       .access = PL1_RW, .resetvalue = 0,
       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
-    REGINFO_SENTINEL
 };
 
 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                              offsetof(CPUARMState, cp15.ttbr1_ns) },
       .writefn = vmsa_ttbr_write, },
-    REGINFO_SENTINEL
 };
 
 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
       .writefn = sdcr_write,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
-    REGINFO_SENTINEL
 };
 
 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .type = ARM_CP_CONST,
       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
       .access = PL2_RW, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 /* Ditto, but for registers which exist in ARMv8 but not v7 */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
       .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
       .access = PL2_RW,
       .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
       .access = PL2_RW,
       .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
       .access = PL2_RW,
       .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
       .writefn = hcr_writehigh },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
       .access = PL2_RW, .accessfn = sel2_access,
       .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae3_write },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tda,
       .type = ARM_CP_NOP },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 /* Return the exception level to which exceptions should be taken
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
               .writefn = dbgbcr_write, .raw_writefn = raw_write
             },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, dbgregs);
     }
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
               .writefn = dbgwcr_write, .raw_writefn = raw_write
             },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, dbgregs);
     }
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .type = ARM_CP_IO,
               .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
               .raw_writefn = pmevtyper_rawwrite },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, pmev_regs);
         g_free(pmevcntr_name);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
               .resetvalue = extract64(cpu->pmceid1, 32, 32) },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, v81_pmu_regs);
     }
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
       .access = PL1_R, .accessfn = access_lor_ns,
       .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 #ifdef TARGET_AARCH64
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_pauth,
       .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo tlbirange_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae3_write },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo tlbios_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
       .access = PL3_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae3is_write },
-    REGINFO_SENTINEL
 };
 
 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rndr_reginfo[] = {
       .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
       .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
       .access = PL0_R, .readfn = rndr_readfn },
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo dcpodp_reg[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
-    REGINFO_SENTINEL
 };
 #endif /*CONFIG_USER_ONLY*/
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
     { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
     { .name = "TCO", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
       .type = ARM_CP_CONST, .access = PL0_RW, },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
       .accessfn = aa64_zva_access,
 #endif
     },
-    REGINFO_SENTINEL
 };
 
 #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
     { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-    REGINFO_SENTINEL
 };
 
 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
       .access = PL1_R,
       .accessfn = access_aa64_tid2,
       .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
-    REGINFO_SENTINEL
 };
 
 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
       .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
       .accessfn = access_joscr_jmcr,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo vhe_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
       .access = PL2_RW, .accessfn = e2h_access,
       .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
 #endif
-    REGINFO_SENTINEL
 };
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write64 },
-    REGINFO_SENTINEL
 };
 
 static const ARMCPRegInfo ats1cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write },
-    REGINFO_SENTINEL
 };
 #endif
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
       .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
       .access = PL2_RW, .type = ARM_CP_CONST,
       .resetvalue = 0 },
-    REGINFO_SENTINEL
 };
 
 void register_cp_regs_for_features(ARMCPU *cpu)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa32_tid3,
               .resetvalue = cpu->isar.id_isar6 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, v6_idregs);
         define_arm_cp_regs(cpu, v6_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
               .resetvalue = cpu->pmceid1 },
-            REGINFO_SENTINEL
         };
 #ifdef CONFIG_USER_ONLY
         ARMCPRegUserSpaceInfo v8_user_idregs[] = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .exported_bits = 0x000000f0ffffffff },
             { .name = "ID_AA64ISAR*_EL1_RESERVED",
               .is_glob = true                     },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(v8_idregs, v8_user_idregs);
 #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL2_RW,
               .resetvalue = vmpidr_def,
               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, vpidr_regs);
         define_arm_cp_regs(cpu, el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                   .access = PL2_RW, .accessfn = access_el3_aa32ns,
                   .type = ARM_CP_NO_RAW,
                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
-                REGINFO_SENTINEL
             };
             define_arm_cp_regs(cpu, vpidr_regs);
             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .raw_writefn = raw_write, .writefn = sctlr_write,
               .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
               .resetvalue = cpu->reset_sctlr },
-            REGINFO_SENTINEL
         };
 
         define_arm_cp_regs(cpu, el3_regs);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "DUMMY",
               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R,
               .accessfn = access_aa64_tid1,
               .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
-            REGINFO_SENTINEL
         };
         ARMCPRegInfo id_cp_reginfo[] = {
             /* These are common to v8 and pre-v8 */
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R,
               .accessfn = access_aa32_tid1,
               .type = ARM_CP_CONST, .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         /* TLBTR is specific to VMSA */
         ARMCPRegInfo id_tlbtr_reginfo = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "MIDR_EL1",
               .exported_bits = 0x00000000ffffffff },
             { .name = "REVIDR_EL1"                },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
 #endif
         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
             arm_feature(env, ARM_FEATURE_STRONGARM)) {
-            ARMCPRegInfo *r;
+            size_t i;
             /* Register the blanket "writes ignored" value first to cover the
              * whole space. Then update the specific ID registers to allow write
              * access, so that they ignore writes rather than causing them to
              * UNDEF.
              */
             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
-            for (r = id_pre_v8_midr_cp_reginfo;
-                 r->type != ARM_CP_SENTINEL; r++) {
-                r->access = PL1_RW;
+            for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) {
+                id_pre_v8_midr_cp_reginfo[i].access = PL1_RW;
             }
-            for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
-                r->access = PL1_RW;
+            for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) {
+                id_cp_reginfo[i].access = PL1_RW;
             }
             id_mpuir_reginfo.access = PL1_RW;
             id_tlbtr_reginfo.access = PL1_RW;
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
-            REGINFO_SENTINEL
         };
 #ifdef CONFIG_USER_ONLY
         ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
             { .name = "MPIDR_EL1",
               .fixed_bits = 0x0000000080000000 },
-            REGUSERINFO_SENTINEL
         };
         modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
 #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
               .access = PL3_RW, .type = ARM_CP_CONST,
               .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, auxcr_reginfo);
         if (cpu_isar_feature(aa32_ac2, cpu)) {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                   .type = ARM_CP_CONST,
                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
-                REGINFO_SENTINEL
             };
             /* We don't implement a r/w 64 bit CBAR currently */
             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                      offsetof(CPUARMState, cp15.vbar_ns) },
               .resetvalue = 0 },
-            REGINFO_SENTINEL
         };
         define_arm_cp_regs(cpu, vbar_cp_reginfo);
     }
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                    r->writefn);
         }
     }
-    /* Bad type field probably means missing sentinel at end of reg list */
-    assert(cptype_valid(r->type));
+
     for (crm = crmmin; crm <= crmmax; crm++) {
         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
     }
 }
 
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
-                                    const ARMCPRegInfo *regs, void *opaque)
+/* Define a whole list of registers */
+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+                                        void *opaque, size_t len)
 {
-    /* Define a whole list of registers */
-    const ARMCPRegInfo *r;
-    for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
-        define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
+    size_t i;
+    for (i = 0; i < len; ++i) {
+        define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
  * user-space cannot alter any values and dynamic values pertaining to
  * execution state are hidden from user space view anyway.
  */
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+                                 const ARMCPRegUserSpaceInfo *mods,
+                                 size_t mods_len)
 {
-    const ARMCPRegUserSpaceInfo *m;
-    ARMCPRegInfo *r;
-
-    for (m = mods; m->name; m++) {
+    for (size_t mi = 0; mi < mods_len; ++mi) {
+        const ARMCPRegUserSpaceInfo *m = mods + mi;
         GPatternSpec *pat = NULL;
+
         if (m->is_glob) {
             pat = g_pattern_spec_new(m->name);
         }
-        for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
+        for (size_t ri = 0; ri < regs_len; ++ri) {
+            ARMCPRegInfo *r = regs + ri;
+
             if (pat && g_pattern_match_string(pat, r->name)) {
                 r->type = ARM_CP_CONST;
                 r->access = PL0U_R;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These particular data structures are not modified at runtime.

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .resetvalue = cpu->pmceid1 },
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+        static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
             { .name = "ID_AA64PFR0_EL1",
               .exported_bits = 0x000f000f00ff0000,
               .fixed_bits    = 0x0000000000000011 },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      */
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR", .type = ARM_CP_CONST,
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL1_RW, .accessfn = nsacr_access,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             };
             define_one_arm_cp_reg(cpu, &nsacr);
         } else {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR",
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL3_RW | PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
     } else {
         if (arm_feature(env, ARM_FEATURE_V8)) {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR", .type = ARM_CP_CONST,
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL1_R,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = cpu->pmsav7_dregion << 8
         };
-        ARMCPRegInfo crn0_wi_reginfo = {
+        static const ARMCPRegInfo crn0_wi_reginfo = {
             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
+        static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1",
               .exported_bits = 0x00000000ffffffff },
             { .name = "REVIDR_EL1"                },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
+        static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
             { .name = "MPIDR_EL1",
               .fixed_bits = 0x0000000080000000 },
         };
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (arm_feature(env, ARM_FEATURE_VBAR)) {
-        ARMCPRegInfo vbar_cp_reginfo[] = {
+        static const ARMCPRegInfo vbar_cp_reginfo[] = {
             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
               .access = PL1_RW, .writefn = vbar_write,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Instead of defining ARM_CP_FLAG_MASK to remove flags,
define ARM_CP_SPECIAL_MASK to isolate special cases.
Sort the specials to the low bits. Use an enum.

Split the large comment block so as to document each
value separately.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h        | 130 +++++++++++++++++++++++--------------
 target/arm/cpu.c           |   4 +-
 target/arm/helper.c        |   4 +-
 target/arm/translate-a64.c |   6 +-
 target/arm/translate.c     |   6 +-
 5 files changed, 92 insertions(+), 58 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@
 #define TARGET_ARM_CPREGS_H
 
 /*
- * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
- * special-behaviour cp reg and bits [11..8] indicate what behaviour
- * it has. Otherwise it is a simple cp reg, where CONST indicates that
- * TCG can assume the value to be constant (ie load at translate time)
- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
- * indicates that the TB should not be ended after a write to this register
- * (the default is that the TB ends after cp writes). OVERRIDE permits
- * a register definition to override a previous definition for the
- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
- * old must have the OVERRIDE bit set.
- * ALIAS indicates that this register is an alias view of some underlying
- * state which is also visible via another register, and that the other
- * register is handling migration and reset; registers marked ALIAS will not be
- * migrated but may have their state set by syncing of register state from KVM.
- * NO_RAW indicates that this register has no underlying state and does not
- * support raw access for state saving/loading; it will not be used for either
- * migration or KVM state synchronization. (Typically this is for "registers"
- * which are actually used as instructions for cache maintenance and so on.)
- * IO indicates that this register does I/O and therefore its accesses
- * need to be marked with gen_io_start() and also end the TB. In particular,
- * registers which implement clocks or timers require this.
- * RAISES_EXC is for when the read or write hook might raise an exception;
- * the generated code will synchronize the CPU state before calling the hook
- * so that it is safe for the hook to call raise_exception().
- * NEWEL is for writes to registers that might change the exception
- * level - typically on older ARM chips. For those cases we need to
- * re-read the new el when recomputing the translation flags.
+ * ARMCPRegInfo type field bits:
  */
-#define ARM_CP_SPECIAL           0x0001
-#define ARM_CP_CONST             0x0002
-#define ARM_CP_64BIT             0x0004
-#define ARM_CP_SUPPRESS_TB_END   0x0008
-#define ARM_CP_OVERRIDE          0x0010
-#define ARM_CP_ALIAS             0x0020
-#define ARM_CP_IO                0x0040
-#define ARM_CP_NO_RAW            0x0080
-#define ARM_CP_NOP               (ARM_CP_SPECIAL | 0x0100)
-#define ARM_CP_WFI               (ARM_CP_SPECIAL | 0x0200)
-#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)
-#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)
-#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)
-#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)
-#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)
-#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA
-#define ARM_CP_FPU               0x1000
-#define ARM_CP_SVE               0x2000
-#define ARM_CP_NO_GDB            0x4000
-#define ARM_CP_RAISES_EXC        0x8000
-#define ARM_CP_NEWEL             0x10000
-/* Mask of only the flag bits in a type field */
-#define ARM_CP_FLAG_MASK         0x1f0ff
+enum {
+    /*
+     * Register must be handled specially during translation.
+     * The method is one of the values below:
+     */
+    ARM_CP_SPECIAL_MASK          = 0x000f,
+    /* Special: no change to PE state: writes ignored, reads ignored. */
+    ARM_CP_NOP                   = 0x0001,
+    /* Special: sysreg is WFI, for v5 and v6. */
+    ARM_CP_WFI                   = 0x0002,
+    /* Special: sysreg is NZCV. */
+    ARM_CP_NZCV                  = 0x0003,
+    /* Special: sysreg is CURRENTEL. */
+    ARM_CP_CURRENTEL             = 0x0004,
+    /* Special: sysreg is DC ZVA or similar. */
+    ARM_CP_DC_ZVA                = 0x0005,
+    ARM_CP_DC_GVA                = 0x0006,
+    ARM_CP_DC_GZVA               = 0x0007,
+
+    /* Flag: reads produce resetvalue; writes ignored. */
+    ARM_CP_CONST                 = 1 << 4,
+    /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
+    ARM_CP_64BIT                 = 1 << 5,
+    /*
+     * Flag: TB should not be ended after a write to this register
+     * (the default is that the TB ends after cp writes).
+     */
+    ARM_CP_SUPPRESS_TB_END       = 1 << 6,
+    /*
+     * Flag: Permit a register definition to override a previous definition
+     * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new
+     * or the old must have the ARM_CP_OVERRIDE bit set.
+     */
+    ARM_CP_OVERRIDE              = 1 << 7,
+    /*
+     * Flag: Register is an alias view of some underlying state which is also
+     * visible via another register, and that the other register is handling
+     * migration and reset; registers marked ARM_CP_ALIAS will not be migrated
+     * but may have their state set by syncing of register state from KVM.
+     */
+    ARM_CP_ALIAS                 = 1 << 8,
+    /*
+     * Flag: Register does I/O and therefore its accesses need to be marked
+     * with gen_io_start() and also end the TB. In particular, registers which
+     * implement clocks or timers require this.
+     */
+    ARM_CP_IO                    = 1 << 9,
+    /*
+     * Flag: Register has no underlying state and does not support raw access
+     * for state saving/loading; it will not be used for either migration or
+     * KVM state synchronization. Typically this is for "registers" which are
+     * actually used as instructions for cache maintenance and so on.
+     */
+    ARM_CP_NO_RAW                = 1 << 10,
+    /*
+     * Flag: The read or write hook might raise an exception; the generated
+     * code will synchronize the CPU state before calling the hook so that it
+     * is safe for the hook to call raise_exception().
+     */
+    ARM_CP_RAISES_EXC            = 1 << 11,
+    /*
+     * Flag: Writes to the sysreg might change the exception level - typically
+     * on older ARM chips. For those cases we need to re-read the new el when
+     * recomputing the translation flags.
+     */
+    ARM_CP_NEWEL                 = 1 << 12,
+    /*
+     * Flag: Access check for this sysreg is identical to accessing FPU state
+     * from an instruction: use translation fp_access_check().
+     */
+    ARM_CP_FPU                   = 1 << 13,
+    /*
+     * Flag: Access check for this sysreg is identical to accessing SVE state
+     * from an instruction: use translation sve_access_check().
+     */
+    ARM_CP_SVE                   = 1 << 14,
+    /* Flag: Do not expose in gdb sysreg xml. */
+    ARM_CP_NO_GDB                = 1 << 15,
+};
 
 /*
  * Valid values for ARMCPRegInfo state field, indicating which of
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
     ARMCPRegInfo *ri = value;
     ARMCPU *cpu = opaque;
 
-    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
     ARMCPU *cpu = opaque;
     uint64_t oldvalue, newvalue;
 
-    if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
+    if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
         return;
     }
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * multiple times. Special registers (ie NOP/WFI) are
      * never migratable and not even raw-accessible.
      */
-    if ((r->type & ARM_CP_SPECIAL)) {
+    if (r->type & ARM_CP_SPECIAL_MASK) {
         r2->type |= ARM_CP_NO_RAW;
     }
     if (((r->crm == CP_ANY) && crm != 0) ||
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
     /* Check that the register definition has enough info to handle
      * reads and writes if they are permitted.
      */
-    if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
+    if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
         if (r->access & PL3_R) {
             assert((r->fieldoffset ||
                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
     }
 
     /* Handle special cases first */
-    switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
+    switch (ri->type & ARM_CP_SPECIAL_MASK) {
+    case 0:
+        break;
     case ARM_CP_NOP:
         return;
     case ARM_CP_NZCV:
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         }
         return;
     default:
-        break;
+        g_assert_not_reached();
     }
     if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
         return;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
         }
 
         /* Handle special cases first */
-        switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
+        switch (ri->type & ARM_CP_SPECIAL_MASK) {
+        case 0:
+            break;
         case ARM_CP_NOP:
             return;
         case ARM_CP_WFI:
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
             s->base.is_jmp = DISAS_WFI;
             return;
         default:
-            break;
+            g_assert_not_reached();
         }
 
         if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Standardize on g_assert_not_reached() for "should not happen".
Retain abort() when preceeded by fprintf or error_report.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c         | 7 +++----
 target/arm/hvf/hvf.c        | 2 +-
 target/arm/kvm-stub.c       | 4 ++--
 target/arm/kvm.c            | 4 ++--
 target/arm/machine.c        | 4 ++--
 target/arm/translate-a64.c  | 4 ++--
 target/arm/translate-neon.c | 2 +-
 target/arm/translate.c      | 4 ++--
 8 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
             break;
         default:
             /* broken reginfo with out-of-range opc1 */
-            assert(false);
-            break;
+            g_assert_not_reached();
         }
         /* assert our permissions are not too lax (stricter is fine) */
         assert((r->access & ~mask) == 0);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
             break;
         default:
             /* Never happens, but compiler isn't smart enough to tell.  */
-            abort();
+            g_assert_not_reached();
         }
     }
     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
             break;
         default:
             /* Never happens, but compiler isn't smart enough to tell.  */
-            abort();
+            g_assert_not_reached();
         }
     }
     if (domain_prot == 3) {
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
         /* we got kicked, no exit to process */
         return 0;
     default:
-        assert(0);
+        g_assert_not_reached();
     }
 
     hvf_sync_vtimer(cpu);
diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm-stub.c
+++ b/target/arm/kvm-stub.c
@@ -XXX,XX +XXX,XX @@
 
 bool write_kvmstate_to_list(ARMCPU *cpu)
 {
-    abort();
+    g_assert_not_reached();
 }
 
 bool write_list_to_kvmstate(ARMCPU *cpu, int level)
 {
-    abort();
+    g_assert_not_reached();
 }
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
             ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         if (ret) {
             ok = false;
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
             r.addr = (uintptr_t)(cpu->cpreg_values + i);
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
         if (ret) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
     if (kvm_enabled()) {
         if (!write_kvmstate_to_list(cpu)) {
             /* This should never fail */
-            abort();
+            g_assert_not_reached();
         }
 
         /*
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
     } else {
         if (!write_cpustate_to_list(cpu, false)) {
             /* This should never fail. */
-            abort();
+            g_assert_not_reached();
         }
     }
 
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
         gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
 
     write_fp_sreg(s, rd, tcg_res);
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
         break;
     }
     default:
-        abort();
+        g_assert_not_reached();
     }
 }
 
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
         }
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
     if ((vd + a->stride * (nregs - 1)) > 31) {
         /*
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
         offset = 4;
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
     tcg_gen_addi_i32(addr, addr, offset);
     tmp = load_reg(s, 14);
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
             offset = 0;
             break;
         default:
-            abort();
+            g_assert_not_reached();
         }
         tcg_gen_addi_i32(addr, addr, offset);
         gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a typedef as well, and use it in ARMCPRegInfo.
This won't be perfect for debugging, but it'll nicely
display the most common cases.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 44 +++++++++++++++++++++++---------------------
 target/arm/helper.c |  2 +-
 2 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
  * described with these bits, then use a laxer set of restrictions, and
  * do the more restrictive/complex check inside a helper function.
  */
-#define PL3_R 0x80
-#define PL3_W 0x40
-#define PL2_R (0x20 | PL3_R)
-#define PL2_W (0x10 | PL3_W)
-#define PL1_R (0x08 | PL2_R)
-#define PL1_W (0x04 | PL2_W)
-#define PL0_R (0x02 | PL1_R)
-#define PL0_W (0x01 | PL1_W)
+typedef enum {
+    PL3_R = 0x80,
+    PL3_W = 0x40,
+    PL2_R = 0x20 | PL3_R,
+    PL2_W = 0x10 | PL3_W,
+    PL1_R = 0x08 | PL2_R,
+    PL1_W = 0x04 | PL2_W,
+    PL0_R = 0x02 | PL1_R,
+    PL0_W = 0x01 | PL1_W,
 
-/*
- * For user-mode some registers are accessible to EL0 via a kernel
- * trap-and-emulate ABI. In this case we define the read permissions
- * as actually being PL0_R. However some bits of any given register
- * may still be masked.
- */
+    /*
+     * For user-mode some registers are accessible to EL0 via a kernel
+     * trap-and-emulate ABI. In this case we define the read permissions
+     * as actually being PL0_R. However some bits of any given register
+     * may still be masked.
+     */
 #ifdef CONFIG_USER_ONLY
-#define PL0U_R PL0_R
+    PL0U_R = PL0_R,
 #else
-#define PL0U_R PL1_R
+    PL0U_R = PL1_R,
 #endif
 
-#define PL3_RW (PL3_R | PL3_W)
-#define PL2_RW (PL2_R | PL2_W)
-#define PL1_RW (PL1_R | PL1_W)
-#define PL0_RW (PL0_R | PL0_W)
+    PL3_RW = PL3_R | PL3_W,
+    PL2_RW = PL2_R | PL2_W,
+    PL1_RW = PL1_R | PL1_W,
+    PL0_RW = PL0_R | PL0_W,
+} CPAccessRights;
 
 typedef enum CPAccessResult {
     /* Access is permitted */
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     /* Register type: ARM_CP_* bits/values */
     int type;
     /* Access rights: PL*_[RW] */
-    int access;
+    CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
     int secure;
     /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      * to encompass the generic architectural permission check.
      */
     if (r->state != ARM_CP_STATE_AA32) {
-        int mask = 0;
+        CPAccessRights mask;
         switch (r->opc1) {
         case 0:
             /* min_EL EL1, but some accessible to EL0 via kernel ABI */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Give this enum a name and use in ARMCPRegInfo,
add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
  * Note that we rely on the values of these enums as we iterate through
  * the various states in some places.
  */
-enum {
+typedef enum {
     ARM_CP_STATE_AA32 = 0,
     ARM_CP_STATE_AA64 = 1,
     ARM_CP_STATE_BOTH = 2,
-};
+} CPState;
 
 /*
  * ARM CP register secure state flags.  These flags identify security state
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     uint8_t opc1;
     uint8_t opc2;
     /* Execution state in which this register is visible: ARM_CP_STATE_* */
-    int state;
+    CPState state;
     /* Register type: ARM_CP_* bits/values */
     int type;
     /* Access rights: PL*_[RW] */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-                                   void *opaque, int state, int secstate,
+                                   void *opaque, CPState state, int secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
      * the register, if any.
      */
-    int crm, opc1, opc2, state;
+    int crm, opc1, opc2;
     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
+    CPState state;
+
     /* 64 bit registers have only CRm and Opc1 fields */
     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
     /* op0 only exists in the AArch64 encodings */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 7 ++++---
 target/arm/helper.c | 7 +++++--
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  * registered entry will only have one to identify whether the entry is secure
  * or non-secure.
  */
-enum {
+typedef enum {
+    ARM_CP_SECSTATE_BOTH = 0,       /* define one cpreg for each secstate */
     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
-};
+} CPSecureState;
 
 /*
  * Access rights:
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     /* Access rights: PL*_[RW] */
     CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
-    int secure;
+    CPSecureState secure;
     /*
      * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
      * this register was defined: can be used to hand data through to the
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-                                   void *opaque, CPState state, int secstate,
+                                   void *opaque, CPState state,
+                                   CPSecureState secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                                    r->secure, crm, opc1, opc2,
                                                    r->name);
                             break;
-                        default:
+                        case ARM_CP_SECSTATE_BOTH:
                             name = g_strdup_printf("%s_S", r->name);
                             add_cpreg_to_hashtable(cpu, r, opaque, state,
                                                    ARM_CP_SECSTATE_S,
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                                    ARM_CP_SECSTATE_NS,
                                                    crm, opc1, opc2, r->name);
                             break;
+                        default:
+                            g_assert_not_reached();
                         }
                     } else {
                         /* AArch64 registers get mapped to non-secure instance
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The new_key field is always non-zero -- drop the if.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-11-richard.henderson@linaro.org
[PMM: reinstated dropped PL3_RW mask]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
 
     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
         const struct E2HAlias *a = &aliases[i];
-        ARMCPRegInfo *src_reg, *dst_reg;
+        ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
+        uint32_t *new_key;
+        bool ok;
 
         if (a->feature && !a->feature(&cpu->isar)) {
             continue;
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
         g_assert(src_reg->opaque == NULL);
 
         /* Create alias before redirection so we dup the right data. */
-        if (a->new_key) {
-            ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-            uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
-            bool ok;
+        new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
+        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
 
-            new_reg->name = a->new_name;
-            new_reg->type |= ARM_CP_ALIAS;
-            /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
-            new_reg->access &= PL2_RW | PL3_RW;
+        new_reg->name = a->new_name;
+        new_reg->type |= ARM_CP_ALIAS;
+        /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
+        new_reg->access &= PL2_RW | PL3_RW;
 
-            ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
-            g_assert(ok);
-        }
+        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
+        g_assert(ok);
 
         src_reg->opaque = dst_reg;
         src_reg->orig_readfn = src_reg->readfn ?: raw_read;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Cast the uint32_t key into a gpointer directly, which
allows us to avoid allocating storage for each key.

Use g_hash_table_lookup when we already have a gpointer
(e.g. for callbacks like count_cpreg), or when using
get_arm_cp_reginfo would require casting away const.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c     |  4 ++--
 target/arm/gdbstub.c |  2 +-
 target/arm/helper.c  | 41 ++++++++++++++++++-----------------------
 3 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
     ARMCPU *cpu = ARM_CPU(obj);
 
     cpu_set_cpustate_pointers(cpu);
-    cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
-                                         g_free, cpreg_hashtable_data_destroy);
+    cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
+                                         NULL, cpreg_hashtable_data_destroy);
 
     QLIST_INIT(&cpu->pre_el_change_hooks);
     QLIST_INIT(&cpu->el_change_hooks);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
 static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
                                         gpointer p)
 {
-    uint32_t ri_key = *(uint32_t *)key;
+    uint32_t ri_key = (uintptr_t)key;
     ARMCPRegInfo *ri = value;
     RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
     GString *s = param->s;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 {
     ARMCPU *cpu = opaque;
-    uint64_t regidx;
-    const ARMCPRegInfo *ri;
-
-    regidx = *(uint32_t *)key;
-    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+    uint32_t regidx = (uintptr_t)key;
+    const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 
     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
 static void count_cpreg(gpointer key, gpointer opaque)
 {
     ARMCPU *cpu = opaque;
-    uint64_t regidx;
     const ARMCPRegInfo *ri;
 
-    regidx = *(uint32_t *)key;
-    ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+    ri = g_hash_table_lookup(cpu->cp_regs, key);
 
     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
         cpu->cpreg_array_len++;
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
 
 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 {
-    uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
-    uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
+    uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a);
+    uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b);
 
     if (aidx > bidx) {
         return 1;
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
     for (i = 0; i < ARRAY_SIZE(aliases); i++) {
         const struct E2HAlias *a = &aliases[i];
         ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
-        uint32_t *new_key;
         bool ok;
 
         if (a->feature && !a->feature(&cpu->isar)) {
             continue;
         }
 
-        src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
-        dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
+        src_reg = g_hash_table_lookup(cpu->cp_regs,
+                                      (gpointer)(uintptr_t)a->src_key);
+        dst_reg = g_hash_table_lookup(cpu->cp_regs,
+                                      (gpointer)(uintptr_t)a->dst_key);
         g_assert(src_reg != NULL);
         g_assert(dst_reg != NULL);
 
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
 
         /* Create alias before redirection so we dup the right data. */
         new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
-        new_key = g_memdup(&a->new_key, sizeof(uint32_t));
 
         new_reg->name = a->new_name;
         new_reg->type |= ARM_CP_ALIAS;
         /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place.  */
         new_reg->access &= PL2_RW | PL3_RW;
 
-        ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
+        ok = g_hash_table_insert(cpu->cp_regs,
+                                 (gpointer)(uintptr_t)a->new_key, new_reg);
         g_assert(ok);
 
         src_reg->opaque = dst_reg;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     /* Private utility function for define_one_arm_cp_reg_with_opaque():
      * add a single reginfo struct to the hash table.
      */
-    uint32_t *key = g_new(uint32_t, 1);
+    uint32_t key;
     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
             r2->cp = CP_REG_ARM64_SYSREG_CP;
         }
-        *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
-                                  r2->opc0, opc1, opc2);
+        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
+                                 r2->opc0, opc1, opc2);
     } else {
-        *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
+        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
     }
     if (opaque) {
         r2->opaque = opaque;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * requested.
      */
     if (!(r->type & ARM_CP_OVERRIDE)) {
-        ARMCPRegInfo *oldreg;
-        oldreg = g_hash_table_lookup(cpu->cp_regs, key);
+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
             fprintf(stderr, "Register redefined: cp=%d %d bit "
                     "crn=%d crm=%d opc1=%d opc2=%d, "
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
             g_assert_not_reached();
         }
     }
-    g_hash_table_insert(cpu->cp_regs, key, r2);
+    g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
 }
 
 
@@ -XXX,XX +XXX,XX @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
 
 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
 {
-    return g_hash_table_lookup(cpregs, &encoded_cp);
+    return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp);
 }
 
 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Simplify freeing cp_regs hash table entries by using a single
allocation for the entire value.

This fixes a theoretical bug if we were to ever free the entire
hash table, because we've been installing string literal constants
into the cpreg structure in define_arm_vh_e2h_redirects_aliases.
However, at present we only free entries created for AArch32
wildcard cpregs which get overwritten by more specific cpregs,
so this bug is never exposed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c    | 16 +---------------
 target/arm/helper.c | 10 ++++++++--
 2 files changed, 9 insertions(+), 17 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 }
 
-static void cpreg_hashtable_data_destroy(gpointer data)
-{
-    /*
-     * Destroy function for cpu->cp_regs hashtable data entries.
-     * We must free the name string because it was g_strdup()ed in
-     * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
-     * from r->name because we know we definitely allocated it.
-     */
-    ARMCPRegInfo *r = data;
-
-    g_free((void *)r->name);
-    g_free(r);
-}
-
 static void arm_cpu_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
     cpu_set_cpustate_pointers(cpu);
     cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
-                                         NULL, cpreg_hashtable_data_destroy);
+                                         NULL, g_free);
 
     QLIST_INIT(&cpu->pre_el_change_hooks);
     QLIST_INIT(&cpu->el_change_hooks);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * add a single reginfo struct to the hash table.
      */
     uint32_t key;
-    ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
+    ARMCPRegInfo *r2;
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+    size_t name_len;
+
+    /* Combine cpreg and name into one allocation. */
+    name_len = strlen(name) + 1;
+    r2 = g_malloc(sizeof(*r2) + name_len);
+    *r2 = *r;
+    r2->name = memcpy(r2 + 1, name, name_len);
 
-    r2->name = g_strdup(name);
     /* Reset the secure state to the specific incoming state.  This is
      * necessary as the register may have been defined with both states.
      */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the computation of key to the top of the function.
Hoist the resolution of cp as well, as an input to the
computation of key.

This will be required by a subsequent patch.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 49 +++++++++++++++++++++++++--------------------
 1 file changed, 27 insertions(+), 22 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     ARMCPRegInfo *r2;
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+    int cp = r->cp;
     size_t name_len;
 
+    switch (state) {
+    case ARM_CP_STATE_AA32:
+        /* We assume it is a cp15 register if the .cp field is left unset. */
+        if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
+            cp = 15;
+        }
+        key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
+        break;
+    case ARM_CP_STATE_AA64:
+        /*
+         * To allow abbreviation of ARMCPRegInfo definitions, we treat
+         * cp == 0 as equivalent to the value for "standard guest-visible
+         * sysreg".  STATE_BOTH definitions are also always "standard sysreg"
+         * in their AArch64 view (the .cp value may be non-zero for the
+         * benefit of the AArch32 view).
+         */
+        if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+            cp = CP_REG_ARM64_SYSREG_CP;
+        }
+        key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
 
         if (r->state == ARM_CP_STATE_BOTH) {
-            /* We assume it is a cp15 register if the .cp field is left unset.
-             */
-            if (r2->cp == 0) {
-                r2->cp = 15;
-            }
-
 #if HOST_BIG_ENDIAN
             if (r2->fieldoffset) {
                 r2->fieldoffset += sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 #endif
         }
     }
-    if (state == ARM_CP_STATE_AA64) {
-        /* To allow abbreviation of ARMCPRegInfo
-         * definitions, we treat cp == 0 as equivalent to
-         * the value for "standard guest-visible sysreg".
-         * STATE_BOTH definitions are also always "standard
-         * sysreg" in their AArch64 view (the .cp value may
-         * be non-zero for the benefit of the AArch32 view).
-         */
-        if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
-            r2->cp = CP_REG_ARM64_SYSREG_CP;
-        }
-        key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
-                                 r2->opc0, opc1, opc2);
-    } else {
-        key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
-    }
     if (opaque) {
         r2->opaque = opaque;
     }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     /* Make sure reginfo passed to helpers for wildcarded regs
      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
      */
+    r2->cp = cp;
     r2->crm = crm;
     r2->opc1 = opc1;
     r2->opc2 = opc2;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Put most of the value writeback to the same place,
and improve the comment that goes with them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
     *r2 = *r;
     r2->name = memcpy(r2 + 1, name, name_len);
 
-    /* Reset the secure state to the specific incoming state.  This is
-     * necessary as the register may have been defined with both states.
+    /*
+     * Update fields to match the instantiation, overwiting wildcards
+     * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
      */
+    r2->cp = cp;
+    r2->crm = crm;
+    r2->opc1 = opc1;
+    r2->opc2 = opc2;
+    r2->state = state;
     r2->secure = secstate;
+    if (opaque) {
+        r2->opaque = opaque;
+    }
 
     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
         /* Register is banked (using both entries in array).
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 #endif
         }
     }
-    if (opaque) {
-        r2->opaque = opaque;
-    }
-    /* reginfo passed to helpers is correct for the actual access,
-     * and is never ARM_CP_STATE_BOTH:
-     */
-    r2->state = state;
-    /* Make sure reginfo passed to helpers for wildcarded regs
-     * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
-     */
-    r2->cp = cp;
-    r2->crm = crm;
-    r2->opc1 = opc1;
-    r2->opc2 = opc2;
+
     /* By convention, for wildcarded registers only the first
      * entry is used for migration; the others are marked as
      * ALIAS so we don't try to transfer the register
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Computing isbanked only once makes the code
a bit easier to read.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Perform the override check early, so that it is still done
even when we decide to discard an unreachable cpreg.

Use assert not printf+abort.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         g_assert_not_reached();
     }
 
+    /* Overriding of an existing definition must be explicitly requested. */
+    if (!(r->type & ARM_CP_OVERRIDE)) {
+        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
+        if (oldreg) {
+            assert(oldreg->type & ARM_CP_OVERRIDE);
+        }
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         assert(!raw_accessors_invalid(r2));
     }
 
-    /* Overriding of an existing definition must be explicitly
-     * requested.
-     */
-    if (!(r->type & ARM_CP_OVERRIDE)) {
-        const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
-        if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
-            fprintf(stderr, "Register redefined: cp=%d %d bit "
-                    "crn=%d crm=%d opc1=%d opc2=%d, "
-                    "was %s, now %s\n", r2->cp, 32 + 32 * is64,
-                    r2->crn, r2->crm, r2->opc1, r2->opc2,
-                    oldreg->name, r2->name);
-            g_assert_not_reached();
-        }
-    }
     g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Put the block comments into the current coding style.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
     return cpu_list;
 }
 
+/*
+ * Private utility function for define_one_arm_cp_reg_with_opaque():
+ * add a single reginfo struct to the hash table.
+ */
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                    void *opaque, CPState state,
                                    CPSecureState secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
-    /* Private utility function for define_one_arm_cp_reg_with_opaque():
-     * add a single reginfo struct to the hash table.
-     */
     uint32_t key;
     ARMCPRegInfo *r2;
     bool is64 = r->type & ARM_CP_64BIT;
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 
     isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
     if (isbanked) {
-        /* Register is banked (using both entries in array).
+        /*
+         * Register is banked (using both entries in array).
          * Overwriting fieldoffset as the array is only used to define
          * banked registers but later only fieldoffset is used.
          */
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 
     if (state == ARM_CP_STATE_AA32) {
         if (isbanked) {
-            /* If the register is banked then we don't need to migrate or
+            /*
+             * If the register is banked then we don't need to migrate or
              * reset the 32-bit instance in certain cases:
              *
              * 1) If the register has both 32-bit and 64-bit instances then we
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                 r2->type |= ARM_CP_ALIAS;
             }
         } else if ((secstate != r->secure) && !ns) {
-            /* The register is not banked so we only want to allow migration of
-             * the non-secure instance.
+            /*
+             * The register is not banked so we only want to allow migration
+             * of the non-secure instance.
              */
             r2->type |= ARM_CP_ALIAS;
         }
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
     }
 
-    /* By convention, for wildcarded registers only the first
+    /*
+     * By convention, for wildcarded registers only the first
      * entry is used for migration; the others are marked as
      * ALIAS so we don't try to transfer the register
      * multiple times. Special registers (ie NOP/WFI) are
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
     }
 
-    /* Check that raw accesses are either forbidden or handled. Note that
+    /*
+     * Check that raw accesses are either forbidden or handled. Note that
      * we can't assert this earlier because the setup of fieldoffset for
      * banked registers has to be done first.
      */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Since e03b56863d2bc, our host endian indicator is unconditionally
set, which means that we can use a normal C condition.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-20-richard.henderson@linaro.org
[PMM: quote correct git hash in commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
             r2->type |= ARM_CP_ALIAS;
         }
 
-        if (r->state == ARM_CP_STATE_BOTH) {
-#if HOST_BIG_ENDIAN
-            if (r2->fieldoffset) {
-                r2->fieldoffset += sizeof(uint32_t);
-            }
-#endif
+        if (HOST_BIG_ENDIAN &&
+            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
+            r2->fieldoffset += sizeof(uint32_t);
         }
     }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
 }
 
+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
 }
 
+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
+}
+
 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
 }
 
+static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
+}
+
 /*
  * Forward to the above feature tests given an ARMCPU pointer.
  */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Add the aa64 predicate for detecting RAS support from id registers.
We already have the aa32 version from the M-profile work.
Add the 'any' predicate for testing both aa64 and aa32.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
 }
 
+static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
+}
+
 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
     return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
 }
 
+static inline bool isar_feature_any_ras(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
+}
+
 /*
  * Forward to the above feature tests given an ARMCPU pointer.
  */
-- 
2.25.1

From: Alex Zuepke <alex.zuepke@tum.de>

The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.

Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
               .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
-              .accessfn = pmreg_access },
+              .accessfn = pmreg_access_xevcntr },
             { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
-              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+              .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
               .type = ARM_CP_IO,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
               .raw_readfn = pmevcntr_rawread,
-- 
2.25.1

I might squeeze in another pullreq before softfreeze, but the
queue was already big enough that I wanted to send this lot out now.

-- PMM

The following changes since commit 4abf70a661a5df3886ac9d7c19c3617fa92b922a:

Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging (2020-07-03 15:34:45 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200703

for you to fetch changes up to 0f10bf84a9d489259a5b11c6aa1b05c1175b76ea:

Deprecate TileGX port (2020-07-03 16:59:46 +0100)

----------------------------------------------------------------
target-arm queue:
 * i.MX6UL EVK board: put PHYs in the correct places
 * hw/arm/virt: Let the virtio-iommu bypass MSIs
 * target/arm: kvm: Handle DABT with no valid ISS
 * hw/arm/virt-acpi-build: Only expose flash on older machine types
 * target/arm: Fix temp double-free in sve ldr/str
 * hw/display/bcm2835_fb.c: Initialize all fields of struct
 * hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak
 * Deprecate TileGX port

----------------------------------------------------------------
Andrew Jones (4):
      tests/acpi: remove stale allowed tables
      tests/acpi: virt: allow DSDT acpi table changes
      hw/arm/virt-acpi-build: Only expose flash on older machine types
      tests/acpi: virt: update golden masters for DSDT

Beata Michalska (2):
      target/arm: kvm: Handle DABT with no valid ISS
      target/arm: kvm: Handle misconfigured dabt injection

Eric Auger (5):
      qdev: Introduce DEFINE_PROP_RESERVED_REGION
      virtio-iommu: Implement RESV_MEM probe request
      virtio-iommu: Handle reserved regions in the translation process
      virtio-iommu-pci: Add array of Interval properties
      hw/arm/virt: Let the virtio-iommu bypass MSIs

Jean-Christophe Dubois (3):
      Add a phy-num property to the i.MX FEC emulator
      Add the ability to select a different PHY for each i.MX6UL FEC interface
      Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.

Peter Maydell (19):
      hw/display/bcm2835_fb.c: Initialize all fields of struct
      hw/arm/spitz: Detabify
      hw/arm/spitz: Create SpitzMachineClass abstract base class
      hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
      hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
      hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
      hw/misc/max111x: provide QOM properties for setting initial values
      hw/misc/max111x: Don't use vmstate_register()
      ssi: Add ssi_realize_and_unref()
      hw/arm/spitz: Use max111x properties to set initial values
      hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
      hw/misc/max111x: Create header file for documentation, TYPE_ macros
      hw/arm/spitz: Encapsulate misc GPIO handling in a device
      hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
      hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
      hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
      hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
      Replace uses of FROM_SSI_SLAVE() macro with QOM casts
      Deprecate TileGX port

Richard Henderson (1):
      target/arm: Fix temp double-free in sve ldr/str

From: Jean-Christophe Dubois <jcd@tribudubois.net>

We need a solution to use an Ethernet PHY that is not the first device
on the MDIO bus (device 0 on MDIO bus).

As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but
only one MDIO bus on which the 2 related PHY are connected but at unique
addresses.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/net/imx_fec.h |  1 +
 hw/net/imx_fec.c         | 24 +++++++++++++++++-------
 hw/net/trace-events      |  4 ++--
 3 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/net/imx_fec.h
+++ b/include/hw/net/imx_fec.h
@@ -XXX,XX +XXX,XX @@ typedef struct IMXFECState {
     uint32_t phy_advertise;
     uint32_t phy_int;
     uint32_t phy_int_mask;
+    uint32_t phy_num;
 
     bool is_fec;
 
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_phy_reset(IMXFECState *s)
 static uint32_t imx_phy_read(IMXFECState *s, int reg)
 {
     uint32_t val;
+    uint32_t phy = reg / 32;
 
-    if (reg > 31) {
-        /* we only advertise one phy */
+    if (phy != s->phy_num) {
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
+                      TYPE_IMX_FEC, __func__, phy);
         return 0;
     }
 
+    reg %= 32;
+
     switch (reg) {
     case 0:     /* Basic Control */
         val = s->phy_control;
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
         break;
     }
 
-    trace_imx_phy_read(val, reg);
+    trace_imx_phy_read(val, phy, reg);
 
     return val;
 }
 
 static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
 {
-    trace_imx_phy_write(val, reg);
+    uint32_t phy = reg / 32;
 
-    if (reg > 31) {
-        /* we only advertise one phy */
+    if (phy != s->phy_num) {
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
+                      TYPE_IMX_FEC, __func__, phy);
         return;
     }
 
+    reg %= 32;
+
+    trace_imx_phy_write(val, phy, reg);
+
     switch (reg) {
     case 0:     /* Basic Control */
         if (val & 0x8000) {
@@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
                                                        extract32(value,
                                                                  18, 10)));
         } else {
-            /* This a write operation */
+            /* This is a write operation */
             imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
         }
         /* raise the interrupt as the PHY operation is done */
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
 static Property imx_eth_properties[] = {
     DEFINE_NIC_PROPERTIES(IMXFECState, conf),
     DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
+    DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/net/trace-events b/hw/net/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
 i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
 
 # imx_fec.c
-imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
-imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
+imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
+imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
 imx_phy_update_link(const char *s) "%s"
 imx_phy_reset(void) ""
 imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
-- 
2.20.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

Add properties to the i.MX6UL processor to be able to select a
particular PHY on the MDIO bus for each FEC device.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 ++
 hw/arm/fsl-imx6ul.c         | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
     MemoryRegion       caam;
     MemoryRegion       ocram;
     MemoryRegion       ocram_alias;
+
+    uint32_t           phy_num[FSL_IMX6UL_NUM_ETHS];
 } FslIMX6ULState;
 
 enum FslIMX6ULMemoryMap {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_ENET2_TIMER_IRQ,
         };
 
+        object_property_set_uint(OBJECT(&s->eth[i]),
+                                 s->phy_num[i],
+                                 "phy-num", &error_abort);
         object_property_set_uint(OBJECT(&s->eth[i]),
                                  FSL_IMX6UL_ETH_NUM_TX_RINGS,
                                  "tx-ring-num", &error_abort);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
 }
 
+static Property fsl_imx6ul_properties[] = {
+    DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
+    DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
+    device_class_set_props(dc, fsl_imx6ul_properties);
     dc->realize = fsl_imx6ul_realize;
     dc->desc = "i.MX6UL SOC";
     /* Reason: Uses serial_hds and nd_table in realize() directly */
-- 
2.20.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The i.MX6UL EVK 14x14 board uses:
- PHY 2 for FEC 1
- PHY 1 for FEC 2

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: fb41992126c091a71d76ab3d1898959091f60583.1593296112.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mcimx6ul-evk.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
 
     s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
     object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
+    object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal);
+    object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal);
     qdev_realize(DEVICE(s), NULL, &error_fatal);
 
     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

Introduce a new property defining a reserved region:
<low address>:<high address>:<type>.

This will be used to encode reserved IOVA regions.

For instance, in virtio-iommu use case, reserved IOVA regions
will be passed by the machine code to the virtio-iommu-pci
device (an array of those). The type of the reserved region
will match the virtio_iommu_probe_resv_mem subtype value:
- VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0)
- VIRTIO_IOMMU_RESV_MEM_T_MSI (1)

on PC/Q35 machine, this will be used to inform the
virtio-iommu-pci device it should bypass the MSI region.
The reserved region will be: 0xfee00000:0xfeefffff:1.

On ARM, we can declare the ITS MSI doorbell as an MSI
region to prevent MSIs from being mapped on guest side.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20200629070404.10969-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/memory.h        |  6 +++
 include/hw/qdev-properties.h |  3 ++
 include/qemu/typedefs.h      |  1 +
 hw/core/qdev-properties.c    | 89 ++++++++++++++++++++++++++++++++++++
 4 files changed, 99 insertions(+)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ extern bool global_dirty_log;
 
 typedef struct MemoryRegionOps MemoryRegionOps;
 
+struct ReservedRegion {
+    hwaddr low;
+    hwaddr high;
+    unsigned type;
+};
+
 typedef struct IOMMUTLBEntry IOMMUTLBEntry;
 
 /* See address_space_translate: bit 0 is read, bit 1 is write.  */
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_string;
 extern const PropertyInfo qdev_prop_chr;
 extern const PropertyInfo qdev_prop_tpm;
 extern const PropertyInfo qdev_prop_macaddr;
+extern const PropertyInfo qdev_prop_reserved_region;
 extern const PropertyInfo qdev_prop_on_off_auto;
 extern const PropertyInfo qdev_prop_multifd_compression;
 extern const PropertyInfo qdev_prop_losttickpolicy;
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_width;
     DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *)
 #define DEFINE_PROP_MACADDR(_n, _s, _f)         \
     DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
+#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f)         \
+    DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion)
 #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
 #define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -XXX,XX +XXX,XX @@ typedef struct ISABus ISABus;
 typedef struct ISADevice ISADevice;
 typedef struct IsaDma IsaDma;
 typedef struct MACAddr MACAddr;
+typedef struct ReservedRegion ReservedRegion;
 typedef struct MachineClass MachineClass;
 typedef struct MachineState MachineState;
 typedef struct MemoryListener MemoryListener;
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -XXX,XX +XXX,XX @@
 #include "chardev/char.h"
 #include "qemu/uuid.h"
 #include "qemu/units.h"
+#include "qemu/cutils.h"
 
 void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
                                   Error **errp)
@@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_macaddr = {
     .set   = set_mac,
 };
 
+/* --- Reserved Region --- */
+
+/*
+ * Accepted syntax:
+ *   <low address>:<high address>:<type>
+ *   where low/high addresses are uint64_t in hexadecimal
+ *   and type is a non-negative decimal integer
+ */
+static void get_reserved_region(Object *obj, Visitor *v, const char *name,
+                                void *opaque, Error **errp)
+{
+    DeviceState *dev = DEVICE(obj);
+    Property *prop = opaque;
+    ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
+    char buffer[64];
+    char *p = buffer;
+    int rc;
+
+    rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u",
+                  rr->low, rr->high, rr->type);
+    assert(rc < sizeof(buffer));
+
+    visit_type_str(v, name, &p, errp);
+}
+
+static void set_reserved_region(Object *obj, Visitor *v, const char *name,
+                                void *opaque, Error **errp)
+{
+    DeviceState *dev = DEVICE(obj);
+    Property *prop = opaque;
+    ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
+    Error *local_err = NULL;
+    const char *endptr;
+    char *str;
+    int ret;
+
+    if (dev->realized) {
+        qdev_prop_set_after_realize(dev, name, errp);
+        return;
+    }
+
+    visit_type_str(v, name, &str, &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    ret = qemu_strtou64(str, &endptr, 16, &rr->low);
+    if (ret) {
+        error_setg(errp, "start address of '%s'"
+                   " must be a hexadecimal integer", name);
+        goto out;
+    }
+    if (*endptr != ':') {
+        goto separator_error;
+    }
+
+    ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high);
+    if (ret) {
+        error_setg(errp, "end address of '%s'"
+                   " must be a hexadecimal integer", name);
+        goto out;
+    }
+    if (*endptr != ':') {
+        goto separator_error;
+    }
+
+    ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type);
+    if (ret) {
+        error_setg(errp, "type of '%s'"
+                   " must be a non-negative decimal integer", name);
+    }
+    goto out;
+
+separator_error:
+    error_setg(errp, "reserved region fields must be separated with ':'");
+out:
+    g_free(str);
+    return;
+}
+
+const PropertyInfo qdev_prop_reserved_region = {
+    .name  = "reserved_region",
+    .description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0",
+    .get   = get_reserved_region,
+    .set   = set_reserved_region,
+};
+
 /* --- on/off/auto --- */
 
 const PropertyInfo qdev_prop_on_off_auto = {
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

This patch implements the PROBE request. At the moment,
only THE RESV_MEM property is handled. The first goal is
to report iommu wide reserved regions such as the MSI regions
set by the machine code. On x86 this will be the IOAPIC MSI
region, [0xFEE00000 - 0xFEEFFFFF], on ARM this may be the ITS
doorbell.

In the future we may introduce per device reserved regions.
This will be useful when protecting host assigned devices
which may expose their own reserved regions

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20200629070404.10969-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/virtio/virtio-iommu.h |  2 +
 hw/virtio/virtio-iommu.c         | 94 ++++++++++++++++++++++++++++++--
 hw/virtio/trace-events           |  1 +
 3 files changed, 93 insertions(+), 4 deletions(-)

diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/virtio/virtio-iommu.h
+++ b/include/hw/virtio/virtio-iommu.h
@@ -XXX,XX +XXX,XX @@ typedef struct VirtIOIOMMU {
     GHashTable *as_by_busptr;
     IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX];
     PCIBus *primary_bus;
+    ReservedRegion *reserved_regions;
+    uint32_t nb_reserved_regions;
     GTree *domains;
     QemuMutex mutex;
     GTree *endpoints;
diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/virtio-iommu.c
+++ b/hw/virtio/virtio-iommu.c
@@ -XXX,XX +XXX,XX @@
 
 /* Max size */
 #define VIOMMU_DEFAULT_QUEUE_SIZE 256
+#define VIOMMU_PROBE_SIZE 512
 
 typedef struct VirtIOIOMMUDomain {
     uint32_t id;
@@ -XXX,XX +XXX,XX @@ static int virtio_iommu_unmap(VirtIOIOMMU *s,
     return ret;
 }
 
+static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep,
+                                               uint8_t *buf, size_t free)
+{
+    struct virtio_iommu_probe_resv_mem prop = {};
+    size_t size = sizeof(prop), length = size - sizeof(prop.head), total;
+    int i;
+
+    total = size * s->nb_reserved_regions;
+
+    if (total > free) {
+        return -ENOSPC;
+    }
+
+    for (i = 0; i < s->nb_reserved_regions; i++) {
+        unsigned subtype = s->reserved_regions[i].type;
+
+        assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED ||
+               subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI);
+        prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM);
+        prop.head.length = cpu_to_le16(length);
+        prop.subtype = subtype;
+        prop.start = cpu_to_le64(s->reserved_regions[i].low);
+        prop.end = cpu_to_le64(s->reserved_regions[i].high);
+
+        memcpy(buf, &prop, size);
+
+        trace_virtio_iommu_fill_resv_property(ep, prop.subtype,
+                                              prop.start, prop.end);
+        buf += size;
+    }
+    return total;
+}
+
+/**
+ * virtio_iommu_probe - Fill the probe request buffer with
+ * the properties the device is able to return
+ */
+static int virtio_iommu_probe(VirtIOIOMMU *s,
+                              struct virtio_iommu_req_probe *req,
+                              uint8_t *buf)
+{
+    uint32_t ep_id = le32_to_cpu(req->endpoint);
+    size_t free = VIOMMU_PROBE_SIZE;
+    ssize_t count;
+
+    if (!virtio_iommu_mr(s, ep_id)) {
+        return VIRTIO_IOMMU_S_NOENT;
+    }
+
+    count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free);
+    if (count < 0) {
+        return VIRTIO_IOMMU_S_INVAL;
+    }
+    buf += count;
+    free -= count;
+
+    return VIRTIO_IOMMU_S_OK;
+}
+
 static int virtio_iommu_iov_to_req(struct iovec *iov,
                                    unsigned int iov_cnt,
                                    void *req, size_t req_sz)
@@ -XXX,XX +XXX,XX @@ virtio_iommu_handle_req(detach)
 virtio_iommu_handle_req(map)
 virtio_iommu_handle_req(unmap)
 
+static int virtio_iommu_handle_probe(VirtIOIOMMU *s,
+                                     struct iovec *iov,
+                                     unsigned int iov_cnt,
+                                     uint8_t *buf)
+{
+    struct virtio_iommu_req_probe req;
+    int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req));
+
+    return ret ? ret : virtio_iommu_probe(s, &req, buf);
+}
+
 static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
 {
     VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
     struct virtio_iommu_req_head head;
     struct virtio_iommu_req_tail tail = {};
+    size_t output_size = sizeof(tail), sz;
     VirtQueueElement *elem;
     unsigned int iov_cnt;
     struct iovec *iov;
-    size_t sz;
+    void *buf = NULL;
 
     for (;;) {
         elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
         case VIRTIO_IOMMU_T_UNMAP:
             tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
             break;
+        case VIRTIO_IOMMU_T_PROBE:
+        {
+            struct virtio_iommu_req_tail *ptail;
+
+            output_size = s->config.probe_size + sizeof(tail);
+            buf = g_malloc0(output_size);
+
+            ptail = (struct virtio_iommu_req_tail *)
+                        (buf + s->config.probe_size);
+            ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf);
+        }
         default:
             tail.status = VIRTIO_IOMMU_S_UNSUPP;
         }
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
 
 out:
         sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
-                          &tail, sizeof(tail));
-        assert(sz == sizeof(tail));
+                          buf ? buf : &tail, output_size);
+        assert(sz == output_size);
 
-        virtqueue_push(vq, elem, sizeof(tail));
+        virtqueue_push(vq, elem, sz);
         virtio_notify(vdev, vq);
         g_free(elem);
+        g_free(buf);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
     s->config.page_size_mask = TARGET_PAGE_MASK;
     s->config.input_range.end = -1UL;
     s->config.domain_range.end = 32;
+    s->config.probe_size = VIOMMU_PROBE_SIZE;
 
     virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX);
     virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC);
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
     virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP);
     virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS);
     virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO);
+    virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE);
 
     qemu_mutex_init(&s->mutex);
 
diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/trace-events
+++ b/hw/virtio/trace-events
@@ -XXX,XX +XXX,XX @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d"
 virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d"
 virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d"
 virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64
+virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

When translating an address we need to check if it belongs to
a reserved virtual address range. If it does, there are 2 cases:

- it belongs to a RESERVED region: the guest should neither use
  this address in a MAP not instruct the end-point to DMA on
  them. We report an error

- It belongs to an MSI region: we bypass the translation.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20200629070404.10969-4-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/virtio/virtio-iommu.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/virtio-iommu.c
+++ b/hw/virtio/virtio-iommu.c
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
     uint32_t sid, flags;
     bool bypass_allowed;
     bool found;
+    int i;
 
     interval.low = addr;
     interval.high = addr + 1;
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
         goto unlock;
     }
 
+    for (i = 0; i < s->nb_reserved_regions; i++) {
+        ReservedRegion *reg = &s->reserved_regions[i];
+
+        if (addr >= reg->low && addr <= reg->high) {
+            switch (reg->type) {
+            case VIRTIO_IOMMU_RESV_MEM_T_MSI:
+                entry.perm = flag;
+                break;
+            case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:
+            default:
+                virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING,
+                                          VIRTIO_IOMMU_FAULT_F_ADDRESS,
+                                          sid, addr);
+                break;
+            }
+            goto unlock;
+        }
+    }
+
     if (!ep->domain) {
         if (!bypass_allowed) {
             error_report_once("%s %02x:%02x.%01x not attached to any domain",
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

The machine may need to pass reserved regions to the
virtio-iommu-pci device (such as the MSI window on x86
or the MSI doorbells on ARM).

So let's add an array of Interval properties.

Note: if some reserved regions are already set by the
machine code - which should be the case in general -,
the length of the property array is already set and
prevents the end-user from modifying them. For example,
attempting to use:

-device virtio-iommu-pci,\
 len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1

would result in the following error message:

qemu-system-aarch64: -device virtio-iommu-pci,addr=0xa,
len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1:
array size property len-reserved-regions may not be set more than once

Otherwise, for example, adding two reserved regions is achieved
using the following options:

-device virtio-iommu-pci,addr=0xa,len-reserved-regions=2,\
 reserved-regions[0]=0xfee00000:0xfeefffff:1,\
 reserved-regions[1]=0x1000000:100ffff:1

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-id: 20200629070404.10969-5-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/virtio/virtio-iommu-pci.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/virtio-iommu-pci.c
+++ b/hw/virtio/virtio-iommu-pci.c
@@ -XXX,XX +XXX,XX @@ struct VirtIOIOMMUPCI {
 
 static Property virtio_iommu_pci_properties[] = {
     DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
+    DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI,
+                      vdev.nb_reserved_regions, vdev.reserved_regions,
+                      qdev_prop_reserved_region, ReservedRegion),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
 {
     VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev);
     DeviceState *vdev = DEVICE(&dev->vdev);
+    VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
 
     if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
         MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
                           "-no-acpi\n");
         return;
     }
+    for (int i = 0; i < s->nb_reserved_regions; i++) {
+        if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED &&
+            s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) {
+            error_setg(errp, "reserved region %d has an invalid type", i);
+            error_append_hint(errp, "Valid values are 0 and 1\n");
+        }
+    }
     object_property_set_link(OBJECT(dev),
                              OBJECT(pci_get_bus(&vpci_dev->pci_dev)),
                              "primary-bus", &error_abort);
-- 
2.20.1

From: Eric Auger <eric.auger@redhat.com>

At the moment the virtio-iommu translates MSI transactions.
This behavior is inherited from ARM SMMU. The virt machine
code knows where the guest MSI doorbells are so we can easily
declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
setting the guest will not map MSIs through the IOMMU and those
transactions will be simply bypassed.

Depending on which MSI controller is in use (ITS or GICV2M),
we declare either:
- the ITS interrupt translation space (ITS_base + 0x10000),
  containing the GITS_TRANSLATOR or
- The GICV2M single frame, containing the MSI_SETSP_NS register.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20200629070404.10969-6-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h |  7 +++++++
 hw/arm/virt.c         | 30 ++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
     VIRT_IOMMU_VIRTIO,
 } VirtIOMMUType;
 
+typedef enum VirtMSIControllerType {
+    VIRT_MSI_CTRL_NONE,
+    VIRT_MSI_CTRL_GICV2M,
+    VIRT_MSI_CTRL_ITS,
+} VirtMSIControllerType;
+
 typedef enum VirtGICType {
     VIRT_GIC_VERSION_MAX,
     VIRT_GIC_VERSION_HOST,
@@ -XXX,XX +XXX,XX @@ typedef struct {
     OnOffAuto acpi;
     VirtGICType gic_version;
     VirtIOMMUType iommu;
+    VirtMSIControllerType msi_controller;
     uint16_t virtio_iommu_bdf;
     struct arm_boot_info bootinfo;
     MemMapEntry *memmap;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_its(VirtMachineState *vms)
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
 
     fdt_add_its_gic_node(vms);
+    vms->msi_controller = VIRT_MSI_CTRL_ITS;
 }
 
 static void create_v2m(VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms)
     }
 
     fdt_add_v2m_gic_node(vms);
+    vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
 }
 
 static void create_gic(VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ out:
 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
                                             DeviceState *dev, Error **errp)
 {
+    VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
+
     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
         virt_memory_pre_plug(hotplug_dev, dev, errp);
+    } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
+        hwaddr db_start = 0, db_end = 0;
+        char *resv_prop_str;
+
+        switch (vms->msi_controller) {
+        case VIRT_MSI_CTRL_NONE:
+            return;
+        case VIRT_MSI_CTRL_ITS:
+            /* GITS_TRANSLATER page */
+            db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
+            db_end = base_memmap[VIRT_GIC_ITS].base +
+                     base_memmap[VIRT_GIC_ITS].size - 1;
+            break;
+        case VIRT_MSI_CTRL_GICV2M:
+            /* MSI_SETSPI_NS page */
+            db_start = base_memmap[VIRT_GIC_V2M].base;
+            db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
+            break;
+        }
+        resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
+                                        db_start, db_end,
+                                        VIRTIO_IOMMU_RESV_MEM_T_MSI);
+
+        qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
+        qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
+        g_free(resv_prop_str);
     }
 }
 
-- 
2.20.1

From: Beata Michalska <beata.michalska@linaro.org>

On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
exception with no valid ISS info to be decoded. The lack of decode info
makes it at least tricky to emulate those instruction which is one of the
(many) reasons why KVM will not even try to do so.

Add support for handling those by requesting KVM to inject external
dabt into the quest.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200629114110.30723-2-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
 
 static bool cap_has_mp_state;
 static bool cap_has_inject_serror_esr;
+static bool cap_has_inject_ext_dabt;
 
 static ARMHostCPUFeatures arm_host_cpu_features;
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
         ret = -EINVAL;
     }
 
+    if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
+        if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) {
+            error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap");
+        } else {
+            /* Set status for supporting the external dabt injection */
+            cap_has_inject_ext_dabt = kvm_check_extension(s,
+                                    KVM_CAP_ARM_INJECT_EXT_DABT);
+        }
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
     }
 }
 
+/**
+ * kvm_arm_handle_dabt_nisv:
+ * @cs: CPUState
+ * @esr_iss: ISS encoding (limited) for the exception from Data Abort
+ *           ISV bit set to '0b0' -> no valid instruction syndrome
+ * @fault_ipa: faulting address for the synchronous data abort
+ *
+ * Returns: 0 if the exception has been handled, < 0 otherwise
+ */
+static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
+                                    uint64_t fault_ipa)
+{
+    /*
+     * Request KVM to inject the external data abort into the guest
+     */
+    if (cap_has_inject_ext_dabt) {
+        struct kvm_vcpu_events events = { };
+        /*
+         * The external data abort event will be handled immediately by KVM
+         * using the address fault that triggered the exit on given VCPU.
+         * Requesting injection of the external data abort does not rely
+         * on any other VCPU state. Therefore, in this particular case, the VCPU
+         * synchronization can be exceptionally skipped.
+         */
+        events.exception.ext_dabt_pending = 1;
+        /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
+        return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
+    } else {
+        error_report("Data abort exception triggered by guest memory access "
+                     "at physical address: 0x"  TARGET_FMT_lx,
+                     (target_ulong)fault_ipa);
+        error_printf("KVM unable to emulate faulting instruction.\n");
+    }
+    return -1;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
             ret = EXCP_DEBUG;
         } /* otherwise return to guest */
         break;
+    case KVM_EXIT_ARM_NISV:
+        /* External DABT with no valid iss to decode */
+        ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss,
+                                       run->arm_nisv.fault_ipa);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.20.1

From: Beata Michalska <beata.michalska@linaro.org>

Injecting external data abort through KVM might trigger
an issue on kernels that do not get updated to include the KVM fix.
For those and aarch32 guests, the injected abort gets misconfigured
to be an implementation defined exception. This leads to the guest
repeatedly re-running the faulting instruction.

Add support for handling that case.

[
  Fixed-by: 018f22f95e8a
	('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
  Fixed-by: 21aecdbd7f3a
	('KVM: arm: Make inject_abt32() inject an external abort instead')
]

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Acked-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200629114110.30723-3-beata.michalska@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |  2 ++
 target/arm/kvm_arm.h | 10 +++++++++
 target/arm/kvm.c     | 30 ++++++++++++++++++++++++++-
 target/arm/kvm32.c   | 34 ++++++++++++++++++++++++++++++
 target/arm/kvm64.c   | 49 ++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 124 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
         uint64_t esr;
     } serror;
 
+    uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
+
     /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
     uint32_t irq_line_state;
 
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_hw_debug_active(CPUState *cs);
 struct kvm_guest_debug_arch;
 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
 
+/**
+ * kvm_arm_verify_ext_dabt_pending:
+ * @cs: CPUState
+ *
+ * Verify the fault status code wrt the Ext DABT injection
+ *
+ * Returns: true if the fault status code is as expected, false otherwise
+ */
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
+
 /**
  * its_class_name:
  *
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu)
 
 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
 {
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+
+    if (unlikely(env->ext_dabt_raised)) {
+        /*
+         * Verifying that the ext DABT has been properly injected,
+         * otherwise risking indefinitely re-running the faulting instruction
+         * Covering a very narrow case for kernels 5.5..5.5.4
+         * when injected abort was misconfigured to be
+         * an IMPLEMENTATION DEFINED exception (for 32-bit EL1)
+         */
+        if (!arm_feature(env, ARM_FEATURE_AARCH64) &&
+            unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) {
+
+            error_report("Data abort exception with no valid ISS generated by "
+                   "guest memory access. KVM unable to emulate faulting "
+                   "instruction. Failed to inject an external data abort "
+                   "into the guest.");
+            abort();
+       }
+       /* Clear the status */
+       env->ext_dabt_raised = 0;
+    }
 }
 
 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
 static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
                                     uint64_t fault_ipa)
 {
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
     /*
      * Request KVM to inject the external data abort into the guest
      */
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
          */
         events.exception.ext_dabt_pending = 1;
         /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
-        return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
+        if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) {
+            env->ext_dabt_raised = 1;
+            return 0;
+        }
     } else {
         error_report("Data abort exception triggered by guest memory access "
                      "at physical address: 0x"  TARGET_FMT_lx,
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
 {
     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 }
+
+#define ARM_REG_DFSR  ARM_CP15_REG32(0, 5, 0, 0)
+#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
+/*
+ *DFSR:
+ *      TTBCR.EAE == 0
+ *          FS[4]   - DFSR[10]
+ *          FS[3:0] - DFSR[3:0]
+ *      TTBCR.EAE == 1
+ *          FS, bits [5:0]
+ */
+#define DFSR_FSC(lpae, v) \
+    ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
+
+#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
+
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
+{
+    uint32_t dfsr_val;
+
+    if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
+        ARMCPU *cpu = ARM_CPU(cs);
+        CPUARMState *env = &cpu->env;
+        uint32_t ttbcr;
+        int lpae = 0;
+
+        if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
+            lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
+        }
+        /* The verification is based on FS filed of the DFSR reg only*/
+        return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
+    }
+    return false;
+}
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 
     return false;
 }
+
+#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
+#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
+
+/*
+ * ESR_EL1
+ * ISS encoding
+ * AARCH64: DFSC,   bits [5:0]
+ * AARCH32:
+ *      TTBCR.EAE == 0
+ *          FS[4]   - DFSR[10]
+ *          FS[3:0] - DFSR[3:0]
+ *      TTBCR.EAE == 1
+ *          FS, bits [5:0]
+ */
+#define ESR_DFSC(aarch64, lpae, v)        \
+    ((aarch64 || (lpae)) ? ((v) & 0x3F)   \
+               : (((v) >> 6) | ((v) & 0x1F)))
+
+#define ESR_DFSC_EXTABT(aarch64, lpae) \
+    ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
+
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
+{
+    uint64_t dfsr_val;
+
+    if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
+        ARMCPU *cpu = ARM_CPU(cs);
+        CPUARMState *env = &cpu->env;
+        int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
+        int lpae = 0;
+
+        if (!aarch64_mode) {
+            uint64_t ttbcr;
+
+            if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
+                lpae = arm_feature(env, ARM_FEATURE_LPAE)
+                        && (ttbcr & TTBCR_EAE);
+            }
+        }
+        /*
+         * The verification here is based on the DFSC bits
+         * of the ESR_EL1 reg only
+         */
+         return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
+                ESR_DFSC_EXTABT(aarch64_mode, lpae));
+    }
+    return false;
+}
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Fixes: 93dd625f8bf7 ("tests/acpi: update expected data files")
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20200629140938.17566-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/bios-tables-test-allowed-diff.h | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,19 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/pc/DSDT",
-"tests/data/acpi/pc/DSDT.acpihmat",
-"tests/data/acpi/pc/DSDT.bridge",
-"tests/data/acpi/pc/DSDT.cphp",
-"tests/data/acpi/pc/DSDT.dimmpxm",
-"tests/data/acpi/pc/DSDT.ipmikcs",
-"tests/data/acpi/pc/DSDT.memhp",
-"tests/data/acpi/pc/DSDT.numamem",
-"tests/data/acpi/q35/DSDT",
-"tests/data/acpi/q35/DSDT.acpihmat",
-"tests/data/acpi/q35/DSDT.bridge",
-"tests/data/acpi/q35/DSDT.cphp",
-"tests/data/acpi/q35/DSDT.dimmpxm",
-"tests/data/acpi/q35/DSDT.ipmibt",
-"tests/data/acpi/q35/DSDT.memhp",
-"tests/data/acpi/q35/DSDT.mmio64",
-"tests/data/acpi/q35/DSDT.numamem",
-"tests/data/acpi/q35/DSDT.tis",
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

The flash device is exclusively for the host-controlled firmware, so
we should not expose it to the OS. Exposing it risks the OS messing
with it, which could break firmware runtime services and surprise the
OS when all its changes disappear after reboot.

As firmware needs the device and uses DT, we leave the device exposed
there. It's up to firmware to remove the nodes from DT before sending
it on to the OS. However, there's no need to force firmware to remove
tables from ACPI (which it doesn't know how to do anyway), so we
simply don't add the tables in the first place. But, as we've been
adding the tables for quite some time and don't want to change the
default hardware exposed to versioned machines, then we only stop
exposing the flash device tables for 5.1 and later machine types.

Suggested-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-id: 20200629140938.17566-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h    | 1 +
 hw/arm/virt-acpi-build.c | 5 ++++-
 hw/arm/virt.c            | 3 +++
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
     bool no_highmem_ecam;
     bool no_ged;   /* Machines < 4.2 has no support for ACPI GED device */
     bool kvm_no_adjvtime;
+    bool acpi_expose_flash;
 } VirtMachineClass;
 
 typedef struct {
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
 static void
 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 {
+    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
     Aml *scope, *dsdt;
     MachineState *ms = MACHINE(vms);
     const MemMapEntry *memmap = vms->memmap;
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     acpi_dsdt_add_cpus(scope, vms->smp_cpus);
     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
-    acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
+    if (vmc->acpi_expose_flash) {
+        acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
+    }
     acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
 
 static void virt_machine_5_0_options(MachineClass *mc)
 {
+    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
     virt_machine_5_1_options(mc);
     compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
     mc->numa_mem_supported = true;
+    vmc->acpi_expose_flash = true;
 }
 DEFINE_VIRT_MACHINE(5, 0)
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Differences between disassembled ASL files for DSDT:

@@ -XXX,XX +XXX,XX @@
  *
  * Disassembling to symbolic ASL+ operators
  *
- * Disassembly of a, Mon Jun 29 09:50:01 2020
+ * Disassembly of b, Mon Jun 29 09:50:03 2020
  *
  * Original Table Header:
  *     Signature        "DSDT"
- *     Length           0x000014BB (5307)
+ *     Length           0x00001455 (5205)
  *     Revision         0x02
- *     Checksum         0xD1
+ *     Checksum         0xE1
  *     OEM ID           "BOCHS "
  *     OEM Table ID     "BXPCDSDT"
  *     OEM Revision     0x00000001 (1)
@@ -XXX,XX +XXX,XX @@
             })
         }

-        Device (FLS0)
-        {
-            Name (_HID, "LNRO0015")  // _HID: Hardware ID
-            Name (_UID, Zero)  // _UID: Unique ID
-            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-            {
-                Memory32Fixed (ReadWrite,
-                    0x00000000,         // Address Base
-                    0x04000000,         // Address Length
-                    )
-            })
-        }
-
-        Device (FLS1)
-        {
-            Name (_HID, "LNRO0015")  // _HID: Hardware ID
-            Name (_UID, One)  // _UID: Unique ID
-            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-            {
-                Memory32Fixed (ReadWrite,
-                    0x04000000,         // Address Base
-                    0x04000000,         // Address Length
-                    )
-            })
-        }
-
         Device (FWCF)
         {
             Name (_HID, "QEMU0002")  // _HID: Hardware ID

The other two binaries have the same changes (the removal of the
flash devices).

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-id: 20200629140938.17566-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/bios-tables-test-allowed-diff.h |   3 ---
 tests/data/acpi/virt/DSDT                   | Bin 5307 -> 5205 bytes
 tests/data/acpi/virt/DSDT.memhp             | Bin 6668 -> 6566 bytes
 tests/data/acpi/virt/DSDT.numamem           | Bin 5307 -> 5205 bytes
 4 files changed, 3 deletions(-)

delta 156
zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
LaERl^1zUvy_;n(J

diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
index XXXXXXX..XXXXXXX 100644
GIT binary patch
delta 28
kcmeA%S!T@T66_MPOp<|tiD@F2G*jb@iRuX(-^xn@0CHUjRR910

delta 156
zcmZ2x++)J!66_MfBgMeL^l>7WG*kP$iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^
zE<n;bC|FRCi?5B7fsp|MSSlH!n?PC&v1wsM*TMqS1=eEW7Vhi@(GuwD8){%+U<5Qj
LIK*+|0yaqism~!^

diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem
index XXXXXXX..XXXXXXX 100644
GIT binary patch
delta 28
kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a

delta 156
zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
LaERl^1zUvy_;n(J

-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The temp that gets assigned to clean_addr has been allocated with
new_tmp_a64, which means that it will be freed at the end of the
instruction.  Freeing it earlier leads to assertion failure.

The loop creates a complication, in which we allocate a new local
temp, which does need freeing, and the final code path is shared
between the loop and non-loop.

Fix this complication by adding new_tmp_a64_local so that the new
local temp is freed at the end, and can be treated exactly like
the non-loop path.

Fixes: bba87d0a0f4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200702175605.1987125-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.h | 1 +
 target/arm/translate-a64.c | 6 ++++++
 target/arm/translate-sve.c | 8 ++------
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
     } while (0)
 
 TCGv_i64 new_tmp_a64(DisasContext *s);
+TCGv_i64 new_tmp_a64_local(DisasContext *s);
 TCGv_i64 new_tmp_a64_zero(DisasContext *s);
 TCGv_i64 cpu_reg(DisasContext *s, int reg);
 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ TCGv_i64 new_tmp_a64(DisasContext *s)
     return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
 }
 
+TCGv_i64 new_tmp_a64_local(DisasContext *s)
+{
+    assert(s->tmp_a64_count < TMP_A64_MAX);
+    return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64();
+}
+
 TCGv_i64 new_tmp_a64_zero(DisasContext *s)
 {
     TCGv_i64 t = new_tmp_a64(s);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
 
         /* Copy the clean address into a local temp, live across the loop. */
         t0 = clean_addr;
-        clean_addr = tcg_temp_local_new_i64();
+        clean_addr = new_tmp_a64_local(s);
         tcg_gen_mov_i64(clean_addr, t0);
-        tcg_temp_free_i64(t0);
 
         gen_set_label(loop);
 
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
         tcg_temp_free_i64(t0);
     }
-    tcg_temp_free_i64(clean_addr);
 }
 
 /* Similarly for stores.  */
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
 
         /* Copy the clean address into a local temp, live across the loop. */
         t0 = clean_addr;
-        clean_addr = tcg_temp_local_new_i64();
+        clean_addr = new_tmp_a64_local(s);
         tcg_gen_mov_i64(clean_addr, t0);
-        tcg_temp_free_i64(t0);
 
         gen_set_label(loop);
 
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         }
         tcg_temp_free_i64(t0);
     }
-    tcg_temp_free_i64(clean_addr);
 }
 
 static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
-- 
2.20.1

In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we
pass a pointer to a local struct to another function without
initializing all its fields.  This is a real bug:
bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig
struct into s->config, so any fields we don't initialize will corrupt
the state of the device.

Copy the two fields which we don't want to update (pixo and alpha)
from the existing config so we don't accidentally change them.

Fixes: cfb7ba983857e40e88
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200628195436.27582-1-peter.maydell@linaro.org
---
 hw/display/bcm2835_fb.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/bcm2835_fb.c
+++ b/hw/display/bcm2835_fb.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
     newconf.base = s->vcram_base | (value & 0xc0000000);
     newconf.base += BCM2835_FB_OFFSET;
 
+    /* Copy fields which we don't want to change from the existing config */
+    newconf.pixo = s->config.pixo;
+    newconf.alpha = s->config.alpha;
+
     bcm2835_fb_validate_config(&newconf);
 
     pitch = bcm2835_fb_get_pitch(&newconf);
-- 
2.20.1

The spitz board has been around a long time, and still has a fair number
of hard-coded tab characters in it. We're about to do some work on
this source file, so start out by expanding out the tabs.

This commit is a pure whitespace only change.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-2-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 156 ++++++++++++++++++++++++-------------------------
 1 file changed, 78 insertions(+), 78 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 
 #undef REG_FMT
-#define REG_FMT			"0x%02lx"
+#define REG_FMT                         "0x%02lx"
 
 /* Spitz Flash */
-#define FLASH_BASE		0x0c000000
-#define FLASH_ECCLPLB		0x00	/* Line parity 7 - 0 bit */
-#define FLASH_ECCLPUB		0x04	/* Line parity 15 - 8 bit */
-#define FLASH_ECCCP		0x08	/* Column parity 5 - 0 bit */
-#define FLASH_ECCCNTR		0x0c	/* ECC byte counter */
-#define FLASH_ECCCLRR		0x10	/* Clear ECC */
-#define FLASH_FLASHIO		0x14	/* Flash I/O */
-#define FLASH_FLASHCTL		0x18	/* Flash Control */
+#define FLASH_BASE              0x0c000000
+#define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
+#define FLASH_ECCLPUB           0x04    /* Line parity 15 - 8 bit */
+#define FLASH_ECCCP             0x08    /* Column parity 5 - 0 bit */
+#define FLASH_ECCCNTR           0x0c    /* ECC byte counter */
+#define FLASH_ECCCLRR           0x10    /* Clear ECC */
+#define FLASH_FLASHIO           0x14    /* Flash I/O */
+#define FLASH_FLASHCTL          0x18    /* Flash Control */
 
-#define FLASHCTL_CE0		(1 << 0)
-#define FLASHCTL_CLE		(1 << 1)
-#define FLASHCTL_ALE		(1 << 2)
-#define FLASHCTL_WP		(1 << 3)
-#define FLASHCTL_CE1		(1 << 4)
-#define FLASHCTL_RYBY		(1 << 5)
-#define FLASHCTL_NCE		(FLASHCTL_CE0 | FLASHCTL_CE1)
+#define FLASHCTL_CE0            (1 << 0)
+#define FLASHCTL_CLE            (1 << 1)
+#define FLASHCTL_ALE            (1 << 2)
+#define FLASHCTL_WP             (1 << 3)
+#define FLASHCTL_CE1            (1 << 4)
+#define FLASHCTL_RYBY           (1 << 5)
+#define FLASHCTL_NCE            (FLASHCTL_CE0 | FLASHCTL_CE1)
 
 #define TYPE_SL_NAND "sl-nand"
 #define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
     int ryby;
 
     switch (addr) {
-#define BSHR(byte, from, to)	((s->ecc.lp[byte] >> (from - to)) & (1 << to))
+#define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
     case FLASH_ECCLPLB:
         return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
                 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
 
-#define BSHL(byte, from, to)	((s->ecc.lp[byte] << (to - from)) & (1 << to))
+#define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
     case FLASH_ECCLPUB:
         return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
                 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
@@ -XXX,XX +XXX,XX @@ static void sl_nand_realize(DeviceState *dev, Error **errp)
 
 /* Spitz Keyboard */
 
-#define SPITZ_KEY_STROBE_NUM	11
-#define SPITZ_KEY_SENSE_NUM	7
+#define SPITZ_KEY_STROBE_NUM    11
+#define SPITZ_KEY_SENSE_NUM     7
 
 static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
     12, 17, 91, 34, 36, 38, 39
@@ -XXX,XX +XXX,XX @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
     { 0x52, 0x43, 0x01, 0x47, 0x49,  -1 ,  -1 ,  -1 ,  -1 ,  -1 ,  -1  },
 };
 
-#define SPITZ_GPIO_AK_INT	13	/* Remote control */
-#define SPITZ_GPIO_SYNC		16	/* Sync button */
-#define SPITZ_GPIO_ON_KEY	95	/* Power button */
-#define SPITZ_GPIO_SWA		97	/* Lid */
-#define SPITZ_GPIO_SWB		96	/* Tablet mode */
+#define SPITZ_GPIO_AK_INT       13      /* Remote control */
+#define SPITZ_GPIO_SYNC                 16      /* Sync button */
+#define SPITZ_GPIO_ON_KEY       95      /* Power button */
+#define SPITZ_GPIO_SWA          97      /* Lid */
+#define SPITZ_GPIO_SWB          96      /* Tablet mode */
 
 /* The special buttons are mapped to unused keys */
 static const int spitz_gpiomap[5] = {
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
 #define SPITZ_MOD_CTRL    (1 << 8)
 #define SPITZ_MOD_FN      (1 << 9)
 
-#define QUEUE_KEY(c)	s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
+#define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
 
 static void spitz_keyboard_handler(void *opaque, int keycode)
 {
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_handler(void *opaque, int keycode)
     uint16_t code;
     int mapcode;
     switch (keycode) {
-    case 0x2a:	/* Left Shift */
+    case 0x2a:  /* Left Shift */
         s->modifiers |= 1;
         break;
     case 0xaa:
         s->modifiers &= ~1;
         break;
-    case 0x36:	/* Right Shift */
+    case 0x36:  /* Right Shift */
         s->modifiers |= 2;
         break;
     case 0xb6:
         s->modifiers &= ~2;
         break;
-    case 0x1d:	/* Control */
+    case 0x1d:  /* Control */
         s->modifiers |= 4;
         break;
     case 0x9d:
         s->modifiers &= ~4;
         break;
-    case 0x38:	/* Alt */
+    case 0x38:  /* Alt */
         s->modifiers |= 8;
         break;
     case 0xb8:
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
 
 /* LCD backlight controller */
 
-#define LCDTG_RESCTL	0x00
-#define LCDTG_PHACTRL	0x01
-#define LCDTG_DUTYCTRL	0x02
-#define LCDTG_POWERREG0	0x03
-#define LCDTG_POWERREG1	0x04
-#define LCDTG_GPOR3	0x05
-#define LCDTG_PICTRL	0x06
-#define LCDTG_POLCTRL	0x07
+#define LCDTG_RESCTL    0x00
+#define LCDTG_PHACTRL   0x01
+#define LCDTG_DUTYCTRL  0x02
+#define LCDTG_POWERREG0         0x03
+#define LCDTG_POWERREG1         0x04
+#define LCDTG_GPOR3     0x05
+#define LCDTG_PICTRL    0x06
+#define LCDTG_POLCTRL   0x07
 
 typedef struct {
     SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
 
 /* SSP devices */
 
-#define CORGI_SSP_PORT		2
+#define CORGI_SSP_PORT          2
 
-#define SPITZ_GPIO_LCDCON_CS	53
-#define SPITZ_GPIO_ADS7846_CS	14
-#define SPITZ_GPIO_MAX1111_CS	20
-#define SPITZ_GPIO_TP_INT	11
+#define SPITZ_GPIO_LCDCON_CS    53
+#define SPITZ_GPIO_ADS7846_CS   14
+#define SPITZ_GPIO_MAX1111_CS   20
+#define SPITZ_GPIO_TP_INT       11
 
 static DeviceState *max1111;
 
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
     s->enable[line] = !level;
 }
 
-#define MAX1111_BATT_VOLT	1
-#define MAX1111_BATT_TEMP	2
-#define MAX1111_ACIN_VOLT	3
+#define MAX1111_BATT_VOLT       1
+#define MAX1111_BATT_TEMP       2
+#define MAX1111_ACIN_VOLT       3
 
-#define SPITZ_BATTERY_TEMP	0xe0	/* About 2.9V */
-#define SPITZ_BATTERY_VOLT	0xd0	/* About 4.0V */
-#define SPITZ_CHARGEON_ACIN	0x80	/* About 5.0V */
+#define SPITZ_BATTERY_TEMP      0xe0    /* About 2.9V */
+#define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
+#define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
 
 static void spitz_adc_temp_on(void *opaque, int line, int level)
 {
@@ -XXX,XX +XXX,XX @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
 
 /* Wm8750 and Max7310 on I2C */
 
-#define AKITA_MAX_ADDR	0x18
-#define SPITZ_WM_ADDRL	0x1b
-#define SPITZ_WM_ADDRH	0x1a
+#define AKITA_MAX_ADDR  0x18
+#define SPITZ_WM_ADDRL  0x1b
+#define SPITZ_WM_ADDRH  0x1a
 
-#define SPITZ_GPIO_WM	5
+#define SPITZ_GPIO_WM   5
 
 static void spitz_wm8750_addr(void *opaque, int line, int level)
 {
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
     }
 }
 
-#define SPITZ_SCP_LED_GREEN		1
-#define SPITZ_SCP_JK_B			2
-#define SPITZ_SCP_CHRG_ON		3
-#define SPITZ_SCP_MUTE_L		4
-#define SPITZ_SCP_MUTE_R		5
-#define SPITZ_SCP_CF_POWER		6
-#define SPITZ_SCP_LED_ORANGE		7
-#define SPITZ_SCP_JK_A			8
-#define SPITZ_SCP_ADC_TEMP_ON		9
-#define SPITZ_SCP2_IR_ON		1
-#define SPITZ_SCP2_AKIN_PULLUP		2
-#define SPITZ_SCP2_BACKLIGHT_CONT	7
-#define SPITZ_SCP2_BACKLIGHT_ON		8
-#define SPITZ_SCP2_MIC_BIAS		9
+#define SPITZ_SCP_LED_GREEN             1
+#define SPITZ_SCP_JK_B                  2
+#define SPITZ_SCP_CHRG_ON               3
+#define SPITZ_SCP_MUTE_L                4
+#define SPITZ_SCP_MUTE_R                5
+#define SPITZ_SCP_CF_POWER              6
+#define SPITZ_SCP_LED_ORANGE            7
+#define SPITZ_SCP_JK_A                  8
+#define SPITZ_SCP_ADC_TEMP_ON           9
+#define SPITZ_SCP2_IR_ON                1
+#define SPITZ_SCP2_AKIN_PULLUP          2
+#define SPITZ_SCP2_BACKLIGHT_CONT       7
+#define SPITZ_SCP2_BACKLIGHT_ON                 8
+#define SPITZ_SCP2_MIC_BIAS             9
 
 static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
                 DeviceState *scp0, DeviceState *scp1)
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
     qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 }
 
-#define SPITZ_GPIO_HSYNC		22
-#define SPITZ_GPIO_SD_DETECT		9
-#define SPITZ_GPIO_SD_WP		81
-#define SPITZ_GPIO_ON_RESET		89
-#define SPITZ_GPIO_BAT_COVER		90
-#define SPITZ_GPIO_CF1_IRQ		105
-#define SPITZ_GPIO_CF1_CD		94
-#define SPITZ_GPIO_CF2_IRQ		106
-#define SPITZ_GPIO_CF2_CD		93
+#define SPITZ_GPIO_HSYNC                22
+#define SPITZ_GPIO_SD_DETECT            9
+#define SPITZ_GPIO_SD_WP                81
+#define SPITZ_GPIO_ON_RESET             89
+#define SPITZ_GPIO_BAT_COVER            90
+#define SPITZ_GPIO_CF1_IRQ              105
+#define SPITZ_GPIO_CF1_CD               94
+#define SPITZ_GPIO_CF2_IRQ              106
+#define SPITZ_GPIO_CF2_CD               93
 
 static int spitz_hsync;
 
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
 /* Board init.  */
 enum spitz_model_e { spitz, akita, borzoi, terrier };
 
-#define SPITZ_RAM	0x04000000
-#define SPITZ_ROM	0x00800000
+#define SPITZ_RAM       0x04000000
+#define SPITZ_ROM       0x00800000
 
 static struct arm_boot_info spitz_binfo = {
     .loader_start = PXA2XX_SDRAM_BASE,
-- 
2.20.1

For the four Spitz-family machines (akita, borzoi, spitz, terrier)
create a proper abstract class SpitzMachineClass which encapsulates
the common behaviour, rather than having them all derive directly
from TYPE_MACHINE:
 * instead of each machine class setting mc->init to a wrapper
   function which calls spitz_common_init() with parameters,
   put that data in the SpitzMachineClass and make spitz_common_init
   the SpitzMachineClass machine-init function
 * move the settings of mc->block_default_type and
   mc->ignore_memory_transaction_failures into the SpitzMachineClass
   class init rather than repeating them in each machine's class init

(The motivation is that we're going to want to keep some state in
the SpitzMachineState so we can connect GPIOs between devices created
in one sub-function of the machine init to devices created in a
different sub-function.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200628142429.17111-3-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++--------------------
 1 file changed, 55 insertions(+), 36 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "cpu.h"
 
+enum spitz_model_e { spitz, akita, borzoi, terrier };
+
+typedef struct {
+    MachineClass parent;
+    enum spitz_model_e model;
+    int arm_id;
+} SpitzMachineClass;
+
+typedef struct {
+    MachineState parent;
+} SpitzMachineState;
+
+#define TYPE_SPITZ_MACHINE "spitz-common"
+#define SPITZ_MACHINE(obj) \
+    OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE)
+#define SPITZ_MACHINE_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE)
+#define SPITZ_MACHINE_CLASS(klass) \
+    OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
+
 #undef REG_FMT
 #define REG_FMT                         "0x%02lx"
 
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
 }
 
 /* Board init.  */
-enum spitz_model_e { spitz, akita, borzoi, terrier };
-
 #define SPITZ_RAM       0x04000000
 #define SPITZ_ROM       0x00800000
 
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
     .ram_size = 0x04000000,
 };
 
-static void spitz_common_init(MachineState *machine,
-                              enum spitz_model_e model, int arm_id)
+static void spitz_common_init(MachineState *machine)
 {
+    SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
+    enum spitz_model_e model = smc->model;
     PXA2xxState *mpu;
     DeviceState *scp0, *scp1 = NULL;
     MemoryRegion *address_space_mem = get_system_memory();
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine,
         /* A 4.0 GB microdrive is permanently sitting in CF slot 0.  */
         spitz_microdrive_attach(mpu, 0);
 
-    spitz_binfo.board_id = arm_id;
+    spitz_binfo.board_id = smc->arm_id;
     arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
     sl_bootparam_write(SL_PXA_PARAM_BASE);
 }
 
-static void spitz_init(MachineState *machine)
+static void spitz_common_class_init(ObjectClass *oc, void *data)
 {
-    spitz_common_init(machine, spitz, 0x2c9);
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->block_default_type = IF_IDE;
+    mc->ignore_memory_transaction_failures = true;
+    mc->init = spitz_common_init;
 }
 
-static void borzoi_init(MachineState *machine)
-{
-    spitz_common_init(machine, borzoi, 0x33f);
-}
-
-static void akita_init(MachineState *machine)
-{
-    spitz_common_init(machine, akita, 0x2e8);
-}
-
-static void terrier_init(MachineState *machine)
-{
-    spitz_common_init(machine, terrier, 0x33f);
-}
+static const TypeInfo spitz_common_info = {
+    .name = TYPE_SPITZ_MACHINE,
+    .parent = TYPE_MACHINE,
+    .abstract = true,
+    .instance_size = sizeof(SpitzMachineState),
+    .class_size = sizeof(SpitzMachineClass),
+    .class_init = spitz_common_class_init,
+};
 
 static void akitapda_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
 
     mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
-    mc->init = akita_init;
-    mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
+    smc->model = akita;
+    smc->arm_id = 0x2e8;
 }
 
 static const TypeInfo akitapda_type = {
     .name = MACHINE_TYPE_NAME("akita"),
-    .parent = TYPE_MACHINE,
+    .parent = TYPE_SPITZ_MACHINE,
     .class_init = akitapda_class_init,
 };
 
 static void spitzpda_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
 
     mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
-    mc->init = spitz_init;
-    mc->block_default_type = IF_IDE;
-    mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
+    smc->model = spitz;
+    smc->arm_id = 0x2c9;
 }
 
 static const TypeInfo spitzpda_type = {
     .name = MACHINE_TYPE_NAME("spitz"),
-    .parent = TYPE_MACHINE,
+    .parent = TYPE_SPITZ_MACHINE,
     .class_init = spitzpda_class_init,
 };
 
 static void borzoipda_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
 
     mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
-    mc->init = borzoi_init;
-    mc->block_default_type = IF_IDE;
-    mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
+    smc->model = borzoi;
+    smc->arm_id = 0x33f;
 }
 
 static const TypeInfo borzoipda_type = {
     .name = MACHINE_TYPE_NAME("borzoi"),
-    .parent = TYPE_MACHINE,
+    .parent = TYPE_SPITZ_MACHINE,
     .class_init = borzoipda_class_init,
 };
 
 static void terrierpda_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
 
     mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
-    mc->init = terrier_init;
-    mc->block_default_type = IF_IDE;
-    mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
+    smc->model = terrier;
+    smc->arm_id = 0x33f;
 }
 
 static const TypeInfo terrierpda_type = {
     .name = MACHINE_TYPE_NAME("terrier"),
-    .parent = TYPE_MACHINE,
+    .parent = TYPE_SPITZ_MACHINE,
     .class_init = terrierpda_class_init,
 };
 
 static void spitz_machine_init(void)
 {
+    type_register_static(&spitz_common_info);
     type_register_static(&akitapda_type);
     type_register_static(&spitzpda_type);
     type_register_static(&borzoipda_type);
-- 
2.20.1

Keep pointers to the MPU and the SSI devices in SpitzMachineState.
We're going to want to make GPIO connections between some of the
SSI devices and the SCPs, so we want to keep hold of a pointer to
those; putting the MPU into the struct allows us to pass just
one thing to spitz_ssp_attach() rather than two.

We have to retain the setting of the global "max1111" variable
for the moment as it is used in spitz_adc_temp_on(); later in
this series of commits we will be able to remove it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-4-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++----------------------
 1 file changed, 28 insertions(+), 22 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 typedef struct {
     MachineState parent;
+    PXA2xxState *mpu;
+    DeviceState *mux;
+    DeviceState *lcdtg;
+    DeviceState *ads7846;
+    DeviceState *max1111;
 } SpitzMachineState;
 
 #define TYPE_SPITZ_MACHINE "spitz-common"
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_realize(SSISlave *d, Error **errp)
     s->bus[2] = ssi_create_bus(dev, "ssi2");
 }
 
-static void spitz_ssp_attach(PXA2xxState *cpu)
+static void spitz_ssp_attach(SpitzMachineState *sms)
 {
-    DeviceState *mux;
-    DeviceState *dev;
     void *bus;
 
-    mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
+    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
 
-    bus = qdev_get_child_bus(mux, "ssi0");
-    ssi_create_slave(bus, "spitz-lcdtg");
+    bus = qdev_get_child_bus(sms->mux, "ssi0");
+    sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
 
-    bus = qdev_get_child_bus(mux, "ssi1");
-    dev = ssi_create_slave(bus, "ads7846");
-    qdev_connect_gpio_out(dev, 0,
-                          qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
+    bus = qdev_get_child_bus(sms->mux, "ssi1");
+    sms->ads7846 = ssi_create_slave(bus, "ads7846");
+    qdev_connect_gpio_out(sms->ads7846, 0,
+                          qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
 
-    bus = qdev_get_child_bus(mux, "ssi2");
-    max1111 = ssi_create_slave(bus, "max1111");
-    max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
-    max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
-    max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
+    bus = qdev_get_child_bus(sms->mux, "ssi2");
+    sms->max1111 = ssi_create_slave(bus, "max1111");
+    max1111 = sms->max1111;
+    max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
+    max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
+    max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
 
-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
-                        qdev_get_gpio_in(mux, 0));
-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
-                        qdev_get_gpio_in(mux, 1));
-    qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
-                        qdev_get_gpio_in(mux, 2));
+    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
+                        qdev_get_gpio_in(sms->mux, 0));
+    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS,
+                        qdev_get_gpio_in(sms->mux, 1));
+    qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS,
+                        qdev_get_gpio_in(sms->mux, 2));
 }
 
 /* CF Microdrive */
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
 static void spitz_common_init(MachineState *machine)
 {
     SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
+    SpitzMachineState *sms = SPITZ_MACHINE(machine);
     enum spitz_model_e model = smc->model;
     PXA2xxState *mpu;
     DeviceState *scp0, *scp1 = NULL;
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
     /* Setup CPU & memory */
     mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
                       machine->cpu_type);
+    sms->mpu = mpu;
 
     sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
 
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
     /* Setup peripherals */
     spitz_keyboard_register(mpu);
 
-    spitz_ssp_attach(mpu);
+    spitz_ssp_attach(sms);
 
     scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
     if (model != akita) {
-- 
2.20.1

Keep pointers to scp0, scp1 in SpitzMachineState, and just pass
that to spitz_scoop_gpio_setup().

(We'll want to use some of the other fields in SpitzMachineState
in that function in the next commit.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-5-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 34 +++++++++++++++++++---------------
 1 file changed, 19 insertions(+), 15 deletions(-)

Currently the Spitz board uses a nasty hack for the GPIO lines
that pass "bit5" and "power" information to the LCD controller:
the lcdtg realize function sets a global variable to point to
the instance it just realized, and then the functions spitz_bl_power()
and spitz_bl_bit5() use that to find the device they are changing
the internal state of. There is a comment reading:
 FIXME: Implement GPIO properly and remove this hack.
which was added in 2009.

Implement GPIO properly and remove this hack.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-6-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void spitz_bl_update(SpitzLCDTG *s)
         zaurus_printf("LCD Backlight now off\n");
 }
 
-/* FIXME: Implement GPIO properly and remove this hack.  */
-static SpitzLCDTG *spitz_lcdtg;
-
 static inline void spitz_bl_bit5(void *opaque, int line, int level)
 {
-    SpitzLCDTG *s = spitz_lcdtg;
+    SpitzLCDTG *s = opaque;
     int prev = s->bl_intensity;
 
     if (level)
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_bit5(void *opaque, int line, int level)
 
 static inline void spitz_bl_power(void *opaque, int line, int level)
 {
-    SpitzLCDTG *s = spitz_lcdtg;
+    SpitzLCDTG *s = opaque;
     s->bl_power = !!level;
     spitz_bl_update(s);
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
     return 0;
 }
 
-static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
+static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
 {
-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
+    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
+    DeviceState *dev = DEVICE(s);
 
-    spitz_lcdtg = s;
     s->bl_power = 0;
     s->bl_intensity = 0x20;
+
+    qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1);
+    qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1);
 }
 
 /* SSP devices */
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
     case 3:
         zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
         break;
-    case 4:
-        spitz_bl_bit5(opaque, line, level);
-        break;
-    case 5:
-        spitz_bl_power(opaque, line, level);
-        break;
     case 6:
         spitz_adc_temp_on(opaque, line, level);
         break;
+    default:
+        g_assert_not_reached();
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
 
     if (sms->scp1) {
         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
-                              outsignals[4]);
+                              qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0));
         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
-                              outsignals[5]);
+                              qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
     }
 
     qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
-- 
2.20.1

Add some QOM properties to the max111x ADC device to allow the
initial values to be configured. Currently this is done by
board code calling max111x_set_input() after it creates the
device, which doesn't work on system reset.

This requires us to implement a reset method for this device,
so while we're doing that make sure we reset the other parts
of the device state.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-7-peter.maydell@linaro.org
---
 hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 47 insertions(+), 10 deletions(-)

diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/ssi/ssi.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
+#include "hw/qdev-properties.h"
 
 typedef struct {
     SSISlave parent_obj;
 
     qemu_irq interrupt;
+    /* Values of inputs at system reset (settable by QOM property) */
+    uint8_t reset_input[8];
+
     uint8_t tb1, rb2, rb3;
     int cycle;
 
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
     qdev_init_gpio_out(dev, &s->interrupt, 1);
 
     s->inputs = inputs;
-    /* TODO: add a user interface for setting these */
-    s->input[0] = 0xf0;
-    s->input[1] = 0xe0;
-    s->input[2] = 0xd0;
-    s->input[3] = 0xc0;
-    s->input[4] = 0xb0;
-    s->input[5] = 0xa0;
-    s->input[6] = 0x90;
-    s->input[7] = 0x80;
-    s->com = 0;
 
     vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
                      &vmstate_max111x, s);
@@ -XXX,XX +XXX,XX @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value)
     s->input[line] = value;
 }
 
+static void max111x_reset(DeviceState *dev)
+{
+    MAX111xState *s = MAX_111X(dev);
+    int i;
+
+    for (i = 0; i < s->inputs; i++) {
+        s->input[i] = s->reset_input[i];
+    }
+    s->com = 0;
+    s->tb1 = 0;
+    s->rb2 = 0;
+    s->rb3 = 0;
+    s->cycle = 0;
+}
+
+static Property max1110_properties[] = {
+    /* Reset values for ADC inputs */
+    DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
+    DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
+    DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
+    DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static Property max1111_properties[] = {
+    /* Reset values for ADC inputs */
+    DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
+    DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
+    DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
+    DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
+    DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0),
+    DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0),
+    DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90),
+    DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void max111x_class_init(ObjectClass *klass, void *data)
 {
     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
 
     k->transfer = max111x_transfer;
+    dc->reset = max111x_reset;
 }
 
 static const TypeInfo max111x_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max111x_info = {
 static void max1110_class_init(ObjectClass *klass, void *data)
 {
     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
 
     k->realize = max1110_realize;
+    device_class_set_props(dc, max1110_properties);
 }
 
 static const TypeInfo max1110_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max1110_info = {
 static void max1111_class_init(ObjectClass *klass, void *data)
 {
     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
 
     k->realize = max1111_realize;
+    device_class_set_props(dc, max1111_properties);
 }
 
 static const TypeInfo max1111_info = {
-- 
2.20.1

The max111x is a proper qdev device; we can use dc->vmsd rather than
directly calling vmstate_register().

It's possible that this is a migration compat break, but the only
boards that use this device are the spitz-family ('akita', 'borzoi',
'spitz', 'terrier').

diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
 
     s->inputs = inputs;
 
-    vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
-                     &vmstate_max111x, s);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static void max111x_class_init(ObjectClass *klass, void *data)
 
     k->transfer = max111x_transfer;
     dc->reset = max111x_reset;
+    dc->vmsd = &vmstate_max111x;
 }
 
 static const TypeInfo max111x_info = {
-- 
2.20.1

Add an ssi_realize_and_unref(), for the benefit of callers
who want to be able to create an SSI device, set QOM properties
on it, and then do the realize-and-unref afterwards.

The API works on the same principle as the recently added
qdev_realize_and_undef(), sysbus_realize_and_undef(), etc.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-9-peter.maydell@linaro.org
---
 include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++
 hw/ssi/ssi.c         |  7 ++++++-
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ssi_slave;
 }
 
 DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
+/**
+ * ssi_realize_and_unref: realize and unref an SSI slave device
+ * @dev: SSI slave device to realize
+ * @bus: SSI bus to put it on
+ * @errp: error pointer
+ *
+ * Call 'realize' on @dev, put it on the specified @bus, and drop the
+ * reference to it. Errors are reported via @errp and by returning
+ * false.
+ *
+ * This function is useful if you have created @dev via qdev_new()
+ * (which takes a reference to the device it returns to you), so that
+ * you can set properties on it before realizing it. If you don't need
+ * to set properties then ssi_create_slave() is probably better (as it
+ * does the create, init and realize in one step).
+ *
+ * If you are embedding the SSI slave into another QOM device and
+ * initialized it via some variant on object_initialize_child() then
+ * do not use this function, because that family of functions arrange
+ * for the only reference to the child device to be held by the parent
+ * via the child<> property, and so the reference-count-drop done here
+ * would be incorrect.  (Instead you would want ssi_realize(), which
+ * doesn't currently exist but would be trivial to create if we had
+ * any code that wanted it.)
+ */
+bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
 
 /* Master interface.  */
 SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/ssi.c
+++ b/hw/ssi/ssi.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ssi_slave_info = {
     .abstract = true,
 };
 
+bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
+{
+    return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
+}
+
 DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
 {
     DeviceState *dev = qdev_new(name);
 
-    qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal);
+    ssi_realize_and_unref(dev, bus, &error_fatal);
     return dev;
 }
 
-- 
2.20.1

Use the new max111x qdev properties to set the initial input
values rather than calling max111x_set_input(); this means that
on system reset the inputs will correctly return to their initial
values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200628142429.17111-10-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
                           qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
 
     bus = qdev_get_child_bus(sms->mux, "ssi2");
-    sms->max1111 = ssi_create_slave(bus, "max1111");
+    sms->max1111 = qdev_new("max1111");
     max1111 = sms->max1111;
-    max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
-    max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
-    max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
+    qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
+                        SPITZ_BATTERY_VOLT);
+    qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
+    qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */,
+                        SPITZ_CHARGEON_ACIN);
+    ssi_realize_and_unref(sms->max1111, bus, &error_fatal);
 
     qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
                         qdev_get_gpio_in(sms->mux, 0));
-- 
2.20.1

The max111x ADC device model allows other code to set the level on
the 8 ADC inputs using the max111x_set_input() function.  Replace
this with generic qdev GPIO inputs, which also allow inputs to be set
to arbitrary values.

Using GPIO lines will make it easier for board code to wire things
up, so that if device A wants to set the ADC input it doesn't need to
have a direct pointer to the max111x but can just set that value on
its output GPIO, which is then wired up by the board to the
appropriate max111x input.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-11-peter.maydell@linaro.org
---
 include/hw/ssi/ssi.h |  3 ---
 hw/arm/spitz.c       |  9 +++++----
 hw/misc/max111x.c    | 16 +++++++++-------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -XXX,XX +XXX,XX @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
 
 uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
 
-/* max111x.c */
-void max111x_set_input(DeviceState *dev, int line, uint8_t value);
-
 #endif
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
 
 static void spitz_adc_temp_on(void *opaque, int line, int level)
 {
+    int batt_temp;
+
     if (!max1111)
         return;
 
-    if (level)
-        max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
-    else
-        max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
+    batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
+
+    qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
 }
 
 static void corgi_ssp_realize(SSISlave *d, Error **errp)
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_max111x = {
     }
 };
 
+static void max111x_input_set(void *opaque, int line, int value)
+{
+    MAX111xState *s = MAX_111X(opaque);
+
+    assert(line >= 0 && line < s->inputs);
+    s->input[line] = value;
+}
+
 static int max111x_init(SSISlave *d, int inputs)
 {
     DeviceState *dev = DEVICE(d);
     MAX111xState *s = MAX_111X(dev);
 
     qdev_init_gpio_out(dev, &s->interrupt, 1);
+    qdev_init_gpio_in(dev, max111x_input_set, inputs);
 
     s->inputs = inputs;
 
@@ -XXX,XX +XXX,XX @@ static void max1111_realize(SSISlave *dev, Error **errp)
     max111x_init(dev, 4);
 }
 
-void max111x_set_input(DeviceState *dev, int line, uint8_t value)
-{
-    MAX111xState *s = MAX_111X(dev);
-    assert(line >= 0 && line < s->inputs);
-    s->input[line] = value;
-}
-
 static void max111x_reset(DeviceState *dev)
 {
     MAX111xState *s = MAX_111X(dev);
-- 
2.20.1

Create a header file for the hw/misc/max111x device, in the
usual modern style for QOM devices:
 * definition of the TYPE_ constants and macros
 * definition of the device's state struct so that it can
   be embedded in other structs if desired
 * documentation of the interface

This allows us to use TYPE_MAX_1111 in the spitz.c code rather
than the string "max1111".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200628142429.17111-12-peter.maydell@linaro.org
---
 include/hw/misc/max111x.h | 56 +++++++++++++++++++++++++++++++++++++++
 hw/arm/spitz.c            |  3 ++-
 hw/misc/max111x.c         | 24 +----------------
 MAINTAINERS               |  1 +
 4 files changed, 60 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/misc/max111x.h

diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/max111x.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Maxim MAX1110/1111 ADC chip emulation.
+ *
+ * Copyright (c) 2006 Openedhand Ltd.
+ * Written by Andrzej Zaborowski <balrog@zabor.org>
+ *
+ * This code is licensed under the GNU GPLv2.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#ifndef HW_MISC_MAX111X_H
+#define HW_MISC_MAX111X_H
+
+#include "hw/ssi/ssi.h"
+
+/*
+ * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
+ * is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
+ * 8-bit ADC channels.
+ *
+ * QEMU interface:
+ *  + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
+ *    of each ADC input, as an unsigned 8-bit value
+ *  + GPIO output 0: interrupt line
+ *  + Properties "input0" to "input3" (max1110) or "input0" to "input7"
+ *    (max1111): initial reset values for ADC inputs.
+ *
+ * Known bugs:
+ *  + the interrupt line is not correctly implemented, and will never
+ *    be lowered once it has been asserted.
+ */
+typedef struct {
+    SSISlave parent_obj;
+
+    qemu_irq interrupt;
+    /* Values of inputs at system reset (settable by QOM property) */
+    uint8_t reset_input[8];
+
+    uint8_t tb1, rb2, rb3;
+    int cycle;
+
+    uint8_t input[8];
+    int inputs, com;
+} MAX111xState;
+
+#define TYPE_MAX_111X "max111x"
+
+#define MAX_111X(obj) \
+    OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
+
+#define TYPE_MAX_1110 "max1110"
+#define TYPE_MAX_1111 "max1111"
+
+#endif
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "audio/audio.h"
 #include "hw/boards.h"
 #include "hw/sysbus.h"
+#include "hw/misc/max111x.h"
 #include "migration/vmstate.h"
 #include "exec/address-spaces.h"
 #include "cpu.h"
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
                           qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
 
     bus = qdev_get_child_bus(sms->mux, "ssi2");
-    sms->max1111 = qdev_new("max1111");
+    sms->max1111 = qdev_new(TYPE_MAX_1111);
     max1111 = sms->max1111;
     qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
                         SPITZ_BATTERY_VOLT);
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/misc/max111x.h"
 #include "hw/irq.h"
-#include "hw/ssi/ssi.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
 #include "hw/qdev-properties.h"
 
-typedef struct {
-    SSISlave parent_obj;
-
-    qemu_irq interrupt;
-    /* Values of inputs at system reset (settable by QOM property) */
-    uint8_t reset_input[8];
-
-    uint8_t tb1, rb2, rb3;
-    int cycle;
-
-    uint8_t input[8];
-    int inputs, com;
-} MAX111xState;
-
-#define TYPE_MAX_111X "max111x"
-
-#define MAX_111X(obj) \
-    OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
-
-#define TYPE_MAX_1110 "max1110"
-#define TYPE_MAX_1111 "max1111"
-
 /* Control-byte bitfields */
 #define CB_PD0		(1 << 0)
 #define CB_PD1		(1 << 1)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/gpio/max7310.c
 F: hw/gpio/zaurus.c
 F: hw/misc/mst_fpga.c
 F: hw/misc/max111x.c
+F: include/hw/misc/max111x.h
 F: include/hw/arm/pxa.h
 F: include/hw/arm/sharpsl.h
 F: include/hw/display/tc6393xb.h
-- 
2.20.1

Currently we have a free-floating set of IRQs and a function
spitz_out_switch() which handle some miscellaneous GPIO lines for the
spitz board.  Encapsulate this behaviour in a simple QOM device.

At this point we can finally remove the 'max1111' global, because the
ADC battery-temperature value is now handled by the misc-gpio device
writing the value to its outbound "adc-temp" GPIO, which the board
code wires up to the appropriate inbound GPIO line on the max1111.

This commit also fixes Coverity issue CID 1421913 (which pointed out
that the 'outsignals' in spitz_scoop_gpio_setup() were leaked),
because it removes the use of the qemu_allocate_irqs() API from this
code entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-13-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++----------------
 1 file changed, 87 insertions(+), 42 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     DeviceState *max1111;
     DeviceState *scp0;
     DeviceState *scp1;
+    DeviceState *misc_gpio;
 } SpitzMachineState;
 
 #define TYPE_SPITZ_MACHINE "spitz-common"
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
 #define SPITZ_GPIO_MAX1111_CS   20
 #define SPITZ_GPIO_TP_INT       11
 
-static DeviceState *max1111;
-
 /* "Demux" the signal based on current chipselect */
 typedef struct {
     SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
 #define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
 #define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
 
-static void spitz_adc_temp_on(void *opaque, int line, int level)
-{
-    int batt_temp;
-
-    if (!max1111)
-        return;
-
-    batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
-
-    qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
-}
-
 static void corgi_ssp_realize(SSISlave *d, Error **errp)
 {
     DeviceState *dev = DEVICE(d);
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
 
     bus = qdev_get_child_bus(sms->mux, "ssi2");
     sms->max1111 = qdev_new(TYPE_MAX_1111);
-    max1111 = sms->max1111;
     qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
                         SPITZ_BATTERY_VOLT);
     qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
@@ -XXX,XX +XXX,XX @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu)
 
 /* Other peripherals */
 
-static void spitz_out_switch(void *opaque, int line, int level)
+/*
+ * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards.
+ *
+ * QEMU interface:
+ *  + named GPIO inputs "green-led", "orange-led", "charging", "discharging":
+ *    these currently just print messages that the line has been signalled
+ *  + named GPIO input "adc-temp-on": set to cause the battery-temperature
+ *    value to be passed to the max111x ADC
+ *  + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
+ */
+#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
+#define SPITZ_MISC_GPIO(obj) \
+    OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
+
+typedef struct SpitzMiscGPIOState {
+    SysBusDevice parent_obj;
+
+    qemu_irq adc_value;
+} SpitzMiscGPIOState;
+
+static void spitz_misc_charging(void *opaque, int n, int level)
 {
-    switch (line) {
-    case 0:
-        zaurus_printf("Charging %s.\n", level ? "off" : "on");
-        break;
-    case 1:
-        zaurus_printf("Discharging %s.\n", level ? "on" : "off");
-        break;
-    case 2:
-        zaurus_printf("Green LED %s.\n", level ? "on" : "off");
-        break;
-    case 3:
-        zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
-        break;
-    case 6:
-        spitz_adc_temp_on(opaque, line, level);
-        break;
-    default:
-        g_assert_not_reached();
-    }
+    zaurus_printf("Charging %s.\n", level ? "off" : "on");
+}
+
+static void spitz_misc_discharging(void *opaque, int n, int level)
+{
+    zaurus_printf("Discharging %s.\n", level ? "off" : "on");
+}
+
+static void spitz_misc_green_led(void *opaque, int n, int level)
+{
+    zaurus_printf("Green LED %s.\n", level ? "off" : "on");
+}
+
+static void spitz_misc_orange_led(void *opaque, int n, int level)
+{
+    zaurus_printf("Orange LED %s.\n", level ? "off" : "on");
+}
+
+static void spitz_misc_adc_temp(void *opaque, int n, int level)
+{
+    SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque);
+    int batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
+
+    qemu_set_irq(s->adc_value, batt_temp);
+}
+
+static void spitz_misc_gpio_init(Object *obj)
+{
+    SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj);
+    DeviceState *dev = DEVICE(obj);
+
+    qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1);
+    qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1);
+    qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1);
+    qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1);
+    qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1);
+
+    qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1);
 }
 
 #define SPITZ_SCP_LED_GREEN             1
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
 
 static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
 {
-    qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
+    DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL);
 
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
+    sms->misc_gpio = miscdev;
+
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON,
+                          qdev_get_gpio_in_named(miscdev, "charging", 0));
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B,
+                          qdev_get_gpio_in_named(miscdev, "discharging", 0));
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN,
+                          qdev_get_gpio_in_named(miscdev, "green-led", 0));
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE,
+                          qdev_get_gpio_in_named(miscdev, "orange-led", 0));
+    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON,
+                          qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0));
+    qdev_connect_gpio_out_named(miscdev, "adc-temp", 0,
+                                qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP));
 
     if (sms->scp1) {
         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
         qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
                               qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
     }
-
-    qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 }
 
 #define SPITZ_GPIO_HSYNC                22
@@ -XXX,XX +XXX,XX @@ static const TypeInfo spitz_lcdtg_info = {
     .class_init    = spitz_lcdtg_class_init,
 };
 
+static const TypeInfo spitz_misc_gpio_info = {
+    .name = TYPE_SPITZ_MISC_GPIO,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SpitzMiscGPIOState),
+    .instance_init = spitz_misc_gpio_init,
+    /*
+     * No class_init required: device has no internal state so does not
+     * need to set up reset or vmstate, and does not have a realize method.
+     */
+};
+
 static void spitz_register_types(void)
 {
     type_register_static(&corgi_ssp_info);
     type_register_static(&spitz_lcdtg_info);
     type_register_static(&spitz_keyboard_info);
     type_register_static(&sl_nand_info);
+    type_register_static(&spitz_misc_gpio_info);
 }
 
 type_init(spitz_register_types)
-- 
2.20.1

Instead of logging guest accesses to invalid register offsets in this
device using zaurus_printf() (which just prints to stderr), use the
usual qemu_log_mask(LOG_GUEST_ERROR,...).

Since this was the only use of the zaurus_printf() macro outside
spitz.c, we can move the definition of that macro from sharpsl.h
to spitz.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-14-peter.maydell@linaro.org
---
 include/hw/arm/sharpsl.h |  3 ---
 hw/arm/spitz.c           |  3 +++
 hw/gpio/zaurus.c         | 12 +++++++-----
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/sharpsl.h
+++ b/include/hw/arm/sharpsl.h
@@ -XXX,XX +XXX,XX @@
 
 #include "exec/hwaddr.h"
 
-#define zaurus_printf(format, ...)	\
-    fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
-
 /* zaurus.c */
 
 #define SL_PXA_PARAM_BASE	0xa0000a00
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
 #define SPITZ_MACHINE_CLASS(klass) \
     OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
 
+#define zaurus_printf(format, ...)                              \
+    fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
+
 #undef REG_FMT
 #define REG_FMT                         "0x%02lx"
 
diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/zaurus.c
+++ b/hw/gpio/zaurus.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
-
-#undef REG_FMT
-#define REG_FMT			"0x%02lx"
+#include "qemu/log.h"
 
 /* SCOOP devices */
 
@@ -XXX,XX +XXX,XX @@ static uint64_t scoop_read(void *opaque, hwaddr addr,
     case SCOOP_GPRR:
         return s->gpio_level;
     default:
-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n",
+                      addr);
     }
 
     return 0;
@@ -XXX,XX +XXX,XX @@ static void scoop_write(void *opaque, hwaddr addr,
         scoop_gpio_handler_update(s);
         break;
     default:
-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n",
+                      addr);
     }
 }
 
-- 
2.20.1

Instead of logging guest accesses to invalid register offsets in the
Spitz flash device with zaurus_printf() (which just prints to stderr),
use the usual qemu_log_mask(LOG_GUEST_ERROR,...).

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/ssi/ssi.h"
 #include "hw/block/flash.h"
 #include "qemu/timer.h"
+#include "qemu/log.h"
 #include "hw/arm/sharpsl.h"
 #include "ui/console.h"
 #include "hw/audio/wm8750.h"
@@ -XXX,XX +XXX,XX @@ typedef struct {
 #define zaurus_printf(format, ...)                              \
     fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
 
-#undef REG_FMT
-#define REG_FMT                         "0x%02lx"
-
 /* Spitz Flash */
 #define FLASH_BASE              0x0c000000
 #define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
         return ecc_digest(&s->ecc, nand_getio(s->nand));
 
     default:
-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n",
+                      addr);
     }
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ static void sl_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n",
+                      addr);
     }
 }
 
-- 
2.20.1

Instead of using printf() for logging guest accesses to invalid
register offsets in the pxa2xx PIC device, use the usual
qemu_log_mask(LOG_GUEST_ERROR,...).

This was the only user of the REG_FMT macro in pxa.h, so we can
remove that.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-16-peter.maydell@linaro.org
---
 include/hw/arm/pxa.h | 1 -
 hw/arm/pxa2xx_pic.c  | 9 +++++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/pxa.h
+++ b/include/hw/arm/pxa.h
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
 };
 
 # define PA_FMT			"0x%08lx"
-# define REG_FMT		"0x" TARGET_FMT_plx
 
 PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
                          const char *revision);
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/module.h"
+#include "qemu/log.h"
 #include "cpu.h"
 #include "hw/arm/pxa.h"
 #include "hw/sysbus.h"
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
     case ICHP:	/* Highest Priority register */
         return pxa2xx_pic_highest(s);
     default:
-        printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
+                      "\n", offset);
         return 0;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
         break;
     default:
-        printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pxa2xx_pic_mem_write: bad register offset 0x%"
+                      HWADDR_PRIx "\n", offset);
         return;
     }
     pxa2xx_pic_update(opaque);
-- 
2.20.1

The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the
usual QOM TYPE and casting macros; provide and use them.

In particular, we can safely use the QOM cast macros instead of
FROM_SSI_SLAVE() because in both cases the 'ssidev' field of
the instance state struct is the first field in it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-17-peter.maydell@linaro.org
---
 hw/arm/spitz.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
 #define LCDTG_PICTRL    0x06
 #define LCDTG_POLCTRL   0x07
 
+#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
+#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
+
 typedef struct {
     SSISlave ssidev;
     uint32_t bl_intensity;
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_power(void *opaque, int line, int level)
 
 static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
 {
-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
+    SpitzLCDTG *s = SPITZ_LCDTG(dev);
     int addr;
     addr = value >> 5;
     value &= 0x1f;
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
 
 static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
 {
-    SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
+    SpitzLCDTG *s = SPITZ_LCDTG(ssi);
     DeviceState *dev = DEVICE(s);
 
     s->bl_power = 0;
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
 #define SPITZ_GPIO_MAX1111_CS   20
 #define SPITZ_GPIO_TP_INT       11
 
+#define TYPE_CORGI_SSP "corgi-ssp"
+#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
+
 /* "Demux" the signal based on current chipselect */
 typedef struct {
     SSISlave ssidev;
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
 {
-    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
+    CorgiSSPState *s = CORGI_SSP(dev);
     int i;
 
     for (i = 0; i < 3; i++) {
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
 static void corgi_ssp_realize(SSISlave *d, Error **errp)
 {
     DeviceState *dev = DEVICE(d);
-    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d);
+    CorgiSSPState *s = CORGI_SSP(d);
 
     qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
     s->bus[0] = ssi_create_bus(dev, "ssi0");
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
 {
     void *bus;
 
-    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
+    sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
+                                TYPE_CORGI_SSP);
 
     bus = qdev_get_child_bus(sms->mux, "ssi0");
-    sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
+    sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
 
     bus = qdev_get_child_bus(sms->mux, "ssi1");
     sms->ads7846 = ssi_create_slave(bus, "ads7846");
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo corgi_ssp_info = {
-    .name          = "corgi-ssp",
+    .name          = TYPE_CORGI_SSP,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(CorgiSSPState),
     .class_init    = corgi_ssp_class_init,
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo spitz_lcdtg_info = {
-    .name          = "spitz-lcdtg",
+    .name          = TYPE_SPITZ_LCDTG,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(SpitzLCDTG),
     .class_init    = spitz_lcdtg_class_init,
-- 
2.20.1

The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way
to cast from an SSISlave* to the instance struct of a subtype of
TYPE_SSI_SLAVE.  Switch to using the QOM cast macros instead, which
have the same effect (by writing the QOM macros if the types were
previously missing them.)

(The FROM_SSI_SLAVE() macro allows the SSISlave member of the
subtype's struct to be anywhere as long as it is named "ssidev",
whereas a QOM cast macro insists that it is the first thing in the
subtype's struct.  This is true for all the types we convert here.)

This removes all the uses of FROM_SSI_SLAVE() so we can delete the
definition.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200628142429.17111-18-peter.maydell@linaro.org
---
 include/hw/ssi/ssi.h |  2 --
 hw/arm/z2.c          | 11 +++++++----
 hw/display/ads7846.c |  9 ++++++---
 hw/display/ssd0323.c | 10 +++++++---
 hw/sd/ssi-sd.c       |  4 ++--
 5 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -XXX,XX +XXX,XX @@ struct SSISlave {
     bool cs;
 };
 
-#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
-
 extern const VMStateDescription vmstate_ssi_slave;
 
 #define VMSTATE_SSI_SLAVE(_field, _state) {                          \
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     int pos;
 } ZipitLCD;
 
+#define TYPE_ZIPIT_LCD "zipit-lcd"
+#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD)
+
 static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
 {
-    ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
+    ZipitLCD *z = ZIPIT_LCD(dev);
     uint16_t val;
     if (z->selected) {
         z->buf[z->pos] = value & 0xff;
@@ -XXX,XX +XXX,XX @@ static void z2_lcd_cs(void *opaque, int line, int level)
 
 static void zipit_lcd_realize(SSISlave *dev, Error **errp)
 {
-    ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
+    ZipitLCD *z = ZIPIT_LCD(dev);
     z->selected = 0;
     z->enabled = 0;
     z->pos = 0;
@@ -XXX,XX +XXX,XX @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo zipit_lcd_info = {
-    .name          = "zipit-lcd",
+    .name          = TYPE_ZIPIT_LCD,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(ZipitLCD),
     .class_init    = zipit_lcd_class_init,
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
 
     type_register_static(&zipit_lcd_info);
     type_register_static(&aer915_info);
-    z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd");
+    z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD);
     bus = pxa2xx_i2c_bus(mpu->i2c[0]);
     i2c_create_slave(bus, TYPE_AER915, 0x55);
     wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b);
diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/ads7846.c
+++ b/hw/display/ads7846.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     int output;
 } ADS7846State;
 
+#define TYPE_ADS7846 "ads7846"
+#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846)
+
 /* Control-byte bitfields */
 #define CB_PD0		(1 << 0)
 #define CB_PD1		(1 << 1)
@@ -XXX,XX +XXX,XX @@ static void ads7846_int_update(ADS7846State *s)
 
 static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value)
 {
-    ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev);
+    ADS7846State *s = ADS7846(dev);
 
     switch (s->cycle ++) {
     case 0:
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ads7846 = {
 static void ads7846_realize(SSISlave *d, Error **errp)
 {
     DeviceState *dev = DEVICE(d);
-    ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d);
+    ADS7846State *s = ADS7846(d);
 
     qdev_init_gpio_out(dev, &s->interrupt, 1);
 
@@ -XXX,XX +XXX,XX @@ static void ads7846_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo ads7846_info = {
-    .name          = "ads7846",
+    .name          = TYPE_ADS7846,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(ADS7846State),
     .class_init    = ads7846_class_init,
diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/ssd0323.c
+++ b/hw/display/ssd0323.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     uint8_t framebuffer[128 * 80 / 2];
 } ssd0323_state;
 
+#define TYPE_SSD0323 "ssd0323"
+#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323)
+
+
 static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
 {
-    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
+    ssd0323_state *s = SSD0323(dev);
 
     switch (s->mode) {
     case SSD0323_DATA:
@@ -XXX,XX +XXX,XX @@ static const GraphicHwOps ssd0323_ops = {
 static void ssd0323_realize(SSISlave *d, Error **errp)
 {
     DeviceState *dev = DEVICE(d);
-    ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
+    ssd0323_state *s = SSD0323(d);
 
     s->col_end = 63;
     s->row_end = 79;
@@ -XXX,XX +XXX,XX @@ static void ssd0323_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo ssd0323_info = {
-    .name          = "ssd0323",
+    .name          = TYPE_SSD0323,
     .parent        = TYPE_SSI_SLAVE,
     .instance_size = sizeof(ssd0323_state),
     .class_init    = ssd0323_class_init,
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
 {
-    ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev);
+    ssi_sd_state *s = SSI_SD(dev);
 
     /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data.  */
     if (s->mode == SSI_SD_DATA_READ && val == 0x4d) {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ssi_sd = {
 
 static void ssi_sd_realize(SSISlave *d, Error **errp)
 {
-    ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
+    ssi_sd_state *s = SSI_SD(d);
     DeviceState *carddev;
     DriveInfo *dinfo;
     Error *err = NULL;
-- 
2.20.1

Deprecate our TileGX target support:
 * we have no active maintainer for it
 * it has had essentially no contributions (other than tree-wide cleanups
   and similar) since it was first added
 * the Linux kernel dropped support in 2018, as has glibc

Note the deprecation in the manual, but don't try to print a warning
when QEMU runs -- printing unsuppressable messages is more obtrusive
for linux-user mode than it would be for system-emulation mode, and
it doesn't seem worth trying to invent a new suppressible-error
system for linux-user just for this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20200619154831.26319-1-peter.maydell@linaro.org
---
 docs/system/deprecated.rst | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
 
   json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
 
+linux-user mode CPUs
+--------------------
+
+``tilegx`` CPUs (since 5.1.0)
+'''''''''''''''''''''''''''''
+
+The ``tilegx`` guest CPU support (which was only implemented in
+linux-user mode) is deprecated and will be removed in a future version
+of QEMU. Support for this CPU was removed from the upstream Linux
+kernel in 2018, and has also been dropped from glibc.
+
 Related binaries
 ----------------
 
-- 
2.20.1