target/mips: Fix store adress of high 64bit in helper_msa_st_b()

[PATCH] target/mips: Fix store adress of high 64bit in helper_msa_st_b()

nihui posted 1 patch 1 year, 11 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20220504023319.12923-1-shuizhuyuanluo@126.com

Maintainers: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>

target/mips/tcg/msa_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

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[PATCH] target/mips: Fix store adress of high 64bit in helper_msa_st_b()

Posted by nihui 1 year, 11 months ago

This patch fix the issue that helper_msa_st_b() write high 64bit
data to where the low 64bit resides, leaving high 64bit undefined.

Signed-off-by: Ni Hui <shuizhuyuanluo@126.com>
---
 target/mips/tcg/msa_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index 4dde5d639a..736283e2af 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -8329,7 +8329,7 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
 
     /* Store 8 bytes at a time.  Vector element ordering makes this LE.  */
     cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra);
-    cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra);
+    cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra);
 }
 
 void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
-- 
2.25.1

Re: [PATCH] target/mips: Fix store adress of high 64bit in helper_msa_st_b()

Posted by Philippe Mathieu-Daudé via 1 year, 11 months ago

On 4/5/22 04:33, nihui wrote:
> This patch fix the issue that helper_msa_st_b() write high 64bit
> data to where the low 64bit resides, leaving high 64bit undefined.
> 
> Signed-off-by: Ni Hui <shuizhuyuanluo@126.com>
> ---
>   target/mips/tcg/msa_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
> index 4dde5d639a..736283e2af 100644
> --- a/target/mips/tcg/msa_helper.c
> +++ b/target/mips/tcg/msa_helper.c
> @@ -8329,7 +8329,7 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
>   
>       /* Store 8 bytes at a time.  Vector element ordering makes this LE.  */
>       cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra);
> -    cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra);
> +    cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra);
>   }
>   
>   void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,

Fixes: 68ad9260e0 ("target/mips: Use 8-byte memory ops for msa load/store")

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Queued to mips-next.

Re: [PATCH] target/mips: Fix store adress of high 64bit in helper_msa_st_b()

Posted by Richard Henderson 1 year, 11 months ago

On 5/3/22 19:33, nihui wrote:
> This patch fix the issue that helper_msa_st_b() write high 64bit
> data to where the low 64bit resides, leaving high 64bit undefined.
> 
> Signed-off-by: Ni Hui<shuizhuyuanluo@126.com>
> ---
>   target/mips/tcg/msa_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~