The following changes since commit f5643914a9e8f79c606a76e6a9d7ea82a3fc3e65:

Merge tag 'pull-9p-20220501' of https://github.com/cschoenebeck/qemu into staging (2022-05-01 07:48:11 -0700)

https://github.com/legoater/qemu/ tags/pull-aspeed-20220503

for you to fetch changes up to e056c52233910ef156e6d790ce41b33cd838bad6:

aspeed/hace: Support AST1030 HACE (2022-05-03 07:17:20 +0200)

* New AST1030 SoC and eval board

* Accumulative mode support for HACE controller

* GPIO fix and unit test

* Clock modeling adjustments for the AST2600

* Dummy eMMC Boot Controller model

* Change of AST2500 EVB and AST2600 EVB flash model (for quad IO)

Jae Hyun Yoo (1):

hw/arm/aspeed: fix AST2500/AST2600 EVB fmc model

Jamin Lin (2):

aspeed: Add an AST1030 eval board

test/avocado/machine_aspeed.py: Add ast1030 test case

Joel Stanley (2):

aspeed: sbc: Correct default reset values

aspeed: Add eMMC Boot Controller stub

From: Steven Lee <steven_lee@aspeedtech.com>

Per ast1030_v7.pdf, AST1030 HACE engine is identical to AST2600's HACE

engine.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

include/hw/misc/aspeed_hace.h | 2 ++

hw/misc/aspeed_hace.c | 20 ++++++++++++++++++++

2 files changed, 22 insertions(+)

diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h

--- a/include/hw/misc/aspeed_hace.h

+++ b/include/hw/misc/aspeed_hace.h

@@ -XXX,XX +XXX,XX @@

#define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400"

#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"

#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"

+#define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"

+

OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)

#define ASPEED_HACE_NR_REGS (0x64 >> 2)

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_hace.c

+++ b/hw/misc/aspeed_hace.c

@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_ast2600_hace_info = {

.class_init = aspeed_ast2600_hace_class_init,

};

+static void aspeed_ast1030_hace_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+ AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass);

+

+ dc->desc = "AST1030 Hash and Crypto Engine";

+

+ ahc->src_mask = 0x7FFFFFFF;

+ ahc->dest_mask = 0x7FFFFFF8;

+ ahc->key_mask = 0x7FFFFFF8;

+ ahc->hash_mask = 0x00147FFF;

+}

+

+static const TypeInfo aspeed_ast1030_hace_info = {

+ .name = TYPE_ASPEED_AST1030_HACE,

+ .parent = TYPE_ASPEED_HACE,

+ .class_init = aspeed_ast1030_hace_class_init,

+};

+

static void aspeed_hace_register_types(void)

{

type_register_static(&aspeed_ast2400_hace_info);

type_register_static(&aspeed_ast2500_hace_info);

type_register_static(&aspeed_ast2600_hace_info);

+ type_register_static(&aspeed_ast1030_hace_info);

type_register_static(&aspeed_hace_info);

}

2.35.1

From: Peter Delevoryas <pdel@fb.com>

I was setting gpioV4-7 to "1110" using the QOM pin property handler and

noticed that lowering gpioV7 was inadvertently lowering gpioV4-6 too.

(qemu) qom-set /machine/soc/gpio gpioV4 true

(qemu) qom-set /machine/soc/gpio gpioV5 true

(qemu) qom-set /machine/soc/gpio gpioV6 true

(qemu) qom-get /machine/soc/gpio gpioV4

true

(qemu) qom-set /machine/soc/gpio gpioV7 false

(qemu) qom-get /machine/soc/gpio gpioV4

false

An expression in aspeed_gpio_set_pin_level was using a logical NOT

operator instead of a bitwise NOT operator:

value &= !pin_mask;

The original author probably intended to make a bitwise NOT expression

"~", but mistakenly used a logical NOT operator "!" instead. Some

programming languages like Rust use "!" for both purposes.

Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and

AST2500")

Signed-off-by: Peter Delevoryas <pdel@fb.com>

Message-Id: <20220502080827.244815-1-pdel@fb.com>

hw/gpio/aspeed_gpio.c | 2 +-

tests/qtest/aspeed_gpio-test.c | 87 ++++++++++++++++++++++++++++++++++

tests/qtest/meson.build | 3 +-

3 files changed, 90 insertions(+), 2 deletions(-)

create mode 100644 tests/qtest/aspeed_gpio-test.c

diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c

--- a/hw/gpio/aspeed_gpio.c

+++ b/hw/gpio/aspeed_gpio.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx,

if (level) {

value |= pin_mask;

} else {

- value &= !pin_mask;

+ value &= ~pin_mask;

}

aspeed_gpio_update(s, &s->sets[set_idx], value);

diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c

+++ b/tests/qtest/aspeed_gpio-test.c

+ * QTest testcase for the Aspeed GPIO Controller.

+ * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com)

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+#include "qemu/bitops.h"

+#include "qemu/timer.h"

+#include "qapi/qmp/qdict.h"

+#include "libqtest-single.h"

+

+static bool qom_get_bool(QTestState *s, const char *path, const char *property)

+{

+ QDict *r;

+ bool b;

+

+ r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': "

+ "{ 'path': %s, 'property': %s } }", path, property);

+ b = qdict_get_bool(r, "return");

+ qobject_unref(r);

+

+ return b;

+}

+

+static void qom_set_bool(QTestState *s, const char *path, const char *property,

+ bool value)

+{

+ QDict *r;

+

+ r = qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': "

+ "{ 'path': %s, 'property': %s, 'value': %i } }",

+ path, property, value);

+ qobject_unref(r);

+}

+

+static void test_set_colocated_pins(const void *data)

+{

+ QTestState *s = (QTestState *)data;

+ * gpioV4-7 occupy bits within a single 32-bit value, so we want to make

+ * sure that modifying one doesn't affect the other.

+ qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true);

+ qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false);

+ qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true);

+ qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false);

+ g_assert(qom_get_bool(s, "/machine/soc/gpio", "gpioV4"));

+ g_assert(!qom_get_bool(s, "/machine/soc/gpio", "gpioV5"));

+ g_assert(qom_get_bool(s, "/machine/soc/gpio", "gpioV6"));

+ g_assert(!qom_get_bool(s, "/machine/soc/gpio", "gpioV7"));

+}

+

+int main(int argc, char **argv)

+{

+ QTestState *s;

+ int r;

+

+ g_test_init(&argc, &argv, NULL);

+

+ s = qtest_init("-machine ast2600-evb");

+ qtest_add_data_func("/ast2600/gpio/set_colocated_pins", s,

+ test_set_colocated_pins);

+ r = g_test_run();

+ qtest_quit(s);

+

+ return r;

+}

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build

--- a/tests/qtest/meson.build

+++ b/tests/qtest/meson.build

@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \

(slirp.found() ? ['npcm7xx_emc-test'] : [])

qtests_aspeed = \

['aspeed_hace-test',

- 'aspeed_smc-test']

+ 'aspeed_smc-test',

+ 'aspeed_gpio-test']

qtests_arm = \

(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \

(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \

2.35.1

From: Steven Lee <steven_lee@aspeedtech.com>

The aspeed ast2600 accumulative mode is described in datasheet

ast2600v10.pdf section 25.6.4:

1. Allocating and initiating accumulative hash digest write buffer

with initial state.

* Since QEMU crypto/hash api doesn't provide the API to set initial

state of hash library, and the initial state is already set by

crypto library (gcrypt/glib/...), so skip this step.

2. Calculating accumulative hash digest.

(a) When receiving the last accumulative data, software need to add

padding message at the end of the accumulative data. Padding

message described in specific of MD5, SHA-1, SHA224, SHA256,

SHA512, SHA512/224, SHA512/256.

* Since the crypto library (gcrypt/glib) already pad the

padding message internally.

* This patch is to remove the padding message which fed byguest

machine driver.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

include/hw/misc/aspeed_hace.h | 4 ++

hw/misc/aspeed_hace.c | 132 ++++++++++++++++++++++++++++++++--

2 files changed, 131 insertions(+), 5 deletions(-)

diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h

--- a/include/hw/misc/aspeed_hace.h

+++ b/include/hw/misc/aspeed_hace.h

@@ -XXX,XX +XXX,XX @@

OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)

#define ASPEED_HACE_NR_REGS (0x64 >> 2)

+#define ASPEED_HACE_MAX_SG 256 /* max number of entries */

struct AspeedHACEState {

SysBusDevice parent;

@@ -XXX,XX +XXX,XX @@ struct AspeedHACEState {

MemoryRegion iomem;

qemu_irq irq;

+ struct iovec iov_cache[ASPEED_HACE_MAX_SG];

uint32_t regs[ASPEED_HACE_NR_REGS];

+ uint32_t total_req_len;

+ uint32_t iov_count;

MemoryRegion *dram_mr;

AddressSpace dram_as;

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_hace.c

+++ b/hw/misc/aspeed_hace.c

@@ -XXX,XX +XXX,XX @@

#define SG_LIST_ADDR_SIZE 4

#define SG_LIST_ADDR_MASK 0x7FFFFFFF

#define SG_LIST_ENTRY_SIZE (SG_LIST_LEN_SIZE + SG_LIST_ADDR_SIZE)

-#define ASPEED_HACE_MAX_SG 256 /* max number of entries */

static const struct {

uint32_t mask;

@@ -XXX,XX +XXX,XX @@ static int hash_algo_lookup(uint32_t reg)

return -1;

-static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode)

+/**

+ * Check whether the request contains padding message.

+ *

+ * @param s aspeed hace state object

+ * @param iov iov of current request

+ * @param req_len length of the current request

+ * @param total_msg_len length of all acc_mode requests(excluding padding msg)

+ * @param pad_offset start offset of padding message

+ */

+static bool has_padding(AspeedHACEState *s, struct iovec *iov,

+ hwaddr req_len, uint32_t *total_msg_len,

+ uint32_t *pad_offset)

+{

+ *total_msg_len = (uint32_t)(ldq_be_p(iov->iov_base + req_len - 8) / 8);

+ /*

+ * SG_LIST_LEN_LAST asserted in the request length doesn't mean it is the

+ * last request. The last request should contain padding message.

+ * We check whether message contains padding by

+ * 1. Get total message length. If the current message contains

+ * padding, the last 8 bytes are total message length.

+ * 2. Check whether the total message length is valid.

+ * If it is valid, the value should less than or equal to

+ * total_req_len.

+ * 3. Current request len - padding_size to get padding offset.

+ * The padding message's first byte should be 0x80

+ */

+ if (*total_msg_len <= s->total_req_len) {

+ uint32_t padding_size = s->total_req_len - *total_msg_len;

+ uint8_t *padding = iov->iov_base;

+ *pad_offset = req_len - padding_size;

+ if (padding[*pad_offset] == 0x80) {

+ return true;

+ }

+ }

+

+ return false;

+}

+

+static int reconstruct_iov(AspeedHACEState *s, struct iovec *iov, int id,

+ uint32_t *pad_offset)

+{

+ int i, iov_count;

+ if (*pad_offset != 0) {

+ s->iov_cache[s->iov_count].iov_base = iov[id].iov_base;

+ s->iov_cache[s->iov_count].iov_len = *pad_offset;

+ ++s->iov_count;

+ }

+ for (i = 0; i < s->iov_count; i++) {

+ iov[i].iov_base = s->iov_cache[i].iov_base;

+ iov[i].iov_len = s->iov_cache[i].iov_len;

+ }

+ iov_count = s->iov_count;

+ s->iov_count = 0;

+ s->total_req_len = 0;

+ return iov_count;

+}

+

+/**

+ * Generate iov for accumulative mode.

+ *

+ * @param s aspeed hace state object

+ * @param iov iov of the current request

+ * @param id index of the current iov

+ * @param req_len length of the current request

+ *

+ * @return count of iov

+ */

+static int gen_acc_mode_iov(AspeedHACEState *s, struct iovec *iov, int id,

+ hwaddr *req_len)

+{

+ uint32_t pad_offset;

+ uint32_t total_msg_len;

+ s->total_req_len += *req_len;

+

+ if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) {

+ if (s->iov_count) {

+ return reconstruct_iov(s, iov, id, &pad_offset);

+ }

+

+ *req_len -= s->total_req_len - total_msg_len;

+ s->total_req_len = 0;

+ iov[id].iov_len = *req_len;

+ } else {

+ s->iov_cache[s->iov_count].iov_base = iov->iov_base;

+ s->iov_cache[s->iov_count].iov_len = *req_len;

+ ++s->iov_count;

+ }

+

+ return id + 1;

+}

+

+static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,

+ bool acc_mode)

struct iovec iov[ASPEED_HACE_MAX_SG];

g_autofree uint8_t *digest_buf;

size_t digest_len = 0;

+ int niov = 0;

int i;

if (sg_mode) {

@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode)

MEMTXATTRS_UNSPECIFIED, NULL);

addr &= SG_LIST_ADDR_MASK;

- iov[i].iov_len = len & SG_LIST_LEN_MASK;

- plen = iov[i].iov_len;

+ plen = len & SG_LIST_LEN_MASK;

iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false,

MEMTXATTRS_UNSPECIFIED);

+

+ if (acc_mode) {

+ niov = gen_acc_mode_iov(s, iov, i, &plen);

+

+ } else {

+ iov[i].iov_len = plen;

+ }

}

} else {

hwaddr len = s->regs[R_HASH_SRC_LEN];

@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode)

&len, false,

MEMTXATTRS_UNSPECIFIED);

i = 1;

+

+ if (s->iov_count) {

+ /*

+ * In aspeed sdk kernel driver, sg_mode is disabled in hash_final().

+ * Thus if we received a request with sg_mode disabled, it is

+ * required to check whether cache is empty. If no, we should

+ * combine cached iov and the current iov.

+ */

+ uint32_t total_msg_len;

+ uint32_t pad_offset;

+ s->total_req_len += len;

+ if (has_padding(s, iov, len, &total_msg_len, &pad_offset)) {

+ niov = reconstruct_iov(s, iov, 0, &pad_offset);

+ }

+ }

+ }

+

+ if (niov) {

+ i = niov;

}

if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, &digest_len, NULL) < 0) {

@@ -XXX,XX +XXX,XX @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,

__func__, data & ahc->hash_mask);

break;

}

- do_hash_operation(s, algo, data & HASH_SG_EN);

+ do_hash_operation(s, algo, data & HASH_SG_EN,

+ ((data & HASH_HMAC_MASK) == HASH_DIGEST_ACCUM));

if (data & HASH_IRQ_EN) {

qemu_irq_raise(s->irq);

@@ -XXX,XX +XXX,XX @@ static void aspeed_hace_reset(DeviceState *dev)

struct AspeedHACEState *s = ASPEED_HACE(dev);

memset(s->regs, 0, sizeof(s->regs));

+ s->iov_count = 0;

+ s->total_req_len = 0;

}

static void aspeed_hace_realize(DeviceState *dev, Error **errp)

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_hace = {

.minimum_version_id = 1,

.fields = (VMStateField[]) {

VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS),

+ VMSTATE_UINT32(total_req_len, AspeedHACEState),

+ VMSTATE_UINT32(iov_count, AspeedHACEState),

VMSTATE_END_OF_LIST(),

}

2.35.1

From: Steven Lee <steven_lee@aspeedtech.com>

Support HACE28: Hash HMAC Key Buffer Base Address Register.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

include/hw/misc/aspeed_hace.h | 1 +

hw/misc/aspeed_hace.c | 7 +++++++

2 files changed, 8 insertions(+)

diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h

--- a/include/hw/misc/aspeed_hace.h

+++ b/include/hw/misc/aspeed_hace.h

@@ -XXX,XX +XXX,XX @@ struct AspeedHACEClass {

uint32_t src_mask;

uint32_t dest_mask;

+ uint32_t key_mask;

uint32_t hash_mask;

};

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_hace.c

+++ b/hw/misc/aspeed_hace.c

@@ -XXX,XX +XXX,XX @@

#define R_HASH_SRC (0x20 / 4)

#define R_HASH_DEST (0x24 / 4)

+#define R_HASH_KEY_BUFF (0x28 / 4)

#define R_HASH_SRC_LEN (0x2c / 4)

#define R_HASH_CMD (0x30 / 4)

@@ -XXX,XX +XXX,XX @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,

case R_HASH_DEST:

data &= ahc->dest_mask;

break;

+ case R_HASH_KEY_BUFF:

+ data &= ahc->key_mask;

+ break;

case R_HASH_SRC_LEN:

data &= 0x0FFFFFFF;

break;

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data)

ahc->src_mask = 0x0FFFFFFF;

ahc->dest_mask = 0x0FFFFFF8;

+ ahc->key_mask = 0x0FFFFFC0;

ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data)

ahc->src_mask = 0x3fffffff;

ahc->dest_mask = 0x3ffffff8;

+ ahc->key_mask = 0x3FFFFFC0;

ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */

@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data)

ahc->src_mask = 0x7FFFFFFF;

ahc->dest_mask = 0x7FFFFFF8;

+ ahc->key_mask = 0x7FFFFFF8;

ahc->hash_mask = 0x00147FFF;

}

2.35.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

The image should be supplied with ELF binary.

$ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

hw/arm/aspeed.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++

1 file changed, 66 insertions(+)

@@ -XXX,XX +XXX,XX @@

#include "hw/loader.h"

#include "qemu/error-report.h"

#include "qemu/units.h"

+#include "hw/qdev-clock.h"

static struct arm_boot_info aspeed_board_binfo = {

.board_id = -1, /* device-tree-only board */