Series comparison

-[PULL 00/25] riscv-to-apply queue
+[PULL 00/54] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit a51e5124a655b3dad80b36b18547cb1eca2c5eb2:
-The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:
+  Merge tag 'pull-omnibus-111023-1' of https://gitlab.com/stsquad/qemu into staging (2023-10-11 09:43:10 -0400)
   Merge tag 'pull-target-arm-20220428' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28 08:34:17 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220429
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231012-1
-for you to fetch changes up to 325b7c4e7582c229d28c47123c3b986ed948eb84:
+for you to fetch changes up to 837570cef237b634eb4c245363470deebea7089d:
-  hw/riscv: Enable TPM backends (2022-04-29 10:48:48 +1000)
+  target/riscv: Fix vfwmaccbf16.vf (2023-10-12 12:50:13 +1000)
 ----------------------------------------------------------------
-Second RISC-V PR for QEMU 7.1
+Second RISC-V PR for 8.2
- * Improve device tree generation
+ * Add support for the max CPU
- * Support configuarable marchid, mvendorid, mipid CSR values
+ * Detect user choice in TCG
- * Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions
+ * Clear CSR values at reset and sync MPSTATE with host
- * Fix incorrect PTE merge in walk_pte
+ * Fix the typo of inverted order of pmpaddr13 and pmpaddr14
- * Add TPM support to the virt board
+ * Split TCG/KVM accelerators from cpu.c
  * Add extension properties for all cpus
  * Replace GDB exit calls with proper shutdown
  * Support KVM_GET_REG_LIST
  * Remove RVG warning
  * Use env_archcpu for better performance
  * Deprecate capital 'Z' CPU properties
  * Fix vfwmaccbf16.vf
 ----------------------------------------------------------------
-Alistair Francis (6):
+Alvin Chang (1):
-      hw/riscv: virt: Add a machine done notifier
+      disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14
       hw/core: Move the ARM sysbus-fdt to core
       hw/riscv: virt: Create a platform bus
       hw/riscv: virt: Add support for generating platform FDT entries
       hw/riscv: virt: Add device plug support
       hw/riscv: Enable TPM backends
-Bin Meng (2):
+Clément Chigot (5):
-      hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
+      softmmu: add means to pass an exit code when requesting a shutdown
-      hw/riscv: Don't add empty bootargs to device tree
+      softmmu: pass the main loop status to gdb "Wxx" packet
       hw/misc/sifive_test.c: replace exit calls with proper shutdown
       hw/char: riscv_htif: replace exit calls with proper shutdown
       gdbstub: replace exit calls with proper shutdown for softmmu
-Frank Chang (1):
+Daniel Henrique Barboza (45):
-      target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
+      target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
       target/riscv/cpu.c: skip 'bool' check when filtering KVM props
       target/riscv/cpu.c: split kvm prop handling to its own helper
       target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
       target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
       target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
       target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
       target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
       target/riscv/cpu.c: limit cfg->vext_spec log message
       target/riscv: add 'max' CPU type
       avocado, risc-v: add tuxboot tests for 'max' CPU
       target/riscv: deprecate the 'any' CPU type
       target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
       target/riscv: make CPUCFG() macro public
       target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
       target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
       target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
       target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
       target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
       target/riscv/cpu.c: consider user option with RVG
       target/riscv: introduce TCG AccelCPUClass
       target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
       target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
       target/riscv: move riscv_tcg_ops to tcg-cpu.c
       target/riscv/cpu.c: add .instance_post_init()
       target/riscv: move 'host' CPU declaration to kvm.c
       target/riscv/cpu.c: mark extensions arrays as 'const'
       target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
       target/riscv: make riscv_add_satp_mode_properties() public
       target/riscv: remove kvm-stub.c
       target/riscv: introduce KVM AccelCPUClass
       target/riscv: move KVM only files to kvm subdir
       target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
       target/riscv/cpu.c: export set_misa()
       target/riscv/tcg: introduce tcg_cpu_instance_init()
       target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
       target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
       target/riscv/cpu.c: export isa_edata_arr[]
       target/riscv/cpu: move priv spec functions to tcg-cpu.c
       target/riscv: add riscv_cpu_get_name()
       target/riscv/tcg-cpu.c: add extension properties for all cpus
       target/riscv/kvm: improve 'init_multiext_cfg' error msg
       target/riscv/kvm: support KVM_GET_REG_LIST
       target/riscv/tcg: remove RVG warning
       target/riscv: deprecate capital 'Z' CPU properties
-Ralf Ramsauer (1):
+Max Chou (1):
-      target/riscv: Fix incorrect PTE merge in walk_pte
+      target/riscv: Fix vfwmaccbf16.vf
-Weiwei Li (15):
+Richard W.M. Jones (1):
-      target/riscv: rvk: add cfg properties for zbk* and zk*
+      target/riscv: Use env_archcpu for better performance
       target/riscv: rvk: add support for zbkb extension
       target/riscv: rvk: add support for zbkc extension
       target/riscv: rvk: add support for zbkx extension
       crypto: move sm4_sbox from target/arm
       target/riscv: rvk: add support for zknd/zkne extension in RV32
       target/riscv: rvk: add support for zkne/zknd extension in RV64
       target/riscv: rvk: add support for sha256 related instructions in zknh extension
       target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
       target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
       target/riscv: rvk: add support for zksed/zksh extension
       target/riscv: rvk: add CSR support for Zkr
       disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
       target/riscv: rvk: expose zbk* and zk* properties
       target/riscv: add scalar crypto related extenstion strings to isa_string
- docs/system/riscv/virt.rst              |  20 ++
+liguang.zhang (1):
- include/crypto/sm4.h                    |   6 +
+      target/riscv: Clear CSR values at reset and sync MPSTATE with host
- include/hw/{arm => core}/sysbus-fdt.h   |   0
- include/hw/riscv/virt.h                 |   8 +-
+ docs/about/deprecated.rst             |   35 ++
- target/riscv/cpu.h                      |  17 ++
+ include/gdbstub/syscalls.h            |    9 +
- target/riscv/cpu_bits.h                 |   9 +
+ include/sysemu/runstate.h             |    2 +
- target/riscv/helper.h                   |  22 ++
+ include/sysemu/sysemu.h               |    2 +-
- target/riscv/pmp.h                      |   8 +-
+ target/riscv/cpu-qom.h                |    1 +
- target/riscv/insn32.decode              |  97 ++++++--
+ target/riscv/cpu.h                    |   34 +-
- crypto/sm4.c                            |  49 ++++
+ target/riscv/{ => kvm}/kvm_riscv.h    |    2 +-
- disas/riscv.c                           | 173 +++++++++++++-
+ target/riscv/tcg/tcg-cpu.h            |   27 +
- hw/arm/virt.c                           |   2 +-
+ disas/riscv.c                         |    4 +-
- hw/arm/xlnx-versal-virt.c               |   1 -
+ gdbstub/gdbstub.c                     |    5 +-
- hw/{arm => core}/sysbus-fdt.c           |   2 +-
+ gdbstub/system.c                      |    6 +
- hw/riscv/microchip_pfsoc.c              |   2 +-
+ gdbstub/user.c                        |    6 +
- hw/riscv/sifive_u.c                     |   2 +-
+ hw/char/riscv_htif.c                  |    5 +-
- hw/riscv/spike.c                        |   7 +-
+ hw/intc/riscv_aplic.c                 |    2 +-
- hw/riscv/virt.c                         | 319 +++++++++++++++++---------
+ hw/misc/sifive_test.c                 |    9 +-
- target/arm/crypto_helper.c              |  36 +--
+ hw/riscv/virt.c                       |    2 +-
- target/riscv/bitmanip_helper.c          |  80 +++++++
+ system/main.c                         |    2 +-
- target/riscv/cpu.c                      |  58 +++++
+ system/runstate.c                     |   16 +-
- target/riscv/crypto_helper.c            | 302 ++++++++++++++++++++++++
+ target/riscv/cpu.c                    | 1030 +++++++--------------------------
- target/riscv/csr.c                      | 118 +++++++++-
+ target/riscv/cpu_helper.c             |    3 +-
- target/riscv/monitor.c                  |  11 +-
+ target/riscv/csr.c                    |    1 +
- target/riscv/op_helper.c                |   9 +
+ target/riscv/kvm-stub.c               |   30 -
- target/riscv/translate.c                |   8 +
+ target/riscv/{kvm.c => kvm/kvm-cpu.c} |  272 ++++++++-
- target/riscv/insn_trans/trans_rvb.c.inc | 116 ++++++++--
+ target/riscv/tcg/tcg-cpu.c            |  949 ++++++++++++++++++++++++++++++
- target/riscv/insn_trans/trans_rvk.c.inc | 391 ++++++++++++++++++++++++++++++++
+ target/riscv/vector_helper.c          |    2 +-
- crypto/meson.build                      |   1 +
+ target/riscv/kvm/meson.build          |    1 +
- hw/arm/meson.build                      |   1 -
+ target/riscv/meson.build              |    4 +-
- hw/core/meson.build                     |   1 +
+ target/riscv/tcg/meson.build          |    2 +
- hw/riscv/Kconfig                        |   2 +
+ tests/avocado/tuxrun_baselines.py     |   32 +
- target/riscv/meson.build                |   3 +-
+files changed, 1604 insertions(+), 891 deletions(-)
-files changed, 1682 insertions(+), 199 deletions(-)
+ rename target/riscv/{ => kvm}/kvm_riscv.h (95%)
- create mode 100644 include/crypto/sm4.h
+ create mode 100644 target/riscv/tcg/tcg-cpu.h
- rename include/hw/{arm => core}/sysbus-fdt.h (100%)
+ delete mode 100644 target/riscv/kvm-stub.c
- create mode 100644 crypto/sm4.c
+ rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (81%)
- rename hw/{arm => core}/sysbus-fdt.c (99%)
+ create mode 100644 target/riscv/tcg/tcg-cpu.c
- create mode 100644 target/riscv/crypto_helper.c
+ create mode 100644 target/riscv/kvm/meson.build
- create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
+ create mode 100644 target/riscv/tcg/meson.build

-New patch
+[PULL 01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+We'll add a new CPU type that will enable a considerable amount of
+extensions. To make it easier for us we'll do a few cleanups in our
+existing riscv_cpu_extensions[] array.
+Start by splitting all CPU non-boolean options from it. Create a new
+riscv_cpu_options[] array for them. Add all these properties in
+riscv_cpu_add_user_properties() as it is already being done today.
+'mmu' and 'pmp' aren't really extensions in the usual way we think about
+RISC-V extensions. These are closer to CPU features/options, so move
+both to riscv_cpu_options[] too. In the near future we'll need to match
+all extensions with all entries in isa_edata_arr[], and so it happens
+that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv
+spec version restriction). This further emphasizes the point that these
+are more a CPU option than an extension.
+No functional changes made.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
+file changed, 23 insertions(+), 10 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+ static Property riscv_cpu_extensions[] = {
+     /* Defaults for standard extensions */
+-    DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
+     DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
+     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+     DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
+     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+     DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
+-    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+-    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+     DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
+-    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+-    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+-    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+-    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+-
+     DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
+     DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
+     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+     DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+     DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
+-    DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
+     DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
+-    DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+     DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+     DEFINE_PROP_END_OF_LIST(),
+ };
++static Property riscv_cpu_options[] = {
++    DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
++
++    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
++    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
++
++    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
++    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
++
++    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
++    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
++
++    DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
++    DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
++};
+ #ifndef CONFIG_USER_ONLY
+ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+ #endif
+         qdev_property_add_static(dev, prop);
+     }
++
++    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
++        /* Check if KVM created the property already */
++        if (object_property_find(obj, riscv_cpu_options[i].name)) {
++            continue;
++        }
++        qdev_property_add_static(dev, &riscv_cpu_options[i]);
++    }
+ }
+ static Property riscv_cpu_properties[] = {
+--
+.41.0

-New patch
+[PULL 02/54] target/riscv/cpu.c: skip 'bool' check when filtering KVM props
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+After the introduction of riscv_cpu_options[] all properties in
+riscv_cpu_extensions[] are booleans. This check is now obsolete.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-3-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 14 ++++----------
+file changed, 4 insertions(+), 10 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+              * Set the default to disabled for every extension
+              * unknown to KVM and error out if the user attempts
+              * to enable any of them.
+-             *
+-             * We're giving a pass for non-bool properties since they're
+-             * not related to the availability of extensions and can be
+-             * safely ignored as is.
+              */
+-            if (prop->info == &qdev_prop_bool) {
+-                object_property_add(obj, prop->name, "bool",
+-                                    NULL, cpu_set_cfg_unavailable,
+-                                    NULL, (void *)prop->name);
+-                continue;
+-            }
++            object_property_add(obj, prop->name, "bool",
++                                NULL, cpu_set_cfg_unavailable,
++                                NULL, (void *)prop->name);
++            continue;
+         }
+ #endif
+         qdev_property_add_static(dev, prop);
+--
+.41.0

-New patch
+[PULL 03/54] target/riscv/cpu.c: split kvm prop handling to its own helper
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Future patches will split the existing Property arrays even further, and
+the existing code in riscv_cpu_add_user_properties() will start to scale
+bad with it because it's dealing with KVM constraints mixed in with TCG
+constraints. We're going to pay a high price to share a couple of common
+lines of code between the two.
+Create a new kvm_riscv_cpu_add_kvm_properties() helper that will be
+forked from riscv_cpu_add_user_properties() if we're running KVM. The
+helper includes all properties that a KVM CPU will add. The rest of
+riscv_cpu_add_user_properties() body will then be relieved from having
+to deal with KVM constraints.
+The helper was declared in kvm_stubs.h, while being implemented in
+cpu.c, to allow '--enable-debug' builds to work. The compiler won't
+remove the kvm_riscv_cpu_add_kvm_properties() reference when
+'kvm_enabled()' is false if we end up with an unused function. Even
+though being a KVM only helper we can't implement it in kvm.c due to its
+many dependencies inside cpu.c, so make it public in kvm_riscv.h and
+keep its implementation in cpu.c for now. We'll move it to kvm.c in the
+near future.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-4-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm_riscv.h |  3 ++
+ target/riscv/cpu.c       | 65 +++++++++++++++++++++++++---------------
+files changed, 44 insertions(+), 24 deletions(-)
+diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm_riscv.h
++++ b/target/riscv/kvm_riscv.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef QEMU_KVM_RISCV_H
+ #define QEMU_KVM_RISCV_H
++/* Temporarily implemented in cpu.c */
++void kvm_riscv_cpu_add_kvm_properties(Object *obj);
++
+ void kvm_riscv_init_user_properties(Object *cpu_obj);
+ void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+ void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
+     DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+ };
+-#ifndef CONFIG_USER_ONLY
++#ifdef CONFIG_KVM
+ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
+                                     const char *name,
+                                     void *opaque, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
+                    propname);
+     }
+ }
++
++static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
++{
++    /* Check if KVM created the property already */
++    if (object_property_find(obj, prop_name)) {
++        return;
++    }
++
++    /*
++     * Set the default to disabled for every extension
++     * unknown to KVM and error out if the user attempts
++     * to enable any of them.
++     */
++    object_property_add(obj, prop_name, "bool",
++                        NULL, cpu_set_cfg_unavailable,
++                        NULL, (void *)prop_name);
++}
++
++void kvm_riscv_cpu_add_kvm_properties(Object *obj)
++{
++    Property *prop;
++    DeviceState *dev = DEVICE(obj);
++
++    kvm_riscv_init_user_properties(obj);
++    riscv_cpu_add_misa_properties(obj);
++
++    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
++        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
++    }
++
++    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
++        /* Check if KVM created the property already */
++        if (object_property_find(obj, riscv_cpu_options[i].name)) {
++            continue;
++        }
++        qdev_property_add_static(dev, &riscv_cpu_options[i]);
++    }
++}
+ #endif
+ /*
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+     riscv_add_satp_mode_properties(obj);
+     if (kvm_enabled()) {
+-        kvm_riscv_init_user_properties(obj);
++        kvm_riscv_cpu_add_kvm_properties(obj);
++        return;
+     }
+ #endif
+     riscv_cpu_add_misa_properties(obj);
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+-#ifndef CONFIG_USER_ONLY
+-        if (kvm_enabled()) {
+-            /* Check if KVM created the property already */
+-            if (object_property_find(obj, prop->name)) {
+-                continue;
+-            }
+-
+-            /*
+-             * Set the default to disabled for every extension
+-             * unknown to KVM and error out if the user attempts
+-             * to enable any of them.
+-             */
+-            object_property_add(obj, prop->name, "bool",
+-                                NULL, cpu_set_cfg_unavailable,
+-                                NULL, (void *)prop->name);
+-            continue;
+-        }
+-#endif
+         qdev_property_add_static(dev, prop);
+     }
+     for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+-        /* Check if KVM created the property already */
+-        if (object_property_find(obj, riscv_cpu_options[i].name)) {
+-            continue;
+-        }
+         qdev_property_add_static(dev, &riscv_cpu_options[i]);
+     }
+ }
+--
+.41.0

-New patch
+[PULL 04/54] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
+iterating in the riscv_cpu_options[] array, making it similar to what
+we already do when working with riscv_cpu_extensions[].
+We also have a more sophisticated motivation behind this change. In the
+future we might need to export riscv_cpu_options[] to other files, and
+ARRAY_LIST() doesn't work properly in that case because the array size
+isn't exposed to the header file. Here's a future sight of what we would
+deal with:
+./target/riscv/kvm.c:1057:5: error: nested extern declaration of 'riscv_cpu_add_misa_properties' [-Werror=nested-externs]
+n file included from ../target/riscv/kvm.c:19:
+home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
+| #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
+     |                               ^
+./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
+|         for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
+     |                             ^~~~~~~~~~
+./target/riscv/kvm.c:1059:5: note: in expansion of macro 'ADD_UNAVAIL_KVM_PROP_ARRAY'
+|     ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions);
+     |     ^~~~~~~~~~~~~~~~~~~~~~~~~~
+home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
+| #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
+     |                               ^
+./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
+|         for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
+Homogenize the present and change the future by using
+DEFINE_PROP_END_OF_LIST() in riscv_cpu_options[].
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20230912132423.268494-5-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 12 +++++++-----
+file changed, 7 insertions(+), 5 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
+     DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
+     DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
++
++    DEFINE_PROP_END_OF_LIST(),
+ };
+ #ifdef CONFIG_KVM
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+     }
+-    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
++    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
+         /* Check if KVM created the property already */
+-        if (object_property_find(obj, riscv_cpu_options[i].name)) {
++        if (object_property_find(obj, prop->name)) {
+             continue;
+         }
+-        qdev_property_add_static(dev, &riscv_cpu_options[i]);
++        qdev_property_add_static(dev, prop);
+     }
+ }
+ #endif
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+         qdev_property_add_static(dev, prop);
+     }
+-    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+-        qdev_property_add_static(dev, &riscv_cpu_options[i]);
++    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
++        qdev_property_add_static(dev, prop);
+     }
+ }
+--
+.41.0

-New patch
+[PULL 05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Create a new riscv_cpu_experimental_exts[] to store the non-ratified
+extensions properties. Once they are ratified we'll move them back to
+riscv_cpu_extensions[].
+riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
+changed to keep adding non-ratified properties to users.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-6-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 13 ++++++++++++-
+file changed, 12 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
+     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
+-    /* These are experimental so mark with 'x-' */
++    DEFINE_PROP_END_OF_LIST(),
++};
++/* These are experimental so mark with 'x-' */
++static Property riscv_cpu_experimental_exts[] = {
+     /* ePMP 0.9.3 */
+     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+     DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+     }
++    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
++        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
++    }
++
+     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
+         /* Check if KVM created the property already */
+         if (object_property_find(obj, prop->name)) {
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
+         qdev_property_add_static(dev, prop);
+     }
++
++    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
++        qdev_property_add_static(dev, prop);
++    }
+ }
+ static Property riscv_cpu_properties[] = {
+--
+.41.0

-New patch
+[PULL 06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Our goal is to make riscv_cpu_extensions[] hold only ratified,
+non-vendor extensions.
+Create a new riscv_cpu_vendor_exts[] array for them, changing
+riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
+accordingly.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-7-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 13 ++++++++++++-
+file changed, 12 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+     DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
+-    /* Vendor-specific custom extensions */
++    DEFINE_PROP_END_OF_LIST(),
++};
++
++static Property riscv_cpu_vendor_exts[] = {
+     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
+     DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
+     DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+     }
++    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
++        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
++    }
++
+     for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
+         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+     }
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+         qdev_property_add_static(dev, prop);
+     }
++    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
++        qdev_property_add_static(dev, prop);
++    }
++
+     for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
+         qdev_property_add_static(dev, prop);
+     }
+--
+.41.0

-New patch
+[PULL 07/54] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+The code inside riscv_cpu_add_user_properties() became quite repetitive
+after recent changes. Add a helper to hide the repetition away.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20230912132423.268494-8-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 29 +++++++++++++----------------
+file changed, 13 insertions(+), 16 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
+     DEFINE_PROP_END_OF_LIST(),
+ };
++static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
++{
++    g_assert(array);
++
++    for (Property *prop = array; prop && prop->name; prop++) {
++        qdev_property_add_static(dev, prop);
++    }
++}
++
+ #ifdef CONFIG_KVM
+ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
+                                     const char *name,
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+  */
+ static void riscv_cpu_add_user_properties(Object *obj)
+ {
+-    Property *prop;
+     DeviceState *dev = DEVICE(obj);
+ #ifndef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+     riscv_cpu_add_misa_properties(obj);
+-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+-        qdev_property_add_static(dev, prop);
+-    }
+-
+-    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
+-        qdev_property_add_static(dev, prop);
+-    }
+-
+-    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
+-        qdev_property_add_static(dev, prop);
+-    }
+-
+-    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
+-        qdev_property_add_static(dev, prop);
+-    }
++    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
++    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
++    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
++    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
+ }
+ static Property riscv_cpu_properties[] = {
+--
+.41.0

-New patch
+[PULL 08/54] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
+code repetition.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230912132423.268494-9-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 24 +++++++++++++-----------
+file changed, 13 insertions(+), 11 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
+                         NULL, (void *)prop_name);
+ }
++static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
++                                                 Property *array)
++{
++    g_assert(array);
++
++    for (Property *prop = array; prop && prop->name; prop++) {
++        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
++    }
++}
++
+ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+ {
+     Property *prop;
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+     kvm_riscv_init_user_properties(obj);
+     riscv_cpu_add_misa_properties(obj);
+-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+-    }
+-
+-    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
+-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+-    }
+-
+-    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
+-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+-    }
++    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
++    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
++    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
+     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
+         /* Check if KVM created the property already */
+--
+.41.0

-New patch
+[PULL 09/54] target/riscv/cpu.c: limit cfg->vext_spec log message
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Inside riscv_cpu_validate_v() we're always throwing a log message if the
+user didn't set a vector version via 'vext_spec'.
+We're going to include one case with the 'max' CPU where env->vext_ver
+will be set in the cpu_init(). But that alone will not stop the "vector
+version is not specified" message from appearing. The usefulness of this
+log message is debatable for the generic CPUs, but for a 'max' CPU type,
+where we are supposed to deliver a CPU model with all features possible,
+it's strange to force users to set 'vext_spec' to get rid of this
+message.
+Change riscv_cpu_validate_v() to not throw this log message if
+env->vext_ver is already set.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Message-ID: <20230912132423.268494-10-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 9 ++++-----
+file changed, 4 insertions(+), 5 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+                                  Error **errp)
+ {
+-    int vext_version = VEXT_VERSION_1_00_0;
+-
+     if (!is_power_of_2(cfg->vlen)) {
+         error_setg(errp, "Vector extension VLEN must be power of 2");
+         return;
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+     }
+     if (cfg->vext_spec) {
+         if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
+-            vext_version = VEXT_VERSION_1_00_0;
++            env->vext_ver = VEXT_VERSION_1_00_0;
+         } else {
+             error_setg(errp, "Unsupported vector spec version '%s'",
+                        cfg->vext_spec);
+             return;
+         }
+-    } else {
++    } else if (env->vext_ver == 0) {
+         qemu_log("vector version is not specified, "
+                  "use the default value v1.0\n");
++
++        env->vext_ver = VEXT_VERSION_1_00_0;
+     }
+-    env->vext_ver = vext_version;
+ }
+ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
+--
+.41.0

-[PULL 22/25] hw/riscv: virt: Create a platform bus
+[PULL 10/54] target/riscv: add 'max' CPU type
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Create a platform bus to allow dynamic devices to be connected. This is
+The 'max' CPU type is used by tooling to determine what's the most
-based on the ARM implementation.
+capable CPU a current QEMU version implements. Other archs such as ARM
 implements this type. Let's add it to RISC-V.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+What we consider "most capable CPU" in this context are related to
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+ratified, non-vendor extensions. This means that we want the 'max' CPU
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+to enable all (possible) ratified extensions by default. The reasoning
-Message-Id: <20220427234146.1130752-4-alistair.francis@opensource.wdc.com>
+behind this design is (1) vendor extensions can conflict with each other
 and we won't play favorities deciding which one is default or not and
 (2) non-ratified extensions are always prone to changes, not being
 stable enough to be enabled by default.
 All this said, we're still not able to enable all ratified extensions
 due to conflicts between them. Zfinx and all its dependencies aren't
 enabled because of a conflict with RVF. zce, zcmp and zcmt are also
 disabled due to RVD conflicts. When running with 64 bits we're also
 disabling zcf.
 MISA bits RVG, RVJ and RVV are also being set manually since they're
 default disabled.
 This is the resulting 'riscv,isa' DT for this new CPU:
 rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
 zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
 zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
 smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230912132423.268494-11-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |  7 ++++-
+ target/riscv/cpu-qom.h |  1 +
- hw/riscv/virt.c         | 68 +++++++++++++++++++++++++++++------------
+ target/riscv/cpu.c     | 56 ++++++++++++++++++++++++++++++++++++++++++
- hw/riscv/Kconfig        |  1 +
+files changed, 57 insertions(+)
 files changed, 56 insertions(+), 20 deletions(-)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
+--- a/target/riscv/cpu-qom.h
-+++ b/include/hw/riscv/virt.h
++++ b/target/riscv/cpu-qom.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
+@@ -XXX,XX +XXX,XX @@
+ #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
-     /*< public >*/
-     Notifier machine_done;
+ #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
-+    DeviceState *platform_bus_dev;
++#define TYPE_RISCV_CPU_MAX              RISCV_CPU_TYPE_NAME("max")
-     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
+ #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
-     DeviceState *irqchip[VIRT_SOCKETS_MAX];
+ #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
-     PFlashCFI01 *flash[2];
+ #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
-@@ -XXX,XX +XXX,XX @@ enum {
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-     VIRT_DRAM,
+index XXXXXXX..XXXXXXX 100644
-     VIRT_PCIE_MMIO,
+--- a/target/riscv/cpu.c
-     VIRT_PCIE_PIO,
++++ b/target/riscv/cpu.c
-+    VIRT_PLATFORM_BUS,
+@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
      VIRT_PCIE_ECAM
  };
-@@ -XXX,XX +XXX,XX @@ enum {
+ static void riscv_cpu_add_user_properties(Object *obj);
-     VIRTIO_IRQ = 1, /* 1 to 8 */
++static void riscv_init_max_cpu_extensions(Object *obj);
-     VIRTIO_COUNT = 8,
-     PCIE_IRQ = 0x20, /* 32 to 35 */
+ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
--    VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
+ {
-+    VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
+@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
-+    VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
+     cpu->cfg.pmp = true;
- };
+ }
-+#define VIRT_PLATFORM_BUS_NUM_IRQS 32
++static void riscv_max_cpu_init(Object *obj)
 +{
 +    RISCVCPU *cpu = RISCV_CPU(obj);
 +    CPURISCVState *env = &cpu->env;
 +    RISCVMXL mlx = MXL_RV64;
 +
- #define VIRT_IRQCHIP_IPI_MSI 1
++#ifdef TARGET_RISCV32
- #define VIRT_IRQCHIP_NUM_MSIS 255
++    mlx = MXL_RV32;
- #define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
++#endif
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
++    set_misa(env, mlx, 0);
-index XXXXXXX..XXXXXXX 100644
++    riscv_cpu_add_user_properties(obj);
---- a/hw/riscv/virt.c
++    riscv_init_max_cpu_extensions(obj);
-+++ b/hw/riscv/virt.c
++    env->priv_ver = PRIV_VERSION_LATEST;
-@@ -XXX,XX +XXX,XX @@
++#ifndef CONFIG_USER_ONLY
- #include "hw/intc/riscv_imsic.h"
++    set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
- #include "hw/intc/sifive_plic.h"
++                                VM_1_10_SV32 : VM_1_10_SV57);
- #include "hw/misc/sifive_test.h"
++#endif
-+#include "hw/platform-bus.h"
++}
- #include "chardev/char.h"
++
- #include "sysemu/device_tree.h"
+ #if defined(TARGET_RISCV64)
- #include "sysemu/sysemu.h"
+ static void rv64_base_cpu_init(Object *obj)
-@@ -XXX,XX +XXX,XX @@
+ {
- #endif
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+     riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
  static const MemMapEntry virt_memmap[] = {
 -    [VIRT_DEBUG] =       {        0x0,         0x100 },
 -    [VIRT_MROM] =        {     0x1000,        0xf000 },
 -    [VIRT_TEST] =        {   0x100000,        0x1000 },
 -    [VIRT_RTC] =         {   0x101000,        0x1000 },
 -    [VIRT_CLINT] =       {  0x2000000,       0x10000 },
 -    [VIRT_ACLINT_SSWI] = {  0x2F00000,        0x4000 },
 -    [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
 -    [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
 -    [VIRT_APLIC_M] =     {  0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
 -    [VIRT_APLIC_S] =     {  0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
 -    [VIRT_UART0] =       { 0x10000000,         0x100 },
 -    [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
 -    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
 -    [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
 -    [VIRT_IMSIC_M] =     { 0x24000000, VIRT_IMSIC_MAX_SIZE },
 -    [VIRT_IMSIC_S] =     { 0x28000000, VIRT_IMSIC_MAX_SIZE },
 -    [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
 -    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
 -    [VIRT_DRAM] =        { 0x80000000,           0x0 },
 +    [VIRT_DEBUG] =        {        0x0,         0x100 },
 +    [VIRT_MROM] =         {     0x1000,        0xf000 },
 +    [VIRT_TEST] =         {   0x100000,        0x1000 },
 +    [VIRT_RTC] =          {   0x101000,        0x1000 },
 +    [VIRT_CLINT] =        {  0x2000000,       0x10000 },
 +    [VIRT_ACLINT_SSWI] =  {  0x2F00000,        0x4000 },
 +    [VIRT_PCIE_PIO] =     {  0x3000000,       0x10000 },
 +    [VIRT_PLATFORM_BUS] = {  0x4000000,     0x2000000 },
 +    [VIRT_PLIC] =         {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
 +    [VIRT_APLIC_M] =      {  0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
 +    [VIRT_APLIC_S] =      {  0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
 +    [VIRT_UART0] =        { 0x10000000,         0x100 },
 +    [VIRT_VIRTIO] =       { 0x10001000,        0x1000 },
 +    [VIRT_FW_CFG] =       { 0x10100000,          0x18 },
 +    [VIRT_FLASH] =        { 0x20000000,     0x4000000 },
 +    [VIRT_IMSIC_M] =      { 0x24000000, VIRT_IMSIC_MAX_SIZE },
 +    [VIRT_IMSIC_S] =      { 0x28000000, VIRT_IMSIC_MAX_SIZE },
 +    [VIRT_PCIE_ECAM] =    { 0x30000000,    0x10000000 },
 +    [VIRT_PCIE_MMIO] =    { 0x40000000,    0x40000000 },
 +    [VIRT_DRAM] =         { 0x80000000,           0x0 },
  };
  /* PCIe high mmio is fixed for RV32 */
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
      return aplic_m;
  }
-+static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
++/*
 + * The 'max' type CPU will have all possible ratified
 + * non-vendor extensions enabled.
 + */
 +static void riscv_init_max_cpu_extensions(Object *obj)
 +{
-+    DeviceState *dev;
++    RISCVCPU *cpu = RISCV_CPU(obj);
-+    SysBusDevice *sysbus;
++    CPURISCVState *env = &cpu->env;
-+    const MemMapEntry *memmap = virt_memmap;
++    Property *prop;
 +    int i;
 +    MemoryRegion *sysmem = get_system_memory();
 +
-+    dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
++    /* Enable RVG, RVJ and RVV that are disabled by default */
-+    dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
++    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 +    qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
 +    qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size);
 +    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 +    s->platform_bus_dev = dev;
 +
-+    sysbus = SYS_BUS_DEVICE(dev);
++    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-+    for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
++        object_property_set_bool(obj, prop->name, true, NULL);
 +        int irq = VIRT_PLATFORM_BUS_IRQ + i;
 +        sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
 +    }
 +
-+    memory_region_add_subregion(sysmem,
++    /* set vector version */
-+                                memmap[VIRT_PLATFORM_BUS].base,
++    env->vext_ver = VEXT_VERSION_1_00_0;
-+                                sysbus_mmio_get_region(sysbus, 0));
++
 +    /* Zfinx is not compatible with F. Disable it */
 +    object_property_set_bool(obj, "zfinx", false, NULL);
 +    object_property_set_bool(obj, "zdinx", false, NULL);
 +    object_property_set_bool(obj, "zhinx", false, NULL);
 +    object_property_set_bool(obj, "zhinxmin", false, NULL);
 +
 +    object_property_set_bool(obj, "zce", false, NULL);
 +    object_property_set_bool(obj, "zcmp", false, NULL);
 +    object_property_set_bool(obj, "zcmt", false, NULL);
 +
 +    if (env->misa_mxl != MXL_RV32) {
 +        object_property_set_bool(obj, "zcf", false, NULL);
 +    }
 +}
 +
- static void virt_machine_done(Notifier *notifier, void *data)
+ static Property riscv_cpu_properties[] = {
- {
+     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
-     RISCVVirtState *s = container_of(notifier, RISCVVirtState,
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
-                    memmap[VIRT_PCIE_PIO].base,
+         .abstract = true,
-                    DEVICE(pcie_irqchip));
+     },
+     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
-+    create_platform_bus(s, DEVICE(mmio_irqchip));
++    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,      riscv_max_cpu_init),
-+
+ #if defined(CONFIG_KVM)
-     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
+     DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
-, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
+ #endif
          serial_hd(0), DEVICE_LITTLE_ENDIAN);
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select SIFIVE_TEST
      select VIRTIO_MMIO
      select FW_CFG_DMA
 +    select PLATFORM_BUS
  config SIFIVE_E
      bool
 --
-.35.1
+.41.0

-New patch
+[PULL 11/54] avocado, risc-v: add tuxboot tests for 'max' CPU
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Add smoke tests to ensure that we'll not break the 'max' CPU type when
+adding new frozen/ratified RISC-V extensions.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20230912132423.268494-12-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ tests/avocado/tuxrun_baselines.py | 32 +++++++++++++++++++++++++++++++
+file changed, 32 insertions(+)
+diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/avocado/tuxrun_baselines.py
++++ b/tests/avocado/tuxrun_baselines.py
+@@ -XXX,XX +XXX,XX @@ def test_riscv64(self):
+         self.common_tuxrun(csums=sums)
++    def test_riscv32_maxcpu(self):
++        """
++        :avocado: tags=arch:riscv32
++        :avocado: tags=machine:virt
++        :avocado: tags=cpu:max
++        :avocado: tags=tuxboot:riscv32
++        """
++        sums = { "Image" :
++                 "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
++                 "fw_jump.elf" :
++                 "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
++                 "rootfs.ext4.zst" :
++                 "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
++
++        self.common_tuxrun(csums=sums)
++
++    def test_riscv64_maxcpu(self):
++        """
++        :avocado: tags=arch:riscv64
++        :avocado: tags=machine:virt
++        :avocado: tags=cpu:max
++        :avocado: tags=tuxboot:riscv64
++        """
++        sums = { "Image" :
++                 "cd634badc65e52fb63465ec99e309c0de0369f0841b7d9486f9729e119bac25e",
++                 "fw_jump.elf" :
++                 "6e3373abcab4305fe151b564a4c71110d833c21f2c0a1753b7935459e36aedcf",
++                 "rootfs.ext4.zst" :
++                 "b18e3a3bdf27be03da0b285e84cb71bf09eca071c3a087b42884b6982ed679eb" }
++
++        self.common_tuxrun(csums=sums)
++
+     def test_s390(self):
+         """
+         :avocado: tags=arch:s390x
+--
+.41.0

-New patch
+[PULL 12/54] target/riscv: deprecate the 'any' CPU type
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
+Core Definition"), being around since the beginning. It's not an easy
+CPU to use: it's undocumented and its name doesn't tell users much about
+what the CPU is supposed to bring. 'git log' doesn't help us either in
+knowing what was the original design of this CPU type.
+The closest we have is a comment from Alistair [1] where he recalls from
+memory that the 'any' CPU is supposed to behave like the newly added
+'max' CPU. He also suggested that the 'any' CPU should be removed.
+The default CPUs are rv32 and rv64, so removing the 'any' CPU will have
+impact only on users that might have a script that uses '-cpu any'.
+And those users are better off using the default CPUs or the new 'max'
+CPU.
+We would love to just remove the code and be done with it, but one does
+not simply remove a feature in QEMU. We'll put the CPU in quarantine
+first, letting users know that we have the intent of removing it in the
+future.
+[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20230912132423.268494-13-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ docs/about/deprecated.rst | 12 ++++++++++++
+ target/riscv/cpu.c        |  5 +++++
+files changed, 17 insertions(+)
+diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/about/deprecated.rst
++++ b/docs/about/deprecated.rst
+@@ -XXX,XX +XXX,XX @@ QEMU's ``vhost`` feature, which would eliminate the high latency costs under
+ which the 9p ``proxy`` backend currently suffers. However as of to date nobody
+ has indicated plans for such kind of reimplementation unfortunately.
++RISC-V 'any' CPU type ``-cpu any`` (since 8.2)
++^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
++
++The 'any' CPU type was introduced back in 2018 and has been around since the
++initial RISC-V QEMU port. Its usage has always been unclear: users don't know
++what to expect from a CPU called 'any', and in fact the CPU does not do anything
++special that isn't already done by the default CPUs rv32/rv64.
++
++After the introduction of the 'max' CPU type, RISC-V now has a good coverage
++of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete
++CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any'
++CPU type starting in 8.2.
+ Block device options
+ ''''''''''''''''''''
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+     Error *local_err = NULL;
++    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
++        warn_report("The 'any' CPU is deprecated and will be "
++                    "removed in the future.");
++    }
++
+     cpu_exec_realizefn(cs, &local_err);
+     if (local_err != NULL) {
+         error_propagate(errp, local_err);
+--
+.41.0

-New patch
+[PULL 13/54] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+We'll have future usage for a function where, given an offset of the
+struct RISCVCPUConfig, the flag is updated to a certain val.
+Change all existing callers to use edata->ext_enable_offset instead of
+'edata'.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-14-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 18 +++++++++---------
+file changed, 9 insertions(+), 9 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+ };
+-static bool isa_ext_is_enabled(RISCVCPU *cpu,
+-                               const struct isa_ext_data *edata)
++static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
+ {
+-    bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
++    bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
+     return *ext_enabled;
+ }
+-static void isa_ext_update_enabled(RISCVCPU *cpu,
+-                                   const struct isa_ext_data *edata, bool en)
++static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
++                                   bool en)
+ {
+-    bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
++    bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
+     *ext_enabled = en;
+ }
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+     /* Force disable extensions if priv spec version does not match */
+     for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+-        if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
++        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
+             (env->priv_ver < isa_edata_arr[i].min_version)) {
+-            isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
++            isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
++                                   false);
+ #ifndef CONFIG_USER_ONLY
+             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
+                         " because privilege spec version does not match",
+@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
+     int i;
+     for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+-        if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
++        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
+             new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
+             g_free(old);
+             old = new;
+--
+.41.0

-New patch
+[PULL 14/54] target/riscv: make CPUCFG() macro public
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
+of a certain field in the struct RISCVCPUConfig. We're going to use this
+macro in target/riscv/cpu.c as well in the next patches. Make it public.
+Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20230912132423.268494-15-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h | 2 ++
+ target/riscv/cpu.c | 2 +-
+ target/riscv/kvm.c | 8 +++-----
+files changed, 6 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@
+ const char *riscv_get_misa_ext_name(uint32_t bit);
+ const char *riscv_get_misa_ext_description(uint32_t bit);
++#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
++
+ /* Privileged specification version */
+ enum {
+     PRIV_VERSION_1_10_0 = 0,
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
+ };
+ #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
+-    {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
++    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
+ /*
+  * From vector_helper.c
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm.c
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
+     }
+ }
+-#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop)
+-
+ #define KVM_EXT_CFG(_name, _prop, _reg_id) \
+-    {.name = _name, .offset = CPUCFG(_prop), \
++    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
+      .kvm_reg_id = _reg_id}
+ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
+@@ -XXX,XX +XXX,XX @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v,
+ static KVMCPUConfig kvm_cbom_blocksize = {
+     .name = "cbom_blocksize",
+-    .offset = CPUCFG(cbom_blocksize),
++    .offset = CPU_CFG_OFFSET(cbom_blocksize),
+     .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)
+ };
+ static KVMCPUConfig kvm_cboz_blocksize = {
+     .name = "cboz_blocksize",
+-    .offset = CPUCFG(cboz_blocksize),
++    .offset = CPU_CFG_OFFSET(cboz_blocksize),
+     .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)
+ };
+--
+.41.0

-New patch
+[PULL 15/54] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+During realize() time we're activating a lot of extensions based on some
+criteria, e.g.:
+    if (cpu->cfg.ext_zk) {
+        cpu->cfg.ext_zkn = true;
+        cpu->cfg.ext_zkr = true;
+        cpu->cfg.ext_zkt = true;
+    }
+This practice resulted in at least one case where we ended up enabling
+something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that
+has priv_spec older than 1.12.0.
+We're also not considering user choice. There's no way of doing it now
+but this is about to change in the next few patches.
+cpu_cfg_ext_auto_update() will check for priv version mismatches before
+enabling extensions. If we have a mismatch between the current priv
+version and the extension we want to enable, do not enable it. In the
+near future, this same function will also consider user choice when
+deciding if we're going to enable/disable an extension or not.
+For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-16-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++++++++++---
+file changed, 40 insertions(+), 3 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
+     *ext_enabled = en;
+ }
++static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
++{
++    int i;
++
++    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
++        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
++            continue;
++        }
++
++        return isa_edata_arr[i].min_version;
++    }
++
++    g_assert_not_reached();
++}
++
++static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
++                                    bool value)
++{
++    CPURISCVState *env = &cpu->env;
++    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
++    int min_version;
++
++    if (prev_val == value) {
++        return;
++    }
++
++    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
++        /* Do not enable it if priv_ver is older than min_version */
++        min_version = cpu_cfg_ext_get_min_version(ext_offset);
++        if (env->priv_ver < min_version) {
++            return;
++        }
++    }
++
++    isa_ext_update_enabled(cpu, ext_offset, value);
++}
++
+ const char * const riscv_int_regnames[] = {
+     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
+     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+     /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
+     if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
+-        cpu->cfg.ext_zca = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+-            cpu->cfg.ext_zcf = true;
++            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+         }
+         if (riscv_has_ext(env, RVD)) {
+-            cpu->cfg.ext_zcd = true;
++            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
+         }
+     }
+--
+.41.0

-New patch
+[PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Let's change the other instances in realize() where we're enabling an
+extension based on a certain criteria (e.g. it's a dependency of another
+extension).
+We're leaving icsr and ifencei being enabled during RVG for later -
+we'll want to error out in that case. Every other extension enablement
+during realize is now done via cpu_cfg_ext_auto_update().
+The end goal is that only cpu init() functions will handle extension
+flags directly via "cpu->cfg.ext_N = true|false".
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-17-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 50 +++++++++++++++++++++++-----------------------
+file changed, 25 insertions(+), 25 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+     }
+     if (cpu->cfg.ext_zfh) {
+-        cpu->cfg.ext_zfhmin = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
+     }
+     if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+         }
+         /* The V vector extension depends on the Zve64d extension */
+-        cpu->cfg.ext_zve64d = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
+     }
+     /* The Zve64d extension depends on the Zve64f extension */
+     if (cpu->cfg.ext_zve64d) {
+-        cpu->cfg.ext_zve64f = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
+     }
+     /* The Zve64f extension depends on the Zve32f extension */
+     if (cpu->cfg.ext_zve64f) {
+-        cpu->cfg.ext_zve32f = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
+     }
+     if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+     }
+     if (cpu->cfg.ext_zvfh) {
+-        cpu->cfg.ext_zvfhmin = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
+     }
+     if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+     /* Set the ISA extensions, checks should have happened above */
+     if (cpu->cfg.ext_zhinx) {
+-        cpu->cfg.ext_zhinxmin = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+     }
+     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+     }
+     if (cpu->cfg.ext_zce) {
+-        cpu->cfg.ext_zca = true;
+-        cpu->cfg.ext_zcb = true;
+-        cpu->cfg.ext_zcmp = true;
+-        cpu->cfg.ext_zcmt = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
+         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+-            cpu->cfg.ext_zcf = true;
++            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+     }
+     if (cpu->cfg.ext_zk) {
+-        cpu->cfg.ext_zkn = true;
+-        cpu->cfg.ext_zkr = true;
+-        cpu->cfg.ext_zkt = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
+     }
+     if (cpu->cfg.ext_zkn) {
+-        cpu->cfg.ext_zbkb = true;
+-        cpu->cfg.ext_zbkc = true;
+-        cpu->cfg.ext_zbkx = true;
+-        cpu->cfg.ext_zkne = true;
+-        cpu->cfg.ext_zknd = true;
+-        cpu->cfg.ext_zknh = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
+     }
+     if (cpu->cfg.ext_zks) {
+-        cpu->cfg.ext_zbkb = true;
+-        cpu->cfg.ext_zbkc = true;
+-        cpu->cfg.ext_zbkx = true;
+-        cpu->cfg.ext_zksed = true;
+-        cpu->cfg.ext_zksh = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
+     }
+     /*
+--
+.41.0

-[PULL 02/25] hw/riscv: Don't add empty bootargs to device tree
+[PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
+If we want to make better decisions when auto-enabling extensions during
-tried to avoid adding *NULL* bootargs to device tree, but unfortunately
+realize() we need a way to tell if an user set an extension manually.
-the changes were entirely useless, due to MachineState::kernel_cmdline
+The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
-can't be NULL at all as the default value is given as an empty string.
+that has an 'user_set' flag that is set during the Property set()
-(see hw/core/machine.c::machine_initfn()).
+callback. The set() callback also does init() time validations based on
+the current KVM driver capabilities.
-Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise
-a segfault had already been observed by dereferencing the NULL pointer.
+For TCG we would want a 'user_set' mechanic too, but we would look
-It should be worded as *empty" bootargs.
+ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set
+or not. If we copy what was made in the KVM side we would look for
-Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
+'user_set' for one into 60+ extension structs spreaded in 3 arrays
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+(riscv_cpu_extensions, riscv_cpu_experimental_exts,
 riscv_cpu_vendor_exts).
 We'll still need an extension struct but we won't be using the
 'user_set' flag:
 - 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to what
 we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'.
 DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by
 MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct;
 - the 'multi_ext_user_opts' hash will be used to store the offset of each
 extension that the user set via the set() callback, cpu_set_multi_ext_cfg().
 For now we're just initializing and populating it - next patch will use
 it to determine if a certain extension was user set;
 - cpu_add_multi_ext_prop() is a new helper that will replace the
 qdev_property_add_static() calls that our macros are doing to populate
 user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY()
 for clarity. Note that the non-extension properties in
 riscv_cpu_options[] still need to be declared via qdev().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220421055629.1177285-2-bmeng.cn@gmail.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230912132423.268494-18-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/microchip_pfsoc.c | 2 +-
+ target/riscv/cpu.c | 258 ++++++++++++++++++++++++++++-----------------
- hw/riscv/sifive_u.c        | 2 +-
+file changed, 159 insertions(+), 99 deletions(-)
- hw/riscv/spike.c           | 2 +-
- hw/riscv/virt.c            | 2 +-
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 files changed, 4 insertions(+), 4 deletions(-)
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
+--- a/target/riscv/cpu.c
-+++ b/hw/riscv/microchip_pfsoc.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-                                   "linux,initrd-end", end);
+     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
-         }
+ };
--        if (machine->kernel_cmdline) {
++/* Hash that stores user set extensions */
-+        if (machine->kernel_cmdline && *machine->kernel_cmdline) {
++static GHashTable *multi_ext_user_opts;
-             qemu_fdt_setprop_string(machine->fdt, "/chosen",
++
-                                     "bootargs", machine->kernel_cmdline);
+ static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
-         }
+ {
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
---- a/hw/riscv/sifive_u.c
+     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
-+++ b/hw/riscv/sifive_u.c
+                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
+ #endif /* CONFIG_USER_ONLY */
-     g_free(nodename);
++
++    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
- update_bootargs:
+ }
--    if (cmdline) {
-+    if (cmdline && *cmdline) {
+ typedef struct RISCVCPUMisaExtConfig {
-         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
      }
  }
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
+-static Property riscv_cpu_extensions[] = {
---- a/hw/riscv/spike.c
++typedef struct RISCVCPUMultiExtConfig {
-+++ b/hw/riscv/spike.c
++    const char *name;
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
++    uint32_t offset;
-     qemu_fdt_add_subnode(fdt, "/chosen");
++    bool enabled;
-     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
++} RISCVCPUMultiExtConfig;
++
--    if (cmdline) {
++#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
-+    if (cmdline && *cmdline) {
++    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
-         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
++     .enabled = _defval}
 +
 +static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      /* Defaults for standard extensions */
 -    DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
 -    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 -    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 -    DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true),
 -    DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
 -    DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
 -    DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true),
 -    DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
 -    DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
 -    DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
 -    DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
 -    DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
 -    DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
 -
 -    DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
 -    DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
 -    DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
 -    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
 -    DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
 -
 -    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
 -    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
 -    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
 -    DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
 -    DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
 -    DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
 -    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
 -    DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
 -    DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
 -    DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
 -    DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
 -    DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
 -    DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
 -    DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
 -    DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
 -    DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
 -    DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
 -
 -    DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
 -    DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
 -    DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
 -    DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
 -
 -    DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
 -    DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
 -
 -    DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
 -
 -    DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
 -    DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
 -    DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
 -    DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
 -    DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
 -    DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
 -    DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
 -    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
 +    MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
 +    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
 +    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
 +    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
 +    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
 +    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
 +    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
 +    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
 +    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
 +    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
 +    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
 +    MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
 +
 +    MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
 +    MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
 +    MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
 +    MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
 +    MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
 +
 +    MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
 +    MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
 +    MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
 +    MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
 +    MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
 +    MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
 +    MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
 +    MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
 +    MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
 +    MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
 +    MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
 +    MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
 +    MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
 +    MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
 +    MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
 +    MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
 +    MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
 +
 +    MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
 +    MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
 +    MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
 +    MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
 +
 +    MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
 +    MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
 +
 +    MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
 +
 +    MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
 +    MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
 +    MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
 +    MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
 +    MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
 +    MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
 +    MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
 +    MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
      DEFINE_PROP_END_OF_LIST(),
  };
 -static Property riscv_cpu_vendor_exts[] = {
 -    DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
 -    DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
 -    DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
 -    DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
 -    DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
 -    DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
 -    DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
 -    DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
 -    DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
 -    DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
 -    DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
 -    DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 +static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 +    MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
 +    MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
 +    MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
 +    MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
 +    MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
 +    MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
 +    MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
 +    MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
 +    MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
 +    MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
 +    MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
 +    MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
      DEFINE_PROP_END_OF_LIST(),
  };
  /* These are experimental so mark with 'x-' */
 -static Property riscv_cpu_experimental_exts[] = {
 +static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
      /* ePMP 0.9.3 */
 -    DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 -    DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
 -    DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
 +    MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
 +    MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
 +    MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
 -    DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
 -    DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
 +    MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
 +    MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
 -    DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
 -    DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
 -    DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
 +    MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
 +    MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
 +    MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
      /* Vector cryptography extensions */
 -    DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
 -    DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
 -    DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false),
 -    DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
 -    DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
 -    DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
 -    DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false),
 -    DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
 +    MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
 +    MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
 +    MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
 +    MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
 +    MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
 +    MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
 +    MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
 +    MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
 -static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
 +static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 +                                  void *opaque, Error **errp)
 +{
 +    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 +    bool value;
 +
 +    if (!visit_type_bool(v, name, &value, errp)) {
 +        return;
 +    }
 +
 +    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
 +
 +    g_hash_table_insert(multi_ext_user_opts,
 +                        GUINT_TO_POINTER(multi_ext_cfg->offset),
 +                        (gpointer)value);
 +}
 +
 +static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 +                                  void *opaque, Error **errp)
 +{
 +    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 +    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
 +
 +    visit_type_bool(v, name, &value, errp);
 +}
 +
 +static void cpu_add_multi_ext_prop(Object *cpu_obj,
 +                                   RISCVCPUMultiExtConfig *multi_cfg)
 +{
 +    object_property_add(cpu_obj, multi_cfg->name, "bool",
 +                        cpu_get_multi_ext_cfg,
 +                        cpu_set_multi_ext_cfg,
 +                        NULL, (void *)multi_cfg);
 +
 +    /*
 +     * Set def val directly instead of using
 +     * object_property_set_bool() to save the set()
 +     * callback hash for user inputs.
 +     */
 +    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
 +                           multi_cfg->enabled);
 +}
 +
 +static void riscv_cpu_add_multiext_prop_array(Object *obj,
 +                                              RISCVCPUMultiExtConfig *array)
  {
      g_assert(array);
 -    for (Property *prop = array; prop && prop->name; prop++) {
 -        qdev_property_add_static(dev, prop);
 +    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
 +        cpu_add_multi_ext_prop(obj, prop);
      }
  }
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
---- a/hw/riscv/virt.c
+ }
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+ static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-     create_fdt_flash(s, memmap);
+-                                                 Property *array)
++                                                 RISCVCPUMultiExtConfig *array)
- update_bootargs:
+ {
--    if (cmdline) {
+     g_assert(array);
-+    if (cmdline && *cmdline) {
-         qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
+-    for (Property *prop = array; prop && prop->name; prop++) {
 +    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
          riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
      }
  }
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+  */
+ static void riscv_cpu_add_user_properties(Object *obj)
+ {
+-    DeviceState *dev = DEVICE(obj);
+-
+ #ifndef CONFIG_USER_ONLY
+     riscv_add_satp_mode_properties(obj);
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
+     riscv_cpu_add_misa_properties(obj);
+-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
+-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
+-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
+-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
++    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
++    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
++    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
++
++    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
++        qdev_property_add_static(DEVICE(obj), prop);
++    }
+ }
+ /*
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
+ {
+     RISCVCPU *cpu = RISCV_CPU(obj);
+     CPURISCVState *env = &cpu->env;
+-    Property *prop;
++    RISCVCPUMultiExtConfig *prop;
+     /* Enable RVG, RVJ and RVV that are disabled by default */
+     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 --
-.35.1
+.41.0

-[PULL 01/25] hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
+[PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-At present the adding '/chosen/stdout-path' property in device tree
+Before adding support to detect if an extension was user set we need to
-is determined by whether a kernel command line is provided, which is
+handle how we're enabling extensions in riscv_init_max_cpu_extensions().
-wrong. It should be added unconditionally.
+object_property_set_bool() calls the set() callback for the property,
 and we're going to use this callback to set the 'multi_ext_user_opts'
 hash.
-Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
+This means that, as is today, all extensions we're setting for the 'max'
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+CPU will be seen as user set in the future. Let's change set_bool() to
 isa_ext_update_enabled() that will just enable/disable the flag on a
 certain offset.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220421055629.1177285-1-bmeng.cn@gmail.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230912132423.268494-19-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/spike.c | 5 +++--
+ target/riscv/cpu.c | 18 +++++++++---------
-file changed, 3 insertions(+), 2 deletions(-)
+file changed, 9 insertions(+), 9 deletions(-)
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
+--- a/target/riscv/cpu.c
-+++ b/hw/riscv/spike.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
+     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-     riscv_socket_fdt_write_distance_matrix(mc, fdt);
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-+    qemu_fdt_add_subnode(fdt, "/chosen");
+-        object_property_set_bool(obj, prop->name, true, NULL);
-+    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
++        isa_ext_update_enabled(cpu, prop->offset, true);
-+
+     }
-     if (cmdline) {
--        qemu_fdt_add_subnode(fdt, "/chosen");
+     /* set vector version */
-         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+     env->vext_ver = VEXT_VERSION_1_00_0;
--        qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
      /* Zfinx is not compatible with F. Disable it */
 -    object_property_set_bool(obj, "zfinx", false, NULL);
 -    object_property_set_bool(obj, "zdinx", false, NULL);
 -    object_property_set_bool(obj, "zhinx", false, NULL);
 -    object_property_set_bool(obj, "zhinxmin", false, NULL);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
 -    object_property_set_bool(obj, "zce", false, NULL);
 -    object_property_set_bool(obj, "zcmp", false, NULL);
 -    object_property_set_bool(obj, "zcmt", false, NULL);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
 +    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
      if (env->misa_mxl != MXL_RV32) {
 -        object_property_set_bool(obj, "zcf", false, NULL);
 +        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
      }
  }
 --
-.35.1
+.41.0

-New patch
+[PULL 19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
+set by the user in the command line. Use it inside
+cpu_cfg_ext_auto_update() to verify if the user set a certain extension
+and, if that's the case, do not change its value.
+This will make us honor user choice instead of overwriting the values.
+Users will then be informed whether they're using an incompatible set of
+extensions instead of QEMU setting a magic value that works.
+The reason why we're not implementing user choice for MISA extensions
+right now is because, today, we do not silently change any MISA bit
+during realize() time (we do warn when enabling bits if RVG is enabled).
+We do that - a lot - with multi-letter extensions though, so we're
+handling the most immediate concern first.
+After this patch, we'll now error out if the user explicitly set 'zce' to true
+and 'zca' to false:
+$ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=true,zca=false -nographic
+qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension
+This didn't happen before because we were enabling 'zca' if 'zce' was enabled
+regardless if the user set 'zca' to false.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20230912132423.268494-20-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 16 ++++++++++++++++
+file changed, 16 insertions(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+     g_assert_not_reached();
+ }
++static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
++{
++    return g_hash_table_contains(multi_ext_user_opts,
++                                 GUINT_TO_POINTER(ext_offset));
++}
++
+ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
+                                     bool value)
+ {
+@@ -XXX,XX +XXX,XX @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
+         return;
+     }
++    if (cpu_cfg_ext_is_user_set(ext_offset)) {
++        return;
++    }
++
+     if (value && env->priv_ver != PRIV_VERSION_LATEST) {
+         /* Do not enable it if priv_ver is older than min_version */
+         min_version = cpu_cfg_ext_get_min_version(ext_offset);
+@@ -XXX,XX +XXX,XX @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+     MISA_CFG(RVG, false),
+ };
++/*
++ * We do not support user choice tracking for MISA
++ * extensions yet because, so far, we do not silently
++ * change MISA bits during realize() (RVG enables MISA
++ * bits but the user is warned about it).
++ */
+ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+ {
+     int i;
+--
+.41.0

-[PULL 19/25] target/riscv: add scalar crypto related extenstion strings to isa_string
+[PULL 20/54] target/riscv/cpu.c: consider user option with RVG
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - add zbk* and zk* strings to isa_edata_arr
+Enabling RVG will enable a set of extensions that we're not checking if
 the user was okay enabling or not. And in this case we want to error
 out, instead of ignoring, otherwise we will be inconsistent enabling RVG
 without all its extensions.
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+After this patch, disabling ifencei or icsr while enabling RVG will
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+result in error:
-Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
 $ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false --nographic
 qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220426095204.24142-1-liweiwei@iscas.ac.cn>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20230912132423.268494-21-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 13 +++++++++++++
+ target/riscv/cpu.c | 18 ++++++++++++++++--
-file changed, 13 insertions(+)
+file changed, 16 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-         ISA_EDATA_ENTRY(zba, ext_zba),
+           riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
-         ISA_EDATA_ENTRY(zbb, ext_zbb),
+           riscv_has_ext(env, RVD) &&
-         ISA_EDATA_ENTRY(zbc, ext_zbc),
+           cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
-+        ISA_EDATA_ENTRY(zbkb, ext_zbkb),
++
-+        ISA_EDATA_ENTRY(zbkc, ext_zbkc),
++        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
-+        ISA_EDATA_ENTRY(zbkx, ext_zbkx),
++            !cpu->cfg.ext_icsr) {
-         ISA_EDATA_ENTRY(zbs, ext_zbs),
++            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
-+        ISA_EDATA_ENTRY(zk, ext_zk),
++            return;
-+        ISA_EDATA_ENTRY(zkn, ext_zkn),
++        }
-+        ISA_EDATA_ENTRY(zknd, ext_zknd),
++
-+        ISA_EDATA_ENTRY(zkne, ext_zkne),
++        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
-+        ISA_EDATA_ENTRY(zknh, ext_zknh),
++            !cpu->cfg.ext_ifencei) {
-+        ISA_EDATA_ENTRY(zkr, ext_zkr),
++            error_setg(errp, "RVG requires Zifencei but user set "
-+        ISA_EDATA_ENTRY(zks, ext_zks),
++                       "Zifencei to false");
-+        ISA_EDATA_ENTRY(zksed, ext_zksed),
++            return;
-+        ISA_EDATA_ENTRY(zksh, ext_zksh),
++        }
-+        ISA_EDATA_ENTRY(zkt, ext_zkt),
++
-         ISA_EDATA_ENTRY(zve32f, ext_zve32f),
+         warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
-         ISA_EDATA_ENTRY(zve64f, ext_zve64f),
+-        cpu->cfg.ext_icsr = true;
-         ISA_EDATA_ENTRY(svinval, ext_svinval),
+-        cpu->cfg.ext_ifencei = true;
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
          env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
          env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
 --
-.35.1
+.41.0

-[PULL 10/25] target/riscv: rvk: add support for zkne/zknd extension in RV64
+[PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: "liguang.zhang" <liguang.zhang@hexintek.com>
- - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions
+This patch fixes guest reboot errors when using KVM.
-Co-authored-by: Ruibo Lu <luruibo2000@163.com>
+There are two issues when rebooting a guest using KVM
-Co-authored-by: Zewen Ye <lustrew@foxmail.com>
+. When the guest initiates a reboot the host is unable to stop the vcpu
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+. When running a SMP guest the qemu monitor system_reset causes a vcpu crash
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+This can be fixed by clearing the CSR values at reset and syncing the
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+MPSTATE with the host.
-Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn>
 Signed-off-by: liguang.zhang <liguang.zhang@hexintek.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20230913091332.17355-1-18622748025@163.com>
 [ Changes by AF
  - Fixup commit message
  - Fixup patch style
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |   8 ++
+ target/riscv/kvm_riscv.h |  1 +
- target/riscv/insn32.decode              |  12 ++
+ target/riscv/kvm.c       | 44 ++++++++++++++++++++++++++++++++++++++++
- target/riscv/crypto_helper.c            | 169 ++++++++++++++++++++++++
+files changed, 45 insertions(+)
  target/riscv/insn_trans/trans_rvk.c.inc |  54 ++++++++
 files changed, 243 insertions(+)
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/target/riscv/kvm_riscv.h
-+++ b/target/riscv/helper.h
++++ b/target/riscv/kvm_riscv.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
- DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+                           uint64_t aplic_base, uint64_t imsic_base,
- DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+                           uint64_t guest_num);
- DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+ void riscv_kvm_aplic_request(void *opaque, int irq, int level);
 +int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state);
  #endif
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void riscv_kvm_aplic_request(void *opaque, int irq, int level)
      kvm_set_irq(kvm_state, irq, !!level);
  }
 +static bool cap_has_mp_state;
 +
-+DEF_HELPER_FLAGS_2(aes64esm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
-+DEF_HELPER_FLAGS_2(aes64es, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+                                  uint64_t idx)
 +DEF_HELPER_FLAGS_2(aes64ds, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 +DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 +DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 +DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 +DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
  %imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
  %imm_u    12:s20                 !function=ex_shift_12
  %imm_bs   30:2                   !function=ex_shift_3
 +%imm_rnum 20:4
  # Argument sets:
  &empty
@@ -XXX,XX +XXX,XX @@
  @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
  @k_aes   .. ..... ..... .....  ... ..... ....... &k_aes  shamt=%imm_bs   %rs2 %rs1 %rd
 +@i_aes   .. ..... ..... .....  ... ..... ....... &i      imm=%imm_rnum        %rs1 %rd
  # Formats 64:
  @sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
@@ -XXX,XX +XXX,XX @@ hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
  # *** RV32 Zknd Standard Extension ***
  aes32dsmi   .. 10111 ..... ..... 000 ..... 0110011 @k_aes
  aes32dsi    .. 10101 ..... ..... 000 ..... 0110011 @k_aes
 +# *** RV64 Zknd Standard Extension ***
 +aes64dsm    00 11111 ..... ..... 000 ..... 0110011 @r
 +aes64ds     00 11101 ..... ..... 000 ..... 0110011 @r
 +aes64im     00 11000 00000 ..... 001 ..... 0010011 @r2
  # *** RV32 Zkne Standard Extension ***
  aes32esmi   .. 10011 ..... ..... 000 ..... 0110011 @k_aes
  aes32esi    .. 10001 ..... ..... 000 ..... 0110011 @k_aes
 +# *** RV64 Zkne Standard Extension ***
 +aes64es     00 11001 ..... ..... 000 ..... 0110011 @r
 +aes64esm    00 11011 ..... ..... 000 ..... 0110011 @r
 +# *** RV64 Zkne/zknd Standard Extension ***
 +aes64ks2    01 11111 ..... ..... 000 ..... 0110011 @r
 +aes64ks1i   00 11000 1.... ..... 001 ..... 0010011 @i_aes
 diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/crypto_helper.c
 +++ b/target/riscv/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
  {
-     return aes32_operation(shamt, rs1, rs2, false, false);
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
      return ret;
  }
++int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state)
++{
++    if (cap_has_mp_state) {
++        struct kvm_mp_state mp_state = {
++            .mp_state = state
++        };
 +
-+#define BY(X, I) ((X >> (8 * I)) & 0xFF)
++        int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
-+
++        if (ret) {
-+#define AES_SHIFROWS_LO(RS1, RS2) ( \
++            fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n",
-+    (((RS1 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
++                    __func__, ret, strerror(-ret));
-+    (((RS2 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
++            return -1;
 +    (((RS2 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
 +    (((RS1 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
 +
 +#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
 +    (((RS2 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
 +    (((RS1 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
 +    (((RS1 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
 +    (((RS2 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
 +
 +#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
 +    BY(COL, B3) ^ BY(COL, B2) ^ AES_GFMUL(BY(COL, B1), 3) ^ \
 +    AES_GFMUL(BY(COL, B0), 2))
 +
 +#define AES_MIXCOLUMN(COL) ( \
 +    AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
 +    AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
 +    AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | AES_MIXBYTE(COL, 0, 1, 2, 3) << 0)
 +
 +#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
 +    AES_GFMUL(BY(COL, B3), 0x9) ^ AES_GFMUL(BY(COL, B2), 0xd) ^ \
 +    AES_GFMUL(BY(COL, B1), 0xb) ^ AES_GFMUL(BY(COL, B0), 0xe))
 +
 +#define AES_INVMIXCOLUMN(COL) ( \
 +    AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
 +    AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
 +    AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
 +    AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0)
 +
 +static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
 +                                           bool enc, bool mix)
 +{
 +    uint64_t RS1 = rs1;
 +    uint64_t RS2 = rs2;
 +    uint64_t result;
 +    uint64_t temp;
 +    uint32_t col_0;
 +    uint32_t col_1;
 +
 +    if (enc) {
 +        temp = AES_SHIFROWS_LO(RS1, RS2);
 +        temp = (((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
 +                ((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
 +                ((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
 +                ((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
 +                ((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
 +                ((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
 +                ((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
 +                ((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56));
 +        if (mix) {
 +            col_0 = temp & 0xFFFFFFFF;
 +            col_1 = temp >> 32;
 +
 +            col_0 = AES_MIXCOLUMN(col_0);
 +            col_1 = AES_MIXCOLUMN(col_1);
 +
 +            result = ((uint64_t)col_1 << 32) | col_0;
 +        } else {
 +            result = temp;
 +        }
 +    } else {
 +        temp = AES_INVSHIFROWS_LO(RS1, RS2);
 +        temp = (((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
 +                ((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
 +                ((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
 +                ((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
 +                ((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
 +                ((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
 +                ((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
 +                ((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56));
 +        if (mix) {
 +            col_0 = temp & 0xFFFFFFFF;
 +            col_1 = temp >> 32;
 +
 +            col_0 = AES_INVMIXCOLUMN(col_0);
 +            col_1 = AES_INVMIXCOLUMN(col_1);
 +
 +            result = ((uint64_t)col_1 << 32) | col_0;
 +        } else {
 +            result = temp;
 +        }
 +    }
 +
-+    return result;
++    return 0;
 +}
 +
-+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
+ int kvm_arch_put_registers(CPUState *cs, int level)
-+{
+ {
-+    return aes64_operation(rs1, rs2, true, true);
+     int ret = 0;
-+}
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
-+
+         return ret;
-+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
+     }
-+{
-+    return aes64_operation(rs1, rs2, true, false);
++    if (KVM_PUT_RESET_STATE == level) {
-+}
++        RISCVCPU *cpu = RISCV_CPU(cs);
-+
++        if (cs->cpu_index == 0) {
-+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
++            ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE);
-+{
++        } else {
-+    return aes64_operation(rs1, rs2, false, false);
++            ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED);
-+}
++        }
-+
++        if (ret) {
-+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
++            return ret;
-+{
++        }
 +    return aes64_operation(rs1, rs2, false, true);
 +}
 +
 +target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
 +{
 +    uint64_t RS1 = rs1;
 +    uint64_t RS2 = rs2;
 +    uint32_t rs1_hi = RS1 >> 32;
 +    uint32_t rs2_lo = RS2;
 +    uint32_t rs2_hi = RS2 >> 32;
 +
 +    uint32_t r_lo = (rs1_hi ^ rs2_lo);
 +    uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi);
 +    target_ulong result = ((uint64_t)r_hi << 32) | r_lo;
 +
 +    return result;
 +}
 +
 +target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
 +{
 +    uint64_t RS1 = rs1;
 +    static const uint8_t round_consts[10] = {
 +        0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
 +    };
 +
 +    uint8_t enc_rnum = rnum;
 +    uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
 +    uint8_t rcon_ = 0;
 +    target_ulong result;
 +
 +    if (enc_rnum != 0xA) {
 +        temp = ror32(temp, 8); /* Rotate right by 8 */
 +        rcon_ = round_consts[enc_rnum];
 +    }
 +
-+    temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+     return ret;
 +           ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
 +           ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
 +           ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
 +
 +    temp ^= rcon_;
 +
 +    result = ((uint64_t)temp << 32) | temp;
 +
 +    return result;
 +}
 +
 +target_ulong HELPER(aes64im)(target_ulong rs1)
 +{
 +    uint64_t RS1 = rs1;
 +    uint32_t col_0 = RS1 & 0xFFFFFFFF;
 +    uint32_t col_1 = RS1 >> 32;
 +    target_ulong result;
 +
 +    col_0 = AES_INVMIXCOLUMN(col_0);
 +    col_1 = AES_INVMIXCOLUMN(col_1);
 +
 +    result = ((uint64_t)col_1 << 32) | col_0;
 +
 +    return result;
 +}
  #undef sext32_xlen
 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvk.c.inc
 +++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
      REQUIRE_ZKND(ctx);
      return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
  }
-+
-+static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_default_type(MachineState *ms)
-+{
-+    REQUIRE_64BIT(ctx);
+ int kvm_arch_init(MachineState *ms, KVMState *s)
-+    REQUIRE_ZKNE(ctx);
+ {
-+    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64es, NULL);
++    cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
-+}
+     return 0;
-+
+ }
-+static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
-+{
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-+    REQUIRE_64BIT(ctx);
+ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-+    REQUIRE_ZKNE(ctx);
+ {
-+    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64esm, NULL);
+     CPURISCVState *env = &cpu->env;
-+}
++    int i;
-+
-+static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
+     if (!kvm_enabled()) {
-+{
+         return;
-+    REQUIRE_64BIT(ctx);
+     }
-+    REQUIRE_ZKND(ctx);
++    for (i = 0; i < 32; i++) {
-+    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ds, NULL);
++        env->gpr[i] = 0;
 +}
 +
 +static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
 +{
 +    REQUIRE_64BIT(ctx);
 +    REQUIRE_ZKND(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64dsm, NULL);
 +}
 +
 +static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
 +{
 +    REQUIRE_64BIT(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zknd, zkne);
 +    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ks2, NULL);
 +}
 +
 +static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
 +{
 +    REQUIRE_64BIT(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zknd, zkne);
 +
 +    if (a->imm > 0xA) {
 +        return false;
 +    }
-+
+     env->pc = cpu->env.kernel_addr;
-+    return gen_arith_imm_tl(ctx, a, EXT_NONE, gen_helper_aes64ks1i, NULL);
+     env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
-+}
+     env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
-+
+     env->satp = 0;
-+static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
++    env->mie = 0;
-+{
++    env->stvec = 0;
-+    REQUIRE_64BIT(ctx);
++    env->sscratch = 0;
-+    REQUIRE_ZKND(ctx);
++    env->sepc = 0;
-+    return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
++    env->scause = 0;
-+}
++    env->stval = 0;
 +    env->mip = 0;
  }
  void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
 --
-.35.1
+.41.0

-New patch
+[PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14
+From: Alvin Chang <vivahavey@gmail.com>
+Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name().
+Signed-off-by: Alvin Chang <alvinga@andestech.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230907084500.328-1-alvinga@andestech.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ disas/riscv.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/disas/riscv.c b/disas/riscv.c
+index XXXXXXX..XXXXXXX 100644
+--- a/disas/riscv.c
++++ b/disas/riscv.c
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
+     case 0x03ba: return "pmpaddr10";
+     case 0x03bb: return "pmpaddr11";
+     case 0x03bc: return "pmpaddr12";
+-    case 0x03bd: return "pmpaddr14";
+-    case 0x03be: return "pmpaddr13";
++    case 0x03bd: return "pmpaddr13";
++    case 0x03be: return "pmpaddr14";
+     case 0x03bf: return "pmpaddr15";
+     case 0x0780: return "mtohost";
+     case 0x0781: return "mfromhost";
+--
+.41.0

-[PULL 09/25] target/riscv: rvk: add support for zknd/zkne extension in RV32
+[PULL 23/54] target/riscv: introduce TCG AccelCPUClass
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
+target/riscv/cpu.c needs to handle all possible accelerators (TCG and
 KVM at this moment) during both init() and realize() time. This forces
 us to resort to a lot of "if tcg" and "if kvm" throughout the code,
 which isn't wrong, but can get cluttered over time. Splitting
 acceleration specific code from cpu.c to its own file will help to
 declutter the existing code and it will also make it easier to support
 KVM/TCG only builds in the future.
-Co-authored-by: Zewen Ye <lustrew@foxmail.com>
+We'll start by adding a new subdir called 'tcg' and a new file called
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+'tcg-cpu.c'. This file will be used to introduce a new accelerator class
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+for TCG acceleration in RISC-V, allowing us to center all TCG exclusive
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+code in its file instead of using 'cpu.c' for everything. This design is
 inpired by the work Claudio Fontana did in x86 a few years ago in commit
 f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using
 AccelCPUClass").
 To avoid moving too much code at once we'll start by adding the new file
 and TCG AccelCPUClass declaration. The 'class_init' from the accel class
 will init 'tcg_ops', relieving the common riscv_cpu_class_init() from
 doing it.
 'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having
 to deal with moving code and files around right now. We'll focus on
 decoupling the realize() logic first.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn>
+Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |   6 ++
+ target/riscv/cpu.h           |  4 +++
- target/riscv/insn32.decode              |  11 +++
+ target/riscv/cpu.c           |  5 +---
- target/riscv/crypto_helper.c            | 105 ++++++++++++++++++++++++
+ target/riscv/tcg/tcg-cpu.c   | 58 ++++++++++++++++++++++++++++++++++++
- target/riscv/translate.c                |   1 +
+ target/riscv/meson.build     |  2 ++
- target/riscv/insn_trans/trans_rvk.c.inc |  71 ++++++++++++++++
+ target/riscv/tcg/meson.build |  2 ++
- target/riscv/meson.build                |   3 +-
+files changed, 67 insertions(+), 4 deletions(-)
-files changed, 196 insertions(+), 1 deletion(-)
+ create mode 100644 target/riscv/tcg/tcg-cpu.c
- create mode 100644 target/riscv/crypto_helper.c
+ create mode 100644 target/riscv/tcg/meson.build
  create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/helper.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(divu_i128, tl, env, tl, tl, tl, tl)
+@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
- DEF_HELPER_5(divs_i128, tl, env, tl, tl, tl, tl)
+     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
- DEF_HELPER_5(remu_i128, tl, env, tl, tl, tl, tl)
+ };
- DEF_HELPER_5(rems_i128, tl, env, tl, tl, tl, tl)
 +/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
 +#include "hw/core/tcg-cpu-ops.h"
 +extern const struct TCGCPUOps riscv_tcg_ops;
 +
-+/* Crypto functions */
+ /* CSR function table */
-+DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
-+DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
-+DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 +DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
- %imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
+ };
- %imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
+ #endif
- %imm_u    12:s20                 !function=ex_shift_12
-+%imm_bs   30:2                   !function=ex_shift_3
+-#include "hw/core/tcg-cpu-ops.h"
+-
- # Argument sets:
+-static const struct TCGCPUOps riscv_tcg_ops = {
- &empty
++const struct TCGCPUOps riscv_tcg_ops = {
-@@ -XXX,XX +XXX,XX @@
+     .initialize = riscv_translate_init,
- &rmr       vm rd rs2
+     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
- &r2nfvm    vm rd rs1 nf
+     .restore_state_to_opc = riscv_restore_state_to_opc,
- &rnfvm     vm rd rs1 rs2 nf
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
-+&k_aes     shamt rs2 rs1 rd
+ #endif
+     cc->gdb_arch_name = riscv_gdb_arch_name;
- # Formats 32:
+     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
- @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
+-    cc->tcg_ops = &riscv_tcg_ops;
-@@ -XXX,XX +XXX,XX @@
- @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
+     object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
- @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
+                               cpu_set_mvendorid, NULL, NULL);
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 +@k_aes   .. ..... ..... .....  ... ..... ....... &k_aes  shamt=%imm_bs   %rs2 %rs1 %rd
 +
  # Formats 64:
  @sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
@@ -XXX,XX +XXX,XX @@ sfence_w_inval    0001100 00000 00000 000 00000 1110011
  sfence_inval_ir   0001100 00001 00000 000 00000 1110011
  hinval_vvma       0010011 ..... ..... 000 00000 1110011 @hfence_vvma
  hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
 +
 +# *** RV32 Zknd Standard Extension ***
 +aes32dsmi   .. 10111 ..... ..... 000 ..... 0110011 @k_aes
 +aes32dsi    .. 10101 ..... ..... 000 ..... 0110011 @k_aes
 +# *** RV32 Zkne Standard Extension ***
 +aes32esmi   .. 10011 ..... ..... 000 ..... 0110011 @k_aes
 +aes32esi    .. 10001 ..... ..... 000 ..... 0110011 @k_aes
 diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/riscv/crypto_helper.c
++++ b/target/riscv/tcg/tcg-cpu.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * RISC-V Crypto Emulation Helpers for QEMU.
++ * riscv TCG cpu class initialization
 + *
-+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
++ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
-+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
++ * Copyright (c) 2017-2018 SiFive, Inc.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "cpu.h"
-+#include "exec/exec-all.h"
++#include "qemu/accel.h"
-+#include "exec/helper-proto.h"
++#include "hw/core/accel-cpu.h"
 +#include "crypto/aes.h"
 +#include "crypto/sm4.h"
 +
-+#define AES_XTIME(a) \
++static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 +    ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
 +
 +#define AES_GFMUL(a, b) (( \
 +    (((b) & 0x1) ? (a) : 0) ^ \
 +    (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
 +    (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
 +    (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
 +
 +static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
 +{
-+    uint32_t u;
++    /*
-+
++     * All cpus use the same set of operations.
-+    if (fwd) {
++     * riscv_tcg_ops is being imported from cpu.c for now.
-+        u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
++     */
-+            (AES_GFMUL(x, 2) << 0);
++    cc->tcg_ops = &riscv_tcg_ops;
 +    } else {
 +        u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
 +            (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
 +    }
 +    return u;
 +}
 +
-+#define sext32_xlen(x) (target_ulong)(int32_t)(x)
++static void tcg_cpu_class_init(CPUClass *cc)
 +
 +static inline target_ulong aes32_operation(target_ulong shamt,
 +                                           target_ulong rs1, target_ulong rs2,
 +                                           bool enc, bool mix)
 +{
-+    uint8_t si = rs2 >> shamt;
++    cc->init_accel_cpu = tcg_cpu_init_ops;
 +    uint8_t so;
 +    uint32_t mixed;
 +    target_ulong res;
 +
 +    if (enc) {
 +        so = AES_sbox[si];
 +        if (mix) {
 +            mixed = aes_mixcolumn_byte(so, true);
 +        } else {
 +            mixed = so;
 +        }
 +    } else {
 +        so = AES_isbox[si];
 +        if (mix) {
 +            mixed = aes_mixcolumn_byte(so, false);
 +        } else {
 +            mixed = so;
 +        }
 +    }
 +    mixed = rol32(mixed, shamt);
 +    res = rs1 ^ mixed;
 +
 +    return sext32_xlen(res);
 +}
 +
-+target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2,
++static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
 +                               target_ulong shamt)
 +{
-+    return aes32_operation(shamt, rs1, rs2, true, true);
++    AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
 +
 +    acc->cpu_class_init = tcg_cpu_class_init;
 +}
 +
-+target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2,
++static const TypeInfo tcg_cpu_accel_type_info = {
-+                              target_ulong shamt)
++    .name = ACCEL_CPU_NAME("tcg"),
 +
 +    .parent = TYPE_ACCEL_CPU,
 +    .class_init = tcg_cpu_accel_class_init,
 +    .abstract = true,
 +};
 +
 +static void tcg_cpu_accel_register_types(void)
 +{
-+    return aes32_operation(shamt, rs1, rs2, true, false);
++    type_register_static(&tcg_cpu_accel_type_info);
 +}
-+
++type_init(tcg_cpu_accel_register_types);
 +target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2,
 +                               target_ulong shamt)
 +{
 +    return aes32_operation(shamt, rs1, rs2, false, true);
 +}
 +
 +target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
 +                              target_ulong shamt)
 +{
 +    return aes32_operation(shamt, rs1, rs2, false, false);
 +}
 +#undef sext32_xlen
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  #include "insn_trans/trans_rvv.c.inc"
  #include "insn_trans/trans_rvb.c.inc"
  #include "insn_trans/trans_rvzfh.c.inc"
 +#include "insn_trans/trans_rvk.c.inc"
  #include "insn_trans/trans_privileged.c.inc"
  #include "insn_trans/trans_svinval.c.inc"
  #include "insn_trans/trans_xventanacondops.c.inc"
 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -XXX,XX +XXX,XX @@
 +/*
 + * RISC-V translation routines for the Zk[nd,ne,nh,sed,sh] Standard Extension.
 + *
 + * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
 + * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#define REQUIRE_ZKND(ctx) do {                  \
 +    if (!ctx->cfg_ptr->ext_zknd) {              \
 +        return false;                           \
 +    }                                           \
 +} while (0)
 +
 +#define REQUIRE_ZKNE(ctx) do {                  \
 +    if (!ctx->cfg_ptr->ext_zkne) {              \
 +        return false;                           \
 +    }                                           \
 +} while (0)
 +
 +static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
 +                          void (*func)(TCGv, TCGv, TCGv, TCGv))
 +{
 +    TCGv shamt = tcg_constant_tl(a->shamt);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
 +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 +
 +    func(dest, src1, src2, shamt);
 +    gen_set_gpr(ctx, a->rd, dest);
 +    return true;
 +}
 +
 +static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
 +{
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZKNE(ctx);
 +    return gen_aes32_sm4(ctx, a, gen_helper_aes32esmi);
 +}
 +
 +static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
 +{
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZKNE(ctx);
 +    return gen_aes32_sm4(ctx, a, gen_helper_aes32esi);
 +}
 +
 +static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
 +{
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZKND(ctx);
 +    return gen_aes32_sm4(ctx, a, gen_helper_aes32dsmi);
 +}
 +
 +static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
 +{
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZKND(ctx);
 +    return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
 +}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
+@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
-   'vector_helper.c',
+   'riscv-qmp-cmds.c',
    'bitmanip_helper.c',
    'translate.c',
 -  'm128_helper.c'
 +  'm128_helper.c',
 +  'crypto_helper.c'
  ))
- riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
++subdir('tcg')
 +
  target_arch += {'riscv': riscv_ss}
  target_system_arch += {'riscv': riscv_system_ss}
 diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/tcg/meson.build
@@ -XXX,XX +XXX,XX @@
 +riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
 +  'tcg-cpu.c'))
 --
-.35.1
+.41.0

-[PULL 14/25] target/riscv: rvk: add support for zksed/zksh extension
+[PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - add sm3p0, sm3p1, sm4ed and sm4ks instructions
+riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
+realize() path during the common riscv_cpu_realize(), making it a good
-Co-authored-by: Ruibo Lu <luruibo2000@163.com>
+choice to start moving TCG exclusive code to tcg-cpu.c.
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+Rename it to tcg_cpu_realizefn() and assign it as a implementation of
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
-Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn>
+approach with KVM in the near future.
 riscv_cpu_validate_set_extensions() is too big and with too many
 dependencies to be moved in this same patch. We'll do that next.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20230925175709.35696-3-dbarboza@ventanamicro.com>
 [ Changes by AF:
  - Renames to fix build failures after rebase
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |  3 ++
+ target/riscv/cpu.c         | 128 -----------------------------------
- target/riscv/insn32.decode              |  6 +++
+ target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++
- target/riscv/crypto_helper.c            | 28 ++++++++++++
+files changed, 133 insertions(+), 128 deletions(-)
- target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
-files changed, 95 insertions(+)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/helper.h
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+@@ -XXX,XX +XXX,XX @@
- DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ #include "qemu/log.h"
- DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ #include "cpu.h"
- DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
+ #include "cpu_vendorid.h"
-+
+-#include "pmu.h"
-+DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+ #include "internals.h"
-+DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+-#include "time_helper.h"
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+ #include "exec/exec-all.h"
  #include "qapi/error.h"
  #include "qapi/visitor.h"
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
      }
  }
 -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
 -{
 -    CPURISCVState *env = &cpu->env;
 -    int priv_version = -1;
 -
 -    if (cpu->cfg.priv_spec) {
 -        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
 -            priv_version = PRIV_VERSION_1_12_0;
 -        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 -            priv_version = PRIV_VERSION_1_11_0;
 -        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 -            priv_version = PRIV_VERSION_1_10_0;
 -        } else {
 -            error_setg(errp,
 -                       "Unsupported privilege spec version '%s'",
 -                       cpu->cfg.priv_spec);
 -            return;
 -        }
 -
 -        env->priv_ver = priv_version;
 -    }
 -}
 -
  static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
  {
      CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
      }
  }
 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
 -{
 -    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 -    CPUClass *cc = CPU_CLASS(mcc);
 -    CPURISCVState *env = &cpu->env;
 -
 -    /* Validate that MISA_MXL is set properly. */
 -    switch (env->misa_mxl_max) {
 -#ifdef TARGET_RISCV64
 -    case MXL_RV64:
 -    case MXL_RV128:
 -        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 -        break;
 -#endif
 -    case MXL_RV32:
 -        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 -
 -    if (env->misa_mxl_max != env->misa_mxl) {
 -        error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
 -        return;
 -    }
 -}
 -
  /*
   * Check consistency between chosen extensions while setting
   * cpu->cfg accordingly.
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
  #endif
  }
 -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
 -{
 -    if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
 -        error_setg(errp, "H extension requires priv spec 1.12.0");
 -        return;
 -    }
 -}
 -
 -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
 -{
 -    RISCVCPU *cpu = RISCV_CPU(dev);
 -    CPURISCVState *env = &cpu->env;
 -    Error *local_err = NULL;
 -
 -    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
 -        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
 -        return;
 -    }
 -
 -    riscv_cpu_validate_misa_mxl(cpu, &local_err);
 -    if (local_err != NULL) {
 -        error_propagate(errp, local_err);
 -        return;
 -    }
 -
 -    riscv_cpu_validate_priv_spec(cpu, &local_err);
 -    if (local_err != NULL) {
 -        error_propagate(errp, local_err);
 -        return;
 -    }
 -
 -    riscv_cpu_validate_misa_priv(env, &local_err);
 -    if (local_err != NULL) {
 -        error_propagate(errp, local_err);
 -        return;
 -    }
 -
 -    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
 -        /*
 -         * Enhanced PMP should only be available
 -         * on harts with PMP support
 -         */
 -        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
 -        return;
 -    }
 -
 -    riscv_cpu_validate_set_extensions(cpu, &local_err);
 -    if (local_err != NULL) {
 -        error_propagate(errp, local_err);
 -        return;
 -    }
 -
 -#ifndef CONFIG_USER_ONLY
 -    CPU(dev)->tcg_cflags |= CF_PCREL;
 -
 -    if (cpu->cfg.ext_sstc) {
 -        riscv_timer_init(cpu);
 -    }
 -
 -    if (cpu->cfg.pmu_num) {
 -        if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
 -            cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 -                                          riscv_pmu_timer_cb, cpu);
 -        }
 -     }
 -#endif
 -}
 -
  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  {
      CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
          return;
      }
 -    if (tcg_enabled()) {
 -        riscv_cpu_realize_tcg(dev, &local_err);
 -        if (local_err != NULL) {
 -            error_propagate(errp, local_err);
 -            return;
 -        }
 -    }
 -
      riscv_cpu_finalize_features(cpu, &local_err);
      if (local_err != NULL) {
          error_propagate(errp, local_err);
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/tcg/tcg-cpu.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ sha512sig0  00 01000 00110 ..... 001 ..... 0010011 @r2
+@@ -XXX,XX +XXX,XX @@
- sha512sig1  00 01000 00111 ..... 001 ..... 0010011 @r2
+  */
- sha512sum0  00 01000 00100 ..... 001 ..... 0010011 @r2
- sha512sum1  00 01000 00101 ..... 001 ..... 0010011 @r2
+ #include "qemu/osdep.h"
-+# *** RV32 Zksh Standard Extension ***
++#include "exec/exec-all.h"
-+sm3p0       00 01000 01000 ..... 001 ..... 0010011 @r2
+ #include "cpu.h"
-+sm3p1       00 01000 01001 ..... 001 ..... 0010011 @r2
++#include "pmu.h"
-+# *** RV32 Zksed Standard Extension ***
++#include "time_helper.h"
-+sm4ed       .. 11000 ..... ..... 000 ..... 0110011 @k_aes
++#include "qapi/error.h"
-+sm4ks       .. 11010 ..... ..... 000 ..... 0110011 @k_aes
+ #include "qemu/accel.h"
-diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
+ #include "hw/core/accel-cpu.h"
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/crypto_helper.c
++
-+++ b/target/riscv/crypto_helper.c
++static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes64im)(target_ulong rs1)
      return result;
  }
 +
 +target_ulong HELPER(sm4ed)(target_ulong rs1, target_ulong rs2,
 +                           target_ulong shamt)
 +{
-+    uint32_t sb_in = (uint8_t)(rs2 >> shamt);
++    if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
-+    uint32_t sb_out = (uint32_t)sm4_sbox[sb_in];
++        error_setg(errp, "H extension requires priv spec 1.12.0");
-+
++        return;
-+    uint32_t x = sb_out ^ (sb_out << 8) ^ (sb_out << 2) ^ (sb_out << 18) ^
++    }
 +                 ((sb_out & 0x3f) << 26) ^ ((sb_out & 0xC0) << 10);
 +
 +    uint32_t rotl = rol32(x, shamt);
 +
 +    return sext32_xlen(rotl ^ (uint32_t)rs1);
 +}
 +
-+target_ulong HELPER(sm4ks)(target_ulong rs1, target_ulong rs2,
++static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
 +                           target_ulong shamt)
 +{
-+    uint32_t sb_in = (uint8_t)(rs2 >> shamt);
++    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-+    uint32_t sb_out = sm4_sbox[sb_in];
++    CPUClass *cc = CPU_CLASS(mcc);
-+
++    CPURISCVState *env = &cpu->env;
-+    uint32_t x = sb_out ^ ((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^
++
-+                 ((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13);
++    /* Validate that MISA_MXL is set properly. */
-+
++    switch (env->misa_mxl_max) {
-+    uint32_t rotl = rol32(x, shamt);
++#ifdef TARGET_RISCV64
-+
++    case MXL_RV64:
-+    return sext32_xlen(rotl ^ (uint32_t)rs1);
++    case MXL_RV128:
 +        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 +        break;
 +#endif
 +    case MXL_RV32:
 +        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
 +    if (env->misa_mxl_max != env->misa_mxl) {
 +        error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
 +        return;
 +    }
 +}
- #undef sext32_xlen
++
-diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
++static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvk.c.inc
 +++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -XXX,XX +XXX,XX @@
      }                                           \
  } while (0)
 +#define REQUIRE_ZKSED(ctx) do {                 \
 +    if (!ctx->cfg_ptr->ext_zksed) {             \
 +        return false;                           \
 +    }                                           \
 +} while (0)
 +
 +#define REQUIRE_ZKSH(ctx) do {                  \
 +    if (!ctx->cfg_ptr->ext_zksh) {              \
 +        return false;                           \
 +    }                                           \
 +} while (0)
 +
  static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
                            void (*func)(TCGv, TCGv, TCGv, TCGv))
  {
@@ -XXX,XX +XXX,XX @@ static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a)
      REQUIRE_ZKNH(ctx);
      return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41);
  }
 +
 +/* SM3 */
 +static bool gen_sm3(DisasContext *ctx, arg_r2 *a, int32_t b, int32_t c)
 +{
-+    TCGv dest = dest_gpr(ctx, a->rd);
++    CPURISCVState *env = &cpu->env;
-+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
++    int priv_version = -1;
-+    TCGv_i32 t0 = tcg_temp_new_i32();
++
-+    TCGv_i32 t1 = tcg_temp_new_i32();
++    if (cpu->cfg.priv_spec) {
-+
++        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
-+    tcg_gen_trunc_tl_i32(t0, src1);
++            priv_version = PRIV_VERSION_1_12_0;
-+    tcg_gen_rotli_i32(t1, t0, b);
++        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
-+    tcg_gen_xor_i32(t1, t0, t1);
++            priv_version = PRIV_VERSION_1_11_0;
-+    tcg_gen_rotli_i32(t0, t0, c);
++        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
-+    tcg_gen_xor_i32(t1, t1, t0);
++            priv_version = PRIV_VERSION_1_10_0;
-+    tcg_gen_ext_i32_tl(dest, t1);
++        } else {
-+    gen_set_gpr(ctx, a->rd, dest);
++            error_setg(errp,
-+
++                       "Unsupported privilege spec version '%s'",
-+    tcg_temp_free_i32(t0);
++                       cpu->cfg.priv_spec);
-+    tcg_temp_free_i32(t1);
++            return;
 +        }
 +
 +        env->priv_ver = priv_version;
 +    }
 +}
 +
 +/*
 + * We'll get here via the following path:
 + *
 + * riscv_cpu_realize()
 + *   -> cpu_exec_realizefn()
 + *      -> tcg_cpu_realize() (via accel_cpu_common_realize())
 + */
 +static bool tcg_cpu_realize(CPUState *cs, Error **errp)
 +{
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    CPURISCVState *env = &cpu->env;
 +    Error *local_err = NULL;
 +
 +    if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
 +        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
 +        return false;
 +    }
 +
 +    riscv_cpu_validate_misa_mxl(cpu, &local_err);
 +    if (local_err != NULL) {
 +        error_propagate(errp, local_err);
 +        return false;
 +    }
 +
 +    riscv_cpu_validate_priv_spec(cpu, &local_err);
 +    if (local_err != NULL) {
 +        error_propagate(errp, local_err);
 +        return false;
 +    }
 +
 +    riscv_cpu_validate_misa_priv(env, &local_err);
 +    if (local_err != NULL) {
 +        error_propagate(errp, local_err);
 +        return false;
 +    }
 +
 +    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
 +        /*
 +         * Enhanced PMP should only be available
 +         * on harts with PMP support
 +         */
 +        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
 +        return false;
 +    }
 +
 +    riscv_cpu_validate_set_extensions(cpu, &local_err);
 +    if (local_err != NULL) {
 +        error_propagate(errp, local_err);
 +        return false;
 +    }
 +
 +#ifndef CONFIG_USER_ONLY
 +    CPU(cs)->tcg_cflags |= CF_PCREL;
 +
 +    if (cpu->cfg.ext_sstc) {
 +        riscv_timer_init(cpu);
 +    }
 +
 +    if (cpu->cfg.pmu_num) {
 +        if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
 +            cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 +                                          riscv_pmu_timer_cb, cpu);
 +        }
 +     }
 +#endif
 +
 +    return true;
 +}
 +
-+static bool trans_sm3p0(DisasContext *ctx, arg_sm3p0 *a)
+ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
-+{
+ {
-+    REQUIRE_ZKSH(ctx);
+     /*
-+    return gen_sm3(ctx, a, 9, 17);
+@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
-+}
+     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
-+
-+static bool trans_sm3p1(DisasContext *ctx, arg_sm3p1 *a)
+     acc->cpu_class_init = tcg_cpu_class_init;
-+{
++    acc->cpu_target_realize = tcg_cpu_realize;
-+    REQUIRE_ZKSH(ctx);
+ }
-+    return gen_sm3(ctx, a, 15, 23);
-+}
+ static const TypeInfo tcg_cpu_accel_type_info = {
 +
 +/* SM4 */
 +static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
 +{
 +    REQUIRE_ZKSED(ctx);
 +    return gen_aes32_sm4(ctx, a, gen_helper_sm4ed);
 +}
 +
 +static bool trans_sm4ks(DisasContext *ctx, arg_sm4ks *a)
 +{
 +    REQUIRE_ZKSED(ctx);
 +    return gen_aes32_sm4(ctx, a, gen_helper_sm4ks);
 +}
 --
-.35.1
+.41.0

-[PULL 08/25] crypto: move sm4_sbox from target/arm
+[PULL 25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-   - share it between target/arm and target/riscv
+This function is the core of the RISC-V validations for TCG CPUs, and it
 has a lot going on.
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Functions in cpu.c were made public to allow them to be used by the KVM
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+hard to move it to another file due to its dependency with isa_edata_arr[]
 array, thus make it public and use it as is for now.
 riscv_cpu_validate_set_extensions() is kept public because it's used by
 csr.c in write_misa().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20230925175709.35696-4-dbarboza@ventanamicro.com>
 Message-Id: <20220423023510.30794-6-liweiwei@iscas.ac.cn>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/crypto/sm4.h       |  6 +++++
+ target/riscv/cpu.h         |   8 +-
- crypto/sm4.c               | 49 ++++++++++++++++++++++++++++++++++++++
+ target/riscv/tcg/tcg-cpu.h |  27 +++
- target/arm/crypto_helper.c | 36 +---------------------------
+ target/riscv/cpu.c         | 361 +------------------------------------
- crypto/meson.build         |  1 +
+ target/riscv/csr.c         |   1 +
-files changed, 57 insertions(+), 35 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 357 ++++++++++++++++++++++++++++++++++++
- create mode 100644 include/crypto/sm4.h
+files changed, 397 insertions(+), 357 deletions(-)
- create mode 100644 crypto/sm4.c
+ create mode 100644 target/riscv/tcg/tcg-cpu.h
-diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                          bool probe, uintptr_t retaddr);
  char *riscv_isa_string(RISCVCPU *cpu);
  void riscv_cpu_list(void);
 -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
  #define cpu_list riscv_cpu_list
  #define cpu_mmu_index riscv_cpu_mmu_index
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
  #include "hw/core/tcg-cpu-ops.h"
  extern const struct TCGCPUOps riscv_tcg_ops;
 +/* used by tcg/tcg-cpu.c*/
 +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
 +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
 +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 +int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
 +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
 +
  /* CSR function table */
  extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/crypto/sm4.h
++++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@
 +#ifndef QEMU_SM4_H
 +#define QEMU_SM4_H
 +
 +extern const uint8_t sm4_sbox[256];
 +
 +#endif
 diff --git a/crypto/sm4.c b/crypto/sm4.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/crypto/sm4.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * QEMU crypto sm4 support
++ * riscv TCG cpu class initialization
 + *
-+ * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
++ * Copyright (c) 2023 Ventana Micro Systems Inc.
 + *
 + * This library is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU Lesser General Public
 + * License as published by the Free Software Foundation; either
-+ * version 2.1 of the License, or (at your option) any later version.
++ * version 2 of the License, or (at your option) any later version.
 + *
 + * This library is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * Lesser General Public License for more details.
 + *
 + * You should have received a copy of the GNU Lesser General Public
 + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#include "qemu/osdep.h"
++#ifndef RISCV_TCG_CPU_H
-+#include "crypto/sm4.h"
++#define RISCV_TCG_CPU_H
 +
-+uint8_t const sm4_sbox[] = {
++#include "cpu.h"
-+    0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
++
-+    0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
++void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
-+    0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
++
-+    0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
++#endif
-+    0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 +    0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
 +    0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
 +    0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
 +    0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
 +    0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
 +    0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
 +    0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
 +    0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
 +    0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
 +    0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
 +    0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
 +    0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
 +    0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
 +    0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
 +    0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
 +    0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
 +    0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
 +    0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
 +    0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
 +    0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
 +    0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
 +    0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
 +    0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
 +    0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
 +    0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
 +    0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
 +    0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
 +};
 +
 diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/crypto_helper.c
+--- a/target/riscv/cpu.c
-+++ b/target/arm/crypto_helper.c
++++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
  /* Hash that stores user set extensions */
  static GHashTable *multi_ext_user_opts;
 -static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
 +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
  {
      bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
      return *ext_enabled;
  }
 -static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
 -                                   bool en)
 +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
  {
      bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
      *ext_enabled = en;
  }
 -static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 +int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
  {
      int i;
@@ -XXX,XX +XXX,XX @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
      g_assert_not_reached();
  }
 -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
 +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
  {
      return g_hash_table_contains(multi_ext_user_opts,
                                   GUINT_TO_POINTER(ext_offset));
  }
 -static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
 -                                    bool value)
 -{
 -    CPURISCVState *env = &cpu->env;
 -    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
 -    int min_version;
 -
 -    if (prev_val == value) {
 -        return;
 -    }
 -
 -    if (cpu_cfg_ext_is_user_set(ext_offset)) {
 -        return;
 -    }
 -
 -    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
 -        /* Do not enable it if priv_ver is older than min_version */
 -        min_version = cpu_cfg_ext_get_min_version(ext_offset);
 -        if (env->priv_ver < min_version) {
 -            return;
 -        }
 -    }
 -
 -    isa_ext_update_enabled(cpu, ext_offset, value);
 -}
 -
  const char * const riscv_int_regnames[] = {
      "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
      "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
      }
  }
 -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
 -                                 Error **errp)
 -{
 -    if (!is_power_of_2(cfg->vlen)) {
 -        error_setg(errp, "Vector extension VLEN must be power of 2");
 -        return;
 -    }
 -    if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
 -        error_setg(errp,
 -                   "Vector extension implementation only supports VLEN "
 -                   "in the range [128, %d]", RV_VLEN_MAX);
 -        return;
 -    }
 -    if (!is_power_of_2(cfg->elen)) {
 -        error_setg(errp, "Vector extension ELEN must be power of 2");
 -        return;
 -    }
 -    if (cfg->elen > 64 || cfg->elen < 8) {
 -        error_setg(errp,
 -                   "Vector extension implementation only supports ELEN "
 -                   "in the range [8, 64]");
 -        return;
 -    }
 -    if (cfg->vext_spec) {
 -        if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
 -            env->vext_ver = VEXT_VERSION_1_00_0;
 -        } else {
 -            error_setg(errp, "Unsupported vector spec version '%s'",
 -                       cfg->vext_spec);
 -            return;
 -        }
 -    } else if (env->vext_ver == 0) {
 -        qemu_log("vector version is not specified, "
 -                 "use the default value v1.0\n");
 -
 -        env->vext_ver = VEXT_VERSION_1_00_0;
 -    }
 -}
 -
 -static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
  {
      CPURISCVState *env = &cpu->env;
      int i;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
      }
  }
 -/*
 - * Check consistency between chosen extensions while setting
 - * cpu->cfg accordingly.
 - */
 -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 -{
 -    CPURISCVState *env = &cpu->env;
 -    Error *local_err = NULL;
 -
 -    /* Do some ISA extension error checking */
 -    if (riscv_has_ext(env, RVG) &&
 -        !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
 -          riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
 -          riscv_has_ext(env, RVD) &&
 -          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
 -
 -        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
 -            !cpu->cfg.ext_icsr) {
 -            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
 -            return;
 -        }
 -
 -        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
 -            !cpu->cfg.ext_ifencei) {
 -            error_setg(errp, "RVG requires Zifencei but user set "
 -                       "Zifencei to false");
 -            return;
 -        }
 -
 -        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
 -
 -        env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
 -        env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
 -    }
 -
 -    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
 -        error_setg(errp,
 -                   "I and E extensions are incompatible");
 -        return;
 -    }
 -
 -    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
 -        error_setg(errp,
 -                   "Either I or E extension must be set");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
 -        error_setg(errp,
 -                   "Setting S extension without U extension is illegal");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
 -        error_setg(errp,
 -                   "H depends on an I base integer ISA with 32 x registers");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
 -        error_setg(errp, "H extension implicitly requires S-mode");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
 -        error_setg(errp, "F extension requires Zicsr");
 -        return;
 -    }
 -
 -    if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
 -        error_setg(errp, "Zawrs extension requires A extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zfa extension requires F extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zfh) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
 -    }
 -
 -    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zfbfmin extension depends on F extension");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "D extension requires F extension");
 -        return;
 -    }
 -
 -    if (riscv_has_ext(env, RVV)) {
 -        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
 -        if (local_err != NULL) {
 -            error_propagate(errp, local_err);
 -            return;
 -        }
 -
 -        /* The V vector extension depends on the Zve64d extension */
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
 -    }
 -
 -    /* The Zve64d extension depends on the Zve64f extension */
 -    if (cpu->cfg.ext_zve64d) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
 -    }
 -
 -    /* The Zve64f extension depends on the Zve32f extension */
 -    if (cpu->cfg.ext_zve64f) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 -    }
 -
 -    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 -        error_setg(errp, "Zve64d/V extensions require D extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfh) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
 -    }
 -
 -    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
 -        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
 -        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
 -        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
 -        error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
 -        error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
 -        return;
 -    }
 -
 -    /* Set the ISA extensions, checks should have happened above */
 -    if (cpu->cfg.ext_zhinx) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 -    }
 -
 -    if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
 -        error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zfinx) {
 -        if (!cpu->cfg.ext_icsr) {
 -            error_setg(errp, "Zfinx extension requires Zicsr");
 -            return;
 -        }
 -        if (riscv_has_ext(env, RVF)) {
 -            error_setg(errp,
 -                       "Zfinx cannot be supported together with F extension");
 -            return;
 -        }
 -    }
 -
 -    if (cpu->cfg.ext_zce) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
 -        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 -            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 -        }
 -    }
 -
 -    /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
 -    if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 -        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 -            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 -        }
 -        if (riscv_has_ext(env, RVD)) {
 -            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
 -        }
 -    }
 -
 -    if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
 -        error_setg(errp, "Zcf extension is only relevant to RV32");
 -        return;
 -    }
 -
 -    if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
 -        error_setg(errp, "Zcf extension requires F extension");
 -        return;
 -    }
 -
 -    if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
 -        error_setg(errp, "Zcd extension requires D extension");
 -        return;
 -    }
 -
 -    if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
 -         cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
 -        error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
 -                         "extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
 -        error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
 -                         "Zcd extension");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
 -        error_setg(errp, "Zcmt extension requires Zicsr extension");
 -        return;
 -    }
 -
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
 -    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
 -         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
 -        !cpu->cfg.ext_zve32f) {
 -        error_setg(errp,
 -                   "Vector crypto extensions require V or Zve* extensions");
 -        return;
 -    }
 -
 -    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 -        error_setg(
 -            errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 -        return;
 -    }
 -
 -    if (cpu->cfg.ext_zk) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
 -    }
 -
 -    if (cpu->cfg.ext_zkn) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
 -    }
 -
 -    if (cpu->cfg.ext_zks) {
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
 -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
 -    }
 -
 -    /*
 -     * Disable isa extensions based on priv spec after we
 -     * validated and set everything we need.
 -     */
 -    riscv_cpu_disable_priv_spec_isa_exts(cpu);
 -}
 -
  #ifndef CONFIG_USER_ONLY
  static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
  {
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
 @@ -XXX,XX +XXX,XX @@
- #include "exec/helper-proto.h"
+ #include "qemu/log.h"
- #include "tcg/tcg-gvec-desc.h"
+ #include "qemu/timer.h"
- #include "crypto/aes.h"
+ #include "cpu.h"
-+#include "crypto/sm4.h"
++#include "tcg/tcg-cpu.h"
- #include "vec_internal.h"
+ #include "pmu.h"
+ #include "time_helper.h"
- union CRYPTO_STATE {
+ #include "exec/exec-all.h"
-@@ -XXX,XX +XXX,XX @@ DO_SM3TT(crypto_sm3tt2b, 3)
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
- #undef DO_SM3TT
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
--static uint8_t const sm4_sbox[] = {
+@@ -XXX,XX +XXX,XX @@
--    0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
--    0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+ #include "qemu/osdep.h"
--    0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
+ #include "exec/exec-all.h"
--    0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
++#include "tcg-cpu.h"
--    0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+ #include "cpu.h"
--    0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+ #include "pmu.h"
--    0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
+ #include "time_helper.h"
--    0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+ #include "qapi/error.h"
--    0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
+ #include "qemu/accel.h"
--    0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
++#include "qemu/error-report.h"
--    0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
++#include "qemu/log.h"
--    0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+ #include "hw/core/accel-cpu.h"
--    0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
--    0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
--    0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
++static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
--    0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
++                                    bool value)
--    0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
++{
--    0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
++    CPURISCVState *env = &cpu->env;
--    0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
++    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
--    0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
++    int min_version;
--    0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
++
--    0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
++    if (prev_val == value) {
--    0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
++        return;
--    0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
++    }
--    0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
++
--    0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
++    if (cpu_cfg_ext_is_user_set(ext_offset)) {
--    0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
++        return;
--    0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
++    }
--    0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
++
--    0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
++    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
--    0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
++        /* Do not enable it if priv_ver is older than min_version */
--    0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
++        min_version = cpu_cfg_ext_get_min_version(ext_offset);
--};
++        if (env->priv_ver < min_version) {
--
++            return;
- static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
++        }
 +    }
 +
 +    isa_ext_update_enabled(cpu, ext_offset, value);
 +}
 +
  static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
  {
-     union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
+     if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
-diff --git a/crypto/meson.build b/crypto/meson.build
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
-index XXXXXXX..XXXXXXX 100644
+     }
---- a/crypto/meson.build
+ }
-+++ b/crypto/meson.build
-@@ -XXX,XX +XXX,XX @@ if have_afalg
++static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
- endif
++                                 Error **errp)
- crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
++{
++    if (!is_power_of_2(cfg->vlen)) {
-+util_ss.add(files('sm4.c'))
++        error_setg(errp, "Vector extension VLEN must be power of 2");
- util_ss.add(files('aes.c'))
++        return;
- util_ss.add(files('init.c'))
++    }
- if gnutls.found()
++
 +    if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
 +        error_setg(errp,
 +                   "Vector extension implementation only supports VLEN "
 +                   "in the range [128, %d]", RV_VLEN_MAX);
 +        return;
 +    }
 +
 +    if (!is_power_of_2(cfg->elen)) {
 +        error_setg(errp, "Vector extension ELEN must be power of 2");
 +        return;
 +    }
 +
 +    if (cfg->elen > 64 || cfg->elen < 8) {
 +        error_setg(errp,
 +                   "Vector extension implementation only supports ELEN "
 +                   "in the range [8, 64]");
 +        return;
 +    }
 +
 +    if (cfg->vext_spec) {
 +        if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
 +            env->vext_ver = VEXT_VERSION_1_00_0;
 +        } else {
 +            error_setg(errp, "Unsupported vector spec version '%s'",
 +                       cfg->vext_spec);
 +            return;
 +        }
 +    } else if (env->vext_ver == 0) {
 +        qemu_log("vector version is not specified, "
 +                 "use the default value v1.0\n");
 +
 +        env->vext_ver = VEXT_VERSION_1_00_0;
 +    }
 +}
 +
 +/*
 + * Check consistency between chosen extensions while setting
 + * cpu->cfg accordingly.
 + */
 +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 +{
 +    CPURISCVState *env = &cpu->env;
 +    Error *local_err = NULL;
 +
 +    /* Do some ISA extension error checking */
 +    if (riscv_has_ext(env, RVG) &&
 +        !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
 +          riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
 +          riscv_has_ext(env, RVD) &&
 +          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
 +
 +        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
 +            !cpu->cfg.ext_icsr) {
 +            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
 +            return;
 +        }
 +
 +        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
 +            !cpu->cfg.ext_ifencei) {
 +            error_setg(errp, "RVG requires Zifencei but user set "
 +                       "Zifencei to false");
 +            return;
 +        }
 +
 +        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
 +
 +        env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
 +        env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
 +    }
 +
 +    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
 +        error_setg(errp,
 +                   "I and E extensions are incompatible");
 +        return;
 +    }
 +
 +    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
 +        error_setg(errp,
 +                   "Either I or E extension must be set");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
 +        error_setg(errp,
 +                   "Setting S extension without U extension is illegal");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
 +        error_setg(errp,
 +                   "H depends on an I base integer ISA with 32 x registers");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
 +        error_setg(errp, "H extension implicitly requires S-mode");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
 +        error_setg(errp, "F extension requires Zicsr");
 +        return;
 +    }
 +
 +    if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
 +        error_setg(errp, "Zawrs extension requires A extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "Zfa extension requires F extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zfh) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
 +    }
 +
 +    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "Zfbfmin extension depends on F extension");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "D extension requires F extension");
 +        return;
 +    }
 +
 +    if (riscv_has_ext(env, RVV)) {
 +        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
 +        if (local_err != NULL) {
 +            error_propagate(errp, local_err);
 +            return;
 +        }
 +
 +        /* The V vector extension depends on the Zve64d extension */
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
 +    }
 +
 +    /* The Zve64d extension depends on the Zve64f extension */
 +    if (cpu->cfg.ext_zve64d) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
 +    }
 +
 +    /* The Zve64f extension depends on the Zve32f extension */
 +    if (cpu->cfg.ext_zve64f) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 +    }
 +
 +    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 +        error_setg(errp, "Zve64d/V extensions require D extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
 +        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfh) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
 +    }
 +
 +    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
 +        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
 +        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
 +        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
 +        error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
 +        error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
 +        return;
 +    }
 +
 +    /* Set the ISA extensions, checks should have happened above */
 +    if (cpu->cfg.ext_zhinx) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 +    }
 +
 +    if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
 +        error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zfinx) {
 +        if (!cpu->cfg.ext_icsr) {
 +            error_setg(errp, "Zfinx extension requires Zicsr");
 +            return;
 +        }
 +        if (riscv_has_ext(env, RVF)) {
 +            error_setg(errp,
 +                       "Zfinx cannot be supported together with F extension");
 +            return;
 +        }
 +    }
 +
 +    if (cpu->cfg.ext_zce) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
 +        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 +            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 +        }
 +    }
 +
 +    /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
 +    if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 +        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 +            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 +        }
 +        if (riscv_has_ext(env, RVD)) {
 +            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
 +        }
 +    }
 +
 +    if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
 +        error_setg(errp, "Zcf extension is only relevant to RV32");
 +        return;
 +    }
 +
 +    if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
 +        error_setg(errp, "Zcf extension requires F extension");
 +        return;
 +    }
 +
 +    if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
 +        error_setg(errp, "Zcd extension requires D extension");
 +        return;
 +    }
 +
 +    if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
 +         cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
 +        error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
 +                         "extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
 +        error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
 +                         "Zcd extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
 +        error_setg(errp, "Zcmt extension requires Zicsr extension");
 +        return;
 +    }
 +
 +    /*
 +     * In principle Zve*x would also suffice here, were they supported
 +     * in qemu
 +     */
 +    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
 +         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
 +        !cpu->cfg.ext_zve32f) {
 +        error_setg(errp,
 +                   "Vector crypto extensions require V or Zve* extensions");
 +        return;
 +    }
 +
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +        error_setg(
 +            errp,
 +            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_zk) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
 +    }
 +
 +    if (cpu->cfg.ext_zkn) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
 +    }
 +
 +    if (cpu->cfg.ext_zks) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
 +    }
 +
 +    /*
 +     * Disable isa extensions based on priv spec after we
 +     * validated and set everything we need.
 +     */
 +    riscv_cpu_disable_priv_spec_isa_exts(cpu);
 +}
 +
  /*
   * We'll get here via the following path:
   *
 --
-.35.1
+.41.0

-[PULL 07/25] target/riscv: rvk: add support for zbkx extension
+[PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - add xperm4 and xperm8 instructions
+Move the remaining of riscv_tcg_ops now that we have a working realize()
 implementation.
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20230925175709.35696-5-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |  2 ++
+ target/riscv/cpu.h         |  4 ---
- target/riscv/insn32.decode              |  4 ++++
+ target/riscv/cpu.c         | 58 ------------------------------------
- target/riscv/bitmanip_helper.c          | 27 +++++++++++++++++++++++++
+ target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++-
- target/riscv/insn_trans/trans_rvb.c.inc | 18 +++++++++++++++++
+files changed, 59 insertions(+), 63 deletions(-)
 files changed, 51 insertions(+)
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/helper.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
- DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
+     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
- DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
+ };
- DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
-+DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+-/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
-+DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+-#include "hw/core/tcg-cpu-ops.h"
+-extern const struct TCGCPUOps riscv_tcg_ops;
- /* Floating Point - Half Precision */
+-
- DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
+ /* used by tcg/tcg-cpu.c*/
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
  bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ clmulh     0000101 .......... 011 ..... 0110011 @r
+@@ -XXX,XX +XXX,XX @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
- # *** RV32 extra Zbc Standard Extension ***
+     return env->pc;
- clmulr     0000101 .......... 010 ..... 0110011 @r
+ }
-+# *** RV32 Zbkx Standard Extension ***
+-static void riscv_cpu_synchronize_from_tb(CPUState *cs,
-+xperm4     0010100 .......... 010 ..... 0110011 @r
+-                                          const TranslationBlock *tb)
-+xperm8     0010100 .......... 100 ..... 0110011 @r
+-{
 -    if (!(tb_cflags(tb) & CF_PCREL)) {
 -        RISCVCPU *cpu = RISCV_CPU(cs);
 -        CPURISCVState *env = &cpu->env;
 -        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 -
 -        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
 -
 -        if (xl == MXL_RV32) {
 -            env->pc = (int32_t) tb->pc;
 -        } else {
 -            env->pc = tb->pc;
 -        }
 -    }
 -}
 -
  static bool riscv_cpu_has_work(CPUState *cs)
  {
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
  #endif
  }
 -static void riscv_restore_state_to_opc(CPUState *cs,
 -                                       const TranslationBlock *tb,
 -                                       const uint64_t *data)
 -{
 -    RISCVCPU *cpu = RISCV_CPU(cs);
 -    CPURISCVState *env = &cpu->env;
 -    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 -    target_ulong pc;
 -
 -    if (tb_cflags(tb) & CF_PCREL) {
 -        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
 -    } else {
 -        pc = data[0];
 -    }
 -
 -    if (xl == MXL_RV32) {
 -        env->pc = (int32_t)pc;
 -    } else {
 -        env->pc = pc;
 -    }
 -    env->bins = data[1];
 -}
 -
  static void riscv_cpu_reset_hold(Object *obj)
  {
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
  };
  #endif
 -const struct TCGCPUOps riscv_tcg_ops = {
 -    .initialize = riscv_translate_init,
 -    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
 -    .restore_state_to_opc = riscv_restore_state_to_opc,
 -
 -#ifndef CONFIG_USER_ONLY
 -    .tlb_fill = riscv_cpu_tlb_fill,
 -    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 -    .do_interrupt = riscv_cpu_do_interrupt,
 -    .do_transaction_failed = riscv_cpu_do_transaction_failed,
 -    .do_unaligned_access = riscv_cpu_do_unaligned_access,
 -    .debug_excp_handler = riscv_cpu_debug_excp_handler,
 -    .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
 -    .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
 -#endif /* !CONFIG_USER_ONLY */
 -};
 -
  static bool riscv_cpu_is_dynamic(Object *cpu_obj)
  {
      return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/error-report.h"
  #include "qemu/log.h"
  #include "hw/core/accel-cpu.h"
 +#include "hw/core/tcg-cpu-ops.h"
 +#include "tcg/tcg.h"
 +static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 +                                          const TranslationBlock *tb)
 +{
 +    if (!(tb_cflags(tb) & CF_PCREL)) {
 +        RISCVCPU *cpu = RISCV_CPU(cs);
 +        CPURISCVState *env = &cpu->env;
 +        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 +
- # *** RV32 Zbs Standard Extension ***
++        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
  bclr       0100100 .......... 001 ..... 0110011 @r
  bclri      01001. ........... 001 ..... 0010011 @sh
 diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/bitmanip_helper.c
 +++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(zip)(target_ulong rs1)
      x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
      return x;
  }
 +
-+static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
++        if (xl == MXL_RV32) {
-+                                    uint32_t sz_log2)
++            env->pc = (int32_t) tb->pc;
-+{
++        } else {
-+    target_ulong r = 0;
++            env->pc = tb->pc;
 +    target_ulong sz = 1LL << sz_log2;
 +    target_ulong mask = (1LL << sz) - 1;
 +    target_ulong pos;
 +
 +    for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
 +        pos = ((rs2 >> i) & mask) << sz_log2;
 +        if (pos < sizeof(target_ulong) * 8) {
 +            r |= ((rs1 >> pos) & mask) << i;
 +        }
 +    }
-+    return r;
 +}
 +
-+target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
++static void riscv_restore_state_to_opc(CPUState *cs,
 +                                       const TranslationBlock *tb,
 +                                       const uint64_t *data)
 +{
-+    return do_xperm(rs1, rs2, 2);
++    RISCVCPU *cpu = RISCV_CPU(cs);
 +    CPURISCVState *env = &cpu->env;
 +    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 +    target_ulong pc;
 +
 +    if (tb_cflags(tb) & CF_PCREL) {
 +        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
 +    } else {
 +        pc = data[0];
 +    }
 +
 +    if (xl == MXL_RV32) {
 +        env->pc = (int32_t)pc;
 +    } else {
 +        env->pc = pc;
 +    }
 +    env->bins = data[1];
 +}
 +
-+target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
++static const struct TCGCPUOps riscv_tcg_ops = {
-+{
++    .initialize = riscv_translate_init,
-+    return do_xperm(rs1, rs2, 3);
++    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
-+}
++    .restore_state_to_opc = riscv_restore_state_to_opc,
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_ZBKX(ctx) do {                   \
 +    if (!ctx->cfg_ptr->ext_zbkx) {               \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
- static void gen_clz(TCGv ret, TCGv arg1)
++#ifndef CONFIG_USER_ONLY
 +    .tlb_fill = riscv_cpu_tlb_fill,
 +    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 +    .do_interrupt = riscv_cpu_do_interrupt,
 +    .do_transaction_failed = riscv_cpu_do_transaction_failed,
 +    .do_unaligned_access = riscv_cpu_do_unaligned_access,
 +    .debug_excp_handler = riscv_cpu_debug_excp_handler,
 +    .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
 +    .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
 +#endif /* !CONFIG_USER_ONLY */
 +};
  static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
                                      bool value)
@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
  {
-     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+     /*
-@@ -XXX,XX +XXX,XX @@ static bool trans_zip(DisasContext *ctx, arg_zip *a)
+      * All cpus use the same set of operations.
-     REQUIRE_ZBKB(ctx);
+-     * riscv_tcg_ops is being imported from cpu.c for now.
-     return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
+      */
      cc->tcg_ops = &riscv_tcg_ops;
  }
-+
-+static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
-+{
-+    REQUIRE_ZBKX(ctx);
-+    return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
-+}
-+
-+static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
-+{
-+    REQUIRE_ZBKX(ctx);
-+    return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
-+}
 --
-.35.1
+.41.0

-[PULL 12/25] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
+[PULL 27/54] target/riscv/cpu.c: add .instance_post_init()
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions
+All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
 calls riscv_init_max_cpu_extensions(). Both can be moved to a common
 instance_post_init() callback, implemented in riscv_cpu_post_init(),
 called by all CPUs. The call order then becomes:
-Co-authored-by: Zewen Ye <lustrew@foxmail.com>
+riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+In the near future riscv_cpu_post_init() will call the init() function
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+of the current accelerator, providing a hook for KVM and TCG accel
 classes to change the init() process of the CPU.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn>
+Message-ID: <20230925175709.35696-6-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              |   6 ++
+ target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++-----------
- target/riscv/insn_trans/trans_rvk.c.inc | 100 ++++++++++++++++++++++++
+file changed, 32 insertions(+), 11 deletions(-)
 files changed, 106 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ sha256sig0  00 01000 00010 ..... 001 ..... 0010011 @r2
+@@ -XXX,XX +XXX,XX @@ static void riscv_max_cpu_init(Object *obj)
- sha256sig1  00 01000 00011 ..... 001 ..... 0010011 @r2
+     mlx = MXL_RV32;
- sha256sum0  00 01000 00000 ..... 001 ..... 0010011 @r2
+ #endif
- sha256sum1  00 01000 00001 ..... 001 ..... 0010011 @r2
+     set_misa(env, mlx, 0);
-+sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
+-    riscv_cpu_add_user_properties(obj);
-+sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
+-    riscv_init_max_cpu_extensions(obj);
-+sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
+     env->priv_ver = PRIV_VERSION_LATEST;
-+sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
+ #ifndef CONFIG_USER_ONLY
-+sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
+     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
-+sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
+@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
-diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
-index XXXXXXX..XXXXXXX 100644
+     /* We set this in the realise function */
---- a/target/riscv/insn_trans/trans_rvk.c.inc
+     set_misa(env, MXL_RV64, 0);
-+++ b/target/riscv/insn_trans/trans_rvk.c.inc
+-    riscv_cpu_add_user_properties(obj);
-@@ -XXX,XX +XXX,XX @@ static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
+     /* Set latest version of privileged specification */
-     REQUIRE_ZKNH(ctx);
+     env->priv_ver = PRIV_VERSION_LATEST;
-     return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 6, 11, 25);
+ #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
      set_misa(env, MXL_RV128, 0);
 -    riscv_cpu_add_user_properties(obj);
      /* Set latest version of privileged specification */
      env->priv_ver = PRIV_VERSION_LATEST;
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
      set_misa(env, MXL_RV32, 0);
 -    riscv_cpu_add_user_properties(obj);
      /* Set latest version of privileged specification */
      env->priv_ver = PRIV_VERSION_LATEST;
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_host_cpu_init(Object *obj)
  #elif defined(TARGET_RISCV64)
      set_misa(env, MXL_RV64, 0);
  #endif
 -    riscv_cpu_add_user_properties(obj);
  }
-+
+ #endif /* CONFIG_KVM */
-+static bool gen_sha512_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
-+                            void (*func1)(TCGv_i64, TCGv_i64, int64_t),
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
-+                            void (*func2)(TCGv_i64, TCGv_i64, int64_t),
+ }
-+                            int64_t num1, int64_t num2, int64_t num3)
+ #endif /* CONFIG_USER_ONLY */
 +static bool riscv_cpu_is_dynamic(Object *cpu_obj)
 +{
-+    TCGv dest = dest_gpr(ctx, a->rd);
++    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
 +    TCGv src1 = get_gpr(ctx, a->rs1, ext);
 +    TCGv src2 = get_gpr(ctx, a->rs2, ext);
 +    TCGv_i64 t0 = tcg_temp_new_i64();
 +    TCGv_i64 t1 = tcg_temp_new_i64();
 +    TCGv_i64 t2 = tcg_temp_new_i64();
 +
 +    tcg_gen_concat_tl_i64(t0, src1, src2);
 +    func1(t1, t0, num1);
 +    func2(t2, t0, num2);
 +    tcg_gen_xor_i64(t1, t1, t2);
 +    tcg_gen_rotri_i64(t2, t0, num3);
 +    tcg_gen_xor_i64(t1, t1, t2);
 +    tcg_gen_trunc_i64_tl(dest, t1);
 +
 +    gen_set_gpr(ctx, a->rd, dest);
 +    tcg_temp_free_i64(t0);
 +    tcg_temp_free_i64(t1);
 +    tcg_temp_free_i64(t2);
 +    return true;
 +}
 +
-+static bool trans_sha512sum0r(DisasContext *ctx, arg_sha512sum0r *a)
++static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
 +{
-+    REQUIRE_32BIT(ctx);
++    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
 +    REQUIRE_ZKNH(ctx);
 +    return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
 +                           tcg_gen_rotli_i64, 25, 30, 28);
 +}
 +
-+static bool trans_sha512sum1r(DisasContext *ctx, arg_sha512sum1r *a)
++static bool riscv_cpu_has_user_properties(Object *cpu_obj)
 +{
-+    REQUIRE_32BIT(ctx);
++    if (kvm_enabled() &&
-+    REQUIRE_ZKNH(ctx);
++        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
-+    return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
++        return true;
-+                           tcg_gen_rotri_i64, 23, 14, 18);
++    }
 +
 +    return riscv_cpu_is_dynamic(cpu_obj);
 +}
 +
-+static bool trans_sha512sig0l(DisasContext *ctx, arg_sha512sig0l *a)
++static void riscv_cpu_post_init(Object *obj)
 +{
-+    REQUIRE_32BIT(ctx);
++    if (riscv_cpu_has_user_properties(obj)) {
-+    REQUIRE_ZKNH(ctx);
++        riscv_cpu_add_user_properties(obj);
-+    return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotri_i64,
++    }
-+                           tcg_gen_rotri_i64, 1, 7, 8);
++
 +    if (riscv_cpu_has_max_extensions(obj)) {
 +        riscv_init_max_cpu_extensions(obj);
 +    }
 +}
 +
-+static bool trans_sha512sig1l(DisasContext *ctx, arg_sha512sig1l *a)
+ static void riscv_cpu_init(Object *obj)
-+{
+ {
-+    REQUIRE_32BIT(ctx);
+ #ifndef CONFIG_USER_ONLY
-+    REQUIRE_ZKNH(ctx);
+@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
-+    return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
+ };
-+                           tcg_gen_rotri_i64, 3, 6, 19);
+ #endif
-+}
-+
+-static bool riscv_cpu_is_dynamic(Object *cpu_obj)
-+static bool gen_sha512h_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
+-{
-+                             void (*func)(TCGv_i64, TCGv_i64, int64_t),
+-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-+                             int64_t num1, int64_t num2, int64_t num3)
+-}
-+{
+-
-+    TCGv dest = dest_gpr(ctx, a->rd);
+ static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
-+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+                               void *opaque, Error **errp)
-+    TCGv src2 = get_gpr(ctx, a->rs2, ext);
+ {
-+    TCGv_i64 t0 = tcg_temp_new_i64();
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
-+    TCGv_i64 t1 = tcg_temp_new_i64();
+         .instance_size = sizeof(RISCVCPU),
-+    TCGv_i64 t2 = tcg_temp_new_i64();
+         .instance_align = __alignof(RISCVCPU),
-+
+         .instance_init = riscv_cpu_init,
-+    tcg_gen_concat_tl_i64(t0, src1, src2);
++        .instance_post_init = riscv_cpu_post_init,
-+    func(t1, t0, num1);
+         .abstract = true,
-+    tcg_gen_ext32u_i64(t2, t0);
+         .class_size = sizeof(RISCVCPUClass),
-+    tcg_gen_shri_i64(t2, t2, num2);
+         .class_init = riscv_cpu_class_init,
 +    tcg_gen_xor_i64(t1, t1, t2);
 +    tcg_gen_rotri_i64(t2, t0, num3);
 +    tcg_gen_xor_i64(t1, t1, t2);
 +    tcg_gen_trunc_i64_tl(dest, t1);
 +
 +    gen_set_gpr(ctx, a->rd, dest);
 +    tcg_temp_free_i64(t0);
 +    tcg_temp_free_i64(t1);
 +    tcg_temp_free_i64(t2);
 +    return true;
 +}
 +
 +static bool trans_sha512sig0h(DisasContext *ctx, arg_sha512sig0h *a)
 +{
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZKNH(ctx);
 +    return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 1, 7, 8);
 +}
 +
 +static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a)
 +{
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZKNH(ctx);
 +    return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19);
 +}
 --
-.35.1
+.41.0

-[PULL 15/25] target/riscv: rvk: add CSR support for Zkr
+[PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - add SEED CSR which must be accessed with a read-write instruction:
+This CPU only exists if we're compiling with KVM so move it to the kvm
-   A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
+specific file.
 with uimm=0 will raise an illegal instruction exception.
  - add USEED, SSEED fields for MSECCFG CSR
-Co-authored-by: Ruibo Lu <luruibo2000@163.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Co-authored-by: Zewen Ye <lustrew@foxmail.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn>
+Message-ID: <20230925175709.35696-7-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h  |  9 +++++
+ target/riscv/cpu.c | 15 ---------------
- target/riscv/pmp.h       |  8 ++--
+ target/riscv/kvm.c | 21 +++++++++++++++++++++
- target/riscv/csr.c       | 80 ++++++++++++++++++++++++++++++++++++++++
+files changed, 21 insertions(+), 15 deletions(-)
  target/riscv/op_helper.c |  9 +++++
 files changed, 103 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
  #define CSR_VSPMMASK        0x2c1
  #define CSR_VSPMBASE        0x2c2
 +/* Crypto Extension */
 +#define CSR_SEED            0x015
 +
  /* mstatus CSR bits */
  #define MSTATUS_UIE         0x00000001
  #define MSTATUS_SIE         0x00000002
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
  #define HVICTL_VALID_MASK                  \
      (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
 +/* seed CSR bits */
 +#define SEED_OPST                        (0b11 << 30)
 +#define SEED_OPST_BIST                   (0b00 << 30)
 +#define SEED_OPST_WAIT                   (0b01 << 30)
 +#define SEED_OPST_ES16                   (0b10 << 30)
 +#define SEED_OPST_DEAD                   (0b11 << 30)
  #endif
 diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.h
 +++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  } pmp_am_t;
  typedef enum {
 -    MSECCFG_MML  = 1 << 0,
 -    MSECCFG_MMWP = 1 << 1,
 -    MSECCFG_RLB  = 1 << 2
 +    MSECCFG_MML   = 1 << 0,
 +    MSECCFG_MMWP  = 1 << 1,
 +    MSECCFG_RLB   = 1 << 2,
 +    MSECCFG_USEED = 1 << 8,
 +    MSECCFG_SSEED = 1 << 9
  } mseccfg_field_t;
  typedef struct {
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/main-loop.h"
  #include "exec/exec-all.h"
  #include "sysemu/cpu-timers.h"
 +#include "qemu/guest-random.h"
 +#include "qapi/error.h"
  /* CSR function table public API */
  void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
@@ -XXX,XX +XXX,XX @@ static RISCVException debug(CPURISCVState *env, int csrno)
  }
  #endif
-+static RISCVException seed(CPURISCVState *env, int csrno)
+-#if defined(CONFIG_KVM)
 -static void riscv_host_cpu_init(Object *obj)
 -{
 -    CPURISCVState *env = &RISCV_CPU(obj)->env;
 -#if defined(TARGET_RISCV32)
 -    set_misa(env, MXL_RV32, 0);
 -#elif defined(TARGET_RISCV64)
 -    set_misa(env, MXL_RV64, 0);
 -#endif
 -}
 -#endif /* CONFIG_KVM */
 -
  static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
  {
      ObjectClass *oc;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
      },
      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,      riscv_max_cpu_init),
 -#if defined(CONFIG_KVM)
 -    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
 -#endif
  #if defined(TARGET_RISCV32)
      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32,   rv32_base_cpu_init),
      DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
      kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
  }
 +
 +static void riscv_host_cpu_init(Object *obj)
 +{
-+    RISCVCPU *cpu = env_archcpu(env);
++    CPURISCVState *env = &RISCV_CPU(obj)->env;
 +
-+    if (!cpu->cfg.ext_zkr) {
++#if defined(TARGET_RISCV32)
-+        return RISCV_EXCP_ILLEGAL_INST;
++    env->misa_mxl_max = env->misa_mxl = MXL_RV32;
-+    }
++#elif defined(TARGET_RISCV64)
-+
++    env->misa_mxl_max = env->misa_mxl = MXL_RV64;
 +#if !defined(CONFIG_USER_ONLY)
 +    /*
 +     * With a CSR read-write instruction:
 +     * 1) The seed CSR is always available in machine mode as normal.
 +     * 2) Attempted access to seed from virtual modes VS and VU always raises
 +     * an exception(virtual instruction exception only if mseccfg.sseed=1).
 +     * 3) Without the corresponding access control bit set to 1, any attempted
 +     * access to seed from U, S or HS modes will raise an illegal instruction
 +     * exception.
 +     */
 +    if (env->priv == PRV_M) {
 +        return RISCV_EXCP_NONE;
 +    } else if (riscv_cpu_virt_enabled(env)) {
 +        if (env->mseccfg & MSECCFG_SSEED) {
 +            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +        } else {
 +            return RISCV_EXCP_ILLEGAL_INST;
 +        }
 +    } else {
 +        if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
 +            return RISCV_EXCP_NONE;
 +        } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
 +            return RISCV_EXCP_NONE;
 +        } else {
 +            return RISCV_EXCP_ILLEGAL_INST;
 +        }
 +    }
 +#else
 +    return RISCV_EXCP_NONE;
 +#endif
 +}
 +
- /* User Floating-Point CSRs */
++static const TypeInfo riscv_kvm_cpu_type_infos[] = {
- static RISCVException read_fflags(CPURISCVState *env, int csrno,
++    {
-                                   target_ulong *val)
++        .name = TYPE_RISCV_CPU_HOST,
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
++        .parent = TYPE_RISCV_CPU,
++        .instance_init = riscv_host_cpu_init,
- #endif
++    }
++};
 +/* Crypto Extension */
 +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 +                               target_ulong *ret_value,
 +                               target_ulong new_value,
 +                               target_ulong write_mask)
 +{
 +    uint16_t random_v;
 +    Error *random_e = NULL;
 +    int random_r;
 +    target_ulong rval;
 +
-+    random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
++DEFINE_TYPES(riscv_kvm_cpu_type_infos)
 +    if (unlikely(random_r < 0)) {
 +        /*
 +         * Failed, for unknown reasons in the crypto subsystem.
 +         * The best we can do is log the reason and return a
 +         * failure indication to the guest.  There is no reason
 +         * we know to expect the failure to be transitory, so
 +         * indicate DEAD to avoid having the guest spin on WAIT.
 +         */
 +        qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
 +                      __func__, error_get_pretty(random_e));
 +        error_free(random_e);
 +        rval = SEED_OPST_DEAD;
 +    } else {
 +        rval = random_v | SEED_OPST_ES16;
 +    }
 +
 +    if (ret_value) {
 +        *ret_value = rval;
 +    }
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
  /*
   * riscv_csrrw - read and/or update control and status register
   *
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_TIME]  = { "time",  ctr,   read_time  },
      [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
 +    /* Crypto Extension */
 +    [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed },
 +
  #if !defined(CONFIG_USER_ONLY)
      /* Machine Timers and Counters */
      [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_raise_exception(CPURISCVState *env, uint32_t exception)
  target_ulong helper_csrr(CPURISCVState *env, int csr)
  {
 +    /*
 +     * The seed CSR must be accessed with a read-write instruction. A
 +     * read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/
 +     * CSRRCI with uimm=0 will raise an illegal instruction exception.
 +     */
 +    if (csr == CSR_SEED) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +
      target_ulong val = 0;
      RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
 --
-.35.1
+.41.0

-[PULL 17/25] target/riscv: rvk: expose zbk* and zk* properties
+[PULL 29/54] target/riscv/cpu.c: mark extensions arrays as 'const'
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+We'll need to export these arrays to the accelerator classes in the next
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+patches. Mark them as 'const' now because they should not be modified at
 runtime.
 Note that 'riscv_cpu_options' will also be exported, but can't be marked
 as 'const', because the properties are changed via
 qdev_property_add_static().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn>
+Message-ID: <20230925175709.35696-8-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 13 +++++++++++++
+ target/riscv/cpu.c | 22 +++++++++++++---------
-file changed, 13 insertions(+)
+file changed, 13 insertions(+), 9 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPUMultiExtConfig {
-     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
+     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
-     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
+      .enabled = _defval}
-     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
-+    DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+-static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-+    DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
++static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-+    DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
+     /* Defaults for standard extensions */
-     DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
-+    DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+     MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
-+    DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+@@ -XXX,XX +XXX,XX @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-+    DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+     DEFINE_PROP_END_OF_LIST(),
-+    DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+ };
-+    DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
-+    DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+-static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
-+    DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
++static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
-+    DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
-+    DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
-+    DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
+     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
+@@ -XXX,XX +XXX,XX @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
-     DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
+ };
-     DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
  /* These are experimental so mark with 'x-' */
 -static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
 +static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
      /* ePMP 0.9.3 */
      MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
      MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -XXX,XX +XXX,XX @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
  }
  static void cpu_add_multi_ext_prop(Object *cpu_obj,
 -                                   RISCVCPUMultiExtConfig *multi_cfg)
 +                                   const RISCVCPUMultiExtConfig *multi_cfg)
  {
      object_property_add(cpu_obj, multi_cfg->name, "bool",
                          cpu_get_multi_ext_cfg,
@@ -XXX,XX +XXX,XX @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
  }
  static void riscv_cpu_add_multiext_prop_array(Object *obj,
 -                                              RISCVCPUMultiExtConfig *array)
 +                                        const RISCVCPUMultiExtConfig *array)
  {
 +    const RISCVCPUMultiExtConfig *prop;
 +
      g_assert(array);
 -    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
 +    for (prop = array; prop && prop->name; prop++) {
          cpu_add_multi_ext_prop(obj, prop);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
  }
  static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
 -                                                 RISCVCPUMultiExtConfig *array)
 +                                        const RISCVCPUMultiExtConfig *array)
  {
 +    const RISCVCPUMultiExtConfig *prop;
 +
      g_assert(array);
 -    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
 +    for (prop = array; prop && prop->name; prop++) {
          riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
  {
      RISCVCPU *cpu = RISCV_CPU(obj);
      CPURISCVState *env = &cpu->env;
 -    RISCVCPUMultiExtConfig *prop;
 +    const RISCVCPUMultiExtConfig *prop;
      /* Enable RVG, RVJ and RVV that are disabled by default */
      set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 --
-.35.1
+.41.0

-[PULL 11/25] target/riscv: rvk: add support for sha256 related instructions in zknh extension
+[PULL 30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
+We'll introduce the KVM accelerator class with a 'cpu_instance_init'
+implementation that is going to be invoked during the common
-Co-authored-by: Zewen Ye <lustrew@foxmail.com>
+riscv_cpu_post_init() (via accel_cpu_instance_init()). This
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+instance_init will execute KVM exclusive code that TCG doesn't care
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+about, such as adding KVM specific properties, initing registers using a
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+KVM scratch CPU and so on.
 The core of the forementioned cpu_instance_init impl is the current
 riscv_cpu_add_kvm_properties() that is being used by the common code via
 riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together
 will all the relevant artifacts, exporting and renaming it to
 kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now.
 To make this work we'll need to export riscv_cpu_extensions,
 riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as
 well. The TCG accelerator will also need to access those in the near
 future so this export will benefit us in the long run.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220423023510.30794-9-liweiwei@iscas.ac.cn>
+Message-ID: <20230925175709.35696-9-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              |  5 +++
+ target/riscv/cpu.h       | 14 +++++++
- target/riscv/insn_trans/trans_rvk.c.inc | 55 +++++++++++++++++++++++++
+ target/riscv/kvm_riscv.h |  3 --
-files changed, 60 insertions(+)
+ target/riscv/cpu.c       | 85 +++-------------------------------------
+ target/riscv/kvm.c       | 68 +++++++++++++++++++++++++++++++-
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+files changed, 86 insertions(+), 84 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ aes64esm    00 11011 ..... ..... 000 ..... 0110011 @r
+@@ -XXX,XX +XXX,XX @@
- # *** RV64 Zkne/zknd Standard Extension ***
- aes64ks2    01 11111 ..... ..... 000 ..... 0110011 @r
+ #include "hw/core/cpu.h"
- aes64ks1i   00 11000 1.... ..... 001 ..... 0010011 @i_aes
+ #include "hw/registerfields.h"
-+# *** RV32 Zknh Standard Extension ***
++#include "hw/qdev-properties.h"
-+sha256sig0  00 01000 00010 ..... 001 ..... 0010011 @r2
+ #include "exec/cpu-defs.h"
-+sha256sig1  00 01000 00011 ..... 001 ..... 0010011 @r2
+ #include "qemu/cpu-float.h"
-+sha256sum0  00 01000 00000 ..... 001 ..... 0010011 @r2
+ #include "qom/object.h"
-+sha256sum1  00 01000 00001 ..... 001 ..... 0010011 @r2
+@@ -XXX,XX +XXX,XX @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
-diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
+ int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
  void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
 +typedef struct RISCVCPUMultiExtConfig {
 +    const char *name;
 +    uint32_t offset;
 +    bool enabled;
 +} RISCVCPUMultiExtConfig;
 +
 +extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
 +extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
 +extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 +extern Property riscv_cpu_options[];
 +
 +void riscv_cpu_add_misa_properties(Object *cpu_obj);
 +
  /* CSR function table */
  extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvk.c.inc
+--- a/target/riscv/kvm_riscv.h
-+++ b/target/riscv/insn_trans/trans_rvk.c.inc
++++ b/target/riscv/kvm_riscv.h
 @@ -XXX,XX +XXX,XX @@
-     }                                           \
+ #ifndef QEMU_KVM_RISCV_H
- } while (0)
+ #define QEMU_KVM_RISCV_H
-+#define REQUIRE_ZKNH(ctx) do {                  \
+-/* Temporarily implemented in cpu.c */
-+    if (!ctx->cfg_ptr->ext_zknh) {              \
+ void kvm_riscv_cpu_add_kvm_properties(Object *obj);
-+        return false;                           \
+-
-+    }                                           \
+-void kvm_riscv_init_user_properties(Object *cpu_obj);
-+} while (0)
+ void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
-+
+ void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
- static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
+ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-                           void (*func)(TCGv, TCGv, TCGv, TCGv))
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
   * change MISA bits during realize() (RVG enables MISA
   * bits but the user is warned about it).
   */
 -static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 +void riscv_cpu_add_misa_properties(Object *cpu_obj)
  {
-@@ -XXX,XX +XXX,XX @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
+     int i;
-     REQUIRE_ZKND(ctx);
-     return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
- }
+     }
-+
+ }
-+static bool gen_sha256(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
-+                       void (*func)(TCGv_i32, TCGv_i32, int32_t),
+-typedef struct RISCVCPUMultiExtConfig {
-+                       int32_t num1, int32_t num2, int32_t num3)
+-    const char *name;
 -    uint32_t offset;
 -    bool enabled;
 -} RISCVCPUMultiExtConfig;
 -
  #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
      {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
       .enabled = _defval}
 -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
 +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      /* Defaults for standard extensions */
      MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
      MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
 -static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 +const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
      MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
      MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
      MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
  };
  /* These are experimental so mark with 'x-' */
 -static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
 +const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
      /* ePMP 0.9.3 */
      MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
      MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
 -static Property riscv_cpu_options[] = {
 +Property riscv_cpu_options[] = {
      DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
      DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
      }
  }
 -#ifdef CONFIG_KVM
 -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
 -                                    const char *name,
 -                                    void *opaque, Error **errp)
 -{
 -    const char *propname = opaque;
 -    bool value;
 -
 -    if (!visit_type_bool(v, name, &value, errp)) {
 -        return;
 -    }
 -
 -    if (value) {
 -        error_setg(errp, "extension %s is not available with KVM",
 -                   propname);
 -    }
 -}
 -
 -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
 -{
 -    /* Check if KVM created the property already */
 -    if (object_property_find(obj, prop_name)) {
 -        return;
 -    }
 -
 -    /*
 -     * Set the default to disabled for every extension
 -     * unknown to KVM and error out if the user attempts
 -     * to enable any of them.
 -     */
 -    object_property_add(obj, prop_name, "bool",
 -                        NULL, cpu_set_cfg_unavailable,
 -                        NULL, (void *)prop_name);
 -}
 -
 -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
 -                                        const RISCVCPUMultiExtConfig *array)
 -{
 -    const RISCVCPUMultiExtConfig *prop;
 -
 -    g_assert(array);
 -
 -    for (prop = array; prop && prop->name; prop++) {
 -        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
 -    }
 -}
 -
 -void kvm_riscv_cpu_add_kvm_properties(Object *obj)
 -{
 -    Property *prop;
 -    DeviceState *dev = DEVICE(obj);
 -
 -    kvm_riscv_init_user_properties(obj);
 -    riscv_cpu_add_misa_properties(obj);
 -
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 -
 -    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
 -        /* Check if KVM created the property already */
 -        if (object_property_find(obj, prop->name)) {
 -            continue;
 -        }
 -        qdev_property_add_static(dev, prop);
 -    }
 -}
 -#endif
 -
  /*
   * Add CPU properties with user-facing flags.
   *
 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm.c
 +++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
      }
  }
 +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
 +                                    const char *name,
 +                                    void *opaque, Error **errp)
 +{
-+    TCGv dest = dest_gpr(ctx, a->rd);
++    const char *propname = opaque;
-+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
++    bool value;
-+    TCGv_i32 t0 = tcg_temp_new_i32();
++
-+    TCGv_i32 t1 = tcg_temp_new_i32();
++    if (!visit_type_bool(v, name, &value, errp)) {
-+    TCGv_i32 t2 = tcg_temp_new_i32();
++        return;
-+
++    }
-+    tcg_gen_trunc_tl_i32(t0, src1);
++
-+    tcg_gen_rotri_i32(t1, t0, num1);
++    if (value) {
-+    tcg_gen_rotri_i32(t2, t0, num2);
++        error_setg(errp, "extension %s is not available with KVM",
-+    tcg_gen_xor_i32(t1, t1, t2);
++                   propname);
-+    func(t2, t0, num3);
++    }
 +    tcg_gen_xor_i32(t1, t1, t2);
 +    tcg_gen_ext_i32_tl(dest, t1);
 +
 +    gen_set_gpr(ctx, a->rd, dest);
 +    tcg_temp_free_i32(t0);
 +    tcg_temp_free_i32(t1);
 +    tcg_temp_free_i32(t2);
 +    return true;
 +}
 +
-+static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
++static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
 +{
-+    REQUIRE_ZKNH(ctx);
++    /* Check if KVM created the property already */
-+    return gen_sha256(ctx, a, EXT_NONE, tcg_gen_shri_i32, 7, 18, 3);
++    if (object_property_find(obj, prop_name)) {
 +        return;
 +    }
 +
 +    /*
 +     * Set the default to disabled for every extension
 +     * unknown to KVM and error out if the user attempts
 +     * to enable any of them.
 +     */
 +    object_property_add(obj, prop_name, "bool",
 +                        NULL, cpu_set_cfg_unavailable,
 +                        NULL, (void *)prop_name);
 +}
 +
-+static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a)
++static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
 +                                        const RISCVCPUMultiExtConfig *array)
 +{
-+    REQUIRE_ZKNH(ctx);
++    const RISCVCPUMultiExtConfig *prop;
-+    return gen_sha256(ctx, a, EXT_NONE, tcg_gen_shri_i32, 17, 19, 10);
++
 +    g_assert(array);
 +
 +    for (prop = array; prop && prop->name; prop++) {
 +        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
 +    }
 +}
 +
-+static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a)
+ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
  {
      int i;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      }
  }
 -void kvm_riscv_init_user_properties(Object *cpu_obj)
 +static void riscv_init_user_properties(Object *cpu_obj)
  {
      RISCVCPU *cpu = RISCV_CPU(cpu_obj);
      KVMScratchCPU kvmcpu;
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
      kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
  }
 +void kvm_riscv_cpu_add_kvm_properties(Object *obj)
 +{
-+    REQUIRE_ZKNH(ctx);
++    DeviceState *dev = DEVICE(obj);
-+    return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 2, 13, 22);
++
 +    riscv_init_user_properties(obj);
 +    riscv_cpu_add_misa_properties(obj);
 +
 +    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
 +    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
 +    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 +
 +    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
 +        /* Check if KVM created the property already */
 +        if (object_property_find(obj, prop->name)) {
 +            continue;
 +        }
 +        qdev_property_add_static(dev, prop);
 +    }
 +}
 +
-+static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
+ static void riscv_host_cpu_init(Object *obj)
-+{
+ {
-+    REQUIRE_ZKNH(ctx);
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
 +    return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 6, 11, 25);
 +}
 --
-.35.1
+.41.0

-New patch
+[PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+This function is used for both accelerators. Make it public, and call it
+from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
+split KVM specific code for the KVM accelerator class in the next patch.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230925175709.35696-10-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h | 1 +
+ target/riscv/cpu.c | 5 ++---
+ target/riscv/kvm.c | 1 +
+files changed, 4 insertions(+), 3 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+ extern Property riscv_cpu_options[];
+ void riscv_cpu_add_misa_properties(Object *cpu_obj);
++void riscv_add_satp_mode_properties(Object *obj);
+ /* CSR function table */
+ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
+     satp_map->init |= 1 << satp;
+ }
+-static void riscv_add_satp_mode_properties(Object *obj)
++void riscv_add_satp_mode_properties(Object *obj)
+ {
+     RISCVCPU *cpu = RISCV_CPU(obj);
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
+ static void riscv_cpu_add_user_properties(Object *obj)
+ {
+ #ifndef CONFIG_USER_ONLY
+-    riscv_add_satp_mode_properties(obj);
+-
+     if (kvm_enabled()) {
+         kvm_riscv_cpu_add_kvm_properties(obj);
+         return;
+     }
++    riscv_add_satp_mode_properties(obj);
+ #endif
+     riscv_cpu_add_misa_properties(obj);
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm.c
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+     DeviceState *dev = DEVICE(obj);
+     riscv_init_user_properties(obj);
++    riscv_add_satp_mode_properties(obj);
+     riscv_cpu_add_misa_properties(obj);
+     riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
+--
+.41.0

-New patch
+[PULL 32/54] target/riscv: remove kvm-stub.c
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+This file is not needed for some time now. Both kvm_riscv_reset_vcpu()
+and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are
+wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out
+in non-KVM builds.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm-stub.c  | 30 ------------------------------
+ target/riscv/meson.build |  2 +-
+files changed, 1 insertion(+), 31 deletions(-)
+ delete mode 100644 target/riscv/kvm-stub.c
+diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
+deleted file mode 100644
+index XXXXXXX..XXXXXXX
+--- a/target/riscv/kvm-stub.c
++++ /dev/null
+@@ -XXX,XX +XXX,XX @@
+-/*
+- * QEMU KVM RISC-V specific function stubs
+- *
+- * Copyright (c) 2020 Huawei Technologies Co., Ltd
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2 or later, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
+- */
+-#include "qemu/osdep.h"
+-#include "cpu.h"
+-#include "kvm_riscv.h"
+-
+-void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+-{
+-    abort();
+-}
+-
+-void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+-{
+-    abort();
+-}
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/meson.build
++++ b/target/riscv/meson.build
+@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
+   'zce_helper.c',
+   'vcrypto_helper.c'
+ ))
+-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
++riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+ riscv_system_ss = ss.source_set()
+ riscv_system_ss.add(files(
+--
+.41.0

-New patch
+[PULL 33/54] target/riscv: introduce KVM AccelCPUClass
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Add a KVM accelerator class like we did with TCG. The difference is
+that, at least for now, we won't be using a realize() implementation for
+this accelerator.
+We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
+kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change
+riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go
+through the 'cpu_instance_init' impl of the current acceleration (if
+available) and execute it. The end result is that the KVM initial setup,
+i.e. starting registers and adding its specific properties, will be done
+via this hook.
+Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid
+calling riscv_cpu_add_user_properties() when running KVM. We'll remove
+this condition when the TCG accel class get its own 'cpu_instance_init'
+implementation.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230925175709.35696-12-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm_riscv.h |  1 -
+ target/riscv/cpu.c       |  8 +++-----
+ target/riscv/kvm.c       | 26 ++++++++++++++++++++++++--
+files changed, 27 insertions(+), 8 deletions(-)
+diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm_riscv.h
++++ b/target/riscv/kvm_riscv.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef QEMU_KVM_RISCV_H
+ #define QEMU_KVM_RISCV_H
+-void kvm_riscv_cpu_add_kvm_properties(Object *obj);
+ void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+ void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
+ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+ static void riscv_cpu_post_init(Object *obj)
+ {
+-    if (riscv_cpu_has_user_properties(obj)) {
++    accel_cpu_instance_init(CPU(obj));
++
++    if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
+         riscv_cpu_add_user_properties(obj);
+     }
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
+ static void riscv_cpu_add_user_properties(Object *obj)
+ {
+ #ifndef CONFIG_USER_ONLY
+-    if (kvm_enabled()) {
+-        kvm_riscv_cpu_add_kvm_properties(obj);
+-        return;
+-    }
+     riscv_add_satp_mode_properties(obj);
+ #endif
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm.c
++++ b/target/riscv/kvm.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/kvm_int.h"
+ #include "cpu.h"
+ #include "trace.h"
++#include "hw/core/accel-cpu.h"
+ #include "hw/pci/pci.h"
+ #include "exec/memattrs.h"
+ #include "exec/address-spaces.h"
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
+ }
+-void kvm_riscv_cpu_add_kvm_properties(Object *obj)
++static void kvm_cpu_instance_init(CPUState *cs)
+ {
++    Object *obj = OBJECT(RISCV_CPU(cs));
+     DeviceState *dev = DEVICE(obj);
+     riscv_init_user_properties(obj);
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+     riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
+     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+-        /* Check if KVM created the property already */
++        /* Check if we have a specific KVM handler for the option */
+         if (object_property_find(obj, prop->name)) {
+             continue;
+         }
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+     }
+ }
++static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
++{
++    AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
++
++    acc->cpu_instance_init = kvm_cpu_instance_init;
++}
++
++static const TypeInfo kvm_cpu_accel_type_info = {
++    .name = ACCEL_CPU_NAME("kvm"),
++
++    .parent = TYPE_ACCEL_CPU,
++    .class_init = kvm_cpu_accel_class_init,
++    .abstract = true,
++};
++static void kvm_cpu_accel_register_types(void)
++{
++    type_register_static(&kvm_cpu_accel_type_info);
++}
++type_init(kvm_cpu_accel_register_types);
++
+ static void riscv_host_cpu_init(Object *obj)
+ {
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+--
+.41.0

-[PULL 23/25] hw/riscv: virt: Add support for generating platform FDT entries
+[PULL 34/54] target/riscv: move KVM only files to kvm subdir
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Similar to the ARM virt machine add support for adding device tree
+Move the files to a 'kvm' dir to promote more code separation between
-entries for dynamically created devices.
+accelerators and making our lives easier supporting build options such
 as --disable-tcg.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
-Message-Id: <20220427234146.1130752-5-alistair.francis@opensource.wdc.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 19 +++++++++++++++++++
+ target/riscv/{ => kvm}/kvm_riscv.h    | 0
-file changed, 19 insertions(+)
+ hw/intc/riscv_aplic.c                 | 2 +-
  hw/riscv/virt.c                       | 2 +-
  target/riscv/cpu.c                    | 2 +-
  target/riscv/{kvm.c => kvm/kvm-cpu.c} | 0
  target/riscv/kvm/meson.build          | 1 +
  target/riscv/meson.build              | 2 +-
 files changed, 5 insertions(+), 4 deletions(-)
  rename target/riscv/{ => kvm}/kvm_riscv.h (100%)
  rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (100%)
  create mode 100644 target/riscv/kvm/meson.build
+diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h
+similarity index 100%
+rename from target/riscv/kvm_riscv.h
+rename to target/riscv/kvm/kvm_riscv.h
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/riscv_aplic.c
++++ b/hw/intc/riscv_aplic.c
+@@ -XXX,XX +XXX,XX @@
+ #include "target/riscv/cpu.h"
+ #include "sysemu/sysemu.h"
+ #include "sysemu/kvm.h"
+-#include "kvm_riscv.h"
++#include "kvm/kvm_riscv.h"
+ #include "migration/vmstate.h"
+ #define APLIC_MAX_IDC                  (1UL << 14)
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/qdev-properties.h"
- #include "hw/char/serial.h"
- #include "target/riscv/cpu.h"
-+#include "hw/core/sysbus-fdt.h"
- #include "hw/riscv/riscv_hart.h"
  #include "hw/riscv/virt.h"
  #include "hw/riscv/boot.h"
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
+ #include "hw/riscv/numa.h"
-     riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
+-#include "kvm_riscv.h"
-     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
++#include "kvm/kvm_riscv.h"
-         plic_phandles[socket]);
+ #include "hw/intc/riscv_aclint.h"
-+
+ #include "hw/intc/riscv_aplic.h"
-+    platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+ #include "hw/intc/riscv_imsic.h"
-+                                   memmap[VIRT_PLATFORM_BUS].base,
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-+                                   memmap[VIRT_PLATFORM_BUS].size,
+index XXXXXXX..XXXXXXX 100644
-+                                   VIRT_PLATFORM_BUS_IRQ);
+--- a/target/riscv/cpu.c
-+
++++ b/target/riscv/cpu.c
-     g_free(plic_name);
+@@ -XXX,XX +XXX,XX @@
+ #include "fpu/softfloat-helpers.h"
-     g_free(plic_cells);
+ #include "sysemu/kvm.h"
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+ #include "sysemu/tcg.h"
-             IMSIC_MMIO_GROUP_MIN_SHIFT);
+-#include "kvm_riscv.h"
-     }
++#include "kvm/kvm_riscv.h"
-     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
+ #include "tcg/tcg.h"
-+
-+    platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
+ /* RISC-V CPU definitions */
-+                                   memmap[VIRT_PLATFORM_BUS].base,
+diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c
-+                                   memmap[VIRT_PLATFORM_BUS].size,
+similarity index 100%
-+                                   VIRT_PLATFORM_BUS_IRQ);
+rename from target/riscv/kvm.c
-+
+rename to target/riscv/kvm/kvm-cpu.c
-     g_free(imsic_name);
+diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
+new file mode 100644
-     /* S-level IMSIC node */
+index XXXXXXX..XXXXXXX
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
+--- /dev/null
-         VIRT_IRQCHIP_NUM_SOURCES);
++++ b/target/riscv/kvm/meson.build
-     riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
+@@ -0,0 +1 @@
-     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
++riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))
-+
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
-+    platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+index XXXXXXX..XXXXXXX 100644
-+                                   memmap[VIRT_PLATFORM_BUS].base,
+--- a/target/riscv/meson.build
-+                                   memmap[VIRT_PLATFORM_BUS].size,
++++ b/target/riscv/meson.build
-+                                   VIRT_PLATFORM_BUS_IRQ);
+@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
-+
+   'zce_helper.c',
-     g_free(aplic_name);
+   'vcrypto_helper.c'
+ ))
-     g_free(aplic_cells);
+-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
  riscv_system_ss = ss.source_set()
  riscv_system_ss.add(files(
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
  ))
  subdir('tcg')
 +subdir('kvm')
  target_arch += {'riscv': riscv_ss}
  target_system_arch += {'riscv': riscv_system_ss}
 --
-.35.1
+.41.0

-[PULL 03/25] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
+[PULL 35/54] target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
-From: Frank Chang <frank.chang@sifive.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Allow user to set core's marchid, mvendorid, mipid CSRs through
+riscv_cpu_add_misa_properties() is being used to fill the missing KVM
--cpu command line option.
+MISA properties but it is a TCG helper that was adapted to do so. We'll
 move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
 the remaining MISA properties on its own.
-The default values of marchid and mipid are built with QEMU's version
+Do not use riscv_cpu_add_misa_properties(). Let's create a new array
-numbers.
+with all available MISA bits we support that can be read by KVM. The
 array is zero terminate to allow us to iterate through it without
 knowing its size.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM
-Reviewed-by: Jim Shu <jim.shu@sifive.com>
+MISA properties as usual and then use this array to add any missing MISA
 properties with the riscv_cpu_add_kvm_unavail_prop() helper.
 Note that we're creating misa_bits[], and not using the existing
 'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa
 related functions and it doesn't have all MISA bits we support. Commit
 e2c377023 ("target/riscv: misa to ISA string conversion fix") has the
 full context.
 While we're at it, move both satp and the multi-letter extension
 properties to kvm_riscv_add_cpu_user_properties() as well.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-ID: <20230925175709.35696-14-dbarboza@ventanamicro.com>
 Message-Id: <20220422040436.2233-1-frank.chang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h |  4 ++++
+ target/riscv/cpu.h         |  3 ++-
- target/riscv/cpu.c |  9 +++++++++
+ target/riscv/cpu.c         |  2 ++
- target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
+ target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++--------
-files changed, 47 insertions(+), 4 deletions(-)
+files changed, 18 insertions(+), 9 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@
-     bool ext_zve32f;
+ #define RV(x) ((target_ulong)1 << (x - 'A'))
-     bool ext_zve64f;
+ /*
-+    uint32_t mvendorid;
+- * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[]
-+    uint64_t marchid;
++ * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
-+    uint64_t mipid;
+  * when adding new MISA bits here.
-+
+  */
-     /* Vendor-specific custom extensions */
+ #define RVI RV('I')
-     bool ext_XVentanaCondOps;
+@@ -XXX,XX +XXX,XX @@
  #define RVJ RV('J')
  #define RVG RV('G')
 +extern const uint32_t misa_bits[];
  const char *riscv_get_misa_ext_name(uint32_t bit);
  const char *riscv_get_misa_ext_description(uint32_t bit);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
 @@ -XXX,XX +XXX,XX @@
  /* RISC-V CPU definitions */
+ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
-+#define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
++const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
-+                             (QEMU_VERSION_MINOR << 8)  | \
++                              RVC, RVS, RVU, RVH, RVJ, RVG, 0};
-+                             (QEMU_VERSION_MICRO))
-+#define RISCV_CPU_MIPID     RISCV_CPU_MARCHID
+ struct isa_ext_data {
      const char *name;
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
  {
      int i;
 +    riscv_add_satp_mode_properties(cpu_obj);
 +
- static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
+     for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) {
+         KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i];
- struct isa_ext_data {
+         int bit = misa_cfg->offset;
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
-     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+                                         misa_cfg->description);
-     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+     }
-+    DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
++    for (i = 0; misa_bits[i] != 0; i++) {
-+    DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
++        const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]);
-+    DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
++        riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name);
 +    }
 +
-     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
+     for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
-     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+         KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i];
-     DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
-index XXXXXXX..XXXXXXX 100644
+     object_property_add(cpu_obj, "cboz_blocksize", "uint16",
---- a/target/riscv/csr.c
+                         NULL, kvm_cpu_set_cbomz_blksize,
-+++ b/target/riscv/csr.c
+                         NULL, &kvm_cboz_blocksize);
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
++
-     return RISCV_EXCP_NONE;
++    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions);
 +    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts);
 +    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts);
  }
-+static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
+ static int kvm_riscv_get_regs_core(CPUState *cs)
-+                                     target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
-+{
+     }
-+    CPUState *cs = env_cpu(env);
+ }
-+    RISCVCPU *cpu = RISCV_CPU(cs);
-+
+-static void riscv_init_user_properties(Object *cpu_obj)
-+    *val = cpu->cfg.mvendorid;
++static void riscv_init_kvm_registers(Object *cpu_obj)
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException read_marchid(CPURISCVState *env, int csrno,
 +                                   target_ulong *val)
 +{
 +    CPUState *cs = env_cpu(env);
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +
 +    *val = cpu->cfg.marchid;
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException read_mipid(CPURISCVState *env, int csrno,
 +                                 target_ulong *val)
 +{
 +    CPUState *cs = env_cpu(env);
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +
 +    *val = cpu->cfg.mipid;
 +    return RISCV_EXCP_NONE;
 +}
 +
  static RISCVException read_mhartid(CPURISCVState *env, int csrno,
                                     target_ulong *val)
  {
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
+     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
-     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
+     KVMScratchCPU kvmcpu;
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_user_properties(Object *cpu_obj)
-     /* Machine Information Registers */
+         return;
--    [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
+     }
--    [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
--    [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
+-    kvm_riscv_add_cpu_user_properties(cpu_obj);
--    [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
+     kvm_riscv_init_machine_ids(cpu, &kvmcpu);
-+    [CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
+     kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
-+    [CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
+     kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
-+    [CSR_MIMPID]    = { "mimpid",    any,   read_mipid     },
+@@ -XXX,XX +XXX,XX @@ static void kvm_cpu_instance_init(CPUState *cs)
-+    [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
+     Object *obj = OBJECT(RISCV_CPU(cs));
+     DeviceState *dev = DEVICE(obj);
-     [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
-                                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+-    riscv_init_user_properties(obj);
 -    riscv_add_satp_mode_properties(obj);
 -    riscv_cpu_add_misa_properties(obj);
 +    riscv_init_kvm_registers(obj);
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
 -    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 +    kvm_riscv_add_cpu_user_properties(obj);
      for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
          /* Check if we have a specific KVM handler for the option */
 --
-.35.1
+.41.0

-New patch
+[PULL 36/54] target/riscv/cpu.c: export set_misa()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
+patch and set_misa() needs to be usable from there.
+Rename it to riscv_cpu_set_misa() and make it public.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230925175709.35696-15-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h |  1 +
+ target/riscv/cpu.c | 34 ++++++++++++++++++----------------
+files changed, 19 insertions(+), 16 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
+ bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
+ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
+ int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
++void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
+ void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
+ typedef struct RISCVCPUMultiExtConfig {
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+     }
+ }
+-static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
++void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+ {
+     env->misa_mxl_max = env->misa_mxl = mxl;
+     env->misa_ext_mask = env->misa_ext = ext;
+@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
+     RISCVCPU *cpu = RISCV_CPU(obj);
+     CPURISCVState *env = &cpu->env;
+ #if defined(TARGET_RISCV32)
+-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
++    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ #elif defined(TARGET_RISCV64)
+-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
++    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ #endif
+ #ifndef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ static void riscv_max_cpu_init(Object *obj)
+ #ifdef TARGET_RISCV32
+     mlx = MXL_RV32;
+ #endif
+-    set_misa(env, mlx, 0);
++    riscv_cpu_set_misa(env, mlx, 0);
+     env->priv_ver = PRIV_VERSION_LATEST;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
+@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
+ {
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     /* We set this in the realise function */
+-    set_misa(env, MXL_RV64, 0);
++    riscv_cpu_set_misa(env, MXL_RV64, 0);
+     /* Set latest version of privileged specification */
+     env->priv_ver = PRIV_VERSION_LATEST;
+ #ifndef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
+ {
+     RISCVCPU *cpu = RISCV_CPU(obj);
+     CPURISCVState *env = &cpu->env;
+-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
++    riscv_cpu_set_misa(env, MXL_RV64,
++                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+     env->priv_ver = PRIV_VERSION_1_10_0;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
+@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     RISCVCPU *cpu = RISCV_CPU(obj);
+-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
++    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+     env->priv_ver = PRIV_VERSION_1_10_0;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
+@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     RISCVCPU *cpu = RISCV_CPU(obj);
+-    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
++    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
+     env->priv_ver = PRIV_VERSION_1_11_0;
+     cpu->cfg.ext_zfa = true;
+@@ -XXX,XX +XXX,XX @@ static void rv64_veyron_v1_cpu_init(Object *obj)
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     RISCVCPU *cpu = RISCV_CPU(obj);
+-    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
++    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
+     env->priv_ver = PRIV_VERSION_1_12_0;
+     /* Enable ISA extensions */
+@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
+     }
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     /* We set this in the realise function */
+-    set_misa(env, MXL_RV128, 0);
++    riscv_cpu_set_misa(env, MXL_RV128, 0);
+     /* Set latest version of privileged specification */
+     env->priv_ver = PRIV_VERSION_LATEST;
+ #ifndef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
+ {
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     /* We set this in the realise function */
+-    set_misa(env, MXL_RV32, 0);
++    riscv_cpu_set_misa(env, MXL_RV32, 0);
+     /* Set latest version of privileged specification */
+     env->priv_ver = PRIV_VERSION_LATEST;
+ #ifndef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
+ {
+     RISCVCPU *cpu = RISCV_CPU(obj);
+     CPURISCVState *env = &cpu->env;
+-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
++    riscv_cpu_set_misa(env, MXL_RV32,
++                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+     env->priv_ver = PRIV_VERSION_1_10_0;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
+@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     RISCVCPU *cpu = RISCV_CPU(obj);
+-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
++    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
+     env->priv_ver = PRIV_VERSION_1_10_0;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
+@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     RISCVCPU *cpu = RISCV_CPU(obj);
+-    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
++    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
+     env->priv_ver = PRIV_VERSION_1_11_0;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
+@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     RISCVCPU *cpu = RISCV_CPU(obj);
+-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
++    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
+     env->priv_ver = PRIV_VERSION_1_10_0;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
+     const RISCVCPUMultiExtConfig *prop;
+     /* Enable RVG, RVJ and RVV that are disabled by default */
+-    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
++    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+         isa_ext_update_enabled(cpu, prop->offset, true);
+--
+.41.0

-New patch
+[PULL 37/54] target/riscv/tcg: introduce tcg_cpu_instance_init()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
+accelerator. It'll be called from within riscv_cpu_post_init(), via
+accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
+preserve behavior, the implementation will be similar to what
+riscv_cpu_post_init() already does.
+In this patch we'll move riscv_cpu_add_user_properties() and
+riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
+All multi-extension properties code was moved. The 'multi_ext_user_opts'
+hash table was also moved to tcg-cpu.c since it's a TCG only structure,
+meaning that we won't have to worry about initializing a TCG hash table
+when running a KVM CPU anymore.
+riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
+much code it requires to be moved at the same time. We'll do that in the
+next patch.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230925175709.35696-16-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h         |   1 -
+ target/riscv/cpu.c         | 150 -------------------------------------
+ target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++
+files changed, 149 insertions(+), 151 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
+ /* used by tcg/tcg-cpu.c*/
+ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
+-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
+ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
+ int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+ void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+ };
+-/* Hash that stores user set extensions */
+-static GHashTable *multi_ext_user_opts;
+-
+ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
+ {
+     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
+@@ -XXX,XX +XXX,XX @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+     g_assert_not_reached();
+ }
+-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+-{
+-    return g_hash_table_contains(multi_ext_user_opts,
+-                                 GUINT_TO_POINTER(ext_offset));
+-}
+-
+ const char * const riscv_int_regnames[] = {
+     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
+     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
+@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
+     "reserved"
+ };
+-static void riscv_cpu_add_user_properties(Object *obj);
+-static void riscv_init_max_cpu_extensions(Object *obj);
+-
+ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+ {
+     if (async) {
+@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
+     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+ }
+-static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+-{
+-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+-}
+-
+-static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+-{
+-    if (kvm_enabled() &&
+-        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
+-        return true;
+-    }
+-
+-    return riscv_cpu_is_dynamic(cpu_obj);
+-}
+-
+ static void riscv_cpu_post_init(Object *obj)
+ {
+     accel_cpu_instance_init(CPU(obj));
+-
+-    if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
+-        riscv_cpu_add_user_properties(obj);
+-    }
+-
+-    if (riscv_cpu_has_max_extensions(obj)) {
+-        riscv_init_max_cpu_extensions(obj);
+-    }
+ }
+ static void riscv_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
+     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
+                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
+ #endif /* CONFIG_USER_ONLY */
+-
+-    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+ }
+ typedef struct RISCVCPUMisaExtConfig {
+@@ -XXX,XX +XXX,XX @@ Property riscv_cpu_options[] = {
+     DEFINE_PROP_END_OF_LIST(),
+ };
+-static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+-                                  void *opaque, Error **errp)
+-{
+-    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+-    bool value;
+-
+-    if (!visit_type_bool(v, name, &value, errp)) {
+-        return;
+-    }
+-
+-    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
+-
+-    g_hash_table_insert(multi_ext_user_opts,
+-                        GUINT_TO_POINTER(multi_ext_cfg->offset),
+-                        (gpointer)value);
+-}
+-
+-static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+-                                  void *opaque, Error **errp)
+-{
+-    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+-    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
+-
+-    visit_type_bool(v, name, &value, errp);
+-}
+-
+-static void cpu_add_multi_ext_prop(Object *cpu_obj,
+-                                   const RISCVCPUMultiExtConfig *multi_cfg)
+-{
+-    object_property_add(cpu_obj, multi_cfg->name, "bool",
+-                        cpu_get_multi_ext_cfg,
+-                        cpu_set_multi_ext_cfg,
+-                        NULL, (void *)multi_cfg);
+-
+-    /*
+-     * Set def val directly instead of using
+-     * object_property_set_bool() to save the set()
+-     * callback hash for user inputs.
+-     */
+-    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
+-                           multi_cfg->enabled);
+-}
+-
+-static void riscv_cpu_add_multiext_prop_array(Object *obj,
+-                                        const RISCVCPUMultiExtConfig *array)
+-{
+-    const RISCVCPUMultiExtConfig *prop;
+-
+-    g_assert(array);
+-
+-    for (prop = array; prop && prop->name; prop++) {
+-        cpu_add_multi_ext_prop(obj, prop);
+-    }
+-}
+-
+-/*
+- * Add CPU properties with user-facing flags.
+- *
+- * This will overwrite existing env->misa_ext values with the
+- * defaults set via riscv_cpu_add_misa_properties().
+- */
+-static void riscv_cpu_add_user_properties(Object *obj)
+-{
+-#ifndef CONFIG_USER_ONLY
+-    riscv_add_satp_mode_properties(obj);
+-#endif
+-
+-    riscv_cpu_add_misa_properties(obj);
+-
+-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
+-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
+-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
+-
+-    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+-        qdev_property_add_static(DEVICE(obj), prop);
+-    }
+-}
+-
+-/*
+- * The 'max' type CPU will have all possible ratified
+- * non-vendor extensions enabled.
+- */
+-static void riscv_init_max_cpu_extensions(Object *obj)
+-{
+-    RISCVCPU *cpu = RISCV_CPU(obj);
+-    CPURISCVState *env = &cpu->env;
+-    const RISCVCPUMultiExtConfig *prop;
+-
+-    /* Enable RVG, RVJ and RVV that are disabled by default */
+-    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+-
+-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+-        isa_ext_update_enabled(cpu, prop->offset, true);
+-    }
+-
+-    /* set vector version */
+-    env->vext_ver = VEXT_VERSION_1_00_0;
+-
+-    /* Zfinx is not compatible with F. Disable it */
+-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
+-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
+-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
+-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
+-
+-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
+-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
+-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
+-
+-    if (env->misa_mxl != MXL_RV32) {
+-        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
+-    }
+-}
+-
+ static Property riscv_cpu_properties[] = {
+     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@
+ #include "pmu.h"
+ #include "time_helper.h"
+ #include "qapi/error.h"
++#include "qapi/visitor.h"
+ #include "qemu/accel.h"
+ #include "qemu/error-report.h"
+ #include "qemu/log.h"
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/core/tcg-cpu-ops.h"
+ #include "tcg/tcg.h"
++/* Hash that stores user set extensions */
++static GHashTable *multi_ext_user_opts;
++
++static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
++{
++    return g_hash_table_contains(multi_ext_user_opts,
++                                 GUINT_TO_POINTER(ext_offset));
++}
++
+ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+                                           const TranslationBlock *tb)
+ {
+@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
+     return true;
+ }
++static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
++                                  void *opaque, Error **errp)
++{
++    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
++    bool value;
++
++    if (!visit_type_bool(v, name, &value, errp)) {
++        return;
++    }
++
++    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
++
++    g_hash_table_insert(multi_ext_user_opts,
++                        GUINT_TO_POINTER(multi_ext_cfg->offset),
++                        (gpointer)value);
++}
++
++static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
++                                  void *opaque, Error **errp)
++{
++    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
++    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
++
++    visit_type_bool(v, name, &value, errp);
++}
++
++static void cpu_add_multi_ext_prop(Object *cpu_obj,
++                                   const RISCVCPUMultiExtConfig *multi_cfg)
++{
++    object_property_add(cpu_obj, multi_cfg->name, "bool",
++                        cpu_get_multi_ext_cfg,
++                        cpu_set_multi_ext_cfg,
++                        NULL, (void *)multi_cfg);
++
++    /*
++     * Set def val directly instead of using
++     * object_property_set_bool() to save the set()
++     * callback hash for user inputs.
++     */
++    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
++                           multi_cfg->enabled);
++}
++
++static void riscv_cpu_add_multiext_prop_array(Object *obj,
++                                        const RISCVCPUMultiExtConfig *array)
++{
++    const RISCVCPUMultiExtConfig *prop;
++
++    g_assert(array);
++
++    for (prop = array; prop && prop->name; prop++) {
++        cpu_add_multi_ext_prop(obj, prop);
++    }
++}
++
++/*
++ * Add CPU properties with user-facing flags.
++ *
++ * This will overwrite existing env->misa_ext values with the
++ * defaults set via riscv_cpu_add_misa_properties().
++ */
++static void riscv_cpu_add_user_properties(Object *obj)
++{
++#ifndef CONFIG_USER_ONLY
++    riscv_add_satp_mode_properties(obj);
++#endif
++
++    riscv_cpu_add_misa_properties(obj);
++
++    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
++    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
++    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
++
++    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
++        qdev_property_add_static(DEVICE(obj), prop);
++    }
++}
++
++/*
++ * The 'max' type CPU will have all possible ratified
++ * non-vendor extensions enabled.
++ */
++static void riscv_init_max_cpu_extensions(Object *obj)
++{
++    RISCVCPU *cpu = RISCV_CPU(obj);
++    CPURISCVState *env = &cpu->env;
++    const RISCVCPUMultiExtConfig *prop;
++
++    /* Enable RVG, RVJ and RVV that are disabled by default */
++    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
++
++    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
++        isa_ext_update_enabled(cpu, prop->offset, true);
++    }
++
++    /* set vector version */
++    env->vext_ver = VEXT_VERSION_1_00_0;
++
++    /* Zfinx is not compatible with F. Disable it */
++    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
++    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
++    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
++    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
++
++    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
++    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
++    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
++
++    if (env->misa_mxl != MXL_RV32) {
++        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
++    }
++}
++
++static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
++{
++    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
++}
++
++static bool riscv_cpu_has_user_properties(Object *cpu_obj)
++{
++    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
++}
++
++static void tcg_cpu_instance_init(CPUState *cs)
++{
++    RISCVCPU *cpu = RISCV_CPU(cs);
++    Object *obj = OBJECT(cpu);
++
++    if (riscv_cpu_has_user_properties(obj)) {
++        multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
++        riscv_cpu_add_user_properties(obj);
++    }
++
++    if (riscv_cpu_has_max_extensions(obj)) {
++        riscv_init_max_cpu_extensions(obj);
++    }
++}
++
+ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
+ {
+     /*
+@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+     acc->cpu_class_init = tcg_cpu_class_init;
++    acc->cpu_instance_init = tcg_cpu_instance_init;
+     acc->cpu_target_realize = tcg_cpu_realize;
+ }
+--
+.41.0

-[PULL 06/25] target/riscv: rvk: add support for zbkc extension
+[PULL 38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - reuse partial instructions of zbc extension, update extension check for them
+The array isn't marked as 'const' because we're initializing their
 elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
 fields.
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+In a closer look we can see that we're not using these 2 fields after
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+creating the MISA properties. And we can create the properties by using
 riscv_get_misa_ext_name() and riscv_get_misa_ext_description()
 directly.
 Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig
 and make misa_ext_cfgs[] a const array.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20230925175709.35696-17-dbarboza@ventanamicro.com>
 Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              | 3 ++-
+ target/riscv/cpu.c | 21 ++++++++-------------
- target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
+file changed, 8 insertions(+), 13 deletions(-)
 files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ clzw       0110000 00000 ..... 001 ..... 0011011 @r2
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
  ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
  cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 -# *** RV32 Zbc Standard Extension ***
 +# *** RV32 Zbc/Zbkc Standard Extension ***
  clmul      0000101 .......... 001 ..... 0110011 @r
  clmulh     0000101 .......... 011 ..... 0110011 @r
 +# *** RV32 extra Zbc Standard Extension ***
  clmulr     0000101 .......... 010 ..... 0110011 @r
  # *** RV32 Zbs Standard Extension ***
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
  static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
  {
 -    REQUIRE_ZBC(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
      return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
  }
-@@ -XXX,XX +XXX,XX @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
+ typedef struct RISCVCPUMisaExtConfig {
+-    const char *name;
- static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
+-    const char *description;
- {
+     target_ulong misa_bit;
--    REQUIRE_ZBC(ctx);
+     bool enabled;
-+    REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
+ } RISCVCPUMisaExtConfig;
-     return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
+@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
  #define MISA_CFG(_bit, _enabled) \
      {.misa_bit = _bit, .enabled = _enabled}
 -static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
 +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
      MISA_CFG(RVA, true),
      MISA_CFG(RVC, true),
      MISA_CFG(RVD, true),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_add_misa_properties(Object *cpu_obj)
      int i;
      for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
 -        RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
 +        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
          int bit = misa_cfg->misa_bit;
 -
 -        misa_cfg->name = riscv_get_misa_ext_name(bit);
 -        misa_cfg->description = riscv_get_misa_ext_description(bit);
 +        const char *name = riscv_get_misa_ext_name(bit);
 +        const char *desc = riscv_get_misa_ext_description(bit);
          /* Check if KVM already created the property */
 -        if (object_property_find(cpu_obj, misa_cfg->name)) {
 +        if (object_property_find(cpu_obj, name)) {
              continue;
          }
 -        object_property_add(cpu_obj, misa_cfg->name, "bool",
 +        object_property_add(cpu_obj, name, "bool",
                              cpu_get_misa_ext_cfg,
                              cpu_set_misa_ext_cfg,
                              NULL, (void *)misa_cfg);
 -        object_property_set_description(cpu_obj, misa_cfg->name,
 -                                        misa_cfg->description);
 -        object_property_set_bool(cpu_obj, misa_cfg->name,
 -                                 misa_cfg->enabled, NULL);
 +        object_property_set_description(cpu_obj, name, desc);
 +        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
      }
  }
 --
-.35.1
+.41.0

-[PULL 13/25] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
+[PULL 39/54] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
- - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
+All code related to MISA TCG properties is also moved.
-Co-authored-by: Zewen Ye <lustrew@foxmail.com>
+At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+properties handling is done in kvm-cpu.c.
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn>
+Message-ID: <20230925175709.35696-18-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              |  5 +++
+ target/riscv/cpu.h         |  1 -
- target/riscv/insn_trans/trans_rvk.c.inc | 53 +++++++++++++++++++++++++
+ target/riscv/cpu.c         | 90 --------------------------------------
-files changed, 58 insertions(+)
+ target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++
+files changed, 90 insertions(+), 91 deletions(-)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu.h
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
+@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
- sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
+ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
- sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
+ extern Property riscv_cpu_options[];
- sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
-+# *** RV64 Zknh Standard Extension ***
+-void riscv_cpu_add_misa_properties(Object *cpu_obj);
-+sha512sig0  00 01000 00110 ..... 001 ..... 0010011 @r2
+ void riscv_add_satp_mode_properties(Object *obj);
-+sha512sig1  00 01000 00111 ..... 001 ..... 0010011 @r2
-+sha512sum0  00 01000 00100 ..... 001 ..... 0010011 @r2
+ /* CSR function table */
-+sha512sum1  00 01000 00101 ..... 001 ..... 0010011 @r2
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvk.c.inc
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/insn_trans/trans_rvk.c.inc
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
-     REQUIRE_ZKNH(ctx);
+ #endif /* CONFIG_USER_ONLY */
      return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19);
  }
-+
-+static bool gen_sha512_rv64(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+-typedef struct RISCVCPUMisaExtConfig {
-+                            void (*func)(TCGv_i64, TCGv_i64, int64_t),
+-    target_ulong misa_bit;
-+                            int64_t num1, int64_t num2, int64_t num3)
+-    bool enabled;
 -} RISCVCPUMisaExtConfig;
 -
 -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 -                                 void *opaque, Error **errp)
 -{
 -    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
 -    target_ulong misa_bit = misa_ext_cfg->misa_bit;
 -    RISCVCPU *cpu = RISCV_CPU(obj);
 -    CPURISCVState *env = &cpu->env;
 -    bool value;
 -
 -    if (!visit_type_bool(v, name, &value, errp)) {
 -        return;
 -    }
 -
 -    if (value) {
 -        env->misa_ext |= misa_bit;
 -        env->misa_ext_mask |= misa_bit;
 -    } else {
 -        env->misa_ext &= ~misa_bit;
 -        env->misa_ext_mask &= ~misa_bit;
 -    }
 -}
 -
 -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 -                                 void *opaque, Error **errp)
 -{
 -    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
 -    target_ulong misa_bit = misa_ext_cfg->misa_bit;
 -    RISCVCPU *cpu = RISCV_CPU(obj);
 -    CPURISCVState *env = &cpu->env;
 -    bool value;
 -
 -    value = env->misa_ext & misa_bit;
 -
 -    visit_type_bool(v, name, &value, errp);
 -}
 -
  typedef struct misa_ext_info {
      const char *name;
      const char *description;
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
      return val;
  }
 -#define MISA_CFG(_bit, _enabled) \
 -    {.misa_bit = _bit, .enabled = _enabled}
 -
 -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
 -    MISA_CFG(RVA, true),
 -    MISA_CFG(RVC, true),
 -    MISA_CFG(RVD, true),
 -    MISA_CFG(RVF, true),
 -    MISA_CFG(RVI, true),
 -    MISA_CFG(RVE, false),
 -    MISA_CFG(RVM, true),
 -    MISA_CFG(RVS, true),
 -    MISA_CFG(RVU, true),
 -    MISA_CFG(RVH, true),
 -    MISA_CFG(RVJ, false),
 -    MISA_CFG(RVV, false),
 -    MISA_CFG(RVG, false),
 -};
 -
 -/*
 - * We do not support user choice tracking for MISA
 - * extensions yet because, so far, we do not silently
 - * change MISA bits during realize() (RVG enables MISA
 - * bits but the user is warned about it).
 - */
 -void riscv_cpu_add_misa_properties(Object *cpu_obj)
 -{
 -    int i;
 -
 -    for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
 -        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
 -        int bit = misa_cfg->misa_bit;
 -        const char *name = riscv_get_misa_ext_name(bit);
 -        const char *desc = riscv_get_misa_ext_description(bit);
 -
 -        /* Check if KVM already created the property */
 -        if (object_property_find(cpu_obj, name)) {
 -            continue;
 -        }
 -
 -        object_property_add(cpu_obj, name, "bool",
 -                            cpu_get_misa_ext_cfg,
 -                            cpu_set_misa_ext_cfg,
 -                            NULL, (void *)misa_cfg);
 -        object_property_set_description(cpu_obj, name, desc);
 -        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
 -    }
 -}
 -
  #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
      {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
       .enabled = _defval}
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
      return true;
  }
 +typedef struct RISCVCPUMisaExtConfig {
 +    target_ulong misa_bit;
 +    bool enabled;
 +} RISCVCPUMisaExtConfig;
 +
 +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 +                                 void *opaque, Error **errp)
 +{
-+    TCGv dest = dest_gpr(ctx, a->rd);
++    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
-+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
++    target_ulong misa_bit = misa_ext_cfg->misa_bit;
-+    TCGv_i64 t0 = tcg_temp_new_i64();
++    RISCVCPU *cpu = RISCV_CPU(obj);
-+    TCGv_i64 t1 = tcg_temp_new_i64();
++    CPURISCVState *env = &cpu->env;
-+    TCGv_i64 t2 = tcg_temp_new_i64();
++    bool value;
 +
-+    tcg_gen_extu_tl_i64(t0, src1);
++    if (!visit_type_bool(v, name, &value, errp)) {
-+    tcg_gen_rotri_i64(t1, t0, num1);
++        return;
-+    tcg_gen_rotri_i64(t2, t0, num2);
++    }
-+    tcg_gen_xor_i64(t1, t1, t2);
++
-+    func(t2, t0, num3);
++    if (value) {
-+    tcg_gen_xor_i64(t1, t1, t2);
++        env->misa_ext |= misa_bit;
-+    tcg_gen_trunc_i64_tl(dest, t1);
++        env->misa_ext_mask |= misa_bit;
-+
++    } else {
-+    gen_set_gpr(ctx, a->rd, dest);
++        env->misa_ext &= ~misa_bit;
-+    tcg_temp_free_i64(t0);
++        env->misa_ext_mask &= ~misa_bit;
-+    tcg_temp_free_i64(t1);
++    }
 +    tcg_temp_free_i64(t2);
 +    return true;
 +}
 +
-+static bool trans_sha512sig0(DisasContext *ctx, arg_sha512sig0 *a)
++static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 +                                 void *opaque, Error **errp)
 +{
-+    REQUIRE_64BIT(ctx);
++    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
-+    REQUIRE_ZKNH(ctx);
++    target_ulong misa_bit = misa_ext_cfg->misa_bit;
-+    return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 1, 8, 7);
++    RISCVCPU *cpu = RISCV_CPU(obj);
 +    CPURISCVState *env = &cpu->env;
 +    bool value;
 +
 +    value = env->misa_ext & misa_bit;
 +
 +    visit_type_bool(v, name, &value, errp);
 +}
 +
-+static bool trans_sha512sig1(DisasContext *ctx, arg_sha512sig1 *a)
++#define MISA_CFG(_bit, _enabled) \
 +    {.misa_bit = _bit, .enabled = _enabled}
 +
 +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
 +    MISA_CFG(RVA, true),
 +    MISA_CFG(RVC, true),
 +    MISA_CFG(RVD, true),
 +    MISA_CFG(RVF, true),
 +    MISA_CFG(RVI, true),
 +    MISA_CFG(RVE, false),
 +    MISA_CFG(RVM, true),
 +    MISA_CFG(RVS, true),
 +    MISA_CFG(RVU, true),
 +    MISA_CFG(RVH, true),
 +    MISA_CFG(RVJ, false),
 +    MISA_CFG(RVV, false),
 +    MISA_CFG(RVG, false),
 +};
 +
 +/*
 + * We do not support user choice tracking for MISA
 + * extensions yet because, so far, we do not silently
 + * change MISA bits during realize() (RVG enables MISA
 + * bits but the user is warned about it).
 + */
 +static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 +{
-+    REQUIRE_64BIT(ctx);
++    int i;
-+    REQUIRE_ZKNH(ctx);
++
-+    return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 19, 61, 6);
++    for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
 +        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
 +        int bit = misa_cfg->misa_bit;
 +        const char *name = riscv_get_misa_ext_name(bit);
 +        const char *desc = riscv_get_misa_ext_description(bit);
 +
 +        /* Check if KVM already created the property */
 +        if (object_property_find(cpu_obj, name)) {
 +            continue;
 +        }
 +
 +        object_property_add(cpu_obj, name, "bool",
 +                            cpu_get_misa_ext_cfg,
 +                            cpu_set_misa_ext_cfg,
 +                            NULL, (void *)misa_cfg);
 +        object_property_set_description(cpu_obj, name, desc);
 +        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
 +    }
 +}
 +
-+static bool trans_sha512sum0(DisasContext *ctx, arg_sha512sum0 *a)
+ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
-+{
+                                   void *opaque, Error **errp)
-+    REQUIRE_64BIT(ctx);
+ {
 +    REQUIRE_ZKNH(ctx);
 +    return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 28, 34, 39);
 +}
 +
 +static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a)
 +{
 +    REQUIRE_64BIT(ctx);
 +    REQUIRE_ZKNH(ctx);
 +    return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41);
 +}
 --
-.35.1
+.41.0

-[PULL 04/25] target/riscv: rvk: add cfg properties for zbk* and zk*
+[PULL 40/54] target/riscv/cpu.c: export isa_edata_arr[]
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+This array will be read by the TCG accel class, allowing it to handle
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+priv spec verifications on its own. The array will remain here in cpu.c
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+because it's also used by the riscv,isa string function.
-Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn>
 To export it we'll finish it with an empty element since ARRAY_SIZE()
 won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to
 alleviate the changes for the next patch.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20230925175709.35696-19-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h | 13 +++++++++++++
+ target/riscv/cpu.h |  7 +++++++
- target/riscv/cpu.c | 23 +++++++++++++++++++++++
+ target/riscv/cpu.c | 47 +++++++++++++++++++++-------------------------
-files changed, 36 insertions(+)
+files changed, 28 insertions(+), 26 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
-     bool ext_zba;
+ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
-     bool ext_zbb;
+ extern Property riscv_cpu_options[];
-     bool ext_zbc;
-+    bool ext_zbkb;
++typedef struct isa_ext_data {
-+    bool ext_zbkc;
++    const char *name;
-+    bool ext_zbkx;
++    int min_version;
-     bool ext_zbs;
++    int ext_enable_offset;
-+    bool ext_zk;
++} RISCVIsaExtData;
-+    bool ext_zkn;
++extern const RISCVIsaExtData isa_edata_arr[];
-+    bool ext_zknd;
++
-+    bool ext_zkne;
+ void riscv_add_satp_mode_properties(Object *obj);
-+    bool ext_zknh;
-+    bool ext_zkr;
+ /* CSR function table */
 +    bool ext_zks;
 +    bool ext_zksed;
 +    bool ext_zksh;
 +    bool ext_zkt;
      bool ext_counters;
      bool ext_ifencei;
      bool ext_icsr;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
-             cpu->cfg.ext_zfinx = true;
+ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
                                RVC, RVS, RVU, RVH, RVJ, RVG, 0};
 -struct isa_ext_data {
 -    const char *name;
 -    int min_version;
 -    int ext_enable_offset;
 -};
 -
 -#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
 -    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
 -
  /*
   * From vector_helper.c
   * Note that vector data is stored in host-endian 64-bit chunks,
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
  #define BYTE(x)   (x)
  #endif
 +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
 +    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
 +
  /*
   * Here are the ordering rules of extension naming defined by RISC-V
   * specification :
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
   * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
   * instead.
   */
 -static const struct isa_ext_data isa_edata_arr[] = {
 +const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
      ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
      ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
      ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
      ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
 +
 +    DEFINE_PROP_END_OF_LIST(),
  };
  bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
  int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
  {
 -    int i;
 +    const RISCVIsaExtData *edata;
 -    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
 -        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
 +    for (edata = isa_edata_arr; edata && edata->name; edata++) {
 +        if (edata->ext_enable_offset != ext_offset) {
              continue;
          }
-+        if (cpu->cfg.ext_zk) {
+-        return isa_edata_arr[i].min_version;
-+            cpu->cfg.ext_zkn = true;
++        return edata->min_version;
-+            cpu->cfg.ext_zkr = true;
+     }
-+            cpu->cfg.ext_zkt = true;
-+        }
+     g_assert_not_reached();
-+
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
-+        if (cpu->cfg.ext_zkn) {
+ void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
-+            cpu->cfg.ext_zbkb = true;
+ {
-+            cpu->cfg.ext_zbkc = true;
+     CPURISCVState *env = &cpu->env;
-+            cpu->cfg.ext_zbkx = true;
+-    int i;
-+            cpu->cfg.ext_zkne = true;
++    const RISCVIsaExtData *edata;
-+            cpu->cfg.ext_zknd = true;
-+            cpu->cfg.ext_zknh = true;
+     /* Force disable extensions if priv spec version does not match */
-+        }
+-    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-+
+-        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
-+        if (cpu->cfg.ext_zks) {
+-            (env->priv_ver < isa_edata_arr[i].min_version)) {
-+            cpu->cfg.ext_zbkb = true;
+-            isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
-+            cpu->cfg.ext_zbkc = true;
+-                                   false);
-+            cpu->cfg.ext_zbkx = true;
++    for (edata = isa_edata_arr; edata && edata->name; edata++) {
-+            cpu->cfg.ext_zksed = true;
++        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
-+            cpu->cfg.ext_zksh = true;
++            (env->priv_ver < edata->min_version)) {
-+        }
++            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
-+
+ #ifndef CONFIG_USER_ONLY
-         /* Set the ISA extensions, checks should have happened above */
+             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
-         if (cpu->cfg.ext_i) {
+                         " because privilege spec version does not match",
-             ext |= RVI;
+-                        isa_edata_arr[i].name, env->mhartid);
 +                        edata->name, env->mhartid);
  #else
              warn_report("disabling %s extension because "
                          "privilege spec version does not match",
 -                        isa_edata_arr[i].name);
 +                        edata->name);
  #endif
          }
      }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
  static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
                                   int max_str_len)
  {
 +    const RISCVIsaExtData *edata;
      char *old = *isa_str;
      char *new = *isa_str;
 -    int i;
 -    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
 -        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
 -            new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
 +    for (edata = isa_edata_arr; edata && edata->name; edata++) {
 +        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
 +            new = g_strconcat(old, "_", edata->name, NULL);
              g_free(old);
              old = new;
          }
 --
-.35.1
+.41.0

-[PULL 24/25] hw/riscv: virt: Add device plug support
+[PULL 41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Add support for plugging in devices, this was tested with the TPM
+Priv spec validation is TCG specific. Move it to the TCG accel class.
 device.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220427234146.1130752-6-alistair.francis@opensource.wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-ID: <20230925175709.35696-20-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 35 +++++++++++++++++++++++++++++++++++
+ target/riscv/cpu.h         |  2 --
-file changed, 35 insertions(+)
+ target/riscv/cpu.c         | 38 --------------------------------------
  target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
 files changed, 38 insertions(+), 40 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/cpu.h
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void virt_set_aclint(Object *obj, bool value, Error **errp)
+@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
-     s->have_aclint = value;
+ /* used by tcg/tcg-cpu.c*/
  void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
  bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 -int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
  void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
 -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
  typedef struct RISCVCPUMultiExtConfig {
      const char *name;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
      *ext_enabled = en;
  }
-+static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
+-int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
-+                                                        DeviceState *dev)
+-{
 -    const RISCVIsaExtData *edata;
 -
 -    for (edata = isa_edata_arr; edata && edata->name; edata++) {
 -        if (edata->ext_enable_offset != ext_offset) {
 -            continue;
 -        }
 -
 -        return edata->min_version;
 -    }
 -
 -    g_assert_not_reached();
 -}
 -
  const char * const riscv_int_regnames[] = {
      "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
      "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
      }
  }
 -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 -{
 -    CPURISCVState *env = &cpu->env;
 -    const RISCVIsaExtData *edata;
 -
 -    /* Force disable extensions if priv spec version does not match */
 -    for (edata = isa_edata_arr; edata && edata->name; edata++) {
 -        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
 -            (env->priv_ver < edata->min_version)) {
 -            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
 -#ifndef CONFIG_USER_ONLY
 -            warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
 -                        " because privilege spec version does not match",
 -                        edata->name, env->mhartid);
 -#else
 -            warn_report("disabling %s extension because "
 -                        "privilege spec version does not match",
 -                        edata->name);
 -#endif
 -        }
 -    }
 -}
 -
  #ifndef CONFIG_USER_ONLY
  static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
  {
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps riscv_tcg_ops = {
  #endif /* !CONFIG_USER_ONLY */
  };
 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 +{
-+    MachineClass *mc = MACHINE_GET_CLASS(machine);
++    const RISCVIsaExtData *edata;
 +
-+    if (device_is_dynamic_sysbus(mc, dev)) {
++    for (edata = isa_edata_arr; edata && edata->name; edata++) {
-+        return HOTPLUG_HANDLER(machine);
++        if (edata->ext_enable_offset != ext_offset) {
 +            continue;
 +        }
 +
 +        return edata->min_version;
 +    }
-+    return NULL;
++
 +    g_assert_not_reached();
 +}
 +
-+static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
+ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
-+                                        DeviceState *dev, Error **errp)
+                                     bool value)
  {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
      }
  }
 +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 +{
-+    RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
++    CPURISCVState *env = &cpu->env;
 +    const RISCVIsaExtData *edata;
 +
-+    if (s->platform_bus_dev) {
++    /* Force disable extensions if priv spec version does not match */
-+        MachineClass *mc = MACHINE_GET_CLASS(s);
++    for (edata = isa_edata_arr; edata && edata->name; edata++) {
-+
++        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
-+        if (device_is_dynamic_sysbus(mc, dev)) {
++            (env->priv_ver < edata->min_version)) {
-+            platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
++            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
-+                                     SYS_BUS_DEVICE(dev));
++#ifndef CONFIG_USER_ONLY
 +            warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
 +                        " because privilege spec version does not match",
 +                        edata->name, env->mhartid);
 +#else
 +            warn_report("disabling %s extension because "
 +                        "privilege spec version does not match",
 +                        edata->name);
 +#endif
 +        }
 +    }
 +}
 +
- static void virt_machine_class_init(ObjectClass *oc, void *data)
+ /*
- {
+  * Check consistency between chosen extensions while setting
-     char str[128];
+  * cpu->cfg accordingly.
      MachineClass *mc = MACHINE_CLASS(oc);
 +    HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
      mc->desc = "RISC-V VirtIO board";
      mc->init = virt_machine_init;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
      mc->numa_mem_supported = true;
      mc->default_ram_id = "riscv_virt_board.ram";
 +    assert(!mc->get_hotplug_handler);
 +    mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
 +
 +    hc->plug = virt_machine_device_plug_cb;
      machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo virt_machine_typeinfo = {
      .class_init = virt_machine_class_init,
      .instance_init = virt_machine_instance_init,
      .instance_size = sizeof(RISCVVirtState),
 +    .interfaces = (InterfaceInfo[]) {
 +         { TYPE_HOTPLUG_HANDLER },
 +         { }
 +    },
  };
  static void virt_machine_init_register_types(void)
 --
-.35.1
+.41.0

-New patch
+[PULL 42/54] target/riscv: add riscv_cpu_get_name()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+We'll introduce generic errors that will output a CPU type name via its
+RISCVCPU pointer. Create a helper for that.
+Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host'
+CPU name.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230926183109.165878-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h         |  1 +
+ target/riscv/cpu.c         | 11 +++++++++++
+ target/riscv/tcg/tcg-cpu.c |  4 +++-
+files changed, 15 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct isa_ext_data {
+     int ext_enable_offset;
+ } RISCVIsaExtData;
+ extern const RISCVIsaExtData isa_edata_arr[];
++char *riscv_cpu_get_name(RISCVCPU *cpu);
+ void riscv_add_satp_mode_properties(Object *obj);
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
+     return oc;
+ }
++char *riscv_cpu_get_name(RISCVCPU *cpu)
++{
++    RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu);
++    const char *typename = object_class_get_name(OBJECT_CLASS(rcc));
++
++    g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX));
++
++    return g_strndup(typename,
++                     strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX));
++}
++
+ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+ {
+     RISCVCPU *cpu = RISCV_CPU(cs);
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
+     Error *local_err = NULL;
+     if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
+-        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
++        g_autofree char *name = riscv_cpu_get_name(cpu);
++        error_setg(errp, "'%s' CPU is not compatible with TCG acceleration",
++                   name);
+         return false;
+     }
+--
+.41.0

-New patch
+[PULL 43/54] target/riscv/tcg-cpu.c: add extension properties for all cpus
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+At this moment we do not expose extension properties for vendor CPUs
+because that would allow users to change them via command line. The
+drawback is that if we were to add an API that shows all CPU properties,
+e.g. qmp-query-cpu-model-expansion, we won't be able to show extensions
+state of vendor CPUs.
+We have the required machinery to create extension properties for vendor
+CPUs while not allowing users to enable extensions. Disabling existing
+extensions is allowed since it can be useful for debugging.
+Change the set() callback cpu_set_multi_ext_cfg() to allow enabling
+extensions only for generic CPUs. In cpu_add_multi_ext_prop() let's not
+set the default values for the properties if we're not dealing with
+generic CPUs, otherwise the values set in cpu_init() of vendor CPUs will
+be overwritten. And finally, in tcg_cpu_instance_init(), add cpu user
+properties for all CPUs.
+For the veyron-v1 CPU, we're now able to disable existing extensions
+like smstateen:
+$ ./build/qemu-system-riscv64 --nographic -M virt \
+    -cpu veyron-v1,smstateen=false
+But setting extensions that the CPU didn't set during cpu_init(), like
+V, is not allowed:
+$ ./build/qemu-system-riscv64 --nographic -M virt \
+    -cpu veyron-v1,v=true
+qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.v=true:
+  'veyron-v1' CPU does not allow enabling extensions
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20230926183109.165878-3-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/tcg/tcg-cpu.c | 64 +++++++++++++++++++++++++++++---------
+file changed, 50 insertions(+), 14 deletions(-)
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+     riscv_cpu_disable_priv_spec_isa_exts(cpu);
+ }
++static bool riscv_cpu_is_generic(Object *cpu_obj)
++{
++    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
++}
++
+ /*
+  * We'll get here via the following path:
+  *
+@@ -XXX,XX +XXX,XX @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+     target_ulong misa_bit = misa_ext_cfg->misa_bit;
+     RISCVCPU *cpu = RISCV_CPU(obj);
+     CPURISCVState *env = &cpu->env;
+-    bool value;
++    bool generic_cpu = riscv_cpu_is_generic(obj);
++    bool prev_val, value;
+     if (!visit_type_bool(v, name, &value, errp)) {
+         return;
+     }
++    prev_val = env->misa_ext & misa_bit;
++
++    if (value == prev_val) {
++        return;
++    }
++
+     if (value) {
++        if (!generic_cpu) {
++            g_autofree char *cpuname = riscv_cpu_get_name(cpu);
++            error_setg(errp, "'%s' CPU does not allow enabling extensions",
++                       cpuname);
++            return;
++        }
++
+         env->misa_ext |= misa_bit;
+         env->misa_ext_mask |= misa_bit;
+     } else {
+@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+  */
+ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+ {
++    bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
+     int i;
+     for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+                             cpu_set_misa_ext_cfg,
+                             NULL, (void *)misa_cfg);
+         object_property_set_description(cpu_obj, name, desc);
+-        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
++        if (use_def_vals) {
++            object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
++        }
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
+ {
+     const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+-    bool value;
++    RISCVCPU *cpu = RISCV_CPU(obj);
++    bool generic_cpu = riscv_cpu_is_generic(obj);
++    bool prev_val, value;
+     if (!visit_type_bool(v, name, &value, errp)) {
+         return;
+     }
+-    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
+-
+     g_hash_table_insert(multi_ext_user_opts,
+                         GUINT_TO_POINTER(multi_ext_cfg->offset),
+                         (gpointer)value);
++
++    prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
++
++    if (value == prev_val) {
++        return;
++    }
++
++    if (value && !generic_cpu) {
++        g_autofree char *cpuname = riscv_cpu_get_name(cpu);
++        error_setg(errp, "'%s' CPU does not allow enabling extensions",
++                   cpuname);
++        return;
++    }
++
++    isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value);
+ }
+ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+@@ -XXX,XX +XXX,XX @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+ static void cpu_add_multi_ext_prop(Object *cpu_obj,
+                                    const RISCVCPUMultiExtConfig *multi_cfg)
+ {
++    bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
++
+     object_property_add(cpu_obj, multi_cfg->name, "bool",
+                         cpu_get_multi_ext_cfg,
+                         cpu_set_multi_ext_cfg,
+                         NULL, (void *)multi_cfg);
++    if (!generic_cpu) {
++        return;
++    }
++
+     /*
+      * Set def val directly instead of using
+      * object_property_set_bool() to save the set()
+@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+     return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+ }
+-static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+-{
+-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+-}
+-
+ static void tcg_cpu_instance_init(CPUState *cs)
+ {
+     RISCVCPU *cpu = RISCV_CPU(cs);
+     Object *obj = OBJECT(cpu);
+-    if (riscv_cpu_has_user_properties(obj)) {
+-        multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+-        riscv_cpu_add_user_properties(obj);
+-    }
++    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
++    riscv_cpu_add_user_properties(obj);
+     if (riscv_cpu_has_max_extensions(obj)) {
+         riscv_init_max_cpu_extensions(obj);
+--
+.41.0

-New patch
+[PULL 44/54] softmmu: add means to pass an exit code when requesting a shutdown
+From: Clément Chigot <chigot@adacore.com>
+As of now, the exit code was either EXIT_FAILURE when a panic shutdown
+was requested or EXIT_SUCCESS otherwise.
+However, some hardware could want to pass more complex exit codes. Thus,
+introduce a new shutdown request function allowing that.
+Signed-off-by: Clément Chigot <chigot@adacore.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20231003071427.188697-2-chigot@adacore.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/sysemu/runstate.h |  2 ++
+ system/runstate.c         | 12 +++++++++++-
+files changed, 13 insertions(+), 1 deletion(-)
+diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/sysemu/runstate.h
++++ b/include/sysemu/runstate.h
+@@ -XXX,XX +XXX,XX @@ void qemu_system_wakeup_request(WakeupReason reason, Error **errp);
+ void qemu_system_wakeup_enable(WakeupReason reason, bool enabled);
+ void qemu_register_wakeup_notifier(Notifier *notifier);
+ void qemu_register_wakeup_support(void);
++void qemu_system_shutdown_request_with_code(ShutdownCause reason,
++                                            int exit_code);
+ void qemu_system_shutdown_request(ShutdownCause reason);
+ void qemu_system_powerdown_request(void);
+ void qemu_register_powerdown_notifier(Notifier *notifier);
+diff --git a/system/runstate.c b/system/runstate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/system/runstate.c
++++ b/system/runstate.c
+@@ -XXX,XX +XXX,XX @@ void vm_state_notify(bool running, RunState state)
+ static ShutdownCause reset_requested;
+ static ShutdownCause shutdown_requested;
++static int shutdown_exit_code = EXIT_SUCCESS;
+ static int shutdown_signal;
+ static pid_t shutdown_pid;
+ static int powerdown_requested;
+@@ -XXX,XX +XXX,XX @@ void qemu_system_killed(int signal, pid_t pid)
+     qemu_notify_event();
+ }
++void qemu_system_shutdown_request_with_code(ShutdownCause reason,
++                                            int exit_code)
++{
++    shutdown_exit_code = exit_code;
++    qemu_system_shutdown_request(reason);
++}
++
+ void qemu_system_shutdown_request(ShutdownCause reason)
+ {
+     trace_qemu_system_shutdown_request(reason);
+@@ -XXX,XX +XXX,XX @@ static bool main_loop_should_exit(int *status)
+         if (shutdown_action == SHUTDOWN_ACTION_PAUSE) {
+             vm_stop(RUN_STATE_SHUTDOWN);
+         } else {
+-            if (request == SHUTDOWN_CAUSE_GUEST_PANIC &&
++            if (shutdown_exit_code != EXIT_SUCCESS) {
++                *status = shutdown_exit_code;
++            } else if (request == SHUTDOWN_CAUSE_GUEST_PANIC &&
+                 panic_action == PANIC_ACTION_EXIT_FAILURE) {
+                 *status = EXIT_FAILURE;
+             }
+--
+.41.0

-New patch
+[PULL 45/54] softmmu: pass the main loop status to gdb "Wxx" packet
+From: Clément Chigot <chigot@adacore.com>
+gdb_exit function aims to close gdb sessions and sends the exit code of
+the current execution. It's being called by qemu_cleanup once the main
+loop is over.
+Until now, the exit code sent was always 0. Now that hardware can
+shutdown this main loop with custom exit codes, these codes must be
+transfered to gdb as well.
+Signed-off-by: Clément Chigot <chigot@adacore.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20231003071427.188697-3-chigot@adacore.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/sysemu/sysemu.h | 2 +-
+ system/main.c           | 2 +-
+ system/runstate.c       | 4 ++--
+files changed, 4 insertions(+), 4 deletions(-)
+diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/sysemu/sysemu.h
++++ b/include/sysemu/sysemu.h
+@@ -XXX,XX +XXX,XX @@ bool defaults_enabled(void);
+ void qemu_init(int argc, char **argv);
+ int qemu_main_loop(void);
+-void qemu_cleanup(void);
++void qemu_cleanup(int);
+ extern QemuOptsList qemu_legacy_drive_opts;
+ extern QemuOptsList qemu_common_drive_opts;
+diff --git a/system/main.c b/system/main.c
+index XXXXXXX..XXXXXXX 100644
+--- a/system/main.c
++++ b/system/main.c
+@@ -XXX,XX +XXX,XX @@ int qemu_default_main(void)
+     int status;
+     status = qemu_main_loop();
+-    qemu_cleanup();
++    qemu_cleanup(status);
+     return status;
+ }
+diff --git a/system/runstate.c b/system/runstate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/system/runstate.c
++++ b/system/runstate.c
+@@ -XXX,XX +XXX,XX @@ void qemu_init_subsystems(void)
+ }
+-void qemu_cleanup(void)
++void qemu_cleanup(int status)
+ {
+-    gdb_exit(0);
++    gdb_exit(status);
+     /*
+      * cleaning up the migration object cancels any existing migration
+--
+.41.0

-[PULL 21/25] hw/core: Move the ARM sysbus-fdt to core
+[PULL 46/54] hw/misc/sifive_test.c: replace exit calls with proper shutdown
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Clément Chigot <chigot@adacore.com>
-The ARM virt machine currently uses sysbus-fdt to create device tree
+This replaces the exit calls by shutdown requests, ensuring a proper
-entries for dynamically created MMIO devices.
+cleanup of Qemu. Otherwise, some connections like gdb could be broken
 before its final packet ("Wxx") is being sent. This part, being done
 inside qemu_cleanup function, can be reached only when the main loop
 exits after a shutdown request.
-The RISC-V virt machine can also benefit from this, so move the code to
+Signed-off-by: Clément Chigot <chigot@adacore.com>
-the core directory.
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20231003071427.188697-4-chigot@adacore.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{arm => core}/sysbus-fdt.h | 0
+ hw/misc/sifive_test.c | 9 +++++++--
- hw/arm/virt.c                         | 2 +-
+file changed, 7 insertions(+), 2 deletions(-)
  hw/arm/xlnx-versal-virt.c             | 1 -
  hw/{arm => core}/sysbus-fdt.c         | 2 +-
  hw/arm/meson.build                    | 1 -
  hw/core/meson.build                   | 1 +
 files changed, 3 insertions(+), 4 deletions(-)
  rename include/hw/{arm => core}/sysbus-fdt.h (100%)
  rename hw/{arm => core}/sysbus-fdt.c (99%)
-diff --git a/include/hw/arm/sysbus-fdt.h b/include/hw/core/sysbus-fdt.h
+diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c
 similarity index 100%
 rename from include/hw/arm/sysbus-fdt.h
 rename to include/hw/core/sysbus-fdt.h
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/hw/misc/sifive_test.c
-+++ b/hw/arm/virt.c
++++ b/hw/misc/sifive_test.c
 @@ -XXX,XX +XXX,XX @@
  #include "qemu/module.h"
- #include "hw/pci-host/gpex.h"
+ #include "sysemu/runstate.h"
- #include "hw/virtio/virtio-pci.h"
+ #include "hw/misc/sifive_test.h"
--#include "hw/arm/sysbus-fdt.h"
++#include "sysemu/sysemu.h"
-+#include "hw/core/sysbus-fdt.h"
- #include "hw/platform-bus.h"
+ static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
- #include "hw/qdev-properties.h"
+ {
- #include "hw/arm/fdt.h"
+@@ -XXX,XX +XXX,XX @@ static void sifive_test_write(void *opaque, hwaddr addr,
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
+         int code = (val64 >> 16) & 0xffff;
-index XXXXXXX..XXXXXXX 100644
+         switch (status) {
---- a/hw/arm/xlnx-versal-virt.c
+         case FINISHER_FAIL:
-+++ b/hw/arm/xlnx-versal-virt.c
+-            exit(code);
-@@ -XXX,XX +XXX,XX @@
++            qemu_system_shutdown_request_with_code(
- #include "sysemu/device_tree.h"
++                SHUTDOWN_CAUSE_GUEST_PANIC, code);
- #include "hw/boards.h"
++            return;
- #include "hw/sysbus.h"
+         case FINISHER_PASS:
--#include "hw/arm/sysbus-fdt.h"
+-            exit(0);
- #include "hw/arm/fdt.h"
++            qemu_system_shutdown_request_with_code(
- #include "cpu.h"
++                SHUTDOWN_CAUSE_GUEST_SHUTDOWN, code);
- #include "hw/qdev-properties.h"
++            return;
-diff --git a/hw/arm/sysbus-fdt.c b/hw/core/sysbus-fdt.c
+         case FINISHER_RESET:
-similarity index 99%
+             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-rename from hw/arm/sysbus-fdt.c
+             return;
 rename to hw/core/sysbus-fdt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/sysbus-fdt.c
 +++ b/hw/core/sysbus-fdt.c
@@ -XXX,XX +XXX,XX @@
  #ifdef CONFIG_LINUX
  #include <linux/vfio.h>
  #endif
 -#include "hw/arm/sysbus-fdt.h"
 +#include "hw/core/sysbus-fdt.h"
  #include "qemu/error-report.h"
  #include "sysemu/device_tree.h"
  #include "sysemu/tpm.h"
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@
  arm_ss = ss.source_set()
  arm_ss.add(files('boot.c'), fdt)
 -arm_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
  arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
  arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
  arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
 diff --git a/hw/core/meson.build b/hw/core/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/meson.build
 +++ b/hw/core/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c'))
  softmmu_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c'))
  softmmu_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c'))
  softmmu_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c'))
 +softmmu_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
  softmmu_ss.add(files(
    'cpu-sysemu.c',
 --
-.35.1
+.41.0

-[PULL 18/25] target/riscv: Fix incorrect PTE merge in walk_pte
+[PULL 47/54] hw/char: riscv_htif: replace exit calls with proper shutdown
-From: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
+From: Clément Chigot <chigot@adacore.com>
-Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
+This replaces the exit calls by shutdown requests, ensuring a proper
-case, walk_pte will erroneously merge them.
+cleanup of Qemu. Otherwise, some connections like gdb could be broken
 before its final packet ("Wxx") is being sent. This part, being done
 inside qemu_cleanup function, can be reached only when the main loop
 exits after a shutdown request.
-Enforce the split up, by tracking the virtual base address.
+Signed-off-by: Clément Chigot <chigot@adacore.com>
 Let's say we have the mapping:
 x81200000 -> 0x89623000 (4K)
 x8120f000 -> 0x89624000 (4K)
 Before, walk_pte would have shown:
 vaddr            paddr            size             attr
 ---------------- ---------------- ---------------- -------
 0000000081200000 0000000089623000 0000000000002000 rwxu-ad
 as it only checks for subsequent paddrs. With this patch, it becomes:
 vaddr            paddr            size             attr
 ---------------- ---------------- ---------------- -------
 0000000081200000 0000000089623000 0000000000001000 rwxu-ad
 000000008120f000 0000000089624000 0000000000001000 rwxu-ad
 Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220423215907.673663-1-ralf.ramsauer@oth-regensburg.de>
+Message-ID: <20231003071427.188697-5-chigot@adacore.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/monitor.c | 11 +++++++----
+ hw/char/riscv_htif.c | 5 ++++-
-file changed, 7 insertions(+), 4 deletions(-)
+file changed, 4 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
+diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/monitor.c
+--- a/hw/char/riscv_htif.c
-+++ b/target/riscv/monitor.c
++++ b/hw/char/riscv_htif.c
-@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
+@@ -XXX,XX +XXX,XX @@
- {
+ #include "exec/address-spaces.h"
-     hwaddr pte_addr;
+ #include "exec/tswap.h"
-     hwaddr paddr;
+ #include "sysemu/dma.h"
-+    target_ulong last_start = -1;
++#include "sysemu/runstate.h"
-     target_ulong pgsize;
-     target_ulong pte;
+ #define RISCV_DEBUG_HTIF 0
-     int ptshift;
+ #define HTIF_DEBUG(fmt, ...)                                                   \
-@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
+@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
-                  * A leaf PTE has been found
+                     g_free(sig_data);
                   *
                   * If current PTE's permission bits differ from the last one,
 -                 * or current PTE's ppn does not make a contiguous physical
 -                 * address block together with the last one, print out the last
 -                 * contiguous mapped block details.
 +                 * or the current PTE breaks up a contiguous virtual or
 +                 * physical mapping, address block together with the last one,
 +                 * print out the last contiguous mapped block details.
                   */
                  if ((*last_attr != attr) ||
 -                    (*last_paddr + *last_size != paddr)) {
 +                    (*last_paddr + *last_size != paddr) ||
 +                    (last_start + *last_size != start)) {
                      print_pte(mon, va_bits, *vbase, *pbase,
                                *last_paddr + *last_size - *pbase, *last_attr);
@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
                      *last_attr = attr;
                  }
-+                last_start = start;
+-                exit(exit_code);
-                 *last_paddr = paddr;
++                qemu_system_shutdown_request_with_code(
-                 *last_size = pgsize;
++                    SHUTDOWN_CAUSE_GUEST_SHUTDOWN, exit_code);
 +                return;
              } else {
+                 uint64_t syscall[8];
+                 cpu_physical_memory_read(payload, syscall, sizeof(syscall));
 --
-.35.1
+.41.0

-[PULL 05/25] target/riscv: rvk: add support for zbkb extension
+[PULL 48/54] gdbstub: replace exit calls with proper shutdown for softmmu
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Clément Chigot <chigot@adacore.com>
- - reuse partial instructions of zbb extension, update extension check for them
+This replaces the exit calls by shutdown requests, ensuring a proper
- - add brev8, pack, packh, packw, unzip, zip instructions
+cleanup of Qemu. Features like net/vhost-vdpa.c are expecting
 qemu_cleanup to be called to remove their last residuals.
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Signed-off-by: Clément Chigot <chigot@adacore.com>
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20231003071427.188697-6-chigot@adacore.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |  3 +
+ include/gdbstub/syscalls.h | 9 +++++++++
- target/riscv/insn32.decode              | 45 +++++++-----
+ gdbstub/gdbstub.c          | 5 +++--
- target/riscv/bitmanip_helper.c          | 53 ++++++++++++++
+ gdbstub/system.c           | 6 ++++++
- target/riscv/translate.c                |  7 ++
+ gdbstub/user.c             | 6 ++++++
- target/riscv/insn_trans/trans_rvb.c.inc | 94 +++++++++++++++++++++----
+files changed, 24 insertions(+), 2 deletions(-)
 files changed, 174 insertions(+), 28 deletions(-)
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+diff --git a/include/gdbstub/syscalls.h b/include/gdbstub/syscalls.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/include/gdbstub/syscalls.h
-+++ b/target/riscv/helper.h
++++ b/include/gdbstub/syscalls.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
+@@ -XXX,XX +XXX,XX @@ int use_gdb_syscalls(void);
- /* Bitmanip */
+  */
- DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ void gdb_exit(int code);
- DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-+DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
++/**
-+DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
++ * gdb_qemu_exit: ask qemu to exit
-+DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
++ * @code: exit code reported
++ *
- /* Floating Point - Half Precision */
++ * This requests qemu to exit. This function is allowed to return as
- DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
++ * the exit request might be processed asynchronously by qemu backend.
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
++ */
 +void gdb_qemu_exit(int code);
 +
  #endif /* _SYSCALLS_H_ */
 diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/gdbstub/gdbstub.c
-+++ b/target/riscv/insn32.decode
++++ b/gdbstub/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ sh2add_uw  0010000 .......... 100 ..... 0111011 @r
+@@ -XXX,XX +XXX,XX @@ static void handle_v_kill(GArray *params, void *user_ctx)
- sh3add_uw  0010000 .......... 110 ..... 0111011 @r
+     gdb_put_packet("OK");
- slli_uw    00001 ............ 001 ..... 0011011 @sh
+     error_report("QEMU: Terminated via GDBstub");
+     gdb_exit(0);
--# *** RV32 Zbb Standard Extension ***
+-    exit(0);
-+# *** RV32 Zbb/Zbkb Standard Extension ***
++    gdb_qemu_exit(0);
- andn       0100000 .......... 111 ..... 0110011 @r
+ }
-+rol        0110000 .......... 001 ..... 0110011 @r
-+ror        0110000 .......... 101 ..... 0110011 @r
+ static const GdbCmdParseEntry gdb_v_commands_table[] = {
-+rori       01100 ............ 101 ..... 0010011 @sh
+@@ -XXX,XX +XXX,XX @@ static int gdb_handle_packet(const char *line_buf)
-+# The encoding for rev8 differs between RV32 and RV64.
+         /* Kill the target */
-+# rev8_32 denotes the RV32 variant.
+         error_report("QEMU: Terminated via GDBstub");
-+rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
+         gdb_exit(0);
-+# The encoding for zext.h differs between RV32 and RV64.
+-        exit(0);
-+# zext_h_32 denotes the RV32 variant.
++        gdb_qemu_exit(0);
 +        break;
      case 'D':
          {
              static const GdbCmdParseEntry detach_cmd_desc = {
 diff --git a/gdbstub/system.c b/gdbstub/system.c
 index XXXXXXX..XXXXXXX 100644
 --- a/gdbstub/system.c
 +++ b/gdbstub/system.c
@@ -XXX,XX +XXX,XX @@ void gdb_exit(int code)
      qemu_chr_fe_deinit(&gdbserver_system_state.chr, true);
  }
 +void gdb_qemu_exit(int code)
 +{
-+  zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
++    qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_SHUTDOWN,
-+  pack       0000100 ..... ..... 100 ..... 0110011 @r
++                                           code);
 +}
 +xnor       0100000 .......... 100 ..... 0110011 @r
 +# *** RV32 extra Zbb Standard Extension ***
  clz        011000 000000 ..... 001 ..... 0010011 @r2
  cpop       011000 000010 ..... 001 ..... 0010011 @r2
  ctz        011000 000001 ..... 001 ..... 0010011 @r2
@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
  minu       0000101 .......... 101 ..... 0110011 @r
  orc_b      001010 000111 ..... 101 ..... 0010011 @r2
  orn        0100000 .......... 110 ..... 0110011 @r
 -# The encoding for rev8 differs between RV32 and RV64.
 -# rev8_32 denotes the RV32 variant.
 -rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
 -rol        0110000 .......... 001 ..... 0110011 @r
 -ror        0110000 .......... 101 ..... 0110011 @r
 -rori       01100 ............ 101 ..... 0010011 @sh
  sext_b     011000 000100 ..... 001 ..... 0010011 @r2
  sext_h     011000 000101 ..... 001 ..... 0010011 @r2
 -xnor       0100000 .......... 100 ..... 0110011 @r
 -# The encoding for zext.h differs between RV32 and RV64.
 -# zext_h_32 denotes the RV32 variant.
 -zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
 +# *** RV32 extra Zbkb Standard Extension ***
 +brev8      0110100 00111 ..... 101 ..... 0010011 @r2  #grevi
 +packh      0000100  .......... 111 ..... 0110011 @r
 +unzip      0000100 01111 ..... 101 ..... 0010011 @r2  #unshfl
 +zip        0000100 01111 ..... 001 ..... 0010011 @r2  #shfl
 -# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
 -clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 -ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 -cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 +# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
  # The encoding for rev8 differs between RV32 and RV64.
  # When executing on RV64, the encoding used in RV32 is an illegal
  # instruction, so we use different handler functions to differentiate.
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
  # The encoding for zext.h differs between RV32 and RV64.
  # When executing on RV64, the encoding used in RV32 is an illegal
  # instruction, so we use different handler functions to differentiate.
 -zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 +{
 +  zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 +  packw      0000100 ..... ..... 100 ..... 0111011 @r
 +}
 +# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
 +clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 +ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 +cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
  # *** RV32 Zbc Standard Extension ***
  clmul      0000101 .......... 001 ..... 0110011 @r
 diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/bitmanip_helper.c
 +++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
      return result;
  }
 +
 +static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
 +{
 +    return ((x & mask) << shift) | ((x & ~mask) >> shift);
 +}
 +
-+target_ulong HELPER(brev8)(target_ulong rs1)
+ /*
-+{
+  * Memory access
-+    target_ulong x = rs1;
+  */
 diff --git a/gdbstub/user.c b/gdbstub/user.c
 index XXXXXXX..XXXXXXX 100644
 --- a/gdbstub/user.c
 +++ b/gdbstub/user.c
@@ -XXX,XX +XXX,XX @@ void gdb_exit(int code)
          gdb_put_packet(buf);
          gdbserver_state.allow_stop_reply = false;
      }
 +
-+    x = do_swap(x, 0x5555555555555555ull, 1);
-+    x = do_swap(x, 0x3333333333333333ull, 2);
-+    x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
-+    return x;
 +}
 +
-+static const uint64_t shuf_masks[] = {
++void gdb_qemu_exit(int code)
 +    dup_const(MO_8, 0x44),
 +    dup_const(MO_8, 0x30),
 +    dup_const(MO_16, 0x0f00),
 +    dup_const(MO_32, 0xff0000)
 +};
 +
 +static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
 +                                         uint64_t maskR, int shift)
 +{
-+    target_ulong x = src & ~(maskL | maskR);
++    exit(code);
 +
 +    x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
 +    return x;
 +}
 +
 +target_ulong HELPER(unzip)(target_ulong rs1)
 +{
 +    target_ulong x = rs1;
 +
 +    x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
 +    x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
 +    x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
 +    x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
 +    return x;
 +}
 +
 +target_ulong HELPER(zip)(target_ulong rs1)
 +{
 +    target_ulong x = rs1;
 +
 +    x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
 +    x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
 +    x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
 +    x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
 +    return x;
 +}
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
      }                                  \
  } while (0)
 +#define REQUIRE_EITHER_EXT(ctx, A, B) do {       \
 +    if (!ctx->cfg_ptr->ext_##A &&      \
 +        !ctx->cfg_ptr->ext_##B) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  static int ex_rvc_register(DisasContext *ctx, int reg)
  {
      return 8 + reg;
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
  /*
 - * RISC-V translation routines for the Zb[abcs] Standard Extension.
 + * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
   *
   * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
   * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_ZBKB(ctx) do {                   \
 +    if (!ctx->cfg_ptr->ext_zbkb) {               \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  static void gen_clz(TCGv ret, TCGv arg1)
  {
      tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -XXX,XX +XXX,XX @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
  static bool trans_andn(DisasContext *ctx, arg_andn *a)
  {
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      return gen_logic(ctx, a, tcg_gen_andc_tl);
  }
- static bool trans_orn(DisasContext *ctx, arg_orn *a)
+ int gdb_handlesig(CPUState *cpu, int sig)
  {
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      return gen_logic(ctx, a, tcg_gen_orc_tl);
  }
  static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
  {
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      return gen_logic(ctx, a, tcg_gen_eqv_tl);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_ror(DisasContext *ctx, arg_ror *a)
  {
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
  static bool trans_rori(DisasContext *ctx, arg_rori *a)
  {
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
                                     tcg_gen_rotri_tl, gen_roriw, NULL);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_rol(DisasContext *ctx, arg_rol *a)
  {
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_rev8_32(TCGv ret, TCGv src1)
  static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
  {
      REQUIRE_32BIT(ctx);
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
  }
  static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
  static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      ctx->ol = MXL_RV32;
      return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      ctx->ol = MXL_RV32;
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
  static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_ZBB(ctx);
 +    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
      ctx->ol = MXL_RV32;
      return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
      REQUIRE_ZBC(ctx);
      return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
  }
 +
 +static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
 +{
 +    tcg_gen_deposit_tl(ret, src1, src2,
 +                       TARGET_LONG_BITS / 2,
 +                       TARGET_LONG_BITS / 2);
 +}
 +
 +static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
 +{
 +    TCGv t = tcg_temp_new();
 +
 +    tcg_gen_ext8u_tl(t, src2);
 +    tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
 +    tcg_temp_free(t);
 +}
 +
 +static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
 +{
 +    TCGv t = tcg_temp_new();
 +
 +    tcg_gen_ext16s_tl(t, src2);
 +    tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
 +    tcg_temp_free(t);
 +}
 +
 +static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
 +{
 +    REQUIRE_ZBKB(ctx);
 +    return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
 +}
 +
 +static bool trans_pack(DisasContext *ctx, arg_pack *a)
 +{
 +    REQUIRE_ZBKB(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
 +}
 +
 +static bool trans_packh(DisasContext *ctx, arg_packh *a)
 +{
 +    REQUIRE_ZBKB(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
 +}
 +
 +static bool trans_packw(DisasContext *ctx, arg_packw *a)
 +{
 +    REQUIRE_64BIT(ctx);
 +    REQUIRE_ZBKB(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
 +}
 +
 +static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
 +{
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZBKB(ctx);
 +    return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
 +}
 +
 +static bool trans_zip(DisasContext *ctx, arg_zip *a)
 +{
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZBKB(ctx);
 +    return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
 +}
 --
-.35.1
+.41.0

-New patch
+[PULL 49/54] target/riscv/kvm: improve 'init_multiext_cfg' error msg
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Our error message is returning the value of 'ret', which will be always
+-1 in case of error, and will not be that useful:
+qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error -1
+Improve the error message by outputting 'errno' instead of 'ret'. Use
+strerrorname_np() to output the error name instead of the error code.
+This will give us what we need to know right away:
+qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error code: ENOENT
+Given that we're going to exit(1) in this condition instead of
+attempting to recover, remove the 'kvm_riscv_destroy_scratch_vcpu()'
+call.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20231003132148.797921-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm/kvm-cpu.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm/kvm-cpu.c
++++ b/target/riscv/kvm/kvm-cpu.c
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
+                 val = false;
+             } else {
+                 error_report("Unable to read ISA_EXT KVM register %s, "
+-                             "error %d", multi_ext_cfg->name, ret);
+-                kvm_riscv_destroy_scratch_vcpu(kvmcpu);
++                             "error code: %s", multi_ext_cfg->name,
++                             strerrorname_np(errno));
+                 exit(EXIT_FAILURE);
+             }
+         } else {
+--
+.41.0

-[PULL 20/25] hw/riscv: virt: Add a machine done notifier
+[PULL 50/54] target/riscv/kvm: support KVM_GET_REG_LIST
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Move the binary and device tree loading code to the machine done
+KVM for RISC-V started supporting KVM_GET_REG_LIST in Linux 6.6. It
-notifier. This allows us to prepare for editing the device tree as part
+consists of a KVM ioctl() that retrieves a list of all available regs
-of the notifier.
+for get_one_reg/set_one_reg. Regs that aren't present in the list aren't
 supported in the host.
-This is based on similar code in the ARM virt machine.
+This simplifies our lives when initing the KVM regs since we don't have
 to always attempt a KVM_GET_ONE_REG for all regs QEMU knows. We'll only
 attempt a get_one_reg() if we're sure the reg is supported, i.e. it was
 retrieved by KVM_GET_REG_LIST. Any error in get_one_reg() will then
 always considered fatal, instead of having to handle special error codes
 that might indicate a non-fatal failure.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Start by moving the current kvm_riscv_init_multiext_cfg() logic into a
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+new kvm_riscv_read_multiext_legacy() helper. We'll prioritize using
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+KVM_GET_REG_LIST, so check if we have it available and, in case we
-Message-Id: <20220427234146.1130752-2-alistair.francis@opensource.wdc.com>
+don't, use the legacy() logic.
 Otherwise, retrieve the available reg list and use it to check if the
 host supports our known KVM regs, doing the usual get_one_reg() for
 the supported regs and setting cpu->cfg accordingly.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20231003132148.797921-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |   1 +
+ target/riscv/kvm/kvm-cpu.c | 96 +++++++++++++++++++++++++++++++++++++-
- hw/riscv/virt.c         | 191 +++++++++++++++++++++-------------------
+file changed, 95 insertions(+), 1 deletion(-)
 files changed, 102 insertions(+), 90 deletions(-)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/include/hw/riscv/virt.h
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
-     MachineState parent;
+     }
      /*< public >*/
 +    Notifier machine_done;
      RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
      DeviceState *irqchip[VIRT_SOCKETS_MAX];
      PFlashCFI01 *flash[2];
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
      return aplic_m;
  }
-+static void virt_machine_done(Notifier *notifier, void *data)
+-static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
 +static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
 +                                           KVMScratchCPU *kvmcpu)
  {
      CPURISCVState *env = &cpu->env;
      uint64_t val;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      }
  }
 +static int uint64_cmp(const void *a, const void *b)
 +{
-+    RISCVVirtState *s = container_of(notifier, RISCVVirtState,
++    uint64_t val1 = *(const uint64_t *)a;
-+                                     machine_done);
++    uint64_t val2 = *(const uint64_t *)b;
-+    const MemMapEntry *memmap = virt_memmap;
++
-+    MachineState *machine = MACHINE(s);
++    if (val1 < val2) {
-+    target_ulong start_addr = memmap[VIRT_DRAM].base;
++        return -1;
-+    target_ulong firmware_end_addr, kernel_start_addr;
++    }
-+    uint32_t fdt_load_addr;
++
-+    uint64_t kernel_entry;
++    if (val1 > val2) {
 +        return 1;
 +    }
 +
 +    return 0;
 +}
 +
 +static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
 +{
 +    KVMCPUConfig *multi_ext_cfg;
 +    struct kvm_one_reg reg;
 +    struct kvm_reg_list rl_struct;
 +    struct kvm_reg_list *reglist;
 +    uint64_t val, reg_id, *reg_search;
 +    int i, ret;
 +
 +    rl_struct.n = 0;
 +    ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct);
 +
 +    /*
-+     * Only direct boot kernel is currently supported for KVM VM,
++     * If KVM_GET_REG_LIST isn't supported we'll get errno 22
-+     * so the "-bios" parameter is not supported when KVM is enabled.
++     * (EINVAL). Use read_legacy() in this case.
 +     */
-+    if (kvm_enabled()) {
++    if (errno == EINVAL) {
-+        if (machine->firmware) {
++        return kvm_riscv_read_multiext_legacy(cpu, kvmcpu);
-+            if (strcmp(machine->firmware, "none")) {
++    } else if (errno != E2BIG) {
-+                error_report("Machine mode firmware is not supported in "
++        /*
-+                             "combination with KVM.");
++         * E2BIG is an expected error message for the API since we
-+                exit(1);
++         * don't know the number of registers. The right amount will
-+            }
++         * be written in rl_struct.n.
-+        } else {
++         *
-+            machine->firmware = g_strdup("none");
++         * Error out if we get any other errno.
-+        }
++         */
 +        error_report("Error when accessing get-reg-list, code: %s",
 +                     strerrorname_np(errno));
 +        exit(EXIT_FAILURE);
 +    }
 +
-+    if (riscv_is_32bit(&s->soc[0])) {
++    reglist = g_malloc(sizeof(struct kvm_reg_list) +
-+        firmware_end_addr = riscv_find_and_load_firmware(machine,
++                       rl_struct.n * sizeof(uint64_t));
-+                                    RISCV32_BIOS_BIN, start_addr, NULL);
++    reglist->n = rl_struct.n;
-+    } else {
++    ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist);
-+        firmware_end_addr = riscv_find_and_load_firmware(machine,
++    if (ret) {
-+                                    RISCV64_BIOS_BIN, start_addr, NULL);
++        error_report("Error when reading KVM_GET_REG_LIST, code %s ",
 +                     strerrorname_np(errno));
 +        exit(EXIT_FAILURE);
 +    }
 +
-+    if (machine->kernel_filename) {
++    /* sort reglist to use bsearch() */
-+        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
++    qsort(&reglist->reg, reglist->n, sizeof(uint64_t), uint64_cmp);
 +                                                         firmware_end_addr);
 +
-+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
++    for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
-+                                         kernel_start_addr, NULL);
++        multi_ext_cfg = &kvm_multi_ext_cfgs[i];
 +        reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT,
 +                                  multi_ext_cfg->kvm_reg_id);
 +        reg_search = bsearch(&reg_id, reglist->reg, reglist->n,
 +                             sizeof(uint64_t), uint64_cmp);
 +        if (!reg_search) {
 +            continue;
 +        }
 +
-+        if (machine->initrd_filename) {
++        reg.id = reg_id;
-+            hwaddr start;
++        reg.addr = (uint64_t)&val;
-+            hwaddr end = riscv_load_initrd(machine->initrd_filename,
++        ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg);
-+                                           machine->ram_size, kernel_entry,
++        if (ret != 0) {
-+                                           &start);
++            error_report("Unable to read ISA_EXT KVM register %s, "
-+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
++                         "error code: %s", multi_ext_cfg->name,
-+                                  "linux,initrd-start", start);
++                         strerrorname_np(errno));
-+            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
++            exit(EXIT_FAILURE);
 +                                  end);
 +        }
-+    } else {
++
-+       /*
++        multi_ext_cfg->supported = true;
-+        * If dynamic firmware is used, it doesn't know where is the next mode
++        kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
 +        * if kernel argument is not set.
 +        */
 +        kernel_entry = 0;
 +    }
 +
-+    if (drive_get(IF_PFLASH, 0, 0)) {
++    if (cpu->cfg.ext_icbom) {
-+        /*
++        kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
 +         * Pflash was supplied, let's overwrite the address we jump to after
 +         * reset to the base of the flash.
 +         */
 +        start_addr = virt_memmap[VIRT_FLASH].base;
 +    }
 +
-+    /*
++    if (cpu->cfg.ext_icboz) {
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
++        kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
 +     * tree cannot be altered and we get FDT_ERR_NOSPACE.
 +     */
 +    s->fw_cfg = create_fw_cfg(machine);
 +    rom_set_fw(s->fw_cfg);
 +
 +    /* Compute the fdt load address in dram */
 +    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
 +                                   machine->ram_size, machine->fdt);
 +    /* load the reset vector */
 +    riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
 +                              virt_memmap[VIRT_MROM].base,
 +                              virt_memmap[VIRT_MROM].size, kernel_entry,
 +                              fdt_load_addr, machine->fdt);
 +
 +    /*
 +     * Only direct boot kernel is currently supported for KVM VM,
 +     * So here setup kernel start address and fdt address.
 +     * TODO:Support firmware loading and integrate to TCG start
 +     */
 +    if (kvm_enabled()) {
 +        riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
 +    }
 +}
 +
- static void virt_machine_init(MachineState *machine)
+ static void riscv_init_kvm_registers(Object *cpu_obj)
  {
-     const MemMapEntry *memmap = virt_memmap;
+     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      MemoryRegion *system_memory = get_system_memory();
      MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
      char *soc_name;
 -    target_ulong start_addr = memmap[VIRT_DRAM].base;
 -    target_ulong firmware_end_addr, kernel_start_addr;
 -    uint32_t fdt_load_addr;
 -    uint64_t kernel_entry;
      DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
      int i, base_hartid, hart_count;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
          machine->ram);
 -    /* create device tree */
 -    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 -               riscv_is_32bit(&s->soc[0]));
 -
      /* boot rom */
      memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
                             memmap[VIRT_MROM].size, &error_fatal);
      memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                  mask_rom);
 -    /*
 -     * Only direct boot kernel is currently supported for KVM VM,
 -     * so the "-bios" parameter is not supported when KVM is enabled.
 -     */
 -    if (kvm_enabled()) {
 -        if (machine->firmware) {
 -            if (strcmp(machine->firmware, "none")) {
 -                error_report("Machine mode firmware is not supported in "
 -                             "combination with KVM.");
 -                exit(1);
 -            }
 -        } else {
 -            machine->firmware = g_strdup("none");
 -        }
 -    }
 -
 -    if (riscv_is_32bit(&s->soc[0])) {
 -        firmware_end_addr = riscv_find_and_load_firmware(machine,
 -                                    RISCV32_BIOS_BIN, start_addr, NULL);
 -    } else {
 -        firmware_end_addr = riscv_find_and_load_firmware(machine,
 -                                    RISCV64_BIOS_BIN, start_addr, NULL);
 -    }
 -
 -    if (machine->kernel_filename) {
 -        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
 -                                                         firmware_end_addr);
 -
 -        kernel_entry = riscv_load_kernel(machine->kernel_filename,
 -                                         kernel_start_addr, NULL);
 -
 -        if (machine->initrd_filename) {
 -            hwaddr start;
 -            hwaddr end = riscv_load_initrd(machine->initrd_filename,
 -                                           machine->ram_size, kernel_entry,
 -                                           &start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 -                                  "linux,initrd-start", start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
 -                                  end);
 -        }
 -    } else {
 -       /*
 -        * If dynamic firmware is used, it doesn't know where is the next mode
 -        * if kernel argument is not set.
 -        */
 -        kernel_entry = 0;
 -    }
 -
 -    if (drive_get(IF_PFLASH, 0, 0)) {
 -        /*
 -         * Pflash was supplied, let's overwrite the address we jump to after
 -         * reset to the base of the flash.
 -         */
 -        start_addr = virt_memmap[VIRT_FLASH].base;
 -    }
 -
 -    /*
 -     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
 -     * tree cannot be altered and we get FDT_ERR_NOSPACE.
 -     */
 -    s->fw_cfg = create_fw_cfg(machine);
 -    rom_set_fw(s->fw_cfg);
 -
 -    /* Compute the fdt load address in dram */
 -    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
 -                                   machine->ram_size, machine->fdt);
 -    /* load the reset vector */
 -    riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
 -                              virt_memmap[VIRT_MROM].base,
 -                              virt_memmap[VIRT_MROM].size, kernel_entry,
 -                              fdt_load_addr, machine->fdt);
 -
 -    /*
 -     * Only direct boot kernel is currently supported for KVM VM,
 -     * So here setup kernel start address and fdt address.
 -     * TODO:Support firmware loading and integrate to TCG start
 -     */
 -    if (kvm_enabled()) {
 -        riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
 -    }
 -
      /* SiFive Test MMIO device */
      sifive_test_create(memmap[VIRT_TEST].base);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                    drive_get(IF_PFLASH, 0, i));
      }
      virt_flash_map(s, system_memory);
 +
 +    /* create device tree */
 +    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 +               riscv_is_32bit(&s->soc[0]));
 +
 +    s->machine_done.notify = virt_machine_done;
 +    qemu_add_machine_init_done_notifier(&s->machine_done);
  }
  static void virt_machine_instance_init(Object *obj)
 --
-.35.1
+.41.0

-New patch
+[PULL 51/54] target/riscv/tcg: remove RVG warning
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Vendor CPUs that set RVG are displaying user warnings about other
+extensions that RVG must enable, one warning per CPU. E.g.:
+$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic
+qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
+This happens because we decided a while ago that, for simplicity, vendor
+CPUs could set RVG instead of setting each G extension individually in
+their cpu_init(). Our warning isn't taking that into account, and we're
+bugging users with a warning that we're causing ourselves.
+In a closer look we conclude that this warning is not warranted in any
+other circumstance since we're just following the ISA [1], which states
+in chapter 24:
+"One goal of the RISC-V project is that it be used as a stable software
+development target. For this purpose, we define a combination of a base
+ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,
+Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for
+the IMAFDZicsr Zifencei combination of instruction-set extensions."
+With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly
+enables 'G' is an expected behavior and the warning is unneeded. Any
+user caught by surprise should refer to the ISA.
+Remove the warning when handling RVG.
+[1] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
+Reported-by: Paul A. Clarke <pclarke@ventanamicro.com>
+Suggested-by: Andrew Jones <ajones@ventanamicro.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20231003122539.775932-1-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/tcg/tcg-cpu.c | 1 -
+file changed, 1 deletion(-)
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+             return;
+         }
+-        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
+--
+.41.0

-New patch
+[PULL 52/54] target/riscv: Use env_archcpu for better performance
+From: "Richard W.M. Jones" <rjones@redhat.com>
+RISCV_CPU(cs) uses a checked cast.  When QOM cast debugging is enabled
+this adds about 5% total overhead when emulating RV64 on x86-64 host.
+Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk
+disk.  The guest has a copy of the qemu source tree.  The test
+involves compiling the qemu source tree with 'make clean; time make -j16'.
+Before making this change the compile step took 449 & 447 seconds over
+two consecutive runs.
+After making this change: 428 & 421 seconds.
+The saving is over 5%.
+Thanks: Paolo Bonzini
+Thanks: Philippe Mathieu-Daudé
+Signed-off-by: Richard W.M. Jones <rjones@redhat.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20231009124859.3373696-2-rjones@redhat.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu_helper.c | 3 +--
+file changed, 1 insertion(+), 2 deletions(-)
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
+ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+                           uint64_t *cs_base, uint32_t *pflags)
+ {
+-    CPUState *cs = env_cpu(env);
+-    RISCVCPU *cpu = RISCV_CPU(cs);
++    RISCVCPU *cpu = env_archcpu(env);
+     RISCVExtStatus fs, vs;
+     uint32_t flags = 0;
+--
+.41.0

-[PULL 16/25] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
+[PULL 53/54] target/riscv: deprecate capital 'Z' CPU properties
-From: Weiwei Li <liweiwei@iscas.ac.cn>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Co-authored-by: Ruibo Lu <luruibo2000@163.com>
+At this moment there are eleven CPU extension properties that starts
-Co-authored-by: Zewen Ye <lustrew@foxmail.com>
+with capital 'Z': Zifencei, Zicsr, Zihintntl, Zihintpause, Zawrs, Zfa,
-Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Zfh, Zfhmin, Zve32f, Zve64f and Zve64d. All other extensions are named
-Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
+with lower-case letters.
 We want all properties to be named with lower-case letters since it's
 consistent with the riscv-isa string that we create in the FDT. Having
 these 11 properties to be exceptions can be confusing.
 Deprecate all of them. Create their lower-case counterpart to be used as
 maintained CPU properties. When trying to use any deprecated property a
 warning message will be displayed, recommending users to switch to the
 lower-case variant:
 ./build/qemu-system-riscv64 -M virt -cpu rv64,Zifencei=true --nographic
 qemu-system-riscv64: warning: CPU property 'Zifencei' is deprecated. Please use 'zifencei' instead
 This will give users some time to change their scripts before we remove
 the capital 'Z' properties entirely.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20231009112817.8896-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- disas/riscv.c | 173 +++++++++++++++++++++++++++++++++++++++++++++++++-
+ docs/about/deprecated.rst  | 23 ++++++++++++++++++++++
-file changed, 172 insertions(+), 1 deletion(-)
+ target/riscv/cpu.h         |  1 +
+ target/riscv/cpu.c         | 39 +++++++++++++++++++++++++++-----------
-diff --git a/disas/riscv.c b/disas/riscv.c
+ target/riscv/tcg/tcg-cpu.c | 31 +++++++++++++++++++++++++++++-
-index XXXXXXX..XXXXXXX 100644
+files changed, 82 insertions(+), 12 deletions(-)
---- a/disas/riscv.c
-+++ b/disas/riscv.c
+diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+index XXXXXXX..XXXXXXX 100644
-     rv_codec_css_swsp,
+--- a/docs/about/deprecated.rst
-     rv_codec_css_sdsp,
++++ b/docs/about/deprecated.rst
-     rv_codec_css_sqsp,
+@@ -XXX,XX +XXX,XX @@ of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete
-+    rv_codec_k_bs,
+ CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any'
-+    rv_codec_k_rnum,
+ CPU type starting in 8.2.
- } rv_codec;
++RISC-V CPU properties which start with capital 'Z' (since 8.2)
- typedef enum {
++^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-@@ -XXX,XX +XXX,XX @@ typedef enum {
++
-     rv_op_bclr = 359,
++All RISC-V CPU properties which start with capital 'Z' are being deprecated
-     rv_op_binv = 360,
++starting in 8.2. The reason is that they were wrongly added with capital 'Z'
-     rv_op_bext = 361,
++in the past. CPU properties were later added with lower-case names, which
-+    rv_op_aes32esmi = 362,
++is the format we want to use from now on.
-+    rv_op_aes32esi = 363,
++
-+    rv_op_aes32dsmi = 364,
++Users which try to use these deprecated properties will receive a warning
-+    rv_op_aes32dsi = 365,
++recommending to switch to their stable counterparts:
-+    rv_op_aes64ks1i = 366,
++
-+    rv_op_aes64ks2 = 367,
++- "Zifencei" should be replaced with "zifencei"
-+    rv_op_aes64im = 368,
++- "Zicsr" should be replaced with "zicsr"
-+    rv_op_aes64esm = 369,
++- "Zihintntl" should be replaced with "zihintntl"
-+    rv_op_aes64es = 370,
++- "Zihintpause" should be replaced with "zihintpause"
-+    rv_op_aes64dsm = 371,
++- "Zawrs" should be replaced with "zawrs"
-+    rv_op_aes64ds = 372,
++- "Zfa" should be replaced with "zfa"
-+    rv_op_sha256sig0 = 373,
++- "Zfh" should be replaced with "zfh"
-+    rv_op_sha256sig1 = 374,
++- "Zfhmin" should be replaced with "zfhmin"
-+    rv_op_sha256sum0 = 375,
++- "Zve32f" should be replaced with "zve32f"
-+    rv_op_sha256sum1 = 376,
++- "Zve64f" should be replaced with "zve64f"
-+    rv_op_sha512sig0 = 377,
++- "Zve64d" should be replaced with "zve64d"
-+    rv_op_sha512sig1 = 378,
++
-+    rv_op_sha512sum0 = 379,
+ Block device options
-+    rv_op_sha512sum1 = 380,
+ ''''''''''''''''''''
-+    rv_op_sha512sum0r = 381,
-+    rv_op_sha512sum1r = 382,
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-+    rv_op_sha512sig0l = 383,
+index XXXXXXX..XXXXXXX 100644
-+    rv_op_sha512sig0h = 384,
+--- a/target/riscv/cpu.h
-+    rv_op_sha512sig1l = 385,
++++ b/target/riscv/cpu.h
-+    rv_op_sha512sig1h = 386,
+@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPUMultiExtConfig {
-+    rv_op_sm3p0 = 387,
+ extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
-+    rv_op_sm3p1 = 388,
+ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
-+    rv_op_sm4ed = 389,
+ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
-+    rv_op_sm4ks = 390,
++extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
-+    rv_op_brev8 = 391,
+ extern Property riscv_cpu_options[];
-+    rv_op_pack = 392,
-+    rv_op_packh = 393,
+ typedef struct isa_ext_data {
-+    rv_op_packw = 394,
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-+    rv_op_unzip = 395,
+index XXXXXXX..XXXXXXX 100644
-+    rv_op_zip = 396,
+--- a/target/riscv/cpu.c
-+    rv_op_xperm4 = 397,
++++ b/target/riscv/cpu.c
-+    rv_op_xperm8 = 398,
+@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
- } rv_op;
+ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+     /* Defaults for standard extensions */
- /* structures */
+     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
-@@ -XXX,XX +XXX,XX @@ typedef struct {
+-    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
-     uint8_t   succ;
+-    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
-     uint8_t   aq;
+-    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
-     uint8_t   rl;
+-    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
-+    uint8_t   bs;
+-    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
-+    uint8_t   rnum;
+-    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
- } rv_decode;
+-    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
+-    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
- typedef struct {
+-    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
-@@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = {
+-    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
- #define rv_fmt_rd_rs2                 "O\t0,2"
+-    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
- #define rv_fmt_rs1_offset             "O\t1,o"
++    MULTI_EXT_CFG_BOOL("zifencei", ext_ifencei, true),
- #define rv_fmt_rs2_offset             "O\t2,o"
++    MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
-+#define rv_fmt_rs1_rs2_bs             "O\t1,2,b"
++    MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
-+#define rv_fmt_rd_rs1_rnum            "O\t0,1,n"
++    MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
++    MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
- /* pseudo-instruction constraints */
++    MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
++    MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
-@@ -XXX,XX +XXX,XX @@ static const rv_comp_data rvcp_csrrw[] = {
++    MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
-     { rv_op_illegal, NULL }
++    MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
 +    MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
      MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
      MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
-+
++/* Deprecated entries marked for future removal */
- static const rv_comp_data rvcp_csrrs[] = {
++const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
-     { rv_op_rdcycle, rvcc_rdcycle },
++    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
-     { rv_op_rdtime, rvcc_rdtime },
++    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
-@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
++    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
-     { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
-     { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
-     { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
-+    { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
++    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
-+    { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
++    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
-+    { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
++    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
-+    { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
++    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
-+    { "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
++    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
-+    { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++
-+    { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
++    DEFINE_PROP_END_OF_LIST(),
-+    { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++};
-+    { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++
-+    { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ Property riscv_cpu_options[] = {
-+    { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+     DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
-+    { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
-+    { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-+    { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+index XXXXXXX..XXXXXXX 100644
-+    { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+--- a/target/riscv/tcg/tcg-cpu.c
-+    { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++++ b/target/riscv/tcg/tcg-cpu.c
-+    { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
-+    { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+     }
 +    { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
 +    { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
 +    { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
 +    { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
 +    { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
  };
  /* CSR names */
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
      case 0x0003: return "fcsr";
      case 0x0004: return "uie";
      case 0x0005: return "utvec";
 +    case 0x0015: return "seed";
      case 0x0040: return "uscratch";
      case 0x0041: return "uepc";
      case 0x0042: return "ucause";
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 1:
                  switch (((inst >> 27) & 0b11111)) {
                  case 0b00000: op = rv_op_slli; break;
 +                case 0b00001:
 +                    switch (((inst >> 20) & 0b1111111)) {
 +                    case 0b0001111: op = rv_op_zip; break;
 +                    }
 +                    break;
 +                case 0b00010:
 +                    switch (((inst >> 20) & 0b1111111)) {
 +                    case 0b0000000: op = rv_op_sha256sum0; break;
 +                    case 0b0000001: op = rv_op_sha256sum1; break;
 +                    case 0b0000010: op = rv_op_sha256sig0; break;
 +                    case 0b0000011: op = rv_op_sha256sig1; break;
 +                    case 0b0000100: op = rv_op_sha512sum0; break;
 +                    case 0b0000101: op = rv_op_sha512sum1; break;
 +                    case 0b0000110: op = rv_op_sha512sig0; break;
 +                    case 0b0000111: op = rv_op_sha512sig1; break;
 +                    case 0b0001000: op = rv_op_sm3p0; break;
 +                    case 0b0001001: op = rv_op_sm3p1; break;
 +                    }
 +                    break;
                  case 0b00101: op = rv_op_bseti; break;
 +                case 0b00110:
 +                    switch (((inst >> 20) & 0b1111111)) {
 +                    case 0b0000000: op = rv_op_aes64im; break;
 +                    default:
 +                        if (((inst >> 24) & 0b0111) == 0b001) {
 +                            op = rv_op_aes64ks1i;
 +                        }
 +                        break;
 +                     }
 +                     break;
                  case 0b01001: op = rv_op_bclri; break;
                  case 0b01101: op = rv_op_binvi; break;
                  case 0b01100:
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 5:
                  switch (((inst >> 27) & 0b11111)) {
                  case 0b00000: op = rv_op_srli; break;
 +                case 0b00001:
 +                    switch (((inst >> 20) & 0b1111111)) {
 +                    case 0b0001111: op = rv_op_unzip; break;
 +                    }
 +                    break;
                  case 0b00101: op = rv_op_orc_b; break;
                  case 0b01000: op = rv_op_srai; break;
                  case 0b01001: op = rv_op_bexti; break;
                  case 0b01100: op = rv_op_rori; break;
                  case 0b01101:
                      switch ((inst >> 20) & 0b1111111) {
 +                    case 0b0011000: op = rv_op_rev8; break;
                      case 0b0111000: op = rv_op_rev8; break;
 +                    case 0b0000111: op = rv_op_brev8; break;
                      }
                      break;
                  }
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 36:
                  switch ((inst >> 20) & 0b11111) {
                  case 0: op = rv_op_zext_h; break;
 +                default: op = rv_op_pack; break;
                  }
                  break;
 +            case 39: op = rv_op_packh; break;
 +
              case 41: op = rv_op_clmul; break;
              case 42: op = rv_op_clmulr; break;
              case 43: op = rv_op_clmulh; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 132: op = rv_op_sh2add; break;
              case 134: op = rv_op_sh3add; break;
              case 161: op = rv_op_bset; break;
 +            case 162: op = rv_op_xperm4; break;
 +            case 164: op = rv_op_xperm8; break;
 +            case 200: op = rv_op_aes64es; break;
 +            case 216: op = rv_op_aes64esm; break;
 +            case 232: op = rv_op_aes64ds; break;
 +            case 248: op = rv_op_aes64dsm; break;
              case 256: op = rv_op_sub; break;
              case 260: op = rv_op_xnor; break;
              case 261: op = rv_op_sra; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 263: op = rv_op_andn; break;
              case 289: op = rv_op_bclr; break;
              case 293: op = rv_op_bext; break;
 +            case 320: op = rv_op_sha512sum0r; break;
 +            case 328: op = rv_op_sha512sum1r; break;
 +            case 336: op = rv_op_sha512sig0l; break;
 +            case 344: op = rv_op_sha512sig1l; break;
 +            case 368: op = rv_op_sha512sig0h; break;
 +            case 376: op = rv_op_sha512sig1h; break;
              case 385: op = rv_op_rol; break;
 -            case 386: op = rv_op_ror; break;
 +            case 389: op = rv_op_ror; break;
              case 417: op = rv_op_binv; break;
 +            case 504: op = rv_op_aes64ks2; break;
 +            }
 +            switch ((inst >> 25) & 0b0011111) {
 +            case 17: op = rv_op_aes32esi; break;
 +            case 19: op = rv_op_aes32esmi; break;
 +            case 21: op = rv_op_aes32dsi; break;
 +            case 23: op = rv_op_aes32dsmi; break;
 +            case 24: op = rv_op_sm4ed; break;
 +            case 26: op = rv_op_sm4ks; break;
              }
              break;
          case 13: op = rv_op_lui; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 36:
                  switch ((inst >> 20) & 0b11111) {
                  case 0: op = rv_op_zext_h; break;
 +                default: op = rv_op_packw; break;
                  }
                  break;
              case 130: op = rv_op_sh1add_uw; break;
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_cimmq(rv_inst inst)
          ((inst << 57) >> 62) << 6;
  }
-+static uint32_t operand_bs(rv_inst inst)
++static bool cpu_ext_is_deprecated(const char *ext_name)
 +{
-+    return (inst << 32) >> 62;
++    return isupper(ext_name[0]);
 +}
 +
-+static uint32_t operand_rnum(rv_inst inst)
++/*
 + * String will be allocated in the heap. Caller is responsible
 + * for freeing it.
 + */
 +static char *cpu_ext_to_lower(const char *ext_name)
 +{
-+    return (inst << 40) >> 60;
++    char *ret = g_malloc0(strlen(ext_name) + 1);
 +
 +    strcpy(ret, ext_name);
 +    ret[0] = tolower(ret[0]);
 +
 +    return ret;
 +}
 +
- /* decode operands */
+ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
- static void decode_inst_operands(rv_decode *dec)
+ {
-@@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec)
+@@ -XXX,XX +XXX,XX @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
-         dec->rs2 = operand_crs2(inst);
+         return;
-         dec->imm = operand_cimmsqsp(inst);
+     }
-         break;
-+    case rv_codec_k_bs:
++    if (cpu_ext_is_deprecated(multi_ext_cfg->name)) {
-+        dec->rs1 = operand_rs1(inst);
++        g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name);
-+        dec->rs2 = operand_rs2(inst);
++
-+        dec->bs = operand_bs(inst);
++        warn_report("CPU property '%s' is deprecated. Please use '%s' instead",
-+        break;
++                    multi_ext_cfg->name, lower);
-+    case rv_codec_k_rnum:
++    }
-+        dec->rd = operand_rd(inst);
++
-+        dec->rs1 = operand_rs1(inst);
+     g_hash_table_insert(multi_ext_user_opts,
-+        dec->rnum = operand_rnum(inst);
+                         GUINT_TO_POINTER(multi_ext_cfg->offset),
-+        break;
+                         (gpointer)value);
-     };
+@@ -XXX,XX +XXX,XX @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
- }
+                                    const RISCVCPUMultiExtConfig *multi_cfg)
+ {
-@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
+     bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
-         case ')':
++    bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name);
-             append(buf, ")", buflen);
-             break;
+     object_property_add(cpu_obj, multi_cfg->name, "bool",
-+        case 'b':
+                         cpu_get_multi_ext_cfg,
-+            snprintf(tmp, sizeof(tmp), "%d", dec->bs);
+                         cpu_set_multi_ext_cfg,
-+            append(buf, tmp, buflen);
+                         NULL, (void *)multi_cfg);
-+            break;
-+        case 'n':
+-    if (!generic_cpu) {
-+            snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
++    if (!generic_cpu || deprecated_ext) {
-+            append(buf, tmp, buflen);
+         return;
-+            break;
+     }
-         case '0':
-             append(buf, rv_ireg_name_sym[dec->rd], buflen);
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
-             break;
+     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
      riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
 +    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
 +
      for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
          qdev_property_add_static(DEVICE(obj), prop);
      }
 --
-.35.1
+.41.0

-[PULL 25/25] hw/riscv: Enable TPM backends
+[PULL 54/54] target/riscv: Fix vfwmaccbf16.vf
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Max Chou <max.chou@sifive.com>
-Imply the TPM sysbus devices. This allows users to add TPM devices to
+The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
-the RISC-V virt board.
+replaced by fwmaccbf16.
-This was tested by first creating an emulated TPM device:
+Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension")
+Signed-off-by: Max Chou <max.chou@sifive.com>
-    swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-        --ctrl type=unixio,path=swtpm-sock
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20231005095734.567575-1-max.chou@sifive.com>
 Then launching QEMU with:
     -chardev socket,id=chrtpm,path=swtpm-sock \
     -tpmdev emulator,id=tpm0,chardev=chrtpm \
     -device tpm-tis-device,tpmdev=tpm0
 The TPM device can be seen in the memory tree and the generated device
 tree.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- docs/system/riscv/virt.rst | 20 ++++++++++++++++++++
+ target/riscv/vector_helper.c | 2 +-
- hw/riscv/virt.c            |  4 ++++
+file changed, 1 insertion(+), 1 deletion(-)
  hw/riscv/Kconfig           |  1 +
 files changed, 25 insertions(+)
-diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
+diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/riscv/virt.rst
+--- a/target/riscv/vector_helper.c
-+++ b/docs/system/riscv/virt.rst
++++ b/target/riscv/vector_helper.c
-@@ -XXX,XX +XXX,XX @@ The minimal QEMU commands to run U-Boot SPL are:
+@@ -XXX,XX +XXX,XX @@ static uint32_t fwmaccbf16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
- To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
- riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
+ RVVCALL(OPFVV3, vfwmaccbf16_vv, WOP_UUU_H, H4, H2, H2, fwmaccbf16)
- ``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.
+ GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
-+
+-RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16)
-+Enabling TPM
++RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmaccbf16)
-+------------
+ GEN_VEXT_VF(vfwmaccbf16_vf, 4)
-+
-+A TPM device can be connected to the virt board by following the steps below.
+ static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 +
 +First launch the TPM emulator
 +
 +    swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
 +        --ctrl type=unixio,path=swtpm-sock
 +
 +Then launch QEMU with:
 +
 +    ...
 +    -chardev socket,id=chrtpm,path=swtpm-sock \
 +    -tpmdev emulator,id=tpm0,chardev=chrtpm \
 +    -device tpm-tis-device,tpmdev=tpm0
 +
 +The TPM device can be seen in the memory tree and the generated device
 +tree and should be accessible from the guest software.
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/device_tree.h"
  #include "sysemu/sysemu.h"
  #include "sysemu/kvm.h"
 +#include "sysemu/tpm.h"
  #include "hw/pci/pci.h"
  #include "hw/pci-host/gpex.h"
  #include "hw/display/ramfb.h"
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
      hc->plug = virt_machine_device_plug_cb;
      machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 +#ifdef CONFIG_TPM
 +    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
 +#endif
      object_class_property_add_bool(oc, "aclint", virt_get_aclint,
                                     virt_set_aclint);
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      imply PCI_DEVICES
      imply VIRTIO_VGA
      imply TEST_DEVICES
 +    imply TPM_TIS_SYSBUS
      select RISCV_NUMA
      select GOLDFISH_RTC
      select MSI_NONBROKEN
 --
-.35.1
+.41.0

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:

Merge tag 'pull-target-arm-20220428' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28 08:34:17 -0700)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220429

for you to fetch changes up to 325b7c4e7582c229d28c47123c3b986ed948eb84:

hw/riscv: Enable TPM backends (2022-04-29 10:48:48 +1000)

----------------------------------------------------------------
Second RISC-V PR for QEMU 7.1

* Improve device tree generation
 * Support configuarable marchid, mvendorid, mipid CSR values
 * Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions
 * Fix incorrect PTE merge in walk_pte
 * Add TPM support to the virt board

----------------------------------------------------------------
Alistair Francis (6):
      hw/riscv: virt: Add a machine done notifier
      hw/core: Move the ARM sysbus-fdt to core
      hw/riscv: virt: Create a platform bus
      hw/riscv: virt: Add support for generating platform FDT entries
      hw/riscv: virt: Add device plug support
      hw/riscv: Enable TPM backends

Bin Meng (2):
      hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
      hw/riscv: Don't add empty bootargs to device tree

Frank Chang (1):
      target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

Ralf Ramsauer (1):
      target/riscv: Fix incorrect PTE merge in walk_pte

Weiwei Li (15):
      target/riscv: rvk: add cfg properties for zbk* and zk*
      target/riscv: rvk: add support for zbkb extension
      target/riscv: rvk: add support for zbkc extension
      target/riscv: rvk: add support for zbkx extension
      crypto: move sm4_sbox from target/arm
      target/riscv: rvk: add support for zknd/zkne extension in RV32
      target/riscv: rvk: add support for zkne/zknd extension in RV64
      target/riscv: rvk: add support for sha256 related instructions in zknh extension
      target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
      target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
      target/riscv: rvk: add support for zksed/zksh extension
      target/riscv: rvk: add CSR support for Zkr
      disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
      target/riscv: rvk: expose zbk* and zk* properties
      target/riscv: add scalar crypto related extenstion strings to isa_string

docs/system/riscv/virt.rst              |  20 ++
 include/crypto/sm4.h                    |   6 +
 include/hw/{arm => core}/sysbus-fdt.h   |   0
 include/hw/riscv/virt.h                 |   8 +-
 target/riscv/cpu.h                      |  17 ++
 target/riscv/cpu_bits.h                 |   9 +
 target/riscv/helper.h                   |  22 ++
 target/riscv/pmp.h                      |   8 +-
 target/riscv/insn32.decode              |  97 ++++++--
 crypto/sm4.c                            |  49 ++++
 disas/riscv.c                           | 173 +++++++++++++-
 hw/arm/virt.c                           |   2 +-
 hw/arm/xlnx-versal-virt.c               |   1 -
 hw/{arm => core}/sysbus-fdt.c           |   2 +-
 hw/riscv/microchip_pfsoc.c              |   2 +-
 hw/riscv/sifive_u.c                     |   2 +-
 hw/riscv/spike.c                        |   7 +-
 hw/riscv/virt.c                         | 319 +++++++++++++++++---------
 target/arm/crypto_helper.c              |  36 +--
 target/riscv/bitmanip_helper.c          |  80 +++++++
 target/riscv/cpu.c                      |  58 +++++
 target/riscv/crypto_helper.c            | 302 ++++++++++++++++++++++++
 target/riscv/csr.c                      | 118 +++++++++-
 target/riscv/monitor.c                  |  11 +-
 target/riscv/op_helper.c                |   9 +
 target/riscv/translate.c                |   8 +
 target/riscv/insn_trans/trans_rvb.c.inc | 116 ++++++++--
 target/riscv/insn_trans/trans_rvk.c.inc | 391 ++++++++++++++++++++++++++++++++
 crypto/meson.build                      |   1 +
 hw/arm/meson.build                      |   1 -
 hw/core/meson.build                     |   1 +
 hw/riscv/Kconfig                        |   2 +
 target/riscv/meson.build                |   3 +-
 33 files changed, 1682 insertions(+), 199 deletions(-)
 create mode 100644 include/crypto/sm4.h
 rename include/hw/{arm => core}/sysbus-fdt.h (100%)
 create mode 100644 crypto/sm4.c
 rename hw/{arm => core}/sysbus-fdt.c (99%)
 create mode 100644 target/riscv/crypto_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc

From: Bin Meng <bin.meng@windriver.com>

At present the adding '/chosen/stdout-path' property in device tree
is determined by whether a kernel command line is provided, which is
wrong. It should be added unconditionally.

Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421055629.1177285-1-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/spike.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
 
     riscv_socket_fdt_write_distance_matrix(mc, fdt);
 
+    qemu_fdt_add_subnode(fdt, "/chosen");
+    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
+
     if (cmdline) {
-        qemu_fdt_add_subnode(fdt, "/chosen");
         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-        qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
     }
 }
 
-- 
2.35.1

From: Bin Meng <bin.meng@windriver.com>

Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
tried to avoid adding *NULL* bootargs to device tree, but unfortunately
the changes were entirely useless, due to MachineState::kernel_cmdline
can't be NULL at all as the default value is given as an empty string.
(see hw/core/machine.c::machine_initfn()).

Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise
a segfault had already been observed by dereferencing the NULL pointer.
It should be worded as *empty" bootargs.

Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421055629.1177285-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/microchip_pfsoc.c | 2 +-
 hw/riscv/sifive_u.c        | 2 +-
 hw/riscv/spike.c           | 2 +-
 hw/riscv/virt.c            | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                                   "linux,initrd-end", end);
         }
 
-        if (machine->kernel_cmdline) {
+        if (machine->kernel_cmdline && *machine->kernel_cmdline) {
             qemu_fdt_setprop_string(machine->fdt, "/chosen",
                                     "bootargs", machine->kernel_cmdline);
         }
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     g_free(nodename);
 
 update_bootargs:
-    if (cmdline) {
+    if (cmdline && *cmdline) {
         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
     }
 }
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
     qemu_fdt_add_subnode(fdt, "/chosen");
     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
 
-    if (cmdline) {
+    if (cmdline && *cmdline) {
         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
     }
 }
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     create_fdt_flash(s, memmap);
 
 update_bootargs:
-    if (cmdline) {
+    if (cmdline && *cmdline) {
         qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
     }
 }
-- 
2.35.1

From: Frank Chang <frank.chang@sifive.com>

Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.

The default values of marchid and mipid are built with QEMU's version
numbers.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220422040436.2233-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  4 ++++
 target/riscv/cpu.c |  9 +++++++++
 target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
 3 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zve32f;
     bool ext_zve64f;
 
+    uint32_t mvendorid;
+    uint64_t marchid;
+    uint64_t mipid;
+
     /* Vendor-specific custom extensions */
     bool ext_XVentanaCondOps;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 
 /* RISC-V CPU definitions */
 
+#define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
+                             (QEMU_VERSION_MINOR << 8)  | \
+                             (QEMU_VERSION_MICRO))
+#define RISCV_CPU_MIPID     RISCV_CPU_MARCHID
+
 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
 
 struct isa_ext_data {
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
+    DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+    DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+    DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
     DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
+                                     target_ulong *val)
+{
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    *val = cpu->cfg.mvendorid;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_marchid(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
+{
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    *val = cpu->cfg.marchid;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipid(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
+{
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    *val = cpu->cfg.mipid;
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
 
     /* Machine Information Registers */
-    [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
-    [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
-    [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
-    [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
+    [CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
+    [CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
+    [CSR_MIMPID]    = { "mimpid",    any,   read_mipid     },
+    [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
 
     [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
                                         .min_priv_ver = PRIV_VERSION_1_12_0 },
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 13 +++++++++++++
 target/riscv/cpu.c | 23 +++++++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zba;
     bool ext_zbb;
     bool ext_zbc;
+    bool ext_zbkb;
+    bool ext_zbkc;
+    bool ext_zbkx;
     bool ext_zbs;
+    bool ext_zk;
+    bool ext_zkn;
+    bool ext_zknd;
+    bool ext_zkne;
+    bool ext_zknh;
+    bool ext_zkr;
+    bool ext_zks;
+    bool ext_zksed;
+    bool ext_zksh;
+    bool ext_zkt;
     bool ext_counters;
     bool ext_ifencei;
     bool ext_icsr;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             cpu->cfg.ext_zfinx = true;
         }
 
+        if (cpu->cfg.ext_zk) {
+            cpu->cfg.ext_zkn = true;
+            cpu->cfg.ext_zkr = true;
+            cpu->cfg.ext_zkt = true;
+        }
+
+        if (cpu->cfg.ext_zkn) {
+            cpu->cfg.ext_zbkb = true;
+            cpu->cfg.ext_zbkc = true;
+            cpu->cfg.ext_zbkx = true;
+            cpu->cfg.ext_zkne = true;
+            cpu->cfg.ext_zknd = true;
+            cpu->cfg.ext_zknh = true;
+        }
+
+        if (cpu->cfg.ext_zks) {
+            cpu->cfg.ext_zbkb = true;
+            cpu->cfg.ext_zbkc = true;
+            cpu->cfg.ext_zbkx = true;
+            cpu->cfg.ext_zksed = true;
+            cpu->cfg.ext_zksh = true;
+        }
+
         /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_i) {
             ext |= RVI;
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- reuse partial instructions of zbb extension, update extension check for them
 - add brev8, pack, packh, packw, unzip, zip instructions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  3 +
 target/riscv/insn32.decode              | 45 +++++++-----
 target/riscv/bitmanip_helper.c          | 53 ++++++++++++++
 target/riscv/translate.c                |  7 ++
 target/riscv/insn_trans/trans_rvb.c.inc | 94 +++++++++++++++++++++----
 5 files changed, 174 insertions(+), 28 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 /* Bitmanip */
 DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
 
 /* Floating Point - Half Precision */
 DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 slli_uw    00001 ............ 001 ..... 0011011 @sh
 
-# *** RV32 Zbb Standard Extension ***
+# *** RV32 Zbb/Zbkb Standard Extension ***
 andn       0100000 .......... 111 ..... 0110011 @r
+rol        0110000 .......... 001 ..... 0110011 @r
+ror        0110000 .......... 101 ..... 0110011 @r
+rori       01100 ............ 101 ..... 0010011 @sh
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+{
+  zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
+  pack       0000100 ..... ..... 100 ..... 0110011 @r
+}
+xnor       0100000 .......... 100 ..... 0110011 @r
+# *** RV32 extra Zbb Standard Extension ***
 clz        011000 000000 ..... 001 ..... 0010011 @r2
 cpop       011000 000010 ..... 001 ..... 0010011 @r2
 ctz        011000 000001 ..... 001 ..... 0010011 @r2
@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
 minu       0000101 .......... 101 ..... 0110011 @r
 orc_b      001010 000111 ..... 101 ..... 0010011 @r2
 orn        0100000 .......... 110 ..... 0110011 @r
-# The encoding for rev8 differs between RV32 and RV64.
-# rev8_32 denotes the RV32 variant.
-rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
-rol        0110000 .......... 001 ..... 0110011 @r
-ror        0110000 .......... 101 ..... 0110011 @r
-rori       01100 ............ 101 ..... 0010011 @sh
 sext_b     011000 000100 ..... 001 ..... 0010011 @r2
 sext_h     011000 000101 ..... 001 ..... 0010011 @r2
-xnor       0100000 .......... 100 ..... 0110011 @r
-# The encoding for zext.h differs between RV32 and RV64.
-# zext_h_32 denotes the RV32 variant.
-zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
+# *** RV32 extra Zbkb Standard Extension ***
+brev8      0110100 00111 ..... 101 ..... 0010011 @r2  #grevi
+packh      0000100  .......... 111 ..... 0110011 @r
+unzip      0000100 01111 ..... 101 ..... 0010011 @r2  #unshfl
+zip        0000100 01111 ..... 001 ..... 0010011 @r2  #shfl
 
-# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
-clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
-cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
+# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
 # The encoding for rev8 differs between RV32 and RV64.
 # When executing on RV64, the encoding used in RV32 is an illegal
 # instruction, so we use different handler functions to differentiate.
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
 # The encoding for zext.h differs between RV32 and RV64.
 # When executing on RV64, the encoding used in RV32 is an illegal
 # instruction, so we use different handler functions to differentiate.
-zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
+{
+  zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
+  packw      0000100 ..... ..... 100 ..... 0111011 @r
+}
+# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
+clzw       0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 
 # *** RV32 Zbc Standard Extension ***
 clmul      0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
 
     return result;
 }
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+    return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+target_ulong HELPER(brev8)(target_ulong rs1)
+{
+    target_ulong x = rs1;
+
+    x = do_swap(x, 0x5555555555555555ull, 1);
+    x = do_swap(x, 0x3333333333333333ull, 2);
+    x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
+    return x;
+}
+
+static const uint64_t shuf_masks[] = {
+    dup_const(MO_8, 0x44),
+    dup_const(MO_8, 0x30),
+    dup_const(MO_16, 0x0f00),
+    dup_const(MO_32, 0xff0000)
+};
+
+static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
+                                         uint64_t maskR, int shift)
+{
+    target_ulong x = src & ~(maskL | maskR);
+
+    x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
+    return x;
+}
+
+target_ulong HELPER(unzip)(target_ulong rs1)
+{
+    target_ulong x = rs1;
+
+    x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+    x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+    x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+    x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+    return x;
+}
+
+target_ulong HELPER(zip)(target_ulong rs1)
+{
+    target_ulong x = rs1;
+
+    x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+    x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+    x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+    x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+    return x;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
     }                                  \
 } while (0)
 
+#define REQUIRE_EITHER_EXT(ctx, A, B) do {       \
+    if (!ctx->cfg_ptr->ext_##A &&      \
+        !ctx->cfg_ptr->ext_##B) {      \
+        return false;                            \
+    }                                            \
+} while (0)
+
 static int ex_rvc_register(DisasContext *ctx, int reg)
 {
     return 8 + reg;
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
 /*
- * RISC-V translation routines for the Zb[abcs] Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
  *
  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+#define REQUIRE_ZBKB(ctx) do {                   \
+    if (!ctx->cfg_ptr->ext_zbkb) {               \
+        return false;                            \
+    }                                            \
+} while (0)
+
 static void gen_clz(TCGv ret, TCGv arg1)
 {
     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -XXX,XX +XXX,XX @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
 
 static bool trans_andn(DisasContext *ctx, arg_andn *a)
 {
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     return gen_logic(ctx, a, tcg_gen_andc_tl);
 }
 
 static bool trans_orn(DisasContext *ctx, arg_orn *a)
 {
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     return gen_logic(ctx, a, tcg_gen_orc_tl);
 }
 
 static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
 {
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     return gen_logic(ctx, a, tcg_gen_eqv_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
 
 static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
 
 static bool trans_rori(DisasContext *ctx, arg_rori *a)
 {
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
                                    tcg_gen_rotri_tl, gen_roriw, NULL);
 }
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
 
 static bool trans_rol(DisasContext *ctx, arg_rol *a)
 {
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_rev8_32(TCGv ret, TCGv src1)
 static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
 {
     REQUIRE_32BIT(ctx);
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
 }
 
 static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     ctx->ol = MXL_RV32;
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
 static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_ZBB(ctx);
+    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
     ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
     REQUIRE_ZBC(ctx);
     return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
 }
+
+static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
+{
+    tcg_gen_deposit_tl(ret, src1, src2,
+                       TARGET_LONG_BITS / 2,
+                       TARGET_LONG_BITS / 2);
+}
+
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
+{
+    TCGv t = tcg_temp_new();
+
+    tcg_gen_ext8u_tl(t, src2);
+    tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
+    tcg_temp_free(t);
+}
+
+static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
+{
+    TCGv t = tcg_temp_new();
+
+    tcg_gen_ext16s_tl(t, src2);
+    tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
+    tcg_temp_free(t);
+}
+
+static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
+{
+    REQUIRE_ZBKB(ctx);
+    return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
+}
+
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+    REQUIRE_ZBKB(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+    REQUIRE_ZBKB(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
+}
+
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_ZBKB(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
+}
+
+static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZBKB(ctx);
+    return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
+}
+
+static bool trans_zip(DisasContext *ctx, arg_zip *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZBKB(ctx);
+    return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
+}
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- reuse partial instructions of zbc extension, update extension check for them

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 3 ++-
 target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add xperm4 and xperm8 instructions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  2 ++
 target/riscv/insn32.decode              |  4 ++++
 target/riscv/bitmanip_helper.c          | 27 +++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 18 +++++++++++++++++
 4 files changed, 51 insertions(+)

From: Weiwei Li <liweiwei@iscas.ac.cn>

- share it between target/arm and target/riscv

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/crypto/sm4.h       |  6 +++++
 crypto/sm4.c               | 49 ++++++++++++++++++++++++++++++++++++++
 target/arm/crypto_helper.c | 36 +---------------------------
 crypto/meson.build         |  1 +
 4 files changed, 57 insertions(+), 35 deletions(-)
 create mode 100644 include/crypto/sm4.h
 create mode 100644 crypto/sm4.c

diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/crypto/sm4.h
@@ -XXX,XX +XXX,XX @@
+#ifndef QEMU_SM4_H
+#define QEMU_SM4_H
+
+extern const uint8_t sm4_sbox[256];
+
+#endif
diff --git a/crypto/sm4.c b/crypto/sm4.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/crypto/sm4.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU crypto sm4 support
+ *
+ * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "crypto/sm4.h"
+
+uint8_t const sm4_sbox[] = {
+    0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
+    0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+    0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
+    0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+    0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+    0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+    0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
+    0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+    0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
+    0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+    0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
+    0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+    0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
+    0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+    0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
+    0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+    0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
+    0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+    0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
+    0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+    0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
+    0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+    0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
+    0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+    0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
+    0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+    0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
+    0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+    0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
+    0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+    0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
+    0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
+};
+
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "crypto/aes.h"
+#include "crypto/sm4.h"
 #include "vec_internal.h"
 
 union CRYPTO_STATE {
@@ -XXX,XX +XXX,XX @@ DO_SM3TT(crypto_sm3tt2b, 3)
 
 #undef DO_SM3TT
 
-static uint8_t const sm4_sbox[] = {
-    0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
-    0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
-    0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
-    0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
-    0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
-    0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
-    0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
-    0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
-    0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
-    0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
-    0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
-    0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
-    0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
-    0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
-    0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
-    0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
-    0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
-    0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
-    0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
-    0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
-    0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
-    0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
-    0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
-    0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
-    0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
-    0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
-    0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
-    0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
-    0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
-    0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
-    0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
-    0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
-};
-
 static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
 {
     union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
diff --git a/crypto/meson.build b/crypto/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/crypto/meson.build
+++ b/crypto/meson.build
@@ -XXX,XX +XXX,XX @@ if have_afalg
 endif
 crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
 
+util_ss.add(files('sm4.c'))
 util_ss.add(files('aes.c'))
 util_ss.add(files('init.c'))
 if gnutls.found()
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions

Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |   6 ++
 target/riscv/insn32.decode              |  11 +++
 target/riscv/crypto_helper.c            | 105 ++++++++++++++++++++++++
 target/riscv/translate.c                |   1 +
 target/riscv/insn_trans/trans_rvk.c.inc |  71 ++++++++++++++++
 target/riscv/meson.build                |   3 +-
 6 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/crypto_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(divu_i128, tl, env, tl, tl, tl, tl)
 DEF_HELPER_5(divs_i128, tl, env, tl, tl, tl, tl)
 DEF_HELPER_5(remu_i128, tl, env, tl, tl, tl, tl)
 DEF_HELPER_5(rems_i128, tl, env, tl, tl, tl, tl)
+
+/* Crypto functions */
+DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 %imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
 %imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
 %imm_u    12:s20                 !function=ex_shift_12
+%imm_bs   30:2                   !function=ex_shift_3
 
 # Argument sets:
 &empty
@@ -XXX,XX +XXX,XX @@
 &rmr       vm rd rs2
 &r2nfvm    vm rd rs1 nf
 &rnfvm     vm rd rs1 rs2 nf
+&k_aes     shamt rs2 rs1 rd
 
 # Formats 32:
 @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
@@ -XXX,XX +XXX,XX @@
 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
 
+@k_aes   .. ..... ..... .....  ... ..... ....... &k_aes  shamt=%imm_bs   %rs2 %rs1 %rd
+
 # Formats 64:
 @sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
 
@@ -XXX,XX +XXX,XX @@ sfence_w_inval    0001100 00000 00000 000 00000 1110011
 sfence_inval_ir   0001100 00001 00000 000 00000 1110011
 hinval_vvma       0010011 ..... ..... 000 00000 1110011 @hfence_vvma
 hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
+
+# *** RV32 Zknd Standard Extension ***
+aes32dsmi   .. 10111 ..... ..... 000 ..... 0110011 @k_aes
+aes32dsi    .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV32 Zkne Standard Extension ***
+aes32esmi   .. 10011 ..... ..... 000 ..... 0110011 @k_aes
+aes32esi    .. 10001 ..... ..... 000 ..... 0110011 @k_aes
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/crypto_helper.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V Crypto Emulation Helpers for QEMU.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "crypto/aes.h"
+#include "crypto/sm4.h"
+
+#define AES_XTIME(a) \
+    ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
+
+#define AES_GFMUL(a, b) (( \
+    (((b) & 0x1) ? (a) : 0) ^ \
+    (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
+    (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
+    (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
+
+static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
+{
+    uint32_t u;
+
+    if (fwd) {
+        u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
+            (AES_GFMUL(x, 2) << 0);
+    } else {
+        u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
+            (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
+    }
+    return u;
+}
+
+#define sext32_xlen(x) (target_ulong)(int32_t)(x)
+
+static inline target_ulong aes32_operation(target_ulong shamt,
+                                           target_ulong rs1, target_ulong rs2,
+                                           bool enc, bool mix)
+{
+    uint8_t si = rs2 >> shamt;
+    uint8_t so;
+    uint32_t mixed;
+    target_ulong res;
+
+    if (enc) {
+        so = AES_sbox[si];
+        if (mix) {
+            mixed = aes_mixcolumn_byte(so, true);
+        } else {
+            mixed = so;
+        }
+    } else {
+        so = AES_isbox[si];
+        if (mix) {
+            mixed = aes_mixcolumn_byte(so, false);
+        } else {
+            mixed = so;
+        }
+    }
+    mixed = rol32(mixed, shamt);
+    res = rs1 ^ mixed;
+
+    return sext32_xlen(res);
+}
+
+target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2,
+                               target_ulong shamt)
+{
+    return aes32_operation(shamt, rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2,
+                              target_ulong shamt)
+{
+    return aes32_operation(shamt, rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2,
+                               target_ulong shamt)
+{
+    return aes32_operation(shamt, rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
+                              target_ulong shamt)
+{
+    return aes32_operation(shamt, rs1, rs2, false, false);
+}
+#undef sext32_xlen
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 #include "insn_trans/trans_rvv.c.inc"
 #include "insn_trans/trans_rvb.c.inc"
 #include "insn_trans/trans_rvzfh.c.inc"
+#include "insn_trans/trans_rvk.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
 #include "insn_trans/trans_svinval.c.inc"
 #include "insn_trans/trans_xventanacondops.c.inc"
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V translation routines for the Zk[nd,ne,nh,sed,sh] Standard Extension.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZKND(ctx) do {                  \
+    if (!ctx->cfg_ptr->ext_zknd) {              \
+        return false;                           \
+    }                                           \
+} while (0)
+
+#define REQUIRE_ZKNE(ctx) do {                  \
+    if (!ctx->cfg_ptr->ext_zkne) {              \
+        return false;                           \
+    }                                           \
+} while (0)
+
+static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
+                          void (*func)(TCGv, TCGv, TCGv, TCGv))
+{
+    TCGv shamt = tcg_constant_tl(a->shamt);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    func(dest, src1, src2, shamt);
+    gen_set_gpr(ctx, a->rd, dest);
+    return true;
+}
+
+static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKNE(ctx);
+    return gen_aes32_sm4(ctx, a, gen_helper_aes32esmi);
+}
+
+static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKNE(ctx);
+    return gen_aes32_sm4(ctx, a, gen_helper_aes32esi);
+}
+
+static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKND(ctx);
+    return gen_aes32_sm4(ctx, a, gen_helper_aes32dsmi);
+}
+
+static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKND(ctx);
+    return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'vector_helper.c',
   'bitmanip_helper.c',
   'translate.c',
-  'm128_helper.c'
+  'm128_helper.c',
+  'crypto_helper.c'
 ))
 riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
 
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions

Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |   8 ++
 target/riscv/insn32.decode              |  12 ++
 target/riscv/crypto_helper.c            | 169 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvk.c.inc |  54 ++++++++
 4 files changed, 243 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
 DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
 DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
 DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+
+DEF_HELPER_FLAGS_2(aes64esm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64es, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ds, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 %imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
 %imm_u    12:s20                 !function=ex_shift_12
 %imm_bs   30:2                   !function=ex_shift_3
+%imm_rnum 20:4
 
 # Argument sets:
 &empty
@@ -XXX,XX +XXX,XX @@
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
 
 @k_aes   .. ..... ..... .....  ... ..... ....... &k_aes  shamt=%imm_bs   %rs2 %rs1 %rd
+@i_aes   .. ..... ..... .....  ... ..... ....... &i      imm=%imm_rnum        %rs1 %rd
 
 # Formats 64:
 @sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
@@ -XXX,XX +XXX,XX @@ hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
 # *** RV32 Zknd Standard Extension ***
 aes32dsmi   .. 10111 ..... ..... 000 ..... 0110011 @k_aes
 aes32dsi    .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zknd Standard Extension ***
+aes64dsm    00 11111 ..... ..... 000 ..... 0110011 @r
+aes64ds     00 11101 ..... ..... 000 ..... 0110011 @r
+aes64im     00 11000 00000 ..... 001 ..... 0010011 @r2
 # *** RV32 Zkne Standard Extension ***
 aes32esmi   .. 10011 ..... ..... 000 ..... 0110011 @k_aes
 aes32esi    .. 10001 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zkne Standard Extension ***
+aes64es     00 11001 ..... ..... 000 ..... 0110011 @r
+aes64esm    00 11011 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zkne/zknd Standard Extension ***
+aes64ks2    01 11111 ..... ..... 000 ..... 0110011 @r
+aes64ks1i   00 11000 1.... ..... 001 ..... 0010011 @i_aes
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
 {
     return aes32_operation(shamt, rs1, rs2, false, false);
 }
+
+#define BY(X, I) ((X >> (8 * I)) & 0xFF)
+
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
+    (((RS1 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+    (((RS2 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+    (((RS2 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+    (((RS1 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
+    (((RS2 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+    (((RS1 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+    (((RS1 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+    (((RS2 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
+    BY(COL, B3) ^ BY(COL, B2) ^ AES_GFMUL(BY(COL, B1), 3) ^ \
+    AES_GFMUL(BY(COL, B0), 2))
+
+#define AES_MIXCOLUMN(COL) ( \
+    AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+    AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+    AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | AES_MIXBYTE(COL, 0, 1, 2, 3) << 0)
+
+#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
+    AES_GFMUL(BY(COL, B3), 0x9) ^ AES_GFMUL(BY(COL, B2), 0xd) ^ \
+    AES_GFMUL(BY(COL, B1), 0xb) ^ AES_GFMUL(BY(COL, B0), 0xe))
+
+#define AES_INVMIXCOLUMN(COL) ( \
+    AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+    AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+    AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
+    AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0)
+
+static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
+                                           bool enc, bool mix)
+{
+    uint64_t RS1 = rs1;
+    uint64_t RS2 = rs2;
+    uint64_t result;
+    uint64_t temp;
+    uint32_t col_0;
+    uint32_t col_1;
+
+    if (enc) {
+        temp = AES_SHIFROWS_LO(RS1, RS2);
+        temp = (((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
+                ((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+                ((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+                ((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+                ((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
+                ((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
+                ((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
+                ((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56));
+        if (mix) {
+            col_0 = temp & 0xFFFFFFFF;
+            col_1 = temp >> 32;
+
+            col_0 = AES_MIXCOLUMN(col_0);
+            col_1 = AES_MIXCOLUMN(col_1);
+
+            result = ((uint64_t)col_1 << 32) | col_0;
+        } else {
+            result = temp;
+        }
+    } else {
+        temp = AES_INVSHIFROWS_LO(RS1, RS2);
+        temp = (((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
+                ((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
+                ((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
+                ((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
+                ((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
+                ((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
+                ((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
+                ((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56));
+        if (mix) {
+            col_0 = temp & 0xFFFFFFFF;
+            col_1 = temp >> 32;
+
+            col_0 = AES_INVMIXCOLUMN(col_0);
+            col_1 = AES_INVMIXCOLUMN(col_1);
+
+            result = ((uint64_t)col_1 << 32) | col_0;
+        } else {
+            result = temp;
+        }
+    }
+
+    return result;
+}
+
+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
+{
+    return aes64_operation(rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
+{
+    return aes64_operation(rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
+{
+    return aes64_operation(rs1, rs2, false, false);
+}
+
+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
+{
+    return aes64_operation(rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
+{
+    uint64_t RS1 = rs1;
+    uint64_t RS2 = rs2;
+    uint32_t rs1_hi = RS1 >> 32;
+    uint32_t rs2_lo = RS2;
+    uint32_t rs2_hi = RS2 >> 32;
+
+    uint32_t r_lo = (rs1_hi ^ rs2_lo);
+    uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi);
+    target_ulong result = ((uint64_t)r_hi << 32) | r_lo;
+
+    return result;
+}
+
+target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
+{
+    uint64_t RS1 = rs1;
+    static const uint8_t round_consts[10] = {
+        0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
+    };
+
+    uint8_t enc_rnum = rnum;
+    uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
+    uint8_t rcon_ = 0;
+    target_ulong result;
+
+    if (enc_rnum != 0xA) {
+        temp = ror32(temp, 8); /* Rotate right by 8 */
+        rcon_ = round_consts[enc_rnum];
+    }
+
+    temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+           ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+           ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+           ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
+
+    temp ^= rcon_;
+
+    result = ((uint64_t)temp << 32) | temp;
+
+    return result;
+}
+
+target_ulong HELPER(aes64im)(target_ulong rs1)
+{
+    uint64_t RS1 = rs1;
+    uint32_t col_0 = RS1 & 0xFFFFFFFF;
+    uint32_t col_1 = RS1 >> 32;
+    target_ulong result;
+
+    col_0 = AES_INVMIXCOLUMN(col_0);
+    col_1 = AES_INVMIXCOLUMN(col_1);
+
+    result = ((uint64_t)col_1 << 32) | col_0;
+
+    return result;
+}
 #undef sext32_xlen
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
     REQUIRE_ZKND(ctx);
     return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
 }
+
+static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_ZKNE(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64es, NULL);
+}
+
+static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_ZKNE(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64esm, NULL);
+}
+
+static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_ZKND(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ds, NULL);
+}
+
+static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_ZKND(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64dsm, NULL);
+}
+
+static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ks2, NULL);
+}
+
+static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+    if (a->imm > 0xA) {
+        return false;
+    }
+
+    return gen_arith_imm_tl(ctx, a, EXT_NONE, gen_helper_aes64ks1i, NULL);
+}
+
+static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_ZKND(ctx);
+    return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
+}
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ aes64esm    00 11011 ..... ..... 000 ..... 0110011 @r
 # *** RV64 Zkne/zknd Standard Extension ***
 aes64ks2    01 11111 ..... ..... 000 ..... 0110011 @r
 aes64ks1i   00 11000 1.... ..... 001 ..... 0010011 @i_aes
+# *** RV32 Zknh Standard Extension ***
+sha256sig0  00 01000 00010 ..... 001 ..... 0010011 @r2
+sha256sig1  00 01000 00011 ..... 001 ..... 0010011 @r2
+sha256sum0  00 01000 00000 ..... 001 ..... 0010011 @r2
+sha256sum1  00 01000 00001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -XXX,XX +XXX,XX @@
     }                                           \
 } while (0)
 
+#define REQUIRE_ZKNH(ctx) do {                  \
+    if (!ctx->cfg_ptr->ext_zknh) {              \
+        return false;                           \
+    }                                           \
+} while (0)
+
 static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
                           void (*func)(TCGv, TCGv, TCGv, TCGv))
 {
@@ -XXX,XX +XXX,XX @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
     REQUIRE_ZKND(ctx);
     return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
 }
+
+static bool gen_sha256(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+                       void (*func)(TCGv_i32, TCGv_i32, int32_t),
+                       int32_t num1, int32_t num2, int32_t num3)
+{
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+    TCGv_i32 t0 = tcg_temp_new_i32();
+    TCGv_i32 t1 = tcg_temp_new_i32();
+    TCGv_i32 t2 = tcg_temp_new_i32();
+
+    tcg_gen_trunc_tl_i32(t0, src1);
+    tcg_gen_rotri_i32(t1, t0, num1);
+    tcg_gen_rotri_i32(t2, t0, num2);
+    tcg_gen_xor_i32(t1, t1, t2);
+    func(t2, t0, num3);
+    tcg_gen_xor_i32(t1, t1, t2);
+    tcg_gen_ext_i32_tl(dest, t1);
+
+    gen_set_gpr(ctx, a->rd, dest);
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+    return true;
+}
+
+static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
+{
+    REQUIRE_ZKNH(ctx);
+    return gen_sha256(ctx, a, EXT_NONE, tcg_gen_shri_i32, 7, 18, 3);
+}
+
+static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a)
+{
+    REQUIRE_ZKNH(ctx);
+    return gen_sha256(ctx, a, EXT_NONE, tcg_gen_shri_i32, 17, 19, 10);
+}
+
+static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a)
+{
+    REQUIRE_ZKNH(ctx);
+    return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 2, 13, 22);
+}
+
+static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
+{
+    REQUIRE_ZKNH(ctx);
+    return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 6, 11, 25);
+}
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ sha256sig0  00 01000 00010 ..... 001 ..... 0010011 @r2
 sha256sig1  00 01000 00011 ..... 001 ..... 0010011 @r2
 sha256sum0  00 01000 00000 ..... 001 ..... 0010011 @r2
 sha256sum1  00 01000 00001 ..... 001 ..... 0010011 @r2
+sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
+sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
+sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
+sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
+sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
+sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
     REQUIRE_ZKNH(ctx);
     return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 6, 11, 25);
 }
+
+static bool gen_sha512_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                            void (*func1)(TCGv_i64, TCGv_i64, int64_t),
+                            void (*func2)(TCGv_i64, TCGv_i64, int64_t),
+                            int64_t num1, int64_t num2, int64_t num3)
+{
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+    TCGv src2 = get_gpr(ctx, a->rs2, ext);
+    TCGv_i64 t0 = tcg_temp_new_i64();
+    TCGv_i64 t1 = tcg_temp_new_i64();
+    TCGv_i64 t2 = tcg_temp_new_i64();
+
+    tcg_gen_concat_tl_i64(t0, src1, src2);
+    func1(t1, t0, num1);
+    func2(t2, t0, num2);
+    tcg_gen_xor_i64(t1, t1, t2);
+    tcg_gen_rotri_i64(t2, t0, num3);
+    tcg_gen_xor_i64(t1, t1, t2);
+    tcg_gen_trunc_i64_tl(dest, t1);
+
+    gen_set_gpr(ctx, a->rd, dest);
+    tcg_temp_free_i64(t0);
+    tcg_temp_free_i64(t1);
+    tcg_temp_free_i64(t2);
+    return true;
+}
+
+static bool trans_sha512sum0r(DisasContext *ctx, arg_sha512sum0r *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKNH(ctx);
+    return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
+                           tcg_gen_rotli_i64, 25, 30, 28);
+}
+
+static bool trans_sha512sum1r(DisasContext *ctx, arg_sha512sum1r *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKNH(ctx);
+    return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
+                           tcg_gen_rotri_i64, 23, 14, 18);
+}
+
+static bool trans_sha512sig0l(DisasContext *ctx, arg_sha512sig0l *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKNH(ctx);
+    return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotri_i64,
+                           tcg_gen_rotri_i64, 1, 7, 8);
+}
+
+static bool trans_sha512sig1l(DisasContext *ctx, arg_sha512sig1l *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKNH(ctx);
+    return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
+                           tcg_gen_rotri_i64, 3, 6, 19);
+}
+
+static bool gen_sha512h_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                             void (*func)(TCGv_i64, TCGv_i64, int64_t),
+                             int64_t num1, int64_t num2, int64_t num3)
+{
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+    TCGv src2 = get_gpr(ctx, a->rs2, ext);
+    TCGv_i64 t0 = tcg_temp_new_i64();
+    TCGv_i64 t1 = tcg_temp_new_i64();
+    TCGv_i64 t2 = tcg_temp_new_i64();
+
+    tcg_gen_concat_tl_i64(t0, src1, src2);
+    func(t1, t0, num1);
+    tcg_gen_ext32u_i64(t2, t0);
+    tcg_gen_shri_i64(t2, t2, num2);
+    tcg_gen_xor_i64(t1, t1, t2);
+    tcg_gen_rotri_i64(t2, t0, num3);
+    tcg_gen_xor_i64(t1, t1, t2);
+    tcg_gen_trunc_i64_tl(dest, t1);
+
+    gen_set_gpr(ctx, a->rd, dest);
+    tcg_temp_free_i64(t0);
+    tcg_temp_free_i64(t1);
+    tcg_temp_free_i64(t2);
+    return true;
+}
+
+static bool trans_sha512sig0h(DisasContext *ctx, arg_sha512sig0h *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKNH(ctx);
+    return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 1, 7, 8);
+}
+
+static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a)
+{
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZKNH(ctx);
+    return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19);
+}
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add sm3p0, sm3p1, sm4ed and sm4ks instructions

Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  3 ++
 target/riscv/insn32.decode              |  6 +++
 target/riscv/crypto_helper.c            | 28 ++++++++++++
 target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
 4 files changed, 95 insertions(+)

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add SEED CSR which must be accessed with a read-write instruction:
   A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
with uimm=0 will raise an illegal instruction exception.
 - add USEED, SSEED fields for MSECCFG CSR

Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h  |  9 +++++
 target/riscv/pmp.h       |  8 ++--
 target/riscv/csr.c       | 80 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/op_helper.c |  9 +++++
 4 files changed, 103 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define CSR_VSPMMASK        0x2c1
 #define CSR_VSPMBASE        0x2c2
 
+/* Crypto Extension */
+#define CSR_SEED            0x015
+
 /* mstatus CSR bits */
 #define MSTATUS_UIE         0x00000001
 #define MSTATUS_SIE         0x00000002
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
 #define HVICTL_VALID_MASK                  \
     (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
 
+/* seed CSR bits */
+#define SEED_OPST                        (0b11 << 30)
+#define SEED_OPST_BIST                   (0b00 << 30)
+#define SEED_OPST_WAIT                   (0b01 << 30)
+#define SEED_OPST_ES16                   (0b10 << 30)
+#define SEED_OPST_DEAD                   (0b11 << 30)
 #endif
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 } pmp_am_t;
 
 typedef enum {
-    MSECCFG_MML  = 1 << 0,
-    MSECCFG_MMWP = 1 << 1,
-    MSECCFG_RLB  = 1 << 2
+    MSECCFG_MML   = 1 << 0,
+    MSECCFG_MMWP  = 1 << 1,
+    MSECCFG_RLB   = 1 << 2,
+    MSECCFG_USEED = 1 << 8,
+    MSECCFG_SSEED = 1 << 9
 } mseccfg_field_t;
 
 typedef struct {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/main-loop.h"
 #include "exec/exec-all.h"
 #include "sysemu/cpu-timers.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
 
 /* CSR function table public API */
 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
@@ -XXX,XX +XXX,XX @@ static RISCVException debug(CPURISCVState *env, int csrno)
 }
 #endif
 
+static RISCVException seed(CPURISCVState *env, int csrno)
+{
+    RISCVCPU *cpu = env_archcpu(env);
+
+    if (!cpu->cfg.ext_zkr) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+#if !defined(CONFIG_USER_ONLY)
+    /*
+     * With a CSR read-write instruction:
+     * 1) The seed CSR is always available in machine mode as normal.
+     * 2) Attempted access to seed from virtual modes VS and VU always raises
+     * an exception(virtual instruction exception only if mseccfg.sseed=1).
+     * 3) Without the corresponding access control bit set to 1, any attempted
+     * access to seed from U, S or HS modes will raise an illegal instruction
+     * exception.
+     */
+    if (env->priv == PRV_M) {
+        return RISCV_EXCP_NONE;
+    } else if (riscv_cpu_virt_enabled(env)) {
+        if (env->mseccfg & MSECCFG_SSEED) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        } else {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+    } else {
+        if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
+            return RISCV_EXCP_NONE;
+        } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
+            return RISCV_EXCP_NONE;
+        } else {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+    }
+#else
+    return RISCV_EXCP_NONE;
+#endif
+}
+
 /* User Floating-Point CSRs */
 static RISCVException read_fflags(CPURISCVState *env, int csrno,
                                   target_ulong *val)
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 
 #endif
 
+/* Crypto Extension */
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    uint16_t random_v;
+    Error *random_e = NULL;
+    int random_r;
+    target_ulong rval;
+
+    random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
+    if (unlikely(random_r < 0)) {
+        /*
+         * Failed, for unknown reasons in the crypto subsystem.
+         * The best we can do is log the reason and return a
+         * failure indication to the guest.  There is no reason
+         * we know to expect the failure to be transitory, so
+         * indicate DEAD to avoid having the guest spin on WAIT.
+         */
+        qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
+                      __func__, error_get_pretty(random_e));
+        error_free(random_e);
+        rval = SEED_OPST_DEAD;
+    } else {
+        rval = random_v | SEED_OPST_ES16;
+    }
+
+    if (ret_value) {
+        *ret_value = rval;
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
 /*
  * riscv_csrrw - read and/or update control and status register
  *
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_TIME]  = { "time",  ctr,   read_time  },
     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
 
+    /* Crypto Extension */
+    [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed },
+
 #if !defined(CONFIG_USER_ONLY)
     /* Machine Timers and Counters */
     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_raise_exception(CPURISCVState *env, uint32_t exception)
 
 target_ulong helper_csrr(CPURISCVState *env, int csr)
 {
+    /*
+     * The seed CSR must be accessed with a read-write instruction. A
+     * read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/
+     * CSRRCI with uimm=0 will raise an illegal instruction exception.
+     */
+    if (csr == CSR_SEED) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+
     target_ulong val = 0;
     RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
 
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 173 +++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 172 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ typedef enum {
     rv_codec_css_swsp,
     rv_codec_css_sdsp,
     rv_codec_css_sqsp,
+    rv_codec_k_bs,
+    rv_codec_k_rnum,
 } rv_codec;
 
 typedef enum {
@@ -XXX,XX +XXX,XX @@ typedef enum {
     rv_op_bclr = 359,
     rv_op_binv = 360,
     rv_op_bext = 361,
+    rv_op_aes32esmi = 362,
+    rv_op_aes32esi = 363,
+    rv_op_aes32dsmi = 364,
+    rv_op_aes32dsi = 365,
+    rv_op_aes64ks1i = 366,
+    rv_op_aes64ks2 = 367,
+    rv_op_aes64im = 368,
+    rv_op_aes64esm = 369,
+    rv_op_aes64es = 370,
+    rv_op_aes64dsm = 371,
+    rv_op_aes64ds = 372,
+    rv_op_sha256sig0 = 373,
+    rv_op_sha256sig1 = 374,
+    rv_op_sha256sum0 = 375,
+    rv_op_sha256sum1 = 376,
+    rv_op_sha512sig0 = 377,
+    rv_op_sha512sig1 = 378,
+    rv_op_sha512sum0 = 379,
+    rv_op_sha512sum1 = 380,
+    rv_op_sha512sum0r = 381,
+    rv_op_sha512sum1r = 382,
+    rv_op_sha512sig0l = 383,
+    rv_op_sha512sig0h = 384,
+    rv_op_sha512sig1l = 385,
+    rv_op_sha512sig1h = 386,
+    rv_op_sm3p0 = 387,
+    rv_op_sm3p1 = 388,
+    rv_op_sm4ed = 389,
+    rv_op_sm4ks = 390,
+    rv_op_brev8 = 391,
+    rv_op_pack = 392,
+    rv_op_packh = 393,
+    rv_op_packw = 394,
+    rv_op_unzip = 395,
+    rv_op_zip = 396,
+    rv_op_xperm4 = 397,
+    rv_op_xperm8 = 398,
 } rv_op;
 
 /* structures */
@@ -XXX,XX +XXX,XX @@ typedef struct {
     uint8_t   succ;
     uint8_t   aq;
     uint8_t   rl;
+    uint8_t   bs;
+    uint8_t   rnum;
 } rv_decode;
 
 typedef struct {
@@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = {
 #define rv_fmt_rd_rs2                 "O\t0,2"
 #define rv_fmt_rs1_offset             "O\t1,o"
 #define rv_fmt_rs2_offset             "O\t2,o"
+#define rv_fmt_rs1_rs2_bs             "O\t1,2,b"
+#define rv_fmt_rd_rs1_rnum            "O\t0,1,n"
 
 /* pseudo-instruction constraints */
 
@@ -XXX,XX +XXX,XX @@ static const rv_comp_data rvcp_csrrw[] = {
     { rv_op_illegal, NULL }
 };
 
+
 static const rv_comp_data rvcp_csrrs[] = {
     { rv_op_rdcycle, rvcc_rdcycle },
     { rv_op_rdtime, rvcc_rdtime },
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
     { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+    { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+    { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+    { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+    { "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
+    { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+    { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+    { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
 };
 
 /* CSR names */
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0003: return "fcsr";
     case 0x0004: return "uie";
     case 0x0005: return "utvec";
+    case 0x0015: return "seed";
     case 0x0040: return "uscratch";
     case 0x0041: return "uepc";
     case 0x0042: return "ucause";
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 1:
                 switch (((inst >> 27) & 0b11111)) {
                 case 0b00000: op = rv_op_slli; break;
+                case 0b00001:
+                    switch (((inst >> 20) & 0b1111111)) {
+                    case 0b0001111: op = rv_op_zip; break;
+                    }
+                    break;
+                case 0b00010:
+                    switch (((inst >> 20) & 0b1111111)) {
+                    case 0b0000000: op = rv_op_sha256sum0; break;
+                    case 0b0000001: op = rv_op_sha256sum1; break;
+                    case 0b0000010: op = rv_op_sha256sig0; break;
+                    case 0b0000011: op = rv_op_sha256sig1; break;
+                    case 0b0000100: op = rv_op_sha512sum0; break;
+                    case 0b0000101: op = rv_op_sha512sum1; break;
+                    case 0b0000110: op = rv_op_sha512sig0; break;
+                    case 0b0000111: op = rv_op_sha512sig1; break;
+                    case 0b0001000: op = rv_op_sm3p0; break;
+                    case 0b0001001: op = rv_op_sm3p1; break;
+                    }
+                    break;
                 case 0b00101: op = rv_op_bseti; break;
+                case 0b00110:
+                    switch (((inst >> 20) & 0b1111111)) {
+                    case 0b0000000: op = rv_op_aes64im; break;
+                    default:
+                        if (((inst >> 24) & 0b0111) == 0b001) {
+                            op = rv_op_aes64ks1i;
+                        }
+                        break;
+                     }
+                     break;
                 case 0b01001: op = rv_op_bclri; break;
                 case 0b01101: op = rv_op_binvi; break;
                 case 0b01100:
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 5:
                 switch (((inst >> 27) & 0b11111)) {
                 case 0b00000: op = rv_op_srli; break;
+                case 0b00001:
+                    switch (((inst >> 20) & 0b1111111)) {
+                    case 0b0001111: op = rv_op_unzip; break;
+                    }
+                    break;
                 case 0b00101: op = rv_op_orc_b; break;
                 case 0b01000: op = rv_op_srai; break;
                 case 0b01001: op = rv_op_bexti; break;
                 case 0b01100: op = rv_op_rori; break;
                 case 0b01101:
                     switch ((inst >> 20) & 0b1111111) {
+                    case 0b0011000: op = rv_op_rev8; break;
                     case 0b0111000: op = rv_op_rev8; break;
+                    case 0b0000111: op = rv_op_brev8; break;
                     }
                     break;
                 }
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 36:
                 switch ((inst >> 20) & 0b11111) {
                 case 0: op = rv_op_zext_h; break;
+                default: op = rv_op_pack; break;
                 }
                 break;
+            case 39: op = rv_op_packh; break;
+
             case 41: op = rv_op_clmul; break;
             case 42: op = rv_op_clmulr; break;
             case 43: op = rv_op_clmulh; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 132: op = rv_op_sh2add; break;
             case 134: op = rv_op_sh3add; break;
             case 161: op = rv_op_bset; break;
+            case 162: op = rv_op_xperm4; break;
+            case 164: op = rv_op_xperm8; break;
+            case 200: op = rv_op_aes64es; break;
+            case 216: op = rv_op_aes64esm; break;
+            case 232: op = rv_op_aes64ds; break;
+            case 248: op = rv_op_aes64dsm; break;
             case 256: op = rv_op_sub; break;
             case 260: op = rv_op_xnor; break;
             case 261: op = rv_op_sra; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 263: op = rv_op_andn; break;
             case 289: op = rv_op_bclr; break;
             case 293: op = rv_op_bext; break;
+            case 320: op = rv_op_sha512sum0r; break;
+            case 328: op = rv_op_sha512sum1r; break;
+            case 336: op = rv_op_sha512sig0l; break;
+            case 344: op = rv_op_sha512sig1l; break;
+            case 368: op = rv_op_sha512sig0h; break;
+            case 376: op = rv_op_sha512sig1h; break;
             case 385: op = rv_op_rol; break;
-            case 386: op = rv_op_ror; break;
+            case 389: op = rv_op_ror; break;
             case 417: op = rv_op_binv; break;
+            case 504: op = rv_op_aes64ks2; break;
+            }
+            switch ((inst >> 25) & 0b0011111) {
+            case 17: op = rv_op_aes32esi; break;
+            case 19: op = rv_op_aes32esmi; break;
+            case 21: op = rv_op_aes32dsi; break;
+            case 23: op = rv_op_aes32dsmi; break;
+            case 24: op = rv_op_sm4ed; break;
+            case 26: op = rv_op_sm4ks; break;
             }
             break;
         case 13: op = rv_op_lui; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 36:
                 switch ((inst >> 20) & 0b11111) {
                 case 0: op = rv_op_zext_h; break;
+                default: op = rv_op_packw; break;
                 }
                 break;
             case 130: op = rv_op_sh1add_uw; break;
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_cimmq(rv_inst inst)
         ((inst << 57) >> 62) << 6;
 }
 
+static uint32_t operand_bs(rv_inst inst)
+{
+    return (inst << 32) >> 62;
+}
+
+static uint32_t operand_rnum(rv_inst inst)
+{
+    return (inst << 40) >> 60;
+}
+
 /* decode operands */
 
 static void decode_inst_operands(rv_decode *dec)
@@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec)
         dec->rs2 = operand_crs2(inst);
         dec->imm = operand_cimmsqsp(inst);
         break;
+    case rv_codec_k_bs:
+        dec->rs1 = operand_rs1(inst);
+        dec->rs2 = operand_rs2(inst);
+        dec->bs = operand_bs(inst);
+        break;
+    case rv_codec_k_rnum:
+        dec->rd = operand_rd(inst);
+        dec->rs1 = operand_rs1(inst);
+        dec->rnum = operand_rnum(inst);
+        break;
     };
 }
 
@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
         case ')':
             append(buf, ")", buflen);
             break;
+        case 'b':
+            snprintf(tmp, sizeof(tmp), "%d", dec->bs);
+            append(buf, tmp, buflen);
+            break;
+        case 'n':
+            snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
+            append(buf, tmp, buflen);
+            break;
         case '0':
             append(buf, rv_ireg_name_sym[dec->rd], buflen);
             break;
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+    DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+    DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+    DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
     DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+    DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+    DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+    DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+    DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+    DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+    DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+    DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+    DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+    DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+    DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
 
     DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
     DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
-- 
2.35.1

From: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>

Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
case, walk_pte will erroneously merge them.

Enforce the split up, by tracking the virtual base address.

Let's say we have the mapping:
0x81200000 -> 0x89623000 (4K)
0x8120f000 -> 0x89624000 (4K)

Before, walk_pte would have shown:

vaddr            paddr            size             attr
---------------- ---------------- ---------------- -------
0000000081200000 0000000089623000 0000000000002000 rwxu-ad

as it only checks for subsequent paddrs. With this patch, it becomes:

vaddr            paddr            size             attr
---------------- ---------------- ---------------- -------
0000000081200000 0000000089623000 0000000000001000 rwxu-ad
000000008120f000 0000000089624000 0000000000001000 rwxu-ad

Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423215907.673663-1-ralf.ramsauer@oth-regensburg.de>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/monitor.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
 {
     hwaddr pte_addr;
     hwaddr paddr;
+    target_ulong last_start = -1;
     target_ulong pgsize;
     target_ulong pte;
     int ptshift;
@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
                  * A leaf PTE has been found
                  *
                  * If current PTE's permission bits differ from the last one,
-                 * or current PTE's ppn does not make a contiguous physical
-                 * address block together with the last one, print out the last
-                 * contiguous mapped block details.
+                 * or the current PTE breaks up a contiguous virtual or
+                 * physical mapping, address block together with the last one,
+                 * print out the last contiguous mapped block details.
                  */
                 if ((*last_attr != attr) ||
-                    (*last_paddr + *last_size != paddr)) {
+                    (*last_paddr + *last_size != paddr) ||
+                    (last_start + *last_size != start)) {
                     print_pte(mon, va_bits, *vbase, *pbase,
                               *last_paddr + *last_size - *pbase, *last_attr);
 
@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
                     *last_attr = attr;
                 }
 
+                last_start = start;
                 *last_paddr = paddr;
                 *last_size = pgsize;
             } else {
-- 
2.35.1

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add zbk* and zk* strings to isa_edata_arr

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220426095204.24142-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
         ISA_EDATA_ENTRY(zba, ext_zba),
         ISA_EDATA_ENTRY(zbb, ext_zbb),
         ISA_EDATA_ENTRY(zbc, ext_zbc),
+        ISA_EDATA_ENTRY(zbkb, ext_zbkb),
+        ISA_EDATA_ENTRY(zbkc, ext_zbkc),
+        ISA_EDATA_ENTRY(zbkx, ext_zbkx),
         ISA_EDATA_ENTRY(zbs, ext_zbs),
+        ISA_EDATA_ENTRY(zk, ext_zk),
+        ISA_EDATA_ENTRY(zkn, ext_zkn),
+        ISA_EDATA_ENTRY(zknd, ext_zknd),
+        ISA_EDATA_ENTRY(zkne, ext_zkne),
+        ISA_EDATA_ENTRY(zknh, ext_zknh),
+        ISA_EDATA_ENTRY(zkr, ext_zkr),
+        ISA_EDATA_ENTRY(zks, ext_zks),
+        ISA_EDATA_ENTRY(zksed, ext_zksed),
+        ISA_EDATA_ENTRY(zksh, ext_zksh),
+        ISA_EDATA_ENTRY(zkt, ext_zkt),
         ISA_EDATA_ENTRY(zve32f, ext_zve32f),
         ISA_EDATA_ENTRY(zve64f, ext_zve64f),
         ISA_EDATA_ENTRY(svinval, ext_svinval),
-- 
2.35.1

From: Alistair Francis <alistair.francis@wdc.com>

Move the binary and device tree loading code to the machine done
notifier. This allows us to prepare for editing the device tree as part
of the notifier.

This is based on similar code in the ARM virt machine.

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     MachineState parent;
 
     /*< public >*/
+    Notifier machine_done;
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *irqchip[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
     return aplic_m;
 }
 
+static void virt_machine_done(Notifier *notifier, void *data)
+{
+    RISCVVirtState *s = container_of(notifier, RISCVVirtState,
+                                     machine_done);
+    const MemMapEntry *memmap = virt_memmap;
+    MachineState *machine = MACHINE(s);
+    target_ulong start_addr = memmap[VIRT_DRAM].base;
+    target_ulong firmware_end_addr, kernel_start_addr;
+    uint32_t fdt_load_addr;
+    uint64_t kernel_entry;
+
+    /*
+     * Only direct boot kernel is currently supported for KVM VM,
+     * so the "-bios" parameter is not supported when KVM is enabled.
+     */
+    if (kvm_enabled()) {
+        if (machine->firmware) {
+            if (strcmp(machine->firmware, "none")) {
+                error_report("Machine mode firmware is not supported in "
+                             "combination with KVM.");
+                exit(1);
+            }
+        } else {
+            machine->firmware = g_strdup("none");
+        }
+    }
+
+    if (riscv_is_32bit(&s->soc[0])) {
+        firmware_end_addr = riscv_find_and_load_firmware(machine,
+                                    RISCV32_BIOS_BIN, start_addr, NULL);
+    } else {
+        firmware_end_addr = riscv_find_and_load_firmware(machine,
+                                    RISCV64_BIOS_BIN, start_addr, NULL);
+    }
+
+    if (machine->kernel_filename) {
+        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
+                                                         firmware_end_addr);
+
+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
+                                         kernel_start_addr, NULL);
+
+        if (machine->initrd_filename) {
+            hwaddr start;
+            hwaddr end = riscv_load_initrd(machine->initrd_filename,
+                                           machine->ram_size, kernel_entry,
+                                           &start);
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
+                                  "linux,initrd-start", start);
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
+                                  end);
+        }
+    } else {
+       /*
+        * If dynamic firmware is used, it doesn't know where is the next mode
+        * if kernel argument is not set.
+        */
+        kernel_entry = 0;
+    }
+
+    if (drive_get(IF_PFLASH, 0, 0)) {
+        /*
+         * Pflash was supplied, let's overwrite the address we jump to after
+         * reset to the base of the flash.
+         */
+        start_addr = virt_memmap[VIRT_FLASH].base;
+    }
+
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
+    /* Compute the fdt load address in dram */
+    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+                                   machine->ram_size, machine->fdt);
+    /* load the reset vector */
+    riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
+                              virt_memmap[VIRT_MROM].base,
+                              virt_memmap[VIRT_MROM].size, kernel_entry,
+                              fdt_load_addr, machine->fdt);
+
+    /*
+     * Only direct boot kernel is currently supported for KVM VM,
+     * So here setup kernel start address and fdt address.
+     * TODO:Support firmware loading and integrate to TCG start
+     */
+    if (kvm_enabled()) {
+        riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
+    }
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     char *soc_name;
-    target_ulong start_addr = memmap[VIRT_DRAM].base;
-    target_ulong firmware_end_addr, kernel_start_addr;
-    uint32_t fdt_load_addr;
-    uint64_t kernel_entry;
     DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
     int i, base_hartid, hart_count;
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
         machine->ram);
 
-    /* create device tree */
-    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-               riscv_is_32bit(&s->soc[0]));
-
     /* boot rom */
     memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
                            memmap[VIRT_MROM].size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                 mask_rom);
 
-    /*
-     * Only direct boot kernel is currently supported for KVM VM,
-     * so the "-bios" parameter is not supported when KVM is enabled.
-     */
-    if (kvm_enabled()) {
-        if (machine->firmware) {
-            if (strcmp(machine->firmware, "none")) {
-                error_report("Machine mode firmware is not supported in "
-                             "combination with KVM.");
-                exit(1);
-            }
-        } else {
-            machine->firmware = g_strdup("none");
-        }
-    }
-
-    if (riscv_is_32bit(&s->soc[0])) {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_BIN, start_addr, NULL);
-    } else {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_BIN, start_addr, NULL);
-    }
-
-    if (machine->kernel_filename) {
-        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
-                                                         firmware_end_addr);
-
-        kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                         kernel_start_addr, NULL);
-
-        if (machine->initrd_filename) {
-            hwaddr start;
-            hwaddr end = riscv_load_initrd(machine->initrd_filename,
-                                           machine->ram_size, kernel_entry,
-                                           &start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-                                  "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
-                                  end);
-        }
-    } else {
-       /*
-        * If dynamic firmware is used, it doesn't know where is the next mode
-        * if kernel argument is not set.
-        */
-        kernel_entry = 0;
-    }
-
-    if (drive_get(IF_PFLASH, 0, 0)) {
-        /*
-         * Pflash was supplied, let's overwrite the address we jump to after
-         * reset to the base of the flash.
-         */
-        start_addr = virt_memmap[VIRT_FLASH].base;
-    }
-
-    /*
-     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
-     * tree cannot be altered and we get FDT_ERR_NOSPACE.
-     */
-    s->fw_cfg = create_fw_cfg(machine);
-    rom_set_fw(s->fw_cfg);
-
-    /* Compute the fdt load address in dram */
-    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
-                                   machine->ram_size, machine->fdt);
-    /* load the reset vector */
-    riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
-                              virt_memmap[VIRT_MROM].base,
-                              virt_memmap[VIRT_MROM].size, kernel_entry,
-                              fdt_load_addr, machine->fdt);
-
-    /*
-     * Only direct boot kernel is currently supported for KVM VM,
-     * So here setup kernel start address and fdt address.
-     * TODO:Support firmware loading and integrate to TCG start
-     */
-    if (kvm_enabled()) {
-        riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
-    }
-
     /* SiFive Test MMIO device */
     sifive_test_create(memmap[VIRT_TEST].base);
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                   drive_get(IF_PFLASH, 0, i));
     }
     virt_flash_map(s, system_memory);
+
+    /* create device tree */
+    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+               riscv_is_32bit(&s->soc[0]));
+
+    s->machine_done.notify = virt_machine_done;
+    qemu_add_machine_init_done_notifier(&s->machine_done);
 }
 
 static void virt_machine_instance_init(Object *obj)
-- 
2.35.1

From: Alistair Francis <alistair.francis@wdc.com>

The ARM virt machine currently uses sysbus-fdt to create device tree
entries for dynamically created MMIO devices.

The RISC-V virt machine can also benefit from this, so move the code to
the core directory.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{arm => core}/sysbus-fdt.h | 0
 hw/arm/virt.c                         | 2 +-
 hw/arm/xlnx-versal-virt.c             | 1 -
 hw/{arm => core}/sysbus-fdt.c         | 2 +-
 hw/arm/meson.build                    | 1 -
 hw/core/meson.build                   | 1 +
 6 files changed, 3 insertions(+), 4 deletions(-)
 rename include/hw/{arm => core}/sysbus-fdt.h (100%)
 rename hw/{arm => core}/sysbus-fdt.c (99%)

diff --git a/include/hw/arm/sysbus-fdt.h b/include/hw/core/sysbus-fdt.h
similarity index 100%
rename from include/hw/arm/sysbus-fdt.h
rename to include/hw/core/sysbus-fdt.h
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "hw/pci-host/gpex.h"
 #include "hw/virtio/virtio-pci.h"
-#include "hw/arm/sysbus-fdt.h"
+#include "hw/core/sysbus-fdt.h"
 #include "hw/platform-bus.h"
 #include "hw/qdev-properties.h"
 #include "hw/arm/fdt.h"
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/device_tree.h"
 #include "hw/boards.h"
 #include "hw/sysbus.h"
-#include "hw/arm/sysbus-fdt.h"
 #include "hw/arm/fdt.h"
 #include "cpu.h"
 #include "hw/qdev-properties.h"
diff --git a/hw/arm/sysbus-fdt.c b/hw/core/sysbus-fdt.c
similarity index 99%
rename from hw/arm/sysbus-fdt.c
rename to hw/core/sysbus-fdt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sysbus-fdt.c
+++ b/hw/core/sysbus-fdt.c
@@ -XXX,XX +XXX,XX @@
 #ifdef CONFIG_LINUX
 #include <linux/vfio.h>
 #endif
-#include "hw/arm/sysbus-fdt.h"
+#include "hw/core/sysbus-fdt.h"
 #include "qemu/error-report.h"
 #include "sysemu/device_tree.h"
 #include "sysemu/tpm.h"
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@
 arm_ss = ss.source_set()
 arm_ss.add(files('boot.c'), fdt)
-arm_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
 arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
 arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
 arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
diff --git a/hw/core/meson.build b/hw/core/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/meson.build
+++ b/hw/core/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c'))
 softmmu_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c'))
 softmmu_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c'))
 softmmu_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c'))
+softmmu_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
 
 softmmu_ss.add(files(
   'cpu-sysemu.c',
-- 
2.35.1

From: Alistair Francis <alistair.francis@wdc.com>

Create a platform bus to allow dynamic devices to be connected. This is
based on the ARM implementation.

From: Alistair Francis <alistair.francis@wdc.com>

Similar to the ARM virt machine add support for adding device tree
entries for dynamically created devices.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20220427234146.1130752-5-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/qdev-properties.h"
 #include "hw/char/serial.h"
 #include "target/riscv/cpu.h"
+#include "hw/core/sysbus-fdt.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
     riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
         plic_phandles[socket]);
+
+    platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+                                   memmap[VIRT_PLATFORM_BUS].base,
+                                   memmap[VIRT_PLATFORM_BUS].size,
+                                   VIRT_PLATFORM_BUS_IRQ);
+
     g_free(plic_name);
 
     g_free(plic_cells);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
             IMSIC_MMIO_GROUP_MIN_SHIFT);
     }
     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
+
+    platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
+                                   memmap[VIRT_PLATFORM_BUS].base,
+                                   memmap[VIRT_PLATFORM_BUS].size,
+                                   VIRT_PLATFORM_BUS_IRQ);
+
     g_free(imsic_name);
 
     /* S-level IMSIC node */
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
         VIRT_IRQCHIP_NUM_SOURCES);
     riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
+
+    platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+                                   memmap[VIRT_PLATFORM_BUS].base,
+                                   memmap[VIRT_PLATFORM_BUS].size,
+                                   VIRT_PLATFORM_BUS_IRQ);
+
     g_free(aplic_name);
 
     g_free(aplic_cells);
-- 
2.35.1

From: Alistair Francis <alistair.francis@wdc.com>

Add support for plugging in devices, this was tested with the TPM
device.

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_set_aclint(Object *obj, bool value, Error **errp)
     s->have_aclint = value;
 }
 
+static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
+                                                        DeviceState *dev)
+{
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+    if (device_is_dynamic_sysbus(mc, dev)) {
+        return HOTPLUG_HANDLER(machine);
+    }
+    return NULL;
+}
+
+static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
+                                        DeviceState *dev, Error **errp)
+{
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
+
+    if (s->platform_bus_dev) {
+        MachineClass *mc = MACHINE_GET_CLASS(s);
+
+        if (device_is_dynamic_sysbus(mc, dev)) {
+            platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
+                                     SYS_BUS_DEVICE(dev));
+        }
+    }
+}
+
 static void virt_machine_class_init(ObjectClass *oc, void *data)
 {
     char str[128];
     MachineClass *mc = MACHINE_CLASS(oc);
+    HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
 
     mc->desc = "RISC-V VirtIO board";
     mc->init = virt_machine_init;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
     mc->default_ram_id = "riscv_virt_board.ram";
+    assert(!mc->get_hotplug_handler);
+    mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
+
+    hc->plug = virt_machine_device_plug_cb;
 
     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo virt_machine_typeinfo = {
     .class_init = virt_machine_class_init,
     .instance_init = virt_machine_instance_init,
     .instance_size = sizeof(RISCVVirtState),
+    .interfaces = (InterfaceInfo[]) {
+         { TYPE_HOTPLUG_HANDLER },
+         { }
+    },
 };
 
 static void virt_machine_init_register_types(void)
-- 
2.35.1

From: Alistair Francis <alistair.francis@wdc.com>

Imply the TPM sysbus devices. This allows users to add TPM devices to
the RISC-V virt board.

This was tested by first creating an emulated TPM device:

swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
        --ctrl type=unixio,path=swtpm-sock

Then launching QEMU with:

-chardev socket,id=chrtpm,path=swtpm-sock \
    -tpmdev emulator,id=tpm0,chardev=chrtpm \
    -device tpm-tis-device,tpmdev=tpm0

The TPM device can be seen in the memory tree and the generated device
tree.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/virt.rst | 20 ++++++++++++++++++++
 hw/riscv/virt.c            |  4 ++++
 hw/riscv/Kconfig           |  1 +
 3 files changed, 25 insertions(+)

diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -XXX,XX +XXX,XX @@ The minimal QEMU commands to run U-Boot SPL are:
 To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
 riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
 ``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.
+
+Enabling TPM
+------------
+
+A TPM device can be connected to the virt board by following the steps below.
+
+First launch the TPM emulator
+
+    swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
+        --ctrl type=unixio,path=swtpm-sock
+
+Then launch QEMU with:
+
+    ...
+    -chardev socket,id=chrtpm,path=swtpm-sock \
+    -tpmdev emulator,id=tpm0,chardev=chrtpm \
+    -device tpm-tis-device,tpmdev=tpm0
+
+The TPM device can be seen in the memory tree and the generated device
+tree and should be accessible from the guest software.
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/device_tree.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
+#include "sysemu/tpm.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
 #include "hw/display/ramfb.h"
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     hc->plug = virt_machine_device_plug_cb;
 
     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+#ifdef CONFIG_TPM
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
+#endif
 
     object_class_property_add_bool(oc, "aclint", virt_get_aclint,
                                    virt_set_aclint);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     imply PCI_DEVICES
     imply VIRTIO_VGA
     imply TEST_DEVICES
+    imply TPM_TIS_SYSBUS
     select RISCV_NUMA
     select GOLDFISH_RTC
     select MSI_NONBROKEN
-- 
2.35.1

The following changes since commit a51e5124a655b3dad80b36b18547cb1eca2c5eb2:

Merge tag 'pull-omnibus-111023-1' of https://gitlab.com/stsquad/qemu into staging (2023-10-11 09:43:10 -0400)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231012-1

for you to fetch changes up to 837570cef237b634eb4c245363470deebea7089d:

target/riscv: Fix vfwmaccbf16.vf (2023-10-12 12:50:13 +1000)

----------------------------------------------------------------
Second RISC-V PR for 8.2

* Add support for the max CPU
 * Detect user choice in TCG
 * Clear CSR values at reset and sync MPSTATE with host
 * Fix the typo of inverted order of pmpaddr13 and pmpaddr14
 * Split TCG/KVM accelerators from cpu.c
 * Add extension properties for all cpus
 * Replace GDB exit calls with proper shutdown
 * Support KVM_GET_REG_LIST
 * Remove RVG warning
 * Use env_archcpu for better performance
 * Deprecate capital 'Z' CPU properties
 * Fix vfwmaccbf16.vf

----------------------------------------------------------------
Alvin Chang (1):
      disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14

Clément Chigot (5):
      softmmu: add means to pass an exit code when requesting a shutdown
      softmmu: pass the main loop status to gdb "Wxx" packet
      hw/misc/sifive_test.c: replace exit calls with proper shutdown
      hw/char: riscv_htif: replace exit calls with proper shutdown
      gdbstub: replace exit calls with proper shutdown for softmmu

Daniel Henrique Barboza (45):
      target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
      target/riscv/cpu.c: skip 'bool' check when filtering KVM props
      target/riscv/cpu.c: split kvm prop handling to its own helper
      target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
      target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
      target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
      target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
      target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
      target/riscv/cpu.c: limit cfg->vext_spec log message
      target/riscv: add 'max' CPU type
      avocado, risc-v: add tuxboot tests for 'max' CPU
      target/riscv: deprecate the 'any' CPU type
      target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
      target/riscv: make CPUCFG() macro public
      target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
      target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
      target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
      target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
      target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
      target/riscv/cpu.c: consider user option with RVG
      target/riscv: introduce TCG AccelCPUClass
      target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
      target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
      target/riscv: move riscv_tcg_ops to tcg-cpu.c
      target/riscv/cpu.c: add .instance_post_init()
      target/riscv: move 'host' CPU declaration to kvm.c
      target/riscv/cpu.c: mark extensions arrays as 'const'
      target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
      target/riscv: make riscv_add_satp_mode_properties() public
      target/riscv: remove kvm-stub.c
      target/riscv: introduce KVM AccelCPUClass
      target/riscv: move KVM only files to kvm subdir
      target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
      target/riscv/cpu.c: export set_misa()
      target/riscv/tcg: introduce tcg_cpu_instance_init()
      target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
      target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
      target/riscv/cpu.c: export isa_edata_arr[]
      target/riscv/cpu: move priv spec functions to tcg-cpu.c
      target/riscv: add riscv_cpu_get_name()
      target/riscv/tcg-cpu.c: add extension properties for all cpus
      target/riscv/kvm: improve 'init_multiext_cfg' error msg
      target/riscv/kvm: support KVM_GET_REG_LIST
      target/riscv/tcg: remove RVG warning
      target/riscv: deprecate capital 'Z' CPU properties

Max Chou (1):
      target/riscv: Fix vfwmaccbf16.vf

Richard W.M. Jones (1):
      target/riscv: Use env_archcpu for better performance

liguang.zhang (1):
      target/riscv: Clear CSR values at reset and sync MPSTATE with host

docs/about/deprecated.rst             |   35 ++
 include/gdbstub/syscalls.h            |    9 +
 include/sysemu/runstate.h             |    2 +
 include/sysemu/sysemu.h               |    2 +-
 target/riscv/cpu-qom.h                |    1 +
 target/riscv/cpu.h                    |   34 +-
 target/riscv/{ => kvm}/kvm_riscv.h    |    2 +-
 target/riscv/tcg/tcg-cpu.h            |   27 +
 disas/riscv.c                         |    4 +-
 gdbstub/gdbstub.c                     |    5 +-
 gdbstub/system.c                      |    6 +
 gdbstub/user.c                        |    6 +
 hw/char/riscv_htif.c                  |    5 +-
 hw/intc/riscv_aplic.c                 |    2 +-
 hw/misc/sifive_test.c                 |    9 +-
 hw/riscv/virt.c                       |    2 +-
 system/main.c                         |    2 +-
 system/runstate.c                     |   16 +-
 target/riscv/cpu.c                    | 1030 +++++++--------------------------
 target/riscv/cpu_helper.c             |    3 +-
 target/riscv/csr.c                    |    1 +
 target/riscv/kvm-stub.c               |   30 -
 target/riscv/{kvm.c => kvm/kvm-cpu.c} |  272 ++++++++-
 target/riscv/tcg/tcg-cpu.c            |  949 ++++++++++++++++++++++++++++++
 target/riscv/vector_helper.c          |    2 +-
 target/riscv/kvm/meson.build          |    1 +
 target/riscv/meson.build              |    4 +-
 target/riscv/tcg/meson.build          |    2 +
 tests/avocado/tuxrun_baselines.py     |   32 +
 29 files changed, 1604 insertions(+), 891 deletions(-)
 rename target/riscv/{ => kvm}/kvm_riscv.h (95%)
 create mode 100644 target/riscv/tcg/tcg-cpu.h
 delete mode 100644 target/riscv/kvm-stub.c
 rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (81%)
 create mode 100644 target/riscv/tcg/tcg-cpu.c
 create mode 100644 target/riscv/kvm/meson.build
 create mode 100644 target/riscv/tcg/meson.build

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.

Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] array for them. Add all these properties in
riscv_cpu_add_user_properties() as it is already being done today.

'mmu' and 'pmp' aren't really extensions in the usual way we think about
RISC-V extensions. These are closer to CPU features/options, so move
both to riscv_cpu_options[] too. In the near future we'll need to match
all extensions with all entries in isa_edata_arr[], and so it happens
that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv
spec version restriction). This further emphasizes the point that these
are more a CPU option than an extension.

No functional changes made.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 
 static Property riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
-    DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
     DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
     DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
-    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
-    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
     DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
 
-    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
-    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
-    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-
     DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
     DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
 
     DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
-    DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
     DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
-    DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
 
     DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
 
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static Property riscv_cpu_options[] = {
+    DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
+
+    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+
+    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+
+    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+
+    DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
+    DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+};
 
 #ifndef CONFIG_USER_ONLY
 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
 #endif
         qdev_property_add_static(dev, prop);
     }
+
+    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+        /* Check if KVM created the property already */
+        if (object_property_find(obj, riscv_cpu_options[i].name)) {
+            continue;
+        }
+        qdev_property_add_static(dev, &riscv_cpu_options[i]);
+    }
 }
 
 static Property riscv_cpu_properties[] = {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
              * Set the default to disabled for every extension
              * unknown to KVM and error out if the user attempts
              * to enable any of them.
-             *
-             * We're giving a pass for non-bool properties since they're
-             * not related to the availability of extensions and can be
-             * safely ignored as is.
              */
-            if (prop->info == &qdev_prop_bool) {
-                object_property_add(obj, prop->name, "bool",
-                                    NULL, cpu_set_cfg_unavailable,
-                                    NULL, (void *)prop->name);
-                continue;
-            }
+            object_property_add(obj, prop->name, "bool",
+                                NULL, cpu_set_cfg_unavailable,
+                                NULL, (void *)prop->name);
+            continue;
         }
 #endif
         qdev_property_add_static(dev, prop);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's dealing with KVM constraints mixed in with TCG
constraints. We're going to pay a high price to share a couple of common
lines of code between the two.

Create a new kvm_riscv_cpu_add_kvm_properties() helper that will be
forked from riscv_cpu_add_user_properties() if we're running KVM. The
helper includes all properties that a KVM CPU will add. The rest of
riscv_cpu_add_user_properties() body will then be relieved from having
to deal with KVM constraints.

The helper was declared in kvm_stubs.h, while being implemented in
cpu.c, to allow '--enable-debug' builds to work. The compiler won't
remove the kvm_riscv_cpu_add_kvm_properties() reference when
'kvm_enabled()' is false if we end up with an unused function. Even
though being a KVM only helper we can't implement it in kvm.c due to its
many dependencies inside cpu.c, so make it public in kvm_riscv.h and
keep its implementation in cpu.c for now. We'll move it to kvm.c in the
near future.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm_riscv.h |  3 ++
 target/riscv/cpu.c       | 65 +++++++++++++++++++++++++---------------
 2 files changed, 44 insertions(+), 24 deletions(-)

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 #ifndef QEMU_KVM_RISCV_H
 #define QEMU_KVM_RISCV_H
 
+/* Temporarily implemented in cpu.c */
+void kvm_riscv_cpu_add_kvm_properties(Object *obj);
+
 void kvm_riscv_init_user_properties(Object *cpu_obj);
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
     DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
 };
 
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_KVM
 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
                                     const char *name,
                                     void *opaque, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
                    propname);
     }
 }
+
+static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
+{
+    /* Check if KVM created the property already */
+    if (object_property_find(obj, prop_name)) {
+        return;
+    }
+
+    /*
+     * Set the default to disabled for every extension
+     * unknown to KVM and error out if the user attempts
+     * to enable any of them.
+     */
+    object_property_add(obj, prop_name, "bool",
+                        NULL, cpu_set_cfg_unavailable,
+                        NULL, (void *)prop_name);
+}
+
+void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+{
+    Property *prop;
+    DeviceState *dev = DEVICE(obj);
+
+    kvm_riscv_init_user_properties(obj);
+    riscv_cpu_add_misa_properties(obj);
+
+    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+
+    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+        /* Check if KVM created the property already */
+        if (object_property_find(obj, riscv_cpu_options[i].name)) {
+            continue;
+        }
+        qdev_property_add_static(dev, &riscv_cpu_options[i]);
+    }
+}
 #endif
 
 /*
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
     riscv_add_satp_mode_properties(obj);
 
     if (kvm_enabled()) {
-        kvm_riscv_init_user_properties(obj);
+        kvm_riscv_cpu_add_kvm_properties(obj);
+        return;
     }
 #endif
 
     riscv_cpu_add_misa_properties(obj);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-#ifndef CONFIG_USER_ONLY
-        if (kvm_enabled()) {
-            /* Check if KVM created the property already */
-            if (object_property_find(obj, prop->name)) {
-                continue;
-            }
-
-            /*
-             * Set the default to disabled for every extension
-             * unknown to KVM and error out if the user attempts
-             * to enable any of them.
-             */
-            object_property_add(obj, prop->name, "bool",
-                                NULL, cpu_set_cfg_unavailable,
-                                NULL, (void *)prop->name);
-            continue;
-        }
-#endif
         qdev_property_add_static(dev, prop);
     }
 
     for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
-        /* Check if KVM created the property already */
-        if (object_property_find(obj, riscv_cpu_options[i].name)) {
-            continue;
-        }
         qdev_property_add_static(dev, &riscv_cpu_options[i]);
     }
 }
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
iterating in the riscv_cpu_options[] array, making it similar to what
we already do when working with riscv_cpu_extensions[].

We also have a more sophisticated motivation behind this change. In the
future we might need to export riscv_cpu_options[] to other files, and
ARRAY_LIST() doesn't work properly in that case because the array size
isn't exposed to the header file. Here's a future sight of what we would
deal with:

./target/riscv/kvm.c:1057:5: error: nested extern declaration of 'riscv_cpu_add_misa_properties' [-Werror=nested-externs]
n file included from ../target/riscv/kvm.c:19:
home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
 473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
     |                               ^
./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
1047 |         for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
     |                             ^~~~~~~~~~
./target/riscv/kvm.c:1059:5: note: in expansion of macro 'ADD_UNAVAIL_KVM_PROP_ARRAY'
1059 |     ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions);
     |     ^~~~~~~~~~~~~~~~~~~~~~~~~~
home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
 473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
     |                               ^
./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
1047 |         for (int i = 0; i < ARRAY_SIZE(_array); i++) { \

Homogenize the present and change the future by using
DEFINE_PROP_END_OF_LIST() in riscv_cpu_options[].

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
 
     DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
     DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+
+    DEFINE_PROP_END_OF_LIST(),
 };
 
 #ifdef CONFIG_KVM
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 
-    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
+    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
         /* Check if KVM created the property already */
-        if (object_property_find(obj, riscv_cpu_options[i].name)) {
+        if (object_property_find(obj, prop->name)) {
             continue;
         }
-        qdev_property_add_static(dev, &riscv_cpu_options[i]);
+        qdev_property_add_static(dev, prop);
     }
 }
 #endif
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
         qdev_property_add_static(dev, prop);
     }
 
-    for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
-        qdev_property_add_static(dev, &riscv_cpu_options[i]);
+    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
     }
 }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].

riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
changed to keep adding non-ratified properties to users.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 
-    /* These are experimental so mark with 'x-' */
+    DEFINE_PROP_END_OF_LIST(),
+};
 
+/* These are experimental so mark with 'x-' */
+static Property riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
     DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 
+    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+
     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
         /* Check if KVM created the property already */
         if (object_property_find(obj, prop->name)) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
         qdev_property_add_static(dev, prop);
     }
+
+    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
+    }
 }
 
 static Property riscv_cpu_properties[] = {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.

Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
     DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
 
-    /* Vendor-specific custom extensions */
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static Property riscv_cpu_vendor_exts[] = {
     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
     DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
     DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 
+    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+
     for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
         qdev_property_add_static(dev, prop);
     }
 
+    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
+    }
+
     for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
         qdev_property_add_static(dev, prop);
     }
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a helper to hide the repetition away.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 29 +++++++++++++----------------
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
+{
+    g_assert(array);
+
+    for (Property *prop = array; prop && prop->name; prop++) {
+        qdev_property_add_static(dev, prop);
+    }
+}
+
 #ifdef CONFIG_KVM
 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
                                     const char *name,
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
  */
 static void riscv_cpu_add_user_properties(Object *obj)
 {
-    Property *prop;
     DeviceState *dev = DEVICE(obj);
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
 
     riscv_cpu_add_misa_properties(obj);
 
-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
-    }
-
-    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
-    }
-
-    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
-    }
-
-    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
-    }
+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
+    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
 }
 
 static Property riscv_cpu_properties[] = {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230912132423.268494-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
                         NULL, (void *)prop_name);
 }
 
+static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
+                                                 Property *array)
+{
+    g_assert(array);
+
+    for (Property *prop = array; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+}
+
 void kvm_riscv_cpu_add_kvm_properties(Object *obj)
 {
     Property *prop;
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
     kvm_riscv_init_user_properties(obj);
     riscv_cpu_add_misa_properties(obj);
 
-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-    }
-
-    for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-    }
-
-    for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {
-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-    }
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 
     for (prop = riscv_cpu_options; prop && prop->name; prop++) {
         /* Check if KVM created the property already */
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Inside riscv_cpu_validate_v() we're always throwing a log message if the
user didn't set a vector version via 'vext_spec'.

We're going to include one case with the 'max' CPU where env->vext_ver
will be set in the cpu_init(). But that alone will not stop the "vector
version is not specified" message from appearing. The usefulness of this
log message is debatable for the generic CPUs, but for a 'max' CPU type,
where we are supposed to deliver a CPU model with all features possible,
it's strange to force users to set 'vext_spec' to get rid of this
message.

Change riscv_cpu_validate_v() to not throw this log message if
env->vext_ver is already set.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230912132423.268494-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
                                  Error **errp)
 {
-    int vext_version = VEXT_VERSION_1_00_0;
-
     if (!is_power_of_2(cfg->vlen)) {
         error_setg(errp, "Vector extension VLEN must be power of 2");
         return;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
     }
     if (cfg->vext_spec) {
         if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
-            vext_version = VEXT_VERSION_1_00_0;
+            env->vext_ver = VEXT_VERSION_1_00_0;
         } else {
             error_setg(errp, "Unsupported vector spec version '%s'",
                        cfg->vext_spec);
             return;
         }
-    } else {
+    } else if (env->vext_ver == 0) {
         qemu_log("vector version is not specified, "
                  "use the default value v1.0\n");
+
+        env->vext_ver = VEXT_VERSION_1_00_0;
     }
-    env->vext_ver = vext_version;
 }
 
 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.

What we consider "most capable CPU" in this context are related to
ratified, non-vendor extensions. This means that we want the 'max' CPU
to enable all (possible) ratified extensions by default. The reasoning
behind this design is (1) vendor extensions can conflict with each other
and we won't play favorities deciding which one is default or not and
(2) non-ratified extensions are always prone to changes, not being
stable enough to be enabled by default.

All this said, we're still not able to enable all ratified extensions
due to conflicts between them. Zfinx and all its dependencies aren't
enabled because of a conflict with RVF. zce, zcmp and zcmt are also
disabled due to RVD conflicts. When running with 64 bits we're also
disabling zcf.

MISA bits RVG, RVJ and RVV are also being set manually since they're
default disabled.

This is the resulting 'riscv,isa' DT for this new CPU:

rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu-qom.h |  1 +
 target/riscv/cpu.c     | 56 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -XXX,XX +XXX,XX @@
 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
 
 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
+#define TYPE_RISCV_CPU_MAX              RISCV_CPU_TYPE_NAME("max")
 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
 #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
 };
 
 static void riscv_cpu_add_user_properties(Object *obj);
+static void riscv_init_max_cpu_extensions(Object *obj);
 
 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 {
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
     cpu->cfg.pmp = true;
 }
 
+static void riscv_max_cpu_init(Object *obj)
+{
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    RISCVMXL mlx = MXL_RV64;
+
+#ifdef TARGET_RISCV32
+    mlx = MXL_RV32;
+#endif
+    set_misa(env, mlx, 0);
+    riscv_cpu_add_user_properties(obj);
+    riscv_init_max_cpu_extensions(obj);
+    env->priv_ver = PRIV_VERSION_LATEST;
+#ifndef CONFIG_USER_ONLY
+    set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
+                                VM_1_10_SV32 : VM_1_10_SV57);
+#endif
+}
+
 #if defined(TARGET_RISCV64)
 static void rv64_base_cpu_init(Object *obj)
 {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
     riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
 }
 
+/*
+ * The 'max' type CPU will have all possible ratified
+ * non-vendor extensions enabled.
+ */
+static void riscv_init_max_cpu_extensions(Object *obj)
+{
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    Property *prop;
+
+    /* Enable RVG, RVJ and RVV that are disabled by default */
+    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+
+    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+        object_property_set_bool(obj, prop->name, true, NULL);
+    }
+
+    /* set vector version */
+    env->vext_ver = VEXT_VERSION_1_00_0;
+
+    /* Zfinx is not compatible with F. Disable it */
+    object_property_set_bool(obj, "zfinx", false, NULL);
+    object_property_set_bool(obj, "zdinx", false, NULL);
+    object_property_set_bool(obj, "zhinx", false, NULL);
+    object_property_set_bool(obj, "zhinxmin", false, NULL);
+
+    object_property_set_bool(obj, "zce", false, NULL);
+    object_property_set_bool(obj, "zcmp", false, NULL);
+    object_property_set_bool(obj, "zcmt", false, NULL);
+
+    if (env->misa_mxl != MXL_RV32) {
+        object_property_set_bool(obj, "zcf", false, NULL);
+    }
+}
+
 static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .abstract = true,
     },
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
+    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,      riscv_max_cpu_init),
 #if defined(CONFIG_KVM)
     DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
 #endif
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new frozen/ratified RISC-V extensions.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tests/avocado/tuxrun_baselines.py | 32 +++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/tuxrun_baselines.py
+++ b/tests/avocado/tuxrun_baselines.py
@@ -XXX,XX +XXX,XX @@ def test_riscv64(self):
 
         self.common_tuxrun(csums=sums)
 
+    def test_riscv32_maxcpu(self):
+        """
+        :avocado: tags=arch:riscv32
+        :avocado: tags=machine:virt
+        :avocado: tags=cpu:max
+        :avocado: tags=tuxboot:riscv32
+        """
+        sums = { "Image" :
+                 "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
+                 "fw_jump.elf" :
+                 "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
+                 "rootfs.ext4.zst" :
+                 "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
+
+        self.common_tuxrun(csums=sums)
+
+    def test_riscv64_maxcpu(self):
+        """
+        :avocado: tags=arch:riscv64
+        :avocado: tags=machine:virt
+        :avocado: tags=cpu:max
+        :avocado: tags=tuxboot:riscv64
+        """
+        sums = { "Image" :
+                 "cd634badc65e52fb63465ec99e309c0de0369f0841b7d9486f9729e119bac25e",
+                 "fw_jump.elf" :
+                 "6e3373abcab4305fe151b564a4c71110d833c21f2c0a1753b7935459e36aedcf",
+                 "rootfs.ext4.zst" :
+                 "b18e3a3bdf27be03da0b285e84cb71bf09eca071c3a087b42884b6982ed679eb" }
+
+        self.common_tuxrun(csums=sums)
+
     def test_s390(self):
         """
         :avocado: tags=arch:s390x
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't help us either in
knowing what was the original design of this CPU type.

The closest we have is a comment from Alistair [1] where he recalls from
memory that the 'any' CPU is supposed to behave like the newly added
'max' CPU. He also suggested that the 'any' CPU should be removed.

The default CPUs are rv32 and rv64, so removing the 'any' CPU will have
impact only on users that might have a script that uses '-cpu any'.
And those users are better off using the default CPUs or the new 'max'
CPU.

We would love to just remove the code and be done with it, but one does
not simply remove a feature in QEMU. We'll put the CPU in quarantine
first, letting users know that we have the intent of removing it in the
future.

[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/about/deprecated.rst | 12 ++++++++++++
 target/riscv/cpu.c        |  5 +++++
 2 files changed, 17 insertions(+)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ QEMU's ``vhost`` feature, which would eliminate the high latency costs under
 which the 9p ``proxy`` backend currently suffers. However as of to date nobody
 has indicated plans for such kind of reimplementation unfortunately.
 
+RISC-V 'any' CPU type ``-cpu any`` (since 8.2)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The 'any' CPU type was introduced back in 2018 and has been around since the
+initial RISC-V QEMU port. Its usage has always been unclear: users don't know
+what to expect from a CPU called 'any', and in fact the CPU does not do anything
+special that isn't already done by the default CPUs rv32/rv64.
+
+After the introduction of the 'max' CPU type, RISC-V now has a good coverage
+of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete
+CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any'
+CPU type starting in 8.2.
 
 Block device options
 ''''''''''''''''''''
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
     Error *local_err = NULL;
 
+    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
+        warn_report("The 'any' CPU is deprecated and will be "
+                    "removed in the future.");
+    }
+
     cpu_exec_realizefn(cs, &local_err);
     if (local_err != NULL) {
         error_propagate(errp, local_err);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.

Change all existing callers to use edata->ext_enable_offset instead of
'edata'.

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.

Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 2 ++
 target/riscv/cpu.c | 2 +-
 target/riscv/kvm.c | 8 +++-----
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 const char *riscv_get_misa_ext_name(uint32_t bit);
 const char *riscv_get_misa_ext_description(uint32_t bit);
 
+#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
+
 /* Privileged specification version */
 enum {
     PRIV_VERSION_1_10_0 = 0,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
 };
 
 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
-    {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
+    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
 
 /*
  * From vector_helper.c
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
     }
 }
 
-#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop)
-
 #define KVM_EXT_CFG(_name, _prop, _reg_id) \
-    {.name = _name, .offset = CPUCFG(_prop), \
+    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .kvm_reg_id = _reg_id}
 
 static KVMCPUConfig kvm_multi_ext_cfgs[] = {
@@ -XXX,XX +XXX,XX @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v,
 
 static KVMCPUConfig kvm_cbom_blocksize = {
     .name = "cbom_blocksize",
-    .offset = CPUCFG(cbom_blocksize),
+    .offset = CPU_CFG_OFFSET(cbom_blocksize),
     .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)
 };
 
 static KVMCPUConfig kvm_cboz_blocksize = {
     .name = "cboz_blocksize",
-    .offset = CPUCFG(cboz_blocksize),
+    .offset = CPU_CFG_OFFSET(cboz_blocksize),
     .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)
 };
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

During realize() time we're activating a lot of extensions based on some
criteria, e.g.:

if (cpu->cfg.ext_zk) {
        cpu->cfg.ext_zkn = true;
        cpu->cfg.ext_zkr = true;
        cpu->cfg.ext_zkt = true;
    }

This practice resulted in at least one case where we ended up enabling
something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that
has priv_spec older than 1.12.0.

We're also not considering user choice. There's no way of doing it now
but this is about to change in the next few patches.

cpu_cfg_ext_auto_update() will check for priv version mismatches before
enabling extensions. If we have a mismatch between the current priv
version and the extension we want to enable, do not enable it. In the
near future, this same function will also consider user choice when
deciding if we're going to enable/disable an extension or not.

For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 40 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
     *ext_enabled = en;
 }
 
+static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
+            continue;
+        }
+
+        return isa_edata_arr[i].min_version;
+    }
+
+    g_assert_not_reached();
+}
+
+static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
+                                    bool value)
+{
+    CPURISCVState *env = &cpu->env;
+    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
+    int min_version;
+
+    if (prev_val == value) {
+        return;
+    }
+
+    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
+        /* Do not enable it if priv_ver is older than min_version */
+        min_version = cpu_cfg_ext_get_min_version(ext_offset);
+        if (env->priv_ver < min_version) {
+            return;
+        }
+    }
+
+    isa_ext_update_enabled(cpu, ext_offset, value);
+}
+
 const char * const riscv_int_regnames[] = {
     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 
     /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
     if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
-        cpu->cfg.ext_zca = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
-            cpu->cfg.ext_zcf = true;
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
         }
         if (riscv_has_ext(env, RVD)) {
-            cpu->cfg.ext_zcd = true;
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
         }
     }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).

We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every other extension enablement
during realize is now done via cpu_cfg_ext_auto_update().

The end goal is that only cpu init() functions will handle extension
flags directly via "cpu->cfg.ext_N = true|false".

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 50 +++++++++++++++++++++++-----------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zfh) {
-        cpu->cfg.ext_zfhmin = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
     }
 
     if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         }
 
         /* The V vector extension depends on the Zve64d extension */
-        cpu->cfg.ext_zve64d = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
     }
 
     /* The Zve64d extension depends on the Zve64f extension */
     if (cpu->cfg.ext_zve64d) {
-        cpu->cfg.ext_zve64f = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
     }
 
     /* The Zve64f extension depends on the Zve32f extension */
     if (cpu->cfg.ext_zve64f) {
-        cpu->cfg.ext_zve32f = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
     }
 
     if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zvfh) {
-        cpu->cfg.ext_zvfhmin = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
     }
 
     if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 
     /* Set the ISA extensions, checks should have happened above */
     if (cpu->cfg.ext_zhinx) {
-        cpu->cfg.ext_zhinxmin = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
     }
 
     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zce) {
-        cpu->cfg.ext_zca = true;
-        cpu->cfg.ext_zcb = true;
-        cpu->cfg.ext_zcmp = true;
-        cpu->cfg.ext_zcmt = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
-            cpu->cfg.ext_zcf = true;
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zk) {
-        cpu->cfg.ext_zkn = true;
-        cpu->cfg.ext_zkr = true;
-        cpu->cfg.ext_zkt = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
     }
 
     if (cpu->cfg.ext_zkn) {
-        cpu->cfg.ext_zbkb = true;
-        cpu->cfg.ext_zbkc = true;
-        cpu->cfg.ext_zbkx = true;
-        cpu->cfg.ext_zkne = true;
-        cpu->cfg.ext_zknd = true;
-        cpu->cfg.ext_zknh = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
     }
 
     if (cpu->cfg.ext_zks) {
-        cpu->cfg.ext_zbkb = true;
-        cpu->cfg.ext_zbkc = true;
-        cpu->cfg.ext_zbkx = true;
-        cpu->cfg.ext_zksed = true;
-        cpu->cfg.ext_zksh = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
     }
 
     /*
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Property set()
callback. The set() callback also does init() time validations based on
the current KVM driver capabilities.

For TCG we would want a 'user_set' mechanic too, but we would look
ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set
or not. If we copy what was made in the KVM side we would look for
'user_set' for one into 60+ extension structs spreaded in 3 arrays
(riscv_cpu_extensions, riscv_cpu_experimental_exts,
riscv_cpu_vendor_exts).

We'll still need an extension struct but we won't be using the
'user_set' flag:

- 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to what
we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'.
DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by
MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct;

- the 'multi_ext_user_opts' hash will be used to store the offset of each
extension that the user set via the set() callback, cpu_set_multi_ext_cfg().
For now we're just initializing and populating it - next patch will use
it to determine if a certain extension was user set;

- cpu_add_multi_ext_prop() is a new helper that will replace the
qdev_property_add_static() calls that our macros are doing to populate
user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY()
for clarity. Note that the non-extension properties in
riscv_cpu_options[] still need to be declared via qdev().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 258 ++++++++++++++++++++++++++++-----------------
 1 file changed, 159 insertions(+), 99 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
 };
 
+/* Hash that stores user set extensions */
+static GHashTable *multi_ext_user_opts;
+
 static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
 {
     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
 #endif /* CONFIG_USER_ONLY */
+
+    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
 }
 
 typedef struct RISCVCPUMisaExtConfig {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
     }
 }
 
-static Property riscv_cpu_extensions[] = {
+typedef struct RISCVCPUMultiExtConfig {
+    const char *name;
+    uint32_t offset;
+    bool enabled;
+} RISCVCPUMultiExtConfig;
+
+#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
+    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
+     .enabled = _defval}
+
+static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
-    DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
-    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-    DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true),
-    DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
-    DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
-    DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true),
-    DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
-    DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
-    DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
-    DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
-    DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
-    DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
-
-    DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
-    DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
-    DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
-    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
-    DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
-
-    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
-    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
-    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
-    DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
-    DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
-    DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
-    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
-    DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
-    DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
-    DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
-    DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
-    DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
-    DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
-    DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
-    DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
-    DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
-    DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
-
-    DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
-    DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
-    DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
-    DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
-
-    DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
-    DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
-
-    DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
-
-    DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
-    DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
-    DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
-    DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
-    DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
-    DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
-    DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
-    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
+    MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
+    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
+    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
+    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
+    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
+    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
+    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
+    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
+    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
+    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
+    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
+    MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
+
+    MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
+    MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
+    MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
+    MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
+    MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
+
+    MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
+    MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
+    MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
+    MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
+    MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
+    MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
+    MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
+    MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
+    MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
+    MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
+    MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
+    MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
+    MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
+    MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
+    MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
+    MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
+    MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
+
+    MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
+    MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
+    MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
+    MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
+
+    MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
+    MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
+
+    MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
+
+    MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
+    MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
+    MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
+    MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
+    MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
+    MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
+    MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
+    MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
 
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static Property riscv_cpu_vendor_exts[] = {
-    DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
-    DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
-    DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
-    DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
-    DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
-    DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
-    DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
-    DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
-    DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
-    DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
-    DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
-    DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
+static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+    MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
+    MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
+    MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
+    MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
+    MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
+    MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
+    MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
+    MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
+    MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
+    MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
+    MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
+    MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
 
     DEFINE_PROP_END_OF_LIST(),
 };
 
 /* These are experimental so mark with 'x-' */
-static Property riscv_cpu_experimental_exts[] = {
+static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
-    DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-    DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
-    DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
+    MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
+    MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
+    MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
 
-    DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
-    DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
+    MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
+    MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
 
-    DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
-    DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
-    DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
+    MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
+    MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
+    MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
 
     /* Vector cryptography extensions */
-    DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
-    DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
-    DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false),
-    DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
-    DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
-    DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
-    DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false),
-    DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
+    MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
+    MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
+    MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
+    MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
+    MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
+    MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
+    MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
 
     DEFINE_PROP_END_OF_LIST(),
 };
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_options[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static void riscv_cpu_add_qdev_prop_array(DeviceState *dev, Property *array)
+static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                  void *opaque, Error **errp)
+{
+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+    bool value;
+
+    if (!visit_type_bool(v, name, &value, errp)) {
+        return;
+    }
+
+    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
+
+    g_hash_table_insert(multi_ext_user_opts,
+                        GUINT_TO_POINTER(multi_ext_cfg->offset),
+                        (gpointer)value);
+}
+
+static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                  void *opaque, Error **errp)
+{
+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
+
+    visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_add_multi_ext_prop(Object *cpu_obj,
+                                   RISCVCPUMultiExtConfig *multi_cfg)
+{
+    object_property_add(cpu_obj, multi_cfg->name, "bool",
+                        cpu_get_multi_ext_cfg,
+                        cpu_set_multi_ext_cfg,
+                        NULL, (void *)multi_cfg);
+
+    /*
+     * Set def val directly instead of using
+     * object_property_set_bool() to save the set()
+     * callback hash for user inputs.
+     */
+    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
+                           multi_cfg->enabled);
+}
+
+static void riscv_cpu_add_multiext_prop_array(Object *obj,
+                                              RISCVCPUMultiExtConfig *array)
 {
     g_assert(array);
 
-    for (Property *prop = array; prop && prop->name; prop++) {
-        qdev_property_add_static(dev, prop);
+    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+        cpu_add_multi_ext_prop(obj, prop);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
 }
 
 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-                                                 Property *array)
+                                                 RISCVCPUMultiExtConfig *array)
 {
     g_assert(array);
 
-    for (Property *prop = array; prop && prop->name; prop++) {
+    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 }
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
  */
 static void riscv_cpu_add_user_properties(Object *obj)
 {
-    DeviceState *dev = DEVICE(obj);
-
 #ifndef CONFIG_USER_ONLY
     riscv_add_satp_mode_properties(obj);
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
 
     riscv_cpu_add_misa_properties(obj);
 
-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions);
-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options);
-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts);
-    riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
+
+    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+        qdev_property_add_static(DEVICE(obj), prop);
+    }
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    Property *prop;
+    RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'multi_ext_user_opts'
hash.

This means that, as is today, all extensions we're setting for the 'max'
CPU will be seen as user set in the future. Let's change set_bool() to
isa_ext_update_enabled() that will just enable/disable the flag on a
certain offset.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-        object_property_set_bool(obj, prop->name, true, NULL);
+        isa_ext_update_enabled(cpu, prop->offset, true);
     }
 
     /* set vector version */
     env->vext_ver = VEXT_VERSION_1_00_0;
 
     /* Zfinx is not compatible with F. Disable it */
-    object_property_set_bool(obj, "zfinx", false, NULL);
-    object_property_set_bool(obj, "zdinx", false, NULL);
-    object_property_set_bool(obj, "zhinx", false, NULL);
-    object_property_set_bool(obj, "zhinxmin", false, NULL);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
 
-    object_property_set_bool(obj, "zce", false, NULL);
-    object_property_set_bool(obj, "zcmp", false, NULL);
-    object_property_set_bool(obj, "zcmt", false, NULL);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
 
     if (env->misa_mxl != MXL_RV32) {
-        object_property_set_bool(obj, "zcf", false, NULL);
+        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
     }
 }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.

This will make us honor user choice instead of overwriting the values.
Users will then be informed whether they're using an incompatible set of
extensions instead of QEMU setting a magic value that works.

The reason why we're not implementing user choice for MISA extensions
right now is because, today, we do not silently change any MISA bit
during realize() time (we do warn when enabling bits if RVG is enabled).
We do that - a lot - with multi-letter extensions though, so we're
handling the most immediate concern first.

After this patch, we'll now error out if the user explicitly set 'zce' to true
and 'zca' to false:

$ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=true,zca=false -nographic
qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension

This didn't happen before because we were enabling 'zca' if 'zce' was enabled
regardless if the user set 'zca' to false.

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
     g_assert_not_reached();
 }
 
+static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+{
+    return g_hash_table_contains(multi_ext_user_opts,
+                                 GUINT_TO_POINTER(ext_offset));
+}
+
 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
                                     bool value)
 {
@@ -XXX,XX +XXX,XX @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
         return;
     }
 
+    if (cpu_cfg_ext_is_user_set(ext_offset)) {
+        return;
+    }
+
     if (value && env->priv_ver != PRIV_VERSION_LATEST) {
         /* Do not enable it if priv_ver is older than min_version */
         min_version = cpu_cfg_ext_get_min_version(ext_offset);
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
     MISA_CFG(RVG, false),
 };
 
+/*
+ * We do not support user choice tracking for MISA
+ * extensions yet because, so far, we do not silently
+ * change MISA bits during realize() (RVG enables MISA
+ * bits but the user is warned about it).
+ */
 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 {
     int i;
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.

After this patch, disabling ifencei or icsr while enabling RVG will
result in error:

$ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false --nographic
qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
           riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
           riscv_has_ext(env, RVD) &&
           cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
+            !cpu->cfg.ext_icsr) {
+            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
+            return;
+        }
+
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
+            !cpu->cfg.ext_ifencei) {
+            error_setg(errp, "RVG requires Zifencei but user set "
+                       "Zifencei to false");
+            return;
+        }
+
         warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
-        cpu->cfg.ext_icsr = true;
-        cpu->cfg.ext_ifencei = true;
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
 
         env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
         env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
-- 
2.41.0

From: "liguang.zhang" <liguang.zhang@hexintek.com>

This patch fixes guest reboot errors when using KVM.

There are two issues when rebooting a guest using KVM
1. When the guest initiates a reboot the host is unable to stop the vcpu
2. When running a SMP guest the qemu monitor system_reset causes a vcpu crash

This can be fixed by clearing the CSR values at reset and syncing the
MPSTATE with the host.

Signed-off-by: liguang.zhang <liguang.zhang@hexintek.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230913091332.17355-1-18622748025@163.com>
[ Changes by AF
 - Fixup commit message
 - Fixup patch style
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm_riscv.h |  1 +
 target/riscv/kvm.c       | 44 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
                           uint64_t aplic_base, uint64_t imsic_base,
                           uint64_t guest_num);
 void riscv_kvm_aplic_request(void *opaque, int irq, int level);
+int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state);
 
 #endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void riscv_kvm_aplic_request(void *opaque, int irq, int level)
     kvm_set_irq(kvm_state, irq, !!level);
 }
 
+static bool cap_has_mp_state;
+
 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
                                  uint64_t idx)
 {
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
     return ret;
 }
 
+int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state)
+{
+    if (cap_has_mp_state) {
+        struct kvm_mp_state mp_state = {
+            .mp_state = state
+        };
+
+        int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
+        if (ret) {
+            fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n",
+                    __func__, ret, strerror(-ret));
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
 int kvm_arch_put_registers(CPUState *cs, int level)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
+    if (KVM_PUT_RESET_STATE == level) {
+        RISCVCPU *cpu = RISCV_CPU(cs);
+        if (cs->cpu_index == 0) {
+            ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE);
+        } else {
+            ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED);
+        }
+        if (ret) {
+            return ret;
+        }
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_default_type(MachineState *ms)
 
 int kvm_arch_init(MachineState *ms, KVMState *s)
 {
+    cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 {
     CPURISCVState *env = &cpu->env;
+    int i;
 
     if (!kvm_enabled()) {
         return;
     }
+    for (i = 0; i < 32; i++) {
+        env->gpr[i] = 0;
+    }
     env->pc = cpu->env.kernel_addr;
     env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
     env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
     env->satp = 0;
+    env->mie = 0;
+    env->stvec = 0;
+    env->sscratch = 0;
+    env->sepc = 0;
+    env->scause = 0;
+    env->stval = 0;
+    env->mip = 0;
 }
 
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

target/riscv/cpu.c needs to handle all possible accelerators (TCG and
KVM at this moment) during both init() and realize() time. This forces
us to resort to a lot of "if tcg" and "if kvm" throughout the code,
which isn't wrong, but can get cluttered over time. Splitting
acceleration specific code from cpu.c to its own file will help to
declutter the existing code and it will also make it easier to support
KVM/TCG only builds in the future.

We'll start by adding a new subdir called 'tcg' and a new file called
'tcg-cpu.c'. This file will be used to introduce a new accelerator class
for TCG acceleration in RISC-V, allowing us to center all TCG exclusive
code in its file instead of using 'cpu.c' for everything. This design is
inpired by the work Claudio Fontana did in x86 a few years ago in commit
f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using
AccelCPUClass").

To avoid moving too much code at once we'll start by adding the new file
and TCG AccelCPUClass declaration. The 'class_init' from the accel class
will init 'tcg_ops', relieving the common riscv_cpu_class_init() from
doing it.

'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having
to deal with moving code and files around right now. We'll focus on
decoupling the realize() logic first.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h           |  4 +++
 target/riscv/cpu.c           |  5 +---
 target/riscv/tcg/tcg-cpu.c   | 58 ++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build     |  2 ++
 target/riscv/tcg/meson.build |  2 ++
 5 files changed, 67 insertions(+), 4 deletions(-)
 create mode 100644 target/riscv/tcg/tcg-cpu.c
 create mode 100644 target/riscv/tcg/meson.build

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
 };
 
+/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
+#include "hw/core/tcg-cpu-ops.h"
+extern const struct TCGCPUOps riscv_tcg_ops;
+
 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
 };
 #endif
 
-#include "hw/core/tcg-cpu-ops.h"
-
-static const struct TCGCPUOps riscv_tcg_ops = {
+const struct TCGCPUOps riscv_tcg_ops = {
     .initialize = riscv_translate_init,
     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
     .restore_state_to_opc = riscv_restore_state_to_opc,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
 #endif
     cc->gdb_arch_name = riscv_gdb_arch_name;
     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
-    cc->tcg_ops = &riscv_tcg_ops;
 
     object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
                               cpu_set_mvendorid, NULL, NULL);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * riscv TCG cpu class initialization
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2017-2018 SiFive, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/accel.h"
+#include "hw/core/accel-cpu.h"
+
+static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
+{
+    /*
+     * All cpus use the same set of operations.
+     * riscv_tcg_ops is being imported from cpu.c for now.
+     */
+    cc->tcg_ops = &riscv_tcg_ops;
+}
+
+static void tcg_cpu_class_init(CPUClass *cc)
+{
+    cc->init_accel_cpu = tcg_cpu_init_ops;
+}
+
+static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+    AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+    acc->cpu_class_init = tcg_cpu_class_init;
+}
+
+static const TypeInfo tcg_cpu_accel_type_info = {
+    .name = ACCEL_CPU_NAME("tcg"),
+
+    .parent = TYPE_ACCEL_CPU,
+    .class_init = tcg_cpu_accel_class_init,
+    .abstract = true,
+};
+
+static void tcg_cpu_accel_register_types(void)
+{
+    type_register_static(&tcg_cpu_accel_type_info);
+}
+type_init(tcg_cpu_accel_register_types);
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'riscv-qmp-cmds.c',
 ))
 
+subdir('tcg')
+
 target_arch += {'riscv': riscv_ss}
 target_system_arch += {'riscv': riscv_system_ss}
diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/tcg/meson.build
@@ -XXX,XX +XXX,XX @@
+riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
+  'tcg-cpu.c'))
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
realize() path during the common riscv_cpu_realize(), making it a good
choice to start moving TCG exclusive code to tcg-cpu.c.

Rename it to tcg_cpu_realizefn() and assign it as a implementation of
accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
approach with KVM in the near future.

riscv_cpu_validate_set_extensions() is too big and with too many
dependencies to be moved in this same patch. We'll do that next.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230925175709.35696-3-dbarboza@ventanamicro.com>
[ Changes by AF:
 - Renames to fix build failures after rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 128 -----------------------------------
 target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++
 2 files changed, 133 insertions(+), 128 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "cpu.h"
 #include "cpu_vendorid.h"
-#include "pmu.h"
 #include "internals.h"
-#include "time_helper.h"
 #include "exec/exec-all.h"
 #include "qapi/error.h"
 #include "qapi/visitor.h"
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
     }
 }
 
-static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
-{
-    CPURISCVState *env = &cpu->env;
-    int priv_version = -1;
-
-    if (cpu->cfg.priv_spec) {
-        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
-            priv_version = PRIV_VERSION_1_12_0;
-        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
-            priv_version = PRIV_VERSION_1_11_0;
-        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
-            priv_version = PRIV_VERSION_1_10_0;
-        } else {
-            error_setg(errp,
-                       "Unsupported privilege spec version '%s'",
-                       cpu->cfg.priv_spec);
-            return;
-        }
-
-        env->priv_ver = priv_version;
-    }
-}
-
 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
     }
 }
 
-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
-{
-    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-    CPUClass *cc = CPU_CLASS(mcc);
-    CPURISCVState *env = &cpu->env;
-
-    /* Validate that MISA_MXL is set properly. */
-    switch (env->misa_mxl_max) {
-#ifdef TARGET_RISCV64
-    case MXL_RV64:
-    case MXL_RV128:
-        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
-        break;
-#endif
-    case MXL_RV32:
-        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
-    if (env->misa_mxl_max != env->misa_mxl) {
-        error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
-        return;
-    }
-}
-
 /*
  * Check consistency between chosen extensions while setting
  * cpu->cfg accordingly.
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
 #endif
 }
 
-static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
-{
-    if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
-        error_setg(errp, "H extension requires priv spec 1.12.0");
-        return;
-    }
-}
-
-static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
-{
-    RISCVCPU *cpu = RISCV_CPU(dev);
-    CPURISCVState *env = &cpu->env;
-    Error *local_err = NULL;
-
-    if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
-        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
-        return;
-    }
-
-    riscv_cpu_validate_misa_mxl(cpu, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-    riscv_cpu_validate_priv_spec(cpu, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-    riscv_cpu_validate_misa_priv(env, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
-        /*
-         * Enhanced PMP should only be available
-         * on harts with PMP support
-         */
-        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
-        return;
-    }
-
-    riscv_cpu_validate_set_extensions(cpu, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-#ifndef CONFIG_USER_ONLY
-    CPU(dev)->tcg_cflags |= CF_PCREL;
-
-    if (cpu->cfg.ext_sstc) {
-        riscv_timer_init(cpu);
-    }
-
-    if (cpu->cfg.pmu_num) {
-        if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
-            cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
-                                          riscv_pmu_timer_cb, cpu);
-        }
-     }
-#endif
-}
-
 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    if (tcg_enabled()) {
-        riscv_cpu_realize_tcg(dev, &local_err);
-        if (local_err != NULL) {
-            error_propagate(errp, local_err);
-            return;
-        }
-    }
-
     riscv_cpu_finalize_features(cpu, &local_err);
     if (local_err != NULL) {
         error_propagate(errp, local_err);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "exec/exec-all.h"
 #include "cpu.h"
+#include "pmu.h"
+#include "time_helper.h"
+#include "qapi/error.h"
 #include "qemu/accel.h"
 #include "hw/core/accel-cpu.h"
 
+
+static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
+{
+    if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
+        error_setg(errp, "H extension requires priv spec 1.12.0");
+        return;
+    }
+}
+
+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
+{
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+    CPUClass *cc = CPU_CLASS(mcc);
+    CPURISCVState *env = &cpu->env;
+
+    /* Validate that MISA_MXL is set properly. */
+    switch (env->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+    case MXL_RV64:
+    case MXL_RV128:
+        cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+        break;
+#endif
+    case MXL_RV32:
+        cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    if (env->misa_mxl_max != env->misa_mxl) {
+        error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
+        return;
+    }
+}
+
+static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
+{
+    CPURISCVState *env = &cpu->env;
+    int priv_version = -1;
+
+    if (cpu->cfg.priv_spec) {
+        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+            priv_version = PRIV_VERSION_1_12_0;
+        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+            priv_version = PRIV_VERSION_1_11_0;
+        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+            priv_version = PRIV_VERSION_1_10_0;
+        } else {
+            error_setg(errp,
+                       "Unsupported privilege spec version '%s'",
+                       cpu->cfg.priv_spec);
+            return;
+        }
+
+        env->priv_ver = priv_version;
+    }
+}
+
+/*
+ * We'll get here via the following path:
+ *
+ * riscv_cpu_realize()
+ *   -> cpu_exec_realizefn()
+ *      -> tcg_cpu_realize() (via accel_cpu_common_realize())
+ */
+static bool tcg_cpu_realize(CPUState *cs, Error **errp)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    Error *local_err = NULL;
+
+    if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
+        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
+        return false;
+    }
+
+    riscv_cpu_validate_misa_mxl(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return false;
+    }
+
+    riscv_cpu_validate_priv_spec(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return false;
+    }
+
+    riscv_cpu_validate_misa_priv(env, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return false;
+    }
+
+    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
+        /*
+         * Enhanced PMP should only be available
+         * on harts with PMP support
+         */
+        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+        return false;
+    }
+
+    riscv_cpu_validate_set_extensions(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return false;
+    }
+
+#ifndef CONFIG_USER_ONLY
+    CPU(cs)->tcg_cflags |= CF_PCREL;
+
+    if (cpu->cfg.ext_sstc) {
+        riscv_timer_init(cpu);
+    }
+
+    if (cpu->cfg.pmu_num) {
+        if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
+            cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+                                          riscv_pmu_timer_cb, cpu);
+        }
+     }
+#endif
+
+    return true;
+}
+
 static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
 
     acc->cpu_class_init = tcg_cpu_class_init;
+    acc->cpu_target_realize = tcg_cpu_realize;
 }
 
 static const TypeInfo tcg_cpu_accel_type_info = {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This function is the core of the RISC-V validations for TCG CPUs, and it
has a lot going on.

Functions in cpu.c were made public to allow them to be used by the KVM
accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
hard to move it to another file due to its dependency with isa_edata_arr[]
array, thus make it public and use it as is for now.

riscv_cpu_validate_set_extensions() is kept public because it's used by
csr.c in write_misa().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |   8 +-
 target/riscv/tcg/tcg-cpu.h |  27 +++
 target/riscv/cpu.c         | 361 +------------------------------------
 target/riscv/csr.c         |   1 +
 target/riscv/tcg/tcg-cpu.c | 357 ++++++++++++++++++++++++++++++++++++
 5 files changed, 397 insertions(+), 357 deletions(-)
 create mode 100644 target/riscv/tcg/tcg-cpu.h

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                         bool probe, uintptr_t retaddr);
 char *riscv_isa_string(RISCVCPU *cpu);
 void riscv_cpu_list(void);
-void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 
 #define cpu_list riscv_cpu_list
 #define cpu_mmu_index riscv_cpu_mmu_index
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
 #include "hw/core/tcg-cpu-ops.h"
 extern const struct TCGCPUOps riscv_tcg_ops;
 
+/* used by tcg/tcg-cpu.c*/
+void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
+bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
+bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
+int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
+
 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * riscv TCG cpu class initialization
+ *
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_TCG_CPU_H
+#define RISCV_TCG_CPU_H
+
+#include "cpu.h"
+
+void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
+
+#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
 /* Hash that stores user set extensions */
 static GHashTable *multi_ext_user_opts;
 
-static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
+bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
 {
     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
 
     return *ext_enabled;
 }
 
-static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
-                                   bool en)
+void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
 {
     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
 
     *ext_enabled = en;
 }
 
-static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 {
     int i;
 
@@ -XXX,XX +XXX,XX @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
     g_assert_not_reached();
 }
 
-static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
 {
     return g_hash_table_contains(multi_ext_user_opts,
                                  GUINT_TO_POINTER(ext_offset));
 }
 
-static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
-                                    bool value)
-{
-    CPURISCVState *env = &cpu->env;
-    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
-    int min_version;
-
-    if (prev_val == value) {
-        return;
-    }
-
-    if (cpu_cfg_ext_is_user_set(ext_offset)) {
-        return;
-    }
-
-    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
-        /* Do not enable it if priv_ver is older than min_version */
-        min_version = cpu_cfg_ext_get_min_version(ext_offset);
-        if (env->priv_ver < min_version) {
-            return;
-        }
-    }
-
-    isa_ext_update_enabled(cpu, ext_offset, value);
-}
-
 const char * const riscv_int_regnames[] = {
     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
     }
 }
 
-static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
-                                 Error **errp)
-{
-    if (!is_power_of_2(cfg->vlen)) {
-        error_setg(errp, "Vector extension VLEN must be power of 2");
-        return;
-    }
-    if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
-        error_setg(errp,
-                   "Vector extension implementation only supports VLEN "
-                   "in the range [128, %d]", RV_VLEN_MAX);
-        return;
-    }
-    if (!is_power_of_2(cfg->elen)) {
-        error_setg(errp, "Vector extension ELEN must be power of 2");
-        return;
-    }
-    if (cfg->elen > 64 || cfg->elen < 8) {
-        error_setg(errp,
-                   "Vector extension implementation only supports ELEN "
-                   "in the range [8, 64]");
-        return;
-    }
-    if (cfg->vext_spec) {
-        if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
-            env->vext_ver = VEXT_VERSION_1_00_0;
-        } else {
-            error_setg(errp, "Unsupported vector spec version '%s'",
-                       cfg->vext_spec);
-            return;
-        }
-    } else if (env->vext_ver == 0) {
-        qemu_log("vector version is not specified, "
-                 "use the default value v1.0\n");
-
-        env->vext_ver = VEXT_VERSION_1_00_0;
-    }
-}
-
-static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 {
     CPURISCVState *env = &cpu->env;
     int i;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
     }
 }
 
-/*
- * Check consistency between chosen extensions while setting
- * cpu->cfg accordingly.
- */
-void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-{
-    CPURISCVState *env = &cpu->env;
-    Error *local_err = NULL;
-
-    /* Do some ISA extension error checking */
-    if (riscv_has_ext(env, RVG) &&
-        !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
-          riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
-          riscv_has_ext(env, RVD) &&
-          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
-
-        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
-            !cpu->cfg.ext_icsr) {
-            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
-            return;
-        }
-
-        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
-            !cpu->cfg.ext_ifencei) {
-            error_setg(errp, "RVG requires Zifencei but user set "
-                       "Zifencei to false");
-            return;
-        }
-
-        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
-
-        env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
-        env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
-    }
-
-    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
-        error_setg(errp,
-                   "I and E extensions are incompatible");
-        return;
-    }
-
-    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
-        error_setg(errp,
-                   "Either I or E extension must be set");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
-        error_setg(errp,
-                   "Setting S extension without U extension is illegal");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
-        error_setg(errp,
-                   "H depends on an I base integer ISA with 32 x registers");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
-        error_setg(errp, "H extension implicitly requires S-mode");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
-        error_setg(errp, "F extension requires Zicsr");
-        return;
-    }
-
-    if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
-        error_setg(errp, "Zawrs extension requires A extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zfa extension requires F extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zfh) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
-    }
-
-    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zfbfmin extension depends on F extension");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "D extension requires F extension");
-        return;
-    }
-
-    if (riscv_has_ext(env, RVV)) {
-        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
-        if (local_err != NULL) {
-            error_propagate(errp, local_err);
-            return;
-        }
-
-        /* The V vector extension depends on the Zve64d extension */
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
-    }
-
-    /* The Zve64d extension depends on the Zve64f extension */
-    if (cpu->cfg.ext_zve64d) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
-    }
-
-    /* The Zve64f extension depends on the Zve32f extension */
-    if (cpu->cfg.ext_zve64f) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
-    }
-
-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
-        error_setg(errp, "Zve64d/V extensions require D extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfh) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
-    }
-
-    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
-        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
-        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
-        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
-        error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
-        error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
-        return;
-    }
-
-    /* Set the ISA extensions, checks should have happened above */
-    if (cpu->cfg.ext_zhinx) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-    }
-
-    if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
-        error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
-        return;
-    }
-
-    if (cpu->cfg.ext_zfinx) {
-        if (!cpu->cfg.ext_icsr) {
-            error_setg(errp, "Zfinx extension requires Zicsr");
-            return;
-        }
-        if (riscv_has_ext(env, RVF)) {
-            error_setg(errp,
-                       "Zfinx cannot be supported together with F extension");
-            return;
-        }
-    }
-
-    if (cpu->cfg.ext_zce) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
-        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
-            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
-        }
-    }
-
-    /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
-    if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
-        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
-            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
-        }
-        if (riscv_has_ext(env, RVD)) {
-            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
-        }
-    }
-
-    if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
-        error_setg(errp, "Zcf extension is only relevant to RV32");
-        return;
-    }
-
-    if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
-        error_setg(errp, "Zcf extension requires F extension");
-        return;
-    }
-
-    if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
-        error_setg(errp, "Zcd extension requires D extension");
-        return;
-    }
-
-    if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
-         cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
-        error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
-                         "extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
-        error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
-                         "Zcd extension");
-        return;
-    }
-
-    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
-        error_setg(errp, "Zcmt extension requires Zicsr extension");
-        return;
-    }
-
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
-    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
-         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
-        !cpu->cfg.ext_zve32f) {
-        error_setg(errp,
-                   "Vector crypto extensions require V or Zve* extensions");
-        return;
-    }
-
-    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
-        error_setg(
-            errp,
-            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
-        return;
-    }
-
-    if (cpu->cfg.ext_zk) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
-    }
-
-    if (cpu->cfg.ext_zkn) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
-    }
-
-    if (cpu->cfg.ext_zks) {
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
-    }
-
-    /*
-     * Disable isa extensions based on priv spec after we
-     * validated and set everything we need.
-     */
-    riscv_cpu_disable_priv_spec_isa_exts(cpu);
-}
-
 #ifndef CONFIG_USER_ONLY
 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
 {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/timer.h"
 #include "cpu.h"
+#include "tcg/tcg-cpu.h"
 #include "pmu.h"
 #include "time_helper.h"
 #include "exec/exec-all.h"
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "exec/exec-all.h"
+#include "tcg-cpu.h"
 #include "cpu.h"
 #include "pmu.h"
 #include "time_helper.h"
 #include "qapi/error.h"
 #include "qemu/accel.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
 #include "hw/core/accel-cpu.h"
 
 
+static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
+                                    bool value)
+{
+    CPURISCVState *env = &cpu->env;
+    bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
+    int min_version;
+
+    if (prev_val == value) {
+        return;
+    }
+
+    if (cpu_cfg_ext_is_user_set(ext_offset)) {
+        return;
+    }
+
+    if (value && env->priv_ver != PRIV_VERSION_LATEST) {
+        /* Do not enable it if priv_ver is older than min_version */
+        min_version = cpu_cfg_ext_get_min_version(ext_offset);
+        if (env->priv_ver < min_version) {
+            return;
+        }
+    }
+
+    isa_ext_update_enabled(cpu, ext_offset, value);
+}
+
 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
 {
     if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
     }
 }
 
+static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+                                 Error **errp)
+{
+    if (!is_power_of_2(cfg->vlen)) {
+        error_setg(errp, "Vector extension VLEN must be power of 2");
+        return;
+    }
+
+    if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
+        error_setg(errp,
+                   "Vector extension implementation only supports VLEN "
+                   "in the range [128, %d]", RV_VLEN_MAX);
+        return;
+    }
+
+    if (!is_power_of_2(cfg->elen)) {
+        error_setg(errp, "Vector extension ELEN must be power of 2");
+        return;
+    }
+
+    if (cfg->elen > 64 || cfg->elen < 8) {
+        error_setg(errp,
+                   "Vector extension implementation only supports ELEN "
+                   "in the range [8, 64]");
+        return;
+    }
+
+    if (cfg->vext_spec) {
+        if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
+            env->vext_ver = VEXT_VERSION_1_00_0;
+        } else {
+            error_setg(errp, "Unsupported vector spec version '%s'",
+                       cfg->vext_spec);
+            return;
+        }
+    } else if (env->vext_ver == 0) {
+        qemu_log("vector version is not specified, "
+                 "use the default value v1.0\n");
+
+        env->vext_ver = VEXT_VERSION_1_00_0;
+    }
+}
+
+/*
+ * Check consistency between chosen extensions while setting
+ * cpu->cfg accordingly.
+ */
+void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+{
+    CPURISCVState *env = &cpu->env;
+    Error *local_err = NULL;
+
+    /* Do some ISA extension error checking */
+    if (riscv_has_ext(env, RVG) &&
+        !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
+          riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
+          riscv_has_ext(env, RVD) &&
+          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
+            !cpu->cfg.ext_icsr) {
+            error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
+            return;
+        }
+
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
+            !cpu->cfg.ext_ifencei) {
+            error_setg(errp, "RVG requires Zifencei but user set "
+                       "Zifencei to false");
+            return;
+        }
+
+        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
+
+        env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
+        env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
+    }
+
+    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
+        error_setg(errp,
+                   "I and E extensions are incompatible");
+        return;
+    }
+
+    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
+        error_setg(errp,
+                   "Either I or E extension must be set");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
+        error_setg(errp,
+                   "Setting S extension without U extension is illegal");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
+        error_setg(errp,
+                   "H depends on an I base integer ISA with 32 x registers");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
+        error_setg(errp, "H extension implicitly requires S-mode");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
+        error_setg(errp, "F extension requires Zicsr");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
+        error_setg(errp, "Zawrs extension requires A extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "Zfa extension requires F extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zfh) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
+    }
+
+    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "Zfbfmin extension depends on F extension");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "D extension requires F extension");
+        return;
+    }
+
+    if (riscv_has_ext(env, RVV)) {
+        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
+            return;
+        }
+
+        /* The V vector extension depends on the Zve64d extension */
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
+    }
+
+    /* The Zve64d extension depends on the Zve64f extension */
+    if (cpu->cfg.ext_zve64d) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
+    }
+
+    /* The Zve64f extension depends on the Zve32f extension */
+    if (cpu->cfg.ext_zve64f) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
+    }
+
+    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
+        error_setg(errp, "Zve64d/V extensions require D extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
+        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfh) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
+    }
+
+    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
+        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
+        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
+        error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
+        return;
+    }
+
+    /* Set the ISA extensions, checks should have happened above */
+    if (cpu->cfg.ext_zhinx) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+    }
+
+    if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
+        error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
+        return;
+    }
+
+    if (cpu->cfg.ext_zfinx) {
+        if (!cpu->cfg.ext_icsr) {
+            error_setg(errp, "Zfinx extension requires Zicsr");
+            return;
+        }
+        if (riscv_has_ext(env, RVF)) {
+            error_setg(errp,
+                       "Zfinx cannot be supported together with F extension");
+            return;
+        }
+    }
+
+    if (cpu->cfg.ext_zce) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
+        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+        }
+    }
+
+    /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
+    if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+        if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+        }
+        if (riscv_has_ext(env, RVD)) {
+            cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
+        }
+    }
+
+    if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
+        error_setg(errp, "Zcf extension is only relevant to RV32");
+        return;
+    }
+
+    if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
+        error_setg(errp, "Zcf extension requires F extension");
+        return;
+    }
+
+    if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
+        error_setg(errp, "Zcd extension requires D extension");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
+         cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
+        error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
+                         "extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
+        error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
+                         "Zcd extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
+        error_setg(errp, "Zcmt extension requires Zicsr extension");
+        return;
+    }
+
+    /*
+     * In principle Zve*x would also suffice here, were they supported
+     * in qemu
+     */
+    if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
+         cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
+        !cpu->cfg.ext_zve32f) {
+        error_setg(errp,
+                   "Vector crypto extensions require V or Zve* extensions");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
+        error_setg(
+            errp,
+            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
+        return;
+    }
+
+    if (cpu->cfg.ext_zk) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
+    }
+
+    if (cpu->cfg.ext_zkn) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
+    }
+
+    if (cpu->cfg.ext_zks) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
+    }
+
+    /*
+     * Disable isa extensions based on priv spec after we
+     * validated and set everything we need.
+     */
+    riscv_cpu_disable_priv_spec_isa_exts(cpu);
+}
+
 /*
  * We'll get here via the following path:
  *
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  4 ---
 target/riscv/cpu.c         | 58 ------------------------------------
 target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++-
 3 files changed, 59 insertions(+), 63 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
 };
 
-/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
-#include "hw/core/tcg-cpu-ops.h"
-extern const struct TCGCPUOps riscv_tcg_ops;
-
 /* used by tcg/tcg-cpu.c*/
 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
 bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
     return env->pc;
 }
 
-static void riscv_cpu_synchronize_from_tb(CPUState *cs,
-                                          const TranslationBlock *tb)
-{
-    if (!(tb_cflags(tb) & CF_PCREL)) {
-        RISCVCPU *cpu = RISCV_CPU(cs);
-        CPURISCVState *env = &cpu->env;
-        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-
-        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
-
-        if (xl == MXL_RV32) {
-            env->pc = (int32_t) tb->pc;
-        } else {
-            env->pc = tb->pc;
-        }
-    }
-}
-
 static bool riscv_cpu_has_work(CPUState *cs)
 {
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs)
 #endif
 }
 
-static void riscv_restore_state_to_opc(CPUState *cs,
-                                       const TranslationBlock *tb,
-                                       const uint64_t *data)
-{
-    RISCVCPU *cpu = RISCV_CPU(cs);
-    CPURISCVState *env = &cpu->env;
-    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-    target_ulong pc;
-
-    if (tb_cflags(tb) & CF_PCREL) {
-        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
-    } else {
-        pc = data[0];
-    }
-
-    if (xl == MXL_RV32) {
-        env->pc = (int32_t)pc;
-    } else {
-        env->pc = pc;
-    }
-    env->bins = data[1];
-}
-
 static void riscv_cpu_reset_hold(Object *obj)
 {
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
 };
 #endif
 
-const struct TCGCPUOps riscv_tcg_ops = {
-    .initialize = riscv_translate_init,
-    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
-    .restore_state_to_opc = riscv_restore_state_to_opc,
-
-#ifndef CONFIG_USER_ONLY
-    .tlb_fill = riscv_cpu_tlb_fill,
-    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
-    .do_interrupt = riscv_cpu_do_interrupt,
-    .do_transaction_failed = riscv_cpu_do_transaction_failed,
-    .do_unaligned_access = riscv_cpu_do_unaligned_access,
-    .debug_excp_handler = riscv_cpu_debug_excp_handler,
-    .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
-    .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
-#endif /* !CONFIG_USER_ONLY */
-};
-
 static bool riscv_cpu_is_dynamic(Object *cpu_obj)
 {
     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/error-report.h"
 #include "qemu/log.h"
 #include "hw/core/accel-cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
+#include "tcg/tcg.h"
 
+static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+                                          const TranslationBlock *tb)
+{
+    if (!(tb_cflags(tb) & CF_PCREL)) {
+        RISCVCPU *cpu = RISCV_CPU(cs);
+        CPURISCVState *env = &cpu->env;
+        RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+        tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+
+        if (xl == MXL_RV32) {
+            env->pc = (int32_t) tb->pc;
+        } else {
+            env->pc = tb->pc;
+        }
+    }
+}
+
+static void riscv_restore_state_to_opc(CPUState *cs,
+                                       const TranslationBlock *tb,
+                                       const uint64_t *data)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+    target_ulong pc;
+
+    if (tb_cflags(tb) & CF_PCREL) {
+        pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+    } else {
+        pc = data[0];
+    }
+
+    if (xl == MXL_RV32) {
+        env->pc = (int32_t)pc;
+    } else {
+        env->pc = pc;
+    }
+    env->bins = data[1];
+}
+
+static const struct TCGCPUOps riscv_tcg_ops = {
+    .initialize = riscv_translate_init,
+    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+    .restore_state_to_opc = riscv_restore_state_to_opc,
+
+#ifndef CONFIG_USER_ONLY
+    .tlb_fill = riscv_cpu_tlb_fill,
+    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
+    .do_interrupt = riscv_cpu_do_interrupt,
+    .do_transaction_failed = riscv_cpu_do_transaction_failed,
+    .do_unaligned_access = riscv_cpu_do_unaligned_access,
+    .debug_excp_handler = riscv_cpu_debug_excp_handler,
+    .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
+    .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
 
 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
                                     bool value)
@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 {
     /*
      * All cpus use the same set of operations.
-     * riscv_tcg_ops is being imported from cpu.c for now.
      */
     cc->tcg_ops = &riscv_tcg_ops;
 }
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order then becomes:

riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()

In the near future riscv_cpu_post_init() will call the init() function
of the current accelerator, providing a hook for KVM and TCG accel
classes to change the init() process of the CPU.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++-----------
 1 file changed, 32 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_max_cpu_init(Object *obj)
     mlx = MXL_RV32;
 #endif
     set_misa(env, mlx, 0);
-    riscv_cpu_add_user_properties(obj);
-    riscv_init_max_cpu_extensions(obj);
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV64, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV128, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV32, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_host_cpu_init(Object *obj)
 #elif defined(TARGET_RISCV64)
     set_misa(env, MXL_RV64, 0);
 #endif
-    riscv_cpu_add_user_properties(obj);
 }
 #endif /* CONFIG_KVM */
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 }
 #endif /* CONFIG_USER_ONLY */
 
+static bool riscv_cpu_is_dynamic(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+}
+
+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+{
+    if (kvm_enabled() &&
+        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
+        return true;
+    }
+
+    return riscv_cpu_is_dynamic(cpu_obj);
+}
+
+static void riscv_cpu_post_init(Object *obj)
+{
+    if (riscv_cpu_has_user_properties(obj)) {
+        riscv_cpu_add_user_properties(obj);
+    }
+
+    if (riscv_cpu_has_max_extensions(obj)) {
+        riscv_init_max_cpu_extensions(obj);
+    }
+}
+
 static void riscv_cpu_init(Object *obj)
 {
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
 };
 #endif
 
-static bool riscv_cpu_is_dynamic(Object *cpu_obj)
-{
-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-}
-
 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
                               void *opaque, Error **errp)
 {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .instance_size = sizeof(RISCVCPU),
         .instance_align = __alignof(RISCVCPU),
         .instance_init = riscv_cpu_init,
+        .instance_post_init = riscv_cpu_post_init,
         .abstract = true,
         .class_size = sizeof(RISCVCPUClass),
         .class_init = riscv_cpu_class_init,
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This CPU only exists if we're compiling with KVM so move it to the kvm
specific file.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 15 ---------------
 target/riscv/kvm.c | 21 +++++++++++++++++++++
 2 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
 }
 #endif
 
-#if defined(CONFIG_KVM)
-static void riscv_host_cpu_init(Object *obj)
-{
-    CPURISCVState *env = &RISCV_CPU(obj)->env;
-#if defined(TARGET_RISCV32)
-    set_misa(env, MXL_RV32, 0);
-#elif defined(TARGET_RISCV64)
-    set_misa(env, MXL_RV64, 0);
-#endif
-}
-#endif /* CONFIG_KVM */
-
 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
     },
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,      riscv_max_cpu_init),
-#if defined(CONFIG_KVM)
-    DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
-#endif
 #if defined(TARGET_RISCV32)
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32,   rv32_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
 
     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 }
+
+static void riscv_host_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+
+#if defined(TARGET_RISCV32)
+    env->misa_mxl_max = env->misa_mxl = MXL_RV32;
+#elif defined(TARGET_RISCV64)
+    env->misa_mxl_max = env->misa_mxl = MXL_RV64;
+#endif
+}
+
+static const TypeInfo riscv_kvm_cpu_type_infos[] = {
+    {
+        .name = TYPE_RISCV_CPU_HOST,
+        .parent = TYPE_RISCV_CPU,
+        .instance_init = riscv_host_cpu_init,
+    }
+};
+
+DEFINE_TYPES(riscv_kvm_cpu_type_infos)
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll need to export these arrays to the accelerator classes in the next
patches. Mark them as 'const' now because they should not be modified at
runtime.

Note that 'riscv_cpu_options' will also be exported, but can't be marked
as 'const', because the properties are changed via
qdev_property_add_static().

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPUMultiExtConfig {
     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .enabled = _defval}
 
-static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
     MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 };
 
 /* These are experimental so mark with 'x-' */
-static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
     MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
     MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -XXX,XX +XXX,XX @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 }
 
 static void cpu_add_multi_ext_prop(Object *cpu_obj,
-                                   RISCVCPUMultiExtConfig *multi_cfg)
+                                   const RISCVCPUMultiExtConfig *multi_cfg)
 {
     object_property_add(cpu_obj, multi_cfg->name, "bool",
                         cpu_get_multi_ext_cfg,
@@ -XXX,XX +XXX,XX @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
 }
 
 static void riscv_cpu_add_multiext_prop_array(Object *obj,
-                                              RISCVCPUMultiExtConfig *array)
+                                        const RISCVCPUMultiExtConfig *array)
 {
+    const RISCVCPUMultiExtConfig *prop;
+
     g_assert(array);
 
-    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+    for (prop = array; prop && prop->name; prop++) {
         cpu_add_multi_ext_prop(obj, prop);
     }
 }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
 }
 
 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-                                                 RISCVCPUMultiExtConfig *array)
+                                        const RISCVCPUMultiExtConfig *array)
 {
+    const RISCVCPUMultiExtConfig *prop;
+
     g_assert(array);
 
-    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+    for (prop = array; prop && prop->name; prop++) {
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 }
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    RISCVCPUMultiExtConfig *prop;
+    const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll introduce the KVM accelerator class with a 'cpu_instance_init'
implementation that is going to be invoked during the common
riscv_cpu_post_init() (via accel_cpu_instance_init()). This
instance_init will execute KVM exclusive code that TCG doesn't care
about, such as adding KVM specific properties, initing registers using a
KVM scratch CPU and so on.

The core of the forementioned cpu_instance_init impl is the current
riscv_cpu_add_kvm_properties() that is being used by the common code via
riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together
will all the relevant artifacts, exporting and renaming it to
kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now.

To make this work we'll need to export riscv_cpu_extensions,
riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as
well. The TCG accelerator will also need to access those in the near
future so this export will benefit us in the long run.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       | 14 +++++++
 target/riscv/kvm_riscv.h |  3 --
 target/riscv/cpu.c       | 85 +++-------------------------------------
 target/riscv/kvm.c       | 68 +++++++++++++++++++++++++++++++-
 4 files changed, 86 insertions(+), 84 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/core/cpu.h"
 #include "hw/registerfields.h"
+#include "hw/qdev-properties.h"
 #include "exec/cpu-defs.h"
 #include "qemu/cpu-float.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
 
+typedef struct RISCVCPUMultiExtConfig {
+    const char *name;
+    uint32_t offset;
+    bool enabled;
+} RISCVCPUMultiExtConfig;
+
+extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+extern Property riscv_cpu_options[];
+
+void riscv_cpu_add_misa_properties(Object *cpu_obj);
+
 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 #ifndef QEMU_KVM_RISCV_H
 #define QEMU_KVM_RISCV_H
 
-/* Temporarily implemented in cpu.c */
 void kvm_riscv_cpu_add_kvm_properties(Object *obj);
-
-void kvm_riscv_init_user_properties(Object *cpu_obj);
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
  * change MISA bits during realize() (RVG enables MISA
  * bits but the user is warned about it).
  */
-static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+void riscv_cpu_add_misa_properties(Object *cpu_obj)
 {
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
     }
 }
 
-typedef struct RISCVCPUMultiExtConfig {
-    const char *name;
-    uint32_t offset;
-    bool enabled;
-} RISCVCPUMultiExtConfig;
-
 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .enabled = _defval}
 
-static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
     MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 };
 
 /* These are experimental so mark with 'x-' */
-static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
     MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
     MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static Property riscv_cpu_options[] = {
+Property riscv_cpu_options[] = {
     DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
 
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
     }
 }
 
-#ifdef CONFIG_KVM
-static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
-                                    const char *name,
-                                    void *opaque, Error **errp)
-{
-    const char *propname = opaque;
-    bool value;
-
-    if (!visit_type_bool(v, name, &value, errp)) {
-        return;
-    }
-
-    if (value) {
-        error_setg(errp, "extension %s is not available with KVM",
-                   propname);
-    }
-}
-
-static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
-{
-    /* Check if KVM created the property already */
-    if (object_property_find(obj, prop_name)) {
-        return;
-    }
-
-    /*
-     * Set the default to disabled for every extension
-     * unknown to KVM and error out if the user attempts
-     * to enable any of them.
-     */
-    object_property_add(obj, prop_name, "bool",
-                        NULL, cpu_set_cfg_unavailable,
-                        NULL, (void *)prop_name);
-}
-
-static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-                                        const RISCVCPUMultiExtConfig *array)
-{
-    const RISCVCPUMultiExtConfig *prop;
-
-    g_assert(array);
-
-    for (prop = array; prop && prop->name; prop++) {
-        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
-    }
-}
-
-void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-{
-    Property *prop;
-    DeviceState *dev = DEVICE(obj);
-
-    kvm_riscv_init_user_properties(obj);
-    riscv_cpu_add_misa_properties(obj);
-
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
-
-    for (prop = riscv_cpu_options; prop && prop->name; prop++) {
-        /* Check if KVM created the property already */
-        if (object_property_find(obj, prop->name)) {
-            continue;
-        }
-        qdev_property_add_static(dev, prop);
-    }
-}
-#endif
-
 /*
  * Add CPU properties with user-facing flags.
  *
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
     }
 }
 
+static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
+                                    const char *name,
+                                    void *opaque, Error **errp)
+{
+    const char *propname = opaque;
+    bool value;
+
+    if (!visit_type_bool(v, name, &value, errp)) {
+        return;
+    }
+
+    if (value) {
+        error_setg(errp, "extension %s is not available with KVM",
+                   propname);
+    }
+}
+
+static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
+{
+    /* Check if KVM created the property already */
+    if (object_property_find(obj, prop_name)) {
+        return;
+    }
+
+    /*
+     * Set the default to disabled for every extension
+     * unknown to KVM and error out if the user attempts
+     * to enable any of them.
+     */
+    object_property_add(obj, prop_name, "bool",
+                        NULL, cpu_set_cfg_unavailable,
+                        NULL, (void *)prop_name);
+}
+
+static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
+                                        const RISCVCPUMultiExtConfig *array)
+{
+    const RISCVCPUMultiExtConfig *prop;
+
+    g_assert(array);
+
+    for (prop = array; prop && prop->name; prop++) {
+        riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+    }
+}
+
 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
 {
     int i;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     }
 }
 
-void kvm_riscv_init_user_properties(Object *cpu_obj)
+static void riscv_init_user_properties(Object *cpu_obj)
 {
     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
     KVMScratchCPU kvmcpu;
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 }
 
+void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+{
+    DeviceState *dev = DEVICE(obj);
+
+    riscv_init_user_properties(obj);
+    riscv_cpu_add_misa_properties(obj);
+
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
+
+    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+        /* Check if KVM created the property already */
+        if (object_property_find(obj, prop->name)) {
+            continue;
+        }
+        qdev_property_add_static(dev, prop);
+    }
+}
+
 static void riscv_host_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This function is used for both accelerators. Make it public, and call it
from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
split KVM specific code for the KVM accelerator class in the next patch.

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 extern Property riscv_cpu_options[];
 
 void riscv_cpu_add_misa_properties(Object *cpu_obj);
+void riscv_add_satp_mode_properties(Object *obj);
 
 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
     satp_map->init |= 1 << satp;
 }
 
-static void riscv_add_satp_mode_properties(Object *obj)
+void riscv_add_satp_mode_properties(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
 static void riscv_cpu_add_user_properties(Object *obj)
 {
 #ifndef CONFIG_USER_ONLY
-    riscv_add_satp_mode_properties(obj);
-
     if (kvm_enabled()) {
         kvm_riscv_cpu_add_kvm_properties(obj);
         return;
     }
+    riscv_add_satp_mode_properties(obj);
 #endif
 
     riscv_cpu_add_misa_properties(obj);
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
     DeviceState *dev = DEVICE(obj);
 
     riscv_init_user_properties(obj);
+    riscv_add_satp_mode_properties(obj);
     riscv_cpu_add_misa_properties(obj);
 
     riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This file is not needed for some time now. Both kvm_riscv_reset_vcpu()
and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are
wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out
in non-KVM builds.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm-stub.c  | 30 ------------------------------
 target/riscv/meson.build |  2 +-
 2 files changed, 1 insertion(+), 31 deletions(-)
 delete mode 100644 target/riscv/kvm-stub.c

diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/riscv/kvm-stub.c
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-/*
- * QEMU KVM RISC-V specific function stubs
- *
- * Copyright (c) 2020 Huawei Technologies Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include "qemu/osdep.h"
-#include "cpu.h"
-#include "kvm_riscv.h"
-
-void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-{
-    abort();
-}
-
-void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
-{
-    abort();
-}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'zce_helper.c',
   'vcrypto_helper.c'
 ))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 riscv_system_ss = ss.source_set()
 riscv_system_ss.add(files(
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add a KVM accelerator class like we did with TCG. The difference is
that, at least for now, we won't be using a realize() implementation for
this accelerator.

We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change
riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go
through the 'cpu_instance_init' impl of the current acceleration (if
available) and execute it. The end result is that the KVM initial setup,
i.e. starting registers and adding its specific properties, will be done
via this hook.

Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid
calling riscv_cpu_add_user_properties() when running KVM. We'll remove
this condition when the TCG accel class get its own 'cpu_instance_init'
implementation.

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -XXX,XX +XXX,XX @@
 #ifndef QEMU_KVM_RISCV_H
 #define QEMU_KVM_RISCV_H
 
-void kvm_riscv_cpu_add_kvm_properties(Object *obj);
 void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_user_properties(Object *cpu_obj)
 
 static void riscv_cpu_post_init(Object *obj)
 {
-    if (riscv_cpu_has_user_properties(obj)) {
+    accel_cpu_instance_init(CPU(obj));
+
+    if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
         riscv_cpu_add_user_properties(obj);
     }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
 static void riscv_cpu_add_user_properties(Object *obj)
 {
 #ifndef CONFIG_USER_ONLY
-    if (kvm_enabled()) {
-        kvm_riscv_cpu_add_kvm_properties(obj);
-        return;
-    }
     riscv_add_satp_mode_properties(obj);
 #endif
 
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm_int.h"
 #include "cpu.h"
 #include "trace.h"
+#include "hw/core/accel-cpu.h"
 #include "hw/pci/pci.h"
 #include "exec/memattrs.h"
 #include "exec/address-spaces.h"
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 }
 
-void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+static void kvm_cpu_instance_init(CPUState *cs)
 {
+    Object *obj = OBJECT(RISCV_CPU(cs));
     DeviceState *dev = DEVICE(obj);
 
     riscv_init_user_properties(obj);
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
     riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
 
     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
-        /* Check if KVM created the property already */
+        /* Check if we have a specific KVM handler for the option */
         if (object_property_find(obj, prop->name)) {
             continue;
         }
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
     }
 }
 
+static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+    AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+    acc->cpu_instance_init = kvm_cpu_instance_init;
+}
+
+static const TypeInfo kvm_cpu_accel_type_info = {
+    .name = ACCEL_CPU_NAME("kvm"),
+
+    .parent = TYPE_ACCEL_CPU,
+    .class_init = kvm_cpu_accel_class_init,
+    .abstract = true,
+};
+static void kvm_cpu_accel_register_types(void)
+{
+    type_register_static(&kvm_cpu_accel_type_info);
+}
+type_init(kvm_cpu_accel_register_types);
+
 static void riscv_host_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --disable-tcg.

Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/{ => kvm}/kvm_riscv.h    | 0
 hw/intc/riscv_aplic.c                 | 2 +-
 hw/riscv/virt.c                       | 2 +-
 target/riscv/cpu.c                    | 2 +-
 target/riscv/{kvm.c => kvm/kvm-cpu.c} | 0
 target/riscv/kvm/meson.build          | 1 +
 target/riscv/meson.build              | 2 +-
 7 files changed, 5 insertions(+), 4 deletions(-)
 rename target/riscv/{ => kvm}/kvm_riscv.h (100%)
 rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (100%)
 create mode 100644 target/riscv/kvm/meson.build

diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h
similarity index 100%
rename from target/riscv/kvm_riscv.h
rename to target/riscv/kvm/kvm_riscv.h
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
 #include "migration/vmstate.h"
 
 #define APLIC_MAX_IDC                  (1UL << 14)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
 #include "hw/intc/riscv_aclint.h"
 #include "hw/intc/riscv_aplic.h"
 #include "hw/intc/riscv_imsic.h"
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "fpu/softfloat-helpers.h"
 #include "sysemu/kvm.h"
 #include "sysemu/tcg.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
 #include "tcg/tcg.h"
 
 /* RISC-V CPU definitions */
diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c
similarity index 100%
rename from target/riscv/kvm.c
rename to target/riscv/kvm/kvm-cpu.c
diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/kvm/meson.build
@@ -0,0 +1 @@
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
   'zce_helper.c',
   'vcrypto_helper.c'
 ))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 riscv_system_ss = ss.source_set()
 riscv_system_ss.add(files(
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
 ))
 
 subdir('tcg')
+subdir('kvm')
 
 target_arch += {'riscv': riscv_ss}
 target_system_arch += {'riscv': riscv_system_ss}
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

riscv_cpu_add_misa_properties() is being used to fill the missing KVM
MISA properties but it is a TCG helper that was adapted to do so. We'll
move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
the remaining MISA properties on its own.

Do not use riscv_cpu_add_misa_properties(). Let's create a new array
with all available MISA bits we support that can be read by KVM. The
array is zero terminate to allow us to iterate through it without
knowing its size.

Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM
MISA properties as usual and then use this array to add any missing MISA
properties with the riscv_cpu_add_kvm_unavail_prop() helper.

Note that we're creating misa_bits[], and not using the existing
'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa
related functions and it doesn't have all MISA bits we support. Commit
0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the
full context.

While we're at it, move both satp and the multi-letter extension
properties to kvm_riscv_add_cpu_user_properties() as well.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 ++-
 target/riscv/cpu.c         |  2 ++
 target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++--------
 3 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define RV(x) ((target_ulong)1 << (x - 'A'))
 
 /*
- * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[]
+ * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
  * when adding new MISA bits here.
  */
 #define RVI RV('I')
@@ -XXX,XX +XXX,XX @@
 #define RVJ RV('J')
 #define RVG RV('G')
 
+extern const uint32_t misa_bits[];
 const char *riscv_get_misa_ext_name(uint32_t bit);
 const char *riscv_get_misa_ext_description(uint32_t bit);
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 
 /* RISC-V CPU definitions */
 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
+const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
+                              RVC, RVS, RVU, RVH, RVJ, RVG, 0};
 
 struct isa_ext_data {
     const char *name;
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
 {
     int i;
 
+    riscv_add_satp_mode_properties(cpu_obj);
+
     for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) {
         KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i];
         int bit = misa_cfg->offset;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
                                         misa_cfg->description);
     }
 
+    for (i = 0; misa_bits[i] != 0; i++) {
+        const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]);
+        riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name);
+    }
+
     for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
         KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i];
 
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
     object_property_add(cpu_obj, "cboz_blocksize", "uint16",
                         NULL, kvm_cpu_set_cbomz_blksize,
                         NULL, &kvm_cboz_blocksize);
+
+    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions);
+    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts);
 }
 
 static int kvm_riscv_get_regs_core(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     }
 }
 
-static void riscv_init_user_properties(Object *cpu_obj)
+static void riscv_init_kvm_registers(Object *cpu_obj)
 {
     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
     KVMScratchCPU kvmcpu;
@@ -XXX,XX +XXX,XX @@ static void riscv_init_user_properties(Object *cpu_obj)
         return;
     }
 
-    kvm_riscv_add_cpu_user_properties(cpu_obj);
     kvm_riscv_init_machine_ids(cpu, &kvmcpu);
     kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
     kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
@@ -XXX,XX +XXX,XX @@ static void kvm_cpu_instance_init(CPUState *cs)
     Object *obj = OBJECT(RISCV_CPU(cs));
     DeviceState *dev = DEVICE(obj);
 
-    riscv_init_user_properties(obj);
-    riscv_add_satp_mode_properties(obj);
-    riscv_cpu_add_misa_properties(obj);
+    riscv_init_kvm_registers(obj);
 
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
-    riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
+    kvm_riscv_add_cpu_user_properties(obj);
 
     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
         /* Check if we have a specific KVM handler for the option */
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
patch and set_misa() needs to be usable from there.

Rename it to riscv_cpu_set_misa() and make it public.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  1 +
 target/riscv/cpu.c | 34 ++++++++++++++++++----------------
 2 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
 bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
 
 typedef struct RISCVCPUMultiExtConfig {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
     }
 }
 
-static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
 {
     env->misa_mxl_max = env->misa_mxl = mxl;
     env->misa_ext_mask = env->misa_ext = ext;
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
 #if defined(TARGET_RISCV32)
-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #elif defined(TARGET_RISCV64)
-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #endif
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void riscv_max_cpu_init(Object *obj)
 #ifdef TARGET_RISCV32
     mlx = MXL_RV32;
 #endif
-    set_misa(env, mlx, 0);
+    riscv_cpu_set_misa(env, mlx, 0);
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, MXL_RV64, 0);
+    riscv_cpu_set_misa(env, MXL_RV64, 0);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    riscv_cpu_set_misa(env, MXL_RV64,
+                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
+    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
     env->priv_ver = PRIV_VERSION_1_11_0;
 
     cpu->cfg.ext_zfa = true;
@@ -XXX,XX +XXX,XX @@ static void rv64_veyron_v1_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
+    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
     env->priv_ver = PRIV_VERSION_1_12_0;
 
     /* Enable ISA extensions */
@@ -XXX,XX +XXX,XX @@ static void rv128_base_cpu_init(Object *obj)
     }
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, MXL_RV128, 0);
+    riscv_cpu_set_misa(env, MXL_RV128, 0);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, MXL_RV32, 0);
+    riscv_cpu_set_misa(env, MXL_RV32, 0);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32,
+                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
     env->priv_ver = PRIV_VERSION_1_11_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
+    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
accelerator. It'll be called from within riscv_cpu_post_init(), via
accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
preserve behavior, the implementation will be similar to what
riscv_cpu_post_init() already does.

In this patch we'll move riscv_cpu_add_user_properties() and
riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
All multi-extension properties code was moved. The 'multi_ext_user_opts'
hash table was also moved to tcg-cpu.c since it's a TCG only structure,
meaning that we won't have to worry about initializing a TCG hash table
when running a KVM CPU anymore.

riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
much code it requires to be moved at the same time. We'll do that in the
next patch.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |   1 -
 target/riscv/cpu.c         | 150 -------------------------------------
 target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+), 151 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ enum riscv_pmu_event_idx {
 
 /* used by tcg/tcg-cpu.c*/
 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
 };
 
-/* Hash that stores user set extensions */
-static GHashTable *multi_ext_user_opts;
-
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
 {
     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
@@ -XXX,XX +XXX,XX @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
     g_assert_not_reached();
 }
 
-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
-{
-    return g_hash_table_contains(multi_ext_user_opts,
-                                 GUINT_TO_POINTER(ext_offset));
-}
-
 const char * const riscv_int_regnames[] = {
     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
@@ -XXX,XX +XXX,XX @@ static const char * const riscv_intr_names[] = {
     "reserved"
 };
 
-static void riscv_cpu_add_user_properties(Object *obj);
-static void riscv_init_max_cpu_extensions(Object *obj);
-
 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 {
     if (async) {
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
 }
 
-static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
-{
-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
-}
-
-static bool riscv_cpu_has_user_properties(Object *cpu_obj)
-{
-    if (kvm_enabled() &&
-        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
-        return true;
-    }
-
-    return riscv_cpu_is_dynamic(cpu_obj);
-}
-
 static void riscv_cpu_post_init(Object *obj)
 {
     accel_cpu_instance_init(CPU(obj));
-
-    if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
-        riscv_cpu_add_user_properties(obj);
-    }
-
-    if (riscv_cpu_has_max_extensions(obj)) {
-        riscv_init_max_cpu_extensions(obj);
-    }
 }
 
 static void riscv_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
 #endif /* CONFIG_USER_ONLY */
-
-    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
 }
 
 typedef struct RISCVCPUMisaExtConfig {
@@ -XXX,XX +XXX,XX @@ Property riscv_cpu_options[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
-                                  void *opaque, Error **errp)
-{
-    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
-    bool value;
-
-    if (!visit_type_bool(v, name, &value, errp)) {
-        return;
-    }
-
-    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
-
-    g_hash_table_insert(multi_ext_user_opts,
-                        GUINT_TO_POINTER(multi_ext_cfg->offset),
-                        (gpointer)value);
-}
-
-static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
-                                  void *opaque, Error **errp)
-{
-    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
-    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
-
-    visit_type_bool(v, name, &value, errp);
-}
-
-static void cpu_add_multi_ext_prop(Object *cpu_obj,
-                                   const RISCVCPUMultiExtConfig *multi_cfg)
-{
-    object_property_add(cpu_obj, multi_cfg->name, "bool",
-                        cpu_get_multi_ext_cfg,
-                        cpu_set_multi_ext_cfg,
-                        NULL, (void *)multi_cfg);
-
-    /*
-     * Set def val directly instead of using
-     * object_property_set_bool() to save the set()
-     * callback hash for user inputs.
-     */
-    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
-                           multi_cfg->enabled);
-}
-
-static void riscv_cpu_add_multiext_prop_array(Object *obj,
-                                        const RISCVCPUMultiExtConfig *array)
-{
-    const RISCVCPUMultiExtConfig *prop;
-
-    g_assert(array);
-
-    for (prop = array; prop && prop->name; prop++) {
-        cpu_add_multi_ext_prop(obj, prop);
-    }
-}
-
-/*
- * Add CPU properties with user-facing flags.
- *
- * This will overwrite existing env->misa_ext values with the
- * defaults set via riscv_cpu_add_misa_properties().
- */
-static void riscv_cpu_add_user_properties(Object *obj)
-{
-#ifndef CONFIG_USER_ONLY
-    riscv_add_satp_mode_properties(obj);
-#endif
-
-    riscv_cpu_add_misa_properties(obj);
-
-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
-    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
-
-    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
-        qdev_property_add_static(DEVICE(obj), prop);
-    }
-}
-
-/*
- * The 'max' type CPU will have all possible ratified
- * non-vendor extensions enabled.
- */
-static void riscv_init_max_cpu_extensions(Object *obj)
-{
-    RISCVCPU *cpu = RISCV_CPU(obj);
-    CPURISCVState *env = &cpu->env;
-    const RISCVCPUMultiExtConfig *prop;
-
-    /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-
-    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-        isa_ext_update_enabled(cpu, prop->offset, true);
-    }
-
-    /* set vector version */
-    env->vext_ver = VEXT_VERSION_1_00_0;
-
-    /* Zfinx is not compatible with F. Disable it */
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
-
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
-    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
-
-    if (env->misa_mxl != MXL_RV32) {
-        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
-    }
-}
-
 static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "pmu.h"
 #include "time_helper.h"
 #include "qapi/error.h"
+#include "qapi/visitor.h"
 #include "qemu/accel.h"
 #include "qemu/error-report.h"
 #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/core/tcg-cpu-ops.h"
 #include "tcg/tcg.h"
 
+/* Hash that stores user set extensions */
+static GHashTable *multi_ext_user_opts;
+
+static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+{
+    return g_hash_table_contains(multi_ext_user_opts,
+                                 GUINT_TO_POINTER(ext_offset));
+}
+
 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
                                           const TranslationBlock *tb)
 {
@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
     return true;
 }
 
+static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                  void *opaque, Error **errp)
+{
+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+    bool value;
+
+    if (!visit_type_bool(v, name, &value, errp)) {
+        return;
+    }
+
+    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
+
+    g_hash_table_insert(multi_ext_user_opts,
+                        GUINT_TO_POINTER(multi_ext_cfg->offset),
+                        (gpointer)value);
+}
+
+static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                  void *opaque, Error **errp)
+{
+    const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+    bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
+
+    visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_add_multi_ext_prop(Object *cpu_obj,
+                                   const RISCVCPUMultiExtConfig *multi_cfg)
+{
+    object_property_add(cpu_obj, multi_cfg->name, "bool",
+                        cpu_get_multi_ext_cfg,
+                        cpu_set_multi_ext_cfg,
+                        NULL, (void *)multi_cfg);
+
+    /*
+     * Set def val directly instead of using
+     * object_property_set_bool() to save the set()
+     * callback hash for user inputs.
+     */
+    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
+                           multi_cfg->enabled);
+}
+
+static void riscv_cpu_add_multiext_prop_array(Object *obj,
+                                        const RISCVCPUMultiExtConfig *array)
+{
+    const RISCVCPUMultiExtConfig *prop;
+
+    g_assert(array);
+
+    for (prop = array; prop && prop->name; prop++) {
+        cpu_add_multi_ext_prop(obj, prop);
+    }
+}
+
+/*
+ * Add CPU properties with user-facing flags.
+ *
+ * This will overwrite existing env->misa_ext values with the
+ * defaults set via riscv_cpu_add_misa_properties().
+ */
+static void riscv_cpu_add_user_properties(Object *obj)
+{
+#ifndef CONFIG_USER_ONLY
+    riscv_add_satp_mode_properties(obj);
+#endif
+
+    riscv_cpu_add_misa_properties(obj);
+
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
+
+    for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+        qdev_property_add_static(DEVICE(obj), prop);
+    }
+}
+
+/*
+ * The 'max' type CPU will have all possible ratified
+ * non-vendor extensions enabled.
+ */
+static void riscv_init_max_cpu_extensions(Object *obj)
+{
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    const RISCVCPUMultiExtConfig *prop;
+
+    /* Enable RVG, RVJ and RVV that are disabled by default */
+    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+
+    for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+        isa_ext_update_enabled(cpu, prop->offset, true);
+    }
+
+    /* set vector version */
+    env->vext_ver = VEXT_VERSION_1_00_0;
+
+    /* Zfinx is not compatible with F. Disable it */
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
+
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
+    isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
+
+    if (env->misa_mxl != MXL_RV32) {
+        isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
+    }
+}
+
+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+}
+
+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static void tcg_cpu_instance_init(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    Object *obj = OBJECT(cpu);
+
+    if (riscv_cpu_has_user_properties(obj)) {
+        multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+        riscv_cpu_add_user_properties(obj);
+    }
+
+    if (riscv_cpu_has_max_extensions(obj)) {
+        riscv_init_max_cpu_extensions(obj);
+    }
+}
+
 static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
 
     acc->cpu_class_init = tcg_cpu_class_init;
+    acc->cpu_instance_init = tcg_cpu_instance_init;
     acc->cpu_target_realize = tcg_cpu_realize;
 }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The array isn't marked as 'const' because we're initializing their
elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
fields.

In a closer look we can see that we're not using these 2 fields after
creating the MISA properties. And we can create the properties by using
riscv_get_misa_ext_name() and riscv_get_misa_ext_description()
directly.

Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig
and make misa_ext_cfgs[] a const array.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
 }
 
 typedef struct RISCVCPUMisaExtConfig {
-    const char *name;
-    const char *description;
     target_ulong misa_bit;
     bool enabled;
 } RISCVCPUMisaExtConfig;
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
 #define MISA_CFG(_bit, _enabled) \
     {.misa_bit = _bit, .enabled = _enabled}
 
-static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
     MISA_CFG(RVA, true),
     MISA_CFG(RVC, true),
     MISA_CFG(RVD, true),
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_add_misa_properties(Object *cpu_obj)
     int i;
 
     for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
-        RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
         int bit = misa_cfg->misa_bit;
-
-        misa_cfg->name = riscv_get_misa_ext_name(bit);
-        misa_cfg->description = riscv_get_misa_ext_description(bit);
+        const char *name = riscv_get_misa_ext_name(bit);
+        const char *desc = riscv_get_misa_ext_description(bit);
 
         /* Check if KVM already created the property */
-        if (object_property_find(cpu_obj, misa_cfg->name)) {
+        if (object_property_find(cpu_obj, name)) {
             continue;
         }
 
-        object_property_add(cpu_obj, misa_cfg->name, "bool",
+        object_property_add(cpu_obj, name, "bool",
                             cpu_get_misa_ext_cfg,
                             cpu_set_misa_ext_cfg,
                             NULL, (void *)misa_cfg);
-        object_property_set_description(cpu_obj, misa_cfg->name,
-                                        misa_cfg->description);
-        object_property_set_bool(cpu_obj, misa_cfg->name,
-                                 misa_cfg->enabled, NULL);
+        object_property_set_description(cpu_obj, name, desc);
+        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
     }
 }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

All code related to MISA TCG properties is also moved.

At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
properties handling is done in kvm-cpu.c.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 -
 target/riscv/cpu.c         | 90 --------------------------------------
 target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 90 insertions(+), 91 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 extern Property riscv_cpu_options[];
 
-void riscv_cpu_add_misa_properties(Object *cpu_obj);
 void riscv_add_satp_mode_properties(Object *obj);
 
 /* CSR function table */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
 #endif /* CONFIG_USER_ONLY */
 }
 
-typedef struct RISCVCPUMisaExtConfig {
-    target_ulong misa_bit;
-    bool enabled;
-} RISCVCPUMisaExtConfig;
-
-static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
-                                 void *opaque, Error **errp)
-{
-    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
-    target_ulong misa_bit = misa_ext_cfg->misa_bit;
-    RISCVCPU *cpu = RISCV_CPU(obj);
-    CPURISCVState *env = &cpu->env;
-    bool value;
-
-    if (!visit_type_bool(v, name, &value, errp)) {
-        return;
-    }
-
-    if (value) {
-        env->misa_ext |= misa_bit;
-        env->misa_ext_mask |= misa_bit;
-    } else {
-        env->misa_ext &= ~misa_bit;
-        env->misa_ext_mask &= ~misa_bit;
-    }
-}
-
-static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
-                                 void *opaque, Error **errp)
-{
-    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
-    target_ulong misa_bit = misa_ext_cfg->misa_bit;
-    RISCVCPU *cpu = RISCV_CPU(obj);
-    CPURISCVState *env = &cpu->env;
-    bool value;
-
-    value = env->misa_ext & misa_bit;
-
-    visit_type_bool(v, name, &value, errp);
-}
-
 typedef struct misa_ext_info {
     const char *name;
     const char *description;
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
     return val;
 }
 
-#define MISA_CFG(_bit, _enabled) \
-    {.misa_bit = _bit, .enabled = _enabled}
-
-static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
-    MISA_CFG(RVA, true),
-    MISA_CFG(RVC, true),
-    MISA_CFG(RVD, true),
-    MISA_CFG(RVF, true),
-    MISA_CFG(RVI, true),
-    MISA_CFG(RVE, false),
-    MISA_CFG(RVM, true),
-    MISA_CFG(RVS, true),
-    MISA_CFG(RVU, true),
-    MISA_CFG(RVH, true),
-    MISA_CFG(RVJ, false),
-    MISA_CFG(RVV, false),
-    MISA_CFG(RVG, false),
-};
-
-/*
- * We do not support user choice tracking for MISA
- * extensions yet because, so far, we do not silently
- * change MISA bits during realize() (RVG enables MISA
- * bits but the user is warned about it).
- */
-void riscv_cpu_add_misa_properties(Object *cpu_obj)
-{
-    int i;
-
-    for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
-        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
-        int bit = misa_cfg->misa_bit;
-        const char *name = riscv_get_misa_ext_name(bit);
-        const char *desc = riscv_get_misa_ext_description(bit);
-
-        /* Check if KVM already created the property */
-        if (object_property_find(cpu_obj, name)) {
-            continue;
-        }
-
-        object_property_add(cpu_obj, name, "bool",
-                            cpu_get_misa_ext_cfg,
-                            cpu_set_misa_ext_cfg,
-                            NULL, (void *)misa_cfg);
-        object_property_set_description(cpu_obj, name, desc);
-        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
-    }
-}
-
 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .enabled = _defval}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
     return true;
 }
 
+typedef struct RISCVCPUMisaExtConfig {
+    target_ulong misa_bit;
+    bool enabled;
+} RISCVCPUMisaExtConfig;
+
+static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                 void *opaque, Error **errp)
+{
+    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+    target_ulong misa_bit = misa_ext_cfg->misa_bit;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    bool value;
+
+    if (!visit_type_bool(v, name, &value, errp)) {
+        return;
+    }
+
+    if (value) {
+        env->misa_ext |= misa_bit;
+        env->misa_ext_mask |= misa_bit;
+    } else {
+        env->misa_ext &= ~misa_bit;
+        env->misa_ext_mask &= ~misa_bit;
+    }
+}
+
+static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+                                 void *opaque, Error **errp)
+{
+    const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+    target_ulong misa_bit = misa_ext_cfg->misa_bit;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
+    bool value;
+
+    value = env->misa_ext & misa_bit;
+
+    visit_type_bool(v, name, &value, errp);
+}
+
+#define MISA_CFG(_bit, _enabled) \
+    {.misa_bit = _bit, .enabled = _enabled}
+
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+    MISA_CFG(RVA, true),
+    MISA_CFG(RVC, true),
+    MISA_CFG(RVD, true),
+    MISA_CFG(RVF, true),
+    MISA_CFG(RVI, true),
+    MISA_CFG(RVE, false),
+    MISA_CFG(RVM, true),
+    MISA_CFG(RVS, true),
+    MISA_CFG(RVU, true),
+    MISA_CFG(RVH, true),
+    MISA_CFG(RVJ, false),
+    MISA_CFG(RVV, false),
+    MISA_CFG(RVG, false),
+};
+
+/*
+ * We do not support user choice tracking for MISA
+ * extensions yet because, so far, we do not silently
+ * change MISA bits during realize() (RVG enables MISA
+ * bits but the user is warned about it).
+ */
+static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+        const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+        int bit = misa_cfg->misa_bit;
+        const char *name = riscv_get_misa_ext_name(bit);
+        const char *desc = riscv_get_misa_ext_description(bit);
+
+        /* Check if KVM already created the property */
+        if (object_property_find(cpu_obj, name)) {
+            continue;
+        }
+
+        object_property_add(cpu_obj, name, "bool",
+                            cpu_get_misa_ext_cfg,
+                            cpu_set_misa_ext_cfg,
+                            NULL, (void *)misa_cfg);
+        object_property_set_description(cpu_obj, name, desc);
+        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+    }
+}
+
 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                   void *opaque, Error **errp)
 {
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This array will be read by the TCG accel class, allowing it to handle
priv spec verifications on its own. The array will remain here in cpu.c
because it's also used by the riscv,isa string function.

To export it we'll finish it with an empty element since ARRAY_SIZE()
won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to
alleviate the changes for the next patch.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  7 +++++++
 target/riscv/cpu.c | 47 +++++++++++++++++++++-------------------------
 2 files changed, 28 insertions(+), 26 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 extern Property riscv_cpu_options[];
 
+typedef struct isa_ext_data {
+    const char *name;
+    int min_version;
+    int ext_enable_offset;
+} RISCVIsaExtData;
+extern const RISCVIsaExtData isa_edata_arr[];
+
 void riscv_add_satp_mode_properties(Object *obj);
 
 /* CSR function table */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
                               RVC, RVS, RVU, RVH, RVJ, RVG, 0};
 
-struct isa_ext_data {
-    const char *name;
-    int min_version;
-    int ext_enable_offset;
-};
-
-#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
-    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
-
 /*
  * From vector_helper.c
  * Note that vector data is stored in host-endian 64-bit chunks,
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
 #define BYTE(x)   (x)
 #endif
 
+#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
+    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
+
 /*
  * Here are the ordering rules of extension naming defined by RISC-V
  * specification :
@@ -XXX,XX +XXX,XX @@ struct isa_ext_data {
  * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
  * instead.
  */
-static const struct isa_ext_data isa_edata_arr[] = {
+const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
     ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
     ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+
+    DEFINE_PROP_END_OF_LIST(),
 };
 
 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
@@ -XXX,XX +XXX,XX @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
 
 int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 {
-    int i;
+    const RISCVIsaExtData *edata;
 
-    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
+        if (edata->ext_enable_offset != ext_offset) {
             continue;
         }
 
-        return isa_edata_arr[i].min_version;
+        return edata->min_version;
     }
 
     g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 {
     CPURISCVState *env = &cpu->env;
-    int i;
+    const RISCVIsaExtData *edata;
 
     /* Force disable extensions if priv spec version does not match */
-    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
-            (env->priv_ver < isa_edata_arr[i].min_version)) {
-            isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
-                                   false);
+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
+        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
+            (env->priv_ver < edata->min_version)) {
+            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
 #ifndef CONFIG_USER_ONLY
             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
                         " because privilege spec version does not match",
-                        isa_edata_arr[i].name, env->mhartid);
+                        edata->name, env->mhartid);
 #else
             warn_report("disabling %s extension because "
                         "privilege spec version does not match",
-                        isa_edata_arr[i].name);
+                        edata->name);
 #endif
         }
     }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
                                  int max_str_len)
 {
+    const RISCVIsaExtData *edata;
     char *old = *isa_str;
     char *new = *isa_str;
-    int i;
 
-    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
-            new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
+    for (edata = isa_edata_arr; edata && edata->name; edata++) {
+        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
+            new = g_strconcat(old, "_", edata->name, NULL);
             g_free(old);
             old = new;
         }
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Priv spec validation is TCG specific. Move it to the TCG accel class.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230925175709.35696-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  2 --
 target/riscv/cpu.c         | 38 --------------------------------------
 target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 38 insertions(+), 40 deletions(-)

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We'll introduce generic errors that will output a CPU type name via its
RISCVCPU pointer. Create a helper for that.

Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host'
CPU name.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230926183109.165878-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/cpu.c         | 11 +++++++++++
 target/riscv/tcg/tcg-cpu.c |  4 +++-
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct isa_ext_data {
     int ext_enable_offset;
 } RISCVIsaExtData;
 extern const RISCVIsaExtData isa_edata_arr[];
+char *riscv_cpu_get_name(RISCVCPU *cpu);
 
 void riscv_add_satp_mode_properties(Object *obj);
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
     return oc;
 }
 
+char *riscv_cpu_get_name(RISCVCPU *cpu)
+{
+    RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu);
+    const char *typename = object_class_get_name(OBJECT_CLASS(rcc));
+
+    g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX));
+
+    return g_strndup(typename,
+                     strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX));
+}
+
 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
     Error *local_err = NULL;
 
     if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
-        error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
+        g_autofree char *name = riscv_cpu_get_name(cpu);
+        error_setg(errp, "'%s' CPU is not compatible with TCG acceleration",
+                   name);
         return false;
     }
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

At this moment we do not expose extension properties for vendor CPUs
because that would allow users to change them via command line. The
drawback is that if we were to add an API that shows all CPU properties,
e.g. qmp-query-cpu-model-expansion, we won't be able to show extensions
state of vendor CPUs.

We have the required machinery to create extension properties for vendor
CPUs while not allowing users to enable extensions. Disabling existing
extensions is allowed since it can be useful for debugging.

Change the set() callback cpu_set_multi_ext_cfg() to allow enabling
extensions only for generic CPUs. In cpu_add_multi_ext_prop() let's not
set the default values for the properties if we're not dealing with
generic CPUs, otherwise the values set in cpu_init() of vendor CPUs will
be overwritten. And finally, in tcg_cpu_instance_init(), add cpu user
properties for all CPUs.

For the veyron-v1 CPU, we're now able to disable existing extensions
like smstateen:

$ ./build/qemu-system-riscv64 --nographic -M virt \
    -cpu veyron-v1,smstateen=false

But setting extensions that the CPU didn't set during cpu_init(), like
V, is not allowed:

$ ./build/qemu-system-riscv64 --nographic -M virt \
    -cpu veyron-v1,v=true
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.v=true:
  'veyron-v1' CPU does not allow enabling extensions

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230926183109.165878-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/tcg/tcg-cpu.c | 64 +++++++++++++++++++++++++++++---------
 1 file changed, 50 insertions(+), 14 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     riscv_cpu_disable_priv_spec_isa_exts(cpu);
 }
 
+static bool riscv_cpu_is_generic(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
 /*
  * We'll get here via the following path:
  *
@@ -XXX,XX +XXX,XX @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
     target_ulong misa_bit = misa_ext_cfg->misa_bit;
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    bool value;
+    bool generic_cpu = riscv_cpu_is_generic(obj);
+    bool prev_val, value;
 
     if (!visit_type_bool(v, name, &value, errp)) {
         return;
     }
 
+    prev_val = env->misa_ext & misa_bit;
+
+    if (value == prev_val) {
+        return;
+    }
+
     if (value) {
+        if (!generic_cpu) {
+            g_autofree char *cpuname = riscv_cpu_get_name(cpu);
+            error_setg(errp, "'%s' CPU does not allow enabling extensions",
+                       cpuname);
+            return;
+        }
+
         env->misa_ext |= misa_bit;
         env->misa_ext_mask |= misa_bit;
     } else {
@@ -XXX,XX +XXX,XX @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
  */
 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 {
+    bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
     int i;
 
     for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
                             cpu_set_misa_ext_cfg,
                             NULL, (void *)misa_cfg);
         object_property_set_description(cpu_obj, name, desc);
-        object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+        if (use_def_vals) {
+            object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+        }
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                   void *opaque, Error **errp)
 {
     const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
-    bool value;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    bool generic_cpu = riscv_cpu_is_generic(obj);
+    bool prev_val, value;
 
     if (!visit_type_bool(v, name, &value, errp)) {
         return;
     }
 
-    isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
-
     g_hash_table_insert(multi_ext_user_opts,
                         GUINT_TO_POINTER(multi_ext_cfg->offset),
                         (gpointer)value);
+
+    prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
+
+    if (value == prev_val) {
+        return;
+    }
+
+    if (value && !generic_cpu) {
+        g_autofree char *cpuname = riscv_cpu_get_name(cpu);
+        error_setg(errp, "'%s' CPU does not allow enabling extensions",
+                   cpuname);
+        return;
+    }
+
+    isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value);
 }
 
 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
@@ -XXX,XX +XXX,XX @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 static void cpu_add_multi_ext_prop(Object *cpu_obj,
                                    const RISCVCPUMultiExtConfig *multi_cfg)
 {
+    bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
+
     object_property_add(cpu_obj, multi_cfg->name, "bool",
                         cpu_get_multi_ext_cfg,
                         cpu_set_multi_ext_cfg,
                         NULL, (void *)multi_cfg);
 
+    if (!generic_cpu) {
+        return;
+    }
+
     /*
      * Set def val directly instead of using
      * object_property_set_bool() to save the set()
@@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
     return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
 }
 
-static bool riscv_cpu_has_user_properties(Object *cpu_obj)
-{
-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-}
-
 static void tcg_cpu_instance_init(CPUState *cs)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     Object *obj = OBJECT(cpu);
 
-    if (riscv_cpu_has_user_properties(obj)) {
-        multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
-        riscv_cpu_add_user_properties(obj);
-    }
+    multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+    riscv_cpu_add_user_properties(obj);
 
     if (riscv_cpu_has_max_extensions(obj)) {
         riscv_init_max_cpu_extensions(obj);
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

As of now, the exit code was either EXIT_FAILURE when a panic shutdown
was requested or EXIT_SUCCESS otherwise.
However, some hardware could want to pass more complex exit codes. Thus,
introduce a new shutdown request function allowing that.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-2-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/sysemu/runstate.h |  2 ++
 system/runstate.c         | 12 +++++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/runstate.h
+++ b/include/sysemu/runstate.h
@@ -XXX,XX +XXX,XX @@ void qemu_system_wakeup_request(WakeupReason reason, Error **errp);
 void qemu_system_wakeup_enable(WakeupReason reason, bool enabled);
 void qemu_register_wakeup_notifier(Notifier *notifier);
 void qemu_register_wakeup_support(void);
+void qemu_system_shutdown_request_with_code(ShutdownCause reason,
+                                            int exit_code);
 void qemu_system_shutdown_request(ShutdownCause reason);
 void qemu_system_powerdown_request(void);
 void qemu_register_powerdown_notifier(Notifier *notifier);
diff --git a/system/runstate.c b/system/runstate.c
index XXXXXXX..XXXXXXX 100644
--- a/system/runstate.c
+++ b/system/runstate.c
@@ -XXX,XX +XXX,XX @@ void vm_state_notify(bool running, RunState state)
 
 static ShutdownCause reset_requested;
 static ShutdownCause shutdown_requested;
+static int shutdown_exit_code = EXIT_SUCCESS;
 static int shutdown_signal;
 static pid_t shutdown_pid;
 static int powerdown_requested;
@@ -XXX,XX +XXX,XX @@ void qemu_system_killed(int signal, pid_t pid)
     qemu_notify_event();
 }
 
+void qemu_system_shutdown_request_with_code(ShutdownCause reason,
+                                            int exit_code)
+{
+    shutdown_exit_code = exit_code;
+    qemu_system_shutdown_request(reason);
+}
+
 void qemu_system_shutdown_request(ShutdownCause reason)
 {
     trace_qemu_system_shutdown_request(reason);
@@ -XXX,XX +XXX,XX @@ static bool main_loop_should_exit(int *status)
         if (shutdown_action == SHUTDOWN_ACTION_PAUSE) {
             vm_stop(RUN_STATE_SHUTDOWN);
         } else {
-            if (request == SHUTDOWN_CAUSE_GUEST_PANIC &&
+            if (shutdown_exit_code != EXIT_SUCCESS) {
+                *status = shutdown_exit_code;
+            } else if (request == SHUTDOWN_CAUSE_GUEST_PANIC &&
                 panic_action == PANIC_ACTION_EXIT_FAILURE) {
                 *status = EXIT_FAILURE;
             }
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

gdb_exit function aims to close gdb sessions and sends the exit code of
the current execution. It's being called by qemu_cleanup once the main
loop is over.
Until now, the exit code sent was always 0. Now that hardware can
shutdown this main loop with custom exit codes, these codes must be
transfered to gdb as well.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-3-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/sysemu/sysemu.h | 2 +-
 system/main.c           | 2 +-
 system/runstate.c       | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -XXX,XX +XXX,XX @@ bool defaults_enabled(void);
 
 void qemu_init(int argc, char **argv);
 int qemu_main_loop(void);
-void qemu_cleanup(void);
+void qemu_cleanup(int);
 
 extern QemuOptsList qemu_legacy_drive_opts;
 extern QemuOptsList qemu_common_drive_opts;
diff --git a/system/main.c b/system/main.c
index XXXXXXX..XXXXXXX 100644
--- a/system/main.c
+++ b/system/main.c
@@ -XXX,XX +XXX,XX @@ int qemu_default_main(void)
     int status;
 
     status = qemu_main_loop();
-    qemu_cleanup();
+    qemu_cleanup(status);
 
     return status;
 }
diff --git a/system/runstate.c b/system/runstate.c
index XXXXXXX..XXXXXXX 100644
--- a/system/runstate.c
+++ b/system/runstate.c
@@ -XXX,XX +XXX,XX @@ void qemu_init_subsystems(void)
 }
 
 
-void qemu_cleanup(void)
+void qemu_cleanup(int status)
 {
-    gdb_exit(0);
+    gdb_exit(status);
 
     /*
      * cleaning up the migration object cancels any existing migration
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Otherwise, some connections like gdb could be broken
before its final packet ("Wxx") is being sent. This part, being done
inside qemu_cleanup function, can be reached only when the main loop
exits after a shutdown request.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-4-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/misc/sifive_test.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sifive_test.c
+++ b/hw/misc/sifive_test.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "sysemu/runstate.h"
 #include "hw/misc/sifive_test.h"
+#include "sysemu/sysemu.h"
 
 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
 {
@@ -XXX,XX +XXX,XX @@ static void sifive_test_write(void *opaque, hwaddr addr,
         int code = (val64 >> 16) & 0xffff;
         switch (status) {
         case FINISHER_FAIL:
-            exit(code);
+            qemu_system_shutdown_request_with_code(
+                SHUTDOWN_CAUSE_GUEST_PANIC, code);
+            return;
         case FINISHER_PASS:
-            exit(0);
+            qemu_system_shutdown_request_with_code(
+                SHUTDOWN_CAUSE_GUEST_SHUTDOWN, code);
+            return;
         case FINISHER_RESET:
             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
             return;
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-5-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/riscv_htif.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "exec/tswap.h"
 #include "sysemu/dma.h"
+#include "sysemu/runstate.h"
 
 #define RISCV_DEBUG_HTIF 0
 #define HTIF_DEBUG(fmt, ...)                                                   \
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
                     g_free(sig_data);
                 }
 
-                exit(exit_code);
+                qemu_system_shutdown_request_with_code(
+                    SHUTDOWN_CAUSE_GUEST_SHUTDOWN, exit_code);
+                return;
             } else {
                 uint64_t syscall[8];
                 cpu_physical_memory_read(payload, syscall, sizeof(syscall));
-- 
2.41.0

From: Clément Chigot <chigot@adacore.com>

This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Features like net/vhost-vdpa.c are expecting
qemu_cleanup to be called to remove their last residuals.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-6-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/gdbstub/syscalls.h | 9 +++++++++
 gdbstub/gdbstub.c          | 5 +++--
 gdbstub/system.c           | 6 ++++++
 gdbstub/user.c             | 6 ++++++
 4 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/include/gdbstub/syscalls.h b/include/gdbstub/syscalls.h
index XXXXXXX..XXXXXXX 100644
--- a/include/gdbstub/syscalls.h
+++ b/include/gdbstub/syscalls.h
@@ -XXX,XX +XXX,XX @@ int use_gdb_syscalls(void);
  */
 void gdb_exit(int code);
 
+/**
+ * gdb_qemu_exit: ask qemu to exit
+ * @code: exit code reported
+ *
+ * This requests qemu to exit. This function is allowed to return as
+ * the exit request might be processed asynchronously by qemu backend.
+ */
+void gdb_qemu_exit(int code);
+
 #endif /* _SYSCALLS_H_ */
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void handle_v_kill(GArray *params, void *user_ctx)
     gdb_put_packet("OK");
     error_report("QEMU: Terminated via GDBstub");
     gdb_exit(0);
-    exit(0);
+    gdb_qemu_exit(0);
 }
 
 static const GdbCmdParseEntry gdb_v_commands_table[] = {
@@ -XXX,XX +XXX,XX @@ static int gdb_handle_packet(const char *line_buf)
         /* Kill the target */
         error_report("QEMU: Terminated via GDBstub");
         gdb_exit(0);
-        exit(0);
+        gdb_qemu_exit(0);
+        break;
     case 'D':
         {
             static const GdbCmdParseEntry detach_cmd_desc = {
diff --git a/gdbstub/system.c b/gdbstub/system.c
index XXXXXXX..XXXXXXX 100644
--- a/gdbstub/system.c
+++ b/gdbstub/system.c
@@ -XXX,XX +XXX,XX @@ void gdb_exit(int code)
     qemu_chr_fe_deinit(&gdbserver_system_state.chr, true);
 }
 
+void gdb_qemu_exit(int code)
+{
+    qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_SHUTDOWN,
+                                           code);
+}
+
 /*
  * Memory access
  */
diff --git a/gdbstub/user.c b/gdbstub/user.c
index XXXXXXX..XXXXXXX 100644
--- a/gdbstub/user.c
+++ b/gdbstub/user.c
@@ -XXX,XX +XXX,XX @@ void gdb_exit(int code)
         gdb_put_packet(buf);
         gdbserver_state.allow_stop_reply = false;
     }
+
+}
+
+void gdb_qemu_exit(int code)
+{
+    exit(code);
 }
 
 int gdb_handlesig(CPUState *cpu, int sig)
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Our error message is returning the value of 'ret', which will be always
-1 in case of error, and will not be that useful:

qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error -1

Improve the error message by outputting 'errno' instead of 'ret'. Use
strerrorname_np() to output the error name instead of the error code.
This will give us what we need to know right away:

qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error code: ENOENT

Given that we're going to exit(1) in this condition instead of
attempting to recover, remove the 'kvm_riscv_destroy_scratch_vcpu()'
call.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231003132148.797921-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

KVM for RISC-V started supporting KVM_GET_REG_LIST in Linux 6.6. It
consists of a KVM ioctl() that retrieves a list of all available regs
for get_one_reg/set_one_reg. Regs that aren't present in the list aren't
supported in the host.

This simplifies our lives when initing the KVM regs since we don't have
to always attempt a KVM_GET_ONE_REG for all regs QEMU knows. We'll only
attempt a get_one_reg() if we're sure the reg is supported, i.e. it was
retrieved by KVM_GET_REG_LIST. Any error in get_one_reg() will then
always considered fatal, instead of having to handle special error codes
that might indicate a non-fatal failure.

Start by moving the current kvm_riscv_init_multiext_cfg() logic into a
new kvm_riscv_read_multiext_legacy() helper. We'll prioritize using
KVM_GET_REG_LIST, so check if we have it available and, in case we
don't, use the legacy() logic.

Otherwise, retrieve the available reg list and use it to check if the
host supports our known KVM regs, doing the usual get_one_reg() for
the supported regs and setting cpu->cfg accordingly.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003132148.797921-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 96 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
     }
 }
 
-static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
+static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
+                                           KVMScratchCPU *kvmcpu)
 {
     CPURISCVState *env = &cpu->env;
     uint64_t val;
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     }
 }
 
+static int uint64_cmp(const void *a, const void *b)
+{
+    uint64_t val1 = *(const uint64_t *)a;
+    uint64_t val2 = *(const uint64_t *)b;
+
+    if (val1 < val2) {
+        return -1;
+    }
+
+    if (val1 > val2) {
+        return 1;
+    }
+
+    return 0;
+}
+
+static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
+{
+    KVMCPUConfig *multi_ext_cfg;
+    struct kvm_one_reg reg;
+    struct kvm_reg_list rl_struct;
+    struct kvm_reg_list *reglist;
+    uint64_t val, reg_id, *reg_search;
+    int i, ret;
+
+    rl_struct.n = 0;
+    ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct);
+
+    /*
+     * If KVM_GET_REG_LIST isn't supported we'll get errno 22
+     * (EINVAL). Use read_legacy() in this case.
+     */
+    if (errno == EINVAL) {
+        return kvm_riscv_read_multiext_legacy(cpu, kvmcpu);
+    } else if (errno != E2BIG) {
+        /*
+         * E2BIG is an expected error message for the API since we
+         * don't know the number of registers. The right amount will
+         * be written in rl_struct.n.
+         *
+         * Error out if we get any other errno.
+         */
+        error_report("Error when accessing get-reg-list, code: %s",
+                     strerrorname_np(errno));
+        exit(EXIT_FAILURE);
+    }
+
+    reglist = g_malloc(sizeof(struct kvm_reg_list) +
+                       rl_struct.n * sizeof(uint64_t));
+    reglist->n = rl_struct.n;
+    ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist);
+    if (ret) {
+        error_report("Error when reading KVM_GET_REG_LIST, code %s ",
+                     strerrorname_np(errno));
+        exit(EXIT_FAILURE);
+    }
+
+    /* sort reglist to use bsearch() */
+    qsort(&reglist->reg, reglist->n, sizeof(uint64_t), uint64_cmp);
+
+    for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
+        multi_ext_cfg = &kvm_multi_ext_cfgs[i];
+        reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT,
+                                  multi_ext_cfg->kvm_reg_id);
+        reg_search = bsearch(&reg_id, reglist->reg, reglist->n,
+                             sizeof(uint64_t), uint64_cmp);
+        if (!reg_search) {
+            continue;
+        }
+
+        reg.id = reg_id;
+        reg.addr = (uint64_t)&val;
+        ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg);
+        if (ret != 0) {
+            error_report("Unable to read ISA_EXT KVM register %s, "
+                         "error code: %s", multi_ext_cfg->name,
+                         strerrorname_np(errno));
+            exit(EXIT_FAILURE);
+        }
+
+        multi_ext_cfg->supported = true;
+        kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
+    }
+
+    if (cpu->cfg.ext_icbom) {
+        kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
+    }
+
+    if (cpu->cfg.ext_icboz) {
+        kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
+    }
+}
+
 static void riscv_init_kvm_registers(Object *cpu_obj)
 {
     RISCVCPU *cpu = RISCV_CPU(cpu_obj);
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Vendor CPUs that set RVG are displaying user warnings about other
extensions that RVG must enable, one warning per CPU. E.g.:

$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei

This happens because we decided a while ago that, for simplicity, vendor
CPUs could set RVG instead of setting each G extension individually in
their cpu_init(). Our warning isn't taking that into account, and we're
bugging users with a warning that we're causing ourselves.

In a closer look we conclude that this warning is not warranted in any
other circumstance since we're just following the ISA [1], which states
in chapter 24:

"One goal of the RISC-V project is that it be used as a stable software
development target. For this purpose, we define a combination of a base
ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,
Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for
the IMAFDZicsr Zifencei combination of instruction-set extensions."

With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly
enables 'G' is an expected behavior and the warning is unneeded. Any
user caught by surprise should refer to the ISA.

Remove the warning when handling RVG.

[1] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf

Reported-by: Paul A. Clarke <pclarke@ventanamicro.com>
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003122539.775932-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/tcg/tcg-cpu.c | 1 -
 1 file changed, 1 deletion(-)

From: "Richard W.M. Jones" <rjones@redhat.com>

RISCV_CPU(cs) uses a checked cast.  When QOM cast debugging is enabled
this adds about 5% total overhead when emulating RV64 on x86-64 host.

Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk
disk.  The guest has a copy of the qemu source tree.  The test
involves compiling the qemu source tree with 'make clean; time make -j16'.

Before making this change the compile step took 449 & 447 seconds over
two consecutive runs.

After making this change: 428 & 421 seconds.

The saving is over 5%.

Thanks: Paolo Bonzini
Thanks: Philippe Mathieu-Daudé
Signed-off-by: Richard W.M. Jones <rjones@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231009124859.3373696-2-rjones@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
                           uint64_t *cs_base, uint32_t *pflags)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
     RISCVExtStatus fs, vs;
     uint32_t flags = 0;
 
-- 
2.41.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

At this moment there are eleven CPU extension properties that starts
with capital 'Z': Zifencei, Zicsr, Zihintntl, Zihintpause, Zawrs, Zfa,
Zfh, Zfhmin, Zve32f, Zve64f and Zve64d. All other extensions are named
with lower-case letters.

We want all properties to be named with lower-case letters since it's
consistent with the riscv-isa string that we create in the FDT. Having
these 11 properties to be exceptions can be confusing.

Deprecate all of them. Create their lower-case counterpart to be used as
maintained CPU properties. When trying to use any deprecated property a
warning message will be displayed, recommending users to switch to the
lower-case variant:

./build/qemu-system-riscv64 -M virt -cpu rv64,Zifencei=true --nographic
qemu-system-riscv64: warning: CPU property 'Zifencei' is deprecated. Please use 'zifencei' instead

This will give users some time to change their scripts before we remove
the capital 'Z' properties entirely.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231009112817.8896-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/about/deprecated.rst  | 23 ++++++++++++++++++++++
 target/riscv/cpu.h         |  1 +
 target/riscv/cpu.c         | 39 +++++++++++++++++++++++++++-----------
 target/riscv/tcg/tcg-cpu.c | 31 +++++++++++++++++++++++++++++-
 4 files changed, 82 insertions(+), 12 deletions(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature complete
 CPU for both 32 and 64 bit builds. Users are then discouraged to use the 'any'
 CPU type starting in 8.2.
 
+RISC-V CPU properties which start with capital 'Z' (since 8.2)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+All RISC-V CPU properties which start with capital 'Z' are being deprecated
+starting in 8.2. The reason is that they were wrongly added with capital 'Z'
+in the past. CPU properties were later added with lower-case names, which
+is the format we want to use from now on.
+
+Users which try to use these deprecated properties will receive a warning
+recommending to switch to their stable counterparts:
+
+- "Zifencei" should be replaced with "zifencei"
+- "Zicsr" should be replaced with "zicsr"
+- "Zihintntl" should be replaced with "zihintntl"
+- "Zihintpause" should be replaced with "zihintpause"
+- "Zawrs" should be replaced with "zawrs"
+- "Zfa" should be replaced with "zfa"
+- "Zfh" should be replaced with "zfh"
+- "Zfhmin" should be replaced with "zfhmin"
+- "Zve32f" should be replaced with "zve32f"
+- "Zve64f" should be replaced with "zve64f"
+- "Zve64d" should be replaced with "zve64d"
+
 Block device options
 ''''''''''''''''''''
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPUMultiExtConfig {
 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
 extern Property riscv_cpu_options[];
 
 typedef struct isa_ext_data {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_get_misa_ext_description(uint32_t bit)
 const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
-    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
-    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
-    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
-    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
-    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
-    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
-    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
-    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
-    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
-    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
-    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
+    MULTI_EXT_CFG_BOOL("zifencei", ext_ifencei, true),
+    MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
+    MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
+    MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
+    MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
+    MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
+    MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
+    MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
+    MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
+    MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
 
     MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+/* Deprecated entries marked for future removal */
+const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
+    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
+    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
+    MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
+    MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
+    MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
+    MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
+    MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
+    MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
+    MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
+    MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
+
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 Property riscv_cpu_options[] = {
     DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
     }
 }
 
+static bool cpu_ext_is_deprecated(const char *ext_name)
+{
+    return isupper(ext_name[0]);
+}
+
+/*
+ * String will be allocated in the heap. Caller is responsible
+ * for freeing it.
+ */
+static char *cpu_ext_to_lower(const char *ext_name)
+{
+    char *ret = g_malloc0(strlen(ext_name) + 1);
+
+    strcpy(ret, ext_name);
+    ret[0] = tolower(ret[0]);
+
+    return ret;
+}
+
 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
                                   void *opaque, Error **errp)
 {
@@ -XXX,XX +XXX,XX @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
         return;
     }
 
+    if (cpu_ext_is_deprecated(multi_ext_cfg->name)) {
+        g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name);
+
+        warn_report("CPU property '%s' is deprecated. Please use '%s' instead",
+                    multi_ext_cfg->name, lower);
+    }
+
     g_hash_table_insert(multi_ext_user_opts,
                         GUINT_TO_POINTER(multi_ext_cfg->offset),
                         (gpointer)value);
@@ -XXX,XX +XXX,XX @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
                                    const RISCVCPUMultiExtConfig *multi_cfg)
 {
     bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
+    bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name);
 
     object_property_add(cpu_obj, multi_cfg->name, "bool",
                         cpu_get_multi_ext_cfg,
                         cpu_set_multi_ext_cfg,
                         NULL, (void *)multi_cfg);
 
-    if (!generic_cpu) {
+    if (!generic_cpu || deprecated_ext) {
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_add_user_properties(Object *obj)
     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
 
+    riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
+
     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
         qdev_property_add_static(DEVICE(obj), prop);
     }
-- 
2.41.0

From: Max Chou <max.chou@sifive.com>

The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
replaced by fwmaccbf16.

Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension")
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231005095734.567575-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -XXX,XX +XXX,XX @@ static uint32_t fwmaccbf16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwmaccbf16_vv, WOP_UUU_H, H4, H2, H2, fwmaccbf16)
 GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
-RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16)
+RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmaccbf16)
 GEN_VEXT_VF(vfwmaccbf16_vf, 4)
 
 static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
-- 
2.41.0