[PULL 00/54] target-arm queue
[PULL 00/72] target-arm queue
1
This is mostly RTH's tcg_constant refactoring work, plus a few
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
other things.
2
handling series. (Lots more in my to-review queue, but I don't
3
like pullreqs growing too close to a hundred patches at a time :-))
3
4
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit cf6f26d6f9b2015ee12b4604b79359e76784163a:
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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Merge tag 'kraxel-20220427-pull-request' of git://git.kraxel.org/qemu into staging (2022-04-27 10:49:28 -0700)
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220428
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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for you to fetch changes up to f8e7163d9e6740b5cef02bf73a17a59d0bef8bdb:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2 (2022-04-28 13:59:23 +0100)
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MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
21
target-arm queue:
21
* refactor to use tcg_constant where appropriate
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
22
* Advertise support for FEAT_TTL and FEAT_BBM level 2
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
23
* smmuv3: Cache event fault record
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
24
* smmuv3: Add space in guest error message
25
* fpu: Minor NaN-related cleanups
25
* smmuv3: Advertise support for SMMUv3.2-BBML2
26
* MAINTAINERS: email address updates
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27
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----------------------------------------------------------------
28
----------------------------------------------------------------
28
Damien Hedde (1):
29
Bernhard Beschow (5):
29
target/arm: Disable cryptographic instructions when neon is disabled
30
hw/net/lan9118: Extract lan9118_phy
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
30
35
31
Jean-Philippe Brucker (2):
36
Leif Lindholm (1):
32
hw/arm/smmuv3: Cache event fault record
37
MAINTAINERS: update email address for Leif Lindholm
33
hw/arm/smmuv3: Add space in guest error message
34
38
35
Peter Maydell (3):
39
Peter Maydell (54):
36
target/arm: Advertise support for FEAT_TTL
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
37
target/arm: Advertise support for FEAT_BBM level 2
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
38
hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2
42
softfloat: Allow runtime choice of inf * 0 + NaN result
43
tests/fp: Explicitly set inf-zero-nan rule
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
39
94
40
Richard Henderson (48):
95
Richard Henderson (11):
41
target/arm: Use tcg_constant in gen_probe_access
96
target/arm: Copy entire float_status in is_ebf
42
target/arm: Use tcg_constant in gen_mte_check*
97
softfloat: Inline pickNaNMulAdd
43
target/arm: Use tcg_constant in gen_exception*
98
softfloat: Use goto for default nan case in pick_nan_muladd
44
target/arm: Use tcg_constant in gen_adc_CC
99
softfloat: Remove which from parts_pick_nan_muladd
45
target/arm: Use tcg_constant in handle_msr_i
100
softfloat: Pad array size in pick_nan_muladd
46
target/arm: Use tcg_constant in handle_sys
101
softfloat: Move propagateFloatx80NaN to softfloat.c
47
target/arm: Use tcg_constant in disas_exc
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
48
target/arm: Use tcg_constant in gen_compare_and_swap_pair
103
softfloat: Inline pickNaN
49
target/arm: Use tcg_constant in disas_ld_lit
104
softfloat: Share code between parts_pick_nan cases
50
target/arm: Use tcg_constant in disas_ldst_*
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
51
target/arm: Use tcg_constant in disas_add_sum_imm*
106
softfloat: Replace WHICH with RET in parts_pick_nan
52
target/arm: Use tcg_constant in disas_movw_imm
53
target/arm: Use tcg_constant in shift_reg_imm
54
target/arm: Use tcg_constant in disas_cond_select
55
target/arm: Use tcg_constant in handle_{rev16,crc32}
56
target/arm: Use tcg_constant in disas_data_proc_2src
57
target/arm: Use tcg_constant in disas_fp*
58
target/arm: Use tcg_constant in simd shift expanders
59
target/arm: Use tcg_constant in simd fp/int conversion
60
target/arm: Use tcg_constant in 2misc expanders
61
target/arm: Use tcg_constant in balance of translate-a64.c
62
target/arm: Use tcg_constant for aa32 exceptions
63
target/arm: Use tcg_constant for disas_iwmmxt_insn
64
target/arm: Use tcg_constant for gen_{msr,mrs}
65
target/arm: Use tcg_constant for vector shift expanders
66
target/arm: Use tcg_constant for do_coproc_insn
67
target/arm: Use tcg_constant for gen_srs
68
target/arm: Use tcg_constant for op_s_{rri,rxi}_rot
69
target/arm: Use tcg_constant for MOVW, UMAAL, CRC32
70
target/arm: Use tcg_constant for v7m MRS, MSR
71
target/arm: Use tcg_constant for TT, SAT, SMMLA
72
target/arm: Use tcg_constant in LDM, STM
73
target/arm: Use tcg_constant in CLRM, DLS, WLS, LE
74
target/arm: Use tcg_constant in trans_CPS_v7m
75
target/arm: Use tcg_constant in trans_CSEL
76
target/arm: Use tcg_constant for trans_INDEX_*
77
target/arm: Use tcg_constant in SINCDEC, INCDEC
78
target/arm: Use tcg_constant in FCPY, CPY
79
target/arm: Use tcg_constant in {incr, wrap}_last_active
80
target/arm: Use tcg_constant in do_clast_scalar
81
target/arm: Use tcg_constant in WHILE
82
target/arm: Use tcg_constant in LD1, ST1
83
target/arm: Use tcg_constant in SUBR
84
target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm
85
target/arm: Use tcg_constant for predicate descriptors
86
target/arm: Use tcg_constant for do_brk{2,3}
87
target/arm: Use tcg_constant for vector descriptor
88
target/arm: Use field names for accessing DBGWCRn
89
107
90
docs/system/arm/emulation.rst | 2 +
108
Vikram Garhwal (1):
91
hw/arm/smmuv3-internal.h | 2 +-
109
MAINTAINERS: Add correct email address for Vikram Garhwal
92
include/hw/arm/smmu-common.h | 1 +
110
93
target/arm/internals.h | 12 ++
111
MAINTAINERS | 4 +-
94
hw/arm/smmuv3.c | 17 +--
112
include/fpu/softfloat-helpers.h | 38 +++-
95
target/arm/cpu.c | 9 ++
113
include/fpu/softfloat-types.h | 89 +++++++-
96
target/arm/cpu64.c | 2 +
114
include/hw/net/imx_fec.h | 9 +-
97
target/arm/debug_helper.c | 10 +-
115
include/hw/net/lan9118_phy.h | 37 ++++
98
target/arm/helper.c | 8 +-
116
include/hw/net/mii.h | 6 +
99
target/arm/kvm64.c | 14 +-
117
target/mips/fpu_helper.h | 20 ++
100
target/arm/translate-a64.c | 301 +++++++++++++-----------------------------
118
target/sparc/helper.h | 4 +-
101
target/arm/translate-sve.c | 202 ++++++++++------------------
119
fpu/softfloat.c | 19 ++
102
target/arm/translate.c | 244 ++++++++++++----------------------
120
hw/net/imx_fec.c | 146 ++------------
103
13 files changed, 293 insertions(+), 531 deletions(-)
121
hw/net/lan9118.c | 137 ++-----------
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
123
linux-user/arm/nwfpe/fpa11.c | 5 +
124
target/alpha/cpu.c | 2 +
125
target/arm/cpu.c | 10 +
126
target/arm/tcg/vec_helper.c | 20 +-
127
target/hexagon/cpu.c | 2 +
128
target/hppa/fpu_helper.c | 12 ++
129
target/i386/tcg/fpu_helper.c | 12 ++
130
target/loongarch/tcg/fpu_helper.c | 14 +-
131
target/m68k/cpu.c | 14 +-
132
target/m68k/fpu_helper.c | 6 +-
133
target/m68k/helper.c | 6 +-
134
target/microblaze/cpu.c | 2 +
135
target/mips/msa.c | 10 +
136
target/openrisc/cpu.c | 2 +
137
target/ppc/cpu_init.c | 19 ++
138
target/ppc/fpu_helper.c | 3 +-
139
target/riscv/cpu.c | 2 +
140
target/rx/cpu.c | 2 +
141
target/s390x/cpu.c | 5 +
142
target/sh4/cpu.c | 2 +
143
target/sparc/cpu.c | 6 +
144
target/sparc/fop_helper.c | 8 +-
145
target/sparc/translate.c | 4 +-
146
target/tricore/helper.c | 2 +
147
target/xtensa/cpu.c | 4 +
148
target/xtensa/fpu_helper.c | 3 +-
149
tests/fp/fp-bench.c | 7 +
150
tests/fp/fp-test-log2.c | 1 +
151
tests/fp/fp-test.c | 7 +
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
154
.mailmap | 5 +-
155
hw/net/Kconfig | 5 +
156
hw/net/meson.build | 1 +
157
hw/net/trace-events | 10 +-
158
47 files changed, 778 insertions(+), 730 deletions(-)
159
create mode 100644 include/hw/net/lan9118_phy.h
160
create mode 100644 hw/net/lan9118_phy.c
diff view generated by jsdifflib
[PULL 47/54] target/arm: Use tcg_constant for vector descriptor
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
a common implementation by extracting a device model into its own files.
5
6
Some migration state has been moved into the new device model which breaks
7
migration compatibility for the following machines:
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
13
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
16
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-48-richard.henderson@linaro.org
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
22
---
8
target/arm/translate-sve.c | 54 ++++++++++----------------------------
23
include/hw/net/lan9118_phy.h | 37 ++++++++
9
1 file changed, 14 insertions(+), 40 deletions(-)
24
hw/net/lan9118.c | 137 +++++-----------------------
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
26
hw/net/Kconfig | 4 +
27
hw/net/meson.build | 1 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
10
31
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
12
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
77
--- a/hw/net/lan9118.c
14
+++ b/target/arm/translate-sve.c
78
+++ b/hw/net/lan9118.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
79
@@ -XXX,XX +XXX,XX @@
16
return true;
80
#include "net/net.h"
17
}
81
#include "net/eth.h"
18
82
#include "hw/irq.h"
19
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
83
+#include "hw/net/lan9118_phy.h"
20
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
84
#include "hw/net/lan9118.h"
21
temp = tcg_temp_new_i64();
85
#include "hw/ptimer.h"
22
t_zn = tcg_temp_new_ptr();
86
#include "hw/qdev-properties.h"
23
t_pg = tcg_temp_new_ptr();
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
24
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
88
#define MAC_CR_RXEN 0x00000004
25
fn(temp, t_zn, t_pg, desc);
89
#define MAC_CR_RESERVED 0x7f404213
26
tcg_temp_free_ptr(t_zn);
90
27
tcg_temp_free_ptr(t_pg);
91
-#define PHY_INT_ENERGYON 0x80
28
- tcg_temp_free_i32(desc);
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
29
93
-#define PHY_INT_FAULT 0x20
30
write_fp_dreg(s, a->rd, temp);
94
-#define PHY_INT_DOWN 0x10
31
tcg_temp_free_i64(temp);
95
-#define PHY_INT_AUTONEG_LP 0x08
32
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
96
-#define PHY_INT_PARFAULT 0x04
33
TCGv_i64 start, TCGv_i64 incr)
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
141
}
142
143
-static void phy_update_irq(lan9118_state *s)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
34
{
145
{
35
unsigned vsz = vec_full_reg_size(s);
146
- if (s->phy_int & s->phy_int_mask) {
36
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
147
+ lan9118_state *s = opaque;
37
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
148
+
38
TCGv_ptr t_zd = tcg_temp_new_ptr();
149
+ if (level) {
39
150
s->int_sts |= PHY_INT;
40
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
151
} else {
41
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
152
s->int_sts &= ~PHY_INT;
42
tcg_temp_free_i32(i32);
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
43
}
154
lan9118_update(s);
44
tcg_temp_free_ptr(t_zd);
45
- tcg_temp_free_i32(desc);
46
}
155
}
47
156
48
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
157
-static void phy_update_link(lan9118_state *s)
49
@@ -XXX,XX +XXX,XX @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
158
-{
50
nptr = tcg_temp_new_ptr();
159
- /* Autonegotiation status mirrors link status. */
51
tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd));
160
- if (qemu_get_queue(s->nic)->link_down) {
52
tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn));
161
- s->phy_status &= ~0x0024;
53
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
162
- s->phy_int |= PHY_INT_DOWN;
54
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
163
- } else {
55
164
- s->phy_status |= 0x0024;
56
switch (esz) {
165
- s->phy_int |= PHY_INT_ENERGYON;
57
case MO_8:
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
58
@@ -XXX,XX +XXX,XX @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
167
- }
59
168
- phy_update_irq(s);
60
tcg_temp_free_ptr(dptr);
169
-}
61
tcg_temp_free_ptr(nptr);
170
-
62
- tcg_temp_free_i32(desc);
171
static void lan9118_set_link(NetClientState *nc)
172
{
173
- phy_update_link(qemu_get_nic_opaque(nc));
174
-}
175
-
176
-static void phy_reset(lan9118_state *s)
177
-{
178
- s->phy_status = 0x7809;
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
63
}
186
}
64
187
65
static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a)
188
static void lan9118_reset(DeviceState *d)
66
@@ -XXX,XX +XXX,XX @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
67
gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d,
190
s->read_word_n = 0;
68
};
191
s->write_word_n = 0;
69
unsigned vsz = vec_full_reg_size(s);
192
70
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
193
- phy_reset(s);
71
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
194
-
72
TCGv_ptr t_zd = tcg_temp_new_ptr();
195
s->eeprom_writable = 0;
73
TCGv_ptr t_zn = tcg_temp_new_ptr();
196
lan9118_reload_eeprom(s);
74
TCGv_ptr t_pg = tcg_temp_new_ptr();
75
@@ -XXX,XX +XXX,XX @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
76
tcg_temp_free_ptr(t_zd);
77
tcg_temp_free_ptr(t_zn);
78
tcg_temp_free_ptr(t_pg);
79
- tcg_temp_free_i32(desc);
80
}
197
}
81
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
82
static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
199
uint32_t status;
83
@@ -XXX,XX +XXX,XX @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
200
84
gen_helper_sve_insr_s, gen_helper_sve_insr_d,
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
85
};
202
- if (s->phy_control & 0x4000) {
86
unsigned vsz = vec_full_reg_size(s);
203
+ if (s->mii.control & 0x4000) {
87
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
204
/* This assumes the receive routine doesn't touch the VLANClient. */
88
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
89
TCGv_ptr t_zd = tcg_temp_new_ptr();
206
} else {
90
TCGv_ptr t_zn = tcg_temp_new_ptr();
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
91
92
@@ -XXX,XX +XXX,XX @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
93
94
tcg_temp_free_ptr(t_zd);
95
tcg_temp_free_ptr(t_zn);
96
- tcg_temp_free_i32(desc);
97
}
98
99
static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)
100
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
101
TCGv_ptr t_d = tcg_temp_new_ptr();
102
TCGv_ptr t_n = tcg_temp_new_ptr();
103
TCGv_ptr t_m = tcg_temp_new_ptr();
104
- TCGv_i32 t_desc;
105
uint32_t desc = 0;
106
107
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
108
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
109
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
110
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
111
tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm));
112
- t_desc = tcg_const_i32(desc);
113
114
- fn(t_d, t_n, t_m, t_desc);
115
+ fn(t_d, t_n, t_m, tcg_constant_i32(desc));
116
117
tcg_temp_free_ptr(t_d);
118
tcg_temp_free_ptr(t_n);
119
tcg_temp_free_ptr(t_m);
120
- tcg_temp_free_i32(t_desc);
121
return true;
122
}
123
124
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
125
unsigned vsz = pred_full_reg_size(s);
126
TCGv_ptr t_d = tcg_temp_new_ptr();
127
TCGv_ptr t_n = tcg_temp_new_ptr();
128
- TCGv_i32 t_desc;
129
uint32_t desc = 0;
130
131
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
132
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
133
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
134
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
135
desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
136
- t_desc = tcg_const_i32(desc);
137
138
- fn(t_d, t_n, t_desc);
139
+ fn(t_d, t_n, tcg_constant_i32(desc));
140
141
- tcg_temp_free_i32(t_desc);
142
tcg_temp_free_ptr(t_d);
143
tcg_temp_free_ptr(t_n);
144
return true;
145
@@ -XXX,XX +XXX,XX @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
146
* round up, as we do elsewhere, because we need the exact size.
147
*/
148
TCGv_ptr t_p = tcg_temp_new_ptr();
149
- TCGv_i32 t_desc;
150
unsigned desc = 0;
151
152
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
153
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
154
155
tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
156
- t_desc = tcg_const_i32(desc);
157
158
- gen_helper_sve_last_active_element(ret, t_p, t_desc);
159
+ gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc));
160
161
- tcg_temp_free_i32(t_desc);
162
tcg_temp_free_ptr(t_p);
163
}
164
165
@@ -XXX,XX +XXX,XX @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
166
TCGv_ptr t_pn = tcg_temp_new_ptr();
167
TCGv_ptr t_pg = tcg_temp_new_ptr();
168
unsigned desc = 0;
169
- TCGv_i32 t_desc;
170
171
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
172
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
173
174
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
175
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
176
- t_desc = tcg_const_i32(desc);
177
178
- gen_helper_sve_cntp(val, t_pn, t_pg, t_desc);
179
+ gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc));
180
tcg_temp_free_ptr(t_pn);
181
tcg_temp_free_ptr(t_pg);
182
- tcg_temp_free_i32(t_desc);
183
}
208
}
184
}
209
}
185
210
186
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
212
-{
213
- uint32_t val;
214
-
215
- switch (reg) {
216
- case 0: /* Basic Control */
217
- return s->phy_control;
218
- case 1: /* Basic Status */
219
- return s->phy_status;
220
- case 2: /* ID1 */
221
- return 0x0007;
222
- case 3: /* ID2 */
223
- return 0xc0d1;
224
- case 4: /* Auto-neg advertisement */
225
- return s->phy_advertise;
226
- case 5: /* Auto-neg Link Partner Ability */
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
243
-}
244
-
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
246
-{
247
- switch (reg) {
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
271
-}
272
-
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
187
{
274
{
188
unsigned vsz = vec_full_reg_size(s);
275
switch (reg) {
189
unsigned p2vsz = pow2ceil(vsz);
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
190
- TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz));
277
if (val & 2) {
191
+ TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
278
DPRINTF("PHY write %d = 0x%04x\n",
192
TCGv_ptr t_zn, t_pg, status;
279
(val >> 6) & 0x1f, s->mac_mii_data);
193
TCGv_i64 temp;
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
194
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
195
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
282
} else {
196
tcg_temp_free_ptr(t_zn);
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
197
tcg_temp_free_ptr(t_pg);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
198
tcg_temp_free_ptr(status);
285
DPRINTF("PHY read %d = 0x%04x\n",
199
- tcg_temp_free_i32(t_desc);
286
(val >> 6) & 0x1f, s->mac_mii_data);
200
287
}
201
write_fp_dreg(s, a->rd, temp);
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
202
tcg_temp_free_i64(temp);
289
break;
203
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
290
case CSR_PMT_CTRL:
204
tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));
291
if (val & 0x400) {
205
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
292
- phy_reset(s);
206
t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
293
+ lan9118_phy_reset(&s->mii);
207
- t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
294
}
208
+ t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
295
s->pmt_ctrl &= ~0x34e;
209
296
s->pmt_ctrl |= (val & 0x34e);
210
fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
211
298
const MemoryRegionOps *mem_ops =
212
- tcg_temp_free_i32(t_desc);
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
213
tcg_temp_free_ptr(t_fpst);
300
214
tcg_temp_free_ptr(t_pg);
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
215
tcg_temp_free_ptr(t_rm);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
216
@@ -XXX,XX +XXX,XX @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
217
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
304
+ return;
218
305
+ }
219
status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
220
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
307
+
221
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
222
fn(t_zd, t_zn, t_pg, scalar, status, desc);
309
"lan9118-mmio", 0x100);
223
310
sysbus_init_mmio(sbd, &s->mmio);
224
- tcg_temp_free_i32(desc);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
225
tcg_temp_free_ptr(status);
312
new file mode 100644
226
tcg_temp_free_ptr(t_pg);
313
index XXXXXXX..XXXXXXX
227
tcg_temp_free_ptr(t_zn);
314
--- /dev/null
228
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
315
+++ b/hw/net/lan9118_phy.c
229
{
316
@@ -XXX,XX +XXX,XX @@
230
unsigned vsz = vec_full_reg_size(s);
317
+/*
231
TCGv_ptr t_pg;
318
+ * SMSC LAN9118 PHY emulation
232
- TCGv_i32 t_desc;
319
+ *
233
int desc = 0;
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
234
321
+ * Written by Paul Brook
235
/*
322
+ *
236
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
323
+ * This code is licensed under the GNU GPL v2
237
}
324
+ *
238
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
239
desc = simd_desc(vsz, vsz, zt | desc);
326
+ * GNU GPL, version 2 or (at your option) any later version.
240
- t_desc = tcg_const_i32(desc);
327
+ */
241
t_pg = tcg_temp_new_ptr();
328
+
242
329
+#include "qemu/osdep.h"
243
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
330
+#include "hw/net/lan9118_phy.h"
244
- fn(cpu_env, t_pg, addr, t_desc);
331
+#include "hw/irq.h"
245
+ fn(cpu_env, t_pg, addr, tcg_constant_i32(desc));
332
+#include "hw/resettable.h"
246
333
+#include "migration/vmstate.h"
247
tcg_temp_free_ptr(t_pg);
334
+#include "qemu/log.h"
248
- tcg_temp_free_i32(t_desc);
335
+
249
}
336
+#define PHY_INT_ENERGYON (1 << 7)
250
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
251
/* Indexed by [mte][be][dtype][nreg] */
338
+#define PHY_INT_FAULT (1 << 5)
252
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
339
+#define PHY_INT_DOWN (1 << 4)
253
TCGv_ptr t_zm = tcg_temp_new_ptr();
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
254
TCGv_ptr t_pg = tcg_temp_new_ptr();
341
+#define PHY_INT_PARFAULT (1 << 2)
255
TCGv_ptr t_zt = tcg_temp_new_ptr();
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
256
- TCGv_i32 t_desc;
343
+
257
int desc = 0;
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
258
345
+{
259
if (s->mte_active[0]) {
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
260
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
347
+}
261
desc <<= SVE_MTEDESC_SHIFT;
348
+
262
}
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
263
desc = simd_desc(vsz, vsz, desc | scale);
350
+{
264
- t_desc = tcg_const_i32(desc);
351
+ uint16_t val;
265
352
+
266
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
353
+ switch (reg) {
267
tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm));
354
+ case 0: /* Basic Control */
268
tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt));
355
+ return s->control;
269
- fn(cpu_env, t_zt, t_pg, t_zm, scalar, t_desc);
356
+ case 1: /* Basic Status */
270
+ fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
357
+ return s->status;
271
358
+ case 2: /* ID1 */
272
tcg_temp_free_ptr(t_zt);
359
+ return 0x0007;
273
tcg_temp_free_ptr(t_zm);
360
+ case 3: /* ID2 */
274
tcg_temp_free_ptr(t_pg);
361
+ return 0xc0d1;
275
- tcg_temp_free_i32(t_desc);
362
+ case 4: /* Auto-neg advertisement */
276
}
363
+ return s->advertise;
277
364
+ case 5: /* Auto-neg Link Partner Ability */
278
/* Indexed by [mte][be][ff][xs][u][msz]. */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
408
+ }
409
+}
410
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
412
+{
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/net/Kconfig
489
+++ b/hw/net/Kconfig
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
491
config SMC91C111
492
bool
493
494
+config LAN9118_PHY
495
+ bool
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
279
--
515
--
280
2.25.1
516
2.34.1
diff view generated by jsdifflib
[PULL 16/54] target/arm: Use tcg_constant in disas_data_proc_2src
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Existing temp usage treats t1 as both zero and as a
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
temporary. Rearrange to only require one temporary,
4
imx_fec having more logging and tracing. Merge these improvements into
5
so remove t1 and rename t2.
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Some migration state how resides in the new device model which breaks migration
8
compatibility for the following machines:
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
13
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220426163043.100432-17-richard.henderson@linaro.org
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
19
---
12
target/arm/translate-a64.c | 12 +++++-------
20
include/hw/net/imx_fec.h | 9 ++-
13
1 file changed, 5 insertions(+), 7 deletions(-)
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
14
26
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
16
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
29
--- a/include/hw/net/imx_fec.h
18
+++ b/target/arm/translate-a64.c
30
+++ b/include/hw/net/imx_fec.h
19
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
20
if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
32
#define TYPE_IMX_ENET "imx.enet"
21
goto do_unallocated;
33
22
} else {
34
#include "hw/sysbus.h"
23
- TCGv_i64 t1 = tcg_const_i64(1);
35
+#include "hw/net/lan9118_phy.h"
24
- TCGv_i64 t2 = tcg_temp_new_i64();
36
+#include "hw/irq.h"
25
+ TCGv_i64 t = tcg_temp_new_i64();
37
#include "net/net.h"
26
38
27
- tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4);
39
#define ENET_EIR 1
28
- tcg_gen_shl_i64(t1, t1, t2);
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
29
- tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1);
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
30
+ tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4);
42
uint32_t tx_ring_num;
31
+ tcg_gen_shl_i64(t, tcg_constant_i64(1), t);
43
32
+ tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t);
44
- uint32_t phy_status;
33
45
- uint32_t phy_control;
34
- tcg_temp_free_i64(t1);
46
- uint32_t phy_advertise;
35
- tcg_temp_free_i64(t2);
47
- uint32_t phy_int;
36
+ tcg_temp_free_i64(t);
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
140
{
141
- uint32_t val;
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
353
{
354
+ trace_lan9118_phy_write(val, reg);
355
+
356
switch (reg) {
357
case 0: /* Basic Control */
358
if (val & 0x8000) {
359
lan9118_phy_reset(s);
360
- break;
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
37
}
372
}
38
break;
373
break;
39
case 8: /* LSLV */
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
40
--
471
--
41
2.25.1
472
2.34.1
diff view generated by jsdifflib
[PULL 51/54] hw/arm/smmuv3: Add space in guest error message
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Make the translation error message prettier by adding a missing space
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
before the parenthesis.
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
5
5
6
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
6
Fixes: 2a424990170b "LAN9118 emulation"
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20220427111543.124620-2-jean-philippe@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
hw/arm/smmuv3.c | 2 +-
13
hw/net/lan9118_phy.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/smmuv3.c
18
--- a/hw/net/lan9118_phy.c
18
+++ b/hw/arm/smmuv3.c
19
+++ b/hw/net/lan9118_phy.c
19
@@ -XXX,XX +XXX,XX @@ epilogue:
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
21
val = s->advertise;
20
break;
22
break;
21
case SMMU_TRANS_ERROR:
23
case 5: /* Auto-neg Link Partner Ability */
22
qemu_log_mask(LOG_GUEST_ERROR,
24
- val = 0x0f71;
23
- "%s translation failed for iova=0x%"PRIx64"(%s)\n",
25
+ val = 0x0fe1;
24
+ "%s translation failed for iova=0x%"PRIx64" (%s)\n",
25
mr->parent_obj.name, addr, smmu_event_string(event.type));
26
smmuv3_record_event(s, &event);
27
break;
26
break;
27
case 6: /* Auto-neg Expansion */
28
val = 1;
28
--
29
--
29
2.25.1
30
2.34.1
diff view generated by jsdifflib
[PULL 10/54] target/arm: Use tcg_constant in disas_ldst_*
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Prefer named constants over magic values for better readability.
4
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-11-richard.henderson@linaro.org
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/translate-a64.c | 9 +++------
11
include/hw/net/mii.h | 6 +++++
9
1 file changed, 3 insertions(+), 6 deletions(-)
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
10
14
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
17
--- a/include/hw/net/mii.h
14
+++ b/target/arm/translate-a64.c
18
+++ b/include/hw/net/mii.h
15
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@
16
mop = endian | size | align;
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
17
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
18
elements = (is_q ? 16 : 8) >> size;
22
19
- tcg_ebytes = tcg_const_i64(1 << size);
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
20
+ tcg_ebytes = tcg_constant_i64(1 << size);
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
21
for (r = 0; r < rpt; r++) {
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
22
int e;
26
#define MII_ANAR_TXFD (1 << 8)
23
for (e = 0; e < elements; e++) {
27
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
28
#define MII_ANAR_10FD (1 << 6)
29
#define MII_ANAR_10 (1 << 5)
30
#define MII_ANAR_CSMACD (1 << 0)
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
42
+
43
/* RealTek 8211E */
44
#define RTL8211E_PHYID1 0x001c
45
#define RTL8211E_PHYID2 0xc915
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/net/lan9118_phy.c
49
+++ b/hw/net/lan9118_phy.c
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
25
}
117
}
26
}
118
}
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
27
}
143
}
28
- tcg_temp_free_i64(tcg_ebytes);
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
29
145
{
30
if (!is_store) {
146
trace_lan9118_phy_reset();
31
/* For non-quad operations, setting a slice of the low
147
32
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
148
- s->control = 0x3000;
33
total);
149
- s->status = 0x7809;
34
mop = finalize_memop(s, scale);
150
- s->advertise = 0x01e1;
35
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
36
- tcg_ebytes = tcg_const_i64(1 << scale);
152
+ s->status = MII_BMSR_100TX_FD
37
+ tcg_ebytes = tcg_constant_i64(1 << scale);
153
+ | MII_BMSR_100TX_HD
38
for (xs = 0; xs < selem; xs++) {
154
+ | MII_BMSR_10T_FD
39
if (replicate) {
155
+ | MII_BMSR_10T_HD
40
/* Load and replicate to all elements */
156
+ | MII_BMSR_AUTONEG
41
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
157
+ | MII_BMSR_EXTCAP;
42
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
158
+ s->advertise = MII_ANAR_TXFD
43
rt = (rt + 1) % 32;
159
+ | MII_ANAR_TX
44
}
160
+ | MII_ANAR_10FD
45
- tcg_temp_free_i64(tcg_ebytes);
161
+ | MII_ANAR_10
46
162
+ | MII_ANAR_CSMACD;
47
if (is_postidx) {
163
s->int_mask = 0;
48
if (rm == 31) {
164
s->ints = 0;
49
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
165
lan9118_phy_update_link(s, s->link_down);
50
51
if (is_zero) {
52
TCGv_i64 clean_addr = clean_data_tbi(s, addr);
53
- TCGv_i64 tcg_zero = tcg_const_i64(0);
54
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
55
int mem_index = get_mem_index(s);
56
int i, n = (1 + is_pair) << LOG2_TAG_GRANULE;
57
58
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
59
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
60
tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ);
61
}
62
- tcg_temp_free_i64(tcg_zero);
63
}
64
65
if (index != 0) {
66
--
166
--
67
2.25.1
167
2.34.1
diff view generated by jsdifflib
[PULL 44/54] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
The real device advertises this mode and the device model already advertises
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
6
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-45-richard.henderson@linaro.org
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
target/arm/translate-sve.c | 15 +++++----------
13
hw/net/lan9118_phy.c | 4 ++--
9
1 file changed, 5 insertions(+), 10 deletions(-)
14
1 file changed, 2 insertions(+), 2 deletions(-)
10
15
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
18
--- a/hw/net/lan9118_phy.c
14
+++ b/target/arm/translate-sve.c
19
+++ b/hw/net/lan9118_phy.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
16
return false;
21
break;
17
}
22
case MII_ANAR:
18
if (sve_access_check(s)) {
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
19
- TCGv_i64 val = tcg_const_i64(a->imm);
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
20
- do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, u, d);
25
- MII_ANAR_SELECT))
21
- tcg_temp_free_i64(val);
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
22
+ do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
23
+ tcg_constant_i64(a->imm), u, d);
28
| MII_ANAR_TX;
24
}
29
break;
25
return true;
30
case 30: /* Interrupt mask */
26
}
27
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
28
{
29
if (sve_access_check(s)) {
30
unsigned vsz = vec_full_reg_size(s);
31
- TCGv_i64 c = tcg_const_i64(a->imm);
32
-
33
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
34
vec_full_reg_offset(s, a->rn),
35
- c, vsz, vsz, 0, fn);
36
- tcg_temp_free_i64(c);
37
+ tcg_constant_i64(a->imm), vsz, vsz, 0, fn);
38
}
39
return true;
40
}
41
@@ -XXX,XX +XXX,XX @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
42
static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm,
43
gen_helper_sve_fp2scalar *fn)
44
{
45
- TCGv_i64 temp = tcg_const_i64(imm);
46
- do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, temp, fn);
47
- tcg_temp_free_i64(temp);
48
+ do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16,
49
+ tcg_constant_i64(imm), fn);
50
}
51
52
#define DO_FP_IMM(NAME, name, const0, const1) \
53
--
31
--
54
2.25.1
32
2.34.1
diff view generated by jsdifflib
New patch
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
1
6
7
For the cases where the infzero test in pickNaNMulAdd was
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
13
14
For Arm, this looks like it might be a behaviour change because we
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
37
---
38
fpu/softfloat-parts.c.inc | 13 +++++++------
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
41
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
43
index XXXXXXX..XXXXXXX 100644
44
--- a/fpu/softfloat-parts.c.inc
45
+++ b/fpu/softfloat-parts.c.inc
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
47
int ab_mask, int abc_mask)
48
{
49
int which;
50
+ bool infzero = (ab_mask == float_cmask_infzero);
51
52
if (unlikely(abc_mask & float_cmask_snan)) {
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
54
}
55
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
57
- ab_mask == float_cmask_infzero, s);
58
+ if (infzero) {
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
61
+ }
62
+
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
64
65
if (s->default_nan_mode || which == 3) {
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
74
index XXXXXXX..XXXXXXX 100644
75
--- a/fpu/softfloat-specialize.c.inc
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
129
}
130
#elif defined(TARGET_RISCV)
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
132
- if (infzero) {
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
165
--
166
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
[PULL 37/54] target/arm: Use tcg_constant in SINCDEC, INCDEC
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
From: Richard Henderson <richard.henderson@linaro.org>
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
architectures thus do different things:
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
* some return the default NaN
5
Message-id: 20220426163043.100432-38-richard.henderson@linaro.org
5
* some return the input NaN
6
* Arm returns the default NaN if the input NaN is quiet,
7
and the input NaN if it is signalling
8
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
7
---
33
---
8
target/arm/translate-sve.c | 18 ++++++------------
34
include/fpu/softfloat-helpers.h | 11 ++++
9
1 file changed, 6 insertions(+), 12 deletions(-)
35
include/fpu/softfloat-types.h | 23 +++++++++
10
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
12
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
41
--- a/include/fpu/softfloat-helpers.h
14
+++ b/target/arm/translate-sve.c
42
+++ b/include/fpu/softfloat-helpers.h
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a)
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
16
tcg_gen_ext32s_i64(reg, reg);
44
status->float_2nan_prop_rule = rule;
45
}
46
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
49
+{
50
+ status->float_infzeronan_rule = rule;
51
+}
52
+
53
static inline void set_flush_to_zero(bool val, float_status *status)
54
{
55
status->flush_to_zero = val;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
57
return status->float_2nan_prop_rule;
58
}
59
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
61
+{
62
+ return status->float_infzeronan_rule;
63
+}
64
+
65
static inline bool get_flush_to_zero(float_status *status)
66
{
67
return status->flush_to_zero;
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
17
}
212
}
18
} else {
213
} else {
19
- TCGv_i64 t = tcg_const_i64(inc);
214
- /*
20
- do_sat_addsub_32(reg, t, a->u, a->d);
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
21
- tcg_temp_free_i64(t);
216
- * case sets InvalidOp and returns the input value 'c'
22
+ do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d);
217
- */
23
}
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
24
return true;
219
if (is_snan(c_cls)) {
25
}
220
return 2;
26
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a)
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
27
TCGv_i64 reg = cpu_reg(s, a->rd);
28
29
if (inc != 0) {
30
- TCGv_i64 t = tcg_const_i64(inc);
31
- do_sat_addsub_64(reg, t, a->u, a->d);
32
- tcg_temp_free_i64(t);
33
+ do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d);
34
}
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
38
39
if (inc != 0) {
40
if (sve_access_check(s)) {
41
- TCGv_i64 t = tcg_const_i64(a->d ? -inc : inc);
42
tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd),
43
vec_full_reg_offset(s, a->rn),
44
- t, fullsz, fullsz);
45
- tcg_temp_free_i64(t);
46
+ tcg_constant_i64(a->d ? -inc : inc),
47
+ fullsz, fullsz);
48
}
222
}
49
} else {
223
}
50
do_mov_z(s, a->rd, a->rn);
224
#elif defined(TARGET_LOONGARCH64)
51
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
225
- /*
52
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
53
if (inc != 0) {
227
- * case sets InvalidOp and returns the input value 'c'
54
if (sve_access_check(s)) {
228
- */
55
- TCGv_i64 t = tcg_const_i64(inc);
229
-
56
- do_sat_addsub_vec(s, a->esz, a->rd, a->rn, t, a->u, a->d);
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
57
- tcg_temp_free_i64(t);
231
if (is_snan(c_cls)) {
58
+ do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
232
return 2;
59
+ tcg_constant_i64(inc), a->u, a->d);
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
}
234
return 1;
61
} else {
235
}
62
do_mov_z(s, a->rd, a->rn);
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
63
--
256
--
64
2.25.1
257
2.34.1
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
[PULL 48/54] target/arm: Disable cryptographic instructions when neon is disabled
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
As of now, cryptographic instructions ISAR fields are never cleared so
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
we can end up with a cpu with cryptographic instructions but no
5
floating-point/neon instructions which is not a possible configuration
6
according to Arm specifications.
7
8
In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
9
+ no support
10
+ cortex-a57/a72: cryptographic extension is optional,
11
floating-point/neon is not.
12
+ cortex-a53: crytographic extension is optional as well as
13
floating-point/neon. But cryptographic requires
14
floating-point/neon support.
15
16
Therefore we can safely clear the ISAR fields when neon is disabled.
17
18
Note that other Arm cpus seem to follow this. For example cortex-a55 is
19
like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
20
21
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20220427090117.6954-1-damien.hedde@greensocs.com
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
24
[PMM: fixed commit message typos]
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
7
---
27
target/arm/cpu.c | 9 +++++++++
8
target/arm/cpu.c | 3 +++
28
1 file changed, 9 insertions(+)
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
29
11
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
31
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
34
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
35
unset_feature(env, ARM_FEATURE_NEON);
17
* * tininess-before-rounding
36
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
37
t = cpu->isar.id_aa64isar0;
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
38
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
39
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
21
+ * and the input NaN if it is signalling
40
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
22
*/
41
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
23
static void arm_set_default_fp_behaviours(float_status *s)
42
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
24
{
43
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
25
set_float_detect_tininess(float_tininess_before_rounding, s);
44
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
45
cpu->isar.id_aa64isar0 = t;
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
46
28
}
47
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
29
48
cpu->isar.id_aa64pfr0 = t;
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
49
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
u = cpu->isar.id_isar5;
32
index XXXXXXX..XXXXXXX 100644
51
+ u = FIELD_DP32(u, ID_ISAR5, AES, 0);
33
--- a/fpu/softfloat-specialize.c.inc
52
+ u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
34
+++ b/fpu/softfloat-specialize.c.inc
53
+ u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
36
/*
55
u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
37
* Temporarily fall back to ifdef ladder
56
cpu->isar.id_isar5 = u;
38
*/
39
-#if defined(TARGET_ARM)
40
- /*
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
42
- * but (inf,zero,snan) returns the input NaN.
43
- */
44
- rule = float_infzeronan_dnan_if_qnan;
45
-#elif defined(TARGET_MIPS)
46
+#if defined(TARGET_MIPS)
47
if (snan_bit_is_one(status)) {
48
/*
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
57
--
50
--
58
2.25.1
51
2.34.1
diff view generated by jsdifflib
[PULL 50/54] hw/arm/smmuv3: Cache event fault record
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
2
3
3
The Record bit in the Context Descriptor tells the SMMU to report fault
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
events to the event queue. Since we don't cache the Record bit at the
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
moment, access faults from a cached Context Descriptor are never
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
6
reported. Store the Record bit in the cached SMMUTransCfg.
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
7
11
8
Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback")
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20220427111543.124620-1-jean-philippe@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/arm/smmuv3-internal.h | 1 -
16
include/hw/arm/smmu-common.h | 1 +
17
hw/arm/smmuv3.c | 14 +++++++-------
18
3 files changed, 8 insertions(+), 8 deletions(-)
19
20
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/smmuv3-internal.h
14
--- a/target/s390x/cpu.c
23
+++ b/hw/arm/smmuv3-internal.h
15
+++ b/target/s390x/cpu.c
24
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUEventInfo {
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
25
SMMUEventType type;
17
set_float_detect_tininess(float_tininess_before_rounding,
26
uint32_t sid;
18
&env->fpu_status);
27
bool recorded;
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
28
- bool record_trans_faults;
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
29
bool inval_ste_allowed;
21
+ &env->fpu_status);
30
union {
22
/* fall through */
31
struct {
23
case RESET_TYPE_S390_CPU_NORMAL:
32
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
33
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/arm/smmu-common.h
27
--- a/fpu/softfloat-specialize.c.inc
35
+++ b/include/hw/arm/smmu-common.h
28
+++ b/fpu/softfloat-specialize.c.inc
36
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
37
bool disabled; /* smmu is disabled */
30
* a default NaN
38
bool bypassed; /* translation is bypassed */
31
*/
39
bool aborted; /* translation is aborted */
32
rule = float_infzeronan_dnan_never;
40
+ bool record_faults; /* record fault events */
33
-#elif defined(TARGET_S390X)
41
uint64_t ttb; /* TT base address */
34
- rule = float_infzeronan_dnan_always;
42
uint8_t oas; /* output address width */
35
#endif
43
uint8_t tbi; /* Top Byte Ignore */
44
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/smmuv3.c
47
+++ b/hw/arm/smmuv3.c
48
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
49
trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt->had);
50
}
36
}
51
37
52
- event->record_trans_faults = CD_R(cd);
53
+ cfg->record_faults = CD_R(cd);
54
55
return 0;
56
57
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
58
59
tt = select_tt(cfg, addr);
60
if (!tt) {
61
- if (event.record_trans_faults) {
62
+ if (cfg->record_faults) {
63
event.type = SMMU_EVT_F_TRANSLATION;
64
event.u.f_translation.addr = addr;
65
event.u.f_translation.rnw = flag & 0x1;
66
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
67
if (cached_entry) {
68
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
69
status = SMMU_TRANS_ERROR;
70
- if (event.record_trans_faults) {
71
+ if (cfg->record_faults) {
72
event.type = SMMU_EVT_F_PERMISSION;
73
event.u.f_permission.addr = addr;
74
event.u.f_permission.rnw = flag & 0x1;
75
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
76
event.u.f_walk_eabt.addr2 = ptw_info.addr;
77
break;
78
case SMMU_PTW_ERR_TRANSLATION:
79
- if (event.record_trans_faults) {
80
+ if (cfg->record_faults) {
81
event.type = SMMU_EVT_F_TRANSLATION;
82
event.u.f_translation.addr = addr;
83
event.u.f_translation.rnw = flag & 0x1;
84
}
85
break;
86
case SMMU_PTW_ERR_ADDR_SIZE:
87
- if (event.record_trans_faults) {
88
+ if (cfg->record_faults) {
89
event.type = SMMU_EVT_F_ADDR_SIZE;
90
event.u.f_addr_size.addr = addr;
91
event.u.f_addr_size.rnw = flag & 0x1;
92
}
93
break;
94
case SMMU_PTW_ERR_ACCESS:
95
- if (event.record_trans_faults) {
96
+ if (cfg->record_faults) {
97
event.type = SMMU_EVT_F_ACCESS;
98
event.u.f_access.addr = addr;
99
event.u.f_access.rnw = flag & 0x1;
100
}
101
break;
102
case SMMU_PTW_ERR_PERMISSION:
103
- if (event.record_trans_faults) {
104
+ if (cfg->record_faults) {
105
event.type = SMMU_EVT_F_PERMISSION;
106
event.u.f_permission.addr = addr;
107
event.u.f_permission.rnw = flag & 0x1;
108
--
38
--
109
2.25.1
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
[PULL 25/54] target/arm: Use tcg_constant for vector shift expanders
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-26-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate.c | 27 +++++++++------------------
8
target/mips/fpu_helper.h | 9 +++++++++
9
1 file changed, 9 insertions(+), 18 deletions(-)
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
10
12
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
15
--- a/target/mips/fpu_helper.h
14
+++ b/target/arm/translate.c
16
+++ b/target/mips/fpu_helper.h
15
@@ -XXX,XX +XXX,XX @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
16
} \
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
17
static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \
19
{
18
{ \
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
19
- TCGv_vec zero = tcg_const_zeros_vec_matching(d); \
21
+ FloatInfZeroNaNRule izn_rule;
20
+ TCGv_vec zero = tcg_constant_vec_matching(d, vece, 0); \
21
tcg_gen_cmp_vec(COND, vece, d, a, zero); \
22
- tcg_temp_free_vec(zero); \
23
} \
24
void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \
25
uint32_t opr_sz, uint32_t max_sz) \
26
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
27
TCGv_i32 rval = tcg_temp_new_i32();
28
TCGv_i32 lsh = tcg_temp_new_i32();
29
TCGv_i32 rsh = tcg_temp_new_i32();
30
- TCGv_i32 zero = tcg_const_i32(0);
31
- TCGv_i32 max = tcg_const_i32(32);
32
+ TCGv_i32 zero = tcg_constant_i32(0);
33
+ TCGv_i32 max = tcg_constant_i32(32);
34
22
35
/*
23
/*
36
* Rely on the TCG guarantee that out of range shifts produce
24
* With nan2008, SNaNs are silenced in the usual way.
37
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
38
tcg_temp_free_i32(rval);
26
*/
39
tcg_temp_free_i32(lsh);
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
40
tcg_temp_free_i32(rsh);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
41
- tcg_temp_free_i32(zero);
29
+ /*
42
- tcg_temp_free_i32(max);
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
43
}
37
}
44
38
45
void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
39
static inline void restore_fp_status(CPUMIPSState *env)
46
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
47
TCGv_i64 rval = tcg_temp_new_i64();
41
index XXXXXXX..XXXXXXX 100644
48
TCGv_i64 lsh = tcg_temp_new_i64();
42
--- a/target/mips/msa.c
49
TCGv_i64 rsh = tcg_temp_new_i64();
43
+++ b/target/mips/msa.c
50
- TCGv_i64 zero = tcg_const_i64(0);
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
51
- TCGv_i64 max = tcg_const_i64(64);
45
52
+ TCGv_i64 zero = tcg_constant_i64(0);
46
/* set proper signanling bit meaning ("1" means "quiet") */
53
+ TCGv_i64 max = tcg_constant_i64(64);
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
54
48
+
55
/*
49
+ /* Inf * 0 + NaN returns the input NaN */
56
* Rely on the TCG guarantee that out of range shifts produce
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
57
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
51
+ &env->active_tc.msa_fp_status);
58
tcg_temp_free_i64(rval);
59
tcg_temp_free_i64(lsh);
60
tcg_temp_free_i64(rsh);
61
- tcg_temp_free_i64(zero);
62
- tcg_temp_free_i64(max);
63
}
52
}
64
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
65
static void gen_ushl_vec(unsigned vece, TCGv_vec dst,
54
index XXXXXXX..XXXXXXX 100644
66
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
55
--- a/fpu/softfloat-specialize.c.inc
67
TCGv_i32 rval = tcg_temp_new_i32();
56
+++ b/fpu/softfloat-specialize.c.inc
68
TCGv_i32 lsh = tcg_temp_new_i32();
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
69
TCGv_i32 rsh = tcg_temp_new_i32();
58
/*
70
- TCGv_i32 zero = tcg_const_i32(0);
59
* Temporarily fall back to ifdef ladder
71
- TCGv_i32 max = tcg_const_i32(31);
60
*/
72
+ TCGv_i32 zero = tcg_constant_i32(0);
61
-#if defined(TARGET_MIPS)
73
+ TCGv_i32 max = tcg_constant_i32(31);
62
- if (snan_bit_is_one(status)) {
74
63
- /*
75
/*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
76
* Rely on the TCG guarantee that out of range shifts produce
65
- * case sets InvalidOp and returns the default NaN
77
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
66
- */
78
tcg_temp_free_i32(rval);
67
- rule = float_infzeronan_dnan_always;
79
tcg_temp_free_i32(lsh);
68
- } else {
80
tcg_temp_free_i32(rsh);
69
- /*
81
- tcg_temp_free_i32(zero);
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
82
- tcg_temp_free_i32(max);
71
- * case sets InvalidOp and returns the input value 'c'
83
}
72
- */
84
73
- rule = float_infzeronan_dnan_never;
85
void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
74
- }
86
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
75
-#elif defined(TARGET_SPARC) || \
87
TCGv_i64 rval = tcg_temp_new_i64();
76
+#if defined(TARGET_SPARC) || \
88
TCGv_i64 lsh = tcg_temp_new_i64();
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
89
TCGv_i64 rsh = tcg_temp_new_i64();
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
90
- TCGv_i64 zero = tcg_const_i64(0);
79
/*
91
- TCGv_i64 max = tcg_const_i64(63);
92
+ TCGv_i64 zero = tcg_constant_i64(0);
93
+ TCGv_i64 max = tcg_constant_i64(63);
94
95
/*
96
* Rely on the TCG guarantee that out of range shifts produce
97
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
98
tcg_temp_free_i64(rval);
99
tcg_temp_free_i64(lsh);
100
tcg_temp_free_i64(rsh);
101
- tcg_temp_free_i64(zero);
102
- tcg_temp_free_i64(max);
103
}
104
105
static void gen_sshl_vec(unsigned vece, TCGv_vec dst,
106
--
80
--
107
2.25.1
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
[PULL 19/54] target/arm: Use tcg_constant in simd fp/int conversion
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-20-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
7
---
9
---
8
target/arm/translate-a64.c | 26 ++++++--------------------
10
fpu/softfloat-parts.c.inc | 5 +++--
9
1 file changed, 6 insertions(+), 20 deletions(-)
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
10
13
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
16
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/translate-a64.c
17
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
16
int pass;
19
{
17
20
int which;
18
if (fracbits || size == MO_64) {
21
bool infzero = (ab_mask == float_cmask_infzero);
19
- tcg_shift = tcg_const_i32(fracbits);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
20
+ tcg_shift = tcg_constant_i32(fracbits);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
21
}
27
}
22
28
23
if (size == MO_64) {
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
24
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
25
}
35
}
26
36
27
tcg_temp_free_ptr(tcg_fpst);
37
if (which == 3) {
28
- if (tcg_shift) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
29
- tcg_temp_free_i32(tcg_shift);
39
index XXXXXXX..XXXXXXX 100644
30
- }
40
--- a/fpu/softfloat-specialize.c.inc
31
41
+++ b/fpu/softfloat-specialize.c.inc
32
clear_vec_high(s, elements << size == 16, rd);
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
33
}
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
34
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
44
*----------------------------------------------------------------------------*/
35
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
46
- bool infzero, float_status *status)
37
fracbits = (16 << size) - immhb;
47
+ bool infzero, bool have_snan, float_status *status)
38
- tcg_shift = tcg_const_i32(fracbits);
48
{
39
+ tcg_shift = tcg_constant_i32(fracbits);
49
/*
40
50
* We guarantee not to require the target to tell us how to
41
if (size == MO_64) {
42
int maxpass = is_scalar ? 1 : 2;
43
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
44
}
45
}
46
47
- tcg_temp_free_i32(tcg_shift);
48
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
49
tcg_temp_free_ptr(tcg_fpstatus);
50
tcg_temp_free_i32(tcg_rmode);
51
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
52
case 0x1c: /* FCVTAS */
53
case 0x3a: /* FCVTPS */
54
case 0x3b: /* FCVTZS */
55
- {
56
- TCGv_i32 tcg_shift = tcg_const_i32(0);
57
- gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
58
- tcg_temp_free_i32(tcg_shift);
59
+ gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
60
break;
61
- }
62
case 0x5a: /* FCVTNU */
63
case 0x5b: /* FCVTMU */
64
case 0x5c: /* FCVTAU */
65
case 0x7a: /* FCVTPU */
66
case 0x7b: /* FCVTZU */
67
- {
68
- TCGv_i32 tcg_shift = tcg_const_i32(0);
69
- gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
70
- tcg_temp_free_i32(tcg_shift);
71
+ gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
72
break;
73
- }
74
case 0x18: /* FRINTN */
75
case 0x19: /* FRINTM */
76
case 0x38: /* FRINTP */
77
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
78
79
if (is_double) {
80
TCGv_i64 tcg_op = tcg_temp_new_i64();
81
- TCGv_i64 tcg_zero = tcg_const_i64(0);
82
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
83
TCGv_i64 tcg_res = tcg_temp_new_i64();
84
NeonGenTwoDoubleOpFn *genfn;
85
bool swap = false;
86
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
87
write_vec_element(s, tcg_res, rd, pass, MO_64);
88
}
89
tcg_temp_free_i64(tcg_res);
90
- tcg_temp_free_i64(tcg_zero);
91
tcg_temp_free_i64(tcg_op);
92
93
clear_vec_high(s, !is_scalar, rd);
94
} else {
95
TCGv_i32 tcg_op = tcg_temp_new_i32();
96
- TCGv_i32 tcg_zero = tcg_const_i32(0);
97
+ TCGv_i32 tcg_zero = tcg_constant_i32(0);
98
TCGv_i32 tcg_res = tcg_temp_new_i32();
99
NeonGenTwoSingleOpFn *genfn;
100
bool swap = false;
101
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
102
}
103
}
104
tcg_temp_free_i32(tcg_res);
105
- tcg_temp_free_i32(tcg_zero);
106
tcg_temp_free_i32(tcg_op);
107
if (!is_scalar) {
108
clear_vec_high(s, is_q, rd);
109
--
51
--
110
2.25.1
52
2.34.1
diff view generated by jsdifflib
[PULL 41/54] target/arm: Use tcg_constant in WHILE
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
are NaNs. As a result different architectures have ended up with
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
different rules for propagating NaNs.
5
Message-id: 20220426163043.100432-42-richard.henderson@linaro.org
5
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
We want to make the propagation rule instead be selectable at
9
runtime, because:
10
* this will let us have multiple targets in one QEMU binary
11
* the Arm FEAT_AFP architectural feature includes letting
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
7
---
27
---
8
target/arm/translate-sve.c | 20 +++++++-------------
28
include/fpu/softfloat-helpers.h | 11 +++
9
1 file changed, 7 insertions(+), 13 deletions(-)
29
include/fpu/softfloat-types.h | 55 +++++++++++
10
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
12
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
35
--- a/include/fpu/softfloat-helpers.h
14
+++ b/target/arm/translate-sve.c
36
+++ b/include/fpu/softfloat-helpers.h
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a)
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
16
static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
38
status->float_2nan_prop_rule = rule;
39
}
40
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
42
+ float_status *status)
43
+{
44
+ status->float_3nan_prop_rule = rule;
45
+}
46
+
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
float_status *status)
17
{
49
{
18
TCGv_i64 op0, op1, t0, t1, tmax;
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
19
- TCGv_i32 t2, t3;
51
return status->float_2nan_prop_rule;
20
+ TCGv_i32 t2;
52
}
21
TCGv_ptr ptr;
53
22
unsigned vsz = vec_full_reg_size(s);
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
23
unsigned desc = 0;
55
+{
24
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
56
+ return status->float_3nan_prop_rule;
57
+}
58
+
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
60
{
61
return status->float_infzeronan_rule;
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
71
+
72
/*
73
* Software IEC/IEEE floating-point types.
74
*/
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
25
}
158
}
26
}
159
}
27
160
28
- tmax = tcg_const_i64(vsz >> a->esz);
161
+ if (rule == float_3nan_prop_none) {
29
+ tmax = tcg_constant_i64(vsz >> a->esz);
162
#if defined(TARGET_ARM)
30
if (eq) {
163
-
31
/* Equality means one more iteration. */
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
32
tcg_gen_addi_i64(t0, t0, 1);
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
33
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
166
- */
34
167
- if (is_snan(c_cls)) {
35
/* Bound to the maximum. */
168
- return 2;
36
tcg_gen_umin_i64(t0, t0, tmax);
169
- } else if (is_snan(a_cls)) {
37
- tcg_temp_free_i64(tmax);
170
- return 0;
38
171
- } else if (is_snan(b_cls)) {
39
/* Set the count to zero if the condition is false. */
172
- return 1;
40
tcg_gen_movi_i64(t1, 0);
173
- } else if (is_qnan(c_cls)) {
41
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
174
- return 2;
42
175
- } else if (is_qnan(a_cls)) {
43
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
176
- return 0;
44
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
177
- } else {
45
- t3 = tcg_const_i32(desc);
178
- return 1;
46
179
- }
47
ptr = tcg_temp_new_ptr();
180
+ /*
48
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
49
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
50
if (a->lt) {
183
+ */
51
- gen_helper_sve_whilel(t2, ptr, t2, t3);
184
+ rule = float_3nan_prop_s_cab;
52
+ gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
185
#elif defined(TARGET_MIPS)
53
} else {
186
- if (snan_bit_is_one(status)) {
54
- gen_helper_sve_whileg(t2, ptr, t2, t3);
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
55
+ gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc));
188
- if (is_snan(a_cls)) {
56
}
189
- return 0;
57
do_pred_flags(t2);
190
- } else if (is_snan(b_cls)) {
58
191
- return 1;
59
tcg_temp_free_ptr(ptr);
192
- } else if (is_snan(c_cls)) {
60
tcg_temp_free_i32(t2);
193
- return 2;
61
- tcg_temp_free_i32(t3);
194
- } else if (is_qnan(a_cls)) {
62
return true;
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
321
+ }
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
63
}
337
}
64
338
65
static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
339
/*----------------------------------------------------------------------------
66
{
67
TCGv_i64 op0, op1, diff, t1, tmax;
68
- TCGv_i32 t2, t3;
69
+ TCGv_i32 t2;
70
TCGv_ptr ptr;
71
unsigned vsz = vec_full_reg_size(s);
72
unsigned desc = 0;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
74
op0 = read_cpu_reg(s, a->rn, 1);
75
op1 = read_cpu_reg(s, a->rm, 1);
76
77
- tmax = tcg_const_i64(vsz);
78
+ tmax = tcg_constant_i64(vsz);
79
diff = tcg_temp_new_i64();
80
81
if (a->rw) {
82
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
83
84
/* Bound to the maximum. */
85
tcg_gen_umin_i64(diff, diff, tmax);
86
- tcg_temp_free_i64(tmax);
87
88
/* Since we're bounded, pass as a 32-bit type. */
89
t2 = tcg_temp_new_i32();
90
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
91
92
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
93
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
94
- t3 = tcg_const_i32(desc);
95
96
ptr = tcg_temp_new_ptr();
97
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
98
99
- gen_helper_sve_whilel(t2, ptr, t2, t3);
100
+ gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
101
do_pred_flags(t2);
102
103
tcg_temp_free_ptr(ptr);
104
tcg_temp_free_i32(t2);
105
- tcg_temp_free_i32(t3);
106
return true;
107
}
108
109
--
340
--
110
2.25.1
341
2.34.1
diff view generated by jsdifflib
[PULL 54/54] hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
The Arm SMMUv3 includes an optional feature equivalent to the CPU
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
FEAT_BBM, which permits an OS to switch a range of memory between
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
"covered by a huge page" and "covered by a sequence of normal pages"
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
4
without having to engage in the traditional 'break-before-make'
5
dance. (This is particularly important for the SMMU, because devices
6
performing I/O through an SMMU are less likely to be able to cope with
7
the window in the sequence where an access results in a translation
8
fault.) The SMMU spec explicitly notes that one of the valid ways to
9
be a BBM level 2 compliant implementation is:
10
* if there are multiple entries in the TLB for an address,
11
choose one of them and use it, ignoring the others
12
13
Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple
14
TLB entries for an address, because the translation table level is
15
part of the SMMUIOTLBKey, and so our IOTLB hashtable can include
16
entries for the same address where the leaf was at different levels
17
(i.e. both hugepage and normal page). Our TLB lookup implementation in
18
smmu_iotlb_lookup() will always find the entry with the lowest level
19
(i.e. it prefers the hugepage over the normal page) and ignore any
20
others. TLB invalidation correctly removes all TLB entries matching
21
the specified address or address range (unless the guest specifies the
22
leaf level explicitly, in which case it gets what it asked for). So we
23
can validly advertise support for BBML level 2.
24
25
Note that we still can't yet advertise ourselves as an SMMU v3.2,
26
because v3.2 requires support for the S2FWB feature, which we don't
27
yet implement.
28
4
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
32
Message-id: 20220426160422.2353158-4-peter.maydell@linaro.org
33
---
8
---
34
hw/arm/smmuv3-internal.h | 1 +
9
tests/fp/fp-bench.c | 1 +
35
hw/arm/smmuv3.c | 1 +
10
tests/fp/fp-test.c | 1 +
36
2 files changed, 2 insertions(+)
11
2 files changed, 2 insertions(+)
37
12
38
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
39
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/smmuv3-internal.h
15
--- a/tests/fp/fp-bench.c
41
+++ b/hw/arm/smmuv3-internal.h
16
+++ b/tests/fp/fp-bench.c
42
@@ -XXX,XX +XXX,XX @@ REG32(IDR2, 0x8)
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
43
REG32(IDR3, 0xc)
18
* doesn't specify match those used by the Arm architecture.
44
FIELD(IDR3, HAD, 2, 1);
19
*/
45
FIELD(IDR3, RIL, 10, 1);
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
46
+ FIELD(IDR3, BBML, 11, 2);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
47
REG32(IDR4, 0x10)
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
48
REG32(IDR5, 0x14)
23
49
FIELD(IDR5, OAS, 0, 3);
24
f = bench_funcs[operation][precision];
50
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
51
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/arm/smmuv3.c
27
--- a/tests/fp/fp-test.c
53
+++ b/hw/arm/smmuv3.c
28
+++ b/tests/fp/fp-test.c
54
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
55
30
* doesn't specify match those used by the Arm architecture.
56
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
31
*/
57
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
58
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
59
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
60
/* 4K, 16K and 64K granule support */
35
61
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
36
genCases_setLevel(test_level);
62
--
37
--
63
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 35/54] target/arm: Use tcg_constant in trans_CSEL
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-36-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate.c | 7 +++----
8
target/arm/cpu.c | 5 +++++
9
1 file changed, 3 insertions(+), 4 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
10
11
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
--- a/target/arm/cpu.c
14
+++ b/target/arm/translate.c
15
+++ b/target/arm/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
33
}
34
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/fpu/softfloat-specialize.c.inc
38
+++ b/fpu/softfloat-specialize.c.inc
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
16
}
40
}
17
41
18
/* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
42
if (rule == float_3nan_prop_none) {
19
+ zero = tcg_constant_i32(0);
43
-#if defined(TARGET_ARM)
20
if (a->rn == 15) {
44
- /*
21
- rn = tcg_const_i32(0);
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
22
+ rn = zero;
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
23
} else {
47
- */
24
rn = load_reg(s, a->rn);
48
- rule = float_3nan_prop_s_cab;
25
}
49
-#elif defined(TARGET_MIPS)
26
if (a->rm == 15) {
50
+#if defined(TARGET_MIPS)
27
- rm = tcg_const_i32(0);
51
if (snan_bit_is_one(status)) {
28
+ rm = zero;
52
rule = float_3nan_prop_s_abc;
29
} else {
53
} else {
30
rm = load_reg(s, a->rm);
31
}
32
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
33
}
34
35
arm_test_cc(&c, a->fcond);
36
- zero = tcg_const_i32(0);
37
tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
38
arm_free_cc(&c);
39
- tcg_temp_free_i32(zero);
40
41
store_reg(s, a->rd, rn);
42
tcg_temp_free_i32(rm);
43
--
54
--
44
2.25.1
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
[PULL 34/54] target/arm: Use tcg_constant in trans_CPS_v7m
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-35-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate.c | 9 +++------
8
target/mips/fpu_helper.h | 4 ++++
9
1 file changed, 3 insertions(+), 6 deletions(-)
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
10
12
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
15
--- a/target/mips/fpu_helper.h
14
+++ b/target/arm/translate.c
16
+++ b/target/mips/fpu_helper.h
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
16
return true;
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
32
}
33
34
static inline void restore_fp_status(CPUMIPSState *env)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
17
}
54
}
18
55
19
- tmp = tcg_const_i32(a->im);
56
if (rule == float_3nan_prop_none) {
20
+ tmp = tcg_constant_i32(a->im);
57
-#if defined(TARGET_MIPS)
21
/* FAULTMASK */
58
- if (snan_bit_is_one(status)) {
22
if (a->F) {
59
- rule = float_3nan_prop_s_abc;
23
- addr = tcg_const_i32(19);
60
- } else {
24
+ addr = tcg_constant_i32(19);
61
- rule = float_3nan_prop_s_cab;
25
gen_helper_v7m_msr(cpu_env, addr, tmp);
62
- }
26
- tcg_temp_free_i32(addr);
63
-#elif defined(TARGET_XTENSA)
27
}
64
+#if defined(TARGET_XTENSA)
28
/* PRIMASK */
65
if (status->use_first_nan) {
29
if (a->I) {
66
rule = float_3nan_prop_abc;
30
- addr = tcg_const_i32(16);
67
} else {
31
+ addr = tcg_constant_i32(16);
32
gen_helper_v7m_msr(cpu_env, addr, tmp);
33
- tcg_temp_free_i32(addr);
34
}
35
gen_rebuild_hflags(s, false);
36
- tcg_temp_free_i32(tmp);
37
gen_lookup_tb(s);
38
return true;
39
}
40
--
68
--
41
2.25.1
69
2.34.1
diff view generated by jsdifflib
[PULL 31/54] target/arm: Use tcg_constant for TT, SAT, SMMLA
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-32-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate.c | 14 +++++---------
8
target/xtensa/fpu_helper.c | 2 ++
9
1 file changed, 5 insertions(+), 9 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
10
11
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
--- a/target/xtensa/fpu_helper.c
14
+++ b/target/arm/translate.c
15
+++ b/target/xtensa/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_TT(DisasContext *s, arg_TT *a)
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
22
}
23
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
16
}
30
}
17
31
18
addr = load_reg(s, a->rn);
32
if (rule == float_3nan_prop_none) {
19
- tmp = tcg_const_i32((a->A << 1) | a->T);
33
-#if defined(TARGET_XTENSA)
20
- gen_helper_v7m_tt(tmp, cpu_env, addr, tmp);
34
- if (status->use_first_nan) {
21
+ tmp = tcg_temp_new_i32();
35
- rule = float_3nan_prop_abc;
22
+ gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a->T));
36
- } else {
23
tcg_temp_free_i32(addr);
37
- rule = float_3nan_prop_cba;
24
store_reg(s, a->rd, tmp);
38
- }
25
return true;
39
-#else
26
@@ -XXX,XX +XXX,XX @@ static bool trans_PKH(DisasContext *s, arg_PKH *a)
40
rule = float_3nan_prop_abc;
27
static bool op_sat(DisasContext *s, arg_sat *a,
41
-#endif
28
void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
29
{
30
- TCGv_i32 tmp, satimm;
31
+ TCGv_i32 tmp;
32
int shift = a->imm;
33
34
if (!ENABLE_ARCH_6) {
35
@@ -XXX,XX +XXX,XX @@ static bool op_sat(DisasContext *s, arg_sat *a,
36
tcg_gen_shli_i32(tmp, tmp, shift);
37
}
42
}
38
43
39
- satimm = tcg_const_i32(a->satimm);
44
assert(rule != float_3nan_prop_none);
40
- gen(tmp, cpu_env, tmp, satimm);
41
- tcg_temp_free_i32(satimm);
42
+ gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm));
43
44
store_reg(s, a->rd, tmp);
45
return true;
46
@@ -XXX,XX +XXX,XX @@ static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub)
47
* a non-zero multiplicand lowpart, and the correct result
48
* lowpart for rounding.
49
*/
50
- TCGv_i32 zero = tcg_const_i32(0);
51
- tcg_gen_sub2_i32(t2, t1, zero, t3, t2, t1);
52
- tcg_temp_free_i32(zero);
53
+ tcg_gen_sub2_i32(t2, t1, tcg_constant_i32(0), t3, t2, t1);
54
} else {
55
tcg_gen_add_i32(t1, t1, t3);
56
}
57
--
45
--
58
2.25.1
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
[PULL 11/54] target/arm: Use tcg_constant in disas_add_sum_imm*
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
HPPA is the only target that was using the default branch of the
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
ifdef ladder (other targets either do not use muladd or set
5
Message-id: 20220426163043.100432-12-richard.henderson@linaro.org
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
7
---
16
---
8
target/arm/translate-a64.c | 12 ++++--------
17
target/hppa/fpu_helper.c | 8 ++++++++
9
1 file changed, 4 insertions(+), 8 deletions(-)
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
10
20
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
23
--- a/target/hppa/fpu_helper.c
14
+++ b/target/arm/translate-a64.c
24
+++ b/target/hppa/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
16
tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
17
}
45
}
18
} else {
19
- TCGv_i64 tcg_imm = tcg_const_i64(imm);
20
+ TCGv_i64 tcg_imm = tcg_constant_i64(imm);
21
if (sub_op) {
22
gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
23
} else {
24
gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
25
}
26
- tcg_temp_free_i64(tcg_imm);
27
}
46
}
28
47
29
if (is_64bit) {
48
- if (rule == float_3nan_prop_none) {
30
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn)
49
- rule = float_3nan_prop_abc;
31
tcg_rd = cpu_reg_sp(s, rd);
50
- }
32
33
if (s->ata) {
34
- TCGv_i32 offset = tcg_const_i32(imm);
35
- TCGv_i32 tag_offset = tcg_const_i32(uimm4);
36
-
51
-
37
- gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset);
52
assert(rule != float_3nan_prop_none);
38
- tcg_temp_free_i32(tag_offset);
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
39
- tcg_temp_free_i32(offset);
54
/* We have at least one SNaN input and should prefer it */
40
+ gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn,
41
+ tcg_constant_i32(imm),
42
+ tcg_constant_i32(uimm4));
43
} else {
44
tcg_gen_addi_i64(tcg_rd, tcg_rn, imm);
45
gen_address_with_allocation_tag0(tcg_rd, tcg_rd);
46
--
55
--
47
2.25.1
56
2.34.1
diff view generated by jsdifflib
New patch
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
15
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/fpu/softfloat-helpers.h
19
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
21
status->snan_bit_is_one = val;
22
}
23
24
-static inline void set_use_first_nan(bool val, float_status *status)
25
-{
26
- status->use_first_nan = val;
27
-}
28
-
29
static inline void set_no_signaling_nans(bool val, float_status *status)
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
1
4
5
floatx80 is used only by:
6
i386
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
40
---
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
42
1 file changed, 10 insertions(+), 10 deletions(-)
43
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
75
76
--
77
2.34.1
diff view generated by jsdifflib
[PULL 28/54] target/arm: Use tcg_constant for op_s_{rri,rxi}_rot
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
This pattern appears to have been copied from target/riscv, where it
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
is used because the functions there do not have ready access to the
5
Message-id: 20220426163043.100432-29-richard.henderson@linaro.org
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
7
---
21
---
8
target/arm/translate.c | 11 +++++------
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
9
1 file changed, 5 insertions(+), 6 deletions(-)
23
1 file changed, 2 insertions(+), 4 deletions(-)
10
24
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
27
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/arm/translate.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a,
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
16
void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32),
30
} else if (float32_is_zero_or_denormal(f)) {
17
int logic_cc, StoreRegKind kind)
31
return sign ? 1 << 4 : 1 << 8;
18
{
32
} else if (float32_is_any_nan(f)) {
19
- TCGv_i32 tmp1, tmp2;
33
- float_status s = { }; /* for snan_bit_is_one */
20
+ TCGv_i32 tmp1;
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
21
uint32_t imm;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
22
36
} else {
23
imm = ror32(a->imm, a->rot);
37
return sign ? 1 << 3 : 1 << 7;
24
if (logic_cc && a->rot) {
25
tcg_gen_movi_i32(cpu_CF, imm >> 31);
26
}
38
}
27
- tmp2 = tcg_const_i32(imm);
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
28
tmp1 = load_reg(s, a->rn);
40
} else if (float64_is_zero_or_denormal(f)) {
29
41
return sign ? 1 << 4 : 1 << 8;
30
- gen(tmp1, tmp1, tmp2);
42
} else if (float64_is_any_nan(f)) {
31
- tcg_temp_free_i32(tmp2);
43
- float_status s = { }; /* for snan_bit_is_one */
32
+ gen(tmp1, tmp1, tcg_constant_i32(imm));
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
33
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
34
if (logic_cc) {
46
} else {
35
gen_logic_CC(tmp1);
47
return sign ? 1 << 3 : 1 << 7;
36
@@ -XXX,XX +XXX,XX @@ static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a,
37
if (logic_cc && a->rot) {
38
tcg_gen_movi_i32(cpu_CF, imm >> 31);
39
}
40
- tmp = tcg_const_i32(imm);
41
42
- gen(tmp, tmp);
43
+ tmp = tcg_temp_new_i32();
44
+ gen(tmp, tcg_constant_i32(imm));
45
+
46
if (logic_cc) {
47
gen_logic_CC(tmp);
48
}
48
}
49
--
49
--
50
2.25.1
50
2.34.1
diff view generated by jsdifflib
[PULL 08/54] target/arm: Use tcg_constant in gen_compare_and_swap_pair
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
2
9
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-9-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
7
---
13
---
8
target/arm/translate-a64.c | 6 ++----
14
target/m68k/fpu_helper.c | 6 ++----
9
1 file changed, 2 insertions(+), 4 deletions(-)
15
1 file changed, 2 insertions(+), 4 deletions(-)
10
16
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
19
--- a/target/m68k/fpu_helper.c
14
+++ b/target/arm/translate-a64.c
20
+++ b/target/m68k/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
16
tcg_temp_free_i64(cmp);
22
17
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
18
if (HAVE_CMPXCHG128) {
24
if (!floatx80_is_any_nan(fp_rem)) {
19
- TCGv_i32 tcg_rs = tcg_const_i32(rs);
25
- float_status fp_status = { };
20
+ TCGv_i32 tcg_rs = tcg_constant_i32(rs);
26
+ /* Use local temporary fp_status to set different rounding mode */
21
if (s->be_data == MO_LE) {
27
+ float_status fp_status = env->fp_status;
22
gen_helper_casp_le_parallel(cpu_env, tcg_rs,
28
uint32_t quotient;
23
clean_addr, t1, t2);
29
int sign;
24
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
30
25
gen_helper_casp_be_parallel(cpu_env, tcg_rs,
31
/* Calculate quotient directly using round to nearest mode */
26
clean_addr, t1, t2);
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
27
}
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
28
- tcg_temp_free_i32(tcg_rs);
34
- set_floatx80_rounding_precision(
29
} else {
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
30
gen_helper_exit_atomic(cpu_env);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
31
s->base.is_jmp = DISAS_NORETURN;
37
32
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
38
sign = extractFloatx80Sign(fp_quot.d);
33
TCGv_i64 a2 = tcg_temp_new_i64();
34
TCGv_i64 c1 = tcg_temp_new_i64();
35
TCGv_i64 c2 = tcg_temp_new_i64();
36
- TCGv_i64 zero = tcg_const_i64(0);
37
+ TCGv_i64 zero = tcg_constant_i64(0);
38
39
/* Load the two words, in memory order. */
40
tcg_gen_qemu_ld_i64(d1, clean_addr, memidx,
41
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
42
tcg_temp_free_i64(a2);
43
tcg_temp_free_i64(c1);
44
tcg_temp_free_i64(c2);
45
- tcg_temp_free_i64(zero);
46
47
/* Write back the data from memory to Rs. */
48
tcg_gen_mov_i64(s1, d1);
49
--
39
--
50
2.25.1
40
2.34.1
diff view generated by jsdifflib
[PULL 02/54] target/arm: Use tcg_constant in gen_mte_check*
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
2
9
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-3-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
7
---
13
---
8
target/arm/translate-a64.c | 10 ++--------
14
target/m68k/helper.c | 6 ++++--
9
1 file changed, 2 insertions(+), 8 deletions(-)
15
1 file changed, 4 insertions(+), 2 deletions(-)
10
16
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
19
--- a/target/m68k/helper.c
14
+++ b/target/arm/translate-a64.c
20
+++ b/target/m68k/helper.c
15
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
16
int core_idx)
22
CPUM68KState *env = &cpu->env;
17
{
23
18
if (tag_checked && s->mte_active[is_unpriv]) {
24
if (n < 8) {
19
- TCGv_i32 tcg_desc;
25
- float_status s = {};
20
TCGv_i64 ret;
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
21
int desc = 0;
27
+ float_status s = env->fp_status;
22
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
23
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
24
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
25
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
26
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1);
27
- tcg_desc = tcg_const_i32(desc);
28
29
ret = new_tmp_a64(s);
30
- gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
31
- tcg_temp_free_i32(tcg_desc);
32
+ gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
33
34
return ret;
35
}
29
}
36
@@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
30
switch (n) {
37
bool tag_checked, int size)
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
38
{
32
CPUM68KState *env = &cpu->env;
39
if (tag_checked && s->mte_active[0]) {
33
40
- TCGv_i32 tcg_desc;
34
if (n < 8) {
41
TCGv_i64 ret;
35
- float_status s = {};
42
int desc = 0;
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
43
37
+ float_status s = env->fp_status;
44
@@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
45
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
39
return 8;
46
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
47
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
48
- tcg_desc = tcg_const_i32(desc);
49
50
ret = new_tmp_a64(s);
51
- gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
52
- tcg_temp_free_i32(tcg_desc);
53
+ gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
54
55
return ret;
56
}
40
}
57
--
41
--
58
2.25.1
42
2.34.1
diff view generated by jsdifflib
[PULL 22/54] target/arm: Use tcg_constant for aa32 exceptions
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
To do this we need to pass the CPU env pointer in to the helper.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
5
Message-id: 20220426163043.100432-23-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
7
---
13
---
8
target/arm/translate.c | 32 +++++++-------------------------
14
target/sparc/helper.h | 4 ++--
9
1 file changed, 7 insertions(+), 25 deletions(-)
15
target/sparc/fop_helper.c | 8 ++++----
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
10
18
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
12
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
21
--- a/target/sparc/helper.h
14
+++ b/target/arm/translate.c
22
+++ b/target/sparc/helper.h
15
@@ -XXX,XX +XXX,XX @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var)
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
16
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
17
void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
32
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/sparc/fop_helper.c
37
+++ b/target/sparc/fop_helper.c
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
39
return finish_fcmp(env, r, GETPC());
40
}
41
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
18
{
44
{
19
- TCGv_i32 tmp_mask = tcg_const_i32(mask);
45
/*
20
- gen_helper_cpsr_write(cpu_env, var, tmp_mask);
46
* FLCMP never raises an exception nor modifies any FSR fields.
21
- tcg_temp_free_i32(tmp_mask);
47
* Perform the comparison with a dummy fp environment.
22
+ gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask));
48
*/
49
- float_status discard = { };
50
+ float_status discard = env->fp_status;
51
FloatRelation r;
52
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
55
g_assert_not_reached();
23
}
56
}
24
57
25
static void gen_rebuild_hflags(DisasContext *s, bool new_el)
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
26
@@ -XXX,XX +XXX,XX @@ static void gen_rebuild_hflags(DisasContext *s, bool new_el)
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
27
28
static void gen_exception_internal(int excp)
29
{
60
{
30
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
61
- float_status discard = { };
31
-
62
+ float_status discard = env->fp_status;
32
assert(excp_is_internal(excp));
63
FloatRelation r;
33
- gen_helper_exception_internal(cpu_env, tcg_excp);
64
34
- tcg_temp_free_i32(tcg_excp);
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
35
+ gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/sparc/translate.c
69
+++ b/target/sparc/translate.c
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
71
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
36
}
77
}
37
78
38
static void gen_singlestep_exception(DisasContext *s)
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
39
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
80
40
/* As with HVC, we may take an exception either before or after
81
src1 = gen_load_fpr_D(dc, a->rs1);
41
* the insn executes.
82
src2 = gen_load_fpr_D(dc, a->rs2);
42
*/
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
43
- TCGv_i32 tmp;
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
44
-
85
return advance_pc(dc);
45
gen_set_pc_im(s, s->pc_curr);
46
- tmp = tcg_const_i32(syn_aa32_smc());
47
- gen_helper_pre_smc(cpu_env, tmp);
48
- tcg_temp_free_i32(tmp);
49
+ gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
50
gen_set_pc_im(s, s->base.pc_next);
51
s->base.is_jmp = DISAS_SMC;
52
}
86
}
53
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
54
55
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
56
{
57
- TCGv_i32 tcg_syn;
58
-
59
gen_set_condexec(s);
60
gen_set_pc_im(s, s->pc_curr);
61
- tcg_syn = tcg_const_i32(syn);
62
- gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
63
- tcg_temp_free_i32(tcg_syn);
64
+ gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
65
s->base.is_jmp = DISAS_NORETURN;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s)
69
static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
70
TCGv_i32 tcg_el)
71
{
72
- TCGv_i32 tcg_excp;
73
- TCGv_i32 tcg_syn;
74
-
75
gen_set_condexec(s);
76
gen_set_pc_im(s, s->pc_curr);
77
- tcg_excp = tcg_const_i32(excp);
78
- tcg_syn = tcg_const_i32(syn);
79
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el);
80
- tcg_temp_free_i32(tcg_syn);
81
- tcg_temp_free_i32(tcg_excp);
82
+ gen_helper_exception_with_syndrome(cpu_env,
83
+ tcg_constant_i32(excp),
84
+ tcg_constant_i32(syn), tcg_el);
85
s->base.is_jmp = DISAS_NORETURN;
86
}
87
87
88
--
88
--
89
2.25.1
89
2.34.1
diff view generated by jsdifflib
[PULL 14/54] target/arm: Use tcg_constant in disas_cond_select
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
2
8
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Use env->fp_status instead of the dummy fp_status.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
5
Message-id: 20220426163043.100432-15-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
7
---
14
---
8
target/arm/translate-a64.c | 3 +--
15
target/ppc/fpu_helper.c | 3 +--
9
1 file changed, 1 insertion(+), 2 deletions(-)
16
1 file changed, 1 insertion(+), 2 deletions(-)
10
17
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
20
--- a/target/ppc/fpu_helper.c
14
+++ b/target/arm/translate-a64.c
21
+++ b/target/ppc/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
16
tcg_rd = cpu_reg(s, rd);
23
} else if (tp##_is_infinity(arg)) { \
17
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
18
a64_test_cc(&c, cond);
25
} else { \
19
- zero = tcg_const_i64(0);
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
20
+ zero = tcg_constant_i64(0);
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
21
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
22
if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
29
fprf = 0x00 << FPSCR_FPRF; \
23
/* CSET & CSETM. */
30
} else { \
24
@@ -XXX,XX +XXX,XX @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
31
fprf = 0x11 << FPSCR_FPRF; \
25
tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
26
}
27
28
- tcg_temp_free_i64(zero);
29
a64_free_cc(&c);
30
31
if (!sf) {
32
--
32
--
33
2.25.1
33
2.34.1
diff view generated by jsdifflib
[PULL 15/54] target/arm: Use tcg_constant in handle_{rev16,crc32}
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Now that float_status has a bunch of fp parameters,
4
it is easier to copy an existing structure than create
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
8
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-16-richard.henderson@linaro.org
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
14
---
8
target/arm/translate-a64.c | 7 ++-----
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
9
1 file changed, 2 insertions(+), 5 deletions(-)
16
1 file changed, 7 insertions(+), 13 deletions(-)
10
17
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
12
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
20
--- a/target/arm/tcg/vec_helper.c
14
+++ b/target/arm/translate-a64.c
21
+++ b/target/arm/tcg/vec_helper.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
16
TCGv_i64 tcg_rd = cpu_reg(s, rd);
23
* no effect on AArch32 instructions.
17
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
24
*/
18
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
19
- TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
26
- *statusp = (float_status){
20
+ TCGv_i64 mask = tcg_constant_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
27
- .tininess_before_rounding = float_tininess_before_rounding,
21
28
- .float_rounding_mode = float_round_to_odd_inf,
22
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
29
- .flush_to_zero = true,
23
tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
30
- .flush_inputs_to_zero = true,
24
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
31
- .default_nan_mode = true,
25
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
32
- };
26
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
33
+
27
34
+ *statusp = env->vfp.fp_status;
28
- tcg_temp_free_i64(mask);
35
+ set_default_nan_mode(true, statusp);
29
tcg_temp_free_i64(tcg_tmp);
36
30
}
37
if (ebf) {
31
38
- float_status *fpst = &env->vfp.fp_status;
32
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
33
}
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
34
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
35
tcg_acc = cpu_reg(s, rn);
42
-
36
- tcg_bytes = tcg_const_i32(1 << sz);
43
/* EBF=1 needs to do a step with round-to-odd semantics */
37
+ tcg_bytes = tcg_constant_i32(1 << sz);
44
*oddstatusp = *statusp;
38
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
39
if (crc32c) {
46
+ } else {
40
gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
47
+ set_flush_to_zero(true, statusp);
41
} else {
48
+ set_flush_inputs_to_zero(true, statusp);
42
gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
43
}
50
}
44
-
51
-
45
- tcg_temp_free_i32(tcg_bytes);
52
return ebf;
46
}
53
}
47
54
48
/* Data-processing (2 source)
49
--
55
--
50
2.25.1
56
2.34.1
57
58
diff view generated by jsdifflib
[PULL 42/54] target/arm: Use tcg_constant in LD1, ST1
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
2
6
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Add a field to float_status to specify the default NaN value; fall
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
back to the old ifdef behaviour if these are not set.
5
Message-id: 20220426163043.100432-43-richard.henderson@linaro.org
9
10
The default NaN value is specified by setting a uint8_t to a
11
pattern corresponding to the sign and upper fraction parts of
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
the pattern.
14
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
7
---
18
---
8
target/arm/translate-sve.c | 12 ++++--------
19
include/fpu/softfloat-helpers.h | 11 +++++++
9
1 file changed, 4 insertions(+), 8 deletions(-)
20
include/fpu/softfloat-types.h | 10 ++++++
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
10
23
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
12
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
26
--- a/include/fpu/softfloat-helpers.h
14
+++ b/target/arm/translate-sve.c
27
+++ b/include/fpu/softfloat-helpers.h
15
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
16
gen_helper_gvec_mem_scatter *fn = NULL;
29
status->float_infzeronan_rule = rule;
17
bool be = s->be_data == MO_BE;
18
bool mte = s->mte_active[0];
19
- TCGv_i64 imm;
20
21
if (a->esz < a->msz || (a->esz == a->msz && !a->u)) {
22
return false;
23
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
24
/* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x])
25
* by loading the immediate into the scalar parameter.
26
*/
27
- imm = tcg_const_i64(a->imm << a->msz);
28
- do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, false, fn);
29
- tcg_temp_free_i64(imm);
30
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
31
+ tcg_constant_i64(a->imm << a->msz), a->msz, false, fn);
32
return true;
33
}
30
}
34
31
35
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
36
gen_helper_gvec_mem_scatter *fn = NULL;
33
+ float_status *status)
37
bool be = s->be_data == MO_BE;
34
+{
38
bool mte = s->mte_active[0];
35
+ status->default_nan_pattern = dnan_pattern;
39
- TCGv_i64 imm;
36
+}
40
37
+
41
if (a->esz < a->msz) {
38
static inline void set_flush_to_zero(bool val, float_status *status)
42
return false;
39
{
43
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
40
status->flush_to_zero = val;
44
/* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x])
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
45
* by loading the immediate into the scalar parameter.
42
return status->float_infzeronan_rule;
46
*/
47
- imm = tcg_const_i64(a->imm << a->msz);
48
- do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, true, fn);
49
- tcg_temp_free_i64(imm);
50
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
51
+ tcg_constant_i64(a->imm << a->msz), a->msz, true, fn);
52
return true;
53
}
43
}
54
44
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
46
+{
47
+ return status->default_nan_pattern;
48
+}
49
+
50
static inline bool get_flush_to_zero(float_status *status)
51
{
52
return status->flush_to_zero;
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/include/fpu/softfloat-types.h
56
+++ b/include/fpu/softfloat-types.h
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
59
bool flush_inputs_to_zero;
60
bool default_nan_mode;
61
+ /*
62
+ * The pattern to use for the default NaN. Here the high bit specifies
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
136
+
137
+ sign = dnan_pattern >> 7;
138
+ /*
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
140
+ * and replecate bit [0] down into [55:0]
141
+ */
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
144
145
*p = (FloatParts64) {
146
.cls = float_class_qnan,
55
--
147
--
56
2.25.1
148
2.34.1
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
[PULL 53/54] target/arm: Advertise support for FEAT_BBM level 2
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
The description in the Arm ARM of the requirements of FEAT_BBM is
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
admirably clear on the guarantees it provides software, but slightly
2
parts64_default_nan().
3
more obscure on what that means for implementations. The description
4
of the equivalent SMMU feature in the SMMU specification (IHI0070D.b
5
section 3.21.1) is perhaps a bit more detailed and includes some
6
example valid implementation choices. (The SMMU version of this
7
feature is slightly tighter than the CPU version: the CPU is permitted
8
to raise TLB Conflict aborts in some situations that the SMMU may
9
not. This doesn't matter for QEMU because we don't want to do TLB
10
Conflict aborts anyway.)
11
12
The informal summary of FEAT_BBM is that it is about permitting an OS
13
to switch a range of memory between "covered by a huge page" and
14
"covered by a sequence of normal pages" without having to engage in
15
the 'break-before-make' dance that has traditionally been
16
necessary. The 'break-before-make' sequence is:
17
18
* replace the old translation table entry with an invalid entry
19
* execute a DSB insn
20
* execute a broadcast TLB invalidate insn
21
* execute a DSB insn
22
* write the new translation table entry
23
* execute a DSB insn
24
25
The point of this is to ensure that no TLB can simultaneously contain
26
TLB entries for the old and the new entry, which would traditionally
27
be UNPREDICTABLE (allowing the CPU to generate a TLB Conflict fault
28
or to use a random mishmash of values from the old and the new
29
entry). FEAT_BBM level 2 says "for the specific case where the only
30
thing that changed is the size of the block, the TLB is guaranteed
31
not to do weird things even if there are multiple entries for an
32
address", which means that software can now do:
33
34
* replace old translation table entry with new entry
35
* DSB
36
* broadcast TLB invalidate
37
* DSB
38
39
As the SMMU spec notes, valid ways to do this include:
40
41
* if there are multiple entries in the TLB for an address,
42
choose one of them and use it, ignoring the others
43
* if there are multiple entries in the TLB for an address,
44
throw them all out and do a page table walk to get a new one
45
46
QEMU's page table walk implementation for Arm CPUs already meets the
47
requirements for FEAT_BBM level 2. When we cache an entry in our TCG
48
TLB, we do so only for the specific (non-huge) page that the address
49
is in, and there is no way for the TLB data structure to ever have
50
more than one TLB entry for that page. (We handle huge pages only in
51
that we track what part of the address space is covered by huge pages
52
so that a TLB invalidate operation for an address in a huge page
53
results in an invalidation of the whole TLB.) We ignore the Contiguous
54
bit in page table entries, so we don't have to do anything for the
55
parts of FEAT_BBM that deal with changis to the Contiguous bit.
56
57
FEAT_BBM level 2 also requires that the nT bit in block descriptors
58
must be ignored; since commit 39a1fd25287f5dece5 we do this.
59
60
It's therefore safe for QEMU to advertise FEAT_BBM level 2 by
61
setting ID_AA64MMFR2_EL1.BBM to 2.
62
3
63
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
64
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
65
Message-id: 20220426160422.2353158-3-peter.maydell@linaro.org
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
66
---
7
---
67
docs/system/arm/emulation.rst | 1 +
8
target/microblaze/cpu.c | 2 ++
68
target/arm/cpu64.c | 1 +
9
fpu/softfloat-specialize.c.inc | 3 +--
69
2 files changed, 2 insertions(+)
10
2 files changed, 3 insertions(+), 2 deletions(-)
70
11
71
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
72
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
73
--- a/docs/system/arm/emulation.rst
14
--- a/target/microblaze/cpu.c
74
+++ b/docs/system/arm/emulation.rst
15
+++ b/target/microblaze/cpu.c
75
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
76
- FEAT_AA32HPD (AArch32 hierarchical permission disables)
17
* this architecture.
77
- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
18
*/
78
- FEAT_AES (AESD and AESE instructions)
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
79
+- FEAT_BBM at level 2 (Translation table break-before-make levels)
20
+ /* Default NaN: sign bit set, most significant frac bit set */
80
- FEAT_BF16 (AArch64 BFloat16 instructions)
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
81
- FEAT_BTI (Branch Target Identification)
22
82
- FEAT_DIT (Data Independent Timing instructions)
23
#if defined(CONFIG_USER_ONLY)
83
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
84
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/cpu64.c
27
--- a/fpu/softfloat-specialize.c.inc
86
+++ b/target/arm/cpu64.c
28
+++ b/fpu/softfloat-specialize.c.inc
87
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
88
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
89
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
31
/* Sign bit clear, all frac bits set */
90
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
32
dnan_pattern = 0b01111111;
91
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
cpu->isar.id_aa64mmfr2 = t;
34
- || defined(TARGET_MICROBLAZE)
93
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
94
t = cpu->isar.id_aa64zfr0;
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
95
--
39
--
96
2.25.1
40
2.34.1
diff view generated by jsdifflib
[PULL 52/54] target/arm: Advertise support for FEAT_TTL
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
The Arm FEAT_TTL architectural feature allows the guest to provide an
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
optional hint in an AArch64 TLB invalidate operation about which
2
parts64_default_nan().
3
translation table level holds the leaf entry for the address being
4
invalidated. QEMU's TLB implementation doesn't need that hint, and
5
we correctly ignore the (previously RES0) bits in TLB invalidate
6
operation values that are now used for the TTL field. So we can
7
simply advertise support for it in our 'max' CPU.
8
3
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
12
---
7
---
13
docs/system/arm/emulation.rst | 1 +
8
target/i386/tcg/fpu_helper.c | 4 ++++
14
target/arm/cpu64.c | 1 +
9
fpu/softfloat-specialize.c.inc | 3 ---
15
2 files changed, 2 insertions(+)
10
2 files changed, 4 insertions(+), 3 deletions(-)
16
11
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/arm/emulation.rst
14
--- a/target/i386/tcg/fpu_helper.c
20
+++ b/docs/system/arm/emulation.rst
15
+++ b/target/i386/tcg/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
22
- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
17
*/
23
- FEAT_TLBIRANGE (TLB invalidate range instructions)
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
24
- FEAT_TTCNP (Translation table Common not private translations)
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
25
+- FEAT_TTL (Translation Table Level)
20
+ /* Default NaN: sign bit set, most significant frac bit set */
26
- FEAT_TTST (Small translation tables)
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
27
- FEAT_UAO (Unprivileged Access Override control)
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
28
- FEAT_VHE (Virtualization Host Extensions)
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
29
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu64.c
29
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/target/arm/cpu64.c
30
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
34
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
35
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
33
/* Sign bit clear, all frac bits set */
36
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
34
dnan_pattern = 0b01111111;
37
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
38
cpu->isar.id_aa64mmfr2 = t;
36
- /* Sign bit set, most significant frac bit set */
39
37
- dnan_pattern = 0b11000000;
40
t = cpu->isar.id_aa64zfr0;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
41
--
42
2.25.1
42
2.34.1
diff view generated by jsdifflib
[PULL 43/54] target/arm: Use tcg_constant in SUBR
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-44-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate-sve.c | 4 +---
8
target/hppa/fpu_helper.c | 2 ++
9
1 file changed, 1 insertion(+), 3 deletions(-)
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
10
11
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
--- a/target/hppa/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
15
+++ b/target/hppa/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
16
}
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
17
if (sve_access_check(s)) {
18
/* For inf * 0 + NaN, return the input NaN */
18
unsigned vsz = vec_full_reg_size(s);
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
19
- TCGv_i64 c = tcg_const_i64(a->imm);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
20
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
21
vec_full_reg_offset(s, a->rn),
22
- vsz, vsz, c, &op[a->esz]);
23
- tcg_temp_free_i64(c);
24
+ vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]);
25
}
26
return true;
27
}
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
28
--
39
--
29
2.25.1
40
2.34.1
diff view generated by jsdifflib
[PULL 40/54] target/arm: Use tcg_constant in do_clast_scalar
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for the alpha target.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-41-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 7 +++----
7
target/alpha/cpu.c | 2 ++
9
1 file changed, 3 insertions(+), 4 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
12
--- a/target/alpha/cpu.c
14
+++ b/target/arm/translate-sve.c
13
+++ b/target/alpha/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
16
bool before, TCGv_i64 reg_val)
15
* operand in Fa. That is float_2nan_prop_ba.
17
{
16
*/
18
TCGv_i32 last = tcg_temp_new_i32();
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
19
- TCGv_i64 ele, cmp, zero;
18
+ /* Default NaN: sign bit clear, msb frac bit set */
20
+ TCGv_i64 ele, cmp;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
20
#if defined(CONFIG_USER_ONLY)
22
find_last_active(s, last, esz, pg);
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
23
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
24
@@ -XXX,XX +XXX,XX @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
25
ele = load_last_active(s, last, rm, esz);
26
tcg_temp_free_i32(last);
27
28
- zero = tcg_const_i64(0);
29
- tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, zero, ele, reg_val);
30
+ tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0),
31
+ ele, reg_val);
32
33
- tcg_temp_free_i64(zero);
34
tcg_temp_free_i64(cmp);
35
tcg_temp_free_i64(ele);
36
}
37
--
23
--
38
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 39/54] target/arm: Use tcg_constant in {incr, wrap}_last_active
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-40-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
7
---
9
---
8
target/arm/translate-sve.c | 12 ++++--------
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
9
1 file changed, 4 insertions(+), 8 deletions(-)
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
10
13
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
16
--- a/linux-user/arm/nwfpe/fpa11.c
14
+++ b/target/arm/translate-sve.c
17
+++ b/linux-user/arm/nwfpe/fpa11.c
15
@@ -XXX,XX +XXX,XX @@ static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz)
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
16
if (is_power_of_2(vsz)) {
19
* this late date.
17
tcg_gen_andi_i32(last, last, vsz - 1);
20
*/
18
} else {
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
19
- TCGv_i32 max = tcg_const_i32(vsz);
22
+ /*
20
- TCGv_i32 zero = tcg_const_i32(0);
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
21
+ TCGv_i32 max = tcg_constant_i32(vsz);
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
22
+ TCGv_i32 zero = tcg_constant_i32(0);
25
+ */
23
tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last);
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
24
- tcg_temp_free_i32(max);
25
- tcg_temp_free_i32(zero);
26
}
27
}
27
}
28
28
29
@@ -XXX,XX +XXX,XX @@ static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz)
29
void SetRoundingMode(const unsigned int opcode)
30
if (is_power_of_2(vsz)) {
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
31
tcg_gen_andi_i32(last, last, vsz - 1);
31
index XXXXXXX..XXXXXXX 100644
32
} else {
32
--- a/target/arm/cpu.c
33
- TCGv_i32 max = tcg_const_i32(vsz - (1 << esz));
33
+++ b/target/arm/cpu.c
34
- TCGv_i32 zero = tcg_const_i32(0);
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
35
+ TCGv_i32 max = tcg_constant_i32(vsz - (1 << esz));
35
* the pseudocode function the arguments are in the order c, a, b.
36
+ TCGv_i32 zero = tcg_constant_i32(0);
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
37
tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last);
37
* and the input NaN if it is signalling
38
- tcg_temp_free_i32(max);
38
+ * * Default NaN has sign bit clear, msb frac bit set
39
- tcg_temp_free_i32(zero);
39
*/
40
}
40
static void arm_set_default_fp_behaviours(float_status *s)
41
{
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
46
+ set_float_default_nan_pattern(0b01000000, s);
41
}
47
}
42
48
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
43
--
50
--
44
2.25.1
51
2.34.1
diff view generated by jsdifflib
[PULL 38/54] target/arm: Use tcg_constant in FCPY, CPY
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for loongarch.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-39-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 13 ++++---------
7
target/loongarch/tcg/fpu_helper.c | 2 ++
9
1 file changed, 4 insertions(+), 9 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
12
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/arm/translate-sve.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
if (sve_access_check(s)) {
15
*/
17
/* Decode the VFP immediate. */
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
18
uint64_t imm = vfp_expand_imm(a->esz, a->imm);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
19
- TCGv_i64 t_imm = tcg_const_i64(imm);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
20
- do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
- tcg_temp_free_i64(t_imm);
22
+ do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm));
23
}
24
return true;
25
}
20
}
26
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a)
21
27
return false;
22
int ieee_ex_to_loongarch(int xcpt)
28
}
29
if (sve_access_check(s)) {
30
- TCGv_i64 t_imm = tcg_const_i64(a->imm);
31
- do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
32
- tcg_temp_free_i64(t_imm);
33
+ do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm));
34
}
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
38
}
39
if (sve_access_check(s)) {
40
unsigned vsz = vec_full_reg_size(s);
41
- TCGv_i64 t_imm = tcg_const_i64(a->imm);
42
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
43
pred_full_reg_offset(s, a->pg),
44
- t_imm, vsz, vsz, 0, fns[a->esz]);
45
- tcg_temp_free_i64(t_imm);
46
+ tcg_constant_i64(a->imm),
47
+ vsz, vsz, 0, fns[a->esz]);
48
}
49
return true;
50
}
51
--
23
--
52
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 36/54] target/arm: Use tcg_constant for trans_INDEX_*
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for m68k.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-37-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-sve.c | 12 ++++--------
7
target/m68k/cpu.c | 2 ++
9
1 file changed, 4 insertions(+), 8 deletions(-)
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
13
--- a/target/m68k/cpu.c
14
+++ b/target/arm/translate-sve.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
16
* preceding paragraph for nonsignaling NaNs.
17
{
17
*/
18
if (sve_access_check(s)) {
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
- TCGv_i64 start = tcg_const_i64(a->imm1);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
- TCGv_i64 incr = tcg_const_i64(a->imm2);
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
+ TCGv_i64 start = tcg_constant_i64(a->imm1);
21
22
+ TCGv_i64 incr = tcg_constant_i64(a->imm2);
22
nan = floatx80_default_nan(&env->fp_status);
23
do_index(s, a->esz, a->rd, start, incr);
23
for (i = 0; i < 8; i++) {
24
- tcg_temp_free_i64(start);
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
- tcg_temp_free_i64(incr);
25
index XXXXXXX..XXXXXXX 100644
26
}
26
--- a/fpu/softfloat-specialize.c.inc
27
return true;
27
+++ b/fpu/softfloat-specialize.c.inc
28
}
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
@@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
30
31
{
31
if (dnan_pattern == 0) {
32
if (sve_access_check(s)) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
- TCGv_i64 start = tcg_const_i64(a->imm);
33
+#if defined(TARGET_SPARC)
34
+ TCGv_i64 start = tcg_constant_i64(a->imm);
34
/* Sign bit clear, all frac bits set */
35
TCGv_i64 incr = cpu_reg(s, a->rm);
35
dnan_pattern = 0b01111111;
36
do_index(s, a->esz, a->rd, start, incr);
36
#elif defined(TARGET_HEXAGON)
37
- tcg_temp_free_i64(start);
38
}
39
return true;
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
42
{
43
if (sve_access_check(s)) {
44
TCGv_i64 start = cpu_reg(s, a->rn);
45
- TCGv_i64 incr = tcg_const_i64(a->imm);
46
+ TCGv_i64 incr = tcg_constant_i64(a->imm);
47
do_index(s, a->esz, a->rd, start, incr);
48
- tcg_temp_free_i64(incr);
49
}
50
return true;
51
}
52
--
37
--
53
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 29/54] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-30-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
7
---
9
---
8
target/arm/translate.c | 11 +++--------
10
target/mips/fpu_helper.h | 7 +++++++
9
1 file changed, 3 insertions(+), 8 deletions(-)
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
10
13
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
16
--- a/target/mips/fpu_helper.h
14
+++ b/target/arm/translate.c
17
+++ b/target/mips/fpu_helper.h
15
@@ -XXX,XX +XXX,XX @@ static bool trans_ADR(DisasContext *s, arg_ri *a)
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
16
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
17
static bool trans_MOVW(DisasContext *s, arg_MOVW *a)
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
18
{
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
19
- TCGv_i32 tmp;
22
+ /*
20
-
23
+ * With nan2008, the default NaN value has the sign bit clear and the
21
if (!ENABLE_ARCH_6T2) {
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
22
return false;
25
+ * frac bits except the msb are set.
23
}
26
+ */
24
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
25
- tmp = tcg_const_i32(a->imm);
28
+ &env->active_fpu.fp_status);
26
- store_reg(s, a->rd, tmp);
29
27
+ store_reg(s, a->rd, tcg_constant_i32(a->imm));
28
return true;
29
}
30
}
30
31
31
@@ -XXX,XX +XXX,XX @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
32
t0 = load_reg(s, a->rm);
33
index XXXXXXX..XXXXXXX 100644
33
t1 = load_reg(s, a->rn);
34
--- a/target/mips/msa.c
34
tcg_gen_mulu2_i32(t0, t1, t0, t1);
35
+++ b/target/mips/msa.c
35
- zero = tcg_const_i32(0);
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
36
+ zero = tcg_constant_i32(0);
37
/* Inf * 0 + NaN returns the input NaN */
37
t2 = load_reg(s, a->ra);
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
38
tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
39
&env->active_tc.msa_fp_status);
39
tcg_temp_free_i32(t2);
40
+ /* Default NaN: sign bit clear, frac msb set */
40
t2 = load_reg(s, a->rd);
41
+ set_float_default_nan_pattern(0b01000000,
41
tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
42
+ &env->active_tc.msa_fp_status);
42
tcg_temp_free_i32(t2);
43
- tcg_temp_free_i32(zero);
44
store_reg(s, a->ra, t0);
45
store_reg(s, a->rd, t1);
46
return true;
47
@@ -XXX,XX +XXX,XX @@ static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz)
48
default:
49
g_assert_not_reached();
50
}
51
- t3 = tcg_const_i32(1 << sz);
52
+ t3 = tcg_constant_i32(1 << sz);
53
if (c) {
54
gen_helper_crc32c(t1, t1, t2, t3);
55
} else {
56
gen_helper_crc32(t1, t1, t2, t3);
57
}
58
tcg_temp_free_i32(t2);
59
- tcg_temp_free_i32(t3);
60
store_reg(s, a->rd, t1);
61
return true;
62
}
43
}
63
--
44
--
64
2.25.1
45
2.34.1
diff view generated by jsdifflib
[PULL 33/54] target/arm: Use tcg_constant in CLRM, DLS, WLS, LE
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for openrisc.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-34-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate.c | 16 +++++-----------
7
target/openrisc/cpu.c | 2 ++
9
1 file changed, 5 insertions(+), 11 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
12
--- a/target/openrisc/cpu.c
14
+++ b/target/arm/translate.c
13
+++ b/target/openrisc/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
16
15
*/
17
s->eci_handled = true;
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
18
17
19
- zero = tcg_const_i32(0);
18
+ /* Default NaN: sign bit clear, frac msb set */
20
+ zero = tcg_constant_i32(0);
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
21
for (i = 0; i < 15; i++) {
20
22
if (extract32(a->list, i, 1)) {
21
#ifndef CONFIG_USER_ONLY
23
/* Clear R[i] */
22
cpu->env.picmr = 0x00000000;
24
@@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
25
* Clear APSR (by calling the MSR helper with the same argument
26
* as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
27
*/
28
- TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
29
- gen_helper_v7m_msr(cpu_env, maskreg, zero);
30
- tcg_temp_free_i32(maskreg);
31
+ gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero);
32
}
33
- tcg_temp_free_i32(zero);
34
clear_eci_state(s);
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)
38
store_reg(s, 14, tmp);
39
if (a->size != 4) {
40
/* DLSTP: set FPSCR.LTPSIZE */
41
- tmp = tcg_const_i32(a->size);
42
- store_cpu_field(tmp, v7m.ltpsize);
43
+ store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize);
44
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
45
}
46
return true;
47
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
48
*/
49
bool ok = vfp_access_check(s);
50
assert(ok);
51
- tmp = tcg_const_i32(a->size);
52
- store_cpu_field(tmp, v7m.ltpsize);
53
+ store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize);
54
/*
55
* LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0)
56
* when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
57
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
58
gen_set_label(loopend);
59
if (a->tp) {
60
/* Exits from tail-pred loops must reset LTPSIZE to 4 */
61
- tmp = tcg_const_i32(4);
62
- store_cpu_field(tmp, v7m.ltpsize);
63
+ store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
64
}
65
/* End TB, continuing to following insn */
66
gen_jmp_tb(s, s->base.pc_next, 1);
67
--
23
--
68
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 32/54] target/arm: Use tcg_constant in LDM, STM
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for ppc.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-33-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate.c | 12 ++++--------
7
target/ppc/cpu_init.c | 4 ++++
9
1 file changed, 4 insertions(+), 8 deletions(-)
8
1 file changed, 4 insertions(+)
10
9
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
12
--- a/target/ppc/cpu_init.c
14
+++ b/target/arm/translate.c
13
+++ b/target/ppc/cpu_init.c
15
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
16
{
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
int i, j, n, list, mem_idx;
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
18
bool user = a->u;
17
19
- TCGv_i32 addr, tmp, tmp2;
18
+ /* Default NaN: sign bit clear, set frac msb */
20
+ TCGv_i32 addr, tmp;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
22
if (user) {
21
+
23
/* STM (user) */
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
24
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
23
ppc_spr_t *spr = &env->spr_cb[i];
25
24
26
if (user && i != 15) {
27
tmp = tcg_temp_new_i32();
28
- tmp2 = tcg_const_i32(i);
29
- gen_helper_get_user_reg(tmp, cpu_env, tmp2);
30
- tcg_temp_free_i32(tmp2);
31
+ gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i));
32
} else {
33
tmp = load_reg(s, i);
34
}
35
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
36
bool loaded_base;
37
bool user = a->u;
38
bool exc_return = false;
39
- TCGv_i32 addr, tmp, tmp2, loaded_var;
40
+ TCGv_i32 addr, tmp, loaded_var;
41
42
if (user) {
43
/* LDM (user), LDM (exception return) */
44
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
45
tmp = tcg_temp_new_i32();
46
gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
47
if (user) {
48
- tmp2 = tcg_const_i32(i);
49
- gen_helper_set_user_reg(cpu_env, tmp2, tmp);
50
- tcg_temp_free_i32(tmp2);
51
+ gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp);
52
tcg_temp_free_i32(tmp);
53
} else if (i == a->rn) {
54
loaded_var = tmp;
55
--
25
--
56
2.25.1
26
2.34.1
diff view generated by jsdifflib
[PULL 24/54] target/arm: Use tcg_constant for gen_{msr,mrs}
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
2
4
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-25-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
7
---
8
---
8
target/arm/translate.c | 22 +++++++++-------------
9
target/sh4/cpu.c | 2 ++
9
1 file changed, 9 insertions(+), 13 deletions(-)
10
1 file changed, 2 insertions(+)
10
11
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
--- a/target/sh4/cpu.c
14
+++ b/target/arm/translate.c
15
+++ b/target/sh4/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
16
tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
17
set_flush_to_zero(1, &env->fp_status);
17
tcg_gen_addi_i32(tcg_el, tcg_el, 3);
18
#endif
18
} else {
19
set_default_nan_mode(1, &env->fp_status);
19
- tcg_el = tcg_const_i32(3);
20
+ /* sign bit clear, set all frac bits other than msb */
20
+ tcg_el = tcg_constant_i32(3);
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
21
}
22
23
gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
24
@@ -XXX,XX +XXX,XX @@ undef:
25
26
static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
27
{
28
- TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
29
+ TCGv_i32 tcg_reg;
30
int tgtmode = 0, regno = 0;
31
32
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
33
@@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
34
gen_set_condexec(s);
35
gen_set_pc_im(s, s->pc_curr);
36
tcg_reg = load_reg(s, rn);
37
- tcg_tgtmode = tcg_const_i32(tgtmode);
38
- tcg_regno = tcg_const_i32(regno);
39
- gen_helper_msr_banked(cpu_env, tcg_reg, tcg_tgtmode, tcg_regno);
40
- tcg_temp_free_i32(tcg_tgtmode);
41
- tcg_temp_free_i32(tcg_regno);
42
+ gen_helper_msr_banked(cpu_env, tcg_reg,
43
+ tcg_constant_i32(tgtmode),
44
+ tcg_constant_i32(regno));
45
tcg_temp_free_i32(tcg_reg);
46
s->base.is_jmp = DISAS_UPDATE_EXIT;
47
}
22
}
48
23
49
static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
50
{
51
- TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
52
+ TCGv_i32 tcg_reg;
53
int tgtmode = 0, regno = 0;
54
55
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
56
@@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
57
gen_set_condexec(s);
58
gen_set_pc_im(s, s->pc_curr);
59
tcg_reg = tcg_temp_new_i32();
60
- tcg_tgtmode = tcg_const_i32(tgtmode);
61
- tcg_regno = tcg_const_i32(regno);
62
- gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_tgtmode, tcg_regno);
63
- tcg_temp_free_i32(tcg_tgtmode);
64
- tcg_temp_free_i32(tcg_regno);
65
+ gen_helper_mrs_banked(tcg_reg, cpu_env,
66
+ tcg_constant_i32(tgtmode),
67
+ tcg_constant_i32(regno));
68
store_reg(s, rn, tcg_reg);
69
s->base.is_jmp = DISAS_UPDATE_EXIT;
70
}
71
--
25
--
72
2.25.1
26
2.34.1
diff view generated by jsdifflib
[PULL 17/54] target/arm: Use tcg_constant in disas_fp*
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for rx.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-18-richard.henderson@linaro.org
6
[PMM: Restore incorrectly removed free of t_false in disas_fp_csel()]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
8
---
6
---
9
target/arm/translate-a64.c | 23 +++++++----------------
7
target/rx/cpu.c | 2 ++
10
1 file changed, 7 insertions(+), 16 deletions(-)
8
1 file changed, 2 insertions(+)
11
9
12
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
13
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate-a64.c
12
--- a/target/rx/cpu.c
15
+++ b/target/arm/translate-a64.c
13
+++ b/target/rx/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, int size,
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
17
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
18
tcg_vn = read_fp_dreg(s, rn);
16
*/
19
if (cmp_with_zero) {
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
- tcg_vm = tcg_const_i64(0);
18
+ /* Default NaN value: sign bit clear, set frac msb */
21
+ tcg_vm = tcg_constant_i64(0);
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
22
} else {
23
tcg_vm = read_fp_dreg(s, rm);
24
}
25
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
26
static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
27
{
28
unsigned int mos, type, rm, cond, rn, op, nzcv;
29
- TCGv_i64 tcg_flags;
30
TCGLabel *label_continue = NULL;
31
int size;
32
33
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
34
label_continue = gen_new_label();
35
arm_gen_test_cc(cond, label_match);
36
/* nomatch: */
37
- tcg_flags = tcg_const_i64(nzcv << 28);
38
- gen_set_nzcv(tcg_flags);
39
- tcg_temp_free_i64(tcg_flags);
40
+ gen_set_nzcv(tcg_constant_i64(nzcv << 28));
41
tcg_gen_br(label_continue);
42
gen_set_label(label_match);
43
}
44
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
45
static void disas_fp_csel(DisasContext *s, uint32_t insn)
46
{
47
unsigned int mos, type, rm, cond, rn, rd;
48
- TCGv_i64 t_true, t_false, t_zero;
49
+ TCGv_i64 t_true, t_false;
50
DisasCompare64 c;
51
MemOp sz;
52
53
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
54
read_vec_element(s, t_false, rm, 0, sz);
55
56
a64_test_cc(&c, cond);
57
- t_zero = tcg_const_i64(0);
58
- tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false);
59
- tcg_temp_free_i64(t_zero);
60
+ tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0),
61
+ t_true, t_false);
62
tcg_temp_free_i64(t_false);
63
a64_free_cc(&c);
64
65
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
66
int type = extract32(insn, 22, 2);
67
int mos = extract32(insn, 29, 3);
68
uint64_t imm;
69
- TCGv_i64 tcg_res;
70
MemOp sz;
71
72
if (mos || imm5) {
73
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
74
}
75
76
imm = vfp_expand_imm(sz, imm8);
77
-
78
- tcg_res = tcg_const_i64(imm);
79
- write_fp_dreg(s, rd, tcg_res);
80
- tcg_temp_free_i64(tcg_res);
81
+ write_fp_dreg(s, rd, tcg_constant_i64(imm));
82
}
20
}
83
21
84
/* Handle floating point <=> fixed point conversions. Note that we can
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
85
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
86
87
tcg_fpstatus = fpstatus_ptr(type == 3 ? FPST_FPCR_F16 : FPST_FPCR);
88
89
- tcg_shift = tcg_const_i32(64 - scale);
90
+ tcg_shift = tcg_constant_i32(64 - scale);
91
92
if (itof) {
93
TCGv_i64 tcg_int = cpu_reg(s, rn);
94
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
95
}
96
97
tcg_temp_free_ptr(tcg_fpstatus);
98
- tcg_temp_free_i32(tcg_shift);
99
}
100
101
/* Floating point <-> fixed point conversions
102
--
23
--
103
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 30/54] target/arm: Use tcg_constant for v7m MRS, MSR
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for s390x.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-31-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate.c | 7 +++----
7
target/s390x/cpu.c | 2 ++
9
1 file changed, 3 insertions(+), 4 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
12
--- a/target/s390x/cpu.c
14
+++ b/target/arm/translate.c
13
+++ b/target/s390x/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
16
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
17
return false;
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
18
}
17
&env->fpu_status);
19
- tmp = tcg_const_i32(a->sysm);
18
+ /* Default NaN value: sign bit clear, frac msb set */
20
- gen_helper_v7m_mrs(tmp, cpu_env, tmp);
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
21
+ tmp = tcg_temp_new_i32();
20
/* fall through */
22
+ gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm));
21
case RESET_TYPE_S390_CPU_NORMAL:
23
store_reg(s, a->rd, tmp);
22
env->psw.mask &= ~PSW_MASK_RI;
24
return true;
25
}
26
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
27
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
28
return false;
29
}
30
- addr = tcg_const_i32((a->mask << 10) | a->sysm);
31
+ addr = tcg_constant_i32((a->mask << 10) | a->sysm);
32
reg = load_reg(s, a->rn);
33
gen_helper_v7m_msr(cpu_env, addr, reg);
34
- tcg_temp_free_i32(addr);
35
tcg_temp_free_i32(reg);
36
/* If we wrote to CONTROL, the EL might have changed */
37
gen_rebuild_hflags(s, true);
38
--
23
--
39
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 26/54] target/arm: Use tcg_constant for do_coproc_insn
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-27-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
7
---
8
target/arm/translate.c | 43 +++++++++++++-----------------------------
8
target/sparc/cpu.c | 2 ++
9
1 file changed, 13 insertions(+), 30 deletions(-)
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
10
11
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
--- a/target/sparc/cpu.c
14
+++ b/target/arm/translate.c
15
+++ b/target/sparc/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
16
* Note that on XScale all cp0..c13 registers do an access check
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
17
* call in order to handle c15_cpar.
18
/* For inf * 0 + NaN, return the input NaN */
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
19
- TCGv_ptr tmpptr;
20
+ /* Default NaN value: sign bit clear, all frac bits set */
20
- TCGv_i32 tcg_syn, tcg_isread;
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
uint32_t syndrome;
22
22
23
cpu_exec_realizefn(cs, &local_err);
23
/* Note that since we are an implementation which takes an
24
if (local_err != NULL) {
24
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
26
index XXXXXXX..XXXXXXX 100644
26
gen_set_condexec(s);
27
--- a/fpu/softfloat-specialize.c.inc
27
gen_set_pc_im(s, s->pc_curr);
28
+++ b/fpu/softfloat-specialize.c.inc
28
- tmpptr = tcg_const_ptr(ri);
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
- tcg_syn = tcg_const_i32(syndrome);
30
uint8_t dnan_pattern = status->default_nan_pattern;
30
- tcg_isread = tcg_const_i32(isread);
31
31
- gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn,
32
if (dnan_pattern == 0) {
32
- tcg_isread);
33
-#if defined(TARGET_SPARC)
33
- tcg_temp_free_ptr(tmpptr);
34
- /* Sign bit clear, all frac bits set */
34
- tcg_temp_free_i32(tcg_syn);
35
- dnan_pattern = 0b01111111;
35
- tcg_temp_free_i32(tcg_isread);
36
-#elif defined(TARGET_HEXAGON)
36
+ gen_helper_access_check_cp_reg(cpu_env,
37
+#if defined(TARGET_HEXAGON)
37
+ tcg_constant_ptr(ri),
38
/* Sign bit set, all frac bits set. */
38
+ tcg_constant_i32(syndrome),
39
dnan_pattern = 0b11111111;
39
+ tcg_constant_i32(isread));
40
#else
40
} else if (ri->type & ARM_CP_RAISES_EXC) {
41
/*
42
* The readfn or writefn might raise an exception;
43
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
44
TCGv_i64 tmp64;
45
TCGv_i32 tmp;
46
if (ri->type & ARM_CP_CONST) {
47
- tmp64 = tcg_const_i64(ri->resetvalue);
48
+ tmp64 = tcg_constant_i64(ri->resetvalue);
49
} else if (ri->readfn) {
50
- TCGv_ptr tmpptr;
51
tmp64 = tcg_temp_new_i64();
52
- tmpptr = tcg_const_ptr(ri);
53
- gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
54
- tcg_temp_free_ptr(tmpptr);
55
+ gen_helper_get_cp_reg64(tmp64, cpu_env,
56
+ tcg_constant_ptr(ri));
57
} else {
58
tmp64 = tcg_temp_new_i64();
59
tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
60
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
61
} else {
62
TCGv_i32 tmp;
63
if (ri->type & ARM_CP_CONST) {
64
- tmp = tcg_const_i32(ri->resetvalue);
65
+ tmp = tcg_constant_i32(ri->resetvalue);
66
} else if (ri->readfn) {
67
- TCGv_ptr tmpptr;
68
tmp = tcg_temp_new_i32();
69
- tmpptr = tcg_const_ptr(ri);
70
- gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
71
- tcg_temp_free_ptr(tmpptr);
72
+ gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
73
} else {
74
tmp = load_cpu_offset(ri->fieldoffset);
75
}
76
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
77
tcg_temp_free_i32(tmplo);
78
tcg_temp_free_i32(tmphi);
79
if (ri->writefn) {
80
- TCGv_ptr tmpptr = tcg_const_ptr(ri);
81
- gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
82
- tcg_temp_free_ptr(tmpptr);
83
+ gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
84
+ tmp64);
85
} else {
86
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
87
}
88
tcg_temp_free_i64(tmp64);
89
} else {
90
+ TCGv_i32 tmp = load_reg(s, rt);
91
if (ri->writefn) {
92
- TCGv_i32 tmp;
93
- TCGv_ptr tmpptr;
94
- tmp = load_reg(s, rt);
95
- tmpptr = tcg_const_ptr(ri);
96
- gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
97
- tcg_temp_free_ptr(tmpptr);
98
+ gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
99
tcg_temp_free_i32(tmp);
100
} else {
101
- TCGv_i32 tmp = load_reg(s, rt);
102
store_cpu_offset(tmp, ri->fieldoffset, 4);
103
}
104
}
105
--
41
--
106
2.25.1
42
2.34.1
diff view generated by jsdifflib
[PULL 13/54] target/arm: Use tcg_constant in shift_reg_imm
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for xtensa.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-14-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-a64.c | 6 +-----
7
target/xtensa/cpu.c | 2 ++
9
1 file changed, 1 insertion(+), 5 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
12
--- a/target/xtensa/cpu.c
14
+++ b/target/arm/translate-a64.c
13
+++ b/target/xtensa/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
16
if (shift_i == 0) {
15
/* For inf * 0 + NaN, return the input NaN */
17
tcg_gen_mov_i64(dst, src);
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
18
} else {
17
set_no_signaling_nans(!dfpu, &env->fp_status);
19
- TCGv_i64 shift_const;
18
+ /* Default NaN value: sign bit clear, set frac msb */
20
-
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
- shift_const = tcg_const_i64(shift_i);
20
xtensa_use_first_nan(env, !dfpu);
22
- shift_reg(dst, src, sf, shift_type, shift_const);
23
- tcg_temp_free_i64(shift_const);
24
+ shift_reg(dst, src, sf, shift_type, tcg_constant_i64(shift_i));
25
}
26
}
21
}
27
22
28
--
23
--
29
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 03/54] target/arm: Use tcg_constant in gen_exception*
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
2
4
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
7
---
8
---
8
target/arm/translate-a64.c | 11 ++---------
9
target/hexagon/cpu.c | 2 ++
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
10
12
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
15
--- a/target/hexagon/cpu.c
14
+++ b/target/arm/translate-a64.c
16
+++ b/target/hexagon/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_rebuild_hflags(DisasContext *s)
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
16
18
17
static void gen_exception_internal(int excp)
19
set_default_nan_mode(1, &env->fp_status);
18
{
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
19
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
21
+ /* Default NaN value: sign bit set, all frac bits set */
20
-
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
21
assert(excp_is_internal(excp));
22
- gen_helper_exception_internal(cpu_env, tcg_excp);
23
- tcg_temp_free_i32(tcg_excp);
24
+ gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
25
}
23
}
26
24
27
static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
28
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
29
27
index XXXXXXX..XXXXXXX 100644
30
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
28
--- a/fpu/softfloat-specialize.c.inc
31
{
29
+++ b/fpu/softfloat-specialize.c.inc
32
- TCGv_i32 tcg_syn;
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
33
-
31
uint8_t dnan_pattern = status->default_nan_pattern;
34
gen_a64_set_pc_im(s->pc_curr);
32
35
- tcg_syn = tcg_const_i32(syndrome);
33
if (dnan_pattern == 0) {
36
- gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
34
-#if defined(TARGET_HEXAGON)
37
- tcg_temp_free_i32(tcg_syn);
35
- /* Sign bit set, all frac bits set. */
38
+ gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
36
- dnan_pattern = 0b11111111;
39
s->base.is_jmp = DISAS_NORETURN;
37
-#else
40
}
38
/*
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
42
/* sign bit clear, set frac msb */
43
dnan_pattern = 0b01000000;
44
}
45
-#endif
46
}
47
assert(dnan_pattern != 0);
41
48
42
--
49
--
43
2.25.1
50
2.34.1
diff view generated by jsdifflib
[PULL 23/54] target/arm: Use tcg_constant for disas_iwmmxt_insn
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for riscv.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-24-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate.c | 25 ++++++++++---------------
7
target/riscv/cpu.c | 2 ++
9
1 file changed, 10 insertions(+), 15 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
12
--- a/target/riscv/cpu.c
14
+++ b/target/arm/translate.c
13
+++ b/target/riscv/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
16
gen_op_iwmmxt_movq_M0_wRn(wrd);
15
cs->exception_index = RISCV_EXCP_NONE;
17
switch ((insn >> 6) & 3) {
16
env->load_res = -1;
18
case 0:
17
set_default_nan_mode(1, &env->fp_status);
19
- tmp2 = tcg_const_i32(0xff);
18
+ /* Default NaN value: sign bit clear, frac msb set */
20
- tmp3 = tcg_const_i32((insn & 7) << 3);
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
+ tmp2 = tcg_constant_i32(0xff);
20
env->vill = true;
22
+ tmp3 = tcg_constant_i32((insn & 7) << 3);
21
23
break;
22
#ifndef CONFIG_USER_ONLY
24
case 1:
25
- tmp2 = tcg_const_i32(0xffff);
26
- tmp3 = tcg_const_i32((insn & 3) << 4);
27
+ tmp2 = tcg_constant_i32(0xffff);
28
+ tmp3 = tcg_constant_i32((insn & 3) << 4);
29
break;
30
case 2:
31
- tmp2 = tcg_const_i32(0xffffffff);
32
- tmp3 = tcg_const_i32((insn & 1) << 5);
33
+ tmp2 = tcg_constant_i32(0xffffffff);
34
+ tmp3 = tcg_constant_i32((insn & 1) << 5);
35
break;
36
default:
37
- tmp2 = NULL;
38
- tmp3 = NULL;
39
+ g_assert_not_reached();
40
}
41
gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
42
- tcg_temp_free_i32(tmp3);
43
- tcg_temp_free_i32(tmp2);
44
tcg_temp_free_i32(tmp);
45
gen_op_iwmmxt_movq_wRn_M0(wrd);
46
gen_op_iwmmxt_set_mup();
47
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
48
rd0 = (insn >> 16) & 0xf;
49
rd1 = (insn >> 0) & 0xf;
50
gen_op_iwmmxt_movq_M0_wRn(rd0);
51
- tmp = tcg_const_i32((insn >> 20) & 3);
52
iwmmxt_load_reg(cpu_V1, rd1);
53
- gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
54
- tcg_temp_free_i32(tmp);
55
+ gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1,
56
+ tcg_constant_i32((insn >> 20) & 3));
57
gen_op_iwmmxt_movq_wRn_M0(wrd);
58
gen_op_iwmmxt_set_mup();
59
break;
60
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
61
wrd = (insn >> 12) & 0xf;
62
rd0 = (insn >> 16) & 0xf;
63
gen_op_iwmmxt_movq_M0_wRn(rd0);
64
- tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
65
+ tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
66
gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
67
- tcg_temp_free_i32(tmp);
68
gen_op_iwmmxt_movq_wRn_M0(wrd);
69
gen_op_iwmmxt_set_mup();
70
gen_op_iwmmxt_set_cup();
71
--
23
--
72
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 09/54] target/arm: Use tcg_constant in disas_ld_lit
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for tricore.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-10-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
7
---
6
---
8
target/arm/translate-a64.c | 3 +--
7
target/tricore/helper.c | 2 ++
9
1 file changed, 1 insertion(+), 2 deletions(-)
8
1 file changed, 2 insertions(+)
10
9
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
12
--- a/target/tricore/helper.c
14
+++ b/target/arm/translate-a64.c
13
+++ b/target/tricore/helper.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
16
15
set_flush_to_zero(1, &env->fp_status);
17
tcg_rt = cpu_reg(s, rt);
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
18
17
set_default_nan_mode(1, &env->fp_status);
19
- clean_addr = tcg_const_i64(s->pc_curr + imm);
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
20
+ clean_addr = tcg_constant_i64(s->pc_curr + imm);
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
if (is_vector) {
22
do_fp_ld(s, rt, clean_addr, size);
23
} else {
24
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
25
do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
26
false, true, rt, iss_sf, false);
27
}
28
- tcg_temp_free_i64(clean_addr);
29
}
20
}
30
21
31
/*
22
uint32_t psw_read(CPUTriCoreState *env)
32
--
23
--
33
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 12/54] target/arm: Use tcg_constant in disas_movw_imm
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
2
4
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-13-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
7
---
8
---
8
target/arm/translate-a64.c | 5 +----
9
fpu/softfloat-specialize.c.inc | 14 --------------
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
1 file changed, 14 deletions(-)
10
11
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
--- a/fpu/softfloat-specialize.c.inc
14
+++ b/target/arm/translate-a64.c
15
+++ b/fpu/softfloat-specialize.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
16
int opc = extract32(insn, 29, 2);
17
uint64_t frac;
17
int pos = extract32(insn, 21, 2) << 4;
18
uint8_t dnan_pattern = status->default_nan_pattern;
18
TCGv_i64 tcg_rd = cpu_reg(s, rd);
19
19
- TCGv_i64 tcg_imm;
20
- if (dnan_pattern == 0) {
20
21
- /*
21
if (!sf && (pos >= 32)) {
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
22
unallocated_encoding(s);
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
23
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
24
- * do not have floating-point.
24
tcg_gen_movi_i64(tcg_rd, imm);
25
- */
25
break;
26
- if (snan_bit_is_one(status)) {
26
case 3: /* MOVK */
27
- /* sign bit clear, set all frac bits other than msb */
27
- tcg_imm = tcg_const_i64(imm);
28
- dnan_pattern = 0b00111111;
28
- tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
29
- } else {
29
- tcg_temp_free_i64(tcg_imm);
30
- /* sign bit clear, set frac msb */
30
+ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16);
31
- dnan_pattern = 0b01000000;
31
if (!sf) {
32
- }
32
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
33
- }
33
}
34
assert(dnan_pattern != 0);
35
36
sign = dnan_pattern >> 7;
34
--
37
--
35
2.25.1
38
2.34.1
diff view generated by jsdifflib
[PULL 45/54] target/arm: Use tcg_constant for predicate descriptors
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In these cases, 't' did double-duty as zero source and
3
Inline pickNaNMulAdd into its only caller. This makes
4
temporary destination. Split the two uses.
4
one assert redundant with the immediately preceding IF.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20220426163043.100432-46-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-sve.c | 17 ++++++++---------
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
12
1 file changed, 8 insertions(+), 9 deletions(-)
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
14
2 files changed, 40 insertions(+), 55 deletions(-)
13
15
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
18
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-sve.c
19
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
TCGv_ptr dptr = tcg_temp_new_ptr();
21
TCGv_ptr gptr = tcg_temp_new_ptr();
22
- TCGv_i32 t;
23
+ TCGv_i32 t = tcg_temp_new_i32();
24
25
tcg_gen_addi_ptr(dptr, cpu_env, dofs);
26
tcg_gen_addi_ptr(gptr, cpu_env, gofs);
27
- t = tcg_const_i32(words);
28
29
- gen_helper_sve_predtest(t, dptr, gptr, t);
30
+ gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words));
31
tcg_temp_free_ptr(dptr);
32
tcg_temp_free_ptr(gptr);
33
34
@@ -XXX,XX +XXX,XX @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
35
36
tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd));
37
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn));
38
- t = tcg_const_i32(desc);
39
+ t = tcg_temp_new_i32();
40
41
- gen_fn(t, t_pd, t_pg, t);
42
+ gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc));
43
tcg_temp_free_ptr(t_pd);
44
tcg_temp_free_ptr(t_pg);
45
46
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
47
}
21
}
48
22
49
vsz = vec_full_reg_size(s);
23
if (s->default_nan_mode) {
50
- t = tcg_const_i32(simd_desc(vsz, vsz, 0));
24
+ /*
51
+ t = tcg_temp_new_i32();
25
+ * We guarantee not to require the target to tell us how to
52
pd = tcg_temp_new_ptr();
26
+ * pick a NaN if we're always returning the default NaN.
53
zn = tcg_temp_new_ptr();
27
+ * But if we're not in default-NaN mode then the target must
54
zm = tcg_temp_new_ptr();
28
+ * specify.
55
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
29
+ */
56
tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm));
30
which = 3;
57
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
31
+ } else if (infzero) {
58
32
+ /*
59
- gen_fn(t, pd, zn, zm, pg, t);
33
+ * Inf * 0 + NaN -- some implementations return the
60
+ gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0)));
34
+ * default NaN here, and some return the input NaN.
61
35
+ */
62
tcg_temp_free_ptr(pd);
36
+ switch (s->float_infzeronan_rule) {
63
tcg_temp_free_ptr(zn);
37
+ case float_infzeronan_dnan_never:
64
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
53
+
54
+ assert(rule != float_3nan_prop_none);
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
56
+ /* We have at least one SNaN input and should prefer it */
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
61
+ } else {
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
66
+ }
65
}
67
}
66
68
67
vsz = vec_full_reg_size(s);
69
if (which == 3) {
68
- t = tcg_const_i32(simd_desc(vsz, vsz, a->imm));
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
69
+ t = tcg_temp_new_i32();
71
index XXXXXXX..XXXXXXX 100644
70
pd = tcg_temp_new_ptr();
72
--- a/fpu/softfloat-specialize.c.inc
71
zn = tcg_temp_new_ptr();
73
+++ b/fpu/softfloat-specialize.c.inc
72
pg = tcg_temp_new_ptr();
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
73
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
75
}
74
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
76
}
75
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
77
76
78
-/*----------------------------------------------------------------------------
77
- gen_fn(t, pd, zn, pg, t);
79
-| Select which NaN to propagate for a three-input operation.
78
+ gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm)));
80
-| For the moment we assume that no CPU needs the 'larger significand'
79
81
-| information.
80
tcg_temp_free_ptr(pd);
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
81
tcg_temp_free_ptr(zn);
83
-*----------------------------------------------------------------------------*/
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
85
- bool infzero, bool have_snan, float_status *status)
86
-{
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
89
- int which;
90
-
91
- /*
92
- * We guarantee not to require the target to tell us how to
93
- * pick a NaN if we're always returning the default NaN.
94
- * But if we're not in default-NaN mode then the target must
95
- * specify.
96
- */
97
- assert(!status->default_nan_mode);
98
-
99
- if (infzero) {
100
- /*
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
106
- return 2;
107
- case float_infzeronan_dnan_always:
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
114
- }
115
-
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
123
- } else {
124
- do {
125
- which = rule & R_3NAN_1ST_MASK;
126
- rule >>= R_3NAN_1ST_LENGTH;
127
- } while (!is_nan(cls[which]));
128
- }
129
- return which;
130
-}
131
-
132
/*----------------------------------------------------------------------------
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
134
| NaN; otherwise returns 0.
82
--
135
--
83
2.25.1
136
2.34.1
137
138
diff view generated by jsdifflib
[PULL 01/54] target/arm: Use tcg_constant in gen_probe_access
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remove "3" as a special case for which and simply
4
branch to return the desired value.
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20220426163043.100432-2-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/translate-a64.c | 12 ++++--------
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
9
1 file changed, 4 insertions(+), 8 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
10
13
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
16
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/translate-a64.c
17
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
16
static void gen_probe_access(DisasContext *s, TCGv_i64 ptr,
19
* But if we're not in default-NaN mode then the target must
17
MMUAccessType acc, int log2_size)
20
* specify.
18
{
21
*/
19
- TCGv_i32 t_acc = tcg_const_i32(acc);
22
- which = 3;
20
- TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s));
23
+ goto default_nan;
21
- TCGv_i32 t_size = tcg_const_i32(1 << log2_size);
24
} else if (infzero) {
25
/*
26
* Inf * 0 + NaN -- some implementations return the
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
28
*/
29
switch (s->float_infzeronan_rule) {
30
case float_infzeronan_dnan_never:
31
- which = 2;
32
break;
33
case float_infzeronan_dnan_always:
34
- which = 3;
35
- break;
36
+ goto default_nan;
37
case float_infzeronan_dnan_if_qnan:
38
- which = is_qnan(c->cls) ? 3 : 2;
39
+ if (is_qnan(c->cls)) {
40
+ goto default_nan;
41
+ }
42
break;
43
default:
44
g_assert_not_reached();
45
}
46
+ which = 2;
47
} else {
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
51
}
52
}
53
54
- if (which == 3) {
55
- parts_default_nan(a, s);
56
- return a;
57
- }
22
-
58
-
23
- gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size);
59
switch (which) {
24
- tcg_temp_free_i32(t_acc);
60
case 0:
25
- tcg_temp_free_i32(t_idx);
61
break;
26
- tcg_temp_free_i32(t_size);
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
27
+ gen_helper_probe_access(cpu_env, ptr,
63
parts_silence_nan(a, s);
28
+ tcg_constant_i32(acc),
64
}
29
+ tcg_constant_i32(get_mem_index(s)),
65
return a;
30
+ tcg_constant_i32(1 << log2_size));
66
+
67
+ default_nan:
68
+ parts_default_nan(a, s);
69
+ return a;
31
}
70
}
32
71
33
/*
72
/*
34
--
73
--
35
2.25.1
74
2.34.1
75
76
diff view generated by jsdifflib
[PULL 20/54] target/arm: Use tcg_constant in 2misc expanders
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Assign the pointer return value to 'a' directly,
4
rather than going through an intermediary index.
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20220426163043.100432-21-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/translate-a64.c | 40 ++++++++++----------------------------
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
9
1 file changed, 10 insertions(+), 30 deletions(-)
12
1 file changed, 10 insertions(+), 22 deletions(-)
10
13
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
16
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/translate-a64.c
17
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
16
int passes = scalar ? 1 : 2;
19
FloatPartsN *c, float_status *s,
17
20
int ab_mask, int abc_mask)
18
if (scalar) {
21
{
19
- tcg_res[1] = tcg_const_i32(0);
22
- int which;
20
+ tcg_res[1] = tcg_constant_i32(0);
23
bool infzero = (ab_mask == float_cmask_infzero);
21
}
24
bool have_snan = (abc_mask & float_cmask_snan);
22
25
+ FloatPartsN *ret;
23
for (pass = 0; pass < passes; pass++) {
26
24
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
27
if (unlikely(have_snan)) {
25
}
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
26
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
27
if (is_scalar) {
28
- TCGv_i64 tcg_zero = tcg_const_i64(0);
29
- write_vec_element(s, tcg_zero, rd, 0, MO_64);
30
- tcg_temp_free_i64(tcg_zero);
31
+ write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64);
32
}
33
write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
34
}
35
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
36
case 0x1c: /* FCVTAS */
37
case 0x3a: /* FCVTPS */
38
case 0x3b: /* FCVTZS */
39
- {
40
- TCGv_i32 tcg_shift = tcg_const_i32(0);
41
- gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
42
- tcg_temp_free_i32(tcg_shift);
43
+ gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
44
+ tcg_fpstatus);
45
break;
46
- }
47
case 0x5a: /* FCVTNU */
48
case 0x5b: /* FCVTMU */
49
case 0x5c: /* FCVTAU */
50
case 0x7a: /* FCVTPU */
51
case 0x7b: /* FCVTZU */
52
- {
53
- TCGv_i32 tcg_shift = tcg_const_i32(0);
54
- gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
55
- tcg_temp_free_i32(tcg_shift);
56
+ gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
57
+ tcg_fpstatus);
58
break;
59
- }
60
default:
30
default:
61
g_assert_not_reached();
31
g_assert_not_reached();
62
}
32
}
63
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
33
- which = 2;
64
read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
34
+ ret = c;
65
66
if (round) {
67
- uint64_t round_const = 1ULL << (shift - 1);
68
- tcg_round = tcg_const_i64(round_const);
69
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
70
} else {
35
} else {
71
tcg_round = NULL;
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
72
}
37
+ FloatPartsN *val[3] = { a, b, c };
73
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
74
} else {
39
75
write_vec_element(s, tcg_final, rd, 1, MO_64);
40
assert(rule != float_3nan_prop_none);
76
}
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
77
- if (round) {
42
/* We have at least one SNaN input and should prefer it */
78
- tcg_temp_free_i64(tcg_round);
43
do {
79
- }
44
- which = rule & R_3NAN_1ST_MASK;
80
tcg_temp_free_i64(tcg_rn);
45
+ ret = val[rule & R_3NAN_1ST_MASK];
81
tcg_temp_free_i64(tcg_rd);
46
rule >>= R_3NAN_1ST_LENGTH;
82
tcg_temp_free_i64(tcg_final);
47
- } while (!is_snan(cls[which]));
83
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
84
}
56
}
85
}
57
}
86
if (!is_q) {
58
87
- tcg_res[1] = tcg_const_i64(0);
59
- switch (which) {
88
+ tcg_res[1] = tcg_constant_i64(0);
60
- case 0:
61
- break;
62
- case 1:
63
- a = b;
64
- break;
65
- case 2:
66
- a = c;
67
- break;
68
- default:
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
89
}
72
}
90
for (pass = 0; pass < 2; pass++) {
73
- if (is_snan(a->cls)) {
91
write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
74
- parts_silence_nan(a, s);
92
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
75
- }
93
case 0x1c: /* FCVTAS */
76
- return a;
94
case 0x3a: /* FCVTPS */
77
+ return ret;
95
case 0x3b: /* FCVTZS */
78
96
- {
79
default_nan:
97
- TCGv_i32 tcg_shift = tcg_const_i32(0);
80
parts_default_nan(a, s);
98
gen_helper_vfp_tosls(tcg_res, tcg_op,
99
- tcg_shift, tcg_fpstatus);
100
- tcg_temp_free_i32(tcg_shift);
101
+ tcg_constant_i32(0), tcg_fpstatus);
102
break;
103
- }
104
case 0x5a: /* FCVTNU */
105
case 0x5b: /* FCVTMU */
106
case 0x5c: /* FCVTAU */
107
case 0x7a: /* FCVTPU */
108
case 0x7b: /* FCVTZU */
109
- {
110
- TCGv_i32 tcg_shift = tcg_const_i32(0);
111
gen_helper_vfp_touls(tcg_res, tcg_op,
112
- tcg_shift, tcg_fpstatus);
113
- tcg_temp_free_i32(tcg_shift);
114
+ tcg_constant_i32(0), tcg_fpstatus);
115
break;
116
- }
117
case 0x18: /* FRINTN */
118
case 0x19: /* FRINTM */
119
case 0x38: /* FRINTP */
120
--
81
--
121
2.25.1
82
2.34.1
83
84
diff view generated by jsdifflib
[PULL 04/54] target/arm: Use tcg_constant in gen_adc_CC
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Note that tmp was doing double-duty as zero
3
While all indices into val[] should be in [0-2], the mask
4
and then later as a temporary in its own right.
4
applied is two bits. To help static analysis see there is
5
Split the use of 0 to a new variable 'zero'.
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
6
7
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20220426163043.100432-5-richard.henderson@linaro.org
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/translate-a64.c | 26 +++++++++++++-------------
13
fpu/softfloat-parts.c.inc | 2 +-
13
1 file changed, 13 insertions(+), 13 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
--- a/fpu/softfloat-parts.c.inc
18
+++ b/target/arm/translate-a64.c
19
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
20
static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
21
}
21
{
22
ret = c;
22
if (sf) {
23
- TCGv_i64 result, cf_64, vf_64, tmp;
24
- result = tcg_temp_new_i64();
25
- cf_64 = tcg_temp_new_i64();
26
- vf_64 = tcg_temp_new_i64();
27
- tmp = tcg_const_i64(0);
28
+ TCGv_i64 result = tcg_temp_new_i64();
29
+ TCGv_i64 cf_64 = tcg_temp_new_i64();
30
+ TCGv_i64 vf_64 = tcg_temp_new_i64();
31
+ TCGv_i64 tmp = tcg_temp_new_i64();
32
+ TCGv_i64 zero = tcg_constant_i64(0);
33
34
tcg_gen_extu_i32_i64(cf_64, cpu_CF);
35
- tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
36
- tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
37
+ tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero);
38
+ tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero);
39
tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
40
gen_set_NZ64(result);
41
42
@@ -XXX,XX +XXX,XX @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
43
tcg_temp_free_i64(cf_64);
44
tcg_temp_free_i64(result);
45
} else {
23
} else {
46
- TCGv_i32 t0_32, t1_32, tmp;
24
- FloatPartsN *val[3] = { a, b, c };
47
- t0_32 = tcg_temp_new_i32();
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
48
- t1_32 = tcg_temp_new_i32();
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
49
- tmp = tcg_const_i32(0);
27
50
+ TCGv_i32 t0_32 = tcg_temp_new_i32();
28
assert(rule != float_3nan_prop_none);
51
+ TCGv_i32 t1_32 = tcg_temp_new_i32();
52
+ TCGv_i32 tmp = tcg_temp_new_i32();
53
+ TCGv_i32 zero = tcg_constant_i32(0);
54
55
tcg_gen_extrl_i64_i32(t0_32, t0);
56
tcg_gen_extrl_i64_i32(t1_32, t1);
57
- tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
58
- tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
59
+ tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero);
60
+ tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero);
61
62
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
63
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
64
--
29
--
65
2.25.1
30
2.34.1
31
32
diff view generated by jsdifflib
[PULL 46/54] target/arm: Use tcg_constant for do_brk{2,3}
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In these cases, 't' did double-duty as zero source and
3
This function is part of the public interface and
4
temporary destination. Split the two uses and narrow
4
is not "specialized" to any target in any way.
5
the scope of the temp.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220426163043.100432-47-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-sve.c | 18 ++++++++++--------
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
13
1 file changed, 10 insertions(+), 8 deletions(-)
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
13
2 files changed, 52 insertions(+), 52 deletions(-)
14
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
17
--- a/fpu/softfloat.c
18
+++ b/target/arm/translate-sve.c
18
+++ b/fpu/softfloat.c
19
@@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
20
TCGv_ptr n = tcg_temp_new_ptr();
20
*zExpPtr = 1 - shiftCount;
21
TCGv_ptr m = tcg_temp_new_ptr();
22
TCGv_ptr g = tcg_temp_new_ptr();
23
- TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
24
+ TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
25
26
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
27
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
28
@@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
29
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
30
31
if (a->s) {
32
- fn_s(t, d, n, m, g, t);
33
+ TCGv_i32 t = tcg_temp_new_i32();
34
+ fn_s(t, d, n, m, g, desc);
35
do_pred_flags(t);
36
+ tcg_temp_free_i32(t);
37
} else {
38
- fn(d, n, m, g, t);
39
+ fn(d, n, m, g, desc);
40
}
41
tcg_temp_free_ptr(d);
42
tcg_temp_free_ptr(n);
43
tcg_temp_free_ptr(m);
44
tcg_temp_free_ptr(g);
45
- tcg_temp_free_i32(t);
46
return true;
47
}
21
}
48
22
49
@@ -XXX,XX +XXX,XX @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
23
+/*----------------------------------------------------------------------------
50
TCGv_ptr d = tcg_temp_new_ptr();
24
+| Takes two extended double-precision floating-point values `a' and `b', one
51
TCGv_ptr n = tcg_temp_new_ptr();
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
52
TCGv_ptr g = tcg_temp_new_ptr();
26
+| `b' is a signaling NaN, the invalid exception is raised.
53
- TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
27
+*----------------------------------------------------------------------------*/
54
+ TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
28
+
55
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
56
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
30
+{
57
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
31
+ bool aIsLargerSignificand;
58
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
32
+ FloatClass a_cls, b_cls;
59
33
+
60
if (a->s) {
34
+ /* This is not complete, but is good enough for pickNaN. */
61
- fn_s(t, d, n, g, t);
35
+ a_cls = (!floatx80_is_any_nan(a)
62
+ TCGv_i32 t = tcg_temp_new_i32();
36
+ ? float_class_normal
63
+ fn_s(t, d, n, g, desc);
37
+ : floatx80_is_signaling_nan(a, status)
64
do_pred_flags(t);
38
+ ? float_class_snan
65
+ tcg_temp_free_i32(t);
39
+ : float_class_qnan);
66
} else {
40
+ b_cls = (!floatx80_is_any_nan(b)
67
- fn(d, n, g, t);
41
+ ? float_class_normal
68
+ fn(d, n, g, desc);
42
+ : floatx80_is_signaling_nan(b, status)
69
}
43
+ ? float_class_snan
70
tcg_temp_free_ptr(d);
44
+ : float_class_qnan);
71
tcg_temp_free_ptr(n);
45
+
72
tcg_temp_free_ptr(g);
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
73
- tcg_temp_free_i32(t);
47
+ float_raise(float_flag_invalid, status);
74
return true;
48
+ }
49
+
50
+ if (status->default_nan_mode) {
51
+ return floatx80_default_nan(status);
52
+ }
53
+
54
+ if (a.low < b.low) {
55
+ aIsLargerSignificand = 0;
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
61
+
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
63
+ if (is_snan(b_cls)) {
64
+ return floatx80_silence_nan(b, status);
65
+ }
66
+ return b;
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
72
+ }
73
+}
74
+
75
/*----------------------------------------------------------------------------
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
79
index XXXXXXX..XXXXXXX 100644
80
--- a/fpu/softfloat-specialize.c.inc
81
+++ b/fpu/softfloat-specialize.c.inc
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
83
return a;
75
}
84
}
76
85
86
-/*----------------------------------------------------------------------------
87
-| Takes two extended double-precision floating-point values `a' and `b', one
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
89
-| `b' is a signaling NaN, the invalid exception is raised.
90
-*----------------------------------------------------------------------------*/
91
-
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
93
-{
94
- bool aIsLargerSignificand;
95
- FloatClass a_cls, b_cls;
96
-
97
- /* This is not complete, but is good enough for pickNaN. */
98
- a_cls = (!floatx80_is_any_nan(a)
99
- ? float_class_normal
100
- : floatx80_is_signaling_nan(a, status)
101
- ? float_class_snan
102
- : float_class_qnan);
103
- b_cls = (!floatx80_is_any_nan(b)
104
- ? float_class_normal
105
- : floatx80_is_signaling_nan(b, status)
106
- ? float_class_snan
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
135
- }
136
-}
137
-
138
/*----------------------------------------------------------------------------
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
140
| NaN; otherwise returns 0.
77
--
141
--
78
2.25.1
142
2.34.1
diff view generated by jsdifflib
[PULL 18/54] target/arm: Use tcg_constant in simd shift expanders
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Unpacking and repacking the parts may be slightly more work
4
than we did before, but we get to reuse more code. For a
5
code path handling exceptional values, this is an improvement.
6
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-19-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
target/arm/translate-a64.c | 21 +++++----------------
12
fpu/softfloat.c | 43 +++++--------------------------------------
9
1 file changed, 5 insertions(+), 16 deletions(-)
13
1 file changed, 5 insertions(+), 38 deletions(-)
10
14
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
17
--- a/fpu/softfloat.c
14
+++ b/target/arm/translate-a64.c
18
+++ b/fpu/softfloat.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
16
/* Deal with the rounding step */
20
17
if (round) {
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
18
if (extended_result) {
22
{
19
- TCGv_i64 tcg_zero = tcg_const_i64(0);
23
- bool aIsLargerSignificand;
20
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
24
- FloatClass a_cls, b_cls;
21
if (!is_u) {
25
+ FloatParts128 pa, pb, *pr;
22
/* take care of sign extending tcg_res */
26
23
tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
27
- /* This is not complete, but is good enough for pickNaN. */
24
@@ -XXX,XX +XXX,XX @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
28
- a_cls = (!floatx80_is_any_nan(a)
25
tcg_src, tcg_zero,
29
- ? float_class_normal
26
tcg_rnd, tcg_zero);
30
- : floatx80_is_signaling_nan(a, status)
27
}
31
- ? float_class_snan
28
- tcg_temp_free_i64(tcg_zero);
32
- : float_class_qnan);
29
} else {
33
- b_cls = (!floatx80_is_any_nan(b)
30
tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
34
- ? float_class_normal
31
}
35
- : floatx80_is_signaling_nan(b, status)
32
@@ -XXX,XX +XXX,XX @@ static void handle_scalar_simd_shri(DisasContext *s,
36
- ? float_class_snan
37
- : float_class_qnan);
38
-
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
40
- float_raise(float_flag_invalid, status);
41
- }
42
-
43
- if (status->default_nan_mode) {
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
46
return floatx80_default_nan(status);
33
}
47
}
34
48
35
if (round) {
49
- if (a.low < b.low) {
36
- uint64_t round_const = 1ULL << (shift - 1);
50
- aIsLargerSignificand = 0;
37
- tcg_round = tcg_const_i64(round_const);
51
- } else if (b.low < a.low) {
38
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
52
- aIsLargerSignificand = 1;
39
} else {
53
- } else {
40
tcg_round = NULL;
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
41
}
42
@@ -XXX,XX +XXX,XX @@ static void handle_scalar_simd_shri(DisasContext *s,
43
44
tcg_temp_free_i64(tcg_rn);
45
tcg_temp_free_i64(tcg_rd);
46
- if (round) {
47
- tcg_temp_free_i64(tcg_round);
48
- }
55
- }
56
-
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
58
- if (is_snan(b_cls)) {
59
- return floatx80_silence_nan(b, status);
60
- }
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
67
- }
68
+ pr = parts_pick_nan(&pa, &pb, status);
69
+ return floatx80_round_pack_canonical(pr, status);
49
}
70
}
50
71
51
/* SHL/SLI - Scalar shift left */
72
/*----------------------------------------------------------------------------
52
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
53
tcg_final = tcg_const_i64(0);
54
55
if (round) {
56
- uint64_t round_const = 1ULL << (shift - 1);
57
- tcg_round = tcg_const_i64(round_const);
58
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
59
} else {
60
tcg_round = NULL;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
63
write_vec_element(s, tcg_final, rd, 1, MO_64);
64
}
65
66
- if (round) {
67
- tcg_temp_free_i64(tcg_round);
68
- }
69
tcg_temp_free_i64(tcg_rn);
70
tcg_temp_free_i64(tcg_rd);
71
tcg_temp_free_i32(tcg_rd_narrowed);
72
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
73
}
74
75
if (size == 3) {
76
- TCGv_i64 tcg_shift = tcg_const_i64(shift);
77
+ TCGv_i64 tcg_shift = tcg_constant_i64(shift);
78
static NeonGenTwo64OpEnvFn * const fns[2][2] = {
79
{ gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
80
{ NULL, gen_helper_neon_qshl_u64 },
81
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
82
83
tcg_temp_free_i64(tcg_op);
84
}
85
- tcg_temp_free_i64(tcg_shift);
86
clear_vec_high(s, is_q, rd);
87
} else {
88
- TCGv_i32 tcg_shift = tcg_const_i32(shift);
89
+ TCGv_i32 tcg_shift = tcg_constant_i32(shift);
90
static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
91
{
92
{ gen_helper_neon_qshl_s8,
93
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
94
95
tcg_temp_free_i32(tcg_op);
96
}
97
- tcg_temp_free_i32(tcg_shift);
98
99
if (!scalar) {
100
clear_vec_high(s, is_q, rd);
101
--
73
--
102
2.25.1
74
2.34.1
diff view generated by jsdifflib
[PULL 21/54] target/arm: Use tcg_constant in balance of translate-a64.c
[PULL 67/72] softfloat: Inline pickNaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Finish conversion of the file to tcg_constant_*.
3
Inline pickNaN into its only caller. This makes one assert
4
redundant with the immediately preceding IF.
4
5
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20220426163043.100432-22-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/translate-a64.c | 20 ++++++++------------
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
11
1 file changed, 8 insertions(+), 12 deletions(-)
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
12
13
2 files changed, 73 insertions(+), 105 deletions(-)
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
17
--- a/fpu/softfloat-parts.c.inc
16
+++ b/target/arm/translate-a64.c
18
+++ b/fpu/softfloat-parts.c.inc
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
float_status *s)
22
{
23
+ int cmp, which;
24
+
25
if (is_snan(a->cls) || is_snan(b->cls)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
if (s->default_nan_mode) {
30
parts_default_nan(a, s);
31
- } else {
32
- int cmp = frac_cmp(a, b);
33
- if (cmp == 0) {
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
18
}
58
}
19
59
+ break;
20
if (is_scalar) {
60
+ case float_2nan_prop_s_ba:
21
- tcg_res[1] = tcg_const_i64(0);
61
+ if (is_snan(b->cls)) {
22
+ tcg_res[1] = tcg_constant_i64(0);
62
+ which = 1;
23
}
63
+ } else if (is_snan(a->cls)) {
24
64
+ which = 0;
25
for (pass = 0; pass < 2; pass++) {
65
+ } else if (is_qnan(b->cls)) {
26
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
66
+ which = 1;
27
tcg_op2 = tcg_temp_new_i32();
67
+ } else {
28
tcg_op3 = tcg_temp_new_i32();
68
+ which = 0;
29
tcg_res = tcg_temp_new_i32();
69
+ }
30
- tcg_zero = tcg_const_i32(0);
70
+ break;
31
+ tcg_zero = tcg_constant_i32(0);
71
+ case float_2nan_prop_ab:
32
72
+ which = is_nan(a->cls) ? 0 : 1;
33
read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);
73
+ break;
34
read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);
74
+ case float_2nan_prop_ba:
35
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
75
+ which = is_nan(b->cls) ? 1 : 0;
36
tcg_temp_free_i32(tcg_op2);
76
+ break;
37
tcg_temp_free_i32(tcg_op3);
77
+ case float_2nan_prop_x87:
38
tcg_temp_free_i32(tcg_res);
78
+ /*
39
- tcg_temp_free_i32(tcg_zero);
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
118
index XXXXXXX..XXXXXXX 100644
119
--- a/fpu/softfloat-specialize.c.inc
120
+++ b/fpu/softfloat-specialize.c.inc
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
40
}
122
}
41
}
123
}
42
124
43
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
125
-/*----------------------------------------------------------------------------
44
gen_helper_yield(cpu_env);
126
-| Select which NaN to propagate for a two-input operation.
45
break;
127
-| IEEE754 doesn't specify all the details of this, so the
46
case DISAS_WFI:
128
-| algorithm is target-specific.
47
- {
129
-| The routine is passed various bits of information about the
48
- /* This is a special case because we don't want to just halt the CPU
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
49
- * if trying to debug across a WFI.
131
-| Note that signalling NaNs are always squashed to quiet NaNs
50
+ /*
132
-| by the caller, by calling floatXX_silence_nan() before
51
+ * This is a special case because we don't want to just halt
133
-| returning them.
52
+ * the CPU if trying to debug across a WFI.
134
-|
53
*/
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
54
- TCGv_i32 tmp = tcg_const_i32(4);
136
-| of some kind, and is true if a has the larger significand,
137
-| or if both a and b have the same significand but a is
138
-| positive but b is negative. It is only needed for the x87
139
-| tie-break rule.
140
-*----------------------------------------------------------------------------*/
55
-
141
-
56
gen_a64_set_pc_im(dc->base.pc_next);
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
57
- gen_helper_wfi(cpu_env, tmp);
143
- bool aIsLargerSignificand, float_status *status)
58
- tcg_temp_free_i32(tmp);
144
-{
59
- /* The helper doesn't necessarily throw an exception, but we
145
- /*
60
+ gen_helper_wfi(cpu_env, tcg_constant_i32(4));
146
- * We guarantee not to require the target to tell us how to
61
+ /*
147
- * pick a NaN if we're always returning the default NaN.
62
+ * The helper doesn't necessarily throw an exception, but we
148
- * But if we're not in default-NaN mode then the target must
63
* must go back to the main loop to check for interrupts anyway.
149
- * specify via set_float_2nan_prop_rule().
64
*/
150
- */
65
tcg_gen_exit_tb(NULL, 0);
151
- assert(!status->default_nan_mode);
66
break;
152
-
67
}
153
- switch (status->float_2nan_prop_rule) {
68
- }
154
- case float_2nan_prop_s_ab:
69
}
155
- if (is_snan(a_cls)) {
70
}
156
- return 0;
71
157
- } else if (is_snan(b_cls)) {
158
- return 1;
159
- } else if (is_qnan(a_cls)) {
160
- return 0;
161
- } else {
162
- return 1;
163
- }
164
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
218
- }
219
-}
220
-
221
/*----------------------------------------------------------------------------
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
223
| NaN; otherwise returns 0.
72
--
224
--
73
2.25.1
225
2.34.1
226
227
diff view generated by jsdifflib
[PULL 05/54] target/arm: Use tcg_constant in handle_msr_i
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Remember if there was an SNaN, and use that to simplify
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
Then, fall through to the corresponding
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
2
8
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-6-richard.henderson@linaro.org
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
target/arm/translate-a64.c | 13 +++----------
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
9
1 file changed, 3 insertions(+), 10 deletions(-)
15
1 file changed, 12 insertions(+), 20 deletions(-)
10
16
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
19
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/translate-a64.c
20
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void gen_axflag(void)
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
16
static void handle_msr_i(DisasContext *s, uint32_t insn,
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
17
unsigned int op1, unsigned int op2, unsigned int crm)
23
float_status *s)
18
{
24
{
19
- TCGv_i32 t1;
25
+ bool have_snan = false;
20
int op = op1 << 3 | op2;
26
int cmp, which;
21
27
22
/* End the TB by default, chaining is ok. */
28
if (is_snan(a->cls) || is_snan(b->cls)) {
23
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
24
if (s->current_el == 0) {
30
+ have_snan = true;
25
goto do_unallocated;
31
}
32
33
if (s->default_nan_mode) {
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
35
36
switch (s->float_2nan_prop_rule) {
37
case float_2nan_prop_s_ab:
38
- if (is_snan(a->cls)) {
39
- which = 0;
40
- } else if (is_snan(b->cls)) {
41
- which = 1;
42
- } else if (is_qnan(a->cls)) {
43
- which = 0;
44
- } else {
45
- which = 1;
46
+ if (have_snan) {
47
+ which = is_snan(a->cls) ? 0 : 1;
48
+ break;
26
}
49
}
27
- t1 = tcg_const_i32(crm & PSTATE_SP);
50
- break;
28
- gen_helper_msr_i_spsel(cpu_env, t1);
51
- case float_2nan_prop_s_ba:
29
- tcg_temp_free_i32(t1);
52
- if (is_snan(b->cls)) {
30
+ gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP));
53
- which = 1;
54
- } else if (is_snan(a->cls)) {
55
- which = 0;
56
- } else if (is_qnan(b->cls)) {
57
- which = 1;
58
- } else {
59
- which = 0;
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
31
break;
65
break;
32
66
+ case float_2nan_prop_s_ba:
33
case 0x19: /* SSBS */
67
+ if (have_snan) {
34
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
68
+ which = is_snan(b->cls) ? 1 : 0;
35
break;
69
+ break;
36
70
+ }
37
case 0x1e: /* DAIFSet */
71
+ /* fall through */
38
- t1 = tcg_const_i32(crm);
72
case float_2nan_prop_ba:
39
- gen_helper_msr_i_daifset(cpu_env, t1);
73
which = is_nan(b->cls) ? 1 : 0;
40
- tcg_temp_free_i32(t1);
41
+ gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm));
42
break;
43
44
case 0x1f: /* DAIFClear */
45
- t1 = tcg_const_i32(crm);
46
- gen_helper_msr_i_daifclear(cpu_env, t1);
47
- tcg_temp_free_i32(t1);
48
+ gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm));
49
/* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
50
s->base.is_jmp = DISAS_UPDATE_EXIT;
51
break;
74
break;
52
--
75
--
53
2.25.1
76
2.34.1
diff view generated by jsdifflib
[PULL 27/54] target/arm: Use tcg_constant for gen_srs
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Move the fractional comparison to the end of the
4
float_2nan_prop_x87 case. This is not required for
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
2
8
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-28-richard.henderson@linaro.org
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
target/arm/translate.c | 8 ++------
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
9
1 file changed, 2 insertions(+), 6 deletions(-)
15
1 file changed, 9 insertions(+), 10 deletions(-)
10
16
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
19
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/translate.c
20
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
22
return a;
16
}
23
}
17
24
18
addr = tcg_temp_new_i32();
25
- cmp = frac_cmp(a, b);
19
- tmp = tcg_const_i32(mode);
26
- if (cmp == 0) {
20
/* get_r13_banked() will raise an exception if called from System mode */
27
- cmp = a->sign < b->sign;
21
gen_set_condexec(s);
28
- }
22
gen_set_pc_im(s, s->pc_curr);
29
-
23
- gen_helper_get_r13_banked(addr, cpu_env, tmp);
30
switch (s->float_2nan_prop_rule) {
24
- tcg_temp_free_i32(tmp);
31
case float_2nan_prop_s_ab:
25
+ gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
32
if (have_snan) {
26
switch (amode) {
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
27
case 0: /* DA */
34
* return the NaN with the positive sign bit (if any).
28
offset = -4;
35
*/
29
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
36
if (is_snan(a->cls)) {
30
abort();
37
- if (is_snan(b->cls)) {
38
- which = cmp > 0 ? 0 : 1;
39
- } else {
40
+ if (!is_snan(b->cls)) {
41
which = is_qnan(b->cls) ? 1 : 0;
42
+ break;
43
}
44
} else if (is_qnan(a->cls)) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
46
which = 0;
47
- } else {
48
- which = cmp > 0 ? 0 : 1;
49
+ break;
50
}
51
} else {
52
which = 1;
53
+ break;
31
}
54
}
32
tcg_gen_addi_i32(addr, addr, offset);
55
+ cmp = frac_cmp(a, b);
33
- tmp = tcg_const_i32(mode);
56
+ if (cmp == 0) {
34
- gen_helper_set_r13_banked(cpu_env, tmp, addr);
57
+ cmp = a->sign < b->sign;
35
- tcg_temp_free_i32(tmp);
58
+ }
36
+ gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
59
+ which = cmp > 0 ? 0 : 1;
37
}
60
break;
38
tcg_temp_free_i32(addr);
61
default:
39
s->base.is_jmp = DISAS_UPDATE_EXIT;
62
g_assert_not_reached();
40
--
63
--
41
2.25.1
64
2.34.1
diff view generated by jsdifflib
[PULL 49/54] target/arm: Use field names for accessing DBGWCRn
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
While defining these names, use the correct field width of 5 not 4 for
3
Replace the "index" selecting between A and B with a result variable
4
DBGWCR.MASK. This typo prevented setting a watchpoint larger than 32k.
4
of the proper type. This improves clarity within the function.
5
5
6
Reported-by: Chris Howard <cvz185@web.de>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20220427051926.295223-1-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/internals.h | 12 ++++++++++++
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
13
target/arm/debug_helper.c | 10 +++++-----
12
1 file changed, 13 insertions(+), 15 deletions(-)
14
target/arm/helper.c | 8 ++++----
15
target/arm/kvm64.c | 14 +++++++-------
16
4 files changed, 28 insertions(+), 16 deletions(-)
17
13
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
16
--- a/fpu/softfloat-parts.c.inc
21
+++ b/target/arm/internals.h
17
+++ b/fpu/softfloat-parts.c.inc
22
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
23
*/
19
float_status *s)
24
#define FNC_RETURN_MIN_MAGIC 0xfefffffe
20
{
25
21
bool have_snan = false;
26
+/* Bit definitions for DBGWCRn and DBGWCRn_EL1 */
22
- int cmp, which;
27
+FIELD(DBGWCR, E, 0, 1)
23
+ FloatPartsN *ret;
28
+FIELD(DBGWCR, PAC, 1, 2)
24
+ int cmp;
29
+FIELD(DBGWCR, LSC, 3, 2)
25
30
+FIELD(DBGWCR, BAS, 5, 8)
26
if (is_snan(a->cls) || is_snan(b->cls)) {
31
+FIELD(DBGWCR, HMC, 13, 1)
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
32
+FIELD(DBGWCR, SSC, 14, 2)
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
33
+FIELD(DBGWCR, LBN, 16, 4)
29
switch (s->float_2nan_prop_rule) {
34
+FIELD(DBGWCR, WT, 20, 1)
30
case float_2nan_prop_s_ab:
35
+FIELD(DBGWCR, MASK, 24, 5)
31
if (have_snan) {
36
+FIELD(DBGWCR, SSCE, 29, 1)
32
- which = is_snan(a->cls) ? 0 : 1;
37
+
33
+ ret = is_snan(a->cls) ? a : b;
38
/* We use a few fake FSR values for internal purposes in M profile.
34
break;
39
* M profile cores don't have A/R format FSRs, but currently our
35
}
40
* get_phys_addr() code assumes A/R profile and reports failures via
36
/* fall through */
41
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
37
case float_2nan_prop_ab:
42
index XXXXXXX..XXXXXXX 100644
38
- which = is_nan(a->cls) ? 0 : 1;
43
--- a/target/arm/debug_helper.c
39
+ ret = is_nan(a->cls) ? a : b;
44
+++ b/target/arm/debug_helper.c
40
break;
45
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
41
case float_2nan_prop_s_ba:
46
* Non-Secure to simplify the code slightly compared to the full
42
if (have_snan) {
47
* table in the ARM ARM.
43
- which = is_snan(b->cls) ? 1 : 0;
48
*/
44
+ ret = is_snan(b->cls) ? b : a;
49
- pac = extract64(cr, 1, 2);
45
break;
50
- hmc = extract64(cr, 13, 1);
46
}
51
- ssc = extract64(cr, 14, 2);
47
/* fall through */
52
+ pac = FIELD_EX64(cr, DBGWCR, PAC);
48
case float_2nan_prop_ba:
53
+ hmc = FIELD_EX64(cr, DBGWCR, HMC);
49
- which = is_nan(b->cls) ? 1 : 0;
54
+ ssc = FIELD_EX64(cr, DBGWCR, SSC);
50
+ ret = is_nan(b->cls) ? b : a;
55
51
break;
56
switch (ssc) {
52
case float_2nan_prop_x87:
57
case 0:
53
/*
58
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
59
g_assert_not_reached();
81
g_assert_not_reached();
60
}
82
}
61
83
62
- wt = extract64(cr, 20, 1);
84
- if (which) {
63
- lbn = extract64(cr, 16, 4);
85
- a = b;
64
+ wt = FIELD_EX64(cr, DBGWCR, WT);
86
+ if (is_snan(ret->cls)) {
65
+ lbn = FIELD_EX64(cr, DBGWCR, LBN);
87
+ parts_silence_nan(ret, s);
66
67
if (wt && !linked_bp_matches(cpu, lbn)) {
68
return false;
69
diff --git a/target/arm/helper.c b/target/arm/helper.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/helper.c
72
+++ b/target/arm/helper.c
73
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
74
env->cpu_watchpoint[n] = NULL;
75
}
88
}
76
89
- if (is_snan(a->cls)) {
77
- if (!extract64(wcr, 0, 1)) {
90
- parts_silence_nan(a, s);
78
+ if (!FIELD_EX64(wcr, DBGWCR, E)) {
91
- }
79
/* E bit clear : watchpoint disabled */
92
- return a;
80
return;
93
+ return ret;
81
}
94
}
82
95
83
- switch (extract64(wcr, 3, 2)) {
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
84
+ switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
85
case 0:
86
/* LSC 00 is reserved and must behave as if the wp is disabled */
87
return;
88
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
89
* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
90
* thus generating a watchpoint for every byte in the masked region.
91
*/
92
- mask = extract64(wcr, 24, 4);
93
+ mask = FIELD_EX64(wcr, DBGWCR, MASK);
94
if (mask == 1 || mask == 2) {
95
/* Reserved values of MASK; we must act as if the mask value was
96
* some non-reserved value, or as if the watchpoint were disabled.
97
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
98
wvr &= ~(len - 1);
99
} else {
100
/* Watchpoint covers bytes defined by the byte address select bits */
101
- int bas = extract64(wcr, 5, 8);
102
+ int bas = FIELD_EX64(wcr, DBGWCR, BAS);
103
int basstart;
104
105
if (extract64(wvr, 2, 1)) {
106
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/kvm64.c
109
+++ b/target/arm/kvm64.c
110
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
111
target_ulong len, int type)
112
{
113
HWWatchpoint wp = {
114
- .wcr = 1, /* E=1, enable */
115
+ .wcr = R_DBGWCR_E_MASK, /* E=1, enable */
116
.wvr = addr & (~0x7ULL),
117
.details = { .vaddr = addr, .len = len }
118
};
119
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
120
* HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
121
* valid whether EL3 is implemented or not
122
*/
123
- wp.wcr = deposit32(wp.wcr, 1, 2, 3);
124
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3);
125
126
switch (type) {
127
case GDB_WATCHPOINT_READ:
128
- wp.wcr = deposit32(wp.wcr, 3, 2, 1);
129
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1);
130
wp.details.flags = BP_MEM_READ;
131
break;
132
case GDB_WATCHPOINT_WRITE:
133
- wp.wcr = deposit32(wp.wcr, 3, 2, 2);
134
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2);
135
wp.details.flags = BP_MEM_WRITE;
136
break;
137
case GDB_WATCHPOINT_ACCESS:
138
- wp.wcr = deposit32(wp.wcr, 3, 2, 3);
139
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3);
140
wp.details.flags = BP_MEM_ACCESS;
141
break;
142
default:
143
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
144
int bits = ctz64(len);
145
146
wp.wvr &= ~((1 << bits) - 1);
147
- wp.wcr = deposit32(wp.wcr, 24, 4, bits);
148
- wp.wcr = deposit32(wp.wcr, 5, 8, 0xff);
149
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits);
150
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff);
151
} else {
152
return -ENOBUFS;
153
}
154
--
97
--
155
2.25.1
98
2.34.1
156
99
157
100
diff view generated by jsdifflib
[PULL 07/54] target/arm: Use tcg_constant in disas_exc
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
update my email address, and update the mailmap to match.
5
Message-id: 20220426163043.100432-8-richard.henderson@linaro.org
5
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
target/arm/translate-a64.c | 5 +----
14
MAINTAINERS | 2 +-
9
1 file changed, 1 insertion(+), 4 deletions(-)
15
.mailmap | 5 +++--
16
2 files changed, 4 insertions(+), 3 deletions(-)
10
17
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
diff --git a/MAINTAINERS b/MAINTAINERS
12
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
20
--- a/MAINTAINERS
14
+++ b/target/arm/translate-a64.c
21
+++ b/MAINTAINERS
15
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
16
int opc = extract32(insn, 21, 3);
23
SBSA-REF
17
int op2_ll = extract32(insn, 0, 5);
24
M: Radoslaw Biernacki <rad@semihalf.com>
18
int imm16 = extract32(insn, 5, 16);
25
M: Peter Maydell <peter.maydell@linaro.org>
19
- TCGv_i32 tmp;
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
20
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
21
switch (opc) {
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
22
case 0:
29
L: qemu-arm@nongnu.org
23
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
30
S: Maintained
24
break;
31
diff --git a/.mailmap b/.mailmap
25
}
32
index XXXXXXX..XXXXXXX 100644
26
gen_a64_set_pc_im(s->pc_curr);
33
--- a/.mailmap
27
- tmp = tcg_const_i32(syn_aa64_smc(imm16));
34
+++ b/.mailmap
28
- gen_helper_pre_smc(cpu_env, tmp);
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
29
- tcg_temp_free_i32(tmp);
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
30
+ gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
31
gen_ss_advance(s);
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
32
gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
33
syn_aa64_smc(imm16), 3);
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
34
--
47
--
35
2.25.1
48
2.34.1
49
50
diff view generated by jsdifflib
[PULL 06/54] target/arm: Use tcg_constant in handle_sys
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
Message-id: 20220426163043.100432-7-richard.henderson@linaro.org
5
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/translate-a64.c | 31 +++++++++----------------------
11
MAINTAINERS | 2 ++
9
1 file changed, 9 insertions(+), 22 deletions(-)
12
1 file changed, 2 insertions(+)
10
13
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/MAINTAINERS b/MAINTAINERS
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
16
--- a/MAINTAINERS
14
+++ b/target/arm/translate-a64.c
17
+++ b/MAINTAINERS
15
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
16
/* Emit code to perform further access permissions checks at
19
17
* runtime; this may result in an exception.
20
Xilinx CAN
18
*/
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
19
- TCGv_ptr tmpptr;
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
20
- TCGv_i32 tcg_syn, tcg_isread;
23
S: Maintained
21
uint32_t syndrome;
24
F: hw/net/can/xlnx-*
22
25
F: include/hw/net/xlnx-*
23
- gen_a64_set_pc_im(s->pc_curr);
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
24
- tmpptr = tcg_const_ptr(ri);
27
CAN bus subsystem and hardware
25
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
26
- tcg_syn = tcg_const_i32(syndrome);
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
27
- tcg_isread = tcg_const_i32(isread);
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
28
- gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
31
S: Maintained
29
- tcg_temp_free_ptr(tmpptr);
32
W: https://canbus.pages.fel.cvut.cz/
30
- tcg_temp_free_i32(tcg_syn);
33
F: net/can/*
31
- tcg_temp_free_i32(tcg_isread);
32
+ gen_a64_set_pc_im(s->pc_curr);
33
+ gen_helper_access_check_cp_reg(cpu_env,
34
+ tcg_constant_ptr(ri),
35
+ tcg_constant_i32(syndrome),
36
+ tcg_constant_i32(isread));
37
} else if (ri->type & ARM_CP_RAISES_EXC) {
38
/*
39
* The readfn or writefn might raise an exception;
40
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
41
case ARM_CP_DC_ZVA:
42
/* Writes clear the aligned block of memory which rt points into. */
43
if (s->mte_active[0]) {
44
- TCGv_i32 t_desc;
45
int desc = 0;
46
47
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
48
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
49
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
50
- t_desc = tcg_const_i32(desc);
51
52
tcg_rt = new_tmp_a64(s);
53
- gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt));
54
- tcg_temp_free_i32(t_desc);
55
+ gen_helper_mte_check_zva(tcg_rt, cpu_env,
56
+ tcg_constant_i32(desc), cpu_reg(s, rt));
57
} else {
58
tcg_rt = clean_data_tbi(s, cpu_reg(s, rt));
59
}
60
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
61
if (ri->type & ARM_CP_CONST) {
62
tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
63
} else if (ri->readfn) {
64
- TCGv_ptr tmpptr;
65
- tmpptr = tcg_const_ptr(ri);
66
- gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
67
- tcg_temp_free_ptr(tmpptr);
68
+ gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri));
69
} else {
70
tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
71
}
72
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
73
/* If not forbidden by access permissions, treat as WI */
74
return;
75
} else if (ri->writefn) {
76
- TCGv_ptr tmpptr;
77
- tmpptr = tcg_const_ptr(ri);
78
- gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
79
- tcg_temp_free_ptr(tmpptr);
80
+ gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt);
81
} else {
82
tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
83
}
84
--
34
--
85
2.25.1
35
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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