[PULL 0/4] tcg patch queue
[PATCH v3 00/28] tcg patch queue
1
The following changes since commit 2d20a57453f6a206938cbbf77bed0b378c806c1f:
1
v3: One more try to fix macos issues.
2
2
3
Merge tag 'pull-fixes-for-7.1-200422-1' of https://github.com/stsquad/qemu into staging (2022-04-20 11:13:08 -0700)
3
4
r~
5
6
7
8
The following changes since commit e0209297cddd5e10a07e15fac5cca7aa1a8e0e59:
9
10
Merge tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu into staging (2025-02-18 10:58:48 +0800)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220420
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-3
8
15
9
for you to fetch changes up to a61532faa5a4d5e021e35b6a4a1e180c72d4a22f:
16
for you to fetch changes up to e726f65867087d86436de05e9f372a86ec1381a6:
10
17
11
tcg: Add tcg_constant_ptr (2022-04-20 12:12:47 -0700)
18
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-18 08:29:03 -0800)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
Cleanup sysemu/tcg.h usage.
21
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
15
Fix indirect lowering vs cond branches
22
tcg: Cleanups after disallowing 64-on-32
16
Remove ATOMIC_MMU_IDX
23
tcg: Introduce constraint for zero register
17
Add tcg_constant_ptr
24
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
25
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
26
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
27
linux-user: Fix alignment when unmapping excess reservation
28
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
29
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
30
target/sparc: fake UltraSPARC T1 PCR and PIC registers
18
31
19
----------------------------------------------------------------
32
----------------------------------------------------------------
20
Richard Henderson (3):
33
Andreas Schwab (1):
21
tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH
34
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
22
accel/tcg: Remove ATOMIC_MMU_IDX
23
tcg: Add tcg_constant_ptr
24
35
25
Thomas Huth (1):
36
Artyom Tarasenko (1):
26
Don't include sysemu/tcg.h if it is not necessary
37
target/sparc: fake UltraSPARC T1 PCR and PIC registers
27
38
28
include/tcg/tcg.h | 4 ++++
39
Fabiano Rosas (1):
29
accel/tcg/cputlb.c | 1 -
40
elfload: Fix alignment when unmapping excess reservation
30
accel/tcg/hmp.c | 1 -
41
31
accel/tcg/tcg-accel-ops-icount.c | 1 -
42
Mikael Szreder (2):
32
accel/tcg/user-exec.c | 1 -
43
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
33
bsd-user/main.c | 1 -
44
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
34
hw/virtio/vhost.c | 1 -
45
35
linux-user/main.c | 1 -
46
Richard Henderson (23):
36
monitor/misc.c | 1 -
47
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
37
target/arm/helper.c | 1 -
48
tcg: Remove TCG_OVERSIZED_GUEST
38
target/s390x/cpu_models_sysemu.c | 1 -
49
tcg: Drop support for two address registers in gen_ldst
39
target/s390x/helper.c | 1 -
50
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
40
tcg/tcg.c | 34 +++++++++++++++++++++++++++-------
51
tcg/arm: Drop addrhi from prepare_host_addr
41
13 files changed, 31 insertions(+), 18 deletions(-)
52
tcg/i386: Drop addrhi from prepare_host_addr
53
tcg/mips: Drop addrhi from prepare_host_addr
54
tcg/ppc: Drop addrhi from prepare_host_addr
55
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
56
plugins: Fix qemu_plugin_read_memory_vaddr parameters
57
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
58
target/loongarch: Use VADDR_PRIx for logging pc_next
59
target/mips: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
70
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/mips/tcg/octeon_translate.c | 4 +-
112
target/riscv/cpu_helper.c | 13 +-
113
target/sparc/gdbstub.c | 18 +-
114
target/sparc/translate.c | 19 +++
115
tcg/optimize.c | 21 +--
116
tcg/tcg-op-ldst.c | 103 +++--------
117
tcg/tcg.c | 97 +++++------
118
tcg/tci.c | 119 +++----------
119
docs/devel/multi-thread-tcg.rst | 1 -
120
docs/devel/tcg-ops.rst | 4 +-
121
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
122
target/sparc/insns.decode | 19 ++-
123
tcg/aarch64/tcg-target.c.inc | 86 ++++------
124
tcg/arm/tcg-target.c.inc | 114 ++++---------
125
tcg/i386/tcg-target.c.inc | 190 +++++----------------
126
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
127
tcg/mips/tcg-target.c.inc | 169 ++++++------------
128
tcg/ppc/tcg-target.c.inc | 164 +++++-------------
129
tcg/riscv/tcg-target.c.inc | 56 +++---
130
tcg/s390x/tcg-target.c.inc | 40 ++---
131
tcg/sparc64/tcg-target.c.inc | 45 ++---
132
tcg/tci/tcg-target.c.inc | 60 ++-----
133
62 files changed, 550 insertions(+), 1162 deletions(-)
134
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 1/4] Don't include sysemu/tcg.h if it is not necessary
Deleted patch
1
From: Thomas Huth <thuth@redhat.com>
2
1
3
This header only defines the tcg_allowed variable and the tcg_enabled()
4
function - which are not required in many files that include this
5
header. Drop the #include statement there.
6
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Markus Armbruster <armbru@redhat.com>
9
Message-Id: <20220315144107.1012530-1-thuth@redhat.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
accel/tcg/hmp.c | 1 -
13
accel/tcg/tcg-accel-ops-icount.c | 1 -
14
bsd-user/main.c | 1 -
15
hw/virtio/vhost.c | 1 -
16
linux-user/main.c | 1 -
17
monitor/misc.c | 1 -
18
target/arm/helper.c | 1 -
19
target/s390x/cpu_models_sysemu.c | 1 -
20
target/s390x/helper.c | 1 -
21
9 files changed, 9 deletions(-)
22
23
diff --git a/accel/tcg/hmp.c b/accel/tcg/hmp.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/accel/tcg/hmp.c
26
+++ b/accel/tcg/hmp.c
27
@@ -XXX,XX +XXX,XX @@
28
#include "qapi/qapi-commands-machine.h"
29
#include "exec/exec-all.h"
30
#include "monitor/monitor.h"
31
-#include "sysemu/tcg.h"
32
33
static void hmp_tcg_register(void)
34
{
35
diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/accel/tcg/tcg-accel-ops-icount.c
38
+++ b/accel/tcg/tcg-accel-ops-icount.c
39
@@ -XXX,XX +XXX,XX @@
40
*/
41
42
#include "qemu/osdep.h"
43
-#include "sysemu/tcg.h"
44
#include "sysemu/replay.h"
45
#include "sysemu/cpu-timers.h"
46
#include "qemu/main-loop.h"
47
diff --git a/bsd-user/main.c b/bsd-user/main.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/bsd-user/main.c
50
+++ b/bsd-user/main.c
51
@@ -XXX,XX +XXX,XX @@
52
#include "qemu-common.h"
53
#include "qemu/units.h"
54
#include "qemu/accel.h"
55
-#include "sysemu/tcg.h"
56
#include "qemu-version.h"
57
#include <machine/trap.h>
58
59
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/virtio/vhost.c
62
+++ b/hw/virtio/vhost.c
63
@@ -XXX,XX +XXX,XX @@
64
#include "migration/blocker.h"
65
#include "migration/qemu-file-types.h"
66
#include "sysemu/dma.h"
67
-#include "sysemu/tcg.h"
68
#include "trace.h"
69
70
/* enabled until disconnected backend stabilizes */
71
diff --git a/linux-user/main.c b/linux-user/main.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/linux-user/main.c
74
+++ b/linux-user/main.c
75
@@ -XXX,XX +XXX,XX @@
76
#include "qemu-common.h"
77
#include "qemu/units.h"
78
#include "qemu/accel.h"
79
-#include "sysemu/tcg.h"
80
#include "qemu-version.h"
81
#include <sys/syscall.h>
82
#include <sys/resource.h>
83
diff --git a/monitor/misc.c b/monitor/misc.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/monitor/misc.c
86
+++ b/monitor/misc.c
87
@@ -XXX,XX +XXX,XX @@
88
#include "qapi/util.h"
89
#include "sysemu/blockdev.h"
90
#include "sysemu/sysemu.h"
91
-#include "sysemu/tcg.h"
92
#include "sysemu/tpm.h"
93
#include "qapi/qmp/qdict.h"
94
#include "qapi/qmp/qerror.h"
95
diff --git a/target/arm/helper.c b/target/arm/helper.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/arm/helper.c
98
+++ b/target/arm/helper.c
99
@@ -XXX,XX +XXX,XX @@
100
#include "sysemu/cpus.h"
101
#include "sysemu/cpu-timers.h"
102
#include "sysemu/kvm.h"
103
-#include "sysemu/tcg.h"
104
#include "qemu/range.h"
105
#include "qapi/qapi-commands-machine-target.h"
106
#include "qapi/error.h"
107
diff --git a/target/s390x/cpu_models_sysemu.c b/target/s390x/cpu_models_sysemu.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/s390x/cpu_models_sysemu.c
110
+++ b/target/s390x/cpu_models_sysemu.c
111
@@ -XXX,XX +XXX,XX @@
112
#include "s390x-internal.h"
113
#include "kvm/kvm_s390x.h"
114
#include "sysemu/kvm.h"
115
-#include "sysemu/tcg.h"
116
#include "qapi/error.h"
117
#include "qapi/visitor.h"
118
#include "qapi/qmp/qerror.h"
119
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/s390x/helper.c
122
+++ b/target/s390x/helper.c
123
@@ -XXX,XX +XXX,XX @@
124
#include "hw/s390x/pv.h"
125
#include "sysemu/hw_accel.h"
126
#include "sysemu/runstate.h"
127
-#include "sysemu/tcg.h"
128
129
void s390x_tod_timer(void *opaque)
130
{
131
--
132
2.34.1
diff view generated by jsdifflib
[PULL 2/4] tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH
Deleted patch
1
With TCG_OPF_COND_BRANCH, we extended the lifetimes of
2
globals across extended basic blocks. This means that
3
the liveness computed in pass 1 does not kill globals
4
in the same way as normal temps.
5
1
6
Introduce TYPE_EBB to match this lifetime, so that we
7
get correct register allocation for the temps that we
8
introduce during the indirect lowering pass.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Fixes: b4cb76e6208 ("tcg: Do not kill globals at conditional branches")
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
include/tcg/tcg.h | 2 ++
15
tcg/tcg.c | 34 +++++++++++++++++++++++++++-------
16
2 files changed, 29 insertions(+), 7 deletions(-)
17
18
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/tcg/tcg.h
21
+++ b/include/tcg/tcg.h
22
@@ -XXX,XX +XXX,XX @@ typedef enum TCGTempVal {
23
typedef enum TCGTempKind {
24
/* Temp is dead at the end of all basic blocks. */
25
TEMP_NORMAL,
26
+ /* Temp is live across conditional branch, but dead otherwise. */
27
+ TEMP_EBB,
28
/* Temp is saved across basic blocks but dead at the end of TBs. */
29
TEMP_LOCAL,
30
/* Temp is saved across both basic blocks and translation blocks. */
31
diff --git a/tcg/tcg.c b/tcg/tcg.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/tcg.c
34
+++ b/tcg/tcg.c
35
@@ -XXX,XX +XXX,XX @@ void tcg_temp_free_internal(TCGTemp *ts)
36
TCGContext *s = tcg_ctx;
37
int k, idx;
38
39
- /* In order to simplify users of tcg_constant_*, silently ignore free. */
40
- if (ts->kind == TEMP_CONST) {
41
+ switch (ts->kind) {
42
+ case TEMP_CONST:
43
+ /*
44
+ * In order to simplify users of tcg_constant_*,
45
+ * silently ignore free.
46
+ */
47
return;
48
+ case TEMP_NORMAL:
49
+ case TEMP_LOCAL:
50
+ break;
51
+ default:
52
+ g_assert_not_reached();
53
}
54
55
#if defined(CONFIG_DEBUG_TCG)
56
@@ -XXX,XX +XXX,XX @@ void tcg_temp_free_internal(TCGTemp *ts)
57
}
58
#endif
59
60
- tcg_debug_assert(ts->kind < TEMP_GLOBAL);
61
tcg_debug_assert(ts->temp_allocated != 0);
62
ts->temp_allocated = 0;
63
64
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_start(TCGContext *s)
65
case TEMP_GLOBAL:
66
break;
67
case TEMP_NORMAL:
68
+ case TEMP_EBB:
69
val = TEMP_VAL_DEAD;
70
/* fall through */
71
case TEMP_LOCAL:
72
@@ -XXX,XX +XXX,XX @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size,
73
case TEMP_LOCAL:
74
snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
75
break;
76
+ case TEMP_EBB:
77
+ snprintf(buf, buf_size, "ebb%d", idx - s->nb_globals);
78
+ break;
79
case TEMP_NORMAL:
80
snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
81
break;
82
@@ -XXX,XX +XXX,XX @@ static void la_bb_end(TCGContext *s, int ng, int nt)
83
state = TS_DEAD | TS_MEM;
84
break;
85
case TEMP_NORMAL:
86
+ case TEMP_EBB:
87
case TEMP_CONST:
88
state = TS_DEAD;
89
break;
90
@@ -XXX,XX +XXX,XX @@ static void la_global_sync(TCGContext *s, int ng)
91
}
92
93
/*
94
- * liveness analysis: conditional branch: all temps are dead,
95
- * globals and local temps should be synced.
96
+ * liveness analysis: conditional branch: all temps are dead unless
97
+ * explicitly live-across-conditional-branch, globals and local temps
98
+ * should be synced.
99
*/
100
static void la_bb_sync(TCGContext *s, int ng, int nt)
101
{
102
@@ -XXX,XX +XXX,XX @@ static void la_bb_sync(TCGContext *s, int ng, int nt)
103
case TEMP_NORMAL:
104
s->temps[i].state = TS_DEAD;
105
break;
106
+ case TEMP_EBB:
107
case TEMP_CONST:
108
continue;
109
default:
110
@@ -XXX,XX +XXX,XX @@ static bool liveness_pass_2(TCGContext *s)
111
TCGTemp *dts = tcg_temp_alloc(s);
112
dts->type = its->type;
113
dts->base_type = its->base_type;
114
+ dts->kind = TEMP_EBB;
115
its->state_ptr = dts;
116
} else {
117
its->state_ptr = NULL;
118
@@ -XXX,XX +XXX,XX @@ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead)
119
new_type = TEMP_VAL_MEM;
120
break;
121
case TEMP_NORMAL:
122
+ case TEMP_EBB:
123
new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD;
124
break;
125
case TEMP_CONST:
126
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
127
temp_save(s, ts, allocated_regs);
128
break;
129
case TEMP_NORMAL:
130
+ case TEMP_EBB:
131
/* The liveness analysis already ensures that temps are dead.
132
Keep an tcg_debug_assert for safety. */
133
tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD);
134
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
135
}
136
137
/*
138
- * At a conditional branch, we assume all temporaries are dead and
139
- * all globals and local temps are synced to their location.
140
+ * At a conditional branch, we assume all temporaries are dead unless
141
+ * explicitly live-across-conditional-branch; all globals and local
142
+ * temps are synced to their location.
143
*/
144
static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs)
145
{
146
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs)
147
case TEMP_NORMAL:
148
tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD);
149
break;
150
+ case TEMP_EBB:
151
case TEMP_CONST:
152
break;
153
default:
154
--
155
2.34.1
diff view generated by jsdifflib
[PULL 3/4] accel/tcg: Remove ATOMIC_MMU_IDX
Deleted patch
1
The last use of this macro was removed in f3e182b10013
2
("accel/tcg: Push trace info building into atomic_common.c.inc")
3
1
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
accel/tcg/cputlb.c | 1 -
8
accel/tcg/user-exec.c | 1 -
9
2 files changed, 2 deletions(-)
10
11
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/accel/tcg/cputlb.c
14
+++ b/accel/tcg/cputlb.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
16
glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
17
18
#define ATOMIC_MMU_CLEANUP
19
-#define ATOMIC_MMU_IDX get_mmuidx(oi)
20
21
#include "atomic_common.c.inc"
22
23
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/accel/tcg/user-exec.c
26
+++ b/accel/tcg/user-exec.c
27
@@ -XXX,XX +XXX,XX @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
28
#define ATOMIC_NAME(X) \
29
glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
30
#define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
31
-#define ATOMIC_MMU_IDX MMU_USER_IDX
32
33
#define DATA_SIZE 1
34
#include "atomic_template.h"
35
--
36
2.34.1
diff view generated by jsdifflib
[PULL 4/4] tcg: Add tcg_constant_ptr
[PATCH v3 13/28] target/mips: Use VADDR_PRIx for logging pc_next
1
Similar to tcg_const_ptr, defer to tcg_constant_{i32,i64}.
1
DisasContextBase.pc_next has type vaddr; use the correct log format.
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual addresses")
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
5
---
6
include/tcg/tcg.h | 2 ++
6
target/mips/tcg/octeon_translate.c | 4 ++--
7
1 file changed, 2 insertions(+)
7
1 file changed, 2 insertions(+), 2 deletions(-)
8
8
9
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
9
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
10
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
11
--- a/include/tcg/tcg.h
11
--- a/target/mips/tcg/octeon_translate.c
12
+++ b/include/tcg/tcg.h
12
+++ b/target/mips/tcg/octeon_translate.c
13
@@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
13
@@ -XXX,XX +XXX,XX @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
14
#if UINTPTR_MAX == UINT32_MAX
14
TCGv p;
15
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
15
16
# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
16
if (ctx->hflags & MIPS_HFLAG_BMASK) {
17
+# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)))
17
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
18
#else
18
- TARGET_FMT_lx "\n", ctx->base.pc_next);
19
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
19
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx "\n",
20
# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
20
+ ctx->base.pc_next);
21
+# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)))
21
generate_exception_end(ctx, EXCP_RI);
22
#endif
22
return true;
23
23
}
24
TCGLabel *gen_new_label(void);
25
--
24
--
26
2.34.1
25
2.43.0
27
28
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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