target/arm: More trivial features, A76, N1

[PATCH 0/7] target/arm: More trivial features, A76, N1

Richard Henderson posted 7 patches 2 years, 1 month ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20220410055725.380246-1-richard.henderson@linaro.org

Maintainers: Radoslaw Biernacki <rad@semihalf.com>, Peter Maydell <peter.maydell@linaro.org>, Leif Lindholm <leif@nuviainc.com>

target/arm/cpu.h           |  39 +++++++++++
hw/arm/sbsa-ref.c          |   2 +
hw/arm/virt.c              |   2 +
target/arm/cpu64.c         | 131 +++++++++++++++++++++++++++++++++++++
target/arm/cpu_tcg.c       |   2 +
target/arm/helper.c        |  70 +++++++++++++++++++-
target/arm/translate-a64.c |   1 +
7 files changed, 246 insertions(+), 1 deletion(-)

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[PATCH 0/7] target/arm: More trivial features, A76, N1

Posted by Richard Henderson 2 years, 1 month ago

Based-on: 20220409000742.293691-1-richard.henderson@linaro.org
("target/arm: Implement features Debugv8p4, RAS, IESB")

3 more completely trivial features, and a 4th that merely
needs to add some state words.

Add definitions for cortex-a76 (also requires gicv4) and
neoverse-n1 (also requires gicv4.1), but we now have all
of the in-cpu features implemented.


r~


Richard Henderson (7):
  target/arm: Enable FEAT_CSV2 for -cpu max
  target/arm: Update ISAR fields for ARMv8.8
  target/arm: Enable FEAT_CSV2_2 for -cpu max
  target/arm: Enable FEAT_CSV3 for -cpu max
  target/arm: Enable FEAT_DGH for -cpu max
  target/arm: Define cortex-a76
  target/arm: Define neoverse-n1

 target/arm/cpu.h           |  39 +++++++++++
 hw/arm/sbsa-ref.c          |   2 +
 hw/arm/virt.c              |   2 +
 target/arm/cpu64.c         | 131 +++++++++++++++++++++++++++++++++++++
 target/arm/cpu_tcg.c       |   2 +
 target/arm/helper.c        |  70 +++++++++++++++++++-
 target/arm/translate-a64.c |   1 +
 7 files changed, 246 insertions(+), 1 deletion(-)

-- 
2.25.1