NPCM8XX BMCs are the successors of the NPCM7XX BMCs. They feature
quad-core ARM Cortex A35 that supports both 32 bits and 64 bits
operations. This patch set aims to support basic functionalities
of the NPCM7XX BMCs. The patch set includes:

1. We derive most devices from the 7XX models and
made some modifications.
2. We have constructed a minimum vBootROM similar to the 7XX one at
https://github.com/google/vbootrom/tree/master/npcm8xx
and included it in the patch set.
3.  We added a new NPCM8XX SOC and an evaluation
board machine npcm845-evb.

The OpenBMC for NPCM845 evaluation board can be found at:
https://github.com/Nuvoton-Israel/openbmc/tree/npcm-v2.10/meta-evb/meta-evb-nuvoton/meta-evb-npcm845

The patch set can boot the evaluation board image built from the source
above to login prompt.

Hao Wu (11):
  docs/system/arm: Add Description for NPCM8XX SoC
  hw/ssi: Make flash size a property in NPCM7XX FIU
  hw/misc: Support NPCM8XX GCR module
  hw/misc: Support NPCM8XX CLK Module Registers
  hw/misc: Store DRAM size in NPCM8XX GCR Module
  hw/intc: Add a property to allow GIC to reset into non secure mode
  hw/misc: Support 8-bytes memop in NPCM GCR module
  hw/net: Add NPCM8XX PCS Module
  pc-bios: Add NPCM8xx Bootrom
  hw/arm: Add NPCM8XX SoC
  hw/arm: Add NPCM845 Evaluation board

 MAINTAINERS                                   |   9 +-
 configs/devices/aarch64-softmmu/default.mak   |   1 +
 docs/system/arm/nuvoton.rst                   |  20 +-
 hw/arm/Kconfig                                |  11 +
 hw/arm/meson.build                            |   1 +
 hw/arm/npcm7xx.c                              |   6 +
 hw/arm/npcm8xx.c                              | 806 ++++++++++++++++++
 hw/arm/npcm8xx_boards.c                       | 257 ++++++
 hw/intc/arm_gic_common.c                      |   2 +
 hw/misc/meson.build                           |   4 +-
 hw/misc/npcm7xx_gcr.c                         | 269 ------
 hw/misc/{npcm7xx_clk.c => npcm_clk.c}         | 238 ++++--
 hw/misc/npcm_gcr.c                            | 492 +++++++++++
 hw/misc/trace-events                          |  12 +-
 hw/net/meson.build                            |   1 +
 hw/net/npcm_pcs.c                             | 409 +++++++++
 hw/net/trace-events                           |   4 +
 hw/ssi/npcm7xx_fiu.c                          |   6 +-
 include/hw/arm/npcm7xx.h                      |   8 +-
 include/hw/arm/npcm8xx.h                      | 126 +++
 include/hw/misc/{npcm7xx_clk.h => npcm_clk.h} |  43 +-
 include/hw/misc/{npcm7xx_gcr.h => npcm_gcr.h} |  30 +-
 include/hw/net/npcm_pcs.h                     |  42 +
 include/hw/ssi/npcm7xx_fiu.h                  |   1 +
 pc-bios/npcm8xx_bootrom.bin                   | Bin 0 -> 608 bytes
 25 files changed, 2428 insertions(+), 370 deletions(-)
 create mode 100644 hw/arm/npcm8xx.c
 create mode 100644 hw/arm/npcm8xx_boards.c
 delete mode 100644 hw/misc/npcm7xx_gcr.c
 rename hw/misc/{npcm7xx_clk.c => npcm_clk.c} (81%)
 create mode 100644 hw/misc/npcm_gcr.c
 create mode 100644 hw/net/npcm_pcs.c
 create mode 100644 include/hw/arm/npcm8xx.h
 rename include/hw/misc/{npcm7xx_clk.h => npcm_clk.h} (83%)
 rename include/hw/misc/{npcm7xx_gcr.h => npcm_gcr.h} (55%)
 create mode 100644 include/hw/net/npcm_pcs.h
 create mode 100644 pc-bios/npcm8xx_bootrom.bin

-- 
2.35.1.1094.g7c7d902a7c-goog

On Tue, 5 Apr 2022 at 23:37, Hao Wu <wuhaotsh@google.com> wrote:
>
> NPCM8XX BMCs are the successors of the NPCM7XX BMCs. They feature
> quad-core ARM Cortex A35 that supports both 32 bits and 64 bits
> operations.

Here and in the documentation patch you say "Cortex-A35", but the
patch implementing the new SoC creates Cortex-A53 CPUs. Which
is correct ?

thanks
-- PMM

Thanks for all the comments you gave! I'll go over and address them
recently.

For this question, The actual CPU should be cortex A35. However, I don't see
them supported in QEMU. If I inserted CPU with "cortex-a35" QEMU will
complain:
qemu-system-aarch64: missing object type 'cortex-a35-arm-cpu'

What should I do here?

On Thu, Apr 21, 2022 at 3:45 AM Peter Maydell <peter.maydell@linaro.org>
wrote:

> On Tue, 5 Apr 2022 at 23:37, Hao Wu <wuhaotsh@google.com> wrote:
> >
> > NPCM8XX BMCs are the successors of the NPCM7XX BMCs. They feature
> > quad-core ARM Cortex A35 that supports both 32 bits and 64 bits
> > operations.
>
> Here and in the documentation patch you say "Cortex-A35", but the
> patch implementing the new SoC creates Cortex-A53 CPUs. Which
> is correct ?
>
> thanks
> -- PMM
>

On Thu, 21 Apr 2022 at 17:29, Hao Wu <wuhaotsh@google.com> wrote:
>
> Thanks for all the comments you gave! I'll go over and address them recently.
>
> For this question, The actual CPU should be cortex A35. However, I don't see
> them supported in QEMU. If I inserted CPU with "cortex-a35" QEMU will complain:
> qemu-system-aarch64: missing object type 'cortex-a35-arm-cpu'
>
> What should I do here?

You need to implement the new CPU type first... This means adding
something to target/arm/cpu64.c which will look similar to the
existing CPU handling. You need to watch out for:
 * getting all the ID register values right (check the TRM for the CPU)
 * implementing whatever the right impdef system registers are
 * checking whether QEMU is still missing support for any of the
   architectural features that the A35 implements (what QEMU
   supports is listed in docs/system/arm/emulation.rst)

It's typically not much code but quite a lot of cross-checking
against the TRM for the CPU that we're not missing pieces...
Since you can add the A35 as a supported CPU type for the 'virt'
board you can do A35 support as a separate patchset that doesn't
depend on the npmc8xx work.

https://patchew.org/QEMU/20220417174426.711829-1-richard.henderson@linaro.org/20220417174426.711829-60-richard.henderson@linaro.org/
is an example of how to add a new CPU (in that case the A76), at
the end of a large patchset from RTH that's still going through
code review.

-- PMM

Thanks!

I can add the new CPU type to virt in a separate patch set. It might take a
while before I send out
that patch set.

Since this patch set will be dependent on that I won't send out a v2 on
this patch set until that finishes.

On Thu, Apr 21, 2022 at 9:42 AM Peter Maydell <peter.maydell@linaro.org>
wrote:

> On Thu, 21 Apr 2022 at 17:29, Hao Wu <wuhaotsh@google.com> wrote:
> >
> > Thanks for all the comments you gave! I'll go over and address them
> recently.
> >
> > For this question, The actual CPU should be cortex A35. However, I don't
> see
> > them supported in QEMU. If I inserted CPU with "cortex-a35" QEMU will
> complain:
> > qemu-system-aarch64: missing object type 'cortex-a35-arm-cpu'
> >
> > What should I do here?
>
> You need to implement the new CPU type first... This means adding
> something to target/arm/cpu64.c which will look similar to the
> existing CPU handling. You need to watch out for:
>  * getting all the ID register values right (check the TRM for the CPU)
>  * implementing whatever the right impdef system registers are
>  * checking whether QEMU is still missing support for any of the
>    architectural features that the A35 implements (what QEMU
>    supports is listed in docs/system/arm/emulation.rst)
>
> It's typically not much code but quite a lot of cross-checking
> against the TRM for the CPU that we're not missing pieces...
> Since you can add the A35 as a supported CPU type for the 'virt'
> board you can do A35 support as a separate patchset that doesn't
> depend on the npmc8xx work.
>
>
> https://patchew.org/QEMU/20220417174426.711829-1-richard.henderson@linaro.org/20220417174426.711829-60-richard.henderson@linaro.org/
> is an example of how to add a new CPU (in that case the A76), at
> the end of a large patchset from RTH that's still going through
> code review.
>
> -- PMM
>