[PULL 0/2] target-arm queue
[PULL 0/2] target-arm queue
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Couple of trivial fixes for rc3...
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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The following changes since commit 20661b75ea6093f5e59079d00a778a972d6732c5:
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thanks
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-- PMM
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Merge tag 'pull-ppc-20220404' of https://github.com/legoater/qemu into staging (2022-04-04 15:48:55 +0100)
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220405
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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for you to fetch changes up to 80b952bb694a90f7e530d407b01066894e64a443:
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation. (2022-04-05 09:29:28 +0100)
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm: Fix bug where we weren't initializing
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* docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
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guarded bit state when combining S1/S2 attrs
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* xlnx-bbram: hw/nvram: Fix uninitialized Error *
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----------------------------------------------------------------
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----------------------------------------------------------------
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Pavel Pisa (1):
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Richard Henderson (2):
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docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
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target/arm: PTE bit GP only applies to stage1
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target/arm: Copy guarded bit in combine_cacheattrs
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Tong Ho (1):
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target/arm/ptw.c | 11 ++++++-----
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xlnx-bbram: hw/nvram: Fix uninitialized Error *
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1 file changed, 6 insertions(+), 5 deletions(-)
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docs/system/devices/can.rst | 6 +++---
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hw/nvram/xlnx-bbram.c | 2 +-
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2 files changed, 4 insertions(+), 4 deletions(-)
diff view generated by jsdifflib
[PULL 2/2] docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
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From: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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From: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Only perform the extract of GP during the stage1 walk.
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Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
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Message-id: 20220402204523.32643-1-pisa@cmp.felk.cvut.cz
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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---
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docs/system/devices/can.rst | 6 +++---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 3 insertions(+), 3 deletions(-)
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/docs/system/devices/can.rst b/docs/system/devices/can.rst
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/system/devices/can.rst
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--- a/target/arm/ptw.c
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+++ b/docs/system/devices/can.rst
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ Links to other resources
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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(5) `GNU/Linux, CAN and CANopen in Real-time Control Applications Slides from LinuxDays 2017 (include updated RTLWS 2015 content) <https://www.linuxdays.cz/2017/video/Pavel_Pisa-CAN_canopen.pdf>`_
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result->f.attrs.secure = false;
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(6) `Linux SocketCAN utilities <https://github.com/linux-can/can-utils>`_
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}
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(7) `CTU CAN FD project including core VHDL design, Linux driver, test utilities etc. <https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core>`_
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- (8) `CTU CAN FD Core Datasheet Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/Progdokum.pdf>`_
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- (9) `CTU CAN FD Core System Architecture Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ctu_can_fd_architecture.pdf>`_
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- (10) `CTU CAN FD Driver Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/driver_doc/ctucanfd-driver.html>`_
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ (8) `CTU CAN FD Core Datasheet Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf>`_
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- }
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+ (9) `CTU CAN FD Core System Architecture Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/System_Architecture.pdf>`_
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-
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+ (10) `CTU CAN FD Driver Documentation <https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/linux_driver/build/ctucanfd-driver.html>`_
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if (regime_is_stage2(mmu_idx)) {
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(11) `Integration with PCIe interfacing for Intel/Altera Cyclone IV based board <https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd>`_
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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--
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2.25.1
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2.34.1
diff view generated by jsdifflib
[PULL 1/2] xlnx-bbram: hw/nvram: Fix uninitialized Error *
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
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From: Tong Ho <tong.ho@xilinx.com>
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From: Richard Henderson <richard.henderson@linaro.org>
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This adds required initialization of Error * variable.
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The guarded bit comes from the stage1 walk.
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Signed-off-by: Tong Ho <tong.ho@xilinx.com>
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Fixes: Coverity CID 1507929
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Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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---
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hw/nvram/xlnx-bbram.c | 2 +-
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+), 1 deletion(-)
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1 file changed, 1 insertion(+)
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diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/nvram/xlnx-bbram.c
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--- a/target/arm/ptw.c
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+++ b/hw/nvram/xlnx-bbram.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool bbram_pgm_enabled(XlnxBBRam *s)
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
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assert(!s1.is_s2_format);
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{
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ret.is_s2_format = false;
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- Error *errp;
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+ ret.guarded = s1.guarded;
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+ Error *errp = NULL;
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if (s1.attrs == 0xf0) {
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error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
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tagged = true;
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blk_name(s->blk), detail);
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--
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--
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2.25.1
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2.34.1
diff view generated by jsdifflib

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