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Couple of trivial fixes for rc3...
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Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
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ethernet device failed 'make check' on big-endian hosts.
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The following changes since commit 20661b75ea6093f5e59079d00a778a972d6732c5:
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-- PMM
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Merge tag 'pull-ppc-20220404' of https://github.com/legoater/qemu into staging (2022-04-04 15:48:55 +0100)
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The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
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Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220405
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
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for you to fetch changes up to 80b952bb694a90f7e530d407b01066894e64a443:
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for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
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docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation. (2022-04-05 09:29:28 +0100)
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target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
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* Correctly initialize MDCR_EL2.HPMN
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* xlnx-bbram: hw/nvram: Fix uninitialized Error *
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* versal: Use nr_apu_cpus in favor of hard coding 2
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* accel/tcg: Add URL of clang bug to comment about our workaround
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* Add support for FEAT_DIT, Data Independent Timing
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* Remove GPIO from unimplemented NPCM7XX
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* Fix SCR RES1 handling
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* Don't migrate CPUARMState.features
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----------------------------------------------------------------
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----------------------------------------------------------------
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Pavel Pisa (1):
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Aaron Lindsay (1):
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docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
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target/arm: Don't migrate CPUARMState.features
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Tong Ho (1):
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Daniel Müller (1):
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xlnx-bbram: hw/nvram: Fix uninitialized Error *
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target/arm: Correctly initialize MDCR_EL2.HPMN
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docs/system/devices/can.rst | 6 +++---
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Edgar E. Iglesias (1):
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hw/nvram/xlnx-bbram.c | 2 +-
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hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
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2 files changed, 4 insertions(+), 4 deletions(-)
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Hao Wu (1):
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hw/arm: Remove GPIO from unimplemented NPCM7XX
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Mike Nawrocki (1):
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target/arm: Fix SCR RES1 handling
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Peter Maydell (2):
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arm: Update infocenter.arm.com URLs
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accel/tcg: Add URL of clang bug to comment about our workaround
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Rebecca Cran (4):
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target/arm: Add support for FEAT_DIT, Data Independent Timing
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target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
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target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
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target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
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include/hw/dma/pl080.h | 7 ++--
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include/hw/misc/arm_integrator_debug.h | 2 +-
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include/hw/ssi/pl022.h | 5 ++-
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target/arm/cpu.h | 17 ++++++++
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target/arm/internals.h | 6 +++
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accel/tcg/cpu-exec.c | 25 +++++++++---
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hw/arm/aspeed_ast2600.c | 2 +-
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hw/arm/musca.c | 4 +-
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hw/arm/npcm7xx.c | 8 ----
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hw/arm/xlnx-versal.c | 4 +-
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hw/misc/arm_integrator_debug.c | 2 +-
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hw/timer/arm_timer.c | 7 ++--
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target/arm/cpu.c | 4 ++
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target/arm/cpu64.c | 5 +++
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target/arm/helper-a64.c | 27 +++++++++++--
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target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
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target/arm/machine.c | 2 +-
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target/arm/op_helper.c | 9 +----
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target/arm/translate-a64.c | 12 ++++++
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19 files changed, 164 insertions(+), 55 deletions(-)
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diff view generated by jsdifflib
Deleted patch
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From: Tong Ho <tong.ho@xilinx.com>
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1
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This adds required initialization of Error * variable.
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Signed-off-by: Tong Ho <tong.ho@xilinx.com>
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Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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hw/nvram/xlnx-bbram.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/nvram/xlnx-bbram.c
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+++ b/hw/nvram/xlnx-bbram.c
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@@ -XXX,XX +XXX,XX @@ static bool bbram_pgm_enabled(XlnxBBRam *s)
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static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
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{
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- Error *errp;
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+ Error *errp = NULL;
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error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
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blk_name(s->blk), detail);
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--
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2.25.1
diff view generated by jsdifflib
Deleted patch
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From: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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1
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
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Message-id: 20220402204523.32643-1-pisa@cmp.felk.cvut.cz
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/devices/can.rst | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/docs/system/devices/can.rst b/docs/system/devices/can.rst
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/system/devices/can.rst
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+++ b/docs/system/devices/can.rst
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@@ -XXX,XX +XXX,XX @@ Links to other resources
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(5) `GNU/Linux, CAN and CANopen in Real-time Control Applications Slides from LinuxDays 2017 (include updated RTLWS 2015 content) <https://www.linuxdays.cz/2017/video/Pavel_Pisa-CAN_canopen.pdf>`_
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(6) `Linux SocketCAN utilities <https://github.com/linux-can/can-utils>`_
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(7) `CTU CAN FD project including core VHDL design, Linux driver, test utilities etc. <https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core>`_
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- (8) `CTU CAN FD Core Datasheet Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/Progdokum.pdf>`_
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- (9) `CTU CAN FD Core System Architecture Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ctu_can_fd_architecture.pdf>`_
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- (10) `CTU CAN FD Driver Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/driver_doc/ctucanfd-driver.html>`_
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+ (8) `CTU CAN FD Core Datasheet Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf>`_
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+ (9) `CTU CAN FD Core System Architecture Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/System_Architecture.pdf>`_
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+ (10) `CTU CAN FD Driver Documentation <https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/linux_driver/build/ctucanfd-driver.html>`_
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(11) `Integration with PCIe interfacing for Intel/Altera Cyclone IV based board <https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd>`_
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--
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2.25.1
diff view generated by jsdifflib