[v1] riscv-to-apply queue

[PULL 0/2] riscv-to-apply queue

Alistair Francis posted 2 patches 3 years, 1 month ago

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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>

There is a newer version of this series

target/riscv/csr.c                      | 14 ++++++++------
target/riscv/insn_trans/trans_rvv.c.inc |  5 +++++
2 files changed, 13 insertions(+), 6 deletions(-)

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[PULL 0/2] riscv-to-apply queue

Posted by Alistair Francis 3 years, 1 month ago

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit d5341e09135b871199073572f53bc11ae9b44897:

  Merge tag 'pull-tcg-20220331' of https://gitlab.com/rth7680/qemu into staging (2022-03-31 18:36:08 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220401

for you to fetch changes up to 8ff8ac63298611c8373b294ec936475b1a33f63f:

  target/riscv: rvv: Add missing early exit condition for whole register load/store (2022-04-01 08:40:55 +1000)

----------------------------------------------------------------
Sixth RISC-V PR for QEMU 7.0

This is a last minute RISC-V PR for 7.0.

It includes a fix to avoid leaking no translation TLB entries. This
incorrectly cached uncachable baremetal entries. This would break Linux
boot while single stepping. As the fix is pretty straight forward (flush
the cache more often) it's being pulled in for 7.0.

At the same time I have included a RISC-V vector extension fixup patch.

----------------------------------------------------------------
Palmer Dabbelt (1):
      target/riscv: Avoid leaking "no translation" TLB entries

Yueh-Ting (eop) Chen (1):
      target/riscv: rvv: Add missing early exit condition for whole register load/store

 target/riscv/csr.c                      | 14 ++++++++------
 target/riscv/insn_trans/trans_rvv.c.inc |  5 +++++
 2 files changed, 13 insertions(+), 6 deletions(-)

Re: [PULL 0/2] riscv-to-apply queue

Posted by Peter Maydell 3 years, 1 month ago

On Fri, 1 Apr 2022 at 00:50, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit d5341e09135b871199073572f53bc11ae9b44897:
>
>   Merge tag 'pull-tcg-20220331' of https://gitlab.com/rth7680/qemu into staging (2022-03-31 18:36:08 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220401
>
> for you to fetch changes up to 8ff8ac63298611c8373b294ec936475b1a33f63f:
>
>   target/riscv: rvv: Add missing early exit condition for whole register load/store (2022-04-01 08:40:55 +1000)
>
> ----------------------------------------------------------------
> Sixth RISC-V PR for QEMU 7.0
>
> This is a last minute RISC-V PR for 7.0.
>
> It includes a fix to avoid leaking no translation TLB entries. This
> incorrectly cached uncachable baremetal entries. This would break Linux
> boot while single stepping. As the fix is pretty straight forward (flush
> the cache more often) it's being pulled in for 7.0.
>
> At the same time I have included a RISC-V vector extension fixup patch.
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.

-- PMM