[PULL 0/2] target-arm queue
[PULL 0/3] target-arm queue
1
Just two small bug fixes for the next rc.
1
Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
2
2
3
The following changes since commit f345abe36527a8b575482bb5a0616f43952bf1f4:
3
-- PMM
4
4
5
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-03-25 10:14:47 +0000)
5
The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
6
7
Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
6
8
7
are available in the Git repository at:
9
are available in the Git repository at:
8
10
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220325
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
10
12
11
for you to fetch changes up to c7ca3ad5e756e263daf082c315e311593ccec3d1:
13
for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
12
14
13
hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging (2022-03-25 14:41:06 +0000)
15
target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
14
16
15
----------------------------------------------------------------
17
----------------------------------------------------------------
16
target-arm queue:
18
target-arm queue:
17
* hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging
19
* Fix KVM SVE ID register probe code
18
* target/arm: Fix sve_ld1_z and sve_st1_z vs MMIO
19
20
20
----------------------------------------------------------------
21
----------------------------------------------------------------
21
Peter Maydell (1):
22
Richard Henderson (3):
22
hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging
23
target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
24
target/arm: Set KVM_ARM_VCPU_SVE while probing the host
25
target/arm: Move sve probe inside kvm >= 4.15 branch
23
26
24
Richard Henderson (1):
27
target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
25
target/arm: Fix sve_ld1_z and sve_st1_z vs MMIO
28
1 file changed, 22 insertions(+), 23 deletions(-)
26
27
hw/intc/arm_gicv3_its.c | 4 ++--
28
target/arm/sve_helper.c | 10 ++++++++--
29
2 files changed, 10 insertions(+), 4 deletions(-)
diff view generated by jsdifflib
New patch
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Indication for support for SVE will not depend on whether we
4
perform the query on the main kvm_state or the temp vcpu.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
}
20
}
21
22
- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
23
+ sve_supported = kvm_arm_sve_supported();
24
25
/* Add feature bits that can't appear until after VCPU init. */
26
if (sve_supported) {
27
--
28
2.25.1
diff view generated by jsdifflib
[PULL 2/2] hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() logging
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
1
In commit 84d43d2e82da we rearranged the logging of errors in
1
From: Richard Henderson <richard.henderson@linaro.org>
2
process_mapc(), and inadvertently dropped the trailing newlines
3
from the log messages. Restore them. The same commit also
4
attempted to switch the ICID printing to hex (which is how we
5
print ICIDs elsewhere) but only did half the job, adding the
6
0x prefix but leaving the format string at %d; correct to %x.
7
2
8
Fixes: 84d43d2e82da ("hw/intc/arm_gicv3_its: In MAPC with V=0, don't check rdbase field")
3
Because we weren't setting this flag, our probe of ID_AA64ZFR0
4
was always returning zero. This also obviates the adjustment
5
of ID_AA64PFR0, which had sanitized the SVE field.
6
7
The effects of the bug are not visible, because the only thing that
8
ID_AA64ZFR0 is used for within qemu at present is tcg translation.
9
The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
10
11
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
---
16
---
13
hw/intc/arm_gicv3_its.c | 4 ++--
17
target/arm/kvm64.c | 27 +++++++++++++--------------
14
1 file changed, 2 insertions(+), 2 deletions(-)
18
1 file changed, 13 insertions(+), 14 deletions(-)
15
19
16
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
20
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gicv3_its.c
22
--- a/target/arm/kvm64.c
19
+++ b/hw/intc/arm_gicv3_its.c
23
+++ b/target/arm/kvm64.c
20
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt)
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
21
trace_gicv3_its_cmd_mapc(icid, cte.rdbase, cte.valid);
25
bool sve_supported;
22
26
bool pmu_supported = false;
23
if (icid >= s->ct.num_entries) {
27
uint64_t features = 0;
24
- qemu_log_mask(LOG_GUEST_ERROR, "ITS MAPC: invalid ICID 0x%d", icid);
28
- uint64_t t;
25
+ qemu_log_mask(LOG_GUEST_ERROR, "ITS MAPC: invalid ICID 0x%x\n", icid);
29
int err;
26
return CMD_CONTINUE;
30
31
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
struct kvm_vcpu_init init = { .target = -1, };
34
35
/*
36
- * Ask for Pointer Authentication if supported. We can't play the
37
- * SVE trick of synthesising the ID reg as KVM won't tell us
38
- * whether we have the architected or IMPDEF version of PAuth, so
39
- * we have to use the actual ID regs.
40
+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
41
+ * which is otherwise RAZ.
42
+ */
43
+ sve_supported = kvm_arm_sve_supported();
44
+ if (sve_supported) {
45
+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
46
+ }
47
+
48
+ /*
49
+ * Ask for Pointer Authentication if supported, so that we get
50
+ * the unsanitized field values for AA64ISAR1_EL1.
51
*/
52
if (kvm_arm_pauth_supported()) {
53
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
54
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
55
}
27
}
56
}
28
if (cte.valid && cte.rdbase >= s->gicv3->num_cpu) {
57
29
qemu_log_mask(LOG_GUEST_ERROR,
58
- sve_supported = kvm_arm_sve_supported();
30
- "ITS MAPC: invalid RDBASE %u ", cte.rdbase);
59
-
31
+ "ITS MAPC: invalid RDBASE %u\n", cte.rdbase);
60
- /* Add feature bits that can't appear until after VCPU init. */
32
return CMD_CONTINUE;
61
if (sve_supported) {
33
}
62
- t = ahcf->isar.id_aa64pfr0;
34
63
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
64
- ahcf->isar.id_aa64pfr0 = t;
65
-
66
/*
67
* There is a range of kernels between kernel commit 73433762fcae
68
* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
69
* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
70
- * SVE support, so we only read it here, rather than together with all
71
- * the other ID registers earlier.
72
+ * SVE support, which resulted in an error rather than RAZ.
73
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
74
*/
75
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
76
ARM64_SYS_REG(3, 0, 0, 4, 4));
35
--
77
--
36
2.25.1
78
2.25.1
37
38
diff view generated by jsdifflib
[PULL 1/2] target/arm: Fix sve_ld1_z and sve_st1_z vs MMIO
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Both of these functions missed handling the TLB_MMIO flag
3
The test for the IF block indicates no ID registers are exposed, much
4
during the conversion to handle MTE.
4
less host support for SVE. Move the SVE probe into the ELSE block.
5
5
6
Fixes: 10a85e2c8ab6 ("target/arm: Reuse sve_probe_page for gather loads")
7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/925
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220324010932.190428-1-richard.henderson@linaro.org
7
Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/sve_helper.c | 10 ++++++++--
11
target/arm/kvm64.c | 22 +++++++++++-----------
14
1 file changed, 8 insertions(+), 2 deletions(-)
12
1 file changed, 11 insertions(+), 11 deletions(-)
15
13
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve_helper.c
16
--- a/target/arm/kvm64.c
19
+++ b/target/arm/sve_helper.c
17
+++ b/target/arm/kvm64.c
20
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
21
if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
19
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
22
mte_check(env, mtedesc, addr, retaddr);
20
ARM64_SYS_REG(3, 3, 9, 12, 0));
23
}
21
}
24
- host_fn(&scratch, reg_off, info.host);
22
- }
25
+ if (unlikely(info.flags & TLB_MMIO)) {
23
26
+ tlb_fn(env, &scratch, reg_off, addr, retaddr);
24
- if (sve_supported) {
27
+ } else {
25
- /*
28
+ host_fn(&scratch, reg_off, info.host);
26
- * There is a range of kernels between kernel commit 73433762fcae
29
+ }
27
- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
30
} else {
28
- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
31
/* Element crosses the page boundary. */
29
- * SVE support, which resulted in an error rather than RAZ.
32
sve_probe_page(&info2, false, env, addr + in_page, 0,
30
- * So only read the register if we set KVM_ARM_VCPU_SVE above.
33
@@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
31
- */
34
if (likely(in_page >= msize)) {
32
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
35
sve_probe_page(&info, false, env, addr, 0, MMU_DATA_STORE,
33
- ARM64_SYS_REG(3, 0, 0, 4, 4));
36
mmu_idx, retaddr);
34
+ if (sve_supported) {
37
- host[i] = info.host;
35
+ /*
38
+ if (!(info.flags & TLB_MMIO)) {
36
+ * There is a range of kernels between kernel commit 73433762fcae
39
+ host[i] = info.host;
37
+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
40
+ }
38
+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
41
} else {
39
+ * enabled SVE support, which resulted in an error rather than RAZ.
42
/*
40
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
43
* Element crosses the page boundary.
41
+ */
42
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
43
+ ARM64_SYS_REG(3, 0, 0, 4, 4));
44
+ }
45
}
46
47
kvm_arm_destroy_scratch_host_vcpu(fdarray);
44
--
48
--
45
2.25.1
49
2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.