[v2] RISC-V Smstateen support

[RFC PATCH v2 0/4] RISC-V Smstateen support

Mayuresh Chitale posted 4 patches 2 years, 1 month ago

Diff against v1 v3 v4 v5 v6 v7 v8 v9 v10 v11
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target/riscv/cpu.c      |   2 +
target/riscv/cpu.h      |   4 +
target/riscv/cpu_bits.h |  36 +++
target/riscv/csr.c      | 554 +++++++++++++++++++++++++++++++++++++++-
target/riscv/machine.c  |  22 +-
5 files changed, 614 insertions(+), 4 deletions(-)

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[RFC PATCH v2 0/4] RISC-V Smstateen support

Posted by Mayuresh Chitale 2 years, 1 month ago

This series adds support for the Smstateen specification which provides
a mechanism plug potential covert channels which are opened by extensions
that add to processor state that may not get context-switched. Currently
access to AIA registers, *envcfg registers and floating point(fcsr) is
controlled via smstateen.

This series depends on the following series from Atish Patra:

https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00031.html
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00142.html


Changes in v2:
- Make h/s/envcfg bits in m/h/stateen registers as writeable by default.

Mayuresh Chitale (4):
  target/riscv: Add smstateen support
  target/riscv: smstateen check for h/senvcfg
  target/riscv: smstateen check for fcsr
  target/riscv: smstateen check for AIA/IMSIC

 target/riscv/cpu.c      |   2 +
 target/riscv/cpu.h      |   4 +
 target/riscv/cpu_bits.h |  36 +++
 target/riscv/csr.c      | 554 +++++++++++++++++++++++++++++++++++++++-
 target/riscv/machine.c  |  22 +-
 5 files changed, 614 insertions(+), 4 deletions(-)

-- 
2.17.1