[PULL 00/21] target-arm queue
[PULL 00/35] target-arm queue
1
Mostly straightforward bugfixes. The new Xilinx devices are
1
The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
2
arguably 'new feature', but they're fixing a regression where
3
our changes to PSCI in commit 3f37979bf mean that EL3 guest
4
code now needs to talk to a proper emulated power-controller
5
device to turn on secondary CPUs; and it's not yet rc1 and
6
they only affect the Xilinx board, so it seems OK to me.
7
2
8
thanks
3
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
9
-- PMM
10
11
The following changes since commit 1d60bb4b14601e38ed17384277aa4c30c57925d3:
12
13
Merge tag 'pull-request-2022-03-15v2' of https://gitlab.com/thuth/qemu into staging (2022-03-16 10:43:58 +0000)
14
4
15
are available in the Git repository at:
5
are available in the Git repository at:
16
6
17
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220318
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
18
8
19
for you to fetch changes up to 79d54c9eac04c554e3c081589542f801ace71797:
9
for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
20
10
21
util/osdep: Remove some early cruft (2022-03-18 11:32:13 +0000)
11
docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
22
12
23
----------------------------------------------------------------
13
----------------------------------------------------------------
24
target-arm queue:
14
target-arm queue:
25
* Fix sve2 ldnt1 and stnt1
15
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
26
* Fix pauth_check_trap vs SEL2
16
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
27
* Fix handling of LPAE block descriptors
17
* Fix some errors in SVE/SME handling of MTE tags
28
* hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
18
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
29
* hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
19
* hw/block/tc58128: Don't emit deprecation warning under qtest
30
* nsis installer: List emulators in alphabetical order
20
* tests/qtest: Fix handling of npcm7xx and GMAC tests
31
* nsis installer: Suppress "ANSI targets are deprecated" warning
21
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
32
* nsis installer: Fix mouse-over descriptions for emulators
22
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
33
* hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
23
* Don't assert on vmload/vmsave of M-profile CPUs
34
* Improve M-profile vector table access logging
24
* hw/arm/smmuv3: add support for stage 1 access fault
35
* Xilinx ZynqMP: model CRF and APU control
25
* hw/arm/stellaris: QOM cleanups
36
* Fix compile issues on modern Solaris
26
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
27
* Improve Cortex_R52 IMPDEF sysreg modelling
28
* Allow access to SPSR_hyp from hyp mode
29
* New board model mps3-an536 (Cortex-R52)
37
30
38
----------------------------------------------------------------
31
----------------------------------------------------------------
39
Andrew Deason (3):
32
Luc Michel (1):
40
util/osdep: Avoid madvise proto on modern Solaris
33
hw/arm/smmuv3: add support for stage 1 access fault
41
hw/i386/acpi-build: Avoid 'sun' identifier
42
util/osdep: Remove some early cruft
43
34
44
Edgar E. Iglesias (6):
35
Nabih Estefan (1):
45
hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area
36
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
46
target/arm: Make rvbar settable after realize
47
hw/misc: Add a model of the Xilinx ZynqMP CRF
48
hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
49
hw/misc: Add a model of the Xilinx ZynqMP APU Control
50
hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
51
37
52
Eric Auger (2):
38
Peter Maydell (22):
53
hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG
39
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
54
hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
40
hw/block/tc58128: Don't emit deprecation warning under qtest
41
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
42
tests/qtest/bios-tables-test: Allow changes to virt GTDT
43
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
44
tests/qtest/bios-tables-tests: Update virt golden reference
45
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
46
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
47
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
48
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
49
target/arm: The Cortex-R52 has a read-only CBAR
50
target/arm: Add Cortex-R52 IMPDEF sysregs
51
target/arm: Allow access to SPSR_hyp from hyp mode
52
hw/misc/mps2-scc: Fix condition for CFG3 register
53
hw/misc/mps2-scc: Factor out which-board conditionals
54
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
55
hw/arm/mps3r: Initial skeleton for mps3-an536 board
56
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
57
hw/arm/mps3r: Add UARTs
58
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
59
hw/arm/mps3r: Add remaining devices
60
docs: Add documentation for the mps3-an536 board
55
61
56
Peter Maydell (8):
62
Philippe Mathieu-Daudé (5):
57
target/arm: Fix handling of LPAE block descriptors
63
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
58
hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
64
hw/arm/stellaris: Convert ADC controller to Resettable interface
59
hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
65
hw/arm/stellaris: Convert I2C controller to Resettable interface
60
nsis installer: List emulators in alphabetical order
66
hw/arm/stellaris: Add missing QOM 'machine' parent
61
nsis installer: Suppress "ANSI targets are deprecated" warning
67
hw/arm/stellaris: Add missing QOM 'SoC' parent
62
nsis installer: Fix mouse-over descriptions for emulators
63
target/arm: Log M-profile vector table accesses
64
target/arm: Log fault address for M-profile faults
65
68
66
Richard Henderson (2):
69
Richard Henderson (6):
67
target/arm: Fix sve2 ldnt1 and stnt1
70
linux-user/aarch64: Choose SYNC as the preferred MTE mode
68
target/arm: Fix pauth_check_trap vs SEL2
71
target/arm: Fix nregs computation in do_{ld,st}_zpa
72
target/arm: Adjust and validate mtedesc sizem1
73
target/arm: Split out make_svemte_desc
74
target/arm: Handle mte in do_ldrq, do_ldro
75
target/arm: Fix SVE/SME gross MTE suppression checks
69
76
70
meson.build | 23 ++-
77
MAINTAINERS | 3 +-
71
include/hw/arm/xlnx-zynqmp.h | 4 +
78
docs/system/arm/mps2.rst | 37 +-
72
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 ++++++++++++
79
configs/devices/arm-softmmu/default.mak | 1 +
73
include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++++
80
hw/arm/smmuv3-internal.h | 1 +
74
include/qemu/osdep.h | 8 +
81
include/hw/arm/smmu-common.h | 1 +
75
target/arm/cpu.h | 3 +-
82
include/hw/arm/virt.h | 2 +
76
target/arm/sve.decode | 5 +-
83
include/hw/misc/mps2-scc.h | 1 +
77
hw/arm/virt.c | 7 +-
84
linux-user/aarch64/target_prctl.h | 29 +-
78
hw/arm/xlnx-zynqmp.c | 46 +++++-
85
target/arm/internals.h | 2 +-
79
hw/dma/xlnx_csu_dma.c | 1 +
86
target/arm/tcg/translate-a64.h | 2 +
80
hw/i386/acpi-build.c | 4 +-
87
hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++
81
hw/misc/npcm7xx_clk.c | 4 +-
88
hw/arm/npcm7xx.c | 1 +
82
hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++++++++++
89
hw/arm/smmu-common.c | 11 +
83
hw/misc/xlnx-zynqmp-crf.c | 266 +++++++++++++++++++++++++++++++++
90
hw/arm/smmuv3.c | 1 +
84
target/arm/cpu.c | 17 ++-
91
hw/arm/stellaris.c | 47 ++-
85
target/arm/helper.c | 20 ++-
92
hw/arm/virt-acpi-build.c | 20 +-
86
target/arm/m_helper.c | 11 ++
93
hw/arm/virt.c | 60 ++-
87
target/arm/pauth_helper.c | 2 +-
94
hw/arm/xilinx_zynq.c | 2 +
88
target/arm/translate-sve.c | 51 ++++++-
95
hw/block/tc58128.c | 4 +-
89
tests/tcg/aarch64/test-826.c | 50 +++++++
96
hw/misc/mps2-scc.c | 138 ++++++-
90
util/osdep.c | 10 --
97
hw/pci-host/raven.c | 1 +
91
hw/intc/Kconfig | 2 +-
98
target/arm/helper.c | 14 +-
92
hw/intc/meson.build | 4 +-
99
target/arm/tcg/cpu32.c | 109 ++++++
93
hw/misc/meson.build | 2 +
100
target/arm/tcg/op_helper.c | 43 ++-
94
qemu.nsi | 8 +-
101
target/arm/tcg/sme_helper.c | 8 +-
95
scripts/nsis.py | 17 ++-
102
target/arm/tcg/sve_helper.c | 12 +-
96
tests/tcg/aarch64/Makefile.target | 4 +
103
target/arm/tcg/translate-sme.c | 15 +-
97
tests/tcg/configure.sh | 4 +
104
target/arm/tcg/translate-sve.c | 83 +++--
98
28 files changed, 1084 insertions(+), 46 deletions(-)
105
target/arm/tcg/translate.c | 19 +-
99
create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
106
tests/qtest/npcm7xx_emc-test.c | 5 +-
100
create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
107
tests/qtest/npcm_gmac-test.c | 84 +----
101
create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
108
hw/arm/Kconfig | 5 +
102
create mode 100644 hw/misc/xlnx-zynqmp-crf.c
109
hw/arm/meson.build | 1 +
103
create mode 100644 tests/tcg/aarch64/test-826.c
110
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
111
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
112
tests/qtest/meson.build | 4 +-
113
36 files changed, 1184 insertions(+), 222 deletions(-)
114
create mode 100644 hw/arm/mps3r.c
115
diff view generated by jsdifflib
[PULL 19/21] util/osdep: Avoid madvise proto on modern Solaris
[PULL 01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
1
From: Andrew Deason <adeason@sinenomine.net>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
On older Solaris releases (before Solaris 11), we didn't get a
3
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
4
prototype for madvise, and so util/osdep.c provides its own prototype.
4
connect FIQ output of the GIC CPU interfaces to the CPU.
5
Some time between the public Solaris 11.4 release and Solaris 11.4.42
6
CBE, we started getting an madvise prototype that looks like this:
7
5
8
extern int madvise(void *, size_t, int);
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
7
Message-id: 20240130152548.17855-1-philmd@linaro.org
10
which conflicts with the prototype in util/osdeps.c. Instead of always
11
declaring this prototype, check if we're missing the madvise()
12
prototype, and only declare it ourselves if the prototype is missing.
13
Move the prototype to include/qemu/osdep.h, the normal place to handle
14
platform-specific header quirks.
15
16
The 'missing_madvise_proto' meson check contains an obviously wrong
17
prototype for madvise. So if that code compiles and links, we must be
18
missing the actual prototype for madvise.
19
20
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
21
Message-id: 20220316035227.3702-2-adeason@sinenomine.net
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
10
---
25
meson.build | 23 +++++++++++++++++++++--
11
hw/arm/xilinx_zynq.c | 2 ++
26
include/qemu/osdep.h | 8 ++++++++
12
1 file changed, 2 insertions(+)
27
util/osdep.c | 3 ---
28
3 files changed, 29 insertions(+), 5 deletions(-)
29
13
30
diff --git a/meson.build b/meson.build
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
31
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
32
--- a/meson.build
16
--- a/hw/arm/xilinx_zynq.c
33
+++ b/meson.build
17
+++ b/hw/arm/xilinx_zynq.c
34
@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_FDATASYNC', cc.links(gnu_source_prefix + '''
18
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
35
#error Not supported
19
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
36
#endif
20
sysbus_connect_irq(busdev, 0,
37
}'''))
21
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
38
-config_host_data.set('CONFIG_MADVISE', cc.links(gnu_source_prefix + '''
22
+ sysbus_connect_irq(busdev, 1,
39
+
23
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
40
+has_madvise = cc.links(gnu_source_prefix + '''
24
41
#include <sys/types.h>
25
for (n = 0; n < 64; n++) {
42
#include <sys/mman.h>
26
pic[n] = qdev_get_gpio_in(dev, n);
43
#include <stddef.h>
44
- int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }'''))
45
+ int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }''')
46
+missing_madvise_proto = false
47
+if has_madvise
48
+ # Some platforms (illumos and Solaris before Solaris 11) provide madvise()
49
+ # but forget to prototype it. In this case, has_madvise will be true (the
50
+ # test program links despite a compile warning). To detect the
51
+ # missing-prototype case, we try again with a definitely-bogus prototype.
52
+ # This will only compile if the system headers don't provide the prototype;
53
+ # otherwise the conflicting prototypes will cause a compiler error.
54
+ missing_madvise_proto = cc.links(gnu_source_prefix + '''
55
+ #include <sys/types.h>
56
+ #include <sys/mman.h>
57
+ #include <stddef.h>
58
+ extern int madvise(int);
59
+ int main(void) { return madvise(0); }''')
60
+endif
61
+config_host_data.set('CONFIG_MADVISE', has_madvise)
62
+config_host_data.set('HAVE_MADVISE_WITHOUT_PROTOTYPE', missing_madvise_proto)
63
+
64
config_host_data.set('CONFIG_MEMFD', cc.links(gnu_source_prefix + '''
65
#include <sys/mman.h>
66
int main(void) { return memfd_create("foo", MFD_ALLOW_SEALING); }'''))
67
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
68
index XXXXXXX..XXXXXXX 100644
69
--- a/include/qemu/osdep.h
70
+++ b/include/qemu/osdep.h
71
@@ -XXX,XX +XXX,XX @@ void qemu_anon_ram_free(void *ptr, size_t size);
72
#define SIGIO SIGPOLL
73
#endif
74
75
+#ifdef HAVE_MADVISE_WITHOUT_PROTOTYPE
76
+/*
77
+ * See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for discussion
78
+ * about Solaris missing the madvise() prototype.
79
+ */
80
+extern int madvise(char *, size_t, int);
81
+#endif
82
+
83
#if defined(CONFIG_LINUX)
84
#ifndef BUS_MCEERR_AR
85
#define BUS_MCEERR_AR 4
86
diff --git a/util/osdep.c b/util/osdep.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/util/osdep.c
89
+++ b/util/osdep.c
90
@@ -XXX,XX +XXX,XX @@
91
92
#ifdef CONFIG_SOLARIS
93
#include <sys/statvfs.h>
94
-/* See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for
95
- discussion about Solaris header problems */
96
-extern int madvise(char *, size_t, int);
97
#endif
98
99
#include "qemu-common.h"
100
--
27
--
101
2.25.1
28
2.34.1
29
30
diff view generated by jsdifflib
New patch
[PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The API does not generate an error for setting ASYNC | SYNC; that merely
4
constrains the selection vs the per-cpu default. For qemu linux-user,
5
choose SYNC as the default.
6
7
Cc: qemu-stable@nongnu.org
8
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
11
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
15
1 file changed, 17 insertions(+), 12 deletions(-)
16
17
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/linux-user/aarch64/target_prctl.h
20
+++ b/linux-user/aarch64/target_prctl.h
21
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
22
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
23
24
if (cpu_isar_feature(aa64_mte, cpu)) {
25
- switch (arg2 & PR_MTE_TCF_MASK) {
26
- case PR_MTE_TCF_NONE:
27
- case PR_MTE_TCF_SYNC:
28
- case PR_MTE_TCF_ASYNC:
29
- break;
30
- default:
31
- return -EINVAL;
32
- }
33
-
34
/*
35
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
36
- * Note that the syscall values are consistent with hw.
37
+ *
38
+ * The kernel has a per-cpu configuration for the sysadmin,
39
+ * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
40
+ * which qemu does not implement.
41
+ *
42
+ * Because there is no performance difference between the modes, and
43
+ * because SYNC is most useful for debugging MTE errors, choose SYNC
44
+ * as the preferred mode. With this preference, and the way the API
45
+ * uses only two bits, there is no way for the program to select
46
+ * ASYMM mode.
47
*/
48
- env->cp15.sctlr_el[1] =
49
- deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
50
+ unsigned tcf = 0;
51
+ if (arg2 & PR_MTE_TCF_SYNC) {
52
+ tcf = 1;
53
+ } else if (arg2 & PR_MTE_TCF_ASYNC) {
54
+ tcf = 2;
55
+ }
56
+ env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
57
58
/*
59
* Write PR_MTE_TAG to GCR_EL1[Exclude].
60
--
61
2.34.1
diff view generated by jsdifflib
[PULL 01/21] target/arm: Fix sve2 ldnt1 and stnt1
[PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
For both ldnt1 and stnt1, the meaning of the Rn and Rm are different
3
The field is encoded as [0-3], which is convenient for
4
from ld1 and st1: the vector and integer registers are reversed, and
4
indexing our array of function pointers, but the true
5
the integer register 31 refers to XZR instead of SP.
5
value is [1-4]. Adjust before calling do_mem_zpa.
6
6
7
Secondly, the 64-bit version of ldnt1 was being interpreted as
7
Add an assert, and move the comment re passing ZT to
8
32-bit unpacked unscaled offset instead of 64-bit unscaled offset,
8
the helper back next to the relevant code.
9
which discarded the upper 32 bits of the address coming from
10
the vector argument.
11
9
12
Thirdly, validate that the memory element size is in range for the
10
Cc: qemu-stable@nongnu.org
13
vector element size for ldnt1. For ld1, we do this via independent
11
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
14
decode patterns, but for ldnt1 we need to do it manually.
15
16
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/826
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
14
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: 20220308031655.240710-1-richard.henderson@linaro.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
17
---
22
target/arm/sve.decode | 5 ++-
18
target/arm/tcg/translate-sve.c | 16 ++++++++--------
23
target/arm/translate-sve.c | 51 +++++++++++++++++++++++++++++--
19
1 file changed, 8 insertions(+), 8 deletions(-)
24
tests/tcg/aarch64/test-826.c | 50 ++++++++++++++++++++++++++++++
25
tests/tcg/aarch64/Makefile.target | 4 +++
26
tests/tcg/configure.sh | 4 +++
27
5 files changed, 109 insertions(+), 5 deletions(-)
28
create mode 100644 tests/tcg/aarch64/test-826.c
29
20
30
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
21
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
31
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/sve.decode
23
--- a/target/arm/tcg/translate-sve.c
33
+++ b/target/arm/sve.decode
24
+++ b/target/arm/tcg/translate-sve.c
34
@@ -XXX,XX +XXX,XX @@ USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm
25
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
35
26
TCGv_ptr t_pg;
36
### SVE2 Memory Gather Load Group
27
int desc = 0;
37
28
38
-# SVE2 64-bit gather non-temporal load
29
- /*
39
-# (scalar plus unpacked 32-bit unscaled offsets)
30
- * For e.g. LD4, there are not enough arguments to pass all 4
40
+# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets)
31
- * registers as pointers, so encode the regno into the data field.
41
LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \
32
- * For consistency, do this even for LD1.
42
- &rprr_gather_load xs=0 esz=3 scale=0 ff=0
33
- */
43
+ &rprr_gather_load xs=2 esz=3 scale=0 ff=0
34
+ assert(mte_n >= 1 && mte_n <= 4);
44
35
if (s->mte_active[0]) {
45
# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
36
int msz = dtype_msz(dtype);
46
LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \
37
47
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
38
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
48
index XXXXXXX..XXXXXXX 100644
39
addr = clean_data_tbi(s, addr);
49
--- a/target/arm/translate-sve.c
50
+++ b/target/arm/translate-sve.c
51
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
52
53
static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a)
54
{
55
+ gen_helper_gvec_mem_scatter *fn = NULL;
56
+ bool be = s->be_data == MO_BE;
57
+ bool mte = s->mte_active[0];
58
+
59
+ if (a->esz < a->msz + !a->u) {
60
+ return false;
61
+ }
62
if (!dc_isar_feature(aa64_sve2, s)) {
63
return false;
64
}
40
}
65
- return trans_LD1_zprz(s, a);
41
66
+ if (!sve_access_check(s)) {
42
+ /*
67
+ return true;
43
+ * For e.g. LD4, there are not enough arguments to pass all 4
68
+ }
44
+ * registers as pointers, so encode the regno into the data field.
69
+
45
+ * For consistency, do this even for LD1.
70
+ switch (a->esz) {
46
+ */
71
+ case MO_32:
47
desc = simd_desc(vsz, vsz, zt | desc);
72
+ fn = gather_load_fn32[mte][be][0][0][a->u][a->msz];
48
t_pg = tcg_temp_new_ptr();
73
+ break;
49
74
+ case MO_64:
50
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
75
+ fn = gather_load_fn64[mte][be][0][2][a->u][a->msz];
51
* accessible via the instruction encoding.
76
+ break;
52
*/
77
+ }
53
assert(fn != NULL);
78
+ assert(fn != NULL);
54
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
79
+
55
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
80
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
81
+ cpu_reg(s, a->rm), a->msz, false, fn);
82
+ return true;
83
}
56
}
84
57
85
/* Indexed by [mte][be][xs][msz]. */
58
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
86
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
59
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
87
60
if (nreg == 0) {
88
static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
61
/* ST1 */
89
{
62
fn = fn_single[s->mte_active[0]][be][msz][esz];
90
+ gen_helper_gvec_mem_scatter *fn;
63
- nreg = 1;
91
+ bool be = s->be_data == MO_BE;
64
} else {
92
+ bool mte = s->mte_active[0];
65
/* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
93
+
66
assert(msz == esz);
94
+ if (a->esz < a->msz) {
67
fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
95
+ return false;
96
+ }
97
if (!dc_isar_feature(aa64_sve2, s)) {
98
return false;
99
}
68
}
100
- return trans_ST1_zprz(s, a);
69
assert(fn != NULL);
101
+ if (!sve_access_check(s)) {
70
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
102
+ return true;
71
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
103
+ }
104
+
105
+ switch (a->esz) {
106
+ case MO_32:
107
+ fn = scatter_store_fn32[mte][be][0][a->msz];
108
+ break;
109
+ case MO_64:
110
+ fn = scatter_store_fn64[mte][be][2][a->msz];
111
+ break;
112
+ default:
113
+ g_assert_not_reached();
114
+ }
115
+
116
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
117
+ cpu_reg(s, a->rm), a->msz, true, fn);
118
+ return true;
119
}
72
}
120
73
121
/*
74
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
122
diff --git a/tests/tcg/aarch64/test-826.c b/tests/tcg/aarch64/test-826.c
123
new file mode 100644
124
index XXXXXXX..XXXXXXX
125
--- /dev/null
126
+++ b/tests/tcg/aarch64/test-826.c
127
@@ -XXX,XX +XXX,XX @@
128
+#include <sys/mman.h>
129
+#include <unistd.h>
130
+#include <signal.h>
131
+#include <stdlib.h>
132
+#include <stdio.h>
133
+#include <assert.h>
134
+
135
+static void *expected;
136
+
137
+void sigsegv(int sig, siginfo_t *info, void *vuc)
138
+{
139
+ ucontext_t *uc = vuc;
140
+
141
+ assert(info->si_addr == expected);
142
+ uc->uc_mcontext.pc += 4;
143
+}
144
+
145
+int main()
146
+{
147
+ struct sigaction sa = {
148
+ .sa_sigaction = sigsegv,
149
+ .sa_flags = SA_SIGINFO
150
+ };
151
+
152
+ void *page;
153
+ long ofs;
154
+
155
+ if (sigaction(SIGSEGV, &sa, NULL) < 0) {
156
+ perror("sigaction");
157
+ return EXIT_FAILURE;
158
+ }
159
+
160
+ page = mmap(0, getpagesize(), PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0);
161
+ if (page == MAP_FAILED) {
162
+ perror("mmap");
163
+ return EXIT_FAILURE;
164
+ }
165
+
166
+ ofs = 0x124;
167
+ expected = page + ofs;
168
+
169
+ asm("ptrue p0.d, vl1\n\t"
170
+ "dup z0.d, %0\n\t"
171
+ "ldnt1h {z1.d}, p0/z, [z0.d, %1]\n\t"
172
+ "dup z1.d, %1\n\t"
173
+ "ldnt1h {z0.d}, p0/z, [z1.d, %0]"
174
+ : : "r"(page), "r"(ofs) : "v0", "v1");
175
+
176
+ return EXIT_SUCCESS;
177
+}
178
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
179
index XXXXXXX..XXXXXXX 100644
180
--- a/tests/tcg/aarch64/Makefile.target
181
+++ b/tests/tcg/aarch64/Makefile.target
182
@@ -XXX,XX +XXX,XX @@ run-gdbstub-sve-ioctls: sve-ioctls
183
184
EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls
185
endif
186
+endif
187
188
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE2),)
189
+AARCH64_TESTS += test-826
190
+test-826: CFLAGS+=-march=armv8.1-a+sve2
191
endif
192
193
TESTS += $(AARCH64_TESTS)
194
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
195
index XXXXXXX..XXXXXXX 100755
196
--- a/tests/tcg/configure.sh
197
+++ b/tests/tcg/configure.sh
198
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
199
-march=armv8.1-a+sve -o $TMPE $TMPC; then
200
echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
201
fi
202
+ if do_compiler "$target_compiler" $target_compiler_cflags \
203
+ -march=armv8.1-a+sve2 -o $TMPE $TMPC; then
204
+ echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
205
+ fi
206
if do_compiler "$target_compiler" $target_compiler_cflags \
207
-march=armv8.3-a -o $TMPE $TMPC; then
208
echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
209
--
75
--
210
2.25.1
76
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/35] target/arm: Adjust and validate mtedesc sizem1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
When we added SVE_MTEDESC_SHIFT, we effectively limited the
4
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
5
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
6
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
7
8
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/internals.h | 2 +-
16
target/arm/tcg/translate-sve.c | 7 ++++---
17
2 files changed, 5 insertions(+), 4 deletions(-)
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2)
24
FIELD(MTEDESC, TCMA, 6, 2)
25
FIELD(MTEDESC, WRITE, 8, 1)
26
FIELD(MTEDESC, ALIGN, 9, 3)
27
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
28
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */
29
30
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
31
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
32
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/translate-sve.c
35
+++ b/target/arm/tcg/translate-sve.c
36
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
37
{
38
unsigned vsz = vec_full_reg_size(s);
39
TCGv_ptr t_pg;
40
+ uint32_t sizem1;
41
int desc = 0;
42
43
assert(mte_n >= 1 && mte_n <= 4);
44
+ sizem1 = (mte_n << dtype_msz(dtype)) - 1;
45
+ assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
46
if (s->mte_active[0]) {
47
- int msz = dtype_msz(dtype);
48
-
49
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
50
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
51
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
52
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
53
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
54
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
55
desc <<= SVE_MTEDESC_SHIFT;
56
} else {
57
addr = clean_data_tbi(s, addr);
58
--
59
2.34.1
diff view generated by jsdifflib
New patch
[PULL 05/35] target/arm: Split out make_svemte_desc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Share code that creates mtedesc and embeds within simd_desc.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/tcg/translate-a64.h | 2 ++
13
target/arm/tcg/translate-sme.c | 15 +++--------
14
target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
15
3 files changed, 31 insertions(+), 33 deletions(-)
16
17
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/tcg/translate-a64.h
20
+++ b/target/arm/tcg/translate-a64.h
21
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
22
bool sve_access_check(DisasContext *s);
23
bool sme_enabled_check(DisasContext *s);
24
bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
25
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
26
+ uint32_t msz, bool is_write, uint32_t data);
27
28
/* This function corresponds to CheckStreamingSVEEnabled. */
29
static inline bool sme_sm_enabled_check(DisasContext *s)
30
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/tcg/translate-sme.c
33
+++ b/target/arm/tcg/translate-sme.c
34
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
35
36
TCGv_ptr t_za, t_pg;
37
TCGv_i64 addr;
38
- int svl, desc = 0;
39
+ uint32_t desc;
40
bool be = s->be_data == MO_BE;
41
bool mte = s->mte_active[0];
42
43
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
44
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
45
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
46
47
- if (mte) {
48
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
49
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
50
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
51
- desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
52
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
53
- desc <<= SVE_MTEDESC_SHIFT;
54
- } else {
55
+ if (!mte) {
56
addr = clean_data_tbi(s, addr);
57
}
58
- svl = streaming_vec_reg_size(s);
59
- desc = simd_desc(svl, svl, desc);
60
+
61
+ desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
62
63
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
64
tcg_constant_i32(desc));
65
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/tcg/translate-sve.c
68
+++ b/target/arm/tcg/translate-sve.c
69
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
70
3, 2, 1, 3
71
};
72
73
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
74
- int dtype, uint32_t mte_n, bool is_write,
75
- gen_helper_gvec_mem *fn)
76
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
77
+ uint32_t msz, bool is_write, uint32_t data)
78
{
79
- unsigned vsz = vec_full_reg_size(s);
80
- TCGv_ptr t_pg;
81
uint32_t sizem1;
82
- int desc = 0;
83
+ uint32_t desc = 0;
84
85
- assert(mte_n >= 1 && mte_n <= 4);
86
- sizem1 = (mte_n << dtype_msz(dtype)) - 1;
87
+ /* Assert all of the data fits, with or without MTE enabled. */
88
+ assert(nregs >= 1 && nregs <= 4);
89
+ sizem1 = (nregs << msz) - 1;
90
assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
91
+ assert(data < 1u << SVE_MTEDESC_SHIFT);
92
+
93
if (s->mte_active[0]) {
94
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
95
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
96
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
97
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
98
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
99
desc <<= SVE_MTEDESC_SHIFT;
100
- } else {
101
+ }
102
+ return simd_desc(vsz, vsz, desc | data);
103
+}
104
+
105
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
106
+ int dtype, uint32_t nregs, bool is_write,
107
+ gen_helper_gvec_mem *fn)
108
+{
109
+ TCGv_ptr t_pg;
110
+ uint32_t desc;
111
+
112
+ if (!s->mte_active[0]) {
113
addr = clean_data_tbi(s, addr);
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
117
* registers as pointers, so encode the regno into the data field.
118
* For consistency, do this even for LD1.
119
*/
120
- desc = simd_desc(vsz, vsz, zt | desc);
121
+ desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
122
+ dtype_msz(dtype), is_write, zt);
123
t_pg = tcg_temp_new_ptr();
124
125
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
126
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
127
int scale, TCGv_i64 scalar, int msz, bool is_write,
128
gen_helper_gvec_mem_scatter *fn)
129
{
130
- unsigned vsz = vec_full_reg_size(s);
131
TCGv_ptr t_zm = tcg_temp_new_ptr();
132
TCGv_ptr t_pg = tcg_temp_new_ptr();
133
TCGv_ptr t_zt = tcg_temp_new_ptr();
134
- int desc = 0;
135
-
136
- if (s->mte_active[0]) {
137
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
138
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
139
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
140
- desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
141
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
142
- desc <<= SVE_MTEDESC_SHIFT;
143
- }
144
- desc = simd_desc(vsz, vsz, desc | scale);
145
+ uint32_t desc;
146
147
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
148
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
149
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
150
+
151
+ desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
152
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
153
}
154
155
--
156
2.34.1
diff view generated by jsdifflib
New patch
[PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
These functions "use the standard load helpers", but
4
fail to clean_data_tbi or populate mtedesc.
5
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
10
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
14
1 file changed, 13 insertions(+), 2 deletions(-)
15
16
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/tcg/translate-sve.c
19
+++ b/target/arm/tcg/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
21
unsigned vsz = vec_full_reg_size(s);
22
TCGv_ptr t_pg;
23
int poff;
24
+ uint32_t desc;
25
26
/* Load the first quadword using the normal predicated load helpers. */
27
+ if (!s->mte_active[0]) {
28
+ addr = clean_data_tbi(s, addr);
29
+ }
30
+
31
poff = pred_full_reg_offset(s, pg);
32
if (vsz > 16) {
33
/*
34
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
35
36
gen_helper_gvec_mem *fn
37
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
38
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
39
+ desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
40
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
41
42
/* Replicate that first quadword. */
43
if (vsz > 16) {
44
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
45
unsigned vsz_r32;
46
TCGv_ptr t_pg;
47
int poff, doff;
48
+ uint32_t desc;
49
50
if (vsz < 32) {
51
/*
52
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
53
}
54
55
/* Load the first octaword using the normal predicated load helpers. */
56
+ if (!s->mte_active[0]) {
57
+ addr = clean_data_tbi(s, addr);
58
+ }
59
60
poff = pred_full_reg_offset(s, pg);
61
if (vsz > 32) {
62
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
63
64
gen_helper_gvec_mem *fn
65
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
66
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
67
+ desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
68
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
69
70
/*
71
* Replicate that first octaword.
72
--
73
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/35] target/arm: Fix SVE/SME gross MTE suppression checks
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The TBI and TCMA bits are located within mtedesc, not desc.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/tcg/sme_helper.c | 8 ++++----
13
target/arm/tcg/sve_helper.c | 12 ++++++------
14
2 files changed, 10 insertions(+), 10 deletions(-)
15
16
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/tcg/sme_helper.c
19
+++ b/target/arm/tcg/sme_helper.c
20
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
21
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
22
23
/* Perform gross MTE suppression early. */
24
- if (!tbi_check(desc, bit55) ||
25
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
26
+ if (!tbi_check(mtedesc, bit55) ||
27
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
28
mtedesc = 0;
29
}
30
31
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
32
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
33
34
/* Perform gross MTE suppression early. */
35
- if (!tbi_check(desc, bit55) ||
36
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
37
+ if (!tbi_check(mtedesc, bit55) ||
38
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
39
mtedesc = 0;
40
}
41
42
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/tcg/sve_helper.c
45
+++ b/target/arm/tcg/sve_helper.c
46
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
47
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
48
49
/* Perform gross MTE suppression early. */
50
- if (!tbi_check(desc, bit55) ||
51
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
52
+ if (!tbi_check(mtedesc, bit55) ||
53
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
54
mtedesc = 0;
55
}
56
57
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
58
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
59
60
/* Perform gross MTE suppression early. */
61
- if (!tbi_check(desc, bit55) ||
62
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
63
+ if (!tbi_check(mtedesc, bit55) ||
64
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
65
mtedesc = 0;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
69
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
70
71
/* Perform gross MTE suppression early. */
72
- if (!tbi_check(desc, bit55) ||
73
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
74
+ if (!tbi_check(mtedesc, bit55) ||
75
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
76
mtedesc = 0;
77
}
78
79
--
80
2.34.1
diff view generated by jsdifflib
[PULL 04/21] hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
[PULL 08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
1
In commit 00f05c02f9e7342f we gave the TYPE_XLNX_CSU_DMA object its
1
The raven_io_ops MemoryRegionOps is the only one in the source tree
2
own class struct, but forgot to update the TypeInfo::class_size
2
which sets .valid.unaligned to indicate that it should support
3
accordingly. This meant that not enough memory was allocated for the
3
unaligned accesses and which does not also set .impl.unaligned to
4
class struct, and the initialization of xcdc->read in the class init
4
indicate that its read and write functions can do the unaligned
5
function wrote off the end of the memory. Add the missing line.
5
handling themselves. This is a problem, because at the moment the
6
core memory system does not implement the support for handling
7
unaligned accesses by doing a series of aligned accesses and
8
combining them (system/memory.c:access_with_adjusted_size() has a
9
TODO comment noting this).
6
10
7
Found by running 'check-qtest-aarch64' with a clang
11
Fortunately raven_io_read() and raven_io_write() will correctly deal
8
address-sanitizer build, which complains:
12
with the case of being passed an unaligned address, so we can fix the
13
missing unaligned access support by setting .impl.unaligned in the
14
MemoryRegionOps struct.
9
15
10
==2542634==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61000000ab00 at pc 0x559a20aebc29 bp 0x7fff97df74d0 sp 0x7fff97df74c8
16
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
11
WRITE of size 8 at 0x61000000ab00 thread T0
12
#0 0x559a20aebc28 in xlnx_csu_dma_class_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../hw/dma/xlnx_csu_dma.c:722:16
13
#1 0x559a21bf297c in type_initialize /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:365:9
14
#2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5
15
#3 0x7f09bcb641b7 in g_hash_table_foreach (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x401b7)
16
#4 0x559a21bf3c27 in object_class_foreach /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1092:5
17
#5 0x559a21bf3c27 in object_class_get_list /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1149:5
18
#6 0x559a2081a2fd in select_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:1661:24
19
#7 0x559a2081a2fd in qemu_create_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:2146:35
20
#8 0x559a2081a2fd in qemu_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:3706:5
21
#9 0x559a20720ed5 in main /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/main.c:49:5
22
#10 0x7f09baec00b2 in __libc_start_main /build/glibc-sMfBJT/glibc-2.31/csu/../csu/libc-start.c:308:16
23
#11 0x559a2067673d in _start (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xf4b73d)
24
25
0x61000000ab00 is located 0 bytes to the right of 192-byte region [0x61000000aa40,0x61000000ab00)
26
allocated by thread T0 here:
27
#0 0x559a206eeff2 in calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xfc3ff2)
28
#1 0x7f09bcb7bef0 in g_malloc0 (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57ef0)
29
#2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5
30
31
Fixes: 00f05c02f9e7342f ("hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method")
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
18
Tested-by: Cédric Le Goater <clg@redhat.com>
34
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
19
Reviewed-by: Cédric Le Goater <clg@redhat.com>
35
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
36
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
37
Message-id: 20220308150207.2546272-1-peter.maydell@linaro.org
38
---
21
---
39
hw/dma/xlnx_csu_dma.c | 1 +
22
hw/pci-host/raven.c | 1 +
40
1 file changed, 1 insertion(+)
23
1 file changed, 1 insertion(+)
41
24
42
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
25
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
43
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/dma/xlnx_csu_dma.c
27
--- a/hw/pci-host/raven.c
45
+++ b/hw/dma/xlnx_csu_dma.c
28
+++ b/hw/pci-host/raven.c
46
@@ -XXX,XX +XXX,XX @@ static const TypeInfo xlnx_csu_dma_info = {
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
47
.parent = TYPE_SYS_BUS_DEVICE,
30
.write = raven_io_write,
48
.instance_size = sizeof(XlnxCSUDMA),
31
.endianness = DEVICE_LITTLE_ENDIAN,
49
.class_init = xlnx_csu_dma_class_init,
32
.impl.max_access_size = 4,
50
+ .class_size = sizeof(XlnxCSUDMAClass),
33
+ .impl.unaligned = true,
51
.instance_init = xlnx_csu_dma_init,
34
.valid.unaligned = true,
52
.interfaces = (InterfaceInfo[]) {
35
};
53
{ TYPE_STREAM_SINK },
36
54
--
37
--
55
2.25.1
38
2.34.1
56
39
57
40
diff view generated by jsdifflib
[PULL 12/21] target/arm: Log fault address for M-profile faults
[PULL 09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
1
For M-profile, the fault address is not always exposed to the guest
1
Suppress the deprecation warning when we're running under qtest,
2
in a fault register (for instance the BFAR bus fault address register
2
to avoid "make check" including warning messages in its output.
3
is only updated for bus faults on data accesses, not instruction
4
accesses). Currently we log the address only if we're putting it
5
into a particular guest-visible register. Since we always have it,
6
log it generically, to make logs of i-side faults a bit clearer.
7
3
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20220315204306.2797684-3-peter.maydell@linaro.org
13
---
7
---
14
target/arm/m_helper.c | 6 ++++++
8
hw/block/tc58128.c | 4 +++-
15
1 file changed, 6 insertions(+)
9
1 file changed, 3 insertions(+), 1 deletion(-)
16
10
17
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
11
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
18
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/m_helper.c
13
--- a/hw/block/tc58128.c
20
+++ b/target/arm/m_helper.c
14
+++ b/hw/block/tc58128.c
21
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
15
@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
22
* Note that for M profile we don't have a guest facing FSR, but
16
23
* the env->exception.fsr will be populated by the code that
17
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
24
* raises the fault, in the A profile short-descriptor format.
18
{
25
+ *
19
- warn_report_once("The TC58128 flash device is deprecated");
26
+ * Log the exception.vaddress now regardless of subtype, because
20
+ if (!qtest_enabled()) {
27
+ * logging below only logs it when it goes into a guest visible
21
+ warn_report_once("The TC58128 flash device is deprecated");
28
+ * register.
22
+ }
29
*/
23
init_dev(&tc58128_devs[0], zone1);
30
+ qemu_log_mask(CPU_LOG_INT, "...at fault address 0x%x\n",
24
init_dev(&tc58128_devs[1], zone2);
31
+ (uint32_t)env->exception.vaddress);
25
return sh7750_register_io_device(s, &tc58128);
32
switch (env->exception.fsr & 0xf) {
33
case M_FAKE_FSR_NSC_EXEC:
34
/*
35
--
26
--
36
2.25.1
27
2.34.1
37
28
38
29
diff view generated by jsdifflib
New patch
[PULL 10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
1
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
2
because we already get the coverage of those tests via qtests_arm,
3
and we don't want to use extra CI minutes testing them twice.
1
4
5
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
6
that change.
7
8
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
12
---
13
tests/qtest/meson.build | 1 -
14
1 file changed, 1 deletion(-)
15
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
17
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/qtest/meson.build
19
+++ b/tests/qtest/meson.build
20
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
21
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
22
(config_all_accel.has_key('CONFIG_TCG') and \
23
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
24
- (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
25
['arm-cpu-features',
26
'numa-test',
27
'boot-serial-test',
28
--
29
2.34.1
30
31
diff view generated by jsdifflib
New patch
[PULL 11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
1
Allow changes to the virt GTDT -- we are going to add the IRQ
2
entry for a new timer to it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
6
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
7
---
8
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/bios-tables-test-allowed-diff.h
14
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
15
@@ -1 +1,3 @@
16
/* List of comma-separated changed AML files to ignore */
17
+"tests/data/acpi/virt/FACP",
18
+"tests/data/acpi/virt/GTDT",
19
--
20
2.34.1
diff view generated by jsdifflib
[PULL 10/21] hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
[PULL 12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
1
From: Eric Auger <eric.auger@redhat.com>
1
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
2
2
non-secure EL2 virtual timer. We implemented the timer itself in the
3
In TCG mode, if gic-version=max we always select GICv3 even if
3
CPU model, but never wired up its IRQ line to the GIC.
4
CONFIG_ARM_GICV3_TCG is unset. We shall rather select GICv2.
4
5
This also brings the benefit of fixing qos tests errors for tests
5
Wire up the IRQ line (this is always safe whether the CPU has the
6
using gic-version=max with CONFIG_ARM_GICV3_TCG unset.
6
interrupt or not, since it always creates the outbound IRQ line).
7
7
Report it to the guest via dtb and ACPI if the CPU has the feature.
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
9
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
The DTB binding is documented in the kernel's
10
Message-id: 20220308182452.223473-3-eric.auger@redhat.com
10
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
and the ACPI table entries are documented in the ACPI specification
12
version 6.3 or later.
13
14
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
15
FADT table rev to show that we might be using 6.3 features.
16
17
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
18
versions prior to edk2-stable202311, for users who use the virt board
19
with 'virtualization=on' to enable EL2 emulation and are booting an
20
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
21
that EDK2 will assert on bootup:
22
23
ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
24
25
If you see that assertion you should do one of:
26
* update your EDK2 binaries to edk2-stable202311 or newer
27
* use the 'virt-8.2' versioned machine type
28
* not use 'virtualization=on'
29
30
(The versions shipped with QEMU itself have the fix.)
31
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
34
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
13
---
35
---
14
hw/arm/virt.c | 7 ++++++-
36
include/hw/arm/virt.h | 2 ++
15
1 file changed, 6 insertions(+), 1 deletion(-)
37
hw/arm/virt-acpi-build.c | 20 ++++++++++----
16
38
hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------
39
3 files changed, 67 insertions(+), 15 deletions(-)
40
41
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/virt.h
44
+++ b/include/hw/arm/virt.h
45
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
46
/* Machines < 6.2 have no support for describing cpu topology to guest */
47
bool no_cpu_topology;
48
bool no_tcg_lpa2;
49
+ bool no_ns_el2_virt_timer_irq;
50
};
51
52
struct VirtMachineState {
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
54
PCIBus *bus;
55
char *oem_id;
56
char *oem_table_id;
57
+ bool ns_el2_virt_timer_irq;
58
};
59
60
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
61
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/virt-acpi-build.c
64
+++ b/hw/arm/virt-acpi-build.c
65
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
}
67
68
/*
69
- * ACPI spec, Revision 5.1
70
- * 5.2.24 Generic Timer Description Table (GTDT)
71
+ * ACPI spec, Revision 6.5
72
+ * 5.2.25 Generic Timer Description Table (GTDT)
73
*/
74
static void
75
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
76
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
77
uint32_t irqflags = vmc->claim_edge_triggered_timers ?
78
1 : /* Interrupt is Edge triggered */
79
0; /* Interrupt is Level triggered */
80
- AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
81
+ AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
82
.oem_table_id = vms->oem_table_id };
83
84
acpi_table_begin(&table, table_data);
85
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
86
build_append_int_noprefix(table_data, 0, 4);
87
/* Platform Timer Offset */
88
build_append_int_noprefix(table_data, 0, 4);
89
-
90
+ if (vms->ns_el2_virt_timer_irq) {
91
+ /* Virtual EL2 Timer GSIV */
92
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
93
+ /* Virtual EL2 Timer Flags */
94
+ build_append_int_noprefix(table_data, irqflags, 4);
95
+ } else {
96
+ build_append_int_noprefix(table_data, 0, 4);
97
+ build_append_int_noprefix(table_data, 0, 4);
98
+ }
99
acpi_table_end(linker, &table);
100
}
101
102
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
103
static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
104
VirtMachineState *vms, unsigned dsdt_tbl_offset)
105
{
106
- /* ACPI v6.0 */
107
+ /* ACPI v6.3 */
108
AcpiFadtData fadt = {
109
.rev = 6,
110
- .minor_ver = 0,
111
+ .minor_ver = 3,
112
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
113
.xdsdt_tbl_offset = &dsdt_tbl_offset,
114
};
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
115
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
116
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
117
--- a/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
118
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
119
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
22
vms->gic_version = VIRT_GIC_VERSION_2;
120
qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
23
break;
121
}
24
case VIRT_GIC_VERSION_MAX:
122
25
- vms->gic_version = VIRT_GIC_VERSION_3;
123
+/*
26
+ if (module_object_class_by_name("arm-gicv3")) {
124
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
27
+ /* CONFIG_ARM_GICV3_TCG was set */
125
+ * but we don't want to advertise it to the guest in the dtb or ACPI
28
+ vms->gic_version = VIRT_GIC_VERSION_3;
126
+ * table unless it's really going to do something.
29
+ } else {
127
+ */
30
+ vms->gic_version = VIRT_GIC_VERSION_2;
128
+static bool ns_el2_virt_timer_present(void)
31
+ }
129
+{
32
break;
130
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
33
case VIRT_GIC_VERSION_HOST:
131
+ CPUARMState *env = &cpu->env;
34
error_report("gic-version=host requires KVM");
132
+
133
+ return arm_feature(env, ARM_FEATURE_AARCH64) &&
134
+ arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
135
+}
136
+
137
static void create_fdt(VirtMachineState *vms)
138
{
139
MachineState *ms = MACHINE(vms);
140
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
141
"arm,armv7-timer");
142
}
143
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
144
- qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
145
- GIC_FDT_IRQ_TYPE_PPI,
146
- INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
147
- GIC_FDT_IRQ_TYPE_PPI,
148
- INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
149
- GIC_FDT_IRQ_TYPE_PPI,
150
- INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
151
- GIC_FDT_IRQ_TYPE_PPI,
152
- INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
153
+ if (vms->ns_el2_virt_timer_irq) {
154
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
155
+ GIC_FDT_IRQ_TYPE_PPI,
156
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
157
+ GIC_FDT_IRQ_TYPE_PPI,
158
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
159
+ GIC_FDT_IRQ_TYPE_PPI,
160
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
161
+ GIC_FDT_IRQ_TYPE_PPI,
162
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
163
+ GIC_FDT_IRQ_TYPE_PPI,
164
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
165
+ } else {
166
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
167
+ GIC_FDT_IRQ_TYPE_PPI,
168
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
169
+ GIC_FDT_IRQ_TYPE_PPI,
170
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
171
+ GIC_FDT_IRQ_TYPE_PPI,
172
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
173
+ GIC_FDT_IRQ_TYPE_PPI,
174
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
175
+ }
176
}
177
178
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
179
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
180
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
181
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
182
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
183
+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
184
};
185
186
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
187
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
188
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
189
object_unref(cpuobj);
190
}
191
+
192
+ /* Now we've created the CPUs we can see if they have the hypvirt timer */
193
+ vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
194
+ !vmc->no_ns_el2_virt_timer_irq;
195
+
196
fdt_add_timer_nodes(vms);
197
fdt_add_cpu_nodes(vms);
198
199
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
200
201
static void virt_machine_8_2_options(MachineClass *mc)
202
{
203
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
204
+
205
virt_machine_9_0_options(mc);
206
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
207
+ /*
208
+ * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
209
+ * earlier machines. (Exposing it tickles a bug in older EDK2
210
+ * guest BIOS binaries.)
211
+ */
212
+ vmc->no_ns_el2_virt_timer_irq = true;
213
}
214
DEFINE_VIRT_MACHINE(8, 2)
215
35
--
216
--
36
2.25.1
217
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/35] tests/qtest/bios-tables-tests: Update virt golden reference
1
1
Update the virt golden reference files to say that the FACP is ACPI
2
v6.3, and the GTDT table is a revision 3 table with space for the
3
virtual EL2 timer.
4
5
Diffs from iasl:
6
7
@@ -XXX,XX +XXX,XX @@
8
/*
9
* Intel ACPI Component Architecture
10
* AML/ASL+ Disassembler version 20200925 (64-bit version)
11
* Copyright (c) 2000 - 2020 Intel Corporation
12
*
13
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
14
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
15
*
16
* ACPI Data Table [FACP]
17
*
18
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
19
*/
20
21
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
22
[004h 0004 4] Table Length : 00000114
23
[008h 0008 1] Revision : 06
24
-[009h 0009 1] Checksum : 15
25
+[009h 0009 1] Checksum : 12
26
[00Ah 0010 6] Oem ID : "BOCHS "
27
[010h 0016 8] Oem Table ID : "BXPC "
28
[018h 0024 4] Oem Revision : 00000001
29
[01Ch 0028 4] Asl Compiler ID : "BXPC"
30
[020h 0032 4] Asl Compiler Revision : 00000001
31
32
[024h 0036 4] FACS Address : 00000000
33
[028h 0040 4] DSDT Address : 00000000
34
[02Ch 0044 1] Model : 00
35
[02Dh 0045 1] PM Profile : 00 [Unspecified]
36
[02Eh 0046 2] SCI Interrupt : 0000
37
[030h 0048 4] SMI Command Port : 00000000
38
[034h 0052 1] ACPI Enable Value : 00
39
[035h 0053 1] ACPI Disable Value : 00
40
[036h 0054 1] S4BIOS Command : 00
41
[037h 0055 1] P-State Control : 00
42
@@ -XXX,XX +XXX,XX @@
43
Use APIC Physical Destination Mode (V4) : 0
44
Hardware Reduced (V5) : 1
45
Low Power S0 Idle (V5) : 0
46
47
[074h 0116 12] Reset Register : [Generic Address Structure]
48
[074h 0116 1] Space ID : 00 [SystemMemory]
49
[075h 0117 1] Bit Width : 00
50
[076h 0118 1] Bit Offset : 00
51
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
52
[078h 0120 8] Address : 0000000000000000
53
54
[080h 0128 1] Value to cause reset : 00
55
[081h 0129 2] ARM Flags (decoded below) : 0003
56
PSCI Compliant : 1
57
Must use HVC for PSCI : 1
58
59
-[083h 0131 1] FADT Minor Revision : 00
60
+[083h 0131 1] FADT Minor Revision : 03
61
[084h 0132 8] FACS Address : 0000000000000000
62
[08Ch 0140 8] DSDT Address : 0000000000000000
63
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
64
[094h 0148 1] Space ID : 00 [SystemMemory]
65
[095h 0149 1] Bit Width : 00
66
[096h 0150 1] Bit Offset : 00
67
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
68
[098h 0152 8] Address : 0000000000000000
69
70
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
71
[0A0h 0160 1] Space ID : 00 [SystemMemory]
72
[0A1h 0161 1] Bit Width : 00
73
[0A2h 0162 1] Bit Offset : 00
74
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
75
[0A4h 0164 8] Address : 0000000000000000
76
77
@@ -XXX,XX +XXX,XX @@
78
[0F5h 0245 1] Bit Width : 00
79
[0F6h 0246 1] Bit Offset : 00
80
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
81
[0F8h 0248 8] Address : 0000000000000000
82
83
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
84
[100h 0256 1] Space ID : 00 [SystemMemory]
85
[101h 0257 1] Bit Width : 00
86
[102h 0258 1] Bit Offset : 00
87
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
88
[104h 0260 8] Address : 0000000000000000
89
90
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
91
92
Raw Table Data: Length 276 (0x114)
93
94
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
95
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
96
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
97
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
98
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
99
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
100
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
101
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
102
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
103
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
104
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
105
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
106
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
107
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
108
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
109
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
110
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
111
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
112
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
113
0110: 00 00 00 00 // ....
114
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
* Intel ACPI Component Architecture
118
* AML/ASL+ Disassembler version 20200925 (64-bit version)
119
* Copyright (c) 2000 - 2020 Intel Corporation
120
*
121
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
122
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
123
*
124
* ACPI Data Table [GTDT]
125
*
126
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
127
*/
128
129
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
130
-[004h 0004 4] Table Length : 00000060
131
-[008h 0008 1] Revision : 02
132
-[009h 0009 1] Checksum : 9C
133
+[004h 0004 4] Table Length : 00000068
134
+[008h 0008 1] Revision : 03
135
+[009h 0009 1] Checksum : 93
136
[00Ah 0010 6] Oem ID : "BOCHS "
137
[010h 0016 8] Oem Table ID : "BXPC "
138
[018h 0024 4] Oem Revision : 00000001
139
[01Ch 0028 4] Asl Compiler ID : "BXPC"
140
[020h 0032 4] Asl Compiler Revision : 00000001
141
142
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
143
[02Ch 0044 4] Reserved : 00000000
144
145
[030h 0048 4] Secure EL1 Interrupt : 0000001D
146
[034h 0052 4] EL1 Flags (decoded below) : 00000000
147
Trigger Mode : 0
148
Polarity : 0
149
Always On : 0
150
151
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
152
@@ -XXX,XX +XXX,XX @@
153
154
[040h 0064 4] Virtual Timer Interrupt : 0000001B
155
[044h 0068 4] VT Flags (decoded below) : 00000000
156
Trigger Mode : 0
157
Polarity : 0
158
Always On : 0
159
160
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
161
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
162
Trigger Mode : 0
163
Polarity : 0
164
Always On : 0
165
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
166
167
[058h 0088 4] Platform Timer Count : 00000000
168
[05Ch 0092 4] Platform Timer Offset : 00000000
169
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
170
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
171
172
-Raw Table Data: Length 96 (0x60)
173
+Raw Table Data: Length 104 (0x68)
174
175
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
176
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
177
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
178
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
179
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
180
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
181
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
182
+ 0060: 00 00 00 00 00 00 00 00 // ........
183
184
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
186
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
187
---
188
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
189
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
190
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
191
3 files changed, 2 deletions(-)
192
193
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/qtest/bios-tables-test-allowed-diff.h
196
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
197
@@ -1,3 +1 @@
198
/* List of comma-separated changed AML files to ignore */
199
-"tests/data/acpi/virt/FACP",
200
-"tests/data/acpi/virt/GTDT",
201
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
202
index XXXXXXX..XXXXXXX 100644
203
GIT binary patch
204
delta 25
205
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
206
207
delta 28
208
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
209
210
diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
211
index XXXXXXX..XXXXXXX 100644
212
GIT binary patch
213
delta 25
214
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
215
216
delta 16
217
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
218
219
--
220
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
1
The patchset adding the GMAC ethernet to this SoC crossed in the
2
mail with the patchset cleaning up the NIC handling. When we
3
create the GMAC modules we must call qemu_configure_nic_device()
4
so that the user has the opportunity to use the -nic commandline
5
option to create a network backend and connect it to the GMACs.
1
6
7
Add the missing call.
8
9
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
12
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
13
---
14
hw/arm/npcm7xx.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/npcm7xx.c
20
+++ b/hw/arm/npcm7xx.c
21
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
22
for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
23
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
24
25
+ qemu_configure_nic_device(DEVICE(sbd), false, NULL);
26
/*
27
* The device exists regardless of whether it's connected to a QEMU
28
* netdev backend. So always instantiate it even if there is no
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
1
Currently QEMU will warn if there is a NIC on the board that
2
is not connected to a backend. By default the '-nic user' will
3
get used for all NICs, but if you manually connect a specific
4
NIC to a specific backend, then the other NICs on the board
5
have no backend and will be warned about:
1
6
7
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
8
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
9
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
10
11
So suppress those warnings by manually connecting every NIC
12
on the board to some backend.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
18
---
19
tests/qtest/npcm7xx_emc-test.c | 5 ++++-
20
1 file changed, 4 insertions(+), 1 deletion(-)
21
22
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/tests/qtest/npcm7xx_emc-test.c
25
+++ b/tests/qtest/npcm7xx_emc-test.c
26
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
27
* KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
28
* in the 'model' field to specify the device to match.
29
*/
30
- g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
31
+ g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
32
+ "-nic user,model=npcm7xx-emc "
33
+ "-nic user,model=npcm-gmac "
34
+ "-nic user,model=npcm-gmac",
35
test_sockets[1], module_num);
36
37
g_test_queue_destroy(packet_test_clear, test_sockets);
38
--
39
2.34.1
diff view generated by jsdifflib
[PULL 14/21] target/arm: Make rvbar settable after realize
[PULL 16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
2
CPU, and in fact if you try to do it we will assert:
2
3
3
Make the rvbar property settable after realize. This is done
4
#6 0x00007ffff4b95e96 in __GI___assert_fail
4
in preparation to model the ZynqMP's runtime configurable rvbar.
5
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
6
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
7
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
8
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
5
9
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
We might call pmu_counter_enabled() on an M-profile CPU (for example
7
Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com
11
from the migration pre/post hooks in machine.c); this should always
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
return false because these CPUs don't set ARM_FEATURE_PMU.
13
14
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
15
have done the early return for "PMU not present".
16
17
This fixes an assertion failure if you try to do a loadvm or
18
savevm for an M-profile board.
19
20
Cc: qemu-stable@nongnu.org
21
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
10
---
26
---
11
target/arm/cpu.h | 3 ++-
27
target/arm/helper.c | 12 ++++++++++--
12
target/arm/cpu.c | 12 +++++++-----
28
1 file changed, 10 insertions(+), 2 deletions(-)
13
target/arm/helper.c | 10 +++++++---
14
3 files changed, 16 insertions(+), 9 deletions(-)
15
29
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
21
uint64_t vbar_el[4];
22
};
23
uint32_t mvbar; /* (monitor) vector base address register */
24
+ uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
25
struct { /* FCSE PID. */
26
uint32_t fcseidr_ns;
27
uint32_t fcseidr_s;
28
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
29
30
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
31
uint32_t dcz_blocksize;
32
- uint64_t rvbar;
33
+ uint64_t rvbar_prop; /* Property/input signals. */
34
35
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
36
int gic_num_lrs; /* number of list registers */
37
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu.c
40
+++ b/target/arm/cpu.c
41
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
42
} else {
43
env->pstate = PSTATE_MODE_EL1h;
44
}
45
- env->pc = cpu->rvbar;
46
+
47
+ /* Sample rvbar at reset. */
48
+ env->cp15.rvbar = cpu->rvbar_prop;
49
+ env->pc = env->cp15.rvbar;
50
#endif
51
} else {
52
#if defined(CONFIG_USER_ONLY)
53
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_reset_cbar_property =
54
static Property arm_cpu_reset_hivecs_property =
55
DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
56
57
-static Property arm_cpu_rvbar_property =
58
- DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
59
-
60
#ifndef CONFIG_USER_ONLY
61
static Property arm_cpu_has_el2_property =
62
DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
63
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
64
}
65
66
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
67
- qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
68
+ object_property_add_uint64_ptr(obj, "rvbar",
69
+ &cpu->rvbar_prop,
70
+ OBJ_PROP_FLAG_READWRITE);
71
}
72
73
#ifndef CONFIG_USER_ONLY
74
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
75
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/helper.c
32
--- a/target/arm/helper.c
77
+++ b/target/arm/helper.c
33
+++ b/target/arm/helper.c
78
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
34
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
79
ARMCPRegInfo rvbar = {
35
bool enabled, prohibited = false, filtered;
80
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
36
bool secure = arm_is_secure(env);
81
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
37
int el = arm_current_el(env);
82
- .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
38
- uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
83
+ .access = PL1_R,
39
- uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
84
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
40
+ uint64_t mdcr_el2;
85
};
41
+ uint8_t hpmn;
86
define_one_arm_cp_reg(cpu, &rvbar);
42
87
}
43
+ /*
88
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
44
+ * We might be called for M-profile cores where MDCR_EL2 doesn't
89
ARMCPRegInfo rvbar = {
45
+ * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
90
.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
46
+ * must be before we read that value.
91
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
47
+ */
92
- .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
48
if (!arm_feature(env, ARM_FEATURE_PMU)) {
93
+ .access = PL2_R,
49
return false;
94
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
50
}
95
};
51
96
define_one_arm_cp_reg(cpu, &rvbar);
52
+ mdcr_el2 = arm_mdcr_el2_eff(env);
97
}
53
+ hpmn = mdcr_el2 & MDCR_HPMN;
98
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
54
+
99
ARMCPRegInfo el3_regs[] = {
55
if (!arm_feature(env, ARM_FEATURE_EL2) ||
100
{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
56
(counter < hpmn || counter == 31)) {
101
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
57
e = env->cp15.c9_pmcr & PMCRE;
102
- .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
103
+ .access = PL3_R,
104
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
105
+ },
106
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
107
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
108
.access = PL3_RW,
109
--
58
--
110
2.25.1
59
2.34.1
60
61
diff view generated by jsdifflib
[PULL 21/21] util/osdep: Remove some early cruft
[PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
1
From: Andrew Deason <adeason@sinenomine.net>
1
From: Nabih Estefan <nabihestefan@google.com>
2
2
3
The include for statvfs.h has not been needed since all statvfs calls
3
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
4
were removed in commit 4a1418e07bdc ("Unbreak large mem support by
4
of 8xx. Also fix comments referencing this and values expecting 8xx.
5
removing kqemu").
6
5
7
The comment mentioning CONFIG_BSD hasn't made sense since an include
6
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
8
for config-host.h was removed in commit aafd75841001 ("util: Clean up
7
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
9
includes").
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
10
9
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
11
Remove this cruft.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
11
[PMM: commit message tweaks]
15
Message-id: 20220316035227.3702-4-adeason@sinenomine.net
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
13
---
18
util/osdep.c | 7 -------
14
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
19
1 file changed, 7 deletions(-)
15
tests/qtest/meson.build | 3 +-
16
2 files changed, 4 insertions(+), 83 deletions(-)
20
17
21
diff --git a/util/osdep.c b/util/osdep.c
18
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
22
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
23
--- a/util/osdep.c
20
--- a/tests/qtest/npcm_gmac-test.c
24
+++ b/util/osdep.c
21
+++ b/tests/qtest/npcm_gmac-test.c
25
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
26
*/
23
const GMACModule *module;
27
#include "qemu/osdep.h"
24
} TestData;
28
#include "qapi/error.h"
25
26
-/* Values extracted from hw/arm/npcm8xx.c */
27
+/* Values extracted from hw/arm/npcm7xx.c */
28
static const GMACModule gmac_module_list[] = {
29
{
30
.irq = 14,
31
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
32
.irq = 15,
33
.base_addr = 0xf0804000
34
},
35
- {
36
- .irq = 16,
37
- .base_addr = 0xf0806000
38
- },
39
- {
40
- .irq = 17,
41
- .base_addr = 0xf0808000
42
- }
43
};
44
45
/* Returns the index of the GMAC module. */
46
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
47
return qtest_readl(qts, mod->base_addr + regno);
48
}
49
50
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
51
- NPCMRegister regno)
52
-{
53
- uint32_t write_value = (regno & 0x3ffe00) >> 9;
54
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
55
- uint32_t read_offset = regno & 0x1ff;
56
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
57
-}
29
-
58
-
30
-/* Needed early for CONFIG_BSD etc. */
59
/* Check that GMAC registers are reset to default value */
60
static void test_init(gconstpointer test_data)
61
{
62
const TestData *td = test_data;
63
const GMACModule *mod = td->module;
64
- QTestState *qts = qtest_init("-machine npcm845-evb");
65
+ QTestState *qts = qtest_init("-machine npcm750-evb");
66
67
#define CHECK_REG32(regno, value) \
68
do { \
69
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
70
} while (0)
71
72
-#define CHECK_REG_PCS(regno, value) \
73
- do { \
74
- g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
75
- } while (0)
31
-
76
-
32
-#ifdef CONFIG_SOLARIS
77
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
33
-#include <sys/statvfs.h>
78
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
34
-#endif
79
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
80
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
81
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
82
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
83
84
- /* TODO Add registers PCS */
85
- if (mod->base_addr == 0xf0802000) {
86
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
87
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
88
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
35
-
89
-
36
#include "qemu-common.h"
90
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
37
#include "qemu/cutils.h"
91
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
38
#include "qemu/sockets.h"
92
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
93
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
94
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
95
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
96
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
97
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
98
-
99
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
100
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
101
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
102
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
103
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
104
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
105
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
106
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
107
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
108
-
109
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
110
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
111
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
112
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
113
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
114
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
115
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
116
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
117
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
118
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
119
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
120
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
121
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
122
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
123
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
124
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
125
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
126
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
127
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
128
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
129
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
130
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
131
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
132
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
133
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
134
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
135
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
136
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
137
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
138
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
139
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
140
- }
141
-
142
qtest_quit(qts);
143
}
144
145
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
146
index XXXXXXX..XXXXXXX 100644
147
--- a/tests/qtest/meson.build
148
+++ b/tests/qtest/meson.build
149
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
150
'npcm7xx_sdhci-test',
151
'npcm7xx_smbus-test',
152
'npcm7xx_timer-test',
153
- 'npcm7xx_watchdog_timer-test'] + \
154
+ 'npcm7xx_watchdog_timer-test',
155
+ 'npcm_gmac-test'] + \
156
(slirp.found() ? ['npcm7xx_emc-test'] : [])
157
qtests_aspeed = \
158
['aspeed_hace-test',
39
--
159
--
40
2.25.1
160
2.34.1
diff view generated by jsdifflib
[PULL 20/21] hw/i386/acpi-build: Avoid 'sun' identifier
[PULL 18/35] hw/arm/smmuv3: add support for stage 1 access fault
1
From: Andrew Deason <adeason@sinenomine.net>
1
From: Luc Michel <luc.michel@amd.com>
2
2
3
On Solaris, 'sun' is #define'd to 1, which causes errors if a variable
3
An access fault is raised when the Access Flag is not set in the
4
is named 'sun'. Slightly change the name of the var for the Slot User
4
looked-up PTE and the AFFD field is not set in the corresponding context
5
Number so we can build on Solaris.
5
descriptor. This was already implemented for stage 2. Implement it for
6
stage 1 as well.
6
7
7
Reviewed-by: Ani Sinha <ani@anisinha.ca>
8
Signed-off-by: Luc Michel <luc.michel@amd.com>
8
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
9
Reviewed-by: Mostafa Saleh <smostafa@google.com>
9
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 20220316035227.3702-3-adeason@sinenomine.net
11
Tested-by: Mostafa Saleh <smostafa@google.com>
12
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
13
[PMM: tweaked comment text]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
15
---
13
hw/i386/acpi-build.c | 4 ++--
16
hw/arm/smmuv3-internal.h | 1 +
14
1 file changed, 2 insertions(+), 2 deletions(-)
17
include/hw/arm/smmu-common.h | 1 +
18
hw/arm/smmu-common.c | 11 +++++++++++
19
hw/arm/smmuv3.c | 1 +
20
4 files changed, 14 insertions(+)
15
21
16
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
22
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
17
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/i386/acpi-build.c
24
--- a/hw/arm/smmuv3-internal.h
19
+++ b/hw/i386/acpi-build.c
25
+++ b/hw/arm/smmuv3-internal.h
20
@@ -XXX,XX +XXX,XX @@ Aml *aml_pci_device_dsm(void)
26
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
21
Aml *bnum = aml_arg(4);
27
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
22
Aml *func = aml_arg(2);
28
#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
23
Aml *rev = aml_arg(1);
29
#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
24
- Aml *sun = aml_arg(5);
30
+#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
25
+ Aml *sunum = aml_arg(5);
31
#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
26
32
#define CD_HD(x) extract32((x)->word[1], 10 , 1)
27
method = aml_method("PDSM", 6, AML_SERIALIZED);
33
#define CD_HA(x) extract32((x)->word[1], 11 , 1)
28
34
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
29
@@ -XXX,XX +XXX,XX @@ Aml *aml_pci_device_dsm(void)
35
index XXXXXXX..XXXXXXX 100644
30
UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
36
--- a/include/hw/arm/smmu-common.h
31
ifctx = aml_if(aml_equal(aml_arg(0), UUID));
37
+++ b/include/hw/arm/smmu-common.h
32
{
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
33
- aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index));
39
bool disabled; /* smmu is disabled */
34
+ aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
40
bool bypassed; /* translation is bypassed */
35
ifctx1 = aml_if(aml_equal(func, zero));
41
bool aborted; /* translation is aborted */
36
{
42
+ bool affd; /* AF fault disable */
37
uint8_t byte_list[1];
43
uint32_t iotlb_hits; /* counts IOTLB hits */
44
uint32_t iotlb_misses; /* counts IOTLB misses*/
45
/* Used by stage-1 only. */
46
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/smmu-common.c
49
+++ b/hw/arm/smmu-common.c
50
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
51
pte_addr, pte, iova, gpa,
52
block_size >> 20);
53
}
54
+
55
+ /*
56
+ * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
57
+ * are 0 we take an Access flag fault. (5.4. Context Descriptor)
58
+ * An Access flag fault takes priority over a Permission fault.
59
+ */
60
+ if (!PTE_AF(pte) && !cfg->affd) {
61
+ info->type = SMMU_PTW_ERR_ACCESS;
62
+ goto error;
63
+ }
64
+
65
ap = PTE_AP(pte);
66
if (is_permission_fault(ap, perm)) {
67
info->type = SMMU_PTW_ERR_PERMISSION;
68
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/smmuv3.c
71
+++ b/hw/arm/smmuv3.c
72
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
73
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
74
cfg->tbi = CD_TBI(cd);
75
cfg->asid = CD_ASID(cd);
76
+ cfg->affd = CD_AFFD(cd);
77
78
trace_smmuv3_decode_cd(cfg->oas);
79
38
--
80
--
39
2.25.1
81
2.34.1
diff view generated by jsdifflib
[PULL 13/21] hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area
[PULL 19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Add an unimplemented SERDES (Serializer/Deserializer) area.
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20240213155214.13619-2-philmd@linaro.org
6
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Message-id: 20220316164645.2303510-2-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
include/hw/arm/xlnx-zynqmp.h | 2 +-
8
hw/arm/stellaris.c | 6 ++++--
12
hw/arm/xlnx-zynqmp.c | 5 +++++
9
1 file changed, 4 insertions(+), 2 deletions(-)
13
2 files changed, 6 insertions(+), 1 deletion(-)
14
10
15
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/xlnx-zynqmp.h
13
--- a/hw/arm/stellaris.c
18
+++ b/include/hw/arm/xlnx-zynqmp.h
14
+++ b/hw/arm/stellaris.c
19
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
20
/*
16
}
21
* Unimplemented mmio regions needed to boot some images.
17
}
22
*/
18
23
-#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
19
-static void stellaris_adc_reset(StellarisADCState *s)
24
+#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
20
+static void stellaris_adc_reset_hold(Object *obj)
25
21
{
26
struct XlnxZynqMPState {
22
+ StellarisADCState *s = STELLARIS_ADC(obj);
27
/*< private >*/
23
int n;
28
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
24
29
index XXXXXXX..XXXXXXX 100644
25
for (n = 0; n < 4; n++) {
30
--- a/hw/arm/xlnx-zynqmp.c
26
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
31
+++ b/hw/arm/xlnx-zynqmp.c
27
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
32
@@ -XXX,XX +XXX,XX @@
28
"adc", 0x1000);
33
#define QSPI_DMA_ADDR 0xff0f0800
29
sysbus_init_mmio(sbd, &s->iomem);
34
#define NUM_QSPI_IRQ_LINES 2
30
- stellaris_adc_reset(s);
35
31
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
36
+/* Serializer/Deserializer. */
32
}
37
+#define SERDES_ADDR 0xfd400000
33
38
+#define SERDES_SIZE 0x20000
34
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
39
+
35
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
40
#define DP_ADDR 0xfd4a0000
36
{
41
#define DP_IRQ 113
37
DeviceClass *dc = DEVICE_CLASS(klass);
42
38
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
43
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
39
44
hwaddr size;
40
+ rc->phases.hold = stellaris_adc_reset_hold;
45
} unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
41
dc->vmsd = &vmstate_stellaris_adc;
46
{ .name = "apu", APU_ADDR, APU_SIZE },
42
}
47
+ { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
48
};
49
unsigned int nr;
50
43
51
--
44
--
52
2.25.1
45
2.34.1
53
46
54
47
diff view generated by jsdifflib
[PULL 18/21] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
[PULL 20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Connect the ZynqMP APU Control device.
3
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
4
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20240213155214.13619-3-philmd@linaro.org
6
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Message-id: 20220316164645.2303510-7-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
8
---
12
include/hw/arm/xlnx-zynqmp.h | 4 +++-
9
hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
13
hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++--
10
1 file changed, 22 insertions(+), 4 deletions(-)
14
2 files changed, 26 insertions(+), 3 deletions(-)
15
11
16
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-zynqmp.h
14
--- a/hw/arm/stellaris.c
19
+++ b/include/hw/arm/xlnx-zynqmp.h
15
+++ b/hw/arm/stellaris.c
20
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
21
#include "hw/nvram/xlnx-bbram.h"
17
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
22
#include "hw/nvram/xlnx-zynqmp-efuse.h"
23
#include "hw/or-irq.h"
24
+#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
25
#include "hw/misc/xlnx-zynqmp-crf.h"
26
27
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
28
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
29
/*
30
* Unimplemented mmio regions needed to boot some images.
31
*/
32
-#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
33
+#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
34
35
struct XlnxZynqMPState {
36
/*< private >*/
37
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
38
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
39
XlnxCSUDMA qspi_dma;
40
qemu_or_irq qspi_irq_orgate;
41
+ XlnxZynqMPAPUCtrl apu_ctrl;
42
XlnxZynqMPCRF crf;
43
44
char *boot_cpu;
45
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/xlnx-zynqmp.c
48
+++ b/hw/arm/xlnx-zynqmp.c
49
@@ -XXX,XX +XXX,XX @@
50
#define DPDMA_IRQ 116
51
52
#define APU_ADDR 0xfd5c0000
53
-#define APU_SIZE 0x100
54
+#define APU_IRQ 153
55
56
#define IPI_ADDR 0xFF300000
57
#define IPI_IRQ 64
58
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
59
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
60
}
18
}
61
19
62
+static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic)
20
-/* I2C controller. */
63
+{
21
+/*
64
+ SysBusDevice *sbd;
22
+ * I2C controller.
65
+ int i;
23
+ * ??? For now we only implement the master interface.
24
+ */
25
26
#define TYPE_STELLARIS_I2C "stellaris-i2c"
27
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
29
stellaris_i2c_update(s);
30
}
31
32
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
33
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
34
{
35
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
66
+
36
+
67
+ object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl,
37
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
68
+ TYPE_XLNX_ZYNQMP_APU_CTRL);
38
i2c_end_transfer(s->bus);
69
+ sbd = SYS_BUS_DEVICE(&s->apu_ctrl);
70
+
71
+ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
72
+ g_autofree gchar *name = g_strdup_printf("cpu%d", i);
73
+
74
+ object_property_set_link(OBJECT(&s->apu_ctrl), name,
75
+ OBJECT(&s->apu_cpu[i]), &error_abort);
76
+ }
77
+
78
+ sysbus_realize(sbd, &error_fatal);
79
+ sysbus_mmio_map(sbd, 0, APU_ADDR);
80
+ sysbus_connect_irq(sbd, 0, gic[APU_IRQ]);
81
+}
39
+}
82
+
40
+
83
static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
41
+static void stellaris_i2c_reset_hold(Object *obj)
42
+{
43
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
44
45
s->msa = 0;
46
s->mcs = 0;
47
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
48
s->mimr = 0;
49
s->mris = 0;
50
s->mcr = 0;
51
+}
52
+
53
+static void stellaris_i2c_reset_exit(Object *obj)
54
+{
55
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
56
+
57
stellaris_i2c_update(s);
58
}
59
60
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
61
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
62
"i2c", 0x1000);
63
sysbus_init_mmio(sbd, &s->iomem);
64
- /* ??? For now we only implement the master interface. */
65
- stellaris_i2c_reset(s);
66
}
67
68
/* Analogue to Digital Converter. This is only partially implemented,
69
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
70
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
84
{
71
{
85
SysBusDevice *sbd;
72
DeviceClass *dc = DEVICE_CLASS(klass);
86
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
73
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
87
hwaddr base;
74
88
hwaddr size;
75
+ rc->phases.enter = stellaris_i2c_reset_enter;
89
} unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
76
+ rc->phases.hold = stellaris_i2c_reset_hold;
90
- { .name = "apu", APU_ADDR, APU_SIZE },
77
+ rc->phases.exit = stellaris_i2c_reset_exit;
91
{ .name = "serdes", SERDES_ADDR, SERDES_SIZE },
78
dc->vmsd = &vmstate_stellaris_i2c;
92
};
79
}
93
unsigned int nr;
94
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
95
96
xlnx_zynqmp_create_bbram(s, gic_spi);
97
xlnx_zynqmp_create_efuse(s, gic_spi);
98
+ xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
99
xlnx_zynqmp_create_crf(s, gic_spi);
100
xlnx_zynqmp_create_unimp_mmio(s);
101
80
102
--
81
--
103
2.25.1
82
2.34.1
104
83
105
84
diff view generated by jsdifflib
[PULL 09/21] hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG
[PULL 21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
CONFIG_ARM_GIC_TCG actually guards the compilation of TCG GICv3
3
QDev objects created with qdev_new() need to manually add
4
specific files. So let's rename it into CONFIG_ARM_GICV3_TCG
4
their parent relationship with object_property_add_child().
5
5
6
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
This commit plug the devices which aren't part of the SoC;
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
7
they will be plugged into a SoC container in the next one.
8
Message-id: 20220308182452.223473-2-eric.auger@redhat.com
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20240213155214.13619-4-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
hw/intc/Kconfig | 2 +-
14
hw/arm/stellaris.c | 4 ++++
13
hw/intc/meson.build | 4 ++--
15
1 file changed, 4 insertions(+)
14
2 files changed, 3 insertions(+), 3 deletions(-)
15
16
16
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
17
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/Kconfig
19
--- a/hw/arm/stellaris.c
19
+++ b/hw/intc/Kconfig
20
+++ b/hw/arm/stellaris.c
20
@@ -XXX,XX +XXX,XX @@ config APIC
21
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
21
select MSI_NONBROKEN
22
&error_fatal);
22
select I8259
23
23
24
ssddev = qdev_new("ssd0323");
24
-config ARM_GIC_TCG
25
+ object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
25
+config ARM_GICV3_TCG
26
qdev_prop_set_uint8(ssddev, "cs", 1);
26
bool
27
qdev_realize_and_unref(ssddev, bus, &error_fatal);
27
default y
28
28
depends on ARM_GIC && TCG
29
gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
29
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
30
+ object_property_add_child(OBJECT(ms), "splitter",
30
index XXXXXXX..XXXXXXX 100644
31
+ OBJECT(gpio_d_splitter));
31
--- a/hw/intc/meson.build
32
qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
32
+++ b/hw/intc/meson.build
33
qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
33
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
34
qdev_connect_gpio_out(
34
'arm_gicv3_common.c',
35
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
35
'arm_gicv3_its_common.c',
36
DeviceState *gpad;
36
))
37
37
-softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
38
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
38
+softmmu_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files(
39
+ object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
39
'arm_gicv3.c',
40
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
40
'arm_gicv3_dist.c',
41
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
41
'arm_gicv3_its.c',
42
}
42
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
43
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
44
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
45
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
46
-specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c'))
47
+specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cpuif.c'))
48
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
49
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
50
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
51
--
43
--
52
2.25.1
44
2.34.1
45
46
diff view generated by jsdifflib
[PULL 11/21] target/arm: Log M-profile vector table accesses
[PULL 22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
1
Currently the CPU_LOG_INT logging misses some useful information
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
about loads from the vector table. Add logging where we load vector
3
table entries. This is particularly helpful for cases where the user
4
has accidentally not put a vector table in their image at all, which
5
can result in confusing guest crashes at startup.
6
2
7
Here's an example of the new logging for a case where
3
QDev objects created with qdev_new() need to manually add
8
the vector table contains garbage:
4
their parent relationship with object_property_add_child().
9
5
10
Loaded reset SP 0x0 PC 0x0 from vector table
6
Since we don't model the SoC, just use a QOM container.
11
Loaded reset SP 0xd008f8df PC 0xf000bf00 from vector table
12
Taking exception 3 [Prefetch Abort] on CPU 0
13
...with CFSR.IACCVIOL
14
...BusFault with BFSR.STKERR
15
...taking pending nonsecure exception 3
16
...loading from element 3 of non-secure vector table at 0xc
17
...loaded new PC 0x20000558
18
----------------
19
IN:
20
0x20000558: 08000079 stmdaeq r0, {r0, r3, r4, r5, r6}
21
7
22
(The double reset logging is the result of our long-standing
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
23
"CPUs all get reset twice" weirdness; it looks a bit ugly
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
but it'll go away if we ever fix that :-))
10
Message-id: 20240213155214.13619-5-philmd@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/stellaris.c | 11 ++++++++++-
14
1 file changed, 10 insertions(+), 1 deletion(-)
25
15
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
27
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
30
Message-id: 20220315204306.2797684-2-peter.maydell@linaro.org
31
---
32
target/arm/cpu.c | 5 +++++
33
target/arm/m_helper.c | 5 +++++
34
2 files changed, 10 insertions(+)
35
36
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
37
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/cpu.c
18
--- a/hw/arm/stellaris.c
39
+++ b/target/arm/cpu.c
19
+++ b/hw/arm/stellaris.c
40
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
41
#include "qemu/osdep.h"
21
* 400fe000 system control
42
#include "qemu/qemu-print.h"
22
*/
43
#include "qemu/timer.h"
23
44
+#include "qemu/log.h"
24
+ Object *soc_container;
45
#include "qemu-common.h"
25
DeviceState *gpio_dev[7], *nvic;
46
#include "target/arm/idau.h"
26
qemu_irq gpio_in[7][8];
47
#include "qemu/module.h"
27
qemu_irq gpio_out[7][8];
48
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
49
initial_pc = ldl_phys(s->as, vecbase + 4);
29
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
50
}
30
sram_size = ((board->dc0 >> 18) + 1) * 1024;
51
31
52
+ qemu_log_mask(CPU_LOG_INT,
32
+ soc_container = object_new("container");
53
+ "Loaded reset SP 0x%x PC 0x%x from vector table\n",
33
+ object_property_add_child(OBJECT(ms), "soc", soc_container);
54
+ initial_msp, initial_pc);
55
+
34
+
56
env->regs[13] = initial_msp & 0xFFFFFFFC;
35
/* Flash programming is done via the SCU, so pretend it is ROM. */
57
env->regs[15] = initial_pc & ~1;
36
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
58
env->thumb = initial_pc & 1;
37
&error_fatal);
59
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
38
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
60
index XXXXXXX..XXXXXXX 100644
39
* need its sysclk output.
61
--- a/target/arm/m_helper.c
40
*/
62
+++ b/target/arm/m_helper.c
41
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
63
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
42
+ object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
64
ARMMMUIdx mmu_idx;
65
bool exc_secure;
66
67
+ qemu_log_mask(CPU_LOG_INT,
68
+ "...loading from element %d of %s vector table at 0x%x\n",
69
+ exc, targets_secure ? "secure" : "non-secure", addr);
70
+
71
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true);
72
43
73
/*
44
/*
74
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
45
* Most devices come preprogrammed with a MAC address in the user data.
75
goto load_fail;
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
76
}
47
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
77
*pvec = vector_entry;
48
78
+ qemu_log_mask(CPU_LOG_INT, "...loaded new PC 0x%x\n", *pvec);
49
nvic = qdev_new(TYPE_ARMV7M);
79
return true;
50
+ object_property_add_child(soc_container, "v7m", OBJECT(nvic));
80
51
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
81
load_fail:
52
qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
53
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
54
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
55
56
dev = qdev_new(TYPE_STELLARIS_GPTM);
57
sbd = SYS_BUS_DEVICE(dev);
58
+ object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
59
qdev_connect_clock_in(dev, "clk",
60
qdev_get_clock_out(ssys_dev, "SYSCLK"));
61
sysbus_realize_and_unref(sbd, &error_fatal);
62
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
63
64
if (board->dc1 & (1 << 3)) { /* watchdog present */
65
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
66
-
67
+ object_property_add_child(soc_container, "wdg", OBJECT(dev));
68
qdev_connect_clock_in(dev, "WDOGCLK",
69
qdev_get_clock_out(ssys_dev, "SYSCLK"));
70
71
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
72
SysBusDevice *sbd;
73
74
dev = qdev_new("pl011_luminary");
75
+ object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
76
sbd = SYS_BUS_DEVICE(dev);
77
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
78
sysbus_realize_and_unref(sbd, &error_fatal);
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
DeviceState *enet;
81
82
enet = qdev_new("stellaris_enet");
83
+ object_property_add_child(soc_container, "enet", OBJECT(enet));
84
if (nd) {
85
qdev_set_nic_properties(enet, nd);
86
} else {
82
--
87
--
83
2.25.1
88
2.34.1
84
89
85
90
diff view generated by jsdifflib
[PULL 03/21] target/arm: Fix handling of LPAE block descriptors
[PULL 23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
1
LPAE descriptors come in three forms:
1
We support two different encodings for the AArch32 IMPDEF
2
CBAR register -- older cores like the Cortex A9, A7, A15
3
have this at 4, c15, c0, 0; newer cores like the
4
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
2
5
3
* table descriptors, giving the address of the next level page table
6
When we implemented this we picked which encoding to
4
* page descriptors, which occur only at level 3 and describe the
7
use based on whether the CPU set ARM_FEATURE_AARCH64.
5
mapping of one page (which might be 4K, 16K or 64K)
8
However this isn't right for three cases:
6
* block descriptors, which occur at higher page table levels, and
9
* the qemu-system-arm 'max' CPU, which is supposed to be
7
describe the mapping of huge pages
10
a variant on a Cortex-A57; it ought to use the same
11
encoding the A57 does and which the AArch64 'max'
12
exposes to AArch32 guest code
13
* the Cortex-R52, which is AArch32-only but has the CBAR
14
at the newer encoding (and where we incorrectly are
15
not yet setting ARM_FEATURE_CBAR_RO anyway)
16
* any possible future support for other v8 AArch32
17
only CPUs, or for supporting "boot the CPU into
18
AArch32 mode" on our existing cores like the A57 etc
8
19
9
QEMU's page-table-walk code treats block and page entries
20
Make the decision of the encoding be based on whether
10
identically, simply ORing in a number of bits from the input virtual
21
the CPU implements the ARM_FEATURE_V8 flag instead.
11
address that depends on the level of the page table that we stopped
12
at; we depend on the previous masking of descaddr with descaddrmask
13
to have already cleared out the low bits of the descriptor word.
14
22
15
This is not quite right: the address field in a block descriptor is
23
This changes the behaviour only for the qemu-system-arm
16
smaller, and so there are bits which are valid address bits in a page
24
'-cpu max'. We don't expect anybody to be relying on the
17
descriptor or a table descriptor but which are not supposed to be
25
old behaviour because:
18
part of the address in a block descriptor, and descaddrmask does not
26
* it's not what the real hardware Cortex-A57 does
19
clear them. We previously mostly got away with this because those
27
(and that's what our ID register claims we are)
20
descriptor bits are RES0; however with FEAT_BBM (part of Armv8.4)
28
* we don't implement the memory-mapped GICv3 support
21
block descriptor bit 16 is defined to be the nT bit. No emulated
29
which is the only thing that exists at the peripheral
22
QEMU CPU has FEAT_BBM yet, but if the host CPU has it then we might
30
base address pointed to by the register
23
see it when using KVM or hvf.
24
31
25
Explicitly zero out all the descaddr bits we're about to OR vaddr
26
bits into.
27
28
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/790
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Message-id: 20220304165628.2345765-1-peter.maydell@linaro.org
34
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
32
---
35
---
33
target/arm/helper.c | 10 ++++++++--
36
target/arm/helper.c | 2 +-
34
1 file changed, 8 insertions(+), 2 deletions(-)
37
1 file changed, 1 insertion(+), 1 deletion(-)
35
38
36
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
39
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
40
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
43
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
41
indexmask = indexmask_grainsize;
44
* AArch64 cores we might need to add a specific feature flag
42
continue;
45
* to indicate cores with "flavour 2" CBAR.
43
}
44
- /* Block entry at level 1 or 2, or page entry at level 3.
45
+ /*
46
+ * Block entry at level 1 or 2, or page entry at level 3.
47
* These are basically the same thing, although the number
48
- * of bits we pull in from the vaddr varies.
49
+ * of bits we pull in from the vaddr varies. Note that although
50
+ * descaddrmask masks enough of the low bits of the descriptor
51
+ * to give a correct page or table address, the address field
52
+ * in a block descriptor is smaller; so we need to explicitly
53
+ * clear the lower bits here before ORing in the low vaddr bits.
54
*/
46
*/
55
page_size = (1ULL << ((stride * (4 - level)) + 3));
47
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
56
+ descaddr &= ~(page_size - 1);
48
+ if (arm_feature(env, ARM_FEATURE_V8)) {
57
descaddr |= (address & (page_size - 1));
49
/* 32 bit view is [31:18] 0...0 [43:32]. */
58
/* Extract attributes from the descriptor */
50
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
59
attrs = extract64(descriptor, 2, 10)
51
| extract64(cpu->reset_cbar, 32, 12);
60
--
52
--
61
2.25.1
53
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/35] target/arm: The Cortex-R52 has a read-only CBAR
1
The Cortex-R52 implements the Configuration Base Address Register
2
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
3
type, so that our implementation provides the register and the
4
associated qdev property.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
18
set_feature(&cpu->env, ARM_FEATURE_PMSA);
19
set_feature(&cpu->env, ARM_FEATURE_NEON);
20
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
21
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
22
cpu->midr = 0x411fd133; /* r1p3 */
23
cpu->revidr = 0x00000000;
24
cpu->reset_fpsid = 0x41034023;
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
1
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
2
also by enabling the AUXCR feature which defines the ACTLR
3
and HACTLR registers. As is our usual practice, we make these
4
simple reads-as-zero stubs for now.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
11
1 file changed, 108 insertions(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
19
}
20
21
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
22
+ { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
23
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
24
+ { .name = "IMP_ATCMREGIONR",
25
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
26
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
27
+ { .name = "IMP_BTCMREGIONR",
28
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
29
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
30
+ { .name = "IMP_CTCMREGIONR",
31
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
32
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ { .name = "IMP_CSCTLR",
34
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "IMP_BPCTLR",
37
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
38
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
+ { .name = "IMP_MEMPROTCLR",
40
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
41
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
+ { .name = "IMP_SLAVEPCTLR",
43
+ .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
44
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
+ { .name = "IMP_PERIPHREGIONR",
46
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
47
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
48
+ { .name = "IMP_FLASHIFREGIONR",
49
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "IMP_BUILDOPTR",
52
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
53
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "IMP_PINOPTR",
55
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
56
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ { .name = "IMP_QOSR",
58
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
59
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60
+ { .name = "IMP_BUSTIMEOUTR",
61
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
62
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
+ { .name = "IMP_INTMONR",
64
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
65
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66
+ { .name = "IMP_ICERR0",
67
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
68
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69
+ { .name = "IMP_ICERR1",
70
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
71
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
+ { .name = "IMP_DCERR0",
73
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
74
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
+ { .name = "IMP_DCERR1",
76
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
77
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78
+ { .name = "IMP_TCMERR0",
79
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
80
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
+ { .name = "IMP_TCMERR1",
82
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
83
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ { .name = "IMP_TCMSYNDR0",
85
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
86
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+ { .name = "IMP_TCMSYNDR1",
88
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
89
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
90
+ { .name = "IMP_FLASHERR0",
91
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
92
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
93
+ { .name = "IMP_FLASHERR1",
94
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
95
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
96
+ { .name = "IMP_CDBGDR0",
97
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
98
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
99
+ { .name = "IMP_CBDGBR1",
100
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
101
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
102
+ { .name = "IMP_TESTR0",
103
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
104
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
105
+ { .name = "IMP_TESTR1",
106
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
107
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
108
+ { .name = "IMP_CDBGDCI",
109
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
110
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
111
+ { .name = "IMP_CDBGDCT",
112
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
113
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
114
+ { .name = "IMP_CDBGICT",
115
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
116
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
117
+ { .name = "IMP_CDBGDCD",
118
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
119
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
120
+ { .name = "IMP_CDBGICD",
121
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
122
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
123
+};
124
+
125
+
126
static void cortex_r52_initfn(Object *obj)
127
{
128
ARMCPU *cpu = ARM_CPU(obj);
129
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
130
set_feature(&cpu->env, ARM_FEATURE_NEON);
131
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
132
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
133
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
134
cpu->midr = 0x411fd133; /* r1p3 */
135
cpu->revidr = 0x00000000;
136
cpu->reset_fpsid = 0x41034023;
137
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
138
139
cpu->pmsav7_dregion = 16;
140
cpu->pmsav8r_hdregion = 16;
141
+
142
+ define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
143
}
144
145
static void cortex_r5f_initfn(Object *obj)
146
--
147
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/35] target/arm: Allow access to SPSR_hyp from hyp mode
1
Architecturally, the AArch32 MSR/MRS to/from banked register
2
instructions are UNPREDICTABLE for attempts to access a banked
3
register that the guest could access in a more direct way (e.g.
4
using this insn to access r8_fiq when already in FIQ mode). QEMU has
5
chosen to UNDEF on all of these.
1
6
7
However, for the case of accessing SPSR_hyp from hyp mode, it turns
8
out that real hardware permits this, with the same effect as if the
9
guest had directly written to SPSR. Further, there is some
10
guest code out there that assumes it can do this, because it
11
happens to work on hardware: an example Cortex-R52 startup code
12
fragment uses this, and it got copied into various other places,
13
including Zephyr. Zephyr was fixed to not use this:
14
https://github.com/zephyrproject-rtos/zephyr/issues/47330
15
but other examples are still out there, like the selftest
16
binary for the MPS3-AN536.
17
18
For convenience of being able to run guest code, permit
19
this UNPREDICTABLE access instead of UNDEFing it.
20
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
24
---
25
target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
26
target/arm/tcg/translate.c | 19 +++++++++++------
27
2 files changed, 43 insertions(+), 19 deletions(-)
28
29
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/tcg/op_helper.c
32
+++ b/target/arm/tcg/op_helper.c
33
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
34
*/
35
int curmode = env->uncached_cpsr & CPSR_M;
36
37
- if (regno == 17) {
38
- /* ELR_Hyp: a special case because access from tgtmode is OK */
39
- if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
40
- goto undef;
41
+ if (tgtmode == ARM_CPU_MODE_HYP) {
42
+ /*
43
+ * Handle Hyp target regs first because some are special cases
44
+ * which don't want the usual "not accessible from tgtmode" check.
45
+ */
46
+ switch (regno) {
47
+ case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
48
+ if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
49
+ goto undef;
50
+ }
51
+ break;
52
+ case 13:
53
+ if (curmode != ARM_CPU_MODE_MON) {
54
+ goto undef;
55
+ }
56
+ break;
57
+ default:
58
+ g_assert_not_reached();
59
}
60
return;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
63
}
64
}
65
66
- if (tgtmode == ARM_CPU_MODE_HYP) {
67
- /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
68
- if (curmode != ARM_CPU_MODE_MON) {
69
- goto undef;
70
- }
71
- }
72
-
73
return;
74
75
undef:
76
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
77
78
switch (regno) {
79
case 16: /* SPSRs */
80
- env->banked_spsr[bank_number(tgtmode)] = value;
81
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
82
+ /* Only happens for SPSR_Hyp access in Hyp mode */
83
+ env->spsr = value;
84
+ } else {
85
+ env->banked_spsr[bank_number(tgtmode)] = value;
86
+ }
87
break;
88
case 17: /* ELR_Hyp */
89
env->elr_el[2] = value;
90
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
91
92
switch (regno) {
93
case 16: /* SPSRs */
94
- return env->banked_spsr[bank_number(tgtmode)];
95
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
96
+ /* Only happens for SPSR_Hyp access in Hyp mode */
97
+ return env->spsr;
98
+ } else {
99
+ return env->banked_spsr[bank_number(tgtmode)];
100
+ }
101
case 17: /* ELR_Hyp */
102
return env->elr_el[2];
103
case 13:
104
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/tcg/translate.c
107
+++ b/target/arm/tcg/translate.c
108
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
109
break;
110
case ARM_CPU_MODE_HYP:
111
/*
112
- * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
113
- * (and so we can forbid accesses from EL2 or below). elr_hyp
114
- * can be accessed also from Hyp mode, so forbid accesses from
115
- * EL0 or EL1.
116
+ * r13_hyp can only be accessed from Monitor mode, and so we
117
+ * can forbid accesses from EL2 or below.
118
+ * elr_hyp can be accessed also from Hyp mode, so forbid
119
+ * accesses from EL0 or EL1.
120
+ * SPSR_hyp is supposed to be in the same category as r13_hyp
121
+ * and UNPREDICTABLE if accessed from anything except Monitor
122
+ * mode. However there is some real-world code that will do
123
+ * it because at least some hardware happens to permit the
124
+ * access. (Notably a standard Cortex-R52 startup code fragment
125
+ * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
126
+ * this (incorrect) guest code to run.
127
*/
128
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
129
- (s->current_el < 3 && *regno != 17)) {
130
+ if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
131
+ || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
132
goto undef;
133
}
134
break;
135
--
136
2.34.1
diff view generated by jsdifflib
[PULL 02/21] target/arm: Fix pauth_check_trap vs SEL2
[PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
1
From: Richard Henderson <richard.henderson@linaro.org>
1
We currently guard the CFG3 register read with
2
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
3
which is clearly wrong as it is never true.
2
4
3
When arm_is_el2_enabled was introduced, we missed
5
This register is present on all board types except AN524
4
updating pauth_check_trap.
6
and AN527; correct the condition.
5
7
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/788
8
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
7
Fixes: e6ef0169264b ("target/arm: use arm_is_el2_enabled() where applicable")
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20220315021205.342768-1-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
12
---
13
---
13
target/arm/pauth_helper.c | 2 +-
14
hw/misc/mps2-scc.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
16
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
17
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/pauth_helper.c
19
--- a/hw/misc/mps2-scc.c
19
+++ b/target/arm/pauth_helper.c
20
+++ b/hw/misc/mps2-scc.c
20
@@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el,
21
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
21
22
r = s->cfg2;
22
static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra)
23
break;
23
{
24
case A_CFG3:
24
- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
25
- if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
25
+ if (el < 2 && arm_is_el2_enabled(env)) {
26
+ if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
26
uint64_t hcr = arm_hcr_el2_eff(env);
27
/* CFG3 reserved on AN524 */
27
bool trap = !(hcr & HCR_API);
28
goto bad_offset;
28
if (el == 0) {
29
}
29
--
30
--
30
2.25.1
31
2.34.1
31
32
32
33
diff view generated by jsdifflib
[PULL 05/21] hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
[PULL 28/35] hw/misc/mps2-scc: Factor out which-board conditionals
1
In npcm7xx_clk_sel_init() we allocate a string with g_strdup_printf().
1
The MPS SCC device has a lot of different flavours for the various
2
Use g_autofree so we free it rather than leaking it.
2
different MPS FPGA images, which look mostly similar but have
3
differences in how particular registers are handled. Currently we
4
deal with this with a lot of open-coded checks on scc_partno(), but
5
as we add more board types this is getting a bit hard to read.
3
6
4
(Detected with the clang leak sanitizer.)
7
Factor out the conditions into some functions which we can
8
give more descriptive names to.
5
9
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
9
Message-id: 20220308170302.2582820-1-peter.maydell@linaro.org
10
---
14
---
11
hw/misc/npcm7xx_clk.c | 4 ++--
15
hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
12
1 file changed, 2 insertions(+), 2 deletions(-)
16
1 file changed, 31 insertions(+), 14 deletions(-)
13
17
14
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
18
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/npcm7xx_clk.c
20
--- a/hw/misc/mps2-scc.c
17
+++ b/hw/misc/npcm7xx_clk.c
21
+++ b/hw/misc/mps2-scc.c
18
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_sel_init(Object *obj)
22
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
19
NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
23
return extract32(s->id, 4, 8);
20
24
}
21
for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
25
22
- sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
26
+/* Is CFG_REG2 present? */
23
- g_strdup_printf("clock-in[%d]", i),
27
+static bool have_cfg2(MPS2SCC *s)
24
+ g_autofree char *s = g_strdup_printf("clock-in[%d]", i);
28
+{
25
+ sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), s,
29
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
26
npcm7xx_clk_update_sel_cb, sel, ClockUpdate);
30
+}
27
}
31
+
28
sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
32
+/* Is CFG_REG3 present? */
33
+static bool have_cfg3(MPS2SCC *s)
34
+{
35
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
36
+}
37
+
38
+/* Is CFG_REG5 present? */
39
+static bool have_cfg5(MPS2SCC *s)
40
+{
41
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
42
+}
43
+
44
+/* Is CFG_REG6 present? */
45
+static bool have_cfg6(MPS2SCC *s)
46
+{
47
+ return scc_partno(s) == 0x524;
48
+}
49
+
50
/* Handle a write via the SYS_CFG channel to the specified function/device.
51
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
52
*/
53
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
54
r = s->cfg1;
55
break;
56
case A_CFG2:
57
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
58
- /* CFG2 reserved on other boards */
59
+ if (!have_cfg2(s)) {
60
goto bad_offset;
61
}
62
r = s->cfg2;
63
break;
64
case A_CFG3:
65
- if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
66
- /* CFG3 reserved on AN524 */
67
+ if (!have_cfg3(s)) {
68
goto bad_offset;
69
}
70
/* These are user-settable DIP switches on the board. We don't
71
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
72
r = s->cfg4;
73
break;
74
case A_CFG5:
75
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
76
- /* CFG5 reserved on other boards */
77
+ if (!have_cfg5(s)) {
78
goto bad_offset;
79
}
80
r = s->cfg5;
81
break;
82
case A_CFG6:
83
- if (scc_partno(s) != 0x524) {
84
- /* CFG6 reserved on other boards */
85
+ if (!have_cfg6(s)) {
86
goto bad_offset;
87
}
88
r = s->cfg6;
89
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
90
}
91
break;
92
case A_CFG2:
93
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
94
- /* CFG2 reserved on other boards */
95
+ if (!have_cfg2(s)) {
96
goto bad_offset;
97
}
98
/* AN524: QSPI Select signal */
99
s->cfg2 = value;
100
break;
101
case A_CFG5:
102
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
103
- /* CFG5 reserved on other boards */
104
+ if (!have_cfg5(s)) {
105
goto bad_offset;
106
}
107
/* AN524: ACLK frequency in Hz */
108
s->cfg5 = value;
109
break;
110
case A_CFG6:
111
- if (scc_partno(s) != 0x524) {
112
- /* CFG6 reserved on other boards */
113
+ if (!have_cfg6(s)) {
114
goto bad_offset;
115
}
116
/* AN524: Clock divider for BRAM */
29
--
117
--
30
2.25.1
118
2.34.1
31
119
32
120
diff view generated by jsdifflib
New patch
[PULL 29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
1
1
The MPS2 SCC device is broadly the same for all FPGA images, but has
2
minor differences in the behaviour of the CFG registers depending on
3
the image. In many cases we don't really care about the functionality
4
controlled by these registers and a reads-as-written or similar
5
behaviour is sufficient for the moment.
6
7
For the AN536 the required behaviour is:
8
9
* A_CFG0 has CPU reset and halt bits
10
- implement as reads-as-written for the moment
11
* A_CFG1 has flash or ATCM address 0 remap handling
12
- QEMU doesn't model this; implement as reads-as-written
13
* A_CFG2 has QSPI select (like AN524)
14
- implemented (no behaviour, as with AN524)
15
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
16
- QEMU doesn't care about these, so use the existing
17
RAZ behaviour for convenience
18
* A_CFG4 is board rev (like all other images)
19
- no change needed
20
* A_CFG5 is ACLK frq in hz (like AN524)
21
- implemented as reads-as-written, as for other boards
22
* A_CFG6 is core 0 vector table base address
23
- implemented as reads-as-written for the moment
24
* A_CFG7 is core 1 vector table base address
25
- implemented as reads-as-written for the moment
26
27
Make the changes necessary for this; leave TODO comments where
28
appropriate to indicate where we might want to come back and
29
implement things like CPU reset.
30
31
The other aspects of the device specific to this FPGA image (like the
32
values of the board ID and similar registers) will be set via the
33
device's qdev properties.
34
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
38
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
39
---
40
include/hw/misc/mps2-scc.h | 1 +
41
hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++----
42
2 files changed, 92 insertions(+), 10 deletions(-)
43
44
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/misc/mps2-scc.h
47
+++ b/include/hw/misc/mps2-scc.h
48
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
49
uint32_t cfg4;
50
uint32_t cfg5;
51
uint32_t cfg6;
52
+ uint32_t cfg7;
53
uint32_t cfgdata_rtn;
54
uint32_t cfgdata_out;
55
uint32_t cfgctrl;
56
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/mps2-scc.c
59
+++ b/hw/misc/mps2-scc.c
60
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
61
REG32(CFG4, 0x10)
62
REG32(CFG5, 0x14)
63
REG32(CFG6, 0x18)
64
+REG32(CFG7, 0x1c)
65
REG32(CFGDATA_RTN, 0xa0)
66
REG32(CFGDATA_OUT, 0xa4)
67
REG32(CFGCTRL, 0xa8)
68
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
69
/* Is CFG_REG2 present? */
70
static bool have_cfg2(MPS2SCC *s)
71
{
72
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
73
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
74
+ scc_partno(s) == 0x536;
75
}
76
77
/* Is CFG_REG3 present? */
78
static bool have_cfg3(MPS2SCC *s)
79
{
80
- return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
81
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
82
+ scc_partno(s) != 0x536;
83
}
84
85
/* Is CFG_REG5 present? */
86
static bool have_cfg5(MPS2SCC *s)
87
{
88
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
89
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
90
+ scc_partno(s) == 0x536;
91
}
92
93
/* Is CFG_REG6 present? */
94
static bool have_cfg6(MPS2SCC *s)
95
{
96
- return scc_partno(s) == 0x524;
97
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
98
+}
99
+
100
+/* Is CFG_REG7 present? */
101
+static bool have_cfg7(MPS2SCC *s)
102
+{
103
+ return scc_partno(s) == 0x536;
104
+}
105
+
106
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
107
+static bool cfg0_is_remap(MPS2SCC *s)
108
+{
109
+ return scc_partno(s) != 0x536;
110
+}
111
+
112
+/* Is CFG_REG1 driving a set of LEDs? */
113
+static bool cfg1_is_leds(MPS2SCC *s)
114
+{
115
+ return scc_partno(s) != 0x536;
116
}
117
118
/* Handle a write via the SYS_CFG channel to the specified function/device.
119
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
120
if (!have_cfg3(s)) {
121
goto bad_offset;
122
}
123
- /* These are user-settable DIP switches on the board. We don't
124
+ /*
125
+ * These are user-settable DIP switches on the board. We don't
126
* model that, so just return zeroes.
127
+ *
128
+ * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
129
+ * bits". These change which part of the DDR4 the motherboard
130
+ * configuration controller can see in its memory map (see the
131
+ * appnote section 2.4). QEMU doesn't model the MCC at all, so these
132
+ * bits are not interesting to us; read-as-zero is as good as anything
133
+ * else.
134
*/
135
r = 0;
136
break;
137
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
138
}
139
r = s->cfg6;
140
break;
141
+ case A_CFG7:
142
+ if (!have_cfg7(s)) {
143
+ goto bad_offset;
144
+ }
145
+ r = s->cfg7;
146
+ break;
147
case A_CFGDATA_RTN:
148
r = s->cfgdata_rtn;
149
break;
150
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
151
* we always reflect bit 0 in the 'remap' GPIO output line,
152
* and let the board wire it up or not as it chooses.
153
* TODO on some boards bit 1 is CPU_WAIT.
154
+ *
155
+ * TODO: on the AN536 this register controls reset and halt
156
+ * for both CPUs. For the moment we don't implement this, so the
157
+ * register just reads as written.
158
*/
159
s->cfg0 = value;
160
- qemu_set_irq(s->remap, s->cfg0 & 1);
161
+ if (cfg0_is_remap(s)) {
162
+ qemu_set_irq(s->remap, s->cfg0 & 1);
163
+ }
164
break;
165
case A_CFG1:
166
s->cfg1 = value;
167
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
168
- led_set_state(s->led[i], extract32(value, i, 1));
169
+ /*
170
+ * On most boards this register drives LEDs.
171
+ *
172
+ * TODO: for AN536 this controls whether flash and ATCM are
173
+ * enabled or disabled on reset. QEMU doesn't model this, and
174
+ * always wires up RAM in the ATCM area and ROM in the flash area.
175
+ */
176
+ if (cfg1_is_leds(s)) {
177
+ for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
178
+ led_set_state(s->led[i], extract32(value, i, 1));
179
+ }
180
}
181
break;
182
case A_CFG2:
183
if (!have_cfg2(s)) {
184
goto bad_offset;
185
}
186
- /* AN524: QSPI Select signal */
187
+ /* AN524, AN536: QSPI Select signal */
188
s->cfg2 = value;
189
break;
190
case A_CFG5:
191
if (!have_cfg5(s)) {
192
goto bad_offset;
193
}
194
- /* AN524: ACLK frequency in Hz */
195
+ /* AN524, AN536: ACLK frequency in Hz */
196
s->cfg5 = value;
197
break;
198
case A_CFG6:
199
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
200
goto bad_offset;
201
}
202
/* AN524: Clock divider for BRAM */
203
+ /* AN536: Core 0 vector table base address */
204
+ s->cfg6 = value;
205
+ break;
206
+ case A_CFG7:
207
+ if (!have_cfg7(s)) {
208
+ goto bad_offset;
209
+ }
210
+ /* AN536: Core 1 vector table base address */
211
s->cfg6 = value;
212
break;
213
case A_CFGDATA_OUT:
214
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
215
g_free(s->oscclk_reset);
216
}
217
218
+static bool cfg7_needed(void *opaque)
219
+{
220
+ MPS2SCC *s = opaque;
221
+
222
+ return have_cfg7(s);
223
+}
224
+
225
+static const VMStateDescription vmstate_cfg7 = {
226
+ .name = "mps2-scc/cfg7",
227
+ .version_id = 1,
228
+ .minimum_version_id = 1,
229
+ .needed = cfg7_needed,
230
+ .fields = (const VMStateField[]) {
231
+ VMSTATE_UINT32(cfg7, MPS2SCC),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
static const VMStateDescription mps2_scc_vmstate = {
237
.name = "mps2-scc",
238
.version_id = 3,
239
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
240
VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
241
0, vmstate_info_uint32, uint32_t),
242
VMSTATE_END_OF_LIST()
243
+ },
244
+ .subsections = (const VMStateDescription * const []) {
245
+ &vmstate_cfg7,
246
+ NULL
247
}
248
};
249
250
--
251
2.34.1
252
253
diff view generated by jsdifflib
[PULL 15/21] hw/misc: Add a model of the Xilinx ZynqMP CRF
[PULL 30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
The AN536 is another FPGA image for the MPS3 development board. Unlike
2
2
the existing FPGA images we already model, this board uses a Cortex-R
3
Add a model of the Xilinx ZynqMP CRF. At the moment this
3
family CPU, and it does not use any equivalent to the M-profile
4
is mostly a stub model.
4
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
5
5
It's therefore more convenient for us to model it as a completely
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
separate C file.
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
This commit adds the basic skeleton of the board model, and the
9
Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com
9
code to create all the RAM and ROM. We assume that we're probably
10
going to want to add more images in future, so use the same
11
base class/subclass setup that mps2-tz.c uses, even though at
12
the moment there's only a single subclass.
13
14
Following commits will add the CPUs and the peripherals.
15
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
11
---
19
---
12
include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++
20
MAINTAINERS | 3 +-
13
hw/misc/xlnx-zynqmp-crf.c | 266 ++++++++++++++++++++++++++++++
21
configs/devices/arm-softmmu/default.mak | 1 +
14
hw/misc/meson.build | 1 +
22
hw/arm/mps3r.c | 239 ++++++++++++++++++++++++
15
3 files changed, 478 insertions(+)
23
hw/arm/Kconfig | 5 +
16
create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
24
hw/arm/meson.build | 1 +
17
create mode 100644 hw/misc/xlnx-zynqmp-crf.c
25
5 files changed, 248 insertions(+), 1 deletion(-)
18
26
create mode 100644 hw/arm/mps3r.c
19
diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h
27
28
diff --git a/MAINTAINERS b/MAINTAINERS
29
index XXXXXXX..XXXXXXX 100644
30
--- a/MAINTAINERS
31
+++ b/MAINTAINERS
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
33
F: hw/pci-host/designware.c
34
F: include/hw/pci-host/designware.h
35
36
-MPS2
37
+MPS2 / MPS3
38
M: Peter Maydell <peter.maydell@linaro.org>
39
L: qemu-arm@nongnu.org
40
S: Maintained
41
F: hw/arm/mps2.c
42
F: hw/arm/mps2-tz.c
43
+F: hw/arm/mps3r.c
44
F: hw/misc/mps2-*.c
45
F: include/hw/misc/mps2-*.h
46
F: hw/arm/armsse.c
47
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
48
index XXXXXXX..XXXXXXX 100644
49
--- a/configs/devices/arm-softmmu/default.mak
50
+++ b/configs/devices/arm-softmmu/default.mak
51
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
52
# CONFIG_INTEGRATOR=n
53
# CONFIG_FSL_IMX31=n
54
# CONFIG_MUSICPAL=n
55
+# CONFIG_MPS3R=n
56
# CONFIG_MUSCA=n
57
# CONFIG_CHEETAH=n
58
# CONFIG_SX1=n
59
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
20
new file mode 100644
60
new file mode 100644
21
index XXXXXXX..XXXXXXX
61
index XXXXXXX..XXXXXXX
22
--- /dev/null
62
--- /dev/null
23
+++ b/include/hw/misc/xlnx-zynqmp-crf.h
63
+++ b/hw/arm/mps3r.c
24
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@
25
+/*
65
+/*
26
+ * QEMU model of the CRF - Clock Reset FPD.
66
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
67
+ * (For M-profile images see mps2.c and mps2tz.c.)
27
+ *
68
+ *
28
+ * Copyright (c) 2022 Xilinx Inc.
69
+ * Copyright (c) 2017 Linaro Limited
29
+ * SPDX-License-Identifier: GPL-2.0-or-later
70
+ * Written by Peter Maydell
30
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
71
+ *
72
+ * This program is free software; you can redistribute it and/or modify
73
+ * it under the terms of the GNU General Public License version 2 or
74
+ * (at your option) any later version.
31
+ */
75
+ */
32
+#ifndef HW_MISC_XLNX_ZYNQMP_CRF_H
76
+
33
+#define HW_MISC_XLNX_ZYNQMP_CRF_H
77
+/*
34
+
78
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
35
+#include "hw/sysbus.h"
79
+ * which use the Cortex-R CPUs. We model these separately from the
36
+#include "hw/register.h"
80
+ * M-profile images, because on M-profile the FPGA image is based on
37
+
81
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
38
+#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
82
+ * the R-profile FPGA images don't have that abstraction layer.
39
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF)
83
+ *
40
+
84
+ * We model the following FPGA images here:
41
+REG32(ERR_CTRL, 0x0)
85
+ * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
42
+ FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
86
+ *
43
+REG32(IR_STATUS, 0x4)
87
+ * Application Note AN536:
44
+ FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
88
+ * https://developer.arm.com/documentation/dai0536/latest/
45
+REG32(IR_MASK, 0x8)
89
+ */
46
+ FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
90
+
47
+REG32(IR_ENABLE, 0xc)
91
+#include "qemu/osdep.h"
48
+ FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
92
+#include "qemu/units.h"
49
+REG32(IR_DISABLE, 0x10)
93
+#include "qapi/error.h"
50
+ FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
94
+#include "exec/address-spaces.h"
51
+REG32(CRF_WPROT, 0x1c)
95
+#include "cpu.h"
52
+ FIELD(CRF_WPROT, ACTIVE, 0, 1)
96
+#include "hw/boards.h"
53
+REG32(APLL_CTRL, 0x20)
97
+#include "hw/arm/boot.h"
54
+ FIELD(APLL_CTRL, POST_SRC, 24, 3)
98
+
55
+ FIELD(APLL_CTRL, PRE_SRC, 20, 3)
99
+/* Define the layout of RAM and ROM in a board */
56
+ FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
100
+typedef struct RAMInfo {
57
+ FIELD(APLL_CTRL, DIV2, 16, 1)
101
+ const char *name;
58
+ FIELD(APLL_CTRL, FBDIV, 8, 7)
102
+ hwaddr base;
59
+ FIELD(APLL_CTRL, BYPASS, 3, 1)
103
+ hwaddr size;
60
+ FIELD(APLL_CTRL, RESET, 0, 1)
104
+ int mrindex; /* index into rams[]; -1 for the system RAM block */
61
+REG32(APLL_CFG, 0x24)
105
+ int flags;
62
+ FIELD(APLL_CFG, LOCK_DLY, 25, 7)
106
+} RAMInfo;
63
+ FIELD(APLL_CFG, LOCK_CNT, 13, 10)
107
+
64
+ FIELD(APLL_CFG, LFHF, 10, 2)
108
+/*
65
+ FIELD(APLL_CFG, CP, 5, 4)
109
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
66
+ FIELD(APLL_CFG, RES, 0, 4)
110
+ * emulation of that much guest RAM, so artificially make it smaller.
67
+REG32(APLL_FRAC_CFG, 0x28)
111
+ */
68
+ FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
112
+#if HOST_LONG_BITS == 32
69
+ FIELD(APLL_FRAC_CFG, SEED, 22, 3)
113
+#define MPS3_DDR_SIZE (1 * GiB)
70
+ FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
114
+#else
71
+ FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
115
+#define MPS3_DDR_SIZE (3 * GiB)
72
+ FIELD(APLL_FRAC_CFG, DATA, 0, 16)
116
+#endif
73
+REG32(DPLL_CTRL, 0x2c)
117
+
74
+ FIELD(DPLL_CTRL, POST_SRC, 24, 3)
118
+/*
75
+ FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
119
+ * Flag values:
76
+ FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
120
+ * IS_MAIN: this is the main machine RAM
77
+ FIELD(DPLL_CTRL, DIV2, 16, 1)
121
+ * IS_ROM: this area is read-only
78
+ FIELD(DPLL_CTRL, FBDIV, 8, 7)
122
+ */
79
+ FIELD(DPLL_CTRL, BYPASS, 3, 1)
123
+#define IS_MAIN 1
80
+ FIELD(DPLL_CTRL, RESET, 0, 1)
124
+#define IS_ROM 2
81
+REG32(DPLL_CFG, 0x30)
125
+
82
+ FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
126
+#define MPS3R_RAM_MAX 9
83
+ FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
127
+
84
+ FIELD(DPLL_CFG, LFHF, 10, 2)
128
+typedef enum MPS3RFPGAType {
85
+ FIELD(DPLL_CFG, CP, 5, 4)
129
+ FPGA_AN536,
86
+ FIELD(DPLL_CFG, RES, 0, 4)
130
+} MPS3RFPGAType;
87
+REG32(DPLL_FRAC_CFG, 0x34)
131
+
88
+ FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
132
+struct MPS3RMachineClass {
89
+ FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
133
+ MachineClass parent;
90
+ FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
134
+ MPS3RFPGAType fpga_type;
91
+ FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
135
+ const RAMInfo *raminfo;
92
+ FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
93
+REG32(VPLL_CTRL, 0x38)
94
+ FIELD(VPLL_CTRL, POST_SRC, 24, 3)
95
+ FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
96
+ FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
97
+ FIELD(VPLL_CTRL, DIV2, 16, 1)
98
+ FIELD(VPLL_CTRL, FBDIV, 8, 7)
99
+ FIELD(VPLL_CTRL, BYPASS, 3, 1)
100
+ FIELD(VPLL_CTRL, RESET, 0, 1)
101
+REG32(VPLL_CFG, 0x3c)
102
+ FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
103
+ FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
104
+ FIELD(VPLL_CFG, LFHF, 10, 2)
105
+ FIELD(VPLL_CFG, CP, 5, 4)
106
+ FIELD(VPLL_CFG, RES, 0, 4)
107
+REG32(VPLL_FRAC_CFG, 0x40)
108
+ FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
109
+ FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
110
+ FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
111
+ FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
112
+ FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
113
+REG32(PLL_STATUS, 0x44)
114
+ FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
115
+ FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
116
+ FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
117
+ FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
118
+ FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
119
+ FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
120
+REG32(APLL_TO_LPD_CTRL, 0x48)
121
+ FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
122
+REG32(DPLL_TO_LPD_CTRL, 0x4c)
123
+ FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
124
+REG32(VPLL_TO_LPD_CTRL, 0x50)
125
+ FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
126
+REG32(ACPU_CTRL, 0x60)
127
+ FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
128
+ FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
129
+ FIELD(ACPU_CTRL, DIVISOR0, 8, 6)
130
+ FIELD(ACPU_CTRL, SRCSEL, 0, 3)
131
+REG32(DBG_TRACE_CTRL, 0x64)
132
+ FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
133
+ FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
134
+ FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
135
+REG32(DBG_FPD_CTRL, 0x68)
136
+ FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
137
+ FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
138
+ FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
139
+REG32(DP_VIDEO_REF_CTRL, 0x70)
140
+ FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
141
+ FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6)
142
+ FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
143
+ FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
144
+REG32(DP_AUDIO_REF_CTRL, 0x74)
145
+ FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
146
+ FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6)
147
+ FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
148
+ FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
149
+REG32(DP_STC_REF_CTRL, 0x7c)
150
+ FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
151
+ FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
152
+ FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
153
+ FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
154
+REG32(DDR_CTRL, 0x80)
155
+ FIELD(DDR_CTRL, CLKACT, 24, 1)
156
+ FIELD(DDR_CTRL, DIVISOR0, 8, 6)
157
+ FIELD(DDR_CTRL, SRCSEL, 0, 3)
158
+REG32(GPU_REF_CTRL, 0x84)
159
+ FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
160
+ FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
161
+ FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
162
+ FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
163
+ FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
164
+REG32(SATA_REF_CTRL, 0xa0)
165
+ FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
166
+ FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
167
+ FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
168
+REG32(PCIE_REF_CTRL, 0xb4)
169
+ FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
170
+ FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
171
+ FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
172
+REG32(GDMA_REF_CTRL, 0xb8)
173
+ FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
174
+ FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
175
+ FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
176
+REG32(DPDMA_REF_CTRL, 0xbc)
177
+ FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
178
+ FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
179
+ FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
180
+REG32(TOPSW_MAIN_CTRL, 0xc0)
181
+ FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
182
+ FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
183
+ FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
184
+REG32(TOPSW_LSBUS_CTRL, 0xc4)
185
+ FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
186
+ FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
187
+ FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
188
+REG32(DBG_TSTMP_CTRL, 0xf8)
189
+ FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6)
190
+ FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
191
+REG32(RST_FPD_TOP, 0x100)
192
+ FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
193
+ FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
194
+ FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
195
+ FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
196
+ FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
197
+ FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
198
+ FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
199
+ FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
200
+ FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
201
+ FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
202
+ FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
203
+ FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
204
+ FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
205
+ FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
206
+ FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
207
+ FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
208
+ FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
209
+REG32(RST_FPD_APU, 0x104)
210
+ FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
211
+ FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
212
+ FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
213
+ FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
214
+ FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
215
+ FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
216
+ FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
217
+ FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
218
+ FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
219
+REG32(RST_DDR_SS, 0x108)
220
+ FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
221
+ FIELD(RST_DDR_SS, APM_RESET, 2, 1)
222
+
223
+#define CRF_R_MAX (R_RST_DDR_SS + 1)
224
+
225
+struct XlnxZynqMPCRF {
226
+ SysBusDevice parent_obj;
227
+ MemoryRegion iomem;
228
+ qemu_irq irq_ir;
229
+
230
+ RegisterInfoArray *reg_array;
231
+ uint32_t regs[CRF_R_MAX];
232
+ RegisterInfo regs_info[CRF_R_MAX];
233
+};
136
+};
234
+
137
+
235
+#endif
138
+struct MPS3RMachineState {
236
diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c
139
+ MachineState parent;
237
new file mode 100644
140
+ MemoryRegion ram[MPS3R_RAM_MAX];
238
index XXXXXXX..XXXXXXX
141
+};
239
--- /dev/null
142
+
240
+++ b/hw/misc/xlnx-zynqmp-crf.c
143
+#define TYPE_MPS3R_MACHINE "mps3r"
241
@@ -XXX,XX +XXX,XX @@
144
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
242
+/*
145
+
243
+ * QEMU model of the CRF - Clock Reset FPD.
146
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
244
+ *
147
+
245
+ * Copyright (c) 2022 Xilinx Inc.
148
+static const RAMInfo an536_raminfo[] = {
246
+ * SPDX-License-Identifier: GPL-2.0-or-later
149
+ {
247
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
150
+ .name = "ATCM",
248
+ */
151
+ .base = 0x00000000,
249
+
152
+ .size = 0x00008000,
250
+#include "qemu/osdep.h"
153
+ .mrindex = 0,
251
+#include "hw/sysbus.h"
154
+ }, {
252
+#include "hw/register.h"
155
+ /* We model the QSPI flash as simple ROM for now */
253
+#include "qemu/bitops.h"
156
+ .name = "QSPI",
254
+#include "qemu/log.h"
157
+ .base = 0x08000000,
255
+#include "migration/vmstate.h"
158
+ .size = 0x00800000,
256
+#include "hw/irq.h"
159
+ .flags = IS_ROM,
257
+#include "hw/misc/xlnx-zynqmp-crf.h"
160
+ .mrindex = 1,
258
+#include "target/arm/arm-powerctl.h"
161
+ }, {
259
+
162
+ .name = "BRAM",
260
+#ifndef XLNX_ZYNQMP_CRF_ERR_DEBUG
163
+ .base = 0x10000000,
261
+#define XLNX_ZYNQMP_CRF_ERR_DEBUG 0
164
+ .size = 0x00080000,
262
+#endif
165
+ .mrindex = 2,
263
+
166
+ }, {
264
+#define CRF_MAX_CPU 4
167
+ .name = "DDR",
265
+
168
+ .base = 0x20000000,
266
+static void ir_update_irq(XlnxZynqMPCRF *s)
169
+ .size = MPS3_DDR_SIZE,
267
+{
170
+ .mrindex = -1,
268
+ bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
171
+ }, {
269
+ qemu_set_irq(s->irq_ir, pending);
172
+ .name = "ATCM0",
270
+}
173
+ .base = 0xee000000,
271
+
174
+ .size = 0x00008000,
272
+static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
175
+ .mrindex = 3,
273
+{
176
+ }, {
274
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
177
+ .name = "BTCM0",
275
+ ir_update_irq(s);
178
+ .base = 0xee100000,
276
+}
179
+ .size = 0x00008000,
277
+
180
+ .mrindex = 4,
278
+static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
181
+ }, {
279
+{
182
+ .name = "CTCM0",
280
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
183
+ .base = 0xee200000,
281
+ uint32_t val = val64;
184
+ .size = 0x00008000,
282
+
185
+ .mrindex = 5,
283
+ s->regs[R_IR_MASK] &= ~val;
186
+ }, {
284
+ ir_update_irq(s);
187
+ .name = "ATCM1",
285
+ return 0;
188
+ .base = 0xee400000,
286
+}
189
+ .size = 0x00008000,
287
+
190
+ .mrindex = 6,
288
+static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
191
+ }, {
289
+{
192
+ .name = "BTCM1",
290
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
193
+ .base = 0xee500000,
291
+ uint32_t val = val64;
194
+ .size = 0x00008000,
292
+
195
+ .mrindex = 7,
293
+ s->regs[R_IR_MASK] |= val;
196
+ }, {
294
+ ir_update_irq(s);
197
+ .name = "CTCM1",
295
+ return 0;
198
+ .base = 0xee600000,
296
+}
199
+ .size = 0x00008000,
297
+
200
+ .mrindex = 8,
298
+static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64)
201
+ }, {
299
+{
202
+ .name = NULL,
300
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
203
+ }
301
+ uint32_t val = val64;
204
+};
302
+ uint32_t val_old = s->regs[R_RST_FPD_APU];
205
+
303
+ unsigned int i;
206
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
304
+
207
+ const RAMInfo *raminfo)
305
+ for (i = 0; i < CRF_MAX_CPU; i++) {
208
+{
306
+ uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i));
209
+ /* Return an initialized MemoryRegion for the RAMInfo. */
307
+
210
+ MemoryRegion *ram;
308
+ if ((val ^ val_old) & mask) {
211
+
309
+ if (val & mask) {
212
+ if (raminfo->mrindex < 0) {
310
+ arm_set_cpu_off(i);
213
+ /* Means this RAMInfo is for QEMU's "system memory" */
311
+ } else {
214
+ MachineState *machine = MACHINE(mms);
312
+ arm_set_cpu_on_and_reset(i);
215
+ assert(!(raminfo->flags & IS_ROM));
313
+ }
216
+ return machine->ram;
217
+ }
218
+
219
+ assert(raminfo->mrindex < MPS3R_RAM_MAX);
220
+ ram = &mms->ram[raminfo->mrindex];
221
+
222
+ memory_region_init_ram(ram, NULL, raminfo->name,
223
+ raminfo->size, &error_fatal);
224
+ if (raminfo->flags & IS_ROM) {
225
+ memory_region_set_readonly(ram, true);
226
+ }
227
+ return ram;
228
+}
229
+
230
+static void mps3r_common_init(MachineState *machine)
231
+{
232
+ MPS3RMachineState *mms = MPS3R_MACHINE(machine);
233
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
234
+ MemoryRegion *sysmem = get_system_memory();
235
+
236
+ for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
237
+ MemoryRegion *mr = mr_for_raminfo(mms, ri);
238
+ memory_region_add_subregion(sysmem, ri->base, mr);
239
+ }
240
+}
241
+
242
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
243
+{
244
+ /*
245
+ * Set mc->default_ram_size and default_ram_id from the
246
+ * information in mmc->raminfo.
247
+ */
248
+ MachineClass *mc = MACHINE_CLASS(mmc);
249
+ const RAMInfo *p;
250
+
251
+ for (p = mmc->raminfo; p->name; p++) {
252
+ if (p->mrindex < 0) {
253
+ /* Found the entry for "system memory" */
254
+ mc->default_ram_size = p->size;
255
+ mc->default_ram_id = p->name;
256
+ return;
314
+ }
257
+ }
315
+ }
258
+ }
316
+ return val64;
259
+ g_assert_not_reached();
317
+}
260
+}
318
+
261
+
319
+static const RegisterAccessInfo crf_regs_info[] = {
262
+static void mps3r_class_init(ObjectClass *oc, void *data)
320
+ { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
263
+{
321
+ },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
264
+ MachineClass *mc = MACHINE_CLASS(oc);
322
+ .w1c = 0x1,
265
+
323
+ .post_write = ir_status_postw,
266
+ mc->init = mps3r_common_init;
324
+ },{ .name = "IR_MASK", .addr = A_IR_MASK,
267
+}
325
+ .reset = 0x1,
268
+
326
+ .ro = 0x1,
269
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
327
+ },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
270
+{
328
+ .pre_write = ir_enable_prew,
271
+ MachineClass *mc = MACHINE_CLASS(oc);
329
+ },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
272
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
330
+ .pre_write = ir_disable_prew,
273
+ static const char * const valid_cpu_types[] = {
331
+ },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT,
274
+ ARM_CPU_TYPE_NAME("cortex-r52"),
332
+ },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL,
275
+ NULL
333
+ .reset = 0x12c09,
276
+ };
334
+ .rsvd = 0xf88c80f6,
277
+
335
+ },{ .name = "APLL_CFG", .addr = A_APLL_CFG,
278
+ mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
336
+ .rsvd = 0x1801210,
279
+ mc->default_cpus = 2;
337
+ },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG,
280
+ mc->min_cpus = mc->default_cpus;
338
+ .rsvd = 0x7e330000,
281
+ mc->max_cpus = mc->default_cpus;
339
+ },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL,
282
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
340
+ .reset = 0x2c09,
283
+ mc->valid_cpu_types = valid_cpu_types;
341
+ .rsvd = 0xf88c80f6,
284
+ mmc->raminfo = an536_raminfo;
342
+ },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG,
285
+ mps3r_set_default_ram_info(mmc);
343
+ .rsvd = 0x1801210,
286
+}
344
+ },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG,
287
+
345
+ .rsvd = 0x7e330000,
288
+static const TypeInfo mps3r_machine_types[] = {
346
+ },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL,
289
+ {
347
+ .reset = 0x12809,
290
+ .name = TYPE_MPS3R_MACHINE,
348
+ .rsvd = 0xf88c80f6,
291
+ .parent = TYPE_MACHINE,
349
+ },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG,
292
+ .abstract = true,
350
+ .rsvd = 0x1801210,
293
+ .instance_size = sizeof(MPS3RMachineState),
351
+ },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG,
294
+ .class_size = sizeof(MPS3RMachineClass),
352
+ .rsvd = 0x7e330000,
295
+ .class_init = mps3r_class_init,
353
+ },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
296
+ }, {
354
+ .reset = 0x3f,
297
+ .name = TYPE_MPS3R_AN536_MACHINE,
355
+ .rsvd = 0xc0,
298
+ .parent = TYPE_MPS3R_MACHINE,
356
+ .ro = 0x3f,
299
+ .class_init = mps3r_an536_class_init,
357
+ },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL,
358
+ .reset = 0x400,
359
+ .rsvd = 0xc0ff,
360
+ },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL,
361
+ .reset = 0x400,
362
+ .rsvd = 0xc0ff,
363
+ },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL,
364
+ .reset = 0x400,
365
+ .rsvd = 0xc0ff,
366
+ },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL,
367
+ .reset = 0x3000400,
368
+ .rsvd = 0xfcffc0f8,
369
+ },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL,
370
+ .reset = 0x2500,
371
+ .rsvd = 0xfeffc0f8,
372
+ },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL,
373
+ .reset = 0x1002500,
374
+ .rsvd = 0xfeffc0f8,
375
+ },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL,
376
+ .reset = 0x1002300,
377
+ .rsvd = 0xfec0c0f8,
378
+ },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL,
379
+ .reset = 0x1032300,
380
+ .rsvd = 0xfec0c0f8,
381
+ },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL,
382
+ .reset = 0x1203200,
383
+ .rsvd = 0xfec0c0f8,
384
+ },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL,
385
+ .reset = 0x1000500,
386
+ .rsvd = 0xfeffc0f8,
387
+ },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL,
388
+ .reset = 0x1500,
389
+ .rsvd = 0xf8ffc0f8,
390
+ },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL,
391
+ .reset = 0x1001600,
392
+ .rsvd = 0xfeffc0f8,
393
+ },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL,
394
+ .reset = 0x1500,
395
+ .rsvd = 0xfeffc0f8,
396
+ },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL,
397
+ .reset = 0x1000500,
398
+ .rsvd = 0xfeffc0f8,
399
+ },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL,
400
+ .reset = 0x1000500,
401
+ .rsvd = 0xfeffc0f8,
402
+ },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL,
403
+ .reset = 0x1000400,
404
+ .rsvd = 0xfeffc0f8,
405
+ },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL,
406
+ .reset = 0x1000800,
407
+ .rsvd = 0xfeffc0f8,
408
+ },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
409
+ .reset = 0xa00,
410
+ .rsvd = 0xffffc0f8,
411
+ },
412
+ { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP,
413
+ .reset = 0xf9ffe,
414
+ .rsvd = 0xf06001,
415
+ },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU,
416
+ .reset = 0x3d0f,
417
+ .rsvd = 0xc2f0,
418
+ .pre_write = rst_fpd_apu_prew,
419
+ },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS,
420
+ .reset = 0xf,
421
+ .rsvd = 0xf3,
422
+ }
423
+};
424
+
425
+static void crf_reset_enter(Object *obj, ResetType type)
426
+{
427
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
428
+ unsigned int i;
429
+
430
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
431
+ register_reset(&s->regs_info[i]);
432
+ }
433
+}
434
+
435
+static void crf_reset_hold(Object *obj)
436
+{
437
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
438
+ ir_update_irq(s);
439
+}
440
+
441
+static const MemoryRegionOps crf_ops = {
442
+ .read = register_read_memory,
443
+ .write = register_write_memory,
444
+ .endianness = DEVICE_LITTLE_ENDIAN,
445
+ .valid = {
446
+ .min_access_size = 4,
447
+ .max_access_size = 4,
448
+ },
300
+ },
449
+};
301
+};
450
+
302
+
451
+static void crf_init(Object *obj)
303
+DEFINE_TYPES(mps3r_machine_types);
452
+{
304
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
453
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
454
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
455
+
456
+ s->reg_array =
457
+ register_init_block32(DEVICE(obj), crf_regs_info,
458
+ ARRAY_SIZE(crf_regs_info),
459
+ s->regs_info, s->regs,
460
+ &crf_ops,
461
+ XLNX_ZYNQMP_CRF_ERR_DEBUG,
462
+ CRF_R_MAX * 4);
463
+ sysbus_init_mmio(sbd, &s->reg_array->mem);
464
+ sysbus_init_irq(sbd, &s->irq_ir);
465
+}
466
+
467
+static void crf_finalize(Object *obj)
468
+{
469
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
470
+ register_finalize_block(s->reg_array);
471
+}
472
+
473
+static const VMStateDescription vmstate_crf = {
474
+ .name = TYPE_XLNX_ZYNQMP_CRF,
475
+ .version_id = 1,
476
+ .minimum_version_id = 1,
477
+ .fields = (VMStateField[]) {
478
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX),
479
+ VMSTATE_END_OF_LIST(),
480
+ }
481
+};
482
+
483
+static void crf_class_init(ObjectClass *klass, void *data)
484
+{
485
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
486
+ DeviceClass *dc = DEVICE_CLASS(klass);
487
+
488
+ dc->vmsd = &vmstate_crf;
489
+ rc->phases.enter = crf_reset_enter;
490
+ rc->phases.hold = crf_reset_hold;
491
+}
492
+
493
+static const TypeInfo crf_info = {
494
+ .name = TYPE_XLNX_ZYNQMP_CRF,
495
+ .parent = TYPE_SYS_BUS_DEVICE,
496
+ .instance_size = sizeof(XlnxZynqMPCRF),
497
+ .class_init = crf_class_init,
498
+ .instance_init = crf_init,
499
+ .instance_finalize = crf_finalize,
500
+};
501
+
502
+static void crf_register_types(void)
503
+{
504
+ type_register_static(&crf_info);
505
+}
506
+
507
+type_init(crf_register_types)
508
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
509
index XXXXXXX..XXXXXXX 100644
305
index XXXXXXX..XXXXXXX 100644
510
--- a/hw/misc/meson.build
306
--- a/hw/arm/Kconfig
511
+++ b/hw/misc/meson.build
307
+++ b/hw/arm/Kconfig
512
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
308
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
513
))
309
select PFLASH_CFI01
514
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
310
select SMC91C111
515
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
311
516
+specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
312
+config MPS3R
517
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
313
+ bool
518
'xlnx-versal-xramc.c',
314
+ default y
519
'xlnx-versal-pmc-iou-slcr.c',
315
+ depends on TCG && ARM
316
+
317
config MUSCA
318
bool
319
default y
320
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/arm/meson.build
323
+++ b/hw/arm/meson.build
324
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
325
arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
326
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
327
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
328
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
329
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
330
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
331
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
520
--
332
--
521
2.25.1
333
2.34.1
522
334
523
335
diff view generated by jsdifflib
[PULL 17/21] hw/misc: Add a model of the Xilinx ZynqMP APU Control
[PULL 31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
Create the CPUs, the GIC, and the per-CPU RAM block for
2
the mps3-an536 board.
2
3
3
Add a model of the Xilinx ZynqMP APU Control.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
6
---
7
hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
8
1 file changed, 177 insertions(+), 3 deletions(-)
4
9
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
10
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
index XXXXXXX..XXXXXXX 100644
7
Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com
12
--- a/hw/arm/mps3r.c
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
+++ b/hw/arm/mps3r.c
9
---
10
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 +++++++++
11
hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++++
12
hw/misc/meson.build | 1 +
13
3 files changed, 347 insertions(+)
14
create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
15
create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
16
17
diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
18
new file mode 100644
19
index XXXXXXX..XXXXXXX
20
--- /dev/null
21
+++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
22
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
15
#include "qemu/osdep.h"
16
#include "qemu/units.h"
17
#include "qapi/error.h"
18
+#include "qapi/qmp/qlist.h"
19
#include "exec/address-spaces.h"
20
#include "cpu.h"
21
#include "hw/boards.h"
22
+#include "hw/qdev-properties.h"
23
#include "hw/arm/boot.h"
24
+#include "hw/arm/bsa.h"
25
+#include "hw/intc/arm_gicv3.h"
26
27
/* Define the layout of RAM and ROM in a board */
28
typedef struct RAMInfo {
29
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
30
#define IS_ROM 2
31
32
#define MPS3R_RAM_MAX 9
33
+#define MPS3R_CPU_MAX 2
34
+
35
+#define PERIPHBASE 0xf0000000
36
+#define NUM_SPIS 96
37
38
typedef enum MPS3RFPGAType {
39
FPGA_AN536,
40
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
41
MachineClass parent;
42
MPS3RFPGAType fpga_type;
43
const RAMInfo *raminfo;
44
+ hwaddr loader_start;
45
};
46
47
struct MPS3RMachineState {
48
MachineState parent;
49
+ struct arm_boot_info bootinfo;
50
MemoryRegion ram[MPS3R_RAM_MAX];
51
+ Object *cpu[MPS3R_CPU_MAX];
52
+ MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
53
+ MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
54
+ MemoryRegion cpu_ram[MPS3R_CPU_MAX];
55
+ GICv3State gic;
56
};
57
58
#define TYPE_MPS3R_MACHINE "mps3r"
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
60
return ram;
61
}
62
23
+/*
63
+/*
24
+ * QEMU model of ZynqMP APU Control.
64
+ * There is no defined secondary boot protocol for Linux for the AN536,
65
+ * because real hardware has a restriction that atomic operations between
66
+ * the two CPUs do not function correctly, and so true SMP is not
67
+ * possible. Therefore for cases where the user is directly booting
68
+ * a kernel, we treat the system as essentially uniprocessor, and
69
+ * put the secondary CPU into power-off state (as if the user on the
70
+ * real hardware had configured the secondary to be halted via the
71
+ * SCC config registers).
25
+ *
72
+ *
26
+ * Copyright (c) 2013-2022 Xilinx Inc
73
+ * Note that the default secondary boot code would not work here anyway
27
+ * SPDX-License-Identifier: GPL-2.0-or-later
74
+ * as it assumes a GICv2, and we have a GICv3.
28
+ *
29
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
30
+ * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
31
+ *
32
+ */
75
+ */
33
+#ifndef HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
76
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
34
+#define HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
77
+ const struct arm_boot_info *info)
35
+
36
+#include "hw/sysbus.h"
37
+#include "hw/register.h"
38
+#include "target/arm/cpu.h"
39
+
40
+#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
41
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
42
+
43
+REG32(APU_ERR_CTRL, 0x0)
44
+ FIELD(APU_ERR_CTRL, PSLVERR, 0, 1)
45
+REG32(ISR, 0x10)
46
+ FIELD(ISR, INV_APB, 0, 1)
47
+REG32(IMR, 0x14)
48
+ FIELD(IMR, INV_APB, 0, 1)
49
+REG32(IEN, 0x18)
50
+ FIELD(IEN, INV_APB, 0, 1)
51
+REG32(IDS, 0x1c)
52
+ FIELD(IDS, INV_APB, 0, 1)
53
+REG32(CONFIG_0, 0x20)
54
+ FIELD(CONFIG_0, CFGTE, 24, 4)
55
+ FIELD(CONFIG_0, CFGEND, 16, 4)
56
+ FIELD(CONFIG_0, VINITHI, 8, 4)
57
+ FIELD(CONFIG_0, AA64NAA32, 0, 4)
58
+REG32(CONFIG_1, 0x24)
59
+ FIELD(CONFIG_1, L2RSTDISABLE, 29, 1)
60
+ FIELD(CONFIG_1, L1RSTDISABLE, 28, 1)
61
+ FIELD(CONFIG_1, CP15DISABLE, 0, 4)
62
+REG32(RVBARADDR0L, 0x40)
63
+ FIELD(RVBARADDR0L, ADDR, 2, 30)
64
+REG32(RVBARADDR0H, 0x44)
65
+ FIELD(RVBARADDR0H, ADDR, 0, 8)
66
+REG32(RVBARADDR1L, 0x48)
67
+ FIELD(RVBARADDR1L, ADDR, 2, 30)
68
+REG32(RVBARADDR1H, 0x4c)
69
+ FIELD(RVBARADDR1H, ADDR, 0, 8)
70
+REG32(RVBARADDR2L, 0x50)
71
+ FIELD(RVBARADDR2L, ADDR, 2, 30)
72
+REG32(RVBARADDR2H, 0x54)
73
+ FIELD(RVBARADDR2H, ADDR, 0, 8)
74
+REG32(RVBARADDR3L, 0x58)
75
+ FIELD(RVBARADDR3L, ADDR, 2, 30)
76
+REG32(RVBARADDR3H, 0x5c)
77
+ FIELD(RVBARADDR3H, ADDR, 0, 8)
78
+REG32(ACE_CTRL, 0x60)
79
+ FIELD(ACE_CTRL, AWQOS, 16, 4)
80
+ FIELD(ACE_CTRL, ARQOS, 0, 4)
81
+REG32(SNOOP_CTRL, 0x80)
82
+ FIELD(SNOOP_CTRL, ACE_INACT, 4, 1)
83
+ FIELD(SNOOP_CTRL, ACP_INACT, 0, 1)
84
+REG32(PWRCTL, 0x90)
85
+ FIELD(PWRCTL, CLREXMONREQ, 17, 1)
86
+ FIELD(PWRCTL, L2FLUSHREQ, 16, 1)
87
+ FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4)
88
+REG32(PWRSTAT, 0x94)
89
+ FIELD(PWRSTAT, CLREXMONACK, 17, 1)
90
+ FIELD(PWRSTAT, L2FLUSHDONE, 16, 1)
91
+ FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4)
92
+
93
+#define APU_R_MAX ((R_PWRSTAT) + 1)
94
+
95
+#define APU_MAX_CPU 4
96
+
97
+struct XlnxZynqMPAPUCtrl {
98
+ SysBusDevice busdev;
99
+
100
+ ARMCPU *cpus[APU_MAX_CPU];
101
+ /* WFIs towards PMU. */
102
+ qemu_irq wfi_out[4];
103
+ /* CPU Power status towards INTC Redirect. */
104
+ qemu_irq cpu_power_status[4];
105
+ qemu_irq irq_imr;
106
+
107
+ uint8_t cpu_pwrdwn_req;
108
+ uint8_t cpu_in_wfi;
109
+
110
+ RegisterInfoArray *reg_array;
111
+ uint32_t regs[APU_R_MAX];
112
+ RegisterInfo regs_info[APU_R_MAX];
113
+};
114
+
115
+#endif
116
diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c
117
new file mode 100644
118
index XXXXXXX..XXXXXXX
119
--- /dev/null
120
+++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c
121
@@ -XXX,XX +XXX,XX @@
122
+/*
123
+ * QEMU model of the ZynqMP APU Control.
124
+ *
125
+ * Copyright (c) 2013-2022 Xilinx Inc
126
+ * SPDX-License-Identifier: GPL-2.0-or-later
127
+ *
128
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
129
+ * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
130
+ */
131
+
132
+#include "qemu/osdep.h"
133
+#include "qapi/error.h"
134
+#include "qemu/log.h"
135
+#include "migration/vmstate.h"
136
+#include "hw/qdev-properties.h"
137
+#include "hw/sysbus.h"
138
+#include "hw/irq.h"
139
+#include "hw/register.h"
140
+
141
+#include "qemu/bitops.h"
142
+#include "qapi/qmp/qerror.h"
143
+
144
+#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
145
+
146
+#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG
147
+#define XILINX_ZYNQMP_APU_ERR_DEBUG 0
148
+#endif
149
+
150
+static void update_wfi_out(void *opaque)
151
+{
78
+{
152
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
79
+ /*
153
+ unsigned int i, wfi_pending;
80
+ * Power the secondary CPU off. This means we don't need to write any
154
+
81
+ * boot code into guest memory. Note that the 'cpu' argument to this
155
+ wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;
82
+ * function is the primary CPU we passed to arm_load_kernel(), not
156
+ for (i = 0; i < APU_MAX_CPU; i++) {
83
+ * the secondary. Loop around all the other CPUs, as the boot.c
157
+ qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));
84
+ * code does for the "disable secondaries if PSCI is enabled" case.
158
+ }
85
+ */
159
+}
86
+ for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
160
+
87
+ if (cs != first_cpu) {
161
+static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val)
88
+ object_property_set_bool(OBJECT(cs), "start-powered-off", true,
162
+{
89
+ &error_abort);
163
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
164
+ int i;
165
+
166
+ for (i = 0; i < APU_MAX_CPU; ++i) {
167
+ uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +
168
+ ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);
169
+ if (s->cpus[i]) {
170
+ object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,
171
+ &error_abort);
172
+ }
90
+ }
173
+ }
91
+ }
174
+}
92
+}
175
+
93
+
176
+static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
94
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
177
+{
96
+{
178
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
97
+ /* We don't need to do anything here because the CPU will be off */
179
+ unsigned int i, new;
98
+}
180
+
99
+
181
+ for (i = 0; i < APU_MAX_CPU; i++) {
100
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
182
+ new = val & (1 << i);
101
+{
183
+ /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */
102
+ MachineState *machine = MACHINE(mms);
184
+ if (new != (s->cpu_pwrdwn_req & (1 << i))) {
103
+ DeviceState *gicdev;
185
+ qemu_set_irq(s->cpu_power_status[i], !!new);
104
+ QList *redist_region_count;
105
+
106
+ object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
107
+ gicdev = DEVICE(&mms->gic);
108
+ qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
109
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
110
+ redist_region_count = qlist_new();
111
+ qlist_append_int(redist_region_count, machine->smp.cpus);
112
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
113
+ object_property_set_link(OBJECT(&mms->gic), "sysmem",
114
+ OBJECT(sysmem), &error_fatal);
115
+ sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
116
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
118
+ /*
119
+ * Wire the outputs from each CPU's generic timer and the GICv3
120
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
121
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
122
+ */
123
+ for (int i = 0; i < machine->smp.cpus; i++) {
124
+ DeviceState *cpudev = DEVICE(mms->cpu[i]);
125
+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
126
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
127
+ int irq;
128
+ /*
129
+ * Mapping from the output timer irq lines from the CPU to the
130
+ * GIC PPI inputs used for this board. This isn't a BSA board,
131
+ * but it uses the standard convention for the PPI numbers.
132
+ */
133
+ const int timer_irq[] = {
134
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
135
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
136
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
137
+ };
138
+
139
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
140
+ qdev_connect_gpio_out(cpudev, irq,
141
+ qdev_get_gpio_in(gicdev,
142
+ intidbase + timer_irq[irq]));
186
+ }
143
+ }
187
+ s->cpu_pwrdwn_req &= ~(1 << i);
144
+
188
+ s->cpu_pwrdwn_req |= new;
145
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
146
+ qdev_get_gpio_in(gicdev,
147
+ intidbase + ARCH_GIC_MAINT_IRQ));
148
+
149
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
150
+ qdev_get_gpio_in(gicdev,
151
+ intidbase + VIRTUAL_PMU_IRQ));
152
+
153
+ sysbus_connect_irq(gicsbd, i,
154
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
155
+ sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
156
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
157
+ sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
158
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
159
+ sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
160
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
189
+ }
161
+ }
190
+ update_wfi_out(s);
191
+}
162
+}
192
+
163
+
193
+static void imr_update_irq(XlnxZynqMPAPUCtrl *s)
164
static void mps3r_common_init(MachineState *machine)
194
+{
165
{
195
+ bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
166
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
196
+ qemu_set_irq(s->irq_imr, pending);
167
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
197
+}
168
MemoryRegion *mr = mr_for_raminfo(mms, ri);
198
+
169
memory_region_add_subregion(sysmem, ri->base, mr);
199
+static void isr_postw(RegisterInfo *reg, uint64_t val64)
170
}
200
+{
171
+
201
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
172
+ assert(machine->smp.cpus <= MPS3R_CPU_MAX);
202
+ imr_update_irq(s);
173
+ for (int i = 0; i < machine->smp.cpus; i++) {
203
+}
174
+ g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
204
+
175
+ g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
205
+static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64)
176
+ g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
206
+{
177
+
207
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
178
+ /*
208
+ uint32_t val = val64;
179
+ * Each CPU has some private RAM/peripherals, so create the container
209
+
180
+ * which will house those, with the whole-machine system memory being
210
+ s->regs[R_IMR] &= ~val;
181
+ * used where there's no CPU-specific device. Note that we need the
211
+ imr_update_irq(s);
182
+ * sysmem_alias aliases because we can't put one MR (the original
212
+ return 0;
183
+ * 'sysmem') into more than one other MR.
213
+}
184
+ */
214
+
185
+ memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
215
+static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64)
186
+ sysmem_name, UINT64_MAX);
216
+{
187
+ memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
217
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
188
+ alias_name, sysmem, 0, UINT64_MAX);
218
+ uint32_t val = val64;
189
+ memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
219
+
190
+ &mms->sysmem_alias[i], -1);
220
+ s->regs[R_IMR] |= val;
191
+
221
+ imr_update_irq(s);
192
+ mms->cpu[i] = object_new(machine->cpu_type);
222
+ return 0;
193
+ object_property_set_link(mms->cpu[i], "memory",
223
+}
194
+ OBJECT(&mms->cpu_sysmem[i]), &error_abort);
224
+
195
+ object_property_set_int(mms->cpu[i], "reset-cbar",
225
+static const RegisterAccessInfo zynqmp_apu_regs_info[] = {
196
+ PERIPHBASE, &error_abort);
226
+#define RVBAR_REGDEF(n) \
197
+ qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
227
+ { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \
198
+ object_unref(mms->cpu[i]);
228
+ .reset = 0xffff0000ul, \
199
+
229
+ .post_write = zynqmp_apu_rvbar_post_write, \
200
+ /* Per-CPU RAM */
230
+ },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \
201
+ memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
231
+ .post_write = zynqmp_apu_rvbar_post_write, \
202
+ 0x1000, &error_fatal);
203
+ memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
204
+ &mms->cpu_ram[i]);
232
+ }
205
+ }
233
+ { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL,
206
+
234
+ },{ .name = "ISR", .addr = A_ISR,
207
+ create_gic(mms, sysmem);
235
+ .w1c = 0x1,
208
+
236
+ .post_write = isr_postw,
209
+ mms->bootinfo.ram_size = machine->ram_size;
237
+ },{ .name = "IMR", .addr = A_IMR,
210
+ mms->bootinfo.board_id = -1;
238
+ .reset = 0x1,
211
+ mms->bootinfo.loader_start = mmc->loader_start;
239
+ .ro = 0x1,
212
+ mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
240
+ },{ .name = "IEN", .addr = A_IEN,
213
+ mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
241
+ .pre_write = ien_prew,
214
+ arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
242
+ },{ .name = "IDS", .addr = A_IDS,
215
}
243
+ .pre_write = ids_prew,
216
244
+ },{ .name = "CONFIG_0", .addr = A_CONFIG_0,
217
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
245
+ .reset = 0xf0f,
218
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
246
+ },{ .name = "CONFIG_1", .addr = A_CONFIG_1,
219
/* Found the entry for "system memory" */
247
+ },
220
mc->default_ram_size = p->size;
248
+ RVBAR_REGDEF(0),
221
mc->default_ram_id = p->name;
249
+ RVBAR_REGDEF(1),
222
+ mmc->loader_start = p->base;
250
+ RVBAR_REGDEF(2),
223
return;
251
+ RVBAR_REGDEF(3),
224
}
252
+ { .name = "ACE_CTRL", .addr = A_ACE_CTRL,
225
}
253
+ .reset = 0xf000f,
226
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
254
+ },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL,
227
};
255
+ },{ .name = "PWRCTL", .addr = A_PWRCTL,
228
256
+ .post_write = zynqmp_apu_pwrctl_post_write,
229
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
257
+ },{ .name = "PWRSTAT", .addr = A_PWRSTAT,
230
- mc->default_cpus = 2;
258
+ .ro = 0x3000f,
231
- mc->min_cpus = mc->default_cpus;
259
+ }
232
- mc->max_cpus = mc->default_cpus;
260
+};
233
+ /*
261
+
234
+ * In the real FPGA image there are always two cores, but the standard
262
+static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
235
+ * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
263
+{
236
+ * that the second core is held in reset and halted. Many images built for
264
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
237
+ * the board do not expect the second core to run at startup (especially
265
+ int i;
238
+ * since on the real FPGA image it is not possible to use LDREX/STREX
266
+
239
+ * in RAM between the two cores, so a true SMP setup isn't supported).
267
+ for (i = 0; i < APU_R_MAX; ++i) {
240
+ *
268
+ register_reset(&s->regs_info[i]);
241
+ * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
269
+ }
242
+ * with the default being -smp 1. This seems a more intuitive UI for
270
+
243
+ * QEMU users than, for instance, having a machine property to allow
271
+ s->cpu_pwrdwn_req = 0;
244
+ * the user to set the initial value of the SYSCON 0x000 register.
272
+ s->cpu_in_wfi = 0;
245
+ */
273
+}
246
+ mc->default_cpus = 1;
274
+
247
+ mc->min_cpus = 1;
275
+static void zynqmp_apu_reset_hold(Object *obj)
248
+ mc->max_cpus = 2;
276
+{
249
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
277
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
250
mc->valid_cpu_types = valid_cpu_types;
278
+
251
mmc->raminfo = an536_raminfo;
279
+ update_wfi_out(s);
280
+ imr_update_irq(s);
281
+}
282
+
283
+static const MemoryRegionOps zynqmp_apu_ops = {
284
+ .read = register_read_memory,
285
+ .write = register_write_memory,
286
+ .endianness = DEVICE_LITTLE_ENDIAN,
287
+ .valid = {
288
+ .min_access_size = 4,
289
+ .max_access_size = 4,
290
+ }
291
+};
292
+
293
+static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
294
+{
295
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
296
+
297
+ s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);
298
+ update_wfi_out(s);
299
+}
300
+
301
+static void zynqmp_apu_init(Object *obj)
302
+{
303
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
304
+ int i;
305
+
306
+ s->reg_array =
307
+ register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
308
+ ARRAY_SIZE(zynqmp_apu_regs_info),
309
+ s->regs_info, s->regs,
310
+ &zynqmp_apu_ops,
311
+ XILINX_ZYNQMP_APU_ERR_DEBUG,
312
+ APU_R_MAX * 4);
313
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);
314
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
315
+
316
+ for (i = 0; i < APU_MAX_CPU; ++i) {
317
+ g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i);
318
+ object_property_add_link(obj, prop_name, TYPE_ARM_CPU,
319
+ (Object **)&s->cpus[i],
320
+ qdev_prop_allow_set_link_before_realize,
321
+ OBJ_PROP_LINK_STRONG);
322
+ }
323
+
324
+ /* wfi_out is used to connect to PMU GPIs. */
325
+ qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
326
+ /* CPU_POWER_STATUS is used to connect to INTC redirect. */
327
+ qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
328
+ "CPU_POWER_STATUS", 4);
329
+ /* wfi_in is used as input from CPUs as wfi request. */
330
+ qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
331
+}
332
+
333
+static void zynqmp_apu_finalize(Object *obj)
334
+{
335
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
336
+ register_finalize_block(s->reg_array);
337
+}
338
+
339
+static const VMStateDescription vmstate_zynqmp_apu = {
340
+ .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
341
+ .version_id = 1,
342
+ .minimum_version_id = 1,
343
+ .fields = (VMStateField[]) {
344
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX),
345
+ VMSTATE_END_OF_LIST(),
346
+ }
347
+};
348
+
349
+static void zynqmp_apu_class_init(ObjectClass *klass, void *data)
350
+{
351
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
352
+ DeviceClass *dc = DEVICE_CLASS(klass);
353
+
354
+ dc->vmsd = &vmstate_zynqmp_apu;
355
+
356
+ rc->phases.enter = zynqmp_apu_reset_enter;
357
+ rc->phases.hold = zynqmp_apu_reset_hold;
358
+}
359
+
360
+static const TypeInfo zynqmp_apu_info = {
361
+ .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
362
+ .parent = TYPE_SYS_BUS_DEVICE,
363
+ .instance_size = sizeof(XlnxZynqMPAPUCtrl),
364
+ .class_init = zynqmp_apu_class_init,
365
+ .instance_init = zynqmp_apu_init,
366
+ .instance_finalize = zynqmp_apu_finalize,
367
+};
368
+
369
+static void zynqmp_apu_register_types(void)
370
+{
371
+ type_register_static(&zynqmp_apu_info);
372
+}
373
+
374
+type_init(zynqmp_apu_register_types)
375
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
376
index XXXXXXX..XXXXXXX 100644
377
--- a/hw/misc/meson.build
378
+++ b/hw/misc/meson.build
379
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
380
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
381
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
382
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
383
+specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
384
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
385
'xlnx-versal-xramc.c',
386
'xlnx-versal-pmc-iou-slcr.c',
387
--
252
--
388
2.25.1
253
2.34.1
diff view generated by jsdifflib
[PULL 16/21] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
[PULL 32/35] hw/arm/mps3r: Add UARTs
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
This board has a lot of UARTs: there is one UART per CPU in the
2
per-CPU peripheral part of the address map, whose interrupts are
3
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
4
normal part of the peripheral space, whose interrupts are shared
5
peripheral interrupts.
2
6
3
Connect the ZynqMP CRF - Clock Reset FPD device.
7
Connect and wire them all up; this involves some OR gates where
8
multiple overflow interrupts are wired into one GIC input.
4
9
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Message-id: 20220316164645.2303510-5-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
11
---
13
---
12
include/hw/arm/xlnx-zynqmp.h | 2 ++
14
hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
13
hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
15
1 file changed, 94 insertions(+)
14
2 files changed, 18 insertions(+)
15
16
16
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
17
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-zynqmp.h
19
--- a/hw/arm/mps3r.c
19
+++ b/include/hw/arm/xlnx-zynqmp.h
20
+++ b/hw/arm/mps3r.c
20
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
21
#include "hw/nvram/xlnx-bbram.h"
22
#include "qapi/qmp/qlist.h"
22
#include "hw/nvram/xlnx-zynqmp-efuse.h"
23
#include "exec/address-spaces.h"
23
#include "hw/or-irq.h"
24
#include "cpu.h"
24
+#include "hw/misc/xlnx-zynqmp-crf.h"
25
+#include "sysemu/sysemu.h"
25
26
#include "hw/boards.h"
26
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
27
+#include "hw/or-irq.h"
27
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
28
#include "hw/qdev-properties.h"
28
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
29
#include "hw/arm/boot.h"
29
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
30
#include "hw/arm/bsa.h"
30
XlnxCSUDMA qspi_dma;
31
+#include "hw/char/cmsdk-apb-uart.h"
31
qemu_or_irq qspi_irq_orgate;
32
#include "hw/intc/arm_gicv3.h"
32
+ XlnxZynqMPCRF crf;
33
33
34
/* Define the layout of RAM and ROM in a board */
34
char *boot_cpu;
35
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
35
ARMCPU *boot_cpu_ptr;
36
36
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
37
#define MPS3R_RAM_MAX 9
37
index XXXXXXX..XXXXXXX 100644
38
#define MPS3R_CPU_MAX 2
38
--- a/hw/arm/xlnx-zynqmp.c
39
+#define MPS3R_UART_MAX 4 /* shared UART count */
39
+++ b/hw/arm/xlnx-zynqmp.c
40
40
@@ -XXX,XX +XXX,XX @@
41
#define PERIPHBASE 0xf0000000
41
#define QSPI_DMA_ADDR 0xff0f0800
42
#define NUM_SPIS 96
42
#define NUM_QSPI_IRQ_LINES 2
43
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
43
44
MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
44
+#define CRF_ADDR 0xfd1a0000
45
MemoryRegion cpu_ram[MPS3R_CPU_MAX];
45
+#define CRF_IRQ 120
46
GICv3State gic;
47
+ /* per-CPU UARTs followed by the shared UARTs */
48
+ CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
49
+ OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
50
+ OrIRQState uart_oflow;
51
};
52
53
#define TYPE_MPS3R_MACHINE "mps3r"
54
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
55
56
OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
57
58
+/*
59
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
60
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
61
+ * model we just roll them all into one.
62
+ */
63
+#define CLK_FRQ 50000000
46
+
64
+
47
/* Serializer/Deserializer. */
65
static const RAMInfo an536_raminfo[] = {
48
#define SERDES_ADDR 0xfd400000
66
{
49
#define SERDES_SIZE 0x20000
67
.name = "ATCM",
50
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
68
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
51
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
69
}
52
}
70
}
53
71
54
+static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
72
+/*
73
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
74
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
75
+ */
76
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
77
+ hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
78
+ qemu_irq txoverirq, qemu_irq rxoverirq,
79
+ qemu_irq combirq)
55
+{
80
+{
81
+ g_autofree char *s = g_strdup_printf("uart%d", uartno);
56
+ SysBusDevice *sbd;
82
+ SysBusDevice *sbd;
57
+
83
+
58
+ object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
84
+ assert(uartno < ARRAY_SIZE(mms->uart));
59
+ sbd = SYS_BUS_DEVICE(&s->crf);
85
+ object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
60
+
86
+ TYPE_CMSDK_APB_UART);
87
+ qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
88
+ qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
89
+ sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
61
+ sysbus_realize(sbd, &error_fatal);
90
+ sysbus_realize(sbd, &error_fatal);
62
+ sysbus_mmio_map(sbd, 0, CRF_ADDR);
91
+ memory_region_add_subregion(mem, baseaddr,
63
+ sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
92
+ sysbus_mmio_get_region(sbd, 0));
93
+ sysbus_connect_irq(sbd, 0, txirq);
94
+ sysbus_connect_irq(sbd, 1, rxirq);
95
+ sysbus_connect_irq(sbd, 2, txoverirq);
96
+ sysbus_connect_irq(sbd, 3, rxoverirq);
97
+ sysbus_connect_irq(sbd, 4, combirq);
64
+}
98
+}
65
+
99
+
66
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
100
static void mps3r_common_init(MachineState *machine)
67
{
101
{
68
static const struct UnimpInfo {
102
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
69
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
103
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
70
104
MemoryRegion *sysmem = get_system_memory();
71
xlnx_zynqmp_create_bbram(s, gic_spi);
105
+ DeviceState *gicdev;
72
xlnx_zynqmp_create_efuse(s, gic_spi);
106
73
+ xlnx_zynqmp_create_crf(s, gic_spi);
107
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
74
xlnx_zynqmp_create_unimp_mmio(s);
108
MemoryRegion *mr = mr_for_raminfo(mms, ri);
75
109
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
76
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
110
}
111
112
create_gic(mms, sysmem);
113
+ gicdev = DEVICE(&mms->gic);
114
+
115
+ /*
116
+ * UARTs 0 and 1 are per-CPU; their interrupts are wired to
117
+ * the relevant CPU's PPI 0..3, aka INTID 16..19
118
+ */
119
+ for (int i = 0; i < machine->smp.cpus; i++) {
120
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
121
+ g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
122
+ DeviceState *orgate;
123
+
124
+ /* The two overflow IRQs from the UART are ORed together into PPI 3 */
125
+ object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
126
+ TYPE_OR_IRQ);
127
+ orgate = DEVICE(&mms->cpu_uart_oflow[i]);
128
+ qdev_prop_set_uint32(orgate, "num-lines", 2);
129
+ qdev_realize(orgate, NULL, &error_fatal);
130
+ qdev_connect_gpio_out(orgate, 0,
131
+ qdev_get_gpio_in(gicdev, intidbase + 19));
132
+
133
+ create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
134
+ qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
135
+ qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
136
+ qdev_get_gpio_in(orgate, 0), /* txover */
137
+ qdev_get_gpio_in(orgate, 1), /* rxover */
138
+ qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
139
+ }
140
+ /*
141
+ * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
142
+ * together into IRQ 17
143
+ */
144
+ object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
145
+ &mms->uart_oflow, TYPE_OR_IRQ);
146
+ qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
147
+ MPS3R_UART_MAX * 2);
148
+ qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
149
+ qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
150
+ qdev_get_gpio_in(gicdev, 17));
151
+
152
+ for (int i = 0; i < MPS3R_UART_MAX; i++) {
153
+ hwaddr baseaddr = 0xe0205000 + i * 0x1000;
154
+ int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
155
+
156
+ create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
157
+ qdev_get_gpio_in(gicdev, txirq),
158
+ qdev_get_gpio_in(gicdev, rxirq),
159
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
160
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
161
+ qdev_get_gpio_in(gicdev, combirq));
162
+ }
163
164
mms->bootinfo.ram_size = machine->ram_size;
165
mms->bootinfo.board_id = -1;
77
--
166
--
78
2.25.1
167
2.34.1
79
168
80
169
diff view generated by jsdifflib
[PULL 08/21] nsis installer: Fix mouse-over descriptions for emulators
[PULL 33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
1
We use the nsis.py script to write out an installer script Section
1
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
2
for each emulator executable, so the exact set of Sections depends on
2
board. These are all simple devices that just need to be created and
3
which executables were built. However the part of qemu.nsi which
3
wired up.
4
specifies mouse-over descriptions for each Section still has a
5
hard-coded and very outdated list (with just i386 and alpha). This
6
causes two problems. Firstly, if you build the installer for a
7
configuration where you didn't build the i386 binaries you get
8
warnings like this:
9
warning 6000: unknown variable/constant "{Section_i386}" detected, ignoring (macro:_==:1)
10
warning 6000: unknown variable/constant "{Section_i386w}" detected, ignoring (macro:_==:1)
11
(this happens in our gitlab CI jobs, for instance).
12
Secondly, most of the emulators in the generated installer don't have
13
any mouseover text.
14
15
Make nsis.py generate a second output file which has the necessary
16
MUI_DESCRIPTION_TEXT lines for each Section it creates, so we can
17
include that at the right point in qemu.nsi to set the mouse-over
18
text.
19
4
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
22
Reviewed-by: John Snow <jsnow@redhat.com>
7
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
23
Message-id: 20220305105743.2384766-4-peter.maydell@linaro.org
24
---
8
---
25
qemu.nsi | 5 +----
9
hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
26
scripts/nsis.py | 13 ++++++++++++-
10
1 file changed, 59 insertions(+)
27
2 files changed, 13 insertions(+), 5 deletions(-)
28
11
29
diff --git a/qemu.nsi b/qemu.nsi
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
30
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
31
--- a/qemu.nsi
14
--- a/hw/arm/mps3r.c
32
+++ b/qemu.nsi
15
+++ b/hw/arm/mps3r.c
33
@@ -XXX,XX +XXX,XX @@ SectionEnd
16
@@ -XXX,XX +XXX,XX @@
34
; Descriptions (mouse-over).
17
#include "sysemu/sysemu.h"
35
!insertmacro MUI_FUNCTION_DESCRIPTION_BEGIN
18
#include "hw/boards.h"
36
!insertmacro MUI_DESCRIPTION_TEXT ${SectionSystem} "System emulation."
19
#include "hw/or-irq.h"
37
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_alpha} "Alpha system emulation."
20
+#include "hw/qdev-clock.h"
38
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_alphaw} "Alpha system emulation (GUI)."
21
#include "hw/qdev-properties.h"
39
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386} "PC i386 system emulation."
22
#include "hw/arm/boot.h"
40
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386w} "PC i386 system emulation (GUI)."
23
#include "hw/arm/bsa.h"
41
+!include "${BINDIR}\system-mui-text.nsh"
24
#include "hw/char/cmsdk-apb-uart.h"
42
!insertmacro MUI_DESCRIPTION_TEXT ${SectionTools} "Tools."
25
+#include "hw/i2c/arm_sbcon_i2c.h"
43
!ifdef DLLDIR
26
#include "hw/intc/arm_gicv3.h"
44
!insertmacro MUI_DESCRIPTION_TEXT ${SectionDll} "Runtime Libraries (DLL)."
27
+#include "hw/misc/unimp.h"
45
diff --git a/scripts/nsis.py b/scripts/nsis.py
28
+#include "hw/timer/cmsdk-apb-dualtimer.h"
46
index XXXXXXX..XXXXXXX 100644
29
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
47
--- a/scripts/nsis.py
30
48
+++ b/scripts/nsis.py
31
/* Define the layout of RAM and ROM in a board */
49
@@ -XXX,XX +XXX,XX @@ def main():
32
typedef struct RAMInfo {
50
subprocess.run(["make", "install", "DESTDIR=" + destdir + os.path.sep])
33
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
51
with open(
34
CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
52
os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w"
35
OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
53
- ) as nsh:
36
OrIRQState uart_oflow;
54
+ ) as nsh, open(
37
+ CMSDKAPBWatchdog watchdog;
55
+ os.path.join(destdir + args.prefix, "system-mui-text.nsh"), "w"
38
+ CMSDKAPBDualTimer dualtimer;
56
+ ) as muinsh:
39
+ ArmSbconI2CState i2c[5];
57
for exe in sorted(glob.glob(
40
+ Clock *clk;
58
os.path.join(destdir + args.prefix, "qemu-system-*.exe")
41
};
59
)):
42
60
@@ -XXX,XX +XXX,XX @@ def main():
43
#define TYPE_MPS3R_MACHINE "mps3r"
61
arch, exe
44
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
62
)
45
MemoryRegion *sysmem = get_system_memory();
63
)
46
DeviceState *gicdev;
64
+ if arch.endswith('w'):
47
65
+ desc = arch[:-1] + " emulation (GUI)."
48
+ mms->clk = clock_new(OBJECT(machine), "CLK");
66
+ else:
49
+ clock_set_hz(mms->clk, CLK_FRQ);
67
+ desc = arch + " emulation."
68
+
50
+
69
+ muinsh.write(
51
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
70
+ """
52
MemoryRegion *mr = mr_for_raminfo(mms, ri);
71
+ !insertmacro MUI_DESCRIPTION_TEXT ${{Section_{0}}} "{1}"
53
memory_region_add_subregion(sysmem, ri->base, mr);
72
+ """.format(arch, desc))
54
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
73
55
qdev_get_gpio_in(gicdev, combirq));
74
for exe in glob.glob(os.path.join(destdir + args.prefix, "*.exe")):
56
}
75
signcode(exe)
57
58
+ for (int i = 0; i < 4; i++) {
59
+ /* CMSDK GPIO controllers */
60
+ g_autofree char *s = g_strdup_printf("gpio%d", i);
61
+ create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
62
+ }
63
+
64
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
65
+ TYPE_CMSDK_APB_WATCHDOG);
66
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
67
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
68
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
69
+ qdev_get_gpio_in(gicdev, 0));
70
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
71
+
72
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
73
+ TYPE_CMSDK_APB_DUALTIMER);
74
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
76
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
77
+ qdev_get_gpio_in(gicdev, 3));
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
79
+ qdev_get_gpio_in(gicdev, 1));
80
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
81
+ qdev_get_gpio_in(gicdev, 2));
82
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
83
+
84
+ for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
85
+ static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
86
+ 0xe0103000, /* Audio */
87
+ 0xe0107000, /* Shield0 */
88
+ 0xe0108000, /* Shield1 */
89
+ 0xe0109000}; /* DDR4 EEPROM */
90
+ g_autofree char *s = g_strdup_printf("i2c%d", i);
91
+
92
+ object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
93
+ TYPE_ARM_SBCON_I2C);
94
+ sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
95
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
96
+ if (i != 2 && i != 3) {
97
+ /*
98
+ * internal-only bus: mark it full to avoid user-created
99
+ * i2c devices being plugged into it.
100
+ */
101
+ qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
102
+ }
103
+ }
104
+
105
mms->bootinfo.ram_size = machine->ram_size;
106
mms->bootinfo.board_id = -1;
107
mms->bootinfo.loader_start = mmc->loader_start;
76
--
108
--
77
2.25.1
109
2.34.1
78
110
79
111
diff view generated by jsdifflib
[PULL 07/21] nsis installer: Suppress "ANSI targets are deprecated" warning
[PULL 34/35] hw/arm/mps3r: Add remaining devices
1
When we build our Windows installer, it emits the warning:
1
Add the remaining devices (or unimplemented-device stubs) for
2
2
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
3
warning 7998: ANSI targets are deprecated
3
QSPI write-config block, and ethernet.
4
5
Fix this by making our installer a Unicode installer instead. These
6
won't work on Win95/98/ME, but we already do not support those.
7
8
See
9
https://nsis.sourceforge.io/Docs/Chapter4.html#aunicodetarget
10
for the documentation of the Unicode directive.
11
4
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Stefan Weil <sw@weilnetz.de>
7
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
15
Message-id: 20220305105743.2384766-3-peter.maydell@linaro.org
16
---
8
---
17
qemu.nsi | 3 +++
9
hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
18
1 file changed, 3 insertions(+)
10
1 file changed, 74 insertions(+)
19
11
20
diff --git a/qemu.nsi b/qemu.nsi
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/qemu.nsi
14
--- a/hw/arm/mps3r.c
23
+++ b/qemu.nsi
15
+++ b/hw/arm/mps3r.c
24
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@
25
!define OUTFILE "qemu-setup.exe"
17
#include "hw/char/cmsdk-apb-uart.h"
26
!endif
18
#include "hw/i2c/arm_sbcon_i2c.h"
27
19
#include "hw/intc/arm_gicv3.h"
28
+; Build a unicode installer
20
+#include "hw/misc/mps2-scc.h"
29
+Unicode true
21
+#include "hw/misc/mps2-fpgaio.h"
22
#include "hw/misc/unimp.h"
23
+#include "hw/net/lan9118.h"
24
+#include "hw/rtc/pl031.h"
25
+#include "hw/ssi/pl022.h"
26
#include "hw/timer/cmsdk-apb-dualtimer.h"
27
#include "hw/watchdog/cmsdk-apb-watchdog.h"
28
29
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
30
CMSDKAPBWatchdog watchdog;
31
CMSDKAPBDualTimer dualtimer;
32
ArmSbconI2CState i2c[5];
33
+ PL022State spi[3];
34
+ MPS2SCC scc;
35
+ MPS2FPGAIO fpgaio;
36
+ UnimplementedDeviceState i2s_audio;
37
+ PL031State rtc;
38
Clock *clk;
39
};
40
41
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
42
}
43
};
44
45
+static const int an536_oscclk[] = {
46
+ 24000000, /* 24MHz reference for RTC and timers */
47
+ 50000000, /* 50MHz ACLK */
48
+ 50000000, /* 50MHz MCLK */
49
+ 50000000, /* 50MHz GPUCLK */
50
+ 24576000, /* 24.576MHz AUDCLK */
51
+ 23750000, /* 23.75MHz HDLCDCLK */
52
+ 100000000, /* 100MHz DDR4_REF_CLK */
53
+};
30
+
54
+
31
; Use maximum compression.
55
static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
32
SetCompressor /SOLID lzma
56
const RAMInfo *raminfo)
33
57
{
58
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
59
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
60
MemoryRegion *sysmem = get_system_memory();
61
DeviceState *gicdev;
62
+ QList *oscclk;
63
64
mms->clk = clock_new(OBJECT(machine), "CLK");
65
clock_set_hz(mms->clk, CLK_FRQ);
66
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
67
}
68
}
69
70
+ for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
71
+ g_autofree char *s = g_strdup_printf("spi%d", i);
72
+ hwaddr baseaddr = 0xe0104000 + i * 0x1000;
73
+
74
+ object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
77
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
78
+ qdev_get_gpio_in(gicdev, 22 + i));
79
+ }
80
+
81
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
82
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
83
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
84
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
85
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
86
+ oscclk = qlist_new();
87
+ for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
88
+ qlist_append_int(oscclk, an536_oscclk[i]);
89
+ }
90
+ qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
91
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
92
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
93
+
94
+ create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
95
+
96
+ object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
97
+ TYPE_MPS2_FPGAIO);
98
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
99
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
100
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
101
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
102
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
104
+
105
+ create_unimplemented_device("clcd", 0xe0209000, 0x1000);
106
+
107
+ object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
108
+ sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
109
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
110
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
111
+ qdev_get_gpio_in(gicdev, 4));
112
+
113
+ /*
114
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
115
+ * except that it doesn't support the checksum-offload feature.
116
+ */
117
+ lan9118_init(0xe0300000,
118
+ qdev_get_gpio_in(gicdev, 18));
119
+
120
+ create_unimplemented_device("usb", 0xe0301000, 0x1000);
121
+ create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
122
+
123
mms->bootinfo.ram_size = machine->ram_size;
124
mms->bootinfo.board_id = -1;
125
mms->bootinfo.loader_start = mmc->loader_start;
34
--
126
--
35
2.25.1
127
2.34.1
36
128
37
129
diff view generated by jsdifflib
[PULL 06/21] nsis installer: List emulators in alphabetical order
[PULL 35/35] docs: Add documentation for the mps3-an536 board
1
We currently list the emulators in the Windows installer's dialog
1
Add documentation for the mps3-an536 board type.
2
in an essentially random order (it's whatever glob.glob() returns
3
them to, which is filesystem-implementation-dependent). Add a
4
call to sorted() so they appear in alphabetical order.
5
2
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Stefan Weil <sw@weilnetz.de>
5
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
9
Reviewed-by: John Snow <jsnow@redhat.com>
10
Message-id: 20220305105743.2384766-2-peter.maydell@linaro.org
11
---
6
---
12
scripts/nsis.py | 4 ++--
7
docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
13
1 file changed, 2 insertions(+), 2 deletions(-)
8
1 file changed, 34 insertions(+), 3 deletions(-)
14
9
15
diff --git a/scripts/nsis.py b/scripts/nsis.py
10
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/scripts/nsis.py
12
--- a/docs/system/arm/mps2.rst
18
+++ b/scripts/nsis.py
13
+++ b/docs/system/arm/mps2.rst
19
@@ -XXX,XX +XXX,XX @@ def main():
14
@@ -XXX,XX +XXX,XX @@
20
with open(
15
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
21
os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w"
16
-=========================================================================================================================================================
22
) as nsh:
17
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
23
- for exe in glob.glob(
18
+=========================================================================================================================================================================
24
+ for exe in sorted(glob.glob(
19
25
os.path.join(destdir + args.prefix, "qemu-system-*.exe")
20
-These board models all use Arm M-profile CPUs.
26
- ):
21
+These board models use Arm M-profile or R-profile CPUs.
27
+ )):
22
28
exe = os.path.basename(exe)
23
The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
29
arch = exe[12:-4]
24
bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
30
nsh.write(
25
@@ -XXX,XX +XXX,XX @@ FPGA image.
26
27
QEMU models the following FPGA images:
28
29
+FPGA images using M-profile CPUs:
30
+
31
``mps2-an385``
32
Cortex-M3 as documented in Arm Application Note AN385
33
``mps2-an386``
34
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
35
``mps3-an547``
36
Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
37
38
+FPGA images using R-profile CPUs:
39
+
40
+``mps3-an536``
41
+ Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
42
+
43
Differences between QEMU and real hardware:
44
45
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
46
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
47
flash, but only as simple ROM, so attempting to rewrite the flash
48
from the guest will fail
49
- QEMU does not model the USB controller in MPS3 boards
50
+- AN536 does not support runtime control of CPU reset and halt via
51
+ the SCC CFG_REG0 register.
52
+- AN536 does not support enabling or disabling the flash and ATCM
53
+ interfaces via the SCC CFG_REG1 register.
54
+- AN536 does not support setting of the initial vector table
55
+ base address via the SCC CFG_REG6 and CFG_REG7 register config,
56
+ and does not provide a mechanism for specifying these values at
57
+ startup, so all guest images must be built to start from TCM
58
+ (i.e. to expect the interrupt vector base at 0 from reset).
59
+- AN536 defaults to only creating a single CPU; this is the equivalent
60
+ of the way the real FPGA image usually runs with the second Cortex-R52
61
+ held in halt via the initial SCC CFG_REG0 register setting. You can
62
+ create the second CPU with ``-smp 2``; both CPUs will then start
63
+ execution immediately on startup.
64
+
65
+Note that for the AN536 the first UART is accessible only by
66
+CPU0, and the second UART is accessible only by CPU1. The
67
+first UART accessible shared between both CPUs is the third
68
+UART. Guest software might therefore be built to use either
69
+the first UART or the third UART; if you don't see any output
70
+from the UART you are looking at, try one of the others.
71
+(Even if the AN536 machine is started with a single CPU and so
72
+no "CPU1-only UART", the UART numbering remains the same,
73
+with the third UART being the first of the shared ones.)
74
75
Machine-specific options
76
""""""""""""""""""""""""
31
--
77
--
32
2.25.1
78
2.34.1
33
79
34
80
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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