[PULL 0/4] tcg patch queue
[PULL v3 00/28] tcg patch queue
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The following changes since commit 15df33ceb73cb6bb3c6736cf4d2cff51129ed4b4:
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v3: One more try to fix macos issues.
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Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20220312-1' into staging (2022-03-13 17:29:18 +0000)
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r~
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The following changes since commit e0209297cddd5e10a07e15fac5cca7aa1a8e0e59:
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Merge tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu into staging (2025-02-18 10:58:48 +0800)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220314
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-3
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for you to fetch changes up to 76cff100beeae8d3676bb658cccd45ef5ced8aa9:
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for you to fetch changes up to e726f65867087d86436de05e9f372a86ec1381a6:
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tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 (2022-03-14 10:31:51 -0700)
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-18 08:29:03 -0800)
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----------------------------------------------------------------
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----------------------------------------------------------------
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Fixes for s390x host vectors
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tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
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Fix for arm ldrd unpredictable case
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tcg: Cleanups after disallowing 64-on-32
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tcg: Introduce constraint for zero register
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
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tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
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linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
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linux-user: Fix alignment when unmapping excess reservation
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target/sparc: Fix register selection for all F*TOx and FxTO* instructions
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target/sparc: Fix gdbstub incorrectly handling registers f32-f62
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target/sparc: fake UltraSPARC T1 PCR and PIC registers
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (4):
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Andreas Schwab (1):
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tcg/s390x: Fix tcg_out_dupi_vec vs VGM
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linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
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tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
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tcg/s390x: Fix tcg_out_dup_vec vs general registers
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tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
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tcg/arm/tcg-target.c.inc | 17 +++++++++++++++--
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Artyom Tarasenko (1):
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tcg/s390x/tcg-target.c.inc | 7 ++++---
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target/sparc: fake UltraSPARC T1 PCR and PIC registers
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2 files changed, 19 insertions(+), 5 deletions(-)
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Fabiano Rosas (1):
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elfload: Fix alignment when unmapping excess reservation
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Mikael Szreder (2):
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target/sparc: Fix register selection for all F*TOx and FxTO* instructions
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target/sparc: Fix gdbstub incorrectly handling registers f32-f62
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Richard Henderson (23):
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tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
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tcg: Remove TCG_OVERSIZED_GUEST
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tcg: Drop support for two address registers in gen_ldst
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tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
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tcg/arm: Drop addrhi from prepare_host_addr
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tcg/i386: Drop addrhi from prepare_host_addr
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tcg/mips: Drop addrhi from prepare_host_addr
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tcg/ppc: Drop addrhi from prepare_host_addr
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tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
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plugins: Fix qemu_plugin_read_memory_vaddr parameters
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accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
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target/loongarch: Use VADDR_PRIx for logging pc_next
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target/mips: Use VADDR_PRIx for logging pc_next
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include/exec: Change vaddr to uintptr_t
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include/exec: Use uintptr_t in CPUTLBEntry
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tcg: Introduce the 'z' constraint for a hardware zero register
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tcg/aarch64: Use 'z' constraint
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tcg/loongarch64: Use 'z' constraint
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tcg/mips: Use 'z' constraint
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tcg/riscv: Use 'z' constraint
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tcg/sparc64: Use 'z' constraint
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tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
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include/exec/tlb-common.h | 10 +-
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include/exec/vaddr.h | 16 +-
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include/qemu/atomic.h | 18 +-
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include/tcg/oversized-guest.h | 23 ---
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include/tcg/tcg-opc.h | 28 +--
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include/tcg/tcg.h | 3 +-
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linux-user/aarch64/target_signal.h | 2 +
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linux-user/arm/target_signal.h | 2 +
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linux-user/generic/signal.h | 1 -
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linux-user/i386/target_signal.h | 2 +
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linux-user/m68k/target_signal.h | 1 +
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linux-user/microblaze/target_signal.h | 2 +
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linux-user/ppc/target_signal.h | 2 +
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linux-user/s390x/target_signal.h | 2 +
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linux-user/sh4/target_signal.h | 2 +
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linux-user/x86_64/target_signal.h | 2 +
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linux-user/xtensa/target_signal.h | 2 +
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tcg/aarch64/tcg-target-con-set.h | 12 +-
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tcg/aarch64/tcg-target.h | 2 +
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tcg/loongarch64/tcg-target-con-set.h | 15 +-
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tcg/loongarch64/tcg-target-con-str.h | 1 -
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tcg/loongarch64/tcg-target-has.h | 2 -
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tcg/loongarch64/tcg-target.h | 2 +
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tcg/mips/tcg-target-con-set.h | 26 +--
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tcg/mips/tcg-target-con-str.h | 1 -
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tcg/mips/tcg-target.h | 2 +
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tcg/riscv/tcg-target-con-set.h | 10 +-
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tcg/riscv/tcg-target-con-str.h | 1 -
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tcg/riscv/tcg-target-has.h | 2 -
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tcg/riscv/tcg-target.h | 2 +
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tcg/sparc64/tcg-target-con-set.h | 12 +-
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tcg/sparc64/tcg-target-con-str.h | 1 -
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tcg/sparc64/tcg-target.h | 3 +-
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tcg/tci/tcg-target.h | 1 -
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accel/tcg/cputlb.c | 32 +---
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accel/tcg/tcg-all.c | 9 +-
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linux-user/elfload.c | 4 +-
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plugins/api.c | 2 +-
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target/arm/ptw.c | 34 ----
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target/loongarch/tcg/translate.c | 2 +-
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target/mips/tcg/octeon_translate.c | 4 +-
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target/riscv/cpu_helper.c | 13 +-
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target/sparc/gdbstub.c | 18 +-
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target/sparc/translate.c | 19 +++
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tcg/optimize.c | 21 +--
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tcg/tcg-op-ldst.c | 103 +++--------
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tcg/tcg.c | 97 +++++------
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tcg/tci.c | 119 +++----------
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docs/devel/multi-thread-tcg.rst | 1 -
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docs/devel/tcg-ops.rst | 4 +-
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target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
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target/sparc/insns.decode | 19 ++-
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tcg/aarch64/tcg-target.c.inc | 86 ++++------
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tcg/arm/tcg-target.c.inc | 114 ++++---------
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tcg/i386/tcg-target.c.inc | 190 +++++----------------
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tcg/loongarch64/tcg-target.c.inc | 72 +++-----
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tcg/mips/tcg-target.c.inc | 169 ++++++------------
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tcg/ppc/tcg-target.c.inc | 164 +++++-------------
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tcg/riscv/tcg-target.c.inc | 56 +++---
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tcg/s390x/tcg-target.c.inc | 40 ++---
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tcg/sparc64/tcg-target.c.inc | 45 ++---
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tcg/tci/tcg-target.c.inc | 60 ++-----
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62 files changed, 550 insertions(+), 1162 deletions(-)
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delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 1/4] tcg/s390x: Fix tcg_out_dupi_vec vs VGM
[PULL v3 13/28] target/mips: Use VADDR_PRIx for logging pc_next
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The immediate operands to VGM were in the wrong order,
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DisasContextBase.pc_next has type vaddr; use the correct log format.
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producing an inverse mask.
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2
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Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual addresses")
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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---
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tcg/s390x/tcg-target.c.inc | 4 ++--
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target/mips/tcg/octeon_translate.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
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diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/tcg/s390x/tcg-target.c.inc
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--- a/target/mips/tcg/octeon_translate.c
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+++ b/tcg/s390x/tcg-target.c.inc
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+++ b/target/mips/tcg/octeon_translate.c
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@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
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@@ -XXX,XX +XXX,XX @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
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msb = clz32(val);
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TCGv p;
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lsb = 31 - ctz32(val);
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}
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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- tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
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- LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
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+ tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32);
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- TARGET_FMT_lx "\n", ctx->base.pc_next);
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return;
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+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx "\n",
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}
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+ ctx->base.pc_next);
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} else {
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generate_exception_end(ctx, EXCP_RI);
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@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
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return true;
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msb = clz64(val);
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lsb = 63 - ctz64(val);
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}
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- tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
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+ tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64);
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return;
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}
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}
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}
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--
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--
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2.25.1
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2.43.0
diff view generated by jsdifflib
[PULL 2/4] tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
Deleted patch
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The operands are output in the wrong order: the tcg selector
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argument is first, whereas the s390x selector argument is last.
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1
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Tested-by: Thomas Huth <thuth@redhat.com>
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898
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Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec")
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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tcg/s390x/tcg-target.c.inc | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
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index XXXXXXX..XXXXXXX 100644
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--- a/tcg/s390x/tcg-target.c.inc
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+++ b/tcg/s390x/tcg-target.c.inc
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@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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break;
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case INDEX_op_bitsel_vec:
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- tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
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+ tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1);
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break;
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case INDEX_op_cmp_vec:
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--
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2.25.1
diff view generated by jsdifflib
[PULL 3/4] tcg/s390x: Fix tcg_out_dup_vec vs general registers
Deleted patch
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We copied the data from the general register input to the
2
vector register output, but have not yet replicated it.
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We intended to fall through into the vector-vector case,
4
but failed to redirect the input register.
5
1
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This is caught by an assertion failure in tcg_out_insn_VRIc,
7
which diagnosed the incorrect register class.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
tcg/s390x/tcg-target.c.inc | 1 +
12
1 file changed, 1 insertion(+)
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14
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/s390x/tcg-target.c.inc
17
+++ b/tcg/s390x/tcg-target.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
19
if (vece == MO_64) {
20
return true;
21
}
22
+ src = dst;
23
}
24
25
/*
26
--
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2.25.1
diff view generated by jsdifflib
[PULL 4/4] tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
Deleted patch
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The LDRD (register) instruction is UNPREDICTABLE if the Rm register
2
is the same as either Rt or Rt+1 (the two registers being loaded to).
3
We weren't making sure we avoided this, with the result that on some
4
host CPUs like the Cortex-A7 we would get a SIGILL because the CPU
5
chooses to UNDEF for this particular UNPREDICTABLE case.
6
1
7
Since we've already checked that datalo is aligned, we can simplify
8
the test vs the Rm operand by aligning it before comparison. Check
9
for the two orderings before falling back to two ldr instructions.
10
11
We don't bother to do anything similar for tcg_out_ldrd_rwb(),
12
because it is only used in tcg_out_tlb_read() with a fixed set of
13
registers which don't overlap.
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There is no equivalent UNPREDICTABLE case for STRD.
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/896
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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tcg/arm/tcg-target.c.inc | 17 +++++++++++++++--
22
1 file changed, 15 insertions(+), 2 deletions(-)
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diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tcg/arm/tcg-target.c.inc
27
+++ b/tcg/arm/tcg-target.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
29
/* LDRD requires alignment; double-check that. */
30
if (get_alignment_bits(opc) >= MO_64
31
&& (datalo & 1) == 0 && datahi == datalo + 1) {
32
- tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
33
- } else if (scratch_addend) {
34
+ /*
35
+ * Rm (the second address op) must not overlap Rt or Rt + 1.
36
+ * Since datalo is aligned, we can simplify the test via alignment.
37
+ * Flip the two address arguments if that works.
38
+ */
39
+ if ((addend & ~1) != datalo) {
40
+ tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
41
+ break;
42
+ }
43
+ if ((addrlo & ~1) != datalo) {
44
+ tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo);
45
+ break;
46
+ }
47
+ }
48
+ if (scratch_addend) {
49
tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
50
tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
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} else {
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--
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2.25.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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