[PULL 0/4] tcg patch queue
[PULL v2.5 00/27] tcg patch queue
1
The following changes since commit 15df33ceb73cb6bb3c6736cf4d2cff51129ed4b4:
1
v2: Fix target/loongarch printf formats for vaddr
2
Include two more reviewed patches.
2
3
3
Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20220312-1' into staging (2022-03-13 17:29:18 +0000)
4
This time with actual pull urls. :-/
5
6
r~
7
8
9
The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
10
11
Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500)
4
12
5
are available in the Git repository at:
13
are available in the Git repository at:
6
14
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220314
15
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2
8
16
9
for you to fetch changes up to 76cff100beeae8d3676bb658cccd45ef5ced8aa9:
17
for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb:
10
18
11
tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 (2022-03-14 10:31:51 -0700)
19
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800)
12
20
13
----------------------------------------------------------------
21
----------------------------------------------------------------
14
Fixes for s390x host vectors
22
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
15
Fix for arm ldrd unpredictable case
23
tcg: Cleanups after disallowing 64-on-32
24
tcg: Introduce constraint for zero register
25
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
26
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
27
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
28
linux-user: Fix alignment when unmapping excess reservation
29
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
30
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
31
target/sparc: fake UltraSPARC T1 PCR and PIC registers
16
32
17
----------------------------------------------------------------
33
----------------------------------------------------------------
18
Richard Henderson (4):
34
Andreas Schwab (1):
19
tcg/s390x: Fix tcg_out_dupi_vec vs VGM
35
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
20
tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
21
tcg/s390x: Fix tcg_out_dup_vec vs general registers
22
tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
23
36
24
tcg/arm/tcg-target.c.inc | 17 +++++++++++++++--
37
Artyom Tarasenko (1):
25
tcg/s390x/tcg-target.c.inc | 7 ++++---
38
target/sparc: fake UltraSPARC T1 PCR and PIC registers
26
2 files changed, 19 insertions(+), 5 deletions(-)
39
40
Fabiano Rosas (1):
41
elfload: Fix alignment when unmapping excess reservation
42
43
Mikael Szreder (2):
44
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
45
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
46
47
Richard Henderson (22):
48
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
49
tcg: Remove TCG_OVERSIZED_GUEST
50
tcg: Drop support for two address registers in gen_ldst
51
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
52
tcg/arm: Drop addrhi from prepare_host_addr
53
tcg/i386: Drop addrhi from prepare_host_addr
54
tcg/mips: Drop addrhi from prepare_host_addr
55
tcg/ppc: Drop addrhi from prepare_host_addr
56
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
57
plugins: Fix qemu_plugin_read_memory_vaddr parameters
58
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
59
target/loongarch: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
70
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/riscv/cpu_helper.c | 13 +-
112
target/sparc/gdbstub.c | 18 +-
113
target/sparc/translate.c | 19 +++
114
tcg/optimize.c | 21 +--
115
tcg/tcg-op-ldst.c | 103 +++--------
116
tcg/tcg.c | 97 +++++------
117
tcg/tci.c | 119 +++----------
118
docs/devel/multi-thread-tcg.rst | 1 -
119
docs/devel/tcg-ops.rst | 4 +-
120
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
121
target/sparc/insns.decode | 19 ++-
122
tcg/aarch64/tcg-target.c.inc | 86 ++++------
123
tcg/arm/tcg-target.c.inc | 114 ++++---------
124
tcg/i386/tcg-target.c.inc | 190 +++++----------------
125
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
126
tcg/mips/tcg-target.c.inc | 169 ++++++------------
127
tcg/ppc/tcg-target.c.inc | 164 +++++-------------
128
tcg/riscv/tcg-target.c.inc | 56 +++---
129
tcg/s390x/tcg-target.c.inc | 40 ++---
130
tcg/sparc64/tcg-target.c.inc | 45 ++---
131
tcg/tci/tcg-target.c.inc | 60 ++-----
132
61 files changed, 548 insertions(+), 1160 deletions(-)
133
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 1/4] tcg/s390x: Fix tcg_out_dupi_vec vs VGM
Deleted patch
1
The immediate operands to VGM were in the wrong order,
2
producing an inverse mask.
3
1
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/s390x/tcg-target.c.inc | 4 ++--
7
1 file changed, 2 insertions(+), 2 deletions(-)
8
9
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/s390x/tcg-target.c.inc
12
+++ b/tcg/s390x/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
14
msb = clz32(val);
15
lsb = 31 - ctz32(val);
16
}
17
- tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
18
+ tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32);
19
return;
20
}
21
} else {
22
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
23
msb = clz64(val);
24
lsb = 63 - ctz64(val);
25
}
26
- tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
27
+ tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64);
28
return;
29
}
30
}
31
--
32
2.25.1
diff view generated by jsdifflib
[PULL 2/4] tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
Deleted patch
1
The operands are output in the wrong order: the tcg selector
2
argument is first, whereas the s390x selector argument is last.
3
1
4
Tested-by: Thomas Huth <thuth@redhat.com>
5
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898
6
Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec")
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/s390x/tcg-target.c.inc | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/s390x/tcg-target.c.inc
15
+++ b/tcg/s390x/tcg-target.c.inc
16
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
17
break;
18
19
case INDEX_op_bitsel_vec:
20
- tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
21
+ tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1);
22
break;
23
24
case INDEX_op_cmp_vec:
25
--
26
2.25.1
diff view generated by jsdifflib
[PULL 3/4] tcg/s390x: Fix tcg_out_dup_vec vs general registers
Deleted patch
1
We copied the data from the general register input to the
2
vector register output, but have not yet replicated it.
3
We intended to fall through into the vector-vector case,
4
but failed to redirect the input register.
5
1
6
This is caught by an assertion failure in tcg_out_insn_VRIc,
7
which diagnosed the incorrect register class.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
tcg/s390x/tcg-target.c.inc | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/s390x/tcg-target.c.inc
17
+++ b/tcg/s390x/tcg-target.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
19
if (vece == MO_64) {
20
return true;
21
}
22
+ src = dst;
23
}
24
25
/*
26
--
27
2.25.1
diff view generated by jsdifflib
[PULL 4/4] tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
Deleted patch
1
The LDRD (register) instruction is UNPREDICTABLE if the Rm register
2
is the same as either Rt or Rt+1 (the two registers being loaded to).
3
We weren't making sure we avoided this, with the result that on some
4
host CPUs like the Cortex-A7 we would get a SIGILL because the CPU
5
chooses to UNDEF for this particular UNPREDICTABLE case.
6
1
7
Since we've already checked that datalo is aligned, we can simplify
8
the test vs the Rm operand by aligning it before comparison. Check
9
for the two orderings before falling back to two ldr instructions.
10
11
We don't bother to do anything similar for tcg_out_ldrd_rwb(),
12
because it is only used in tcg_out_tlb_read() with a fixed set of
13
registers which don't overlap.
14
15
There is no equivalent UNPREDICTABLE case for STRD.
16
17
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
18
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/896
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
---
21
tcg/arm/tcg-target.c.inc | 17 +++++++++++++++--
22
1 file changed, 15 insertions(+), 2 deletions(-)
23
24
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tcg/arm/tcg-target.c.inc
27
+++ b/tcg/arm/tcg-target.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
29
/* LDRD requires alignment; double-check that. */
30
if (get_alignment_bits(opc) >= MO_64
31
&& (datalo & 1) == 0 && datahi == datalo + 1) {
32
- tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
33
- } else if (scratch_addend) {
34
+ /*
35
+ * Rm (the second address op) must not overlap Rt or Rt + 1.
36
+ * Since datalo is aligned, we can simplify the test via alignment.
37
+ * Flip the two address arguments if that works.
38
+ */
39
+ if ((addend & ~1) != datalo) {
40
+ tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
41
+ break;
42
+ }
43
+ if ((addrlo & ~1) != datalo) {
44
+ tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo);
45
+ break;
46
+ }
47
+ }
48
+ if (scratch_addend) {
49
tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
50
tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
51
} else {
52
--
53
2.25.1
54
55
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.