Series comparison

 [PULL 0/4] tcg patch queue
-The following changes since commit 15df33ceb73cb6bb3c6736cf4d2cff51129ed4b4:
+Pretty small still, but there are two patches that ought
 to get backported to stable, so no point in delaying.
-  Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20220312-1' into staging (2022-03-13 17:29:18 +0000)
+r~
 The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
   Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
 are available in the Git repository at:
-  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220314
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
-for you to fetch changes up to 76cff100beeae8d3676bb658cccd45ef5ced8aa9:
+for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
-  tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 (2022-03-14 10:31:51 -0700)
+  target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
 ----------------------------------------------------------------
-Fixes for s390x host vectors
+tcg: Reset free_temps before tcg_optimize
-Fix for arm ldrd unpredictable case
+tcg/riscv: Fix StoreStore barrier generation
 include/exec: Introduce fpst alias in helper-head.h.inc
 target/sparc: Use memcpy() and remove memcpy32()
 ----------------------------------------------------------------
-Richard Henderson (4):
+Philippe Mathieu-Daudé (1):
-      tcg/s390x: Fix tcg_out_dupi_vec vs VGM
+      target/sparc: Use memcpy() and remove memcpy32()
       tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
       tcg/s390x: Fix tcg_out_dup_vec vs general registers
       tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
- tcg/arm/tcg-target.c.inc   | 17 +++++++++++++++--
+Richard Henderson (2):
- tcg/s390x/tcg-target.c.inc |  7 ++++---
+      tcg: Reset free_temps before tcg_optimize
-files changed, 19 insertions(+), 5 deletions(-)
+      include/exec: Introduce fpst alias in helper-head.h.inc
 Roman Artemev (1):
       tcg/riscv: Fix StoreStore barrier generation
  include/tcg/tcg-temp-internal.h |  6 ++++++
  accel/tcg/plugin-gen.c          |  2 +-
  target/sparc/win_helper.c       | 26 ++++++++------------------
  tcg/tcg.c                       |  5 ++++-
  include/exec/helper-head.h.inc  |  3 +++
  tcg/riscv/tcg-target.c.inc      |  2 +-
 files changed, 23 insertions(+), 21 deletions(-)

-[PULL 3/4] tcg/s390x: Fix tcg_out_dup_vec vs general registers
+[PULL 1/4] tcg: Reset free_temps before tcg_optimize
-We copied the data from the general register input to the
+When allocating new temps during tcg_optmize, do not re-use
-vector register output, but have not yet replicated it.
+any EBB temps that were used within the TB.  We do not have
-We intended to fall through into the vector-vector case,
+any idea what span of the TB in which the temp was live.
 but failed to redirect the input register.
-This is caught by an assertion failure in tcg_out_insn_VRIc,
+Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
-which diagnosed the incorrect register class.
+as well as replacing the equivalent in plugin_gen_inject and
 tcg_func_start.
+Cc: qemu-stable@nongnu.org
+Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
+Reported-by: wannacu <wannacu2049@gmail.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- tcg/s390x/tcg-target.c.inc | 1 +
+ include/tcg/tcg-temp-internal.h | 6 ++++++
-file changed, 1 insertion(+)
+ accel/tcg/plugin-gen.c          | 2 +-
  tcg/tcg.c                       | 5 ++++-
 files changed, 11 insertions(+), 2 deletions(-)
-diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
+diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390x/tcg-target.c.inc
+--- a/include/tcg/tcg-temp-internal.h
-+++ b/tcg/s390x/tcg-target.c.inc
++++ b/include/tcg/tcg-temp-internal.h
-@@ -XXX,XX +XXX,XX @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
-         if (vece == MO_64) {
+ TCGv_ptr tcg_temp_ebb_new_ptr(void);
-             return true;
+ TCGv_i128 tcg_temp_ebb_new_i128(void);
-         }
-+        src = dst;
++/* Forget all freed EBB temps, so that new allocations produce new temps. */
 +static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
 +{
 +    memset(s->free_temps, 0, sizeof(s->free_temps));
 +}
 +
  #endif /* TCG_TEMP_FREE_H */
 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/plugin-gen.c
 +++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
       * that might be live within the existing opcode stream.
       * The simplest solution is to release them all and create new.
       */
 -    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
 +    tcg_temp_ebb_reset_freed(tcg_ctx);
      QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
          switch (op->opc) {
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg.c
 +++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
      s->nb_temps = s->nb_globals;
      /* No temps have been previously allocated for size or locality.  */
 -    memset(s->free_temps, 0, sizeof(s->free_temps));
 +    tcg_temp_ebb_reset_freed(s);
      /* No constant temps have been previously allocated. */
      for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
      }
+ #endif
-     /*
 +    /* Do not reuse any EBB that may be allocated within the TB. */
 +    tcg_temp_ebb_reset_freed(s);
 +
      tcg_optimize(s);
      reachable_code_pass(s);
 --
-.25.1
+.43.0

-[PULL 2/4] tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
+[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
-The operands are output in the wrong order: the tcg selector
+From: Roman Artemev <roman.artemev@syntacore.com>
 argument is first, whereas the s390x selector argument is last.
-Tested-by: Thomas Huth <thuth@redhat.com>
+On RISC-V to StoreStore barrier corresponds
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898
+`fence w, w` not `fence r, r`
-Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec")
 Cc: qemu-stable@nongnu.org
 Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
 Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
 Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/s390x/tcg-target.c.inc | 2 +-
+ tcg/riscv/tcg-target.c.inc | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
+diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390x/tcg-target.c.inc
+--- a/tcg/riscv/tcg-target.c.inc
-+++ b/tcg/s390x/tcg-target.c.inc
++++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
-         break;
+         insn |= 0x02100000;
+     }
-     case INDEX_op_bitsel_vec:
+     if (a0 & TCG_MO_ST_ST) {
--        tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
+-        insn |= 0x02200000;
-+        tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1);
++        insn |= 0x01100000;
-         break;
+     }
+     tcg_out32(s, insn);
-     case INDEX_op_cmp_vec:
+ }
 --
-.25.1
+.43.0

-[PULL 4/4] tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
+[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
-The LDRD (register) instruction is UNPREDICTABLE if the Rm register
+This allows targets to declare that the helper requires a
-is the same as either Rt or Rt+1 (the two registers being loaded to).
+float_status pointer and instead of a generic void pointer.
 We weren't making sure we avoided this, with the result that on some
 host CPUs like the Cortex-A7 we would get a SIGILL because the CPU
 chooses to UNDEF for this particular UNPREDICTABLE case.
-Since we've already checked that datalo is aligned, we can simplify
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 the test vs the Rm operand by aligning it before comparison.  Check
 for the two orderings before falling back to two ldr instructions.
 We don't bother to do anything similar for tcg_out_ldrd_rwb(),
 because it is only used in tcg_out_tlb_read() with a fixed set of
 registers which don't overlap.
 There is no equivalent UNPREDICTABLE case for STRD.
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/896
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.c.inc | 17 +++++++++++++++--
+ include/exec/helper-head.h.inc | 3 +++
-file changed, 15 insertions(+), 2 deletions(-)
+file changed, 3 insertions(+)
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
+--- a/include/exec/helper-head.h.inc
-+++ b/tcg/arm/tcg-target.c.inc
++++ b/include/exec/helper-head.h.inc
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
+@@ -XXX,XX +XXX,XX @@
-         /* LDRD requires alignment; double-check that. */
+ #define dh_alias_ptr ptr
-         if (get_alignment_bits(opc) >= MO_64
+ #define dh_alias_cptr ptr
-             && (datalo & 1) == 0 && datahi == datalo + 1) {
+ #define dh_alias_env ptr
--            tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
++#define dh_alias_fpst ptr
--        } else if (scratch_addend) {
+ #define dh_alias_void void
-+            /*
+ #define dh_alias_noreturn noreturn
-+             * Rm (the second address op) must not overlap Rt or Rt + 1.
+ #define dh_alias(t) glue(dh_alias_, t)
-+             * Since datalo is aligned, we can simplify the test via alignment.
+@@ -XXX,XX +XXX,XX @@
-+             * Flip the two address arguments if that works.
+ #define dh_ctype_ptr void *
-+             */
+ #define dh_ctype_cptr const void *
-+            if ((addend & ~1) != datalo) {
+ #define dh_ctype_env CPUArchState *
-+                tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
++#define dh_ctype_fpst float_status *
-+                break;
+ #define dh_ctype_void void
-+            }
+ #define dh_ctype_noreturn G_NORETURN void
-+            if ((addrlo & ~1) != datalo) {
+ #define dh_ctype(t) dh_ctype_##t
-+                tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo);
+@@ -XXX,XX +XXX,XX @@
-+                break;
+ #define dh_typecode_f64 dh_typecode_i64
-+            }
+ #define dh_typecode_cptr dh_typecode_ptr
-+        }
+ #define dh_typecode_env dh_typecode_ptr
-+        if (scratch_addend) {
++#define dh_typecode_fpst dh_typecode_ptr
-             tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
+ #define dh_typecode(t) dh_typecode_##t
-             tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
-         } else {
+ #define dh_callflag_i32  0
 --
-.25.1
+.43.0

-[PULL 1/4] tcg/s390x: Fix tcg_out_dupi_vec vs VGM
+[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
-The immediate operands to VGM were in the wrong order,
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 producing an inverse mask.
+Rather than manually copying each register, use
+the libc memcpy(), which is well optimized nowadays.
+Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
+Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20241205205418.67613-1-philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/s390x/tcg-target.c.inc | 4 ++--
+ target/sparc/win_helper.c | 26 ++++++++------------------
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 8 insertions(+), 18 deletions(-)
-diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
+diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390x/tcg-target.c.inc
+--- a/target/sparc/win_helper.c
-+++ b/tcg/s390x/tcg-target.c.inc
++++ b/target/sparc/win_helper.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+@@ -XXX,XX +XXX,XX @@
-                 msb = clz32(val);
+ #include "exec/helper-proto.h"
-                 lsb = 31 - ctz32(val);
+ #include "trace.h"
-             }
--            tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
+-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-+            tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32);
+-{
-             return;
+-    dst[0] = src[0];
-         }
+-    dst[1] = src[1];
 -    dst[2] = src[2];
 -    dst[3] = src[3];
 -    dst[4] = src[4];
 -    dst[5] = src[5];
 -    dst[6] = src[6];
 -    dst[7] = src[7];
 -}
 -
  void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
  {
      /* put the modified wrap registers at their proper location */
      if (env->cwp == env->nwindows - 1) {
 -        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
 +        memcpy(env->regbase, env->regbase + env->nwindows * 16,
 +               sizeof(env->gregs));
      }
      env->cwp = new_cwp;
      /* put the wrap registers at their temporary location */
      if (new_cwp == env->nwindows - 1) {
 -        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
 +        memcpy(env->regbase + env->nwindows * 16, env->regbase,
 +               sizeof(env->gregs));
      }
      env->regwptr = env->regbase + (new_cwp * 16);
  }
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
      dst = get_gl_gregset(env, env->gl);
      if (src != dst) {
 -        memcpy32(dst, env->gregs);
 -        memcpy32(env->gregs, src);
 +        memcpy(dst, env->gregs, sizeof(env->gregs));
 +        memcpy(env->gregs, src, sizeof(env->gregs));
      }
  }
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
          /* Switch global register bank */
          src = get_gregset(env, new_pstate_regs);
          dst = get_gregset(env, pstate_regs);
 -        memcpy32(dst, env->gregs);
 -        memcpy32(env->gregs, src);
 +        memcpy(dst, env->gregs, sizeof(env->gregs));
 +        memcpy(env->gregs, src, sizeof(env->gregs));
      } else {
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+         trace_win_helper_no_switch_pstate(new_pstate_regs);
                  msb = clz64(val);
                  lsb = 63 - ctz64(val);
              }
 -            tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
 +            tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64);
              return;
          }
      }
 --
-.25.1
+.43.0

The following changes since commit 15df33ceb73cb6bb3c6736cf4d2cff51129ed4b4:

Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20220312-1' into staging (2022-03-13 17:29:18 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220314

for you to fetch changes up to 76cff100beeae8d3676bb658cccd45ef5ced8aa9:

tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 (2022-03-14 10:31:51 -0700)

----------------------------------------------------------------
Fixes for s390x host vectors
Fix for arm ldrd unpredictable case

----------------------------------------------------------------
Richard Henderson (4):
      tcg/s390x: Fix tcg_out_dupi_vec vs VGM
      tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
      tcg/s390x: Fix tcg_out_dup_vec vs general registers
      tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1

tcg/arm/tcg-target.c.inc   | 17 +++++++++++++++--
 tcg/s390x/tcg-target.c.inc |  7 ++++---
 2 files changed, 19 insertions(+), 5 deletions(-)

The immediate operands to VGM were in the wrong order,
producing an inverse mask.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                 msb = clz32(val);
                 lsb = 31 - ctz32(val);
             }
-            tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
+            tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32);
             return;
         }
     } else {
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                 msb = clz64(val);
                 lsb = 63 - ctz64(val);
             }
-            tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
+            tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64);
             return;
         }
     }
-- 
2.25.1

The LDRD (register) instruction is UNPREDICTABLE if the Rm register
is the same as either Rt or Rt+1 (the two registers being loaded to).
We weren't making sure we avoided this, with the result that on some
host CPUs like the Cortex-A7 we would get a SIGILL because the CPU
chooses to UNDEF for this particular UNPREDICTABLE case.

Since we've already checked that datalo is aligned, we can simplify
the test vs the Rm operand by aligning it before comparison.  Check
for the two orderings before falling back to two ldr instructions.

We don't bother to do anything similar for tcg_out_ldrd_rwb(),
because it is only used in tcg_out_tlb_read() with a fixed set of
registers which don't overlap.

There is no equivalent UNPREDICTABLE case for STRD.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/896
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
         /* LDRD requires alignment; double-check that. */
         if (get_alignment_bits(opc) >= MO_64
             && (datalo & 1) == 0 && datahi == datalo + 1) {
-            tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
-        } else if (scratch_addend) {
+            /*
+             * Rm (the second address op) must not overlap Rt or Rt + 1.
+             * Since datalo is aligned, we can simplify the test via alignment.
+             * Flip the two address arguments if that works.
+             */
+            if ((addend & ~1) != datalo) {
+                tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
+                break;
+            }
+            if ((addrlo & ~1) != datalo) {
+                tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo);
+                break;
+            }
+        }
+        if (scratch_addend) {
             tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
             tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
         } else {
-- 
2.25.1

Pretty small still, but there are two patches that ought
to get backported to stable, so no point in delaying.

The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:

Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212

for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:

target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)

----------------------------------------------------------------
tcg: Reset free_temps before tcg_optimize
tcg/riscv: Fix StoreStore barrier generation
include/exec: Introduce fpst alias in helper-head.h.inc
target/sparc: Use memcpy() and remove memcpy32()

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      target/sparc: Use memcpy() and remove memcpy32()

Richard Henderson (2):
      tcg: Reset free_temps before tcg_optimize
      include/exec: Introduce fpst alias in helper-head.h.inc

Roman Artemev (1):
      tcg/riscv: Fix StoreStore barrier generation

When allocating new temps during tcg_optmize, do not re-use
any EBB temps that were used within the TB.  We do not have
any idea what span of the TB in which the temp was live.

Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
as well as replacing the equivalent in plugin_gen_inject and
tcg_func_start.

Cc: qemu-stable@nongnu.org
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
Reported-by: wannacu <wannacu2049@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-temp-internal.h | 6 ++++++
 accel/tcg/plugin-gen.c          | 2 +-
 tcg/tcg.c                       | 5 ++++-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-temp-internal.h
+++ b/include/tcg/tcg-temp-internal.h
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
 TCGv_ptr tcg_temp_ebb_new_ptr(void);
 TCGv_i128 tcg_temp_ebb_new_i128(void);
 
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
+{
+    memset(s->free_temps, 0, sizeof(s->free_temps));
+}
+
 #endif /* TCG_TEMP_FREE_H */
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
      * that might be live within the existing opcode stream.
      * The simplest solution is to release them all and create new.
      */
-    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
+    tcg_temp_ebb_reset_freed(tcg_ctx);
 
     QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
         switch (op->opc) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
     s->nb_temps = s->nb_globals;
 
     /* No temps have been previously allocated for size or locality.  */
-    memset(s->free_temps, 0, sizeof(s->free_temps));
+    tcg_temp_ebb_reset_freed(s);
 
     /* No constant temps have been previously allocated. */
     for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
     }
 #endif
 
+    /* Do not reuse any EBB that may be allocated within the TB. */
+    tcg_temp_ebb_reset_freed(s);
+
     tcg_optimize(s);
 
     reachable_code_pass(s);
-- 
2.43.0

From: Roman Artemev <roman.artemev@syntacore.com>

On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`

Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
         insn |= 0x02100000;
     }
     if (a0 & TCG_MO_ST_ST) {
-        insn |= 0x02200000;
+        insn |= 0x01100000;
     }
     tcg_out32(s, insn);
 }
-- 
2.43.0

This allows targets to declare that the helper requires a
float_status pointer and instead of a generic void pointer.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/helper-head.h.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h.inc
+++ b/include/exec/helper-head.h.inc
@@ -XXX,XX +XXX,XX @@
 #define dh_alias_ptr ptr
 #define dh_alias_cptr ptr
 #define dh_alias_env ptr
+#define dh_alias_fpst ptr
 #define dh_alias_void void
 #define dh_alias_noreturn noreturn
 #define dh_alias(t) glue(dh_alias_, t)
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_ptr void *
 #define dh_ctype_cptr const void *
 #define dh_ctype_env CPUArchState *
+#define dh_ctype_fpst float_status *
 #define dh_ctype_void void
 #define dh_ctype_noreturn G_NORETURN void
 #define dh_ctype(t) dh_ctype_##t
@@ -XXX,XX +XXX,XX @@
 #define dh_typecode_f64 dh_typecode_i64
 #define dh_typecode_cptr dh_typecode_ptr
 #define dh_typecode_env dh_typecode_ptr
+#define dh_typecode_fpst dh_typecode_ptr
 #define dh_typecode(t) dh_typecode_##t
 
 #define dh_callflag_i32  0
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Rather than manually copying each register, use
the libc memcpy(), which is well optimized nowadays.

Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/win_helper.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sparc/win_helper.c
+++ b/target/sparc/win_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "trace.h"
 
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-{
-    dst[0] = src[0];
-    dst[1] = src[1];
-    dst[2] = src[2];
-    dst[3] = src[3];
-    dst[4] = src[4];
-    dst[5] = src[5];
-    dst[6] = src[6];
-    dst[7] = src[7];
-}
-
 void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
 {
     /* put the modified wrap registers at their proper location */
     if (env->cwp == env->nwindows - 1) {
-        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
+        memcpy(env->regbase, env->regbase + env->nwindows * 16,
+               sizeof(env->gregs));
     }
     env->cwp = new_cwp;
 
     /* put the wrap registers at their temporary location */
     if (new_cwp == env->nwindows - 1) {
-        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
+        memcpy(env->regbase + env->nwindows * 16, env->regbase,
+               sizeof(env->gregs));
     }
     env->regwptr = env->regbase + (new_cwp * 16);
 }
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
     dst = get_gl_gregset(env, env->gl);
 
     if (src != dst) {
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
         /* Switch global register bank */
         src = get_gregset(env, new_pstate_regs);
         dst = get_gregset(env, pstate_regs);
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     } else {
         trace_win_helper_no_switch_pstate(new_pstate_regs);
     }
-- 
2.43.0