Last lot of target-arm stuff: cleanups, bug fixes; nothing major here.

-- PMM

The following changes since commit 9d662a6b22a0838a85c5432385f35db2488a33a5:

Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220305' into staging (2022-03-05 18:03:15 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220307

for you to fetch changes up to 0942820408dc788560f6968e9b5f011803b846c2:

hw/arm/virt: Disable LPA2 for -machine virt-6.2 (2022-03-07 14:32:21 +0000)

* cleanups of qemu_oom_check() and qemu_memalign()

* target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero

* target/arm/translate-neon: Simplify align field check for VLD3

* GICv3 ITS: add more trace events

* GICv3 ITS: implement 8-byte accesses properly

* GICv3: fix minor issues with some trace/log messages

* ui/cocoa: Use the standard about panel

* target/arm: Provide cpu property for controling FEAT_LPA2

* hw/arm/virt: Disable LPA2 for -machine virt-6.2

Akihiko Odaki (1):

ui/cocoa: Use the standard about panel

Peter Maydell (15):

util: Make qemu_oom_check() a static function

util: Unify implementations of qemu_memalign()

util: Return valid allocation for qemu_try_memalign() with zero size

meson.build: Don't misdetect posix_memalign() on Windows

util: Share qemu_try_memalign() implementation between POSIX and Windows

util: Use meson checks for valloc() and memalign() presence

util: Put qemu_vfree() in memalign.c

osdep: Move memalign-related functions to their own header

target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero

target/arm/translate-neon: Simplify align field check for VLD3

hw/intc/arm_gicv3_its: Add trace events for commands

hw/intc/arm_gicv3_its: Add trace events for table reads and writes

hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps

hw/intc/arm_gicv3: Fix missing spaces in error log messages

hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event

Richard Henderson (2):

target/arm: Provide cpu property for controling FEAT_LPA2

hw/arm/virt: Disable LPA2 for -machine virt-6.2

meson.build | 7 ++-

include/hw/arm/virt.h | 1 +

include/qemu-common.h | 2 -

include/qemu/memalign.h | 61 ++++++++++++++++++++++

include/qemu/osdep.h | 18 -------

target/arm/cpu.h | 5 +-

block/blkverify.c | 1 +

block/block-copy.c | 1 +

block/commit.c | 1 +

block/crypto.c | 1 +

block/dmg.c | 1 +

block/export/fuse.c | 1 +

block/file-posix.c | 1 +

block/io.c | 1 +

block/mirror.c | 1 +

block/nvme.c | 1 +

block/parallels-ext.c | 1 +

block/parallels.c | 1 +

block/qcow.c | 1 +

block/qcow2-cache.c | 1 +

block/qcow2-cluster.c | 1 +

block/qcow2-refcount.c | 1 +

block/qcow2-snapshot.c | 1 +

block/qcow2.c | 1 +

block/qed-l2-cache.c | 1 +

block/qed-table.c | 1 +

block/qed.c | 1 +

block/quorum.c | 1 +

block/raw-format.c | 1 +

block/vdi.c | 1 +

block/vhdx-log.c | 1 +

block/vhdx.c | 1 +

block/vmdk.c | 1 +

block/vpc.c | 1 +

block/win32-aio.c | 1 +

hw/arm/virt.c | 7 +++

hw/block/dataplane/xen-block.c | 1 +

hw/block/fdc.c | 1 +

hw/ide/core.c | 1 +

hw/intc/arm_gicv3.c | 8 +++

hw/intc/arm_gicv3_cpuif.c | 3 +-

hw/intc/arm_gicv3_dist.c | 4 +-

hw/intc/arm_gicv3_its.c | 69 +++++++++++++++++++++----

hw/ppc/spapr.c | 1 +

hw/ppc/spapr_softmmu.c | 1 +

hw/scsi/scsi-disk.c | 1 +

hw/tpm/tpm_ppi.c | 2 +-

nbd/server.c | 1 +

net/l2tpv3.c | 2 +-

plugins/loader.c | 1 +

qemu-img.c | 1 +

qemu-io-cmds.c | 1 +

qom/object.c | 1 +

softmmu/physmem.c | 1 +

target/arm/cpu.c | 6 +++

target/arm/cpu64.c | 24 +++++++++

target/arm/translate-neon.c | 13 +++--

target/i386/hvf/hvf.c | 1 +

target/i386/kvm/kvm.c | 1 +

tcg/region.c | 1 +

tests/bench/atomic_add-bench.c | 1 +

tests/bench/qht-bench.c | 1 +

util/atomic64.c | 1 +

util/memalign.c | 92 +++++++++++++++++++++++++++++++++

util/oslib-posix.c | 46 -----------------

util/oslib-win32.c | 35 -------------

util/qht.c | 1 +

hw/intc/trace-events | 21 ++++++++

tests/avocado/boot_linux.py | 2 +

ui/cocoa.m | 112 +++++++++--------------------------------

util/meson.build | 1 +

71 files changed, 377 insertions(+), 212 deletions(-)

create mode 100644 include/qemu/memalign.h

create mode 100644 util/memalign.c

From: Richard Henderson <richard.henderson@linaro.org>

There is a Linux kernel bug present until v5.12 that prevents

booting with FEAT_LPA2 enabled. As a workaround for TCG, allow

the feature to be disabled from -cpu max.

Since this kernel bug is present in the Fedora 31 image that

we test in avocado, disable lpa2 on the command-line.

target/arm/cpu.h | 5 ++++-

target/arm/cpu.c | 6 ++++++

target/arm/cpu64.c | 24 ++++++++++++++++++++++++

tests/avocado/boot_linux.py | 2 ++

4 files changed, 36 insertions(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@ typedef struct {

# define ARM_MAX_VQ 16

void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);

void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);

+void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);

#else

# define ARM_MAX_VQ 1

static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }

static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }

+static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { }

#endif

typedef struct ARMVectorReg {

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

/*

* Intermediate values used during property parsing.

- * Once finalized, the values should be read from ID_AA64ISAR1.

+ * Once finalized, the values should be read from ID_AA64*.

*/

bool prop_pauth;

bool prop_pauth_impdef;

+ bool prop_lpa2;

/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */

uint32_t dcz_blocksize;

@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)

error_propagate(errp, local_err);

return;

}

+

+ arm_cpu_lpa2_finalize(cpu, &local_err);

+ if (local_err != NULL) {

+ error_propagate(errp, local_err);

+ return;

+ }

}

if (kvm_enabled()) {

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ void aarch64_add_pauth_properties(Object *obj)

}

}

+static Property arm_cpu_lpa2_property =

+ DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);

+

+void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)

+{

+ uint64_t t;

+

+ /*

+ * We only install the property for tcg -cpu max; this is the

+ * only situation in which the cpu field can be true.

+ */

+ if (!cpu->prop_lpa2) {

+ return;

+ }

+

+ t = cpu->isar.id_aa64mmfr0;

+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */

+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */

+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */

+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */

+ cpu->isar.id_aa64mmfr0 = t;

+}

+

static void aarch64_host_initfn(Object *obj)

{

#if defined(CONFIG_KVM)

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

aarch64_add_sve_properties(obj);

object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,

cpu_max_set_sve_max_vq, NULL, NULL);

+ qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);

}

static void aarch64_a64fx_initfn(Object *obj)

diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py

index XXXXXXX..XXXXXXX 100644

--- a/tests/avocado/boot_linux.py

+++ b/tests/avocado/boot_linux.py

@@ -XXX,XX +XXX,XX @@ def test_virt_tcg_gicv2(self):

"""

self.require_accelerator("tcg")

self.vm.add_args("-accel", "tcg")

+ self.vm.add_args("-cpu", "max,lpa2=off")

self.vm.add_args("-machine", "virt,gic-version=2")

self.add_common_args()

self.launch_and_wait(set_up_ssh_connection=False)

@@ -XXX,XX +XXX,XX @@ def test_virt_tcg_gicv3(self):

"""

self.require_accelerator("tcg")

self.vm.add_args("-accel", "tcg")

+ self.vm.add_args("-cpu", "max,lpa2=off")

self.vm.add_args("-machine", "virt,gic-version=3")

self.add_common_args()

self.launch_and_wait(set_up_ssh_connection=False)

2.25.1

The qemu_try_memalign() functions for POSIX and Windows used to be

significantly different, but these days they are identical except for

the actual allocation function called, and the POSIX version already

has to have ifdeffery for different allocation functions.

Move to a single implementation in memalign.c, which uses the Windows

_aligned_malloc if we detect that function in meson.

Message-id: 20220226180723.1706285-7-peter.maydell@linaro.org

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

meson.build | 1 +

util/memalign.c | 39 +++++++++++++++++++++++++++++++++++++++

util/oslib-posix.c | 29 -----------------------------

util/oslib-win32.c | 17 -----------------

4 files changed, 40 insertions(+), 46 deletions(-)

diff --git a/meson.build b/meson.build

--- a/meson.build

+++ b/meson.build

@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_POSIX_FALLOCATE', cc.has_function('posix_fallocate'

# Note that we need to specify prefix: here to avoid incorrectly

# thinking that Windows has posix_memalign()

config_host_data.set('CONFIG_POSIX_MEMALIGN', cc.has_function('posix_memalign', prefix: '#include <stdlib.h>'))

+config_host_data.set('CONFIG_ALIGNED_MALLOC', cc.has_function('_aligned_malloc'))

config_host_data.set('CONFIG_PPOLL', cc.has_function('ppoll'))

config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))

config_host_data.set('CONFIG_SEM_TIMEDWAIT', cc.has_function('sem_timedwait', dependencies: threads))

diff --git a/util/memalign.c b/util/memalign.c

--- a/util/memalign.c

+++ b/util/memalign.c

*/

#include "qemu/osdep.h"

+#include "qemu/host-utils.h"

+#include "trace.h"

+

+void *qemu_try_memalign(size_t alignment, size_t size)

+{

+ void *ptr;

+

+ if (alignment < sizeof(void*)) {

+ alignment = sizeof(void*);

+ } else {

+ g_assert(is_power_of_2(alignment));

+ }

+

+ /*

+ * Handling of 0 allocations varies among the different

+ * platform APIs (for instance _aligned_malloc() will

+ * fail) -- ensure that we always return a valid non-NULL

+ * pointer that can be freed by qemu_vfree().

+ */

+ if (size == 0) {

+ size++;

+ }

+#if defined(CONFIG_POSIX_MEMALIGN)

+ int ret;

+ ret = posix_memalign(&ptr, alignment, size);

+ if (ret != 0) {

+ errno = ret;

+ ptr = NULL;

+ }

+#elif defined(CONFIG_ALIGNED_MALLOC)

+ ptr = _aligned_malloc(size, alignment);

+#elif defined(CONFIG_BSD)

+ ptr = valloc(size);

+#else

+ ptr = memalign(alignment, size);

+#endif

+ trace_qemu_memalign(alignment, size, ptr);

+ return ptr;

+}

void *qemu_memalign(size_t alignment, size_t size)

{

diff --git a/util/oslib-posix.c b/util/oslib-posix.c

index XXXXXXX..XXXXXXX 100644

--- a/util/oslib-posix.c

+++ b/util/oslib-posix.c

@@ -XXX,XX +XXX,XX @@ fail_close:

return false;

}

-void *qemu_try_memalign(size_t alignment, size_t size)

-{

- void *ptr;

- if (alignment < sizeof(void*)) {

- alignment = sizeof(void*);

- } else {

- g_assert(is_power_of_2(alignment));

- }

- if (size == 0) {

- size++;

- }

-#if defined(CONFIG_POSIX_MEMALIGN)

- int ret;

- ret = posix_memalign(&ptr, alignment, size);

- if (ret != 0) {

- errno = ret;

- ptr = NULL;

- }

-#elif defined(CONFIG_BSD)

- ptr = valloc(size);

-#else

- ptr = memalign(alignment, size);

-#endif

- trace_qemu_memalign(alignment, size, ptr);

- return ptr;

-}

-

/* alloc shared memory pages */

void *qemu_anon_ram_alloc(size_t size, uint64_t *alignment, bool shared,

bool noreserve)

diff --git a/util/oslib-win32.c b/util/oslib-win32.c

index XXXXXXX..XXXXXXX 100644

--- a/util/oslib-win32.c

+++ b/util/oslib-win32.c

@@ -XXX,XX +XXX,XX @@

/* this must come after including "trace.h" */

#include <shlobj.h>

-void *qemu_try_memalign(size_t alignment, size_t size)

-{

- void *ptr;

-

- if (alignment < sizeof(void *)) {

- alignment = sizeof(void *);

- } else {

- g_assert(is_power_of_2(alignment));

- }

- if (size == 0) {

- size++;

- }

- ptr = _aligned_malloc(size, alignment);

- trace_qemu_memalign(alignment, size, ptr);

- return ptr;

-}

-

static int get_allocation_granularity(void)

{

SYSTEM_INFO system_info;

2.25.1

The trace_gicv3_icv_hppir_read trace event takes an integer value

which it uses to form the register name, which should be either

ICV_HPPIR0 or ICV_HPPIR1. We were passing in the 'grp' variable for

this, but that is either GICV3_G0 or GICV3_G1NS, which happen to be 0

and 2, which meant that tracing for the ICV_HPPIR1 register was

incorrectly printed as ICV_HPPIR2.

Use the same approach we do for all the other similar trace events,

and pass in 'ri->crm == 8 ? 0 : 1', deriving the index value

directly from the ARMCPRegInfo struct.

Message-id: 20220303202341.2232284-6-peter.maydell@linaro.org

hw/intc/arm_gicv3_cpuif.c | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c

--- a/hw/intc/arm_gicv3_cpuif.c

+++ b/hw/intc/arm_gicv3_cpuif.c

@@ -XXX,XX +XXX,XX @@ static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri)

}

}

- trace_gicv3_icv_hppir_read(grp, gicv3_redist_affid(cs), value);

+ trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1,

+ gicv3_redist_affid(cs), value);

return value;

}

2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

There is a Linux kernel bug present until v5.12 that prevents

booting with FEAT_LPA2 enabled. As a workaround for TCG,

disable this feature for machine versions prior to 7.0.

Cc: Daniel P. Berrangé <berrange@redhat.com>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

include/hw/arm/virt.h | 1 +

hw/arm/virt.c | 7 +++++++

2 files changed, 8 insertions(+)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h

--- a/include/hw/arm/virt.h

+++ b/include/hw/arm/virt.h

@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {

bool no_secure_gpio;

/* Machines < 6.2 have no support for describing cpu topology to guest */

bool no_cpu_topology;

+ bool no_tcg_lpa2;

};

struct VirtMachineState {

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

object_property_set_bool(cpuobj, "pmu", false, NULL);

}

+ if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {

+ object_property_set_bool(cpuobj, "lpa2", false, NULL);

+ }

+

if (object_property_find(cpuobj, "reset-cbar")) {

object_property_set_int(cpuobj, "reset-cbar",

vms->memmap[VIRT_CPUPERIPHS].base,

@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 0)

static void virt_machine_6_2_options(MachineClass *mc)

{

+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));

+

virt_machine_7_0_options(mc);

compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);

+ vmc->no_tcg_lpa2 = true;

}

DEFINE_VIRT_MACHINE(6, 2)

2.25.1

Currently we incorrectly think that posix_memalign() exists on

Windows. This is because of a combination of:

* the msys2/mingw toolchain/libc claim to have a

__builtin_posix_memalign when there isn't a builtin of that name

* meson will assume that if you have a __builtin_foo that

counts for has_function('foo')

Specifying a specific include file via prefix: causes meson to not

treat builtins as sufficient and actually look for the function

itself; see this meson pull request which added that as the official

way to get the right answer:

https://github.com/mesonbuild/meson/pull/1150

Currently this misdectection doesn't cause problems because we only

use CONFIG_POSIX_MEMALIGN in oslib-posix.c; however that will change

in a following commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220226180723.1706285-6-peter.maydell@linaro.org

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

---

meson.build | 4 +++-

1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build

--- a/meson.build

+++ b/meson.build

@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_CLOCK_ADJTIME', cc.has_function('clock_adjtime'))

config_host_data.set('CONFIG_DUP3', cc.has_function('dup3'))

config_host_data.set('CONFIG_FALLOCATE', cc.has_function('fallocate'))

config_host_data.set('CONFIG_POSIX_FALLOCATE', cc.has_function('posix_fallocate'))

-config_host_data.set('CONFIG_POSIX_MEMALIGN', cc.has_function('posix_memalign'))

+# Note that we need to specify prefix: here to avoid incorrectly

+# thinking that Windows has posix_memalign()

+config_host_data.set('CONFIG_POSIX_MEMALIGN', cc.has_function('posix_memalign', prefix: '#include <stdlib.h>'))

config_host_data.set('CONFIG_PPOLL', cc.has_function('ppoll'))

config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))

config_host_data.set('CONFIG_SEM_TIMEDWAIT', cc.has_function('sem_timedwait', dependencies: threads))

2.25.1

For debugging guest use of the ITS, it can be helpful to trace

when the ITS reads and writes the in-memory tables.

hw/intc/arm_gicv3_its.c | 37 +++++++++++++++++++++++++++++++------

hw/intc/trace-events | 9 +++++++++

2 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c

--- a/hw/intc/arm_gicv3_its.c

+++ b/hw/intc/arm_gicv3_its.c

@@ -XXX,XX +XXX,XX @@ static MemTxResult get_cte(GICv3ITSState *s, uint16_t icid, CTEntry *cte)

if (entry_addr == -1) {

/* No L2 table entry, i.e. no valid CTE, or a memory error */

cte->valid = false;

- return res;

+ goto out;

cteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res);

if (res != MEMTX_OK) {

- return res;

+ goto out;

cte->valid = FIELD_EX64(cteval, CTE, VALID);

cte->rdbase = FIELD_EX64(cteval, CTE, RDBASE);

- return MEMTX_OK;

+out:

+ if (res != MEMTX_OK) {

+ trace_gicv3_its_cte_read_fault(icid);

+ } else {

+ trace_gicv3_its_cte_read(icid, cte->valid, cte->rdbase);

+ }

+ return res;

}

/*

@@ -XXX,XX +XXX,XX @@ static bool update_ite(GICv3ITSState *s, uint32_t eventid, const DTEntry *dte,

uint64_t itel = 0;

uint32_t iteh = 0;

+ trace_gicv3_its_ite_write(dte->ittaddr, eventid, ite->valid,

+ ite->inttype, ite->intid, ite->icid,

+ ite->vpeid, ite->doorbell);

+

if (ite->valid) {

itel = FIELD_DP64(itel, ITE_L, VALID, 1);

itel = FIELD_DP64(itel, ITE_L, INTTYPE, ite->inttype);

@@ -XXX,XX +XXX,XX @@ static MemTxResult get_ite(GICv3ITSState *s, uint32_t eventid,

itel = address_space_ldq_le(as, iteaddr, MEMTXATTRS_UNSPECIFIED, &res);

if (res != MEMTX_OK) {

+ trace_gicv3_its_ite_read_fault(dte->ittaddr, eventid);

return res;

iteh = address_space_ldl_le(as, iteaddr + 8, MEMTXATTRS_UNSPECIFIED, &res);

if (res != MEMTX_OK) {

+ trace_gicv3_its_ite_read_fault(dte->ittaddr, eventid);

return res;

@@ -XXX,XX +XXX,XX @@ static MemTxResult get_ite(GICv3ITSState *s, uint32_t eventid,

ite->icid = FIELD_EX64(itel, ITE_L, ICID);

ite->vpeid = FIELD_EX64(itel, ITE_L, VPEID);

ite->doorbell = FIELD_EX64(iteh, ITE_H, DOORBELL);

+ trace_gicv3_its_ite_read(dte->ittaddr, eventid, ite->valid,

+ ite->inttype, ite->intid, ite->icid,

+ ite->vpeid, ite->doorbell);

return MEMTX_OK;

}

@@ -XXX,XX +XXX,XX @@ static MemTxResult get_dte(GICv3ITSState *s, uint32_t devid, DTEntry *dte)

if (entry_addr == -1) {

/* No L2 table entry, i.e. no valid DTE, or a memory error */

dte->valid = false;

- return res;

+ goto out;

dteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res);

if (res != MEMTX_OK) {

- return res;

+ goto out;

dte->valid = FIELD_EX64(dteval, DTE, VALID);

dte->size = FIELD_EX64(dteval, DTE, SIZE);

/* DTE word field stores bits [51:8] of the ITT address */

dte->ittaddr = FIELD_EX64(dteval, DTE, ITTADDR) << ITTADDR_SHIFT;

- return MEMTX_OK;

+out:

+ if (res != MEMTX_OK) {

+ trace_gicv3_its_dte_read_fault(devid);

+ } else {

+ trace_gicv3_its_dte_read(devid, dte->valid, dte->size, dte->ittaddr);

+ }

+ return res;

}

/*

@@ -XXX,XX +XXX,XX @@ static bool update_cte(GICv3ITSState *s, uint16_t icid, const CTEntry *cte)

uint64_t cteval = 0;

MemTxResult res = MEMTX_OK;

+ trace_gicv3_its_cte_write(icid, cte->valid, cte->rdbase);

+

if (cte->valid) {

/* add mapping entry to collection table */

cteval = FIELD_DP64(cteval, CTE, VALID, 1);

@@ -XXX,XX +XXX,XX @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, const DTEntry *dte)

uint64_t dteval = 0;

MemTxResult res = MEMTX_OK;

+ trace_gicv3_its_dte_write(devid, dte->valid, dte->size, dte->ittaddr);

+

if (dte->valid) {

/* add mapping entry to device table */

dteval = FIELD_DP64(dteval, DTE, VALID, 1);

diff --git a/hw/intc/trace-events b/hw/intc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/trace-events

+++ b/hw/intc/trace-events

@@ -XXX,XX +XXX,XX @@ gicv3_its_cmd_inv(void) "GICv3 ITS: command INV or INVALL"

gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64

gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x"

gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x"

+gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x"

+gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x"

+gicv3_its_cte_read_fault(uint32_t icid) "GICv3 ITS: Collection Table read for ICID 0x%x: faulted"

+gicv3_its_ite_read(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x"

+gicv3_its_ite_read_fault(uint64_t ittaddr, uint32_t eventid) "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: faulted"

+gicv3_its_ite_write(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: Interrupt Table write for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x"

+gicv3_its_dte_read(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table read for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64

+gicv3_its_dte_write(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table write for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64

+gicv3_its_dte_read_fault(uint32_t devid) "GICv3 ITS: Device Table read for DeviceID 0x%x: faulted"

# armv7m_nvic.c

nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"

2.25.1

Currently qemu_try_memalign()'s behaviour if asked to allocate

0 bytes is rather variable:

* on Windows, we will assert

* on POSIX platforms, we get the underlying behaviour of

the posix_memalign() or equivalent function, which may be

either "return a valid non-NULL pointer" or "return NULL"

Explictly check for 0 byte allocations, so we get consistent

behaviour across platforms. We handle them by incrementing the size

so that we return a valid non-NULL pointer that can later be passed

to qemu_vfree(). This is permitted behaviour for the

posix_memalign() API and is the most usual way that underlying

malloc() etc implementations handle a zero-sized allocation request,

because it won't trip up calling code that assumes NULL means an

error. (This includes our own qemu_memalign(), which will abort on

NULL.)

This change is a preparation for sharing the qemu_try_memalign() code

between Windows and POSIX.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

---

util/oslib-posix.c | 3 +++

util/oslib-win32.c | 4 +++-

2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/util/oslib-posix.c b/util/oslib-posix.c

--- a/util/oslib-posix.c

+++ b/util/oslib-posix.c

@@ -XXX,XX +XXX,XX @@ void *qemu_try_memalign(size_t alignment, size_t size)

g_assert(is_power_of_2(alignment));

+ if (size == 0) {

+ size++;

+ }

#if defined(CONFIG_POSIX_MEMALIGN)

int ret;

ret = posix_memalign(&ptr, alignment, size);

diff --git a/util/oslib-win32.c b/util/oslib-win32.c

index XXXXXXX..XXXXXXX 100644

--- a/util/oslib-win32.c

+++ b/util/oslib-win32.c

@@ -XXX,XX +XXX,XX @@ void *qemu_try_memalign(size_t alignment, size_t size)

{

void *ptr;

- g_assert(size != 0);

if (alignment < sizeof(void *)) {

alignment = sizeof(void *);

} else {

g_assert(is_power_of_2(alignment));

+ if (size == 0) {

+ size++;

+ }

ptr = _aligned_malloc(size, alignment);

trace_qemu_memalign(alignment, size, ptr);

return ptr;