[PULL 00/18] target-arm queue
[PULL 00/19] target-arm queue
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Last lot of target-arm stuff: cleanups, bug fixes; nothing major here.
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Hi; this is one last arm pullreq before the end of the year.
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Mostly minor cleanups, and also implementation of the
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FEAT_XS architectural feature.
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thanks
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-- PMM
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-- PMM
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7
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The following changes since commit 9d662a6b22a0838a85c5432385f35db2488a33a5:
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The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:
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Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220305' into staging (2022-03-05 18:03:15 +0000)
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Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu into staging (2024-12-16 14:20:33 -0500)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220307
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241217
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for you to fetch changes up to 0942820408dc788560f6968e9b5f011803b846c2:
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for you to fetch changes up to e91254250acb8570bd7b8a8f89d30e6d18291d02:
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hw/arm/virt: Disable LPA2 for -machine virt-6.2 (2022-03-07 14:32:21 +0000)
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tests/functional: update sbsa-ref firmware used in test (2024-12-17 15:21:06 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
21
target-arm queue:
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* cleanups of qemu_oom_check() and qemu_memalign()
22
* remove a line of redundant code
20
* target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
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* convert various TCG helper fns to use 'fpst' alias
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* target/arm/translate-neon: Simplify align field check for VLD3
24
* Use float_status in helper_fcvtx_f64_to_f32
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* GICv3 ITS: add more trace events
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* Use float_status in helper_vfp_fcvt{ds,sd}
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* GICv3 ITS: implement 8-byte accesses properly
26
* Implement FEAT_XS
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* GICv3: fix minor issues with some trace/log messages
27
* hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
25
* ui/cocoa: Use the standard about panel
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* tests/functional: update sbsa-ref firmware used in test
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* target/arm: Provide cpu property for controling FEAT_LPA2
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* hw/arm/virt: Disable LPA2 for -machine virt-6.2
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----------------------------------------------------------------
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----------------------------------------------------------------
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Akihiko Odaki (1):
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Denis Rastyogin (1):
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ui/cocoa: Use the standard about panel
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target/arm: remove redundant code
32
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Peter Maydell (15):
34
Manos Pitsidianakis (3):
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util: Make qemu_oom_check() a static function
35
target/arm: Add decodetree entry for DSB nXS variant
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util: Unify implementations of qemu_memalign()
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target/arm: Enable FEAT_XS for the max cpu
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util: Return valid allocation for qemu_try_memalign() with zero size
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tests/tcg/aarch64: add system test for FEAT_XS
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meson.build: Don't misdetect posix_memalign() on Windows
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util: Share qemu_try_memalign() implementation between POSIX and Windows
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util: Use meson checks for valloc() and memalign() presence
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util: Put qemu_vfree() in memalign.c
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osdep: Move memalign-related functions to their own header
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target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
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target/arm/translate-neon: Simplify align field check for VLD3
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hw/intc/arm_gicv3_its: Add trace events for commands
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hw/intc/arm_gicv3_its: Add trace events for table reads and writes
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hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps
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hw/intc/arm_gicv3: Fix missing spaces in error log messages
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hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event
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Richard Henderson (2):
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Marcin Juszkiewicz (1):
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target/arm: Provide cpu property for controling FEAT_LPA2
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tests/functional: update sbsa-ref firmware used in test
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hw/arm/virt: Disable LPA2 for -machine virt-6.2
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meson.build | 7 ++-
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Peter Maydell (4):
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include/hw/arm/virt.h | 1 +
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target/arm: Implement fine-grained-trap handling for FEAT_XS
56
include/qemu-common.h | 2 -
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target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns
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include/qemu/memalign.h | 61 ++++++++++++++++++++++
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target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns
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include/qemu/osdep.h | 18 -------
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hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
59
target/arm/cpu.h | 5 +-
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60
block/blkverify.c | 1 +
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Richard Henderson (10):
61
block/block-copy.c | 1 +
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target/arm: Convert vfp_helper.c to fpst alias
62
block/commit.c | 1 +
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target/arm: Convert helper-a64.c to fpst alias
63
block/crypto.c | 1 +
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target/arm: Convert vec_helper.c to fpst alias
64
block/dmg.c | 1 +
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target/arm: Convert neon_helper.c to fpst alias
65
block/export/fuse.c | 1 +
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target/arm: Convert sve_helper.c to fpst alias
66
block/file-posix.c | 1 +
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target/arm: Convert sme_helper.c to fpst alias
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block/io.c | 1 +
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target/arm: Convert vec_helper.c to use env alias
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block/mirror.c | 1 +
56
target/arm: Convert neon_helper.c to use env alias
69
block/nvme.c | 1 +
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target/arm: Use float_status in helper_fcvtx_f64_to_f32
70
block/parallels-ext.c | 1 +
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target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
71
block/parallels.c | 1 +
59
72
block/qcow.c | 1 +
60
docs/system/arm/emulation.rst | 1 +
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block/qcow2-cache.c | 1 +
61
target/arm/cpregs.h | 80 ++--
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block/qcow2-cluster.c | 1 +
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target/arm/cpu-features.h | 5 +
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block/qcow2-refcount.c | 1 +
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target/arm/helper.h | 638 +++++++++++++++----------------
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block/qcow2-snapshot.c | 1 +
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target/arm/tcg/helper-a64.h | 116 +++---
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block/qcow2.c | 1 +
65
target/arm/tcg/helper-sme.h | 4 +-
78
block/qed-l2-cache.c | 1 +
66
target/arm/tcg/helper-sve.h | 426 ++++++++++-----------
79
block/qed-table.c | 1 +
67
target/arm/tcg/a64.decode | 3 +
80
block/qed.c | 1 +
68
hw/intc/arm_gicv3_its.c | 44 +--
81
block/quorum.c | 1 +
69
target/arm/helper.c | 30 +-
82
block/raw-format.c | 1 +
70
target/arm/tcg/cpu64.c | 1 +
83
block/vdi.c | 1 +
71
target/arm/tcg/helper-a64.c | 101 ++---
84
block/vhdx-log.c | 1 +
72
target/arm/tcg/neon_helper.c | 27 +-
85
block/vhdx.c | 1 +
73
target/arm/tcg/op_helper.c | 11 +-
86
block/vmdk.c | 1 +
74
target/arm/tcg/sme_helper.c | 8 +-
87
block/vpc.c | 1 +
75
target/arm/tcg/sve_helper.c | 96 ++---
88
block/win32-aio.c | 1 +
76
target/arm/tcg/tlb-insns.c | 202 ++++++----
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hw/arm/virt.c | 7 +++
77
target/arm/tcg/translate-a64.c | 26 +-
90
hw/block/dataplane/xen-block.c | 1 +
78
target/arm/tcg/translate-vfp.c | 4 +-
91
hw/block/fdc.c | 1 +
79
target/arm/tcg/vec_helper.c | 81 ++--
92
hw/ide/core.c | 1 +
80
target/arm/vfp_helper.c | 130 +++----
93
hw/intc/arm_gicv3.c | 8 +++
81
tests/tcg/aarch64/system/feat-xs.c | 27 ++
94
hw/intc/arm_gicv3_cpuif.c | 3 +-
82
tests/functional/test_aarch64_sbsaref.py | 20 +-
95
hw/intc/arm_gicv3_dist.c | 4 +-
83
23 files changed, 1083 insertions(+), 998 deletions(-)
96
hw/intc/arm_gicv3_its.c | 69 +++++++++++++++++++++----
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create mode 100644 tests/tcg/aarch64/system/feat-xs.c
97
hw/ppc/spapr.c | 1 +
98
hw/ppc/spapr_softmmu.c | 1 +
99
hw/scsi/scsi-disk.c | 1 +
100
hw/tpm/tpm_ppi.c | 2 +-
101
nbd/server.c | 1 +
102
net/l2tpv3.c | 2 +-
103
plugins/loader.c | 1 +
104
qemu-img.c | 1 +
105
qemu-io-cmds.c | 1 +
106
qom/object.c | 1 +
107
softmmu/physmem.c | 1 +
108
target/arm/cpu.c | 6 +++
109
target/arm/cpu64.c | 24 +++++++++
110
target/arm/translate-neon.c | 13 +++--
111
target/i386/hvf/hvf.c | 1 +
112
target/i386/kvm/kvm.c | 1 +
113
tcg/region.c | 1 +
114
tests/bench/atomic_add-bench.c | 1 +
115
tests/bench/qht-bench.c | 1 +
116
util/atomic64.c | 1 +
117
util/memalign.c | 92 +++++++++++++++++++++++++++++++++
118
util/oslib-posix.c | 46 -----------------
119
util/oslib-win32.c | 35 -------------
120
util/qht.c | 1 +
121
hw/intc/trace-events | 21 ++++++++
122
tests/avocado/boot_linux.py | 2 +
123
ui/cocoa.m | 112 +++++++++--------------------------------
124
util/meson.build | 1 +
125
71 files changed, 377 insertions(+), 212 deletions(-)
126
create mode 100644 include/qemu/memalign.h
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create mode 100644 util/memalign.c
diff view generated by jsdifflib
New patch
[PULL 01/19] target/arm: remove redundant code
1
From: Denis Rastyogin <gerben@altlinux.org>
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2
3
This call is redundant as it only retrieves a value that is not used further.
4
5
Found by Linux Verification Center (linuxtesting.org) with SVACE.
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7
Signed-off-by: Denis Rastyogin <gerben@altlinux.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241212120618.518369-1-gerben@altlinux.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/vfp_helper.c | 2 --
13
1 file changed, 2 deletions(-)
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diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
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index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vfp_helper.c
18
+++ b/target/arm/vfp_helper.c
19
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rintd)(float64 x, void *fp_status)
20
21
ret = float64_round_to_int(x, fp_status);
22
23
- new_flags = get_float_exception_flags(fp_status);
24
-
25
/* Suppress any inexact exceptions the conversion produced */
26
if (!(old_flags & float_flag_inexact)) {
27
new_flags = get_float_exception_flags(fp_status);
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--
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2.34.1
diff view generated by jsdifflib
[PULL 03/18] util: Return valid allocation for qemu_try_memalign() with zero size
[PULL 02/19] target/arm: Convert vfp_helper.c to fpst alias
1
Currently qemu_try_memalign()'s behaviour if asked to allocate
1
From: Richard Henderson <richard.henderson@linaro.org>
2
0 bytes is rather variable:
3
* on Windows, we will assert
4
* on POSIX platforms, we get the underlying behaviour of
5
the posix_memalign() or equivalent function, which may be
6
either "return a valid non-NULL pointer" or "return NULL"
7
2
8
Explictly check for 0 byte allocations, so we get consistent
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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behaviour across platforms. We handle them by incrementing the size
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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so that we return a valid non-NULL pointer that can later be passed
5
Message-id: 20241206031224.78525-3-richard.henderson@linaro.org
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to qemu_vfree(). This is permitted behaviour for the
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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posix_memalign() API and is the most usual way that underlying
7
---
13
malloc() etc implementations handle a zero-sized allocation request,
8
target/arm/helper.h | 268 ++++++++++++++++++++--------------------
14
because it won't trip up calling code that assumes NULL means an
9
target/arm/vfp_helper.c | 120 ++++++++----------
15
error. (This includes our own qemu_memalign(), which will abort on
10
2 files changed, 186 insertions(+), 202 deletions(-)
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NULL.)
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This change is a preparation for sharing the qemu_try_memalign() code
12
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
between Windows and POSIX.
20
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
---
25
util/oslib-posix.c | 3 +++
26
util/oslib-win32.c | 4 +++-
27
2 files changed, 6 insertions(+), 1 deletion(-)
28
29
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
30
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
31
--- a/util/oslib-posix.c
14
--- a/target/arm/helper.h
32
+++ b/util/oslib-posix.c
15
+++ b/target/arm/helper.h
33
@@ -XXX,XX +XXX,XX @@ void *qemu_try_memalign(size_t alignment, size_t size)
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32)
34
g_assert(is_power_of_2(alignment));
17
DEF_HELPER_1(vfp_get_fpscr, i32, env)
18
DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
19
20
-DEF_HELPER_3(vfp_addh, f16, f16, f16, ptr)
21
-DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr)
22
-DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr)
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-DEF_HELPER_3(vfp_subh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr)
25
-DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr)
26
-DEF_HELPER_3(vfp_mulh, f16, f16, f16, ptr)
27
-DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr)
28
-DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr)
29
-DEF_HELPER_3(vfp_divh, f16, f16, f16, ptr)
30
-DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr)
31
-DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr)
32
-DEF_HELPER_3(vfp_maxh, f16, f16, f16, ptr)
33
-DEF_HELPER_3(vfp_maxs, f32, f32, f32, ptr)
34
-DEF_HELPER_3(vfp_maxd, f64, f64, f64, ptr)
35
-DEF_HELPER_3(vfp_minh, f16, f16, f16, ptr)
36
-DEF_HELPER_3(vfp_mins, f32, f32, f32, ptr)
37
-DEF_HELPER_3(vfp_mind, f64, f64, f64, ptr)
38
-DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, ptr)
39
-DEF_HELPER_3(vfp_maxnums, f32, f32, f32, ptr)
40
-DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr)
41
-DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr)
42
-DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr)
43
-DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr)
44
-DEF_HELPER_2(vfp_sqrth, f16, f16, ptr)
45
-DEF_HELPER_2(vfp_sqrts, f32, f32, ptr)
46
-DEF_HELPER_2(vfp_sqrtd, f64, f64, ptr)
47
+DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst)
48
+DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst)
49
+DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst)
50
+DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst)
51
+DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst)
52
+DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst)
53
+DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst)
54
+DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst)
55
+DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst)
56
+DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst)
57
+DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst)
58
+DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst)
59
+DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst)
60
+DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst)
61
+DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst)
62
+DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst)
63
+DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst)
64
+DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst)
65
+DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst)
66
+DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst)
67
+DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst)
68
+DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst)
69
+DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst)
70
+DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst)
71
+DEF_HELPER_2(vfp_sqrth, f16, f16, fpst)
72
+DEF_HELPER_2(vfp_sqrts, f32, f32, fpst)
73
+DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst)
74
DEF_HELPER_3(vfp_cmph, void, f16, f16, env)
75
DEF_HELPER_3(vfp_cmps, void, f32, f32, env)
76
DEF_HELPER_3(vfp_cmpd, void, f64, f64, env)
77
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
78
79
DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
80
DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
81
-DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr)
82
-DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr)
83
+DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
84
+DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
85
86
-DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
87
-DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
88
-DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
89
-DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
90
-DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
91
-DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
92
+DEF_HELPER_2(vfp_uitoh, f16, i32, fpst)
93
+DEF_HELPER_2(vfp_uitos, f32, i32, fpst)
94
+DEF_HELPER_2(vfp_uitod, f64, i32, fpst)
95
+DEF_HELPER_2(vfp_sitoh, f16, i32, fpst)
96
+DEF_HELPER_2(vfp_sitos, f32, i32, fpst)
97
+DEF_HELPER_2(vfp_sitod, f64, i32, fpst)
98
99
-DEF_HELPER_2(vfp_touih, i32, f16, ptr)
100
-DEF_HELPER_2(vfp_touis, i32, f32, ptr)
101
-DEF_HELPER_2(vfp_touid, i32, f64, ptr)
102
-DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
103
-DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
104
-DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
105
-DEF_HELPER_2(vfp_tosih, s32, f16, ptr)
106
-DEF_HELPER_2(vfp_tosis, s32, f32, ptr)
107
-DEF_HELPER_2(vfp_tosid, s32, f64, ptr)
108
-DEF_HELPER_2(vfp_tosizh, s32, f16, ptr)
109
-DEF_HELPER_2(vfp_tosizs, s32, f32, ptr)
110
-DEF_HELPER_2(vfp_tosizd, s32, f64, ptr)
111
+DEF_HELPER_2(vfp_touih, i32, f16, fpst)
112
+DEF_HELPER_2(vfp_touis, i32, f32, fpst)
113
+DEF_HELPER_2(vfp_touid, i32, f64, fpst)
114
+DEF_HELPER_2(vfp_touizh, i32, f16, fpst)
115
+DEF_HELPER_2(vfp_touizs, i32, f32, fpst)
116
+DEF_HELPER_2(vfp_touizd, i32, f64, fpst)
117
+DEF_HELPER_2(vfp_tosih, s32, f16, fpst)
118
+DEF_HELPER_2(vfp_tosis, s32, f32, fpst)
119
+DEF_HELPER_2(vfp_tosid, s32, f64, fpst)
120
+DEF_HELPER_2(vfp_tosizh, s32, f16, fpst)
121
+DEF_HELPER_2(vfp_tosizs, s32, f32, fpst)
122
+DEF_HELPER_2(vfp_tosizd, s32, f64, fpst)
123
124
-DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr)
125
-DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr)
126
-DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr)
127
-DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr)
128
-DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr)
129
-DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr)
130
-DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr)
131
-DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr)
132
-DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
133
-DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
134
-DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, ptr)
135
-DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
136
-DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
137
-DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, ptr)
138
-DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
139
-DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
140
-DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
141
-DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
142
-DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
143
-DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
144
-DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
145
-DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
146
-DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
147
-DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr)
148
-DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr)
149
-DEF_HELPER_3(vfp_touqs, i64, f32, i32, ptr)
150
-DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr)
151
-DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr)
152
-DEF_HELPER_3(vfp_tosqd, i64, f64, i32, ptr)
153
-DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr)
154
-DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr)
155
-DEF_HELPER_3(vfp_touqd, i64, f64, i32, ptr)
156
-DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr)
157
-DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr)
158
-DEF_HELPER_3(vfp_sqtos, f32, i64, i32, ptr)
159
-DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr)
160
-DEF_HELPER_3(vfp_ultos, f32, i32, i32, ptr)
161
-DEF_HELPER_3(vfp_uqtos, f32, i64, i32, ptr)
162
-DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr)
163
-DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr)
164
-DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
165
-DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
166
-DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
167
-DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
168
-DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr)
169
-DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr)
170
-DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
171
-DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
172
-DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
173
-DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
174
+DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst)
175
+DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst)
176
+DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst)
177
+DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst)
178
+DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst)
179
+DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst)
180
+DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst)
181
+DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst)
182
+DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst)
183
+DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst)
184
+DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst)
185
+DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst)
186
+DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst)
187
+DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst)
188
+DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst)
189
+DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst)
190
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst)
191
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst)
192
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst)
193
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst)
194
+DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst)
195
+DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst)
196
+DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst)
197
+DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst)
198
+DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst)
199
+DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst)
200
+DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst)
201
+DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst)
202
+DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst)
203
+DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst)
204
+DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst)
205
+DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst)
206
+DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst)
207
+DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst)
208
+DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst)
209
+DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst)
210
+DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst)
211
+DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst)
212
+DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst)
213
+DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst)
214
+DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst)
215
+DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst)
216
+DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst)
217
+DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst)
218
+DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst)
219
+DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst)
220
+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst)
221
+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst)
222
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst)
223
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst)
224
225
-DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr)
226
-DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr)
227
-DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr)
228
-DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr)
229
-DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr)
230
-DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr)
231
-DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr)
232
-DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr)
233
-DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr)
234
-DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr)
235
-DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr)
236
-DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr)
237
+DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst)
238
+DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst)
239
+DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst)
240
+DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst)
241
+DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst)
242
+DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst)
243
+DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst)
244
+DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst)
245
+DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst)
246
+DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst)
247
+DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst)
248
+DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst)
249
250
-DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
251
+DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst)
252
253
-DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32)
254
-DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i32)
255
-DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i32)
256
-DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32)
257
+DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i32)
258
+DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i32)
259
+DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i32)
260
+DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i32)
261
262
-DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr)
263
-DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
264
-DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr)
265
+DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst)
266
+DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst)
267
+DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst)
268
269
-DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
270
-DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
271
-DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
272
-DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
273
-DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
274
-DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
275
+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
276
+DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
277
+DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
278
+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
279
+DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
280
+DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
281
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
282
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
283
DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
284
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(shr_cc, i32, env, i32, i32)
285
DEF_HELPER_3(sar_cc, i32, env, i32, i32)
286
DEF_HELPER_3(ror_cc, i32, env, i32, i32)
287
288
-DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, ptr)
289
-DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr)
290
-DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr)
291
-DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, ptr)
292
-DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
293
-DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
294
+DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst)
295
+DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst)
296
+DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst)
297
+DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst)
298
+DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst)
299
+DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst)
300
301
DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env)
302
-DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
303
+DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst)
304
305
DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32)
306
307
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
308
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
309
void, ptr, ptr, ptr, ptr, i32)
310
311
-DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr)
312
-DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
313
-DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
314
-DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
315
+DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst)
316
+DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst)
317
+DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst)
318
+DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst)
319
320
DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
321
DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
322
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
323
index XXXXXXX..XXXXXXX 100644
324
--- a/target/arm/vfp_helper.c
325
+++ b/target/arm/vfp_helper.c
326
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val)
327
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
328
329
#define VFP_BINOP(name) \
330
-dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
331
+dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, float_status *fpst) \
332
{ \
333
- float_status *fpst = fpstp; \
334
return float16_ ## name(a, b, fpst); \
335
} \
336
-float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
337
+float32 VFP_HELPER(name, s)(float32 a, float32 b, float_status *fpst) \
338
{ \
339
- float_status *fpst = fpstp; \
340
return float32_ ## name(a, b, fpst); \
341
} \
342
-float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
343
+float64 VFP_HELPER(name, d)(float64 a, float64 b, float_status *fpst) \
344
{ \
345
- float_status *fpst = fpstp; \
346
return float64_ ## name(a, b, fpst); \
347
}
348
VFP_BINOP(add)
349
@@ -XXX,XX +XXX,XX @@ VFP_BINOP(minnum)
350
VFP_BINOP(maxnum)
351
#undef VFP_BINOP
352
353
-dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, void *fpstp)
354
+dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, float_status *fpst)
355
{
356
- return float16_sqrt(a, fpstp);
357
+ return float16_sqrt(a, fpst);
358
}
359
360
-float32 VFP_HELPER(sqrt, s)(float32 a, void *fpstp)
361
+float32 VFP_HELPER(sqrt, s)(float32 a, float_status *fpst)
362
{
363
- return float32_sqrt(a, fpstp);
364
+ return float32_sqrt(a, fpst);
365
}
366
367
-float64 VFP_HELPER(sqrt, d)(float64 a, void *fpstp)
368
+float64 VFP_HELPER(sqrt, d)(float64 a, float_status *fpst)
369
{
370
- return float64_sqrt(a, fpstp);
371
+ return float64_sqrt(a, fpst);
372
}
373
374
static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
375
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64, float64, fp_status)
376
/* Integer to float and float to integer conversions */
377
378
#define CONV_ITOF(name, ftype, fsz, sign) \
379
-ftype HELPER(name)(uint32_t x, void *fpstp) \
380
+ftype HELPER(name)(uint32_t x, float_status *fpst) \
381
{ \
382
- float_status *fpst = fpstp; \
383
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
384
}
385
386
#define CONV_FTOI(name, ftype, fsz, sign, round) \
387
-sign##int32_t HELPER(name)(ftype x, void *fpstp) \
388
+sign##int32_t HELPER(name)(ftype x, float_status *fpst) \
389
{ \
390
- float_status *fpst = fpstp; \
391
if (float##fsz##_is_any_nan(x)) { \
392
float_raise(float_flag_invalid, fpst); \
393
return 0; \
394
@@ -XXX,XX +XXX,XX @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
395
return float64_to_float32(x, &env->vfp.fp_status);
396
}
397
398
-uint32_t HELPER(bfcvt)(float32 x, void *status)
399
+uint32_t HELPER(bfcvt)(float32 x, float_status *status)
400
{
401
return float32_to_bfloat16(x, status);
402
}
403
404
-uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
405
+uint32_t HELPER(bfcvt_pair)(uint64_t pair, float_status *status)
406
{
407
bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status);
408
bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status);
409
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
410
*/
411
#define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
412
ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
413
- void *fpstp) \
414
-{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
415
+ float_status *fpst) \
416
+{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpst); }
417
418
#define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
419
ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
420
uint32_t shift, \
421
- void *fpstp) \
422
+ float_status *fpst) \
423
{ \
424
ftype ret; \
425
- float_status *fpst = fpstp; \
426
FloatRoundMode oldmode = fpst->float_rounding_mode; \
427
fpst->float_rounding_mode = float_round_nearest_even; \
428
- ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
429
+ ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpst); \
430
fpst->float_rounding_mode = oldmode; \
431
return ret; \
35
}
432
}
36
433
37
+ if (size == 0) {
434
#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
38
+ size++;
435
uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
39
+ }
436
- void *fpst) \
40
#if defined(CONFIG_POSIX_MEMALIGN)
437
+ float_status *fpst) \
41
int ret;
438
{ \
42
ret = posix_memalign(&ptr, alignment, size);
439
if (unlikely(float##fsz##_is_any_nan(x))) { \
43
diff --git a/util/oslib-win32.c b/util/oslib-win32.c
440
float_raise(float_flag_invalid, fpst); \
44
index XXXXXXX..XXXXXXX 100644
441
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FLOAT_FIX_ROUND(uq, d, 64, float64, 64, uint64,
45
--- a/util/oslib-win32.c
442
/* Set the current fp rounding mode and return the old one.
46
+++ b/util/oslib-win32.c
443
* The argument is a softfloat float_round_ value.
47
@@ -XXX,XX +XXX,XX @@ void *qemu_try_memalign(size_t alignment, size_t size)
444
*/
48
{
445
-uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
49
void *ptr;
446
+uint32_t HELPER(set_rmode)(uint32_t rmode, float_status *fp_status)
50
447
{
51
- g_assert(size != 0);
448
- float_status *fp_status = fpstp;
52
if (alignment < sizeof(void *)) {
449
-
53
alignment = sizeof(void *);
450
uint32_t prev_rmode = get_float_rounding_mode(fp_status);
54
} else {
451
set_float_rounding_mode(rmode, fp_status);
55
g_assert(is_power_of_2(alignment));
452
453
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
454
}
455
456
/* Half precision conversions. */
457
-float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
458
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, float_status *fpst,
459
+ uint32_t ahp_mode)
460
{
461
/* Squash FZ16 to 0 for the duration of conversion. In this case,
462
* it would affect flushing input denormals.
463
*/
464
- float_status *fpst = fpstp;
465
bool save = get_flush_inputs_to_zero(fpst);
466
set_flush_inputs_to_zero(false, fpst);
467
float32 r = float16_to_float32(a, !ahp_mode, fpst);
468
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
469
return r;
470
}
471
472
-uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
473
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, float_status *fpst,
474
+ uint32_t ahp_mode)
475
{
476
/* Squash FZ16 to 0 for the duration of conversion. In this case,
477
* it would affect flushing output denormals.
478
*/
479
- float_status *fpst = fpstp;
480
bool save = get_flush_to_zero(fpst);
481
set_flush_to_zero(false, fpst);
482
float16 r = float32_to_float16(a, !ahp_mode, fpst);
483
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
484
return r;
485
}
486
487
-float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
488
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, float_status *fpst,
489
+ uint32_t ahp_mode)
490
{
491
/* Squash FZ16 to 0 for the duration of conversion. In this case,
492
* it would affect flushing input denormals.
493
*/
494
- float_status *fpst = fpstp;
495
bool save = get_flush_inputs_to_zero(fpst);
496
set_flush_inputs_to_zero(false, fpst);
497
float64 r = float16_to_float64(a, !ahp_mode, fpst);
498
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
499
return r;
500
}
501
502
-uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
503
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, float_status *fpst,
504
+ uint32_t ahp_mode)
505
{
506
/* Squash FZ16 to 0 for the duration of conversion. In this case,
507
* it would affect flushing output denormals.
508
*/
509
- float_status *fpst = fpstp;
510
bool save = get_flush_to_zero(fpst);
511
set_flush_to_zero(false, fpst);
512
float16 r = float64_to_float16(a, !ahp_mode, fpst);
513
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
56
}
514
}
57
+ if (size == 0) {
515
}
58
+ size++;
516
59
+ }
517
-uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
60
ptr = _aligned_malloc(size, alignment);
518
+uint32_t HELPER(recpe_f16)(uint32_t input, float_status *fpst)
61
trace_qemu_memalign(alignment, size, ptr);
519
{
62
return ptr;
520
- float_status *fpst = fpstp;
521
float16 f16 = float16_squash_input_denormal(input, fpst);
522
uint32_t f16_val = float16_val(f16);
523
uint32_t f16_sign = float16_is_neg(f16);
524
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
525
return make_float16(f16_val);
526
}
527
528
-float32 HELPER(recpe_f32)(float32 input, void *fpstp)
529
+float32 HELPER(recpe_f32)(float32 input, float_status *fpst)
530
{
531
- float_status *fpst = fpstp;
532
float32 f32 = float32_squash_input_denormal(input, fpst);
533
uint32_t f32_val = float32_val(f32);
534
bool f32_sign = float32_is_neg(f32);
535
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
536
return make_float32(f32_val);
537
}
538
539
-float64 HELPER(recpe_f64)(float64 input, void *fpstp)
540
+float64 HELPER(recpe_f64)(float64 input, float_status *fpst)
541
{
542
- float_status *fpst = fpstp;
543
float64 f64 = float64_squash_input_denormal(input, fpst);
544
uint64_t f64_val = float64_val(f64);
545
bool f64_sign = float64_is_neg(f64);
546
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
547
return extract64(estimate, 0, 8) << 44;
548
}
549
550
-uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
551
+uint32_t HELPER(rsqrte_f16)(uint32_t input, float_status *s)
552
{
553
- float_status *s = fpstp;
554
float16 f16 = float16_squash_input_denormal(input, s);
555
uint16_t val = float16_val(f16);
556
bool f16_sign = float16_is_neg(f16);
557
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
558
if (float16_is_signaling_nan(f16, s)) {
559
float_raise(float_flag_invalid, s);
560
if (!s->default_nan_mode) {
561
- nan = float16_silence_nan(f16, fpstp);
562
+ nan = float16_silence_nan(f16, s);
563
}
564
}
565
if (s->default_nan_mode) {
566
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
567
return make_float16(val);
568
}
569
570
-float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
571
+float32 HELPER(rsqrte_f32)(float32 input, float_status *s)
572
{
573
- float_status *s = fpstp;
574
float32 f32 = float32_squash_input_denormal(input, s);
575
uint32_t val = float32_val(f32);
576
uint32_t f32_sign = float32_is_neg(f32);
577
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
578
if (float32_is_signaling_nan(f32, s)) {
579
float_raise(float_flag_invalid, s);
580
if (!s->default_nan_mode) {
581
- nan = float32_silence_nan(f32, fpstp);
582
+ nan = float32_silence_nan(f32, s);
583
}
584
}
585
if (s->default_nan_mode) {
586
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
587
return make_float32(val);
588
}
589
590
-float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
591
+float64 HELPER(rsqrte_f64)(float64 input, float_status *s)
592
{
593
- float_status *s = fpstp;
594
float64 f64 = float64_squash_input_denormal(input, s);
595
uint64_t val = float64_val(f64);
596
bool f64_sign = float64_is_neg(f64);
597
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
598
if (float64_is_signaling_nan(f64, s)) {
599
float_raise(float_flag_invalid, s);
600
if (!s->default_nan_mode) {
601
- nan = float64_silence_nan(f64, fpstp);
602
+ nan = float64_silence_nan(f64, s);
603
}
604
}
605
if (s->default_nan_mode) {
606
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_u32)(uint32_t a)
607
608
/* VFPv4 fused multiply-accumulate */
609
dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
610
- dh_ctype_f16 c, void *fpstp)
611
+ dh_ctype_f16 c, float_status *fpst)
612
{
613
- float_status *fpst = fpstp;
614
return float16_muladd(a, b, c, 0, fpst);
615
}
616
617
-float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
618
+float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c,
619
+ float_status *fpst)
620
{
621
- float_status *fpst = fpstp;
622
return float32_muladd(a, b, c, 0, fpst);
623
}
624
625
-float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
626
+float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c,
627
+ float_status *fpst)
628
{
629
- float_status *fpst = fpstp;
630
return float64_muladd(a, b, c, 0, fpst);
631
}
632
633
/* ARMv8 round to integral */
634
-dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status)
635
+dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, float_status *fp_status)
636
{
637
return float16_round_to_int(x, fp_status);
638
}
639
640
-float32 HELPER(rints_exact)(float32 x, void *fp_status)
641
+float32 HELPER(rints_exact)(float32 x, float_status *fp_status)
642
{
643
return float32_round_to_int(x, fp_status);
644
}
645
646
-float64 HELPER(rintd_exact)(float64 x, void *fp_status)
647
+float64 HELPER(rintd_exact)(float64 x, float_status *fp_status)
648
{
649
return float64_round_to_int(x, fp_status);
650
}
651
652
-dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
653
+dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, float_status *fp_status)
654
{
655
int old_flags = get_float_exception_flags(fp_status), new_flags;
656
float16 ret;
657
@@ -XXX,XX +XXX,XX @@ dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
658
return ret;
659
}
660
661
-float32 HELPER(rints)(float32 x, void *fp_status)
662
+float32 HELPER(rints)(float32 x, float_status *fp_status)
663
{
664
int old_flags = get_float_exception_flags(fp_status), new_flags;
665
float32 ret;
666
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rints)(float32 x, void *fp_status)
667
return ret;
668
}
669
670
-float64 HELPER(rintd)(float64 x, void *fp_status)
671
+float64 HELPER(rintd)(float64 x, float_status *fp_status)
672
{
673
int old_flags = get_float_exception_flags(fp_status), new_flags;
674
float64 ret;
675
@@ -XXX,XX +XXX,XX @@ const FloatRoundMode arm_rmode_to_sf_map[] = {
676
* Implement float64 to int32_t conversion without saturation;
677
* the result is supplied modulo 2^32.
678
*/
679
-uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
680
+uint64_t HELPER(fjcvtzs)(float64 value, float_status *status)
681
{
682
- float_status *status = vstatus;
683
uint32_t frac, e_old, e_new;
684
bool inexact;
685
686
@@ -XXX,XX +XXX,XX @@ static float32 frint_s(float32 f, float_status *fpst, int intsize)
687
return (0x100u + 126u + intsize) << 23;
688
}
689
690
-float32 HELPER(frint32_s)(float32 f, void *fpst)
691
+float32 HELPER(frint32_s)(float32 f, float_status *fpst)
692
{
693
return frint_s(f, fpst, 32);
694
}
695
696
-float32 HELPER(frint64_s)(float32 f, void *fpst)
697
+float32 HELPER(frint64_s)(float32 f, float_status *fpst)
698
{
699
return frint_s(f, fpst, 64);
700
}
701
@@ -XXX,XX +XXX,XX @@ static float64 frint_d(float64 f, float_status *fpst, int intsize)
702
return (uint64_t)(0x800 + 1022 + intsize) << 52;
703
}
704
705
-float64 HELPER(frint32_d)(float64 f, void *fpst)
706
+float64 HELPER(frint32_d)(float64 f, float_status *fpst)
707
{
708
return frint_d(f, fpst, 32);
709
}
710
711
-float64 HELPER(frint64_d)(float64 f, void *fpst)
712
+float64 HELPER(frint64_d)(float64 f, float_status *fpst)
713
{
714
return frint_d(f, fpst, 64);
715
}
63
--
716
--
64
2.25.1
717
2.34.1
65
718
66
719
diff view generated by jsdifflib
[PULL 18/18] hw/arm/virt: Disable LPA2 for -machine virt-6.2
[PULL 03/19] target/arm: Convert helper-a64.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
There is a Linux kernel bug present until v5.12 that prevents
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
booting with FEAT_LPA2 enabled. As a workaround for TCG,
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
disable this feature for machine versions prior to 7.0.
5
Message-id: 20241206031224.78525-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/tcg/helper-a64.h | 94 +++++++++++++++++------------------
9
target/arm/tcg/helper-a64.c | 98 +++++++++++++------------------------
10
2 files changed, 80 insertions(+), 112 deletions(-)
6
11
7
Cc: Daniel P. Berrangé <berrange@redhat.com>
12
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/virt.h | 1 +
13
hw/arm/virt.c | 7 +++++++
14
2 files changed, 8 insertions(+)
15
16
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/virt.h
14
--- a/target/arm/tcg/helper-a64.h
19
+++ b/include/hw/arm/virt.h
15
+++ b/target/arm/tcg/helper-a64.h
20
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(msr_i_spsel, void, env, i32)
21
bool no_secure_gpio;
17
DEF_HELPER_2(msr_i_daifset, void, env, i32)
22
/* Machines < 6.2 have no support for describing cpu topology to guest */
18
DEF_HELPER_2(msr_i_daifclear, void, env, i32)
23
bool no_cpu_topology;
19
DEF_HELPER_1(msr_set_allint_el1, void, env)
24
+ bool no_tcg_lpa2;
20
-DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
25
};
21
-DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
26
22
-DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
27
struct VirtMachineState {
23
-DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
28
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
24
-DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
25
-DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr)
26
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, fpst)
27
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, fpst)
28
+DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, fpst)
29
+DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, fpst)
30
+DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, fpst)
31
+DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, fpst)
32
DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
-DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
34
-DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
35
-DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
36
-DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
37
-DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
38
-DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
39
-DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
40
-DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
41
-DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
42
-DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
43
-DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
44
-DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
45
-DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
46
-DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
47
+DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
48
+DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
49
+DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
50
+DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
51
+DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
52
+DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
53
+DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
54
+DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
55
+DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
56
+DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
57
+DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
58
+DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
59
+DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
60
+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
61
DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
62
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
63
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
64
-DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
65
-DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
66
-DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
67
-DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
68
-DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
69
-DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
70
-DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
71
-DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
72
-DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
73
-DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
74
-DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
75
-DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
76
-DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
77
-DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
78
-DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
79
-DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
80
-DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
81
-DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
82
-DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
83
-DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
84
-DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
85
-DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
86
-DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
87
-DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
88
-DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
89
-DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
90
-DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
91
+DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
92
+DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
93
+DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
94
+DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
95
+DEF_HELPER_3(advsimd_addh, f16, f16, f16, fpst)
96
+DEF_HELPER_3(advsimd_subh, f16, f16, f16, fpst)
97
+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, fpst)
98
+DEF_HELPER_3(advsimd_divh, f16, f16, f16, fpst)
99
+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, fpst)
100
+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, fpst)
101
+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, fpst)
102
+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, fpst)
103
+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, fpst)
104
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, fpst)
105
+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, fpst)
106
+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, fpst)
107
+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, fpst)
108
+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, fpst)
109
+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, fpst)
110
+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, fpst)
111
+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, fpst)
112
+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, fpst)
113
+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, fpst)
114
+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, fpst)
115
+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, fpst)
116
+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, fpst)
117
+DEF_HELPER_2(advsimd_rinth, f16, f16, fpst)
118
119
DEF_HELPER_2(exception_return, void, env, i64)
120
DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64)
121
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
29
index XXXXXXX..XXXXXXX 100644
122
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/virt.c
123
--- a/target/arm/tcg/helper-a64.c
31
+++ b/hw/arm/virt.c
124
+++ b/target/arm/tcg/helper-a64.c
32
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
125
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
33
object_property_set_bool(cpuobj, "pmu", false, NULL);
126
return flags;
34
}
127
}
35
128
36
+ if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
129
-uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
37
+ object_property_set_bool(cpuobj, "lpa2", false, NULL);
130
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, float_status *fp_status)
38
+ }
131
{
39
+
132
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
40
if (object_property_find(cpuobj, "reset-cbar")) {
133
}
41
object_property_set_int(cpuobj, "reset-cbar",
134
42
vms->memmap[VIRT_CPUPERIPHS].base,
135
-uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
43
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 0)
136
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, float_status *fp_status)
44
137
{
45
static void virt_machine_6_2_options(MachineClass *mc)
138
return float_rel_to_flags(float16_compare(x, y, fp_status));
46
{
139
}
47
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
140
48
+
141
-uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
49
virt_machine_7_0_options(mc);
142
+uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, float_status *fp_status)
50
compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
143
{
51
+ vmc->no_tcg_lpa2 = true;
144
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
52
}
145
}
53
DEFINE_VIRT_MACHINE(6, 2)
146
54
147
-uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
148
+uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, float_status *fp_status)
149
{
150
return float_rel_to_flags(float32_compare(x, y, fp_status));
151
}
152
153
-uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
154
+uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, float_status *fp_status)
155
{
156
return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
157
}
158
159
-uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
160
+uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, float_status *fp_status)
161
{
162
return float_rel_to_flags(float64_compare(x, y, fp_status));
163
}
164
165
-float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
166
+float32 HELPER(vfp_mulxs)(float32 a, float32 b, float_status *fpst)
167
{
168
- float_status *fpst = fpstp;
169
-
170
a = float32_squash_input_denormal(a, fpst);
171
b = float32_squash_input_denormal(b, fpst);
172
173
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
174
return float32_mul(a, b, fpst);
175
}
176
177
-float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
178
+float64 HELPER(vfp_mulxd)(float64 a, float64 b, float_status *fpst)
179
{
180
- float_status *fpst = fpstp;
181
-
182
a = float64_squash_input_denormal(a, fpst);
183
b = float64_squash_input_denormal(b, fpst);
184
185
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
186
}
187
188
/* 64bit/double versions of the neon float compare functions */
189
-uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
190
+uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, float_status *fpst)
191
{
192
- float_status *fpst = fpstp;
193
return -float64_eq_quiet(a, b, fpst);
194
}
195
196
-uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
197
+uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, float_status *fpst)
198
{
199
- float_status *fpst = fpstp;
200
return -float64_le(b, a, fpst);
201
}
202
203
-uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
204
+uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, float_status *fpst)
205
{
206
- float_status *fpst = fpstp;
207
return -float64_lt(b, a, fpst);
208
}
209
210
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
211
* multiply-add-and-halve.
212
*/
213
214
-uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
215
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
216
{
217
- float_status *fpst = fpstp;
218
-
219
a = float16_squash_input_denormal(a, fpst);
220
b = float16_squash_input_denormal(b, fpst);
221
222
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
223
return float16_muladd(a, b, float16_two, 0, fpst);
224
}
225
226
-float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
227
+float32 HELPER(recpsf_f32)(float32 a, float32 b, float_status *fpst)
228
{
229
- float_status *fpst = fpstp;
230
-
231
a = float32_squash_input_denormal(a, fpst);
232
b = float32_squash_input_denormal(b, fpst);
233
234
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
235
return float32_muladd(a, b, float32_two, 0, fpst);
236
}
237
238
-float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
239
+float64 HELPER(recpsf_f64)(float64 a, float64 b, float_status *fpst)
240
{
241
- float_status *fpst = fpstp;
242
-
243
a = float64_squash_input_denormal(a, fpst);
244
b = float64_squash_input_denormal(b, fpst);
245
246
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
247
return float64_muladd(a, b, float64_two, 0, fpst);
248
}
249
250
-uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
251
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
252
{
253
- float_status *fpst = fpstp;
254
-
255
a = float16_squash_input_denormal(a, fpst);
256
b = float16_squash_input_denormal(b, fpst);
257
258
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
259
return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
260
}
261
262
-float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
263
+float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, float_status *fpst)
264
{
265
- float_status *fpst = fpstp;
266
-
267
a = float32_squash_input_denormal(a, fpst);
268
b = float32_squash_input_denormal(b, fpst);
269
270
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
271
return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
272
}
273
274
-float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
275
+float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, float_status *fpst)
276
{
277
- float_status *fpst = fpstp;
278
-
279
a = float64_squash_input_denormal(a, fpst);
280
b = float64_squash_input_denormal(b, fpst);
281
282
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
283
}
284
285
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
286
-uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
287
+uint32_t HELPER(frecpx_f16)(uint32_t a, float_status *fpst)
288
{
289
- float_status *fpst = fpstp;
290
uint16_t val16, sbit;
291
int16_t exp;
292
293
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
294
}
295
}
296
297
-float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
298
+float32 HELPER(frecpx_f32)(float32 a, float_status *fpst)
299
{
300
- float_status *fpst = fpstp;
301
uint32_t val32, sbit;
302
int32_t exp;
303
304
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
305
}
306
}
307
308
-float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
309
+float64 HELPER(frecpx_f64)(float64 a, float_status *fpst)
310
{
311
- float_status *fpst = fpstp;
312
uint64_t val64, sbit;
313
int64_t exp;
314
315
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
316
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
317
318
#define ADVSIMD_HALFOP(name) \
319
-uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
320
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, float_status *fpst) \
321
{ \
322
- float_status *fpst = fpstp; \
323
return float16_ ## name(a, b, fpst); \
324
}
325
326
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(minnum)
327
ADVSIMD_HALFOP(maxnum)
328
329
#define ADVSIMD_TWOHALFOP(name) \
330
-uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
331
+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, \
332
+ float_status *fpst) \
333
{ \
334
float16 a1, a2, b1, b2; \
335
uint32_t r1, r2; \
336
- float_status *fpst = fpstp; \
337
a1 = extract32(two_a, 0, 16); \
338
a2 = extract32(two_a, 16, 16); \
339
b1 = extract32(two_b, 0, 16); \
340
@@ -XXX,XX +XXX,XX @@ ADVSIMD_TWOHALFOP(minnum)
341
ADVSIMD_TWOHALFOP(maxnum)
342
343
/* Data processing - scalar floating-point and advanced SIMD */
344
-static float16 float16_mulx(float16 a, float16 b, void *fpstp)
345
+static float16 float16_mulx(float16 a, float16 b, float_status *fpst)
346
{
347
- float_status *fpst = fpstp;
348
-
349
a = float16_squash_input_denormal(a, fpst);
350
b = float16_squash_input_denormal(b, fpst);
351
352
@@ -XXX,XX +XXX,XX @@ ADVSIMD_TWOHALFOP(mulx)
353
354
/* fused multiply-accumulate */
355
uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
356
- void *fpstp)
357
+ float_status *fpst)
358
{
359
- float_status *fpst = fpstp;
360
return float16_muladd(a, b, c, 0, fpst);
361
}
362
363
uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
364
- uint32_t two_c, void *fpstp)
365
+ uint32_t two_c, float_status *fpst)
366
{
367
- float_status *fpst = fpstp;
368
float16 a1, a2, b1, b2, c1, c2;
369
uint32_t r1, r2;
370
a1 = extract32(two_a, 0, 16);
371
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
372
373
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
374
375
-uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
376
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, float_status *fpst)
377
{
378
- float_status *fpst = fpstp;
379
int compare = float16_compare_quiet(a, b, fpst);
380
return ADVSIMD_CMPRES(compare == float_relation_equal);
381
}
382
383
-uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
384
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, float_status *fpst)
385
{
386
- float_status *fpst = fpstp;
387
int compare = float16_compare(a, b, fpst);
388
return ADVSIMD_CMPRES(compare == float_relation_greater ||
389
compare == float_relation_equal);
390
}
391
392
-uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
393
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, float_status *fpst)
394
{
395
- float_status *fpst = fpstp;
396
int compare = float16_compare(a, b, fpst);
397
return ADVSIMD_CMPRES(compare == float_relation_greater);
398
}
399
400
-uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
401
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, float_status *fpst)
402
{
403
- float_status *fpst = fpstp;
404
float16 f0 = float16_abs(a);
405
float16 f1 = float16_abs(b);
406
int compare = float16_compare(f0, f1, fpst);
407
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
408
compare == float_relation_equal);
409
}
410
411
-uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
412
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, float_status *fpst)
413
{
414
- float_status *fpst = fpstp;
415
float16 f0 = float16_abs(a);
416
float16 f1 = float16_abs(b);
417
int compare = float16_compare(f0, f1, fpst);
418
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
419
}
420
421
/* round to integral */
422
-uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
423
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, float_status *fp_status)
424
{
425
return float16_round_to_int(x, fp_status);
426
}
427
428
-uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
429
+uint32_t HELPER(advsimd_rinth)(uint32_t x, float_status *fp_status)
430
{
431
int old_flags = get_float_exception_flags(fp_status), new_flags;
432
float16 ret;
55
--
433
--
56
2.25.1
434
2.34.1
57
435
58
436
diff view generated by jsdifflib
[PULL 06/18] util: Use meson checks for valloc() and memalign() presence
[PULL 04/19] target/arm: Convert vec_helper.c to fpst alias
1
Instead of assuming that all CONFIG_BSD have valloc() and anything
1
From: Richard Henderson <richard.henderson@linaro.org>
2
else is memalign(), explicitly check for those functions in
3
meson.build and use the "is the function present" define. Tests for
4
specific functionality are better than which-OS checks; this also
5
lets us give a helpful error message if somehow there's no usable
6
function present.
7
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-5-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20220226180723.1706285-8-peter.maydell@linaro.org
12
---
7
---
13
meson.build | 2 ++
8
target/arm/helper.h | 284 ++++++++++++++++++------------------
14
util/memalign.c | 6 ++++--
9
target/arm/tcg/helper-a64.h | 18 +--
15
2 files changed, 6 insertions(+), 2 deletions(-)
10
target/arm/tcg/helper-sve.h | 12 +-
11
target/arm/tcg/vec_helper.c | 60 ++++----
12
4 files changed, 183 insertions(+), 191 deletions(-)
16
13
17
diff --git a/meson.build b/meson.build
14
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/meson.build
16
--- a/target/arm/helper.h
20
+++ b/meson.build
17
+++ b/target/arm/helper.h
21
@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_POSIX_FALLOCATE', cc.has_function('posix_fallocate'
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG,
22
# thinking that Windows has posix_memalign()
19
void, ptr, ptr, ptr, ptr, i32)
23
config_host_data.set('CONFIG_POSIX_MEMALIGN', cc.has_function('posix_memalign', prefix: '#include <stdlib.h>'))
20
24
config_host_data.set('CONFIG_ALIGNED_MALLOC', cc.has_function('_aligned_malloc'))
21
DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG,
25
+config_host_data.set('CONFIG_VALLOC', cc.has_function('valloc'))
22
- void, ptr, ptr, ptr, ptr, i32)
26
+config_host_data.set('CONFIG_MEMALIGN', cc.has_function('memalign'))
23
+ void, ptr, ptr, ptr, fpst, i32)
27
config_host_data.set('CONFIG_PPOLL', cc.has_function('ppoll'))
24
DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
28
config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))
25
- void, ptr, ptr, ptr, ptr, i32)
29
config_host_data.set('CONFIG_SEM_TIMEDWAIT', cc.has_function('sem_timedwait', dependencies: threads))
26
+ void, ptr, ptr, ptr, fpst, i32)
30
diff --git a/util/memalign.c b/util/memalign.c
27
DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
28
- void, ptr, ptr, ptr, ptr, i32)
29
+ void, ptr, ptr, ptr, fpst, i32)
30
31
DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG,
32
- void, ptr, ptr, ptr, ptr, ptr, i32)
33
+ void, ptr, ptr, ptr, ptr, fpst, i32)
34
DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG,
35
- void, ptr, ptr, ptr, ptr, ptr, i32)
36
+ void, ptr, ptr, ptr, ptr, fpst, i32)
37
DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG,
38
- void, ptr, ptr, ptr, ptr, ptr, i32)
39
+ void, ptr, ptr, ptr, ptr, fpst, i32)
40
DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG,
41
- void, ptr, ptr, ptr, ptr, ptr, i32)
42
+ void, ptr, ptr, ptr, ptr, fpst, i32)
43
DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG,
44
- void, ptr, ptr, ptr, ptr, ptr, i32)
45
+ void, ptr, ptr, ptr, ptr, fpst, i32)
46
47
-DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
48
-DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
-DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
50
-DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
51
-DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
52
-DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
53
-DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
54
-DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
55
+DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
56
+DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
57
+DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
58
+DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
59
+DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
60
+DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
61
+DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
62
+DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
63
64
-DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
65
-DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
66
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
67
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
68
+DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
69
+DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
70
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
71
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
72
73
-DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
74
-DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
75
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
76
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
77
+DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
78
+DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
79
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
80
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
81
82
-DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
83
-DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
84
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
85
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
86
+DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
87
+DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
88
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
89
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
90
91
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
92
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
93
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
94
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
95
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
96
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
97
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
98
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
99
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
100
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
101
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
102
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
103
104
-DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
105
-DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
106
+DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
107
+DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
108
109
-DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
110
-DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
111
+DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
112
+DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
113
114
-DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
115
-DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
116
-DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
117
+DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
118
+DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
119
+DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
120
121
-DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
122
-DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
123
-DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
124
+DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
125
+DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
126
+DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
127
128
-DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
129
-DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
130
-DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
131
+DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
132
+DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
133
+DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
134
135
-DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
136
-DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
137
-DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
138
+DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
139
+DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
140
+DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
141
142
-DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
143
-DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
144
-DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
145
+DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
146
+DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
147
+DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
148
149
-DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
150
-DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
151
-DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
152
+DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
153
+DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
154
+DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
155
156
-DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
157
-DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
158
-DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
159
+DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
160
+DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
161
+DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
162
163
-DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
164
-DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
165
-DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
166
+DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
167
+DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
168
+DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
169
170
-DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
171
-DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
172
-DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
173
+DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
174
+DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
175
+DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
176
177
-DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
178
-DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
179
-DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
180
+DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
181
+DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
182
+DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
183
184
-DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
185
-DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
186
-DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
187
+DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
188
+DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
189
+DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
190
191
-DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
192
-DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
193
-DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
194
+DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
195
+DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
196
+DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
197
198
-DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
199
-DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
200
-DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
201
+DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
202
+DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
203
+DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
204
205
-DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
206
-DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
207
-DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
208
+DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
209
+DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
210
+DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
211
212
-DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
213
-DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
214
-DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
215
+DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
216
+DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
217
+DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
218
219
-DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
220
-DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
221
-DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
222
+DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
223
+DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
224
+DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
225
226
-DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
227
-DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
228
-DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
229
+DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
230
+DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
231
+DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
232
233
-DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
234
-DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
235
-DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
236
+DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
237
+DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
238
+DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
239
240
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
241
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
242
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
243
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
244
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
245
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
246
247
-DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
248
-DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
249
-DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
250
+DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
251
+DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
252
+DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
253
254
-DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
255
-DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
256
+DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
257
+DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
258
259
-DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
260
-DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
261
+DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
262
+DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
263
264
-DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
265
-DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
266
+DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
267
+DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
268
269
-DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
270
-DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
271
+DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
272
+DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
273
274
-DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
275
-DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
276
-DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
277
+DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
278
+DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
279
+DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
280
281
-DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
282
-DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
283
-DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
284
+DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
285
+DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
286
+DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
287
288
DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG,
289
- void, ptr, ptr, ptr, ptr, i32)
290
+ void, ptr, ptr, ptr, fpst, i32)
291
DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG,
292
- void, ptr, ptr, ptr, ptr, i32)
293
+ void, ptr, ptr, ptr, fpst, i32)
294
DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG,
295
- void, ptr, ptr, ptr, ptr, i32)
296
+ void, ptr, ptr, ptr, fpst, i32)
297
298
DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG,
299
- void, ptr, ptr, ptr, ptr, i32)
300
+ void, ptr, ptr, ptr, fpst, i32)
301
DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG,
302
- void, ptr, ptr, ptr, ptr, i32)
303
+ void, ptr, ptr, ptr, fpst, i32)
304
DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG,
305
- void, ptr, ptr, ptr, ptr, i32)
306
+ void, ptr, ptr, ptr, fpst, i32)
307
308
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG,
309
- void, ptr, ptr, ptr, ptr, i32)
310
+ void, ptr, ptr, ptr, fpst, i32)
311
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG,
312
- void, ptr, ptr, ptr, ptr, i32)
313
+ void, ptr, ptr, ptr, fpst, i32)
314
315
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG,
316
- void, ptr, ptr, ptr, ptr, i32)
317
+ void, ptr, ptr, ptr, fpst, i32)
318
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG,
319
- void, ptr, ptr, ptr, ptr, i32)
320
+ void, ptr, ptr, ptr, fpst, i32)
321
322
DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG,
323
- void, ptr, ptr, ptr, ptr, ptr, i32)
324
+ void, ptr, ptr, ptr, ptr, fpst, i32)
325
DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG,
326
- void, ptr, ptr, ptr, ptr, ptr, i32)
327
+ void, ptr, ptr, ptr, ptr, fpst, i32)
328
DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG,
329
- void, ptr, ptr, ptr, ptr, ptr, i32)
330
+ void, ptr, ptr, ptr, ptr, fpst, i32)
331
332
DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG,
333
void, ptr, ptr, ptr, ptr, i32)
334
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG,
335
void, ptr, ptr, ptr, ptr, env, i32)
336
337
DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
338
- void, ptr, ptr, ptr, ptr, ptr, i32)
339
+ void, ptr, ptr, ptr, ptr, fpst, i32)
340
DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
341
- void, ptr, ptr, ptr, ptr, ptr, i32)
342
+ void, ptr, ptr, ptr, ptr, fpst, i32)
343
344
DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
345
void, ptr, ptr, ptr, ptr, i32)
346
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
347
DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
348
void, ptr, ptr, ptr, ptr, i32)
349
350
-DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
351
-DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
352
-DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
353
+DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
354
+DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
355
+DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
356
357
-DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
358
-DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
359
-DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
360
+DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
361
+DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
362
+DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
363
364
-DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
365
-DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
366
-DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
367
+DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
368
+DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
369
+DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
370
371
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
372
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
373
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
374
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
375
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
376
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
377
378
-DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
379
-DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
380
-DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
381
+DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
382
+DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
383
+DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
384
385
DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
386
DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
387
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
31
index XXXXXXX..XXXXXXX 100644
388
index XXXXXXX..XXXXXXX 100644
32
--- a/util/memalign.c
389
--- a/target/arm/tcg/helper-a64.h
33
+++ b/util/memalign.c
390
+++ b/target/arm/tcg/helper-a64.h
34
@@ -XXX,XX +XXX,XX @@ void *qemu_try_memalign(size_t alignment, size_t size)
391
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(cpyfe, void, env, i32, i32, i32)
35
}
392
DEF_HELPER_FLAGS_1(guarded_page_check, TCG_CALL_NO_WG, void, env)
36
#elif defined(CONFIG_ALIGNED_MALLOC)
393
DEF_HELPER_FLAGS_2(guarded_page_br, TCG_CALL_NO_RWG, void, env, tl)
37
ptr = _aligned_malloc(size, alignment);
394
38
-#elif defined(CONFIG_BSD)
395
-DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
39
+#elif defined(CONFIG_VALLOC)
396
-DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
40
ptr = valloc(size);
397
-DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
41
-#else
398
+DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
42
+#elif defined(CONFIG_MEMALIGN)
399
+DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
43
ptr = memalign(alignment, size);
400
+DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
44
+#else
401
45
+ #error No function to allocate aligned memory available
402
-DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
46
#endif
403
-DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
47
trace_qemu_memalign(alignment, size, ptr);
404
-DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
48
return ptr;
405
+DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
406
+DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
407
+DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
408
409
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
410
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
411
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
412
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
413
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
414
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
415
diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h
416
index XXXXXXX..XXXXXXX 100644
417
--- a/target/arm/tcg/helper-sve.h
418
+++ b/target/arm/tcg/helper-sve.h
419
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_umini_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
420
DEF_HELPER_FLAGS_4(sve_umini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
421
422
DEF_HELPER_FLAGS_5(gvec_recps_h, TCG_CALL_NO_RWG,
423
- void, ptr, ptr, ptr, ptr, i32)
424
+ void, ptr, ptr, ptr, fpst, i32)
425
DEF_HELPER_FLAGS_5(gvec_recps_s, TCG_CALL_NO_RWG,
426
- void, ptr, ptr, ptr, ptr, i32)
427
+ void, ptr, ptr, ptr, fpst, i32)
428
DEF_HELPER_FLAGS_5(gvec_recps_d, TCG_CALL_NO_RWG,
429
- void, ptr, ptr, ptr, ptr, i32)
430
+ void, ptr, ptr, ptr, fpst, i32)
431
432
DEF_HELPER_FLAGS_5(gvec_rsqrts_h, TCG_CALL_NO_RWG,
433
- void, ptr, ptr, ptr, ptr, i32)
434
+ void, ptr, ptr, ptr, fpst, i32)
435
DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
436
- void, ptr, ptr, ptr, ptr, i32)
437
+ void, ptr, ptr, ptr, fpst, i32)
438
DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
439
- void, ptr, ptr, ptr, ptr, i32)
440
+ void, ptr, ptr, ptr, fpst, i32)
441
442
DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
443
i64, ptr, ptr, ptr, i32)
444
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
445
index XXXXXXX..XXXXXXX 100644
446
--- a/target/arm/tcg/vec_helper.c
447
+++ b/target/arm/tcg/vec_helper.c
448
@@ -XXX,XX +XXX,XX @@ DO_DOT_IDX(gvec_sdot_idx_h, int64_t, int16_t, int16_t, H8)
449
DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, H8)
450
451
void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
452
- void *vfpst, uint32_t desc)
453
+ float_status *fpst, uint32_t desc)
454
{
455
uintptr_t opr_sz = simd_oprsz(desc);
456
float16 *d = vd;
457
float16 *n = vn;
458
float16 *m = vm;
459
- float_status *fpst = vfpst;
460
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
461
uint32_t neg_imag = neg_real ^ 1;
462
uintptr_t i;
463
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
464
}
465
466
void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
467
- void *vfpst, uint32_t desc)
468
+ float_status *fpst, uint32_t desc)
469
{
470
uintptr_t opr_sz = simd_oprsz(desc);
471
float32 *d = vd;
472
float32 *n = vn;
473
float32 *m = vm;
474
- float_status *fpst = vfpst;
475
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
476
uint32_t neg_imag = neg_real ^ 1;
477
uintptr_t i;
478
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
479
}
480
481
void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
482
- void *vfpst, uint32_t desc)
483
+ float_status *fpst, uint32_t desc)
484
{
485
uintptr_t opr_sz = simd_oprsz(desc);
486
float64 *d = vd;
487
float64 *n = vn;
488
float64 *m = vm;
489
- float_status *fpst = vfpst;
490
uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
491
uint64_t neg_imag = neg_real ^ 1;
492
uintptr_t i;
493
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
494
}
495
496
void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va,
497
- void *vfpst, uint32_t desc)
498
+ float_status *fpst, uint32_t desc)
499
{
500
uintptr_t opr_sz = simd_oprsz(desc);
501
float16 *d = vd, *n = vn, *m = vm, *a = va;
502
- float_status *fpst = vfpst;
503
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
504
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
505
uint32_t neg_real = flip ^ neg_imag;
506
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va,
507
}
508
509
void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
510
- void *vfpst, uint32_t desc)
511
+ float_status *fpst, uint32_t desc)
512
{
513
uintptr_t opr_sz = simd_oprsz(desc);
514
float16 *d = vd, *n = vn, *m = vm, *a = va;
515
- float_status *fpst = vfpst;
516
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
517
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
518
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
519
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
520
}
521
522
void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va,
523
- void *vfpst, uint32_t desc)
524
+ float_status *fpst, uint32_t desc)
525
{
526
uintptr_t opr_sz = simd_oprsz(desc);
527
float32 *d = vd, *n = vn, *m = vm, *a = va;
528
- float_status *fpst = vfpst;
529
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
530
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
531
uint32_t neg_real = flip ^ neg_imag;
532
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va,
533
}
534
535
void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
536
- void *vfpst, uint32_t desc)
537
+ float_status *fpst, uint32_t desc)
538
{
539
uintptr_t opr_sz = simd_oprsz(desc);
540
float32 *d = vd, *n = vn, *m = vm, *a = va;
541
- float_status *fpst = vfpst;
542
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
543
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
544
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
545
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
546
}
547
548
void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, void *va,
549
- void *vfpst, uint32_t desc)
550
+ float_status *fpst, uint32_t desc)
551
{
552
uintptr_t opr_sz = simd_oprsz(desc);
553
float64 *d = vd, *n = vn, *m = vm, *a = va;
554
- float_status *fpst = vfpst;
555
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
556
uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
557
uint64_t neg_real = flip ^ neg_imag;
558
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_acgt(float64 op1, float64 op2, float_status *stat)
559
return -float64_lt(float64_abs(op2), float64_abs(op1), stat);
560
}
561
562
-static int16_t vfp_tosszh(float16 x, void *fpstp)
563
+static int16_t vfp_tosszh(float16 x, float_status *fpst)
564
{
565
- float_status *fpst = fpstp;
566
if (float16_is_any_nan(x)) {
567
float_raise(float_flag_invalid, fpst);
568
return 0;
569
@@ -XXX,XX +XXX,XX @@ static int16_t vfp_tosszh(float16 x, void *fpstp)
570
return float16_to_int16_round_to_zero(x, fpst);
571
}
572
573
-static uint16_t vfp_touszh(float16 x, void *fpstp)
574
+static uint16_t vfp_touszh(float16 x, float_status *fpst)
575
{
576
- float_status *fpst = fpstp;
577
if (float16_is_any_nan(x)) {
578
float_raise(float_flag_invalid, fpst);
579
return 0;
580
@@ -XXX,XX +XXX,XX @@ static uint16_t vfp_touszh(float16 x, void *fpstp)
581
}
582
583
#define DO_2OP(NAME, FUNC, TYPE) \
584
-void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
585
+void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
586
{ \
587
intptr_t i, oprsz = simd_oprsz(desc); \
588
TYPE *d = vd, *n = vn; \
589
@@ -XXX,XX +XXX,XX @@ static float32 float32_rsqrts_nf(float32 op1, float32 op2, float_status *stat)
590
}
591
592
#define DO_3OP(NAME, FUNC, TYPE) \
593
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
594
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
595
+ float_status *stat, uint32_t desc) \
596
{ \
597
intptr_t i, oprsz = simd_oprsz(desc); \
598
TYPE *d = vd, *n = vn, *m = vm; \
599
@@ -XXX,XX +XXX,XX @@ static float64 float64_mulsub_f(float64 dest, float64 op1, float64 op2,
600
return float64_muladd(float64_chs(op1), op2, dest, 0, stat);
601
}
602
603
-#define DO_MULADD(NAME, FUNC, TYPE) \
604
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
605
+#define DO_MULADD(NAME, FUNC, TYPE) \
606
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
607
+ float_status *stat, uint32_t desc) \
608
{ \
609
intptr_t i, oprsz = simd_oprsz(desc); \
610
TYPE *d = vd, *n = vn, *m = vm; \
611
@@ -XXX,XX +XXX,XX @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8)
612
#undef DO_MLA_IDX
613
614
#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) \
615
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
616
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
617
+ float_status *stat, uint32_t desc) \
618
{ \
619
intptr_t i, j, oprsz = simd_oprsz(desc); \
620
intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \
621
@@ -XXX,XX +XXX,XX @@ DO_FMUL_IDX(gvec_fmls_nf_idx_s, float32_sub, float32_mul, float32, H4)
622
623
#define DO_FMLA_IDX(NAME, TYPE, H) \
624
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
625
- void *stat, uint32_t desc) \
626
+ float_status *stat, uint32_t desc) \
627
{ \
628
intptr_t i, j, oprsz = simd_oprsz(desc); \
629
intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \
630
@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)
631
#undef DO_ABA
632
633
#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \
634
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
635
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
636
+ float_status *stat, uint32_t desc) \
637
{ \
638
ARMVectorReg scratch; \
639
intptr_t oprsz = simd_oprsz(desc); \
640
@@ -XXX,XX +XXX,XX @@ DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4)
641
#undef DO_3OP_PAIR
642
643
#define DO_VCVT_FIXED(NAME, FUNC, TYPE) \
644
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
645
+ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
646
{ \
647
intptr_t i, oprsz = simd_oprsz(desc); \
648
int shift = simd_data(desc); \
649
@@ -XXX,XX +XXX,XX @@ DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
650
#undef DO_VCVT_FIXED
651
652
#define DO_VCVT_RMODE(NAME, FUNC, TYPE) \
653
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
654
+ void HELPER(NAME)(void *vd, void *vn, float_status *fpst, uint32_t desc) \
655
{ \
656
- float_status *fpst = stat; \
657
intptr_t i, oprsz = simd_oprsz(desc); \
658
uint32_t rmode = simd_data(desc); \
659
uint32_t prev_rmode = get_float_rounding_mode(fpst); \
660
@@ -XXX,XX +XXX,XX @@ DO_VCVT_RMODE(gvec_vcvt_rm_uh, helper_vfp_touhh, uint16_t)
661
#undef DO_VCVT_RMODE
662
663
#define DO_VRINT_RMODE(NAME, FUNC, TYPE) \
664
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
665
+ void HELPER(NAME)(void *vd, void *vn, float_status *fpst, uint32_t desc) \
666
{ \
667
- float_status *fpst = stat; \
668
intptr_t i, oprsz = simd_oprsz(desc); \
669
uint32_t rmode = simd_data(desc); \
670
uint32_t prev_rmode = get_float_rounding_mode(fpst); \
671
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va,
672
}
673
674
void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va,
675
- void *stat, uint32_t desc)
676
+ float_status *stat, uint32_t desc)
677
{
678
intptr_t i, opr_sz = simd_oprsz(desc);
679
intptr_t sel = simd_data(desc);
680
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va,
681
}
682
683
void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm,
684
- void *va, void *stat, uint32_t desc)
685
+ void *va, float_status *stat, uint32_t desc)
686
{
687
intptr_t i, j, opr_sz = simd_oprsz(desc);
688
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT, 1);
49
--
689
--
50
2.25.1
690
2.34.1
51
691
52
692
diff view generated by jsdifflib
[PULL 07/18] util: Put qemu_vfree() in memalign.c
[PULL 05/19] target/arm: Convert neon_helper.c to fpst alias
1
qemu_vfree() is the companion free function to qemu_memalign(); put
1
From: Richard Henderson <richard.henderson@linaro.org>
2
it in memalign.c so the allocation and free functions are together.
3
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-6-richard.henderson@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220226180723.1706285-9-peter.maydell@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
---
7
---
9
util/memalign.c | 11 +++++++++++
8
target/arm/helper.h | 14 +++++++-------
10
util/oslib-posix.c | 6 ------
9
target/arm/tcg/neon_helper.c | 21 +++++++--------------
11
util/oslib-win32.c | 6 ------
10
2 files changed, 14 insertions(+), 21 deletions(-)
12
3 files changed, 11 insertions(+), 12 deletions(-)
13
11
14
diff --git a/util/memalign.c b/util/memalign.c
12
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/util/memalign.c
14
--- a/target/arm/helper.h
17
+++ b/util/memalign.c
15
+++ b/target/arm/helper.h
18
@@ -XXX,XX +XXX,XX @@ void *qemu_memalign(size_t alignment, size_t size)
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32)
19
size, alignment, strerror(errno));
17
DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32)
20
abort();
18
DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64)
19
20
-DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr)
21
-DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr)
22
-DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr)
23
-DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr)
24
-DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr)
25
-DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr)
26
-DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr)
27
+DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst)
28
+DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst)
29
+DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst)
30
+DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst)
31
+DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst)
32
+DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst)
33
+DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst)
34
35
/* iwmmxt_helper.c */
36
DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64)
37
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/tcg/neon_helper.c
40
+++ b/target/arm/tcg/neon_helper.c
41
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x)
42
* Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do.
43
* Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires.
44
*/
45
-uint32_t HELPER(neon_ceq_f32)(uint32_t a, uint32_t b, void *fpstp)
46
+uint32_t HELPER(neon_ceq_f32)(uint32_t a, uint32_t b, float_status *fpst)
47
{
48
- float_status *fpst = fpstp;
49
return -float32_eq_quiet(make_float32(a), make_float32(b), fpst);
21
}
50
}
22
+
51
23
+void qemu_vfree(void *ptr)
52
-uint32_t HELPER(neon_cge_f32)(uint32_t a, uint32_t b, void *fpstp)
24
+{
53
+uint32_t HELPER(neon_cge_f32)(uint32_t a, uint32_t b, float_status *fpst)
25
+ trace_qemu_vfree(ptr);
54
{
26
+#if !defined(CONFIG_POSIX_MEMALIGN) && defined(CONFIG_ALIGNED_MALLOC)
55
- float_status *fpst = fpstp;
27
+ /* Only Windows _aligned_malloc needs a special free function */
56
return -float32_le(make_float32(b), make_float32(a), fpst);
28
+ _aligned_free(ptr);
29
+#else
30
+ free(ptr);
31
+#endif
32
+}
33
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/util/oslib-posix.c
36
+++ b/util/oslib-posix.c
37
@@ -XXX,XX +XXX,XX @@ void *qemu_anon_ram_alloc(size_t size, uint64_t *alignment, bool shared,
38
return ptr;
39
}
57
}
40
58
41
-void qemu_vfree(void *ptr)
59
-uint32_t HELPER(neon_cgt_f32)(uint32_t a, uint32_t b, void *fpstp)
42
-{
60
+uint32_t HELPER(neon_cgt_f32)(uint32_t a, uint32_t b, float_status *fpst)
43
- trace_qemu_vfree(ptr);
44
- free(ptr);
45
-}
46
-
47
void qemu_anon_ram_free(void *ptr, size_t size)
48
{
61
{
49
trace_qemu_anon_ram_free(ptr, size);
62
- float_status *fpst = fpstp;
50
diff --git a/util/oslib-win32.c b/util/oslib-win32.c
63
return -float32_lt(make_float32(b), make_float32(a), fpst);
51
index XXXXXXX..XXXXXXX 100644
52
--- a/util/oslib-win32.c
53
+++ b/util/oslib-win32.c
54
@@ -XXX,XX +XXX,XX @@ void *qemu_anon_ram_alloc(size_t size, uint64_t *align, bool shared,
55
return ptr;
56
}
64
}
57
65
58
-void qemu_vfree(void *ptr)
66
-uint32_t HELPER(neon_acge_f32)(uint32_t a, uint32_t b, void *fpstp)
59
-{
67
+uint32_t HELPER(neon_acge_f32)(uint32_t a, uint32_t b, float_status *fpst)
60
- trace_qemu_vfree(ptr);
61
- _aligned_free(ptr);
62
-}
63
-
64
void qemu_anon_ram_free(void *ptr, size_t size)
65
{
68
{
66
trace_qemu_anon_ram_free(ptr, size);
69
- float_status *fpst = fpstp;
70
float32 f0 = float32_abs(make_float32(a));
71
float32 f1 = float32_abs(make_float32(b));
72
return -float32_le(f1, f0, fpst);
73
}
74
75
-uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, void *fpstp)
76
+uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, float_status *fpst)
77
{
78
- float_status *fpst = fpstp;
79
float32 f0 = float32_abs(make_float32(a));
80
float32 f1 = float32_abs(make_float32(b));
81
return -float32_lt(f1, f0, fpst);
82
}
83
84
-uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, void *fpstp)
85
+uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, float_status *fpst)
86
{
87
- float_status *fpst = fpstp;
88
float64 f0 = float64_abs(make_float64(a));
89
float64 f1 = float64_abs(make_float64(b));
90
return -float64_le(f1, f0, fpst);
91
}
92
93
-uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, void *fpstp)
94
+uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, float_status *fpst)
95
{
96
- float_status *fpst = fpstp;
97
float64 f0 = float64_abs(make_float64(a));
98
float64 f1 = float64_abs(make_float64(b));
99
return -float64_lt(f1, f0, fpst);
67
--
100
--
68
2.25.1
101
2.34.1
69
102
70
103
diff view generated by jsdifflib
[PULL 04/18] meson.build: Don't misdetect posix_memalign() on Windows
[PULL 06/19] target/arm: Convert sve_helper.c to fpst alias
1
Currently we incorrectly think that posix_memalign() exists on
1
From: Richard Henderson <richard.henderson@linaro.org>
2
Windows. This is because of a combination of:
3
2
4
* the msys2/mingw toolchain/libc claim to have a
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
__builtin_posix_memalign when there isn't a builtin of that name
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
* meson will assume that if you have a __builtin_foo that
5
Message-id: 20241206031224.78525-7-richard.henderson@linaro.org
7
counts for has_function('foo')
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/tcg/helper-sve.h | 414 ++++++++++++++++++------------------
9
target/arm/tcg/sve_helper.c | 96 +++++----
10
2 files changed, 258 insertions(+), 252 deletions(-)
8
11
9
Specifying a specific include file via prefix: causes meson to not
12
diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h
10
treat builtins as sufficient and actually look for the function
11
itself; see this meson pull request which added that as the official
12
way to get the right answer:
13
https://github.com/mesonbuild/meson/pull/1150
14
15
Currently this misdectection doesn't cause problems because we only
16
use CONFIG_POSIX_MEMALIGN in oslib-posix.c; however that will change
17
in a following commit.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20220226180723.1706285-6-peter.maydell@linaro.org
22
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
---
24
meson.build | 4 +++-
25
1 file changed, 3 insertions(+), 1 deletion(-)
26
27
diff --git a/meson.build b/meson.build
28
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
29
--- a/meson.build
14
--- a/target/arm/tcg/helper-sve.h
30
+++ b/meson.build
15
+++ b/target/arm/tcg/helper-sve.h
31
@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_CLOCK_ADJTIME', cc.has_function('clock_adjtime'))
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
32
config_host_data.set('CONFIG_DUP3', cc.has_function('dup3'))
17
void, ptr, ptr, ptr, fpst, i32)
33
config_host_data.set('CONFIG_FALLOCATE', cc.has_function('fallocate'))
18
34
config_host_data.set('CONFIG_POSIX_FALLOCATE', cc.has_function('posix_fallocate'))
19
DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
35
-config_host_data.set('CONFIG_POSIX_MEMALIGN', cc.has_function('posix_memalign'))
20
- i64, ptr, ptr, ptr, i32)
36
+# Note that we need to specify prefix: here to avoid incorrectly
21
+ i64, ptr, ptr, fpst, i32)
37
+# thinking that Windows has posix_memalign()
22
DEF_HELPER_FLAGS_4(sve_faddv_s, TCG_CALL_NO_RWG,
38
+config_host_data.set('CONFIG_POSIX_MEMALIGN', cc.has_function('posix_memalign', prefix: '#include <stdlib.h>'))
23
- i64, ptr, ptr, ptr, i32)
39
config_host_data.set('CONFIG_PPOLL', cc.has_function('ppoll'))
24
+ i64, ptr, ptr, fpst, i32)
40
config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))
25
DEF_HELPER_FLAGS_4(sve_faddv_d, TCG_CALL_NO_RWG,
41
config_host_data.set('CONFIG_SEM_TIMEDWAIT', cc.has_function('sem_timedwait', dependencies: threads))
26
- i64, ptr, ptr, ptr, i32)
27
+ i64, ptr, ptr, fpst, i32)
28
29
DEF_HELPER_FLAGS_4(sve_fmaxnmv_h, TCG_CALL_NO_RWG,
30
- i64, ptr, ptr, ptr, i32)
31
+ i64, ptr, ptr, fpst, i32)
32
DEF_HELPER_FLAGS_4(sve_fmaxnmv_s, TCG_CALL_NO_RWG,
33
- i64, ptr, ptr, ptr, i32)
34
+ i64, ptr, ptr, fpst, i32)
35
DEF_HELPER_FLAGS_4(sve_fmaxnmv_d, TCG_CALL_NO_RWG,
36
- i64, ptr, ptr, ptr, i32)
37
+ i64, ptr, ptr, fpst, i32)
38
39
DEF_HELPER_FLAGS_4(sve_fminnmv_h, TCG_CALL_NO_RWG,
40
- i64, ptr, ptr, ptr, i32)
41
+ i64, ptr, ptr, fpst, i32)
42
DEF_HELPER_FLAGS_4(sve_fminnmv_s, TCG_CALL_NO_RWG,
43
- i64, ptr, ptr, ptr, i32)
44
+ i64, ptr, ptr, fpst, i32)
45
DEF_HELPER_FLAGS_4(sve_fminnmv_d, TCG_CALL_NO_RWG,
46
- i64, ptr, ptr, ptr, i32)
47
+ i64, ptr, ptr, fpst, i32)
48
49
DEF_HELPER_FLAGS_4(sve_fmaxv_h, TCG_CALL_NO_RWG,
50
- i64, ptr, ptr, ptr, i32)
51
+ i64, ptr, ptr, fpst, i32)
52
DEF_HELPER_FLAGS_4(sve_fmaxv_s, TCG_CALL_NO_RWG,
53
- i64, ptr, ptr, ptr, i32)
54
+ i64, ptr, ptr, fpst, i32)
55
DEF_HELPER_FLAGS_4(sve_fmaxv_d, TCG_CALL_NO_RWG,
56
- i64, ptr, ptr, ptr, i32)
57
+ i64, ptr, ptr, fpst, i32)
58
59
DEF_HELPER_FLAGS_4(sve_fminv_h, TCG_CALL_NO_RWG,
60
- i64, ptr, ptr, ptr, i32)
61
+ i64, ptr, ptr, fpst, i32)
62
DEF_HELPER_FLAGS_4(sve_fminv_s, TCG_CALL_NO_RWG,
63
- i64, ptr, ptr, ptr, i32)
64
+ i64, ptr, ptr, fpst, i32)
65
DEF_HELPER_FLAGS_4(sve_fminv_d, TCG_CALL_NO_RWG,
66
- i64, ptr, ptr, ptr, i32)
67
+ i64, ptr, ptr, fpst, i32)
68
69
DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
70
- i64, i64, ptr, ptr, ptr, i32)
71
+ i64, i64, ptr, ptr, fpst, i32)
72
DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
73
- i64, i64, ptr, ptr, ptr, i32)
74
+ i64, i64, ptr, ptr, fpst, i32)
75
DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,
76
- i64, i64, ptr, ptr, ptr, i32)
77
+ i64, i64, ptr, ptr, fpst, i32)
78
79
DEF_HELPER_FLAGS_5(sve_fcmge0_h, TCG_CALL_NO_RWG,
80
- void, ptr, ptr, ptr, ptr, i32)
81
+ void, ptr, ptr, ptr, fpst, i32)
82
DEF_HELPER_FLAGS_5(sve_fcmge0_s, TCG_CALL_NO_RWG,
83
- void, ptr, ptr, ptr, ptr, i32)
84
+ void, ptr, ptr, ptr, fpst, i32)
85
DEF_HELPER_FLAGS_5(sve_fcmge0_d, TCG_CALL_NO_RWG,
86
- void, ptr, ptr, ptr, ptr, i32)
87
+ void, ptr, ptr, ptr, fpst, i32)
88
89
DEF_HELPER_FLAGS_5(sve_fcmgt0_h, TCG_CALL_NO_RWG,
90
- void, ptr, ptr, ptr, ptr, i32)
91
+ void, ptr, ptr, ptr, fpst, i32)
92
DEF_HELPER_FLAGS_5(sve_fcmgt0_s, TCG_CALL_NO_RWG,
93
- void, ptr, ptr, ptr, ptr, i32)
94
+ void, ptr, ptr, ptr, fpst, i32)
95
DEF_HELPER_FLAGS_5(sve_fcmgt0_d, TCG_CALL_NO_RWG,
96
- void, ptr, ptr, ptr, ptr, i32)
97
+ void, ptr, ptr, ptr, fpst, i32)
98
99
DEF_HELPER_FLAGS_5(sve_fcmlt0_h, TCG_CALL_NO_RWG,
100
- void, ptr, ptr, ptr, ptr, i32)
101
+ void, ptr, ptr, ptr, fpst, i32)
102
DEF_HELPER_FLAGS_5(sve_fcmlt0_s, TCG_CALL_NO_RWG,
103
- void, ptr, ptr, ptr, ptr, i32)
104
+ void, ptr, ptr, ptr, fpst, i32)
105
DEF_HELPER_FLAGS_5(sve_fcmlt0_d, TCG_CALL_NO_RWG,
106
- void, ptr, ptr, ptr, ptr, i32)
107
+ void, ptr, ptr, ptr, fpst, i32)
108
109
DEF_HELPER_FLAGS_5(sve_fcmle0_h, TCG_CALL_NO_RWG,
110
- void, ptr, ptr, ptr, ptr, i32)
111
+ void, ptr, ptr, ptr, fpst, i32)
112
DEF_HELPER_FLAGS_5(sve_fcmle0_s, TCG_CALL_NO_RWG,
113
- void, ptr, ptr, ptr, ptr, i32)
114
+ void, ptr, ptr, ptr, fpst, i32)
115
DEF_HELPER_FLAGS_5(sve_fcmle0_d, TCG_CALL_NO_RWG,
116
- void, ptr, ptr, ptr, ptr, i32)
117
+ void, ptr, ptr, ptr, fpst, i32)
118
119
DEF_HELPER_FLAGS_5(sve_fcmeq0_h, TCG_CALL_NO_RWG,
120
- void, ptr, ptr, ptr, ptr, i32)
121
+ void, ptr, ptr, ptr, fpst, i32)
122
DEF_HELPER_FLAGS_5(sve_fcmeq0_s, TCG_CALL_NO_RWG,
123
- void, ptr, ptr, ptr, ptr, i32)
124
+ void, ptr, ptr, ptr, fpst, i32)
125
DEF_HELPER_FLAGS_5(sve_fcmeq0_d, TCG_CALL_NO_RWG,
126
- void, ptr, ptr, ptr, ptr, i32)
127
+ void, ptr, ptr, ptr, fpst, i32)
128
129
DEF_HELPER_FLAGS_5(sve_fcmne0_h, TCG_CALL_NO_RWG,
130
- void, ptr, ptr, ptr, ptr, i32)
131
+ void, ptr, ptr, ptr, fpst, i32)
132
DEF_HELPER_FLAGS_5(sve_fcmne0_s, TCG_CALL_NO_RWG,
133
- void, ptr, ptr, ptr, ptr, i32)
134
+ void, ptr, ptr, ptr, fpst, i32)
135
DEF_HELPER_FLAGS_5(sve_fcmne0_d, TCG_CALL_NO_RWG,
136
- void, ptr, ptr, ptr, ptr, i32)
137
+ void, ptr, ptr, ptr, fpst, i32)
138
139
DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
140
- void, ptr, ptr, ptr, ptr, ptr, i32)
141
+ void, ptr, ptr, ptr, ptr, fpst, i32)
142
DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,
143
- void, ptr, ptr, ptr, ptr, ptr, i32)
144
+ void, ptr, ptr, ptr, ptr, fpst, i32)
145
DEF_HELPER_FLAGS_6(sve_fadd_d, TCG_CALL_NO_RWG,
146
- void, ptr, ptr, ptr, ptr, ptr, i32)
147
+ void, ptr, ptr, ptr, ptr, fpst, i32)
148
149
DEF_HELPER_FLAGS_6(sve_fsub_h, TCG_CALL_NO_RWG,
150
- void, ptr, ptr, ptr, ptr, ptr, i32)
151
+ void, ptr, ptr, ptr, ptr, fpst, i32)
152
DEF_HELPER_FLAGS_6(sve_fsub_s, TCG_CALL_NO_RWG,
153
- void, ptr, ptr, ptr, ptr, ptr, i32)
154
+ void, ptr, ptr, ptr, ptr, fpst, i32)
155
DEF_HELPER_FLAGS_6(sve_fsub_d, TCG_CALL_NO_RWG,
156
- void, ptr, ptr, ptr, ptr, ptr, i32)
157
+ void, ptr, ptr, ptr, ptr, fpst, i32)
158
159
DEF_HELPER_FLAGS_6(sve_fmul_h, TCG_CALL_NO_RWG,
160
- void, ptr, ptr, ptr, ptr, ptr, i32)
161
+ void, ptr, ptr, ptr, ptr, fpst, i32)
162
DEF_HELPER_FLAGS_6(sve_fmul_s, TCG_CALL_NO_RWG,
163
- void, ptr, ptr, ptr, ptr, ptr, i32)
164
+ void, ptr, ptr, ptr, ptr, fpst, i32)
165
DEF_HELPER_FLAGS_6(sve_fmul_d, TCG_CALL_NO_RWG,
166
- void, ptr, ptr, ptr, ptr, ptr, i32)
167
+ void, ptr, ptr, ptr, ptr, fpst, i32)
168
169
DEF_HELPER_FLAGS_6(sve_fdiv_h, TCG_CALL_NO_RWG,
170
- void, ptr, ptr, ptr, ptr, ptr, i32)
171
+ void, ptr, ptr, ptr, ptr, fpst, i32)
172
DEF_HELPER_FLAGS_6(sve_fdiv_s, TCG_CALL_NO_RWG,
173
- void, ptr, ptr, ptr, ptr, ptr, i32)
174
+ void, ptr, ptr, ptr, ptr, fpst, i32)
175
DEF_HELPER_FLAGS_6(sve_fdiv_d, TCG_CALL_NO_RWG,
176
- void, ptr, ptr, ptr, ptr, ptr, i32)
177
+ void, ptr, ptr, ptr, ptr, fpst, i32)
178
179
DEF_HELPER_FLAGS_6(sve_fmin_h, TCG_CALL_NO_RWG,
180
- void, ptr, ptr, ptr, ptr, ptr, i32)
181
+ void, ptr, ptr, ptr, ptr, fpst, i32)
182
DEF_HELPER_FLAGS_6(sve_fmin_s, TCG_CALL_NO_RWG,
183
- void, ptr, ptr, ptr, ptr, ptr, i32)
184
+ void, ptr, ptr, ptr, ptr, fpst, i32)
185
DEF_HELPER_FLAGS_6(sve_fmin_d, TCG_CALL_NO_RWG,
186
- void, ptr, ptr, ptr, ptr, ptr, i32)
187
+ void, ptr, ptr, ptr, ptr, fpst, i32)
188
189
DEF_HELPER_FLAGS_6(sve_fmax_h, TCG_CALL_NO_RWG,
190
- void, ptr, ptr, ptr, ptr, ptr, i32)
191
+ void, ptr, ptr, ptr, ptr, fpst, i32)
192
DEF_HELPER_FLAGS_6(sve_fmax_s, TCG_CALL_NO_RWG,
193
- void, ptr, ptr, ptr, ptr, ptr, i32)
194
+ void, ptr, ptr, ptr, ptr, fpst, i32)
195
DEF_HELPER_FLAGS_6(sve_fmax_d, TCG_CALL_NO_RWG,
196
- void, ptr, ptr, ptr, ptr, ptr, i32)
197
+ void, ptr, ptr, ptr, ptr, fpst, i32)
198
199
DEF_HELPER_FLAGS_6(sve_fminnum_h, TCG_CALL_NO_RWG,
200
- void, ptr, ptr, ptr, ptr, ptr, i32)
201
+ void, ptr, ptr, ptr, ptr, fpst, i32)
202
DEF_HELPER_FLAGS_6(sve_fminnum_s, TCG_CALL_NO_RWG,
203
- void, ptr, ptr, ptr, ptr, ptr, i32)
204
+ void, ptr, ptr, ptr, ptr, fpst, i32)
205
DEF_HELPER_FLAGS_6(sve_fminnum_d, TCG_CALL_NO_RWG,
206
- void, ptr, ptr, ptr, ptr, ptr, i32)
207
+ void, ptr, ptr, ptr, ptr, fpst, i32)
208
209
DEF_HELPER_FLAGS_6(sve_fmaxnum_h, TCG_CALL_NO_RWG,
210
- void, ptr, ptr, ptr, ptr, ptr, i32)
211
+ void, ptr, ptr, ptr, ptr, fpst, i32)
212
DEF_HELPER_FLAGS_6(sve_fmaxnum_s, TCG_CALL_NO_RWG,
213
- void, ptr, ptr, ptr, ptr, ptr, i32)
214
+ void, ptr, ptr, ptr, ptr, fpst, i32)
215
DEF_HELPER_FLAGS_6(sve_fmaxnum_d, TCG_CALL_NO_RWG,
216
- void, ptr, ptr, ptr, ptr, ptr, i32)
217
+ void, ptr, ptr, ptr, ptr, fpst, i32)
218
219
DEF_HELPER_FLAGS_6(sve_fabd_h, TCG_CALL_NO_RWG,
220
- void, ptr, ptr, ptr, ptr, ptr, i32)
221
+ void, ptr, ptr, ptr, ptr, fpst, i32)
222
DEF_HELPER_FLAGS_6(sve_fabd_s, TCG_CALL_NO_RWG,
223
- void, ptr, ptr, ptr, ptr, ptr, i32)
224
+ void, ptr, ptr, ptr, ptr, fpst, i32)
225
DEF_HELPER_FLAGS_6(sve_fabd_d, TCG_CALL_NO_RWG,
226
- void, ptr, ptr, ptr, ptr, ptr, i32)
227
+ void, ptr, ptr, ptr, ptr, fpst, i32)
228
229
DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG,
230
- void, ptr, ptr, ptr, ptr, ptr, i32)
231
+ void, ptr, ptr, ptr, ptr, fpst, i32)
232
DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG,
233
- void, ptr, ptr, ptr, ptr, ptr, i32)
234
+ void, ptr, ptr, ptr, ptr, fpst, i32)
235
DEF_HELPER_FLAGS_6(sve_fscalbn_d, TCG_CALL_NO_RWG,
236
- void, ptr, ptr, ptr, ptr, ptr, i32)
237
+ void, ptr, ptr, ptr, ptr, fpst, i32)
238
239
DEF_HELPER_FLAGS_6(sve_fmulx_h, TCG_CALL_NO_RWG,
240
- void, ptr, ptr, ptr, ptr, ptr, i32)
241
+ void, ptr, ptr, ptr, ptr, fpst, i32)
242
DEF_HELPER_FLAGS_6(sve_fmulx_s, TCG_CALL_NO_RWG,
243
- void, ptr, ptr, ptr, ptr, ptr, i32)
244
+ void, ptr, ptr, ptr, ptr, fpst, i32)
245
DEF_HELPER_FLAGS_6(sve_fmulx_d, TCG_CALL_NO_RWG,
246
- void, ptr, ptr, ptr, ptr, ptr, i32)
247
+ void, ptr, ptr, ptr, ptr, fpst, i32)
248
249
DEF_HELPER_FLAGS_6(sve_fadds_h, TCG_CALL_NO_RWG,
250
- void, ptr, ptr, ptr, i64, ptr, i32)
251
+ void, ptr, ptr, ptr, i64, fpst, i32)
252
DEF_HELPER_FLAGS_6(sve_fadds_s, TCG_CALL_NO_RWG,
253
- void, ptr, ptr, ptr, i64, ptr, i32)
254
+ void, ptr, ptr, ptr, i64, fpst, i32)
255
DEF_HELPER_FLAGS_6(sve_fadds_d, TCG_CALL_NO_RWG,
256
- void, ptr, ptr, ptr, i64, ptr, i32)
257
+ void, ptr, ptr, ptr, i64, fpst, i32)
258
259
DEF_HELPER_FLAGS_6(sve_fsubs_h, TCG_CALL_NO_RWG,
260
- void, ptr, ptr, ptr, i64, ptr, i32)
261
+ void, ptr, ptr, ptr, i64, fpst, i32)
262
DEF_HELPER_FLAGS_6(sve_fsubs_s, TCG_CALL_NO_RWG,
263
- void, ptr, ptr, ptr, i64, ptr, i32)
264
+ void, ptr, ptr, ptr, i64, fpst, i32)
265
DEF_HELPER_FLAGS_6(sve_fsubs_d, TCG_CALL_NO_RWG,
266
- void, ptr, ptr, ptr, i64, ptr, i32)
267
+ void, ptr, ptr, ptr, i64, fpst, i32)
268
269
DEF_HELPER_FLAGS_6(sve_fmuls_h, TCG_CALL_NO_RWG,
270
- void, ptr, ptr, ptr, i64, ptr, i32)
271
+ void, ptr, ptr, ptr, i64, fpst, i32)
272
DEF_HELPER_FLAGS_6(sve_fmuls_s, TCG_CALL_NO_RWG,
273
- void, ptr, ptr, ptr, i64, ptr, i32)
274
+ void, ptr, ptr, ptr, i64, fpst, i32)
275
DEF_HELPER_FLAGS_6(sve_fmuls_d, TCG_CALL_NO_RWG,
276
- void, ptr, ptr, ptr, i64, ptr, i32)
277
+ void, ptr, ptr, ptr, i64, fpst, i32)
278
279
DEF_HELPER_FLAGS_6(sve_fsubrs_h, TCG_CALL_NO_RWG,
280
- void, ptr, ptr, ptr, i64, ptr, i32)
281
+ void, ptr, ptr, ptr, i64, fpst, i32)
282
DEF_HELPER_FLAGS_6(sve_fsubrs_s, TCG_CALL_NO_RWG,
283
- void, ptr, ptr, ptr, i64, ptr, i32)
284
+ void, ptr, ptr, ptr, i64, fpst, i32)
285
DEF_HELPER_FLAGS_6(sve_fsubrs_d, TCG_CALL_NO_RWG,
286
- void, ptr, ptr, ptr, i64, ptr, i32)
287
+ void, ptr, ptr, ptr, i64, fpst, i32)
288
289
DEF_HELPER_FLAGS_6(sve_fmaxnms_h, TCG_CALL_NO_RWG,
290
- void, ptr, ptr, ptr, i64, ptr, i32)
291
+ void, ptr, ptr, ptr, i64, fpst, i32)
292
DEF_HELPER_FLAGS_6(sve_fmaxnms_s, TCG_CALL_NO_RWG,
293
- void, ptr, ptr, ptr, i64, ptr, i32)
294
+ void, ptr, ptr, ptr, i64, fpst, i32)
295
DEF_HELPER_FLAGS_6(sve_fmaxnms_d, TCG_CALL_NO_RWG,
296
- void, ptr, ptr, ptr, i64, ptr, i32)
297
+ void, ptr, ptr, ptr, i64, fpst, i32)
298
299
DEF_HELPER_FLAGS_6(sve_fminnms_h, TCG_CALL_NO_RWG,
300
- void, ptr, ptr, ptr, i64, ptr, i32)
301
+ void, ptr, ptr, ptr, i64, fpst, i32)
302
DEF_HELPER_FLAGS_6(sve_fminnms_s, TCG_CALL_NO_RWG,
303
- void, ptr, ptr, ptr, i64, ptr, i32)
304
+ void, ptr, ptr, ptr, i64, fpst, i32)
305
DEF_HELPER_FLAGS_6(sve_fminnms_d, TCG_CALL_NO_RWG,
306
- void, ptr, ptr, ptr, i64, ptr, i32)
307
+ void, ptr, ptr, ptr, i64, fpst, i32)
308
309
DEF_HELPER_FLAGS_6(sve_fmaxs_h, TCG_CALL_NO_RWG,
310
- void, ptr, ptr, ptr, i64, ptr, i32)
311
+ void, ptr, ptr, ptr, i64, fpst, i32)
312
DEF_HELPER_FLAGS_6(sve_fmaxs_s, TCG_CALL_NO_RWG,
313
- void, ptr, ptr, ptr, i64, ptr, i32)
314
+ void, ptr, ptr, ptr, i64, fpst, i32)
315
DEF_HELPER_FLAGS_6(sve_fmaxs_d, TCG_CALL_NO_RWG,
316
- void, ptr, ptr, ptr, i64, ptr, i32)
317
+ void, ptr, ptr, ptr, i64, fpst, i32)
318
319
DEF_HELPER_FLAGS_6(sve_fmins_h, TCG_CALL_NO_RWG,
320
- void, ptr, ptr, ptr, i64, ptr, i32)
321
+ void, ptr, ptr, ptr, i64, fpst, i32)
322
DEF_HELPER_FLAGS_6(sve_fmins_s, TCG_CALL_NO_RWG,
323
- void, ptr, ptr, ptr, i64, ptr, i32)
324
+ void, ptr, ptr, ptr, i64, fpst, i32)
325
DEF_HELPER_FLAGS_6(sve_fmins_d, TCG_CALL_NO_RWG,
326
- void, ptr, ptr, ptr, i64, ptr, i32)
327
+ void, ptr, ptr, ptr, i64, fpst, i32)
328
329
DEF_HELPER_FLAGS_5(sve_fcvt_sh, TCG_CALL_NO_RWG,
330
- void, ptr, ptr, ptr, ptr, i32)
331
+ void, ptr, ptr, ptr, fpst, i32)
332
DEF_HELPER_FLAGS_5(sve_fcvt_dh, TCG_CALL_NO_RWG,
333
- void, ptr, ptr, ptr, ptr, i32)
334
+ void, ptr, ptr, ptr, fpst, i32)
335
DEF_HELPER_FLAGS_5(sve_fcvt_hs, TCG_CALL_NO_RWG,
336
- void, ptr, ptr, ptr, ptr, i32)
337
+ void, ptr, ptr, ptr, fpst, i32)
338
DEF_HELPER_FLAGS_5(sve_fcvt_ds, TCG_CALL_NO_RWG,
339
- void, ptr, ptr, ptr, ptr, i32)
340
+ void, ptr, ptr, ptr, fpst, i32)
341
DEF_HELPER_FLAGS_5(sve_fcvt_hd, TCG_CALL_NO_RWG,
342
- void, ptr, ptr, ptr, ptr, i32)
343
+ void, ptr, ptr, ptr, fpst, i32)
344
DEF_HELPER_FLAGS_5(sve_fcvt_sd, TCG_CALL_NO_RWG,
345
- void, ptr, ptr, ptr, ptr, i32)
346
+ void, ptr, ptr, ptr, fpst, i32)
347
DEF_HELPER_FLAGS_5(sve_bfcvt, TCG_CALL_NO_RWG,
348
- void, ptr, ptr, ptr, ptr, i32)
349
+ void, ptr, ptr, ptr, fpst, i32)
350
351
DEF_HELPER_FLAGS_5(sve_fcvtzs_hh, TCG_CALL_NO_RWG,
352
- void, ptr, ptr, ptr, ptr, i32)
353
+ void, ptr, ptr, ptr, fpst, i32)
354
DEF_HELPER_FLAGS_5(sve_fcvtzs_hs, TCG_CALL_NO_RWG,
355
- void, ptr, ptr, ptr, ptr, i32)
356
+ void, ptr, ptr, ptr, fpst, i32)
357
DEF_HELPER_FLAGS_5(sve_fcvtzs_ss, TCG_CALL_NO_RWG,
358
- void, ptr, ptr, ptr, ptr, i32)
359
+ void, ptr, ptr, ptr, fpst, i32)
360
DEF_HELPER_FLAGS_5(sve_fcvtzs_ds, TCG_CALL_NO_RWG,
361
- void, ptr, ptr, ptr, ptr, i32)
362
+ void, ptr, ptr, ptr, fpst, i32)
363
DEF_HELPER_FLAGS_5(sve_fcvtzs_hd, TCG_CALL_NO_RWG,
364
- void, ptr, ptr, ptr, ptr, i32)
365
+ void, ptr, ptr, ptr, fpst, i32)
366
DEF_HELPER_FLAGS_5(sve_fcvtzs_sd, TCG_CALL_NO_RWG,
367
- void, ptr, ptr, ptr, ptr, i32)
368
+ void, ptr, ptr, ptr, fpst, i32)
369
DEF_HELPER_FLAGS_5(sve_fcvtzs_dd, TCG_CALL_NO_RWG,
370
- void, ptr, ptr, ptr, ptr, i32)
371
+ void, ptr, ptr, ptr, fpst, i32)
372
373
DEF_HELPER_FLAGS_5(sve_fcvtzu_hh, TCG_CALL_NO_RWG,
374
- void, ptr, ptr, ptr, ptr, i32)
375
+ void, ptr, ptr, ptr, fpst, i32)
376
DEF_HELPER_FLAGS_5(sve_fcvtzu_hs, TCG_CALL_NO_RWG,
377
- void, ptr, ptr, ptr, ptr, i32)
378
+ void, ptr, ptr, ptr, fpst, i32)
379
DEF_HELPER_FLAGS_5(sve_fcvtzu_ss, TCG_CALL_NO_RWG,
380
- void, ptr, ptr, ptr, ptr, i32)
381
+ void, ptr, ptr, ptr, fpst, i32)
382
DEF_HELPER_FLAGS_5(sve_fcvtzu_ds, TCG_CALL_NO_RWG,
383
- void, ptr, ptr, ptr, ptr, i32)
384
+ void, ptr, ptr, ptr, fpst, i32)
385
DEF_HELPER_FLAGS_5(sve_fcvtzu_hd, TCG_CALL_NO_RWG,
386
- void, ptr, ptr, ptr, ptr, i32)
387
+ void, ptr, ptr, ptr, fpst, i32)
388
DEF_HELPER_FLAGS_5(sve_fcvtzu_sd, TCG_CALL_NO_RWG,
389
- void, ptr, ptr, ptr, ptr, i32)
390
+ void, ptr, ptr, ptr, fpst, i32)
391
DEF_HELPER_FLAGS_5(sve_fcvtzu_dd, TCG_CALL_NO_RWG,
392
- void, ptr, ptr, ptr, ptr, i32)
393
+ void, ptr, ptr, ptr, fpst, i32)
394
395
DEF_HELPER_FLAGS_5(sve_frint_h, TCG_CALL_NO_RWG,
396
- void, ptr, ptr, ptr, ptr, i32)
397
+ void, ptr, ptr, ptr, fpst, i32)
398
DEF_HELPER_FLAGS_5(sve_frint_s, TCG_CALL_NO_RWG,
399
- void, ptr, ptr, ptr, ptr, i32)
400
+ void, ptr, ptr, ptr, fpst, i32)
401
DEF_HELPER_FLAGS_5(sve_frint_d, TCG_CALL_NO_RWG,
402
- void, ptr, ptr, ptr, ptr, i32)
403
+ void, ptr, ptr, ptr, fpst, i32)
404
405
DEF_HELPER_FLAGS_5(sve_frintx_h, TCG_CALL_NO_RWG,
406
- void, ptr, ptr, ptr, ptr, i32)
407
+ void, ptr, ptr, ptr, fpst, i32)
408
DEF_HELPER_FLAGS_5(sve_frintx_s, TCG_CALL_NO_RWG,
409
- void, ptr, ptr, ptr, ptr, i32)
410
+ void, ptr, ptr, ptr, fpst, i32)
411
DEF_HELPER_FLAGS_5(sve_frintx_d, TCG_CALL_NO_RWG,
412
- void, ptr, ptr, ptr, ptr, i32)
413
+ void, ptr, ptr, ptr, fpst, i32)
414
415
DEF_HELPER_FLAGS_5(sve_frecpx_h, TCG_CALL_NO_RWG,
416
- void, ptr, ptr, ptr, ptr, i32)
417
+ void, ptr, ptr, ptr, fpst, i32)
418
DEF_HELPER_FLAGS_5(sve_frecpx_s, TCG_CALL_NO_RWG,
419
- void, ptr, ptr, ptr, ptr, i32)
420
+ void, ptr, ptr, ptr, fpst, i32)
421
DEF_HELPER_FLAGS_5(sve_frecpx_d, TCG_CALL_NO_RWG,
422
- void, ptr, ptr, ptr, ptr, i32)
423
+ void, ptr, ptr, ptr, fpst, i32)
424
425
DEF_HELPER_FLAGS_5(sve_fsqrt_h, TCG_CALL_NO_RWG,
426
- void, ptr, ptr, ptr, ptr, i32)
427
+ void, ptr, ptr, ptr, fpst, i32)
428
DEF_HELPER_FLAGS_5(sve_fsqrt_s, TCG_CALL_NO_RWG,
429
- void, ptr, ptr, ptr, ptr, i32)
430
+ void, ptr, ptr, ptr, fpst, i32)
431
DEF_HELPER_FLAGS_5(sve_fsqrt_d, TCG_CALL_NO_RWG,
432
- void, ptr, ptr, ptr, ptr, i32)
433
+ void, ptr, ptr, ptr, fpst, i32)
434
435
DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG,
436
- void, ptr, ptr, ptr, ptr, i32)
437
+ void, ptr, ptr, ptr, fpst, i32)
438
DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG,
439
- void, ptr, ptr, ptr, ptr, i32)
440
+ void, ptr, ptr, ptr, fpst, i32)
441
DEF_HELPER_FLAGS_5(sve_scvt_dh, TCG_CALL_NO_RWG,
442
- void, ptr, ptr, ptr, ptr, i32)
443
+ void, ptr, ptr, ptr, fpst, i32)
444
DEF_HELPER_FLAGS_5(sve_scvt_ss, TCG_CALL_NO_RWG,
445
- void, ptr, ptr, ptr, ptr, i32)
446
+ void, ptr, ptr, ptr, fpst, i32)
447
DEF_HELPER_FLAGS_5(sve_scvt_sd, TCG_CALL_NO_RWG,
448
- void, ptr, ptr, ptr, ptr, i32)
449
+ void, ptr, ptr, ptr, fpst, i32)
450
DEF_HELPER_FLAGS_5(sve_scvt_ds, TCG_CALL_NO_RWG,
451
- void, ptr, ptr, ptr, ptr, i32)
452
+ void, ptr, ptr, ptr, fpst, i32)
453
DEF_HELPER_FLAGS_5(sve_scvt_dd, TCG_CALL_NO_RWG,
454
- void, ptr, ptr, ptr, ptr, i32)
455
+ void, ptr, ptr, ptr, fpst, i32)
456
457
DEF_HELPER_FLAGS_5(sve_ucvt_hh, TCG_CALL_NO_RWG,
458
- void, ptr, ptr, ptr, ptr, i32)
459
+ void, ptr, ptr, ptr, fpst, i32)
460
DEF_HELPER_FLAGS_5(sve_ucvt_sh, TCG_CALL_NO_RWG,
461
- void, ptr, ptr, ptr, ptr, i32)
462
+ void, ptr, ptr, ptr, fpst, i32)
463
DEF_HELPER_FLAGS_5(sve_ucvt_dh, TCG_CALL_NO_RWG,
464
- void, ptr, ptr, ptr, ptr, i32)
465
+ void, ptr, ptr, ptr, fpst, i32)
466
DEF_HELPER_FLAGS_5(sve_ucvt_ss, TCG_CALL_NO_RWG,
467
- void, ptr, ptr, ptr, ptr, i32)
468
+ void, ptr, ptr, ptr, fpst, i32)
469
DEF_HELPER_FLAGS_5(sve_ucvt_sd, TCG_CALL_NO_RWG,
470
- void, ptr, ptr, ptr, ptr, i32)
471
+ void, ptr, ptr, ptr, fpst, i32)
472
DEF_HELPER_FLAGS_5(sve_ucvt_ds, TCG_CALL_NO_RWG,
473
- void, ptr, ptr, ptr, ptr, i32)
474
+ void, ptr, ptr, ptr, fpst, i32)
475
DEF_HELPER_FLAGS_5(sve_ucvt_dd, TCG_CALL_NO_RWG,
476
- void, ptr, ptr, ptr, ptr, i32)
477
+ void, ptr, ptr, ptr, fpst, i32)
478
479
DEF_HELPER_FLAGS_6(sve_fcmge_h, TCG_CALL_NO_RWG,
480
- void, ptr, ptr, ptr, ptr, ptr, i32)
481
+ void, ptr, ptr, ptr, ptr, fpst, i32)
482
DEF_HELPER_FLAGS_6(sve_fcmge_s, TCG_CALL_NO_RWG,
483
- void, ptr, ptr, ptr, ptr, ptr, i32)
484
+ void, ptr, ptr, ptr, ptr, fpst, i32)
485
DEF_HELPER_FLAGS_6(sve_fcmge_d, TCG_CALL_NO_RWG,
486
- void, ptr, ptr, ptr, ptr, ptr, i32)
487
+ void, ptr, ptr, ptr, ptr, fpst, i32)
488
489
DEF_HELPER_FLAGS_6(sve_fcmgt_h, TCG_CALL_NO_RWG,
490
- void, ptr, ptr, ptr, ptr, ptr, i32)
491
+ void, ptr, ptr, ptr, ptr, fpst, i32)
492
DEF_HELPER_FLAGS_6(sve_fcmgt_s, TCG_CALL_NO_RWG,
493
- void, ptr, ptr, ptr, ptr, ptr, i32)
494
+ void, ptr, ptr, ptr, ptr, fpst, i32)
495
DEF_HELPER_FLAGS_6(sve_fcmgt_d, TCG_CALL_NO_RWG,
496
- void, ptr, ptr, ptr, ptr, ptr, i32)
497
+ void, ptr, ptr, ptr, ptr, fpst, i32)
498
499
DEF_HELPER_FLAGS_6(sve_fcmeq_h, TCG_CALL_NO_RWG,
500
- void, ptr, ptr, ptr, ptr, ptr, i32)
501
+ void, ptr, ptr, ptr, ptr, fpst, i32)
502
DEF_HELPER_FLAGS_6(sve_fcmeq_s, TCG_CALL_NO_RWG,
503
- void, ptr, ptr, ptr, ptr, ptr, i32)
504
+ void, ptr, ptr, ptr, ptr, fpst, i32)
505
DEF_HELPER_FLAGS_6(sve_fcmeq_d, TCG_CALL_NO_RWG,
506
- void, ptr, ptr, ptr, ptr, ptr, i32)
507
+ void, ptr, ptr, ptr, ptr, fpst, i32)
508
509
DEF_HELPER_FLAGS_6(sve_fcmne_h, TCG_CALL_NO_RWG,
510
- void, ptr, ptr, ptr, ptr, ptr, i32)
511
+ void, ptr, ptr, ptr, ptr, fpst, i32)
512
DEF_HELPER_FLAGS_6(sve_fcmne_s, TCG_CALL_NO_RWG,
513
- void, ptr, ptr, ptr, ptr, ptr, i32)
514
+ void, ptr, ptr, ptr, ptr, fpst, i32)
515
DEF_HELPER_FLAGS_6(sve_fcmne_d, TCG_CALL_NO_RWG,
516
- void, ptr, ptr, ptr, ptr, ptr, i32)
517
+ void, ptr, ptr, ptr, ptr, fpst, i32)
518
519
DEF_HELPER_FLAGS_6(sve_fcmuo_h, TCG_CALL_NO_RWG,
520
- void, ptr, ptr, ptr, ptr, ptr, i32)
521
+ void, ptr, ptr, ptr, ptr, fpst, i32)
522
DEF_HELPER_FLAGS_6(sve_fcmuo_s, TCG_CALL_NO_RWG,
523
- void, ptr, ptr, ptr, ptr, ptr, i32)
524
+ void, ptr, ptr, ptr, ptr, fpst, i32)
525
DEF_HELPER_FLAGS_6(sve_fcmuo_d, TCG_CALL_NO_RWG,
526
- void, ptr, ptr, ptr, ptr, ptr, i32)
527
+ void, ptr, ptr, ptr, ptr, fpst, i32)
528
529
DEF_HELPER_FLAGS_6(sve_facge_h, TCG_CALL_NO_RWG,
530
- void, ptr, ptr, ptr, ptr, ptr, i32)
531
+ void, ptr, ptr, ptr, ptr, fpst, i32)
532
DEF_HELPER_FLAGS_6(sve_facge_s, TCG_CALL_NO_RWG,
533
- void, ptr, ptr, ptr, ptr, ptr, i32)
534
+ void, ptr, ptr, ptr, ptr, fpst, i32)
535
DEF_HELPER_FLAGS_6(sve_facge_d, TCG_CALL_NO_RWG,
536
- void, ptr, ptr, ptr, ptr, ptr, i32)
537
+ void, ptr, ptr, ptr, ptr, fpst, i32)
538
539
DEF_HELPER_FLAGS_6(sve_facgt_h, TCG_CALL_NO_RWG,
540
- void, ptr, ptr, ptr, ptr, ptr, i32)
541
+ void, ptr, ptr, ptr, ptr, fpst, i32)
542
DEF_HELPER_FLAGS_6(sve_facgt_s, TCG_CALL_NO_RWG,
543
- void, ptr, ptr, ptr, ptr, ptr, i32)
544
+ void, ptr, ptr, ptr, ptr, fpst, i32)
545
DEF_HELPER_FLAGS_6(sve_facgt_d, TCG_CALL_NO_RWG,
546
- void, ptr, ptr, ptr, ptr, ptr, i32)
547
+ void, ptr, ptr, ptr, ptr, fpst, i32)
548
549
DEF_HELPER_FLAGS_6(sve_fcadd_h, TCG_CALL_NO_RWG,
550
- void, ptr, ptr, ptr, ptr, ptr, i32)
551
+ void, ptr, ptr, ptr, ptr, fpst, i32)
552
DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
553
- void, ptr, ptr, ptr, ptr, ptr, i32)
554
+ void, ptr, ptr, ptr, ptr, fpst, i32)
555
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
556
- void, ptr, ptr, ptr, ptr, ptr, i32)
557
+ void, ptr, ptr, ptr, ptr, fpst, i32)
558
559
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
560
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
561
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
562
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
563
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
564
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
565
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
566
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
567
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
568
569
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
570
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
571
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
572
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
573
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
574
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
575
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
576
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
577
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
578
579
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
580
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
581
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
582
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
583
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
584
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
585
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
586
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
587
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
588
589
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
590
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
591
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
592
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
593
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
594
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
595
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
596
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
597
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
598
599
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
600
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
601
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
602
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
603
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
604
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
605
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
606
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
607
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
608
609
-DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
610
-DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
611
-DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
612
+DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
613
+DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
614
+DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
615
616
DEF_HELPER_FLAGS_4(sve2_saddl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
617
DEF_HELPER_FLAGS_4(sve2_saddl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
618
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve2_xar_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
619
DEF_HELPER_FLAGS_4(sve2_xar_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
620
621
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG,
622
- void, ptr, ptr, ptr, ptr, ptr, i32)
623
+ void, ptr, ptr, ptr, ptr, fpst, i32)
624
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG,
625
- void, ptr, ptr, ptr, ptr, ptr, i32)
626
+ void, ptr, ptr, ptr, ptr, fpst, i32)
627
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_d, TCG_CALL_NO_RWG,
628
- void, ptr, ptr, ptr, ptr, ptr, i32)
629
+ void, ptr, ptr, ptr, ptr, fpst, i32)
630
631
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_h, TCG_CALL_NO_RWG,
632
- void, ptr, ptr, ptr, ptr, ptr, i32)
633
+ void, ptr, ptr, ptr, ptr, fpst, i32)
634
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_s, TCG_CALL_NO_RWG,
635
- void, ptr, ptr, ptr, ptr, ptr, i32)
636
+ void, ptr, ptr, ptr, ptr, fpst, i32)
637
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_d, TCG_CALL_NO_RWG,
638
- void, ptr, ptr, ptr, ptr, ptr, i32)
639
+ void, ptr, ptr, ptr, ptr, fpst, i32)
640
641
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_h, TCG_CALL_NO_RWG,
642
- void, ptr, ptr, ptr, ptr, ptr, i32)
643
+ void, ptr, ptr, ptr, ptr, fpst, i32)
644
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_s, TCG_CALL_NO_RWG,
645
- void, ptr, ptr, ptr, ptr, ptr, i32)
646
+ void, ptr, ptr, ptr, ptr, fpst, i32)
647
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_d, TCG_CALL_NO_RWG,
648
- void, ptr, ptr, ptr, ptr, ptr, i32)
649
+ void, ptr, ptr, ptr, ptr, fpst, i32)
650
651
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_h, TCG_CALL_NO_RWG,
652
- void, ptr, ptr, ptr, ptr, ptr, i32)
653
+ void, ptr, ptr, ptr, ptr, fpst, i32)
654
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_s, TCG_CALL_NO_RWG,
655
- void, ptr, ptr, ptr, ptr, ptr, i32)
656
+ void, ptr, ptr, ptr, ptr, fpst, i32)
657
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_d, TCG_CALL_NO_RWG,
658
- void, ptr, ptr, ptr, ptr, ptr, i32)
659
+ void, ptr, ptr, ptr, ptr, fpst, i32)
660
661
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_h, TCG_CALL_NO_RWG,
662
- void, ptr, ptr, ptr, ptr, ptr, i32)
663
+ void, ptr, ptr, ptr, ptr, fpst, i32)
664
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_s, TCG_CALL_NO_RWG,
665
- void, ptr, ptr, ptr, ptr, ptr, i32)
666
+ void, ptr, ptr, ptr, ptr, fpst, i32)
667
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_d, TCG_CALL_NO_RWG,
668
- void, ptr, ptr, ptr, ptr, ptr, i32)
669
+ void, ptr, ptr, ptr, ptr, fpst, i32)
670
671
DEF_HELPER_FLAGS_5(sve2_eor3, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
672
DEF_HELPER_FLAGS_5(sve2_bcax, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
673
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_s, TCG_CALL_NO_RWG,
674
DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG,
675
void, ptr, ptr, ptr, ptr, i32)
676
677
-DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
678
-DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
679
+DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
680
+DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
681
682
DEF_HELPER_FLAGS_5(sve2_sqrdmlah_idx_h, TCG_CALL_NO_RWG,
683
void, ptr, ptr, ptr, ptr, i32)
684
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve2_cdot_idx_d, TCG_CALL_NO_RWG,
685
void, ptr, ptr, ptr, ptr, i32)
686
687
DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG,
688
- void, ptr, ptr, ptr, ptr, i32)
689
+ void, ptr, ptr, ptr, fpst, i32)
690
DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG,
691
- void, ptr, ptr, ptr, ptr, i32)
692
+ void, ptr, ptr, ptr, fpst, i32)
693
DEF_HELPER_FLAGS_5(sve_bfcvtnt, TCG_CALL_NO_RWG,
694
- void, ptr, ptr, ptr, ptr, i32)
695
+ void, ptr, ptr, ptr, fpst, i32)
696
697
DEF_HELPER_FLAGS_5(sve2_fcvtlt_hs, TCG_CALL_NO_RWG,
698
- void, ptr, ptr, ptr, ptr, i32)
699
+ void, ptr, ptr, ptr, fpst, i32)
700
DEF_HELPER_FLAGS_5(sve2_fcvtlt_sd, TCG_CALL_NO_RWG,
701
- void, ptr, ptr, ptr, ptr, i32)
702
+ void, ptr, ptr, ptr, fpst, i32)
703
704
-DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
705
-DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
706
-DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
707
+DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
708
+DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
709
+DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
710
711
DEF_HELPER_FLAGS_4(sve2_sqshl_zpzi_b, TCG_CALL_NO_RWG,
712
void, ptr, ptr, ptr, i32)
713
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
714
index XXXXXXX..XXXXXXX 100644
715
--- a/target/arm/tcg/sve_helper.c
716
+++ b/target/arm/tcg/sve_helper.c
717
@@ -XXX,XX +XXX,XX @@ DO_ZPZZ_PAIR_D(sve2_sminp_zpzz_d, int64_t, DO_MIN)
718
719
#define DO_ZPZZ_PAIR_FP(NAME, TYPE, H, OP) \
720
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
721
- void *status, uint32_t desc) \
722
+ float_status *status, uint32_t desc) \
723
{ \
724
intptr_t i, opr_sz = simd_oprsz(desc); \
725
for (i = 0; i < opr_sz; ) { \
726
@@ -XXX,XX +XXX,XX @@ static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
727
return TYPE##_##FUNC(lo, hi, status); \
728
} \
729
} \
730
-uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
731
+uint64_t HELPER(NAME)(void *vn, void *vg, float_status *s, uint32_t desc) \
732
{ \
733
uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
734
TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
735
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
736
for (; i < maxsz; i += sizeof(TYPE)) { \
737
*(TYPE *)((void *)data + i) = IDENT; \
738
} \
739
- return NAME##_reduce(data, vs, maxsz / sizeof(TYPE)); \
740
+ return NAME##_reduce(data, s, maxsz / sizeof(TYPE)); \
741
}
742
743
DO_REDUCE(sve_faddv_h, float16, H1_2, add, float16_zero)
744
@@ -XXX,XX +XXX,XX @@ DO_REDUCE(sve_fmaxv_d, float64, H1_8, max, float64_chs(float64_infinity))
745
#undef DO_REDUCE
746
747
uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
748
- void *status, uint32_t desc)
749
+ float_status *status, uint32_t desc)
750
{
751
intptr_t i = 0, opr_sz = simd_oprsz(desc);
752
float16 result = nn;
753
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
754
}
755
756
uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
757
- void *status, uint32_t desc)
758
+ float_status *status, uint32_t desc)
759
{
760
intptr_t i = 0, opr_sz = simd_oprsz(desc);
761
float32 result = nn;
762
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
763
}
764
765
uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
766
- void *status, uint32_t desc)
767
+ float_status *status, uint32_t desc)
768
{
769
intptr_t i = 0, opr_sz = simd_oprsz(desc) / 8;
770
uint64_t *m = vm;
771
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
772
*/
773
#define DO_ZPZZ_FP(NAME, TYPE, H, OP) \
774
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
775
- void *status, uint32_t desc) \
776
+ float_status *status, uint32_t desc) \
777
{ \
778
intptr_t i = simd_oprsz(desc); \
779
uint64_t *g = vg; \
780
@@ -XXX,XX +XXX,XX @@ DO_ZPZZ_FP(sve_fmulx_d, uint64_t, H1_8, helper_vfp_mulxd)
781
*/
782
#define DO_ZPZS_FP(NAME, TYPE, H, OP) \
783
void HELPER(NAME)(void *vd, void *vn, void *vg, uint64_t scalar, \
784
- void *status, uint32_t desc) \
785
+ float_status *status, uint32_t desc) \
786
{ \
787
intptr_t i = simd_oprsz(desc); \
788
uint64_t *g = vg; \
789
@@ -XXX,XX +XXX,XX @@ DO_ZPZS_FP(sve_fmins_d, float64, H1_8, float64_min)
790
* With the extra float_status parameter.
791
*/
792
#define DO_ZPZ_FP(NAME, TYPE, H, OP) \
793
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
794
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
795
+ float_status *status, uint32_t desc) \
796
{ \
797
intptr_t i = simd_oprsz(desc); \
798
uint64_t *g = vg; \
799
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
800
}
801
802
void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
803
- void *vg, void *status, uint32_t desc)
804
+ void *vg, float_status *status, uint32_t desc)
805
{
806
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
807
}
808
809
void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
810
- void *vg, void *status, uint32_t desc)
811
+ void *vg, float_status *status, uint32_t desc)
812
{
813
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
814
}
815
816
void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
817
- void *vg, void *status, uint32_t desc)
818
+ void *vg, float_status *status, uint32_t desc)
819
{
820
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
821
}
822
823
void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
824
- void *vg, void *status, uint32_t desc)
825
+ void *vg, float_status *status, uint32_t desc)
826
{
827
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
828
}
829
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
830
}
831
832
void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
833
- void *vg, void *status, uint32_t desc)
834
+ void *vg, float_status *status, uint32_t desc)
835
{
836
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
837
}
838
839
void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
840
- void *vg, void *status, uint32_t desc)
841
+ void *vg, float_status *status, uint32_t desc)
842
{
843
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
844
}
845
846
void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
847
- void *vg, void *status, uint32_t desc)
848
+ void *vg, float_status *status, uint32_t desc)
849
{
850
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
851
}
852
853
void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
854
- void *vg, void *status, uint32_t desc)
855
+ void *vg, float_status *status, uint32_t desc)
856
{
857
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
858
}
859
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
860
}
861
862
void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
863
- void *vg, void *status, uint32_t desc)
864
+ void *vg, float_status *status, uint32_t desc)
865
{
866
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
867
}
868
869
void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
870
- void *vg, void *status, uint32_t desc)
871
+ void *vg, float_status *status, uint32_t desc)
872
{
873
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
874
}
875
876
void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
877
- void *vg, void *status, uint32_t desc)
878
+ void *vg, float_status *status, uint32_t desc)
879
{
880
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
881
}
882
883
void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
884
- void *vg, void *status, uint32_t desc)
885
+ void *vg, float_status *status, uint32_t desc)
886
{
887
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
888
}
889
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
890
*/
891
#define DO_FPCMP_PPZZ(NAME, TYPE, H, OP) \
892
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
893
- void *status, uint32_t desc) \
894
+ float_status *status, uint32_t desc) \
895
{ \
896
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
897
uint64_t *d = vd, *g = vg; \
898
@@ -XXX,XX +XXX,XX @@ DO_FPCMP_PPZZ_ALL(sve_facgt, DO_FACGT)
899
*/
900
#define DO_FPCMP_PPZ0(NAME, TYPE, H, OP) \
901
void HELPER(NAME)(void *vd, void *vn, void *vg, \
902
- void *status, uint32_t desc) \
903
+ float_status *status, uint32_t desc) \
904
{ \
905
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
906
uint64_t *d = vd, *g = vg; \
907
@@ -XXX,XX +XXX,XX @@ DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE)
908
909
/* FP Trig Multiply-Add. */
910
911
-void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
912
+void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm,
913
+ float_status *s, uint32_t desc)
914
{
915
static const float16 coeff[16] = {
916
0x3c00, 0xb155, 0x2030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
917
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
918
mm = float16_abs(mm);
919
xx += 8;
920
}
921
- d[i] = float16_muladd(n[i], mm, coeff[xx], 0, vs);
922
+ d[i] = float16_muladd(n[i], mm, coeff[xx], 0, s);
923
}
924
}
925
926
-void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
927
+void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm,
928
+ float_status *s, uint32_t desc)
929
{
930
static const float32 coeff[16] = {
931
0x3f800000, 0xbe2aaaab, 0x3c088886, 0xb95008b9,
932
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
933
mm = float32_abs(mm);
934
xx += 8;
935
}
936
- d[i] = float32_muladd(n[i], mm, coeff[xx], 0, vs);
937
+ d[i] = float32_muladd(n[i], mm, coeff[xx], 0, s);
938
}
939
}
940
941
-void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
942
+void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm,
943
+ float_status *s, uint32_t desc)
944
{
945
static const float64 coeff[16] = {
946
0x3ff0000000000000ull, 0xbfc5555555555543ull,
947
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
948
mm = float64_abs(mm);
949
xx += 8;
950
}
951
- d[i] = float64_muladd(n[i], mm, coeff[xx], 0, vs);
952
+ d[i] = float64_muladd(n[i], mm, coeff[xx], 0, s);
953
}
954
}
955
956
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
957
*/
958
959
void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg,
960
- void *vs, uint32_t desc)
961
+ float_status *s, uint32_t desc)
962
{
963
intptr_t j, i = simd_oprsz(desc);
964
uint64_t *g = vg;
965
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg,
966
e3 = *(float16 *)(vm + H1_2(i)) ^ neg_imag;
967
968
if (likely((pg >> (i & 63)) & 1)) {
969
- *(float16 *)(vd + H1_2(i)) = float16_add(e0, e1, vs);
970
+ *(float16 *)(vd + H1_2(i)) = float16_add(e0, e1, s);
971
}
972
if (likely((pg >> (j & 63)) & 1)) {
973
- *(float16 *)(vd + H1_2(j)) = float16_add(e2, e3, vs);
974
+ *(float16 *)(vd + H1_2(j)) = float16_add(e2, e3, s);
975
}
976
} while (i & 63);
977
} while (i != 0);
978
}
979
980
void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg,
981
- void *vs, uint32_t desc)
982
+ float_status *s, uint32_t desc)
983
{
984
intptr_t j, i = simd_oprsz(desc);
985
uint64_t *g = vg;
986
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg,
987
e3 = *(float32 *)(vm + H1_2(i)) ^ neg_imag;
988
989
if (likely((pg >> (i & 63)) & 1)) {
990
- *(float32 *)(vd + H1_2(i)) = float32_add(e0, e1, vs);
991
+ *(float32 *)(vd + H1_2(i)) = float32_add(e0, e1, s);
992
}
993
if (likely((pg >> (j & 63)) & 1)) {
994
- *(float32 *)(vd + H1_2(j)) = float32_add(e2, e3, vs);
995
+ *(float32 *)(vd + H1_2(j)) = float32_add(e2, e3, s);
996
}
997
} while (i & 63);
998
} while (i != 0);
999
}
1000
1001
void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1002
- void *vs, uint32_t desc)
1003
+ float_status *s, uint32_t desc)
1004
{
1005
intptr_t j, i = simd_oprsz(desc);
1006
uint64_t *g = vg;
1007
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1008
e3 = *(float64 *)(vm + H1_2(i)) ^ neg_imag;
1009
1010
if (likely((pg >> (i & 63)) & 1)) {
1011
- *(float64 *)(vd + H1_2(i)) = float64_add(e0, e1, vs);
1012
+ *(float64 *)(vd + H1_2(i)) = float64_add(e0, e1, s);
1013
}
1014
if (likely((pg >> (j & 63)) & 1)) {
1015
- *(float64 *)(vd + H1_2(j)) = float64_add(e2, e3, vs);
1016
+ *(float64 *)(vd + H1_2(j)) = float64_add(e2, e3, s);
1017
}
1018
} while (i & 63);
1019
} while (i != 0);
1020
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1021
*/
1022
1023
void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
1024
- void *vg, void *status, uint32_t desc)
1025
+ void *vg, float_status *status, uint32_t desc)
1026
{
1027
intptr_t j, i = simd_oprsz(desc);
1028
unsigned rot = simd_data(desc);
1029
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
1030
}
1031
1032
void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
1033
- void *vg, void *status, uint32_t desc)
1034
+ void *vg, float_status *status, uint32_t desc)
1035
{
1036
intptr_t j, i = simd_oprsz(desc);
1037
unsigned rot = simd_data(desc);
1038
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
1039
}
1040
1041
void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
1042
- void *vg, void *status, uint32_t desc)
1043
+ void *vg, float_status *status, uint32_t desc)
1044
{
1045
intptr_t j, i = simd_oprsz(desc);
1046
unsigned rot = simd_data(desc);
1047
@@ -XXX,XX +XXX,XX @@ void HELPER(sve2_xar_s)(void *vd, void *vn, void *vm, uint32_t desc)
1048
}
1049
1050
void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va,
1051
- void *status, uint32_t desc)
1052
+ float_status *status, uint32_t desc)
1053
{
1054
intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float32) * 4);
1055
1056
@@ -XXX,XX +XXX,XX @@ void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va,
1057
}
1058
1059
void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va,
1060
- void *status, uint32_t desc)
1061
+ float_status *status, uint32_t desc)
1062
{
1063
intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float64) * 4);
1064
1065
@@ -XXX,XX +XXX,XX @@ void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va,
1066
}
1067
1068
#define DO_FCVTNT(NAME, TYPEW, TYPEN, HW, HN, OP) \
1069
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
1070
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
1071
+ float_status *status, uint32_t desc) \
1072
{ \
1073
intptr_t i = simd_oprsz(desc); \
1074
uint64_t *g = vg; \
1075
@@ -XXX,XX +XXX,XX @@ DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16)
1076
DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_8, H1_4, float64_to_float32)
1077
1078
#define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \
1079
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
1080
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
1081
+ float_status *status, uint32_t desc) \
1082
{ \
1083
intptr_t i = simd_oprsz(desc); \
1084
uint64_t *g = vg; \
42
--
1085
--
43
2.25.1
1086
2.34.1
44
1087
45
1088
diff view generated by jsdifflib
[PULL 12/18] hw/intc/arm_gicv3_its: Add trace events for table reads and writes
[PULL 07/19] target/arm: Convert sme_helper.c to fpst alias
1
For debugging guest use of the ITS, it can be helpful to trace
1
From: Richard Henderson <richard.henderson@linaro.org>
2
when the ITS reads and writes the in-memory tables.
3
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20241206031224.78525-8-richard.henderson@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220303202341.2232284-3-peter.maydell@linaro.org
7
---
7
---
8
hw/intc/arm_gicv3_its.c | 37 +++++++++++++++++++++++++++++++------
8
target/arm/tcg/helper-sme.h | 4 ++--
9
hw/intc/trace-events | 9 +++++++++
9
target/arm/tcg/sme_helper.c | 8 ++++----
10
2 files changed, 40 insertions(+), 6 deletions(-)
10
2 files changed, 6 insertions(+), 6 deletions(-)
11
11
12
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
12
diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme.h
13
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/intc/arm_gicv3_its.c
14
--- a/target/arm/tcg/helper-sme.h
15
+++ b/hw/intc/arm_gicv3_its.c
15
+++ b/target/arm/tcg/helper-sme.h
16
@@ -XXX,XX +XXX,XX @@ static MemTxResult get_cte(GICv3ITSState *s, uint16_t icid, CTEntry *cte)
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
17
if (entry_addr == -1) {
17
DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG,
18
/* No L2 table entry, i.e. no valid CTE, or a memory error */
18
void, ptr, ptr, ptr, ptr, ptr, env, i32)
19
cte->valid = false;
19
DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
20
- return res;
20
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
21
+ goto out;
21
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
22
}
22
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
23
23
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
24
cteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res);
24
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
25
if (res != MEMTX_OK) {
25
DEF_HELPER_FLAGS_7(sme_bfmopa, TCG_CALL_NO_RWG,
26
- return res;
26
void, ptr, ptr, ptr, ptr, ptr, env, i32)
27
+ goto out;
27
DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG,
28
}
28
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
29
cte->valid = FIELD_EX64(cteval, CTE, VALID);
29
index XXXXXXX..XXXXXXX 100644
30
cte->rdbase = FIELD_EX64(cteval, CTE, RDBASE);
30
--- a/target/arm/tcg/sme_helper.c
31
- return MEMTX_OK;
31
+++ b/target/arm/tcg/sme_helper.c
32
+out:
32
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
33
+ if (res != MEMTX_OK) {
34
+ trace_gicv3_its_cte_read_fault(icid);
35
+ } else {
36
+ trace_gicv3_its_cte_read(icid, cte->valid, cte->rdbase);
37
+ }
38
+ return res;
39
}
33
}
40
34
41
/*
35
void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
42
@@ -XXX,XX +XXX,XX @@ static bool update_ite(GICv3ITSState *s, uint32_t eventid, const DTEntry *dte,
36
- void *vpm, void *vst, uint32_t desc)
43
uint64_t itel = 0;
37
+ void *vpm, float_status *fpst_in, uint32_t desc)
44
uint32_t iteh = 0;
38
{
45
39
intptr_t row, col, oprsz = simd_maxsz(desc);
46
+ trace_gicv3_its_ite_write(dte->ittaddr, eventid, ite->valid,
40
uint32_t neg = simd_data(desc) << 31;
47
+ ite->inttype, ite->intid, ite->icid,
41
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
48
+ ite->vpeid, ite->doorbell);
42
* update the cumulative fp exception status. It also produces
49
+
43
* default nans.
50
if (ite->valid) {
44
*/
51
itel = FIELD_DP64(itel, ITE_L, VALID, 1);
45
- fpst = *(float_status *)vst;
52
itel = FIELD_DP64(itel, ITE_L, INTTYPE, ite->inttype);
46
+ fpst = *fpst_in;
53
@@ -XXX,XX +XXX,XX @@ static MemTxResult get_ite(GICv3ITSState *s, uint32_t eventid,
47
set_default_nan_mode(true, &fpst);
54
48
55
itel = address_space_ldq_le(as, iteaddr, MEMTXATTRS_UNSPECIFIED, &res);
49
for (row = 0; row < oprsz; ) {
56
if (res != MEMTX_OK) {
50
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
57
+ trace_gicv3_its_ite_read_fault(dte->ittaddr, eventid);
58
return res;
59
}
60
61
iteh = address_space_ldl_le(as, iteaddr + 8, MEMTXATTRS_UNSPECIFIED, &res);
62
if (res != MEMTX_OK) {
63
+ trace_gicv3_its_ite_read_fault(dte->ittaddr, eventid);
64
return res;
65
}
66
67
@@ -XXX,XX +XXX,XX @@ static MemTxResult get_ite(GICv3ITSState *s, uint32_t eventid,
68
ite->icid = FIELD_EX64(itel, ITE_L, ICID);
69
ite->vpeid = FIELD_EX64(itel, ITE_L, VPEID);
70
ite->doorbell = FIELD_EX64(iteh, ITE_H, DOORBELL);
71
+ trace_gicv3_its_ite_read(dte->ittaddr, eventid, ite->valid,
72
+ ite->inttype, ite->intid, ite->icid,
73
+ ite->vpeid, ite->doorbell);
74
return MEMTX_OK;
75
}
51
}
76
52
77
@@ -XXX,XX +XXX,XX @@ static MemTxResult get_dte(GICv3ITSState *s, uint32_t devid, DTEntry *dte)
53
void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
78
if (entry_addr == -1) {
54
- void *vpm, void *vst, uint32_t desc)
79
/* No L2 table entry, i.e. no valid DTE, or a memory error */
55
+ void *vpm, float_status *fpst_in, uint32_t desc)
80
dte->valid = false;
56
{
81
- return res;
57
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
82
+ goto out;
58
uint64_t neg = (uint64_t)simd_data(desc) << 63;
83
}
59
uint64_t *za = vza, *zn = vzn, *zm = vzm;
84
dteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res);
60
uint8_t *pn = vpn, *pm = vpm;
85
if (res != MEMTX_OK) {
61
- float_status fpst = *(float_status *)vst;
86
- return res;
62
+ float_status fpst = *fpst_in;
87
+ goto out;
63
88
}
64
set_default_nan_mode(true, &fpst);
89
dte->valid = FIELD_EX64(dteval, DTE, VALID);
65
90
dte->size = FIELD_EX64(dteval, DTE, SIZE);
91
/* DTE word field stores bits [51:8] of the ITT address */
92
dte->ittaddr = FIELD_EX64(dteval, DTE, ITTADDR) << ITTADDR_SHIFT;
93
- return MEMTX_OK;
94
+out:
95
+ if (res != MEMTX_OK) {
96
+ trace_gicv3_its_dte_read_fault(devid);
97
+ } else {
98
+ trace_gicv3_its_dte_read(devid, dte->valid, dte->size, dte->ittaddr);
99
+ }
100
+ return res;
101
}
102
103
/*
104
@@ -XXX,XX +XXX,XX @@ static bool update_cte(GICv3ITSState *s, uint16_t icid, const CTEntry *cte)
105
uint64_t cteval = 0;
106
MemTxResult res = MEMTX_OK;
107
108
+ trace_gicv3_its_cte_write(icid, cte->valid, cte->rdbase);
109
+
110
if (cte->valid) {
111
/* add mapping entry to collection table */
112
cteval = FIELD_DP64(cteval, CTE, VALID, 1);
113
@@ -XXX,XX +XXX,XX @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, const DTEntry *dte)
114
uint64_t dteval = 0;
115
MemTxResult res = MEMTX_OK;
116
117
+ trace_gicv3_its_dte_write(devid, dte->valid, dte->size, dte->ittaddr);
118
+
119
if (dte->valid) {
120
/* add mapping entry to device table */
121
dteval = FIELD_DP64(dteval, DTE, VALID, 1);
122
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
123
index XXXXXXX..XXXXXXX 100644
124
--- a/hw/intc/trace-events
125
+++ b/hw/intc/trace-events
126
@@ -XXX,XX +XXX,XX @@ gicv3_its_cmd_inv(void) "GICv3 ITS: command INV or INVALL"
127
gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64
128
gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x"
129
gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x"
130
+gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x"
131
+gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x"
132
+gicv3_its_cte_read_fault(uint32_t icid) "GICv3 ITS: Collection Table read for ICID 0x%x: faulted"
133
+gicv3_its_ite_read(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x"
134
+gicv3_its_ite_read_fault(uint64_t ittaddr, uint32_t eventid) "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: faulted"
135
+gicv3_its_ite_write(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: Interrupt Table write for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x"
136
+gicv3_its_dte_read(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table read for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64
137
+gicv3_its_dte_write(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table write for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64
138
+gicv3_its_dte_read_fault(uint32_t devid) "GICv3 ITS: Device Table read for DeviceID 0x%x: faulted"
139
140
# armv7m_nvic.c
141
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
142
--
66
--
143
2.25.1
67
2.34.1
diff view generated by jsdifflib
[PULL 02/18] util: Unify implementations of qemu_memalign()
[PULL 08/19] target/arm: Convert vec_helper.c to use env alias
1
We implement qemu_memalign() in both oslib-posix.c and oslib-win32.c,
1
From: Richard Henderson <richard.henderson@linaro.org>
2
but the two versions are essentially the same: they call
3
qemu_try_memalign(), and abort() after printing an error message if
4
it fails. The only difference is that the win32 version prints the
5
GetLastError() value whereas the POSIX version prints
6
strerror(errno). However, this is a bug in the win32 version: in
7
commit dfbd0b873a85021 in 2020 we changed the implementation of
8
qemu_try_memalign() from using VirtualAlloc() (which sets the
9
GetLastError() value) to using _aligned_malloc() (which sets errno),
10
but didn't update the error message to match.
11
2
12
Replace the two separate functions with a single version in a
3
Allow the helpers to receive CPUARMState* directly
13
new memalign.c file, which drops the unnecessary extra qemu_oom_check()
4
instead of via void*.
14
function and instead prints a more useful message including the
15
requested size and alignment as well as the errno string.
16
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241206031224.78525-9-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20220226180723.1706285-4-peter.maydell@linaro.org
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
---
10
---
22
util/memalign.c | 39 +++++++++++++++++++++++++++++++++++++++
11
target/arm/helper.h | 12 ++++++------
23
util/oslib-posix.c | 14 --------------
12
target/arm/tcg/helper-a64.h | 2 +-
24
util/oslib-win32.c | 14 --------------
13
target/arm/tcg/vec_helper.c | 21 +++++++--------------
25
util/meson.build | 1 +
14
3 files changed, 14 insertions(+), 21 deletions(-)
26
4 files changed, 40 insertions(+), 28 deletions(-)
27
create mode 100644 util/memalign.c
28
15
29
diff --git a/util/memalign.c b/util/memalign.c
16
diff --git a/target/arm/helper.h b/target/arm/helper.h
30
new file mode 100644
31
index XXXXXXX..XXXXXXX
32
--- /dev/null
33
+++ b/util/memalign.c
34
@@ -XXX,XX +XXX,XX @@
35
+/*
36
+ * memalign.c: Allocate an aligned memory region
37
+ *
38
+ * Copyright (c) 2003-2008 Fabrice Bellard
39
+ * Copyright (c) 2010-2016 Red Hat, Inc.
40
+ * Copyright (c) 2022 Linaro Ltd
41
+ *
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
43
+ * of this software and associated documentation files (the "Software"), to deal
44
+ * in the Software without restriction, including without limitation the rights
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
49
+ * The above copyright notice and this permission notice shall be included in
50
+ * all copies or substantial portions of the Software.
51
+ *
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
60
+
61
+#include "qemu/osdep.h"
62
+
63
+void *qemu_memalign(size_t alignment, size_t size)
64
+{
65
+ void *p = qemu_try_memalign(alignment, size);
66
+ if (p) {
67
+ return p;
68
+ }
69
+ fprintf(stderr,
70
+ "qemu_memalign: failed to allocate %zu bytes at alignment %zu: %s\n",
71
+ size, alignment, strerror(errno));
72
+ abort();
73
+}
74
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
75
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
76
--- a/util/oslib-posix.c
18
--- a/target/arm/helper.h
77
+++ b/util/oslib-posix.c
19
+++ b/target/arm/helper.h
78
@@ -XXX,XX +XXX,XX @@ fail_close:
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG,
79
return false;
21
void, ptr, ptr, ptr, ptr, i32)
22
23
DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
24
- void, ptr, ptr, ptr, ptr, i32)
25
+ void, ptr, ptr, ptr, env, i32)
26
DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
27
- void, ptr, ptr, ptr, ptr, i32)
28
+ void, ptr, ptr, ptr, env, i32)
29
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
30
- void, ptr, ptr, ptr, ptr, i32)
31
+ void, ptr, ptr, ptr, env, i32)
32
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
33
- void, ptr, ptr, ptr, ptr, i32)
34
+ void, ptr, ptr, ptr, env, i32)
35
36
DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst)
37
DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst)
38
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG,
39
void, ptr, ptr, ptr, i32)
40
41
DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG,
42
- void, ptr, ptr, ptr, ptr, ptr, i32)
43
+ void, ptr, ptr, ptr, ptr, env, i32)
44
DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG,
45
- void, ptr, ptr, ptr, ptr, ptr, i32)
46
+ void, ptr, ptr, ptr, ptr, env, i32)
47
48
DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
50
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/tcg/helper-a64.h
53
+++ b/target/arm/tcg/helper-a64.h
54
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, fpst)
55
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, fpst)
56
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, fpst)
57
DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, fpst)
58
-DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
59
+DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
60
DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
61
DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
62
DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
63
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/tcg/vec_helper.c
66
+++ b/target/arm/tcg/vec_helper.c
67
@@ -XXX,XX +XXX,XX @@ static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
80
}
68
}
81
69
82
-static void *qemu_oom_check(void *ptr)
70
void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
83
-{
71
- void *venv, uint32_t desc)
84
- if (ptr == NULL) {
72
+ CPUARMState *env, uint32_t desc)
85
- fprintf(stderr, "Failed to allocate memory: %s\n", strerror(errno));
86
- abort();
87
- }
88
- return ptr;
89
-}
90
-
91
void *qemu_try_memalign(size_t alignment, size_t size)
92
{
73
{
93
void *ptr;
74
- CPUARMState *env = venv;
94
@@ -XXX,XX +XXX,XX @@ void *qemu_try_memalign(size_t alignment, size_t size)
75
do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
95
return ptr;
76
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
96
}
77
}
97
78
98
-void *qemu_memalign(size_t alignment, size_t size)
79
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
99
-{
80
- void *venv, uint32_t desc)
100
- return qemu_oom_check(qemu_try_memalign(alignment, size));
81
+ CPUARMState *env, uint32_t desc)
101
-}
102
-
103
/* alloc shared memory pages */
104
void *qemu_anon_ram_alloc(size_t size, uint64_t *alignment, bool shared,
105
bool noreserve)
106
diff --git a/util/oslib-win32.c b/util/oslib-win32.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/util/oslib-win32.c
109
+++ b/util/oslib-win32.c
110
@@ -XXX,XX +XXX,XX @@
111
/* this must come after including "trace.h" */
112
#include <shlobj.h>
113
114
-static void *qemu_oom_check(void *ptr)
115
-{
116
- if (ptr == NULL) {
117
- fprintf(stderr, "Failed to allocate memory: %lu\n", GetLastError());
118
- abort();
119
- }
120
- return ptr;
121
-}
122
-
123
void *qemu_try_memalign(size_t alignment, size_t size)
124
{
82
{
125
void *ptr;
83
- CPUARMState *env = venv;
126
@@ -XXX,XX +XXX,XX @@ void *qemu_try_memalign(size_t alignment, size_t size)
84
do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
127
return ptr;
85
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
128
}
86
}
129
87
130
-void *qemu_memalign(size_t alignment, size_t size)
88
void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
131
-{
89
- void *venv, uint32_t desc)
132
- return qemu_oom_check(qemu_try_memalign(alignment, size));
90
+ CPUARMState *env, uint32_t desc)
133
-}
134
-
135
static int get_allocation_granularity(void)
136
{
91
{
137
SYSTEM_INFO system_info;
92
intptr_t i, oprsz = simd_oprsz(desc);
138
diff --git a/util/meson.build b/util/meson.build
93
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
139
index XXXXXXX..XXXXXXX 100644
94
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
140
--- a/util/meson.build
95
- CPUARMState *env = venv;
141
+++ b/util/meson.build
96
float_status *status = &env->vfp.fp_status;
142
@@ -XXX,XX +XXX,XX @@ util_ss.add(when: 'CONFIG_POSIX', if_true: files('drm.c'))
97
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
143
util_ss.add(files('guest-random.c'))
98
144
util_ss.add(files('yank.c'))
99
@@ -XXX,XX +XXX,XX @@ static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
145
util_ss.add(files('int128.c'))
100
}
146
+util_ss.add(files('memalign.c'))
101
147
102
void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
148
if have_user
103
- void *venv, uint32_t desc)
149
util_ss.add(files('selfmap.c'))
104
+ CPUARMState *env, uint32_t desc)
105
{
106
- CPUARMState *env = venv;
107
do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
108
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
109
}
110
111
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
112
- void *venv, uint32_t desc)
113
+ CPUARMState *env, uint32_t desc)
114
{
115
- CPUARMState *env = venv;
116
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
117
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
118
}
119
120
void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
121
- void *venv, uint32_t desc)
122
+ CPUARMState *env, uint32_t desc)
123
{
124
intptr_t i, j, oprsz = simd_oprsz(desc);
125
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
126
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
127
intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
128
- CPUARMState *env = venv;
129
float_status *status = &env->vfp.fp_status;
130
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
131
132
@@ -XXX,XX +XXX,XX @@ DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32_t)
133
#undef DO_VRINT_RMODE
134
135
#ifdef TARGET_AARCH64
136
-void HELPER(simd_tblx)(void *vd, void *vm, void *venv, uint32_t desc)
137
+void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc)
138
{
139
const uint8_t *indices = vm;
140
- CPUARMState *env = venv;
141
size_t oprsz = simd_oprsz(desc);
142
uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5);
143
bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1);
150
--
144
--
151
2.25.1
145
2.34.1
152
146
153
147
diff view generated by jsdifflib
[PULL 05/18] util: Share qemu_try_memalign() implementation between POSIX and Windows
[PULL 09/19] target/arm: Convert neon_helper.c to use env alias
1
The qemu_try_memalign() functions for POSIX and Windows used to be
1
From: Richard Henderson <richard.henderson@linaro.org>
2
significantly different, but these days they are identical except for
3
the actual allocation function called, and the POSIX version already
4
has to have ifdeffery for different allocation functions.
5
2
6
Move to a single implementation in memalign.c, which uses the Windows
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
_aligned_malloc if we detect that function in meson.
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-10-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.h | 56 ++++++++++++++++++------------------
9
target/arm/tcg/neon_helper.c | 6 ++--
10
2 files changed, 30 insertions(+), 32 deletions(-)
8
11
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/arm/helper.h b/target/arm/helper.h
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220226180723.1706285-7-peter.maydell@linaro.org
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
---
14
meson.build | 1 +
15
util/memalign.c | 39 +++++++++++++++++++++++++++++++++++++++
16
util/oslib-posix.c | 29 -----------------------------
17
util/oslib-win32.c | 17 -----------------
18
4 files changed, 40 insertions(+), 46 deletions(-)
19
20
diff --git a/meson.build b/meson.build
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/meson.build
14
--- a/target/arm/helper.h
23
+++ b/meson.build
15
+++ b/target/arm/helper.h
24
@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_POSIX_FALLOCATE', cc.has_function('posix_fallocate'
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32)
25
# Note that we need to specify prefix: here to avoid incorrectly
17
DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32)
26
# thinking that Windows has posix_memalign()
18
DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64)
27
config_host_data.set('CONFIG_POSIX_MEMALIGN', cc.has_function('posix_memalign', prefix: '#include <stdlib.h>'))
19
DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64)
28
+config_host_data.set('CONFIG_ALIGNED_MALLOC', cc.has_function('_aligned_malloc'))
20
-DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
29
config_host_data.set('CONFIG_PPOLL', cc.has_function('ppoll'))
21
-DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
30
config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))
22
-DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
31
config_host_data.set('CONFIG_SEM_TIMEDWAIT', cc.has_function('sem_timedwait', dependencies: threads))
23
-DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
32
diff --git a/util/memalign.c b/util/memalign.c
24
-DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
25
-DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
26
-DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
27
-DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
28
-DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
29
-DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
30
-DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
31
-DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
32
-DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
33
-DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
34
-DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
35
-DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
36
-DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
37
-DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
38
-DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
39
-DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
40
-DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
41
-DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
42
-DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
43
-DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
44
-DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
45
-DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
46
-DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
47
-DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
49
+DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
50
+DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
51
+DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
52
+DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
53
+DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
54
+DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
55
+DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
56
+DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
57
+DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
58
+DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
59
+DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
60
+DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
61
+DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
62
+DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
63
+DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
64
+DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
65
+DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
66
+DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
67
+DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
68
+DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
69
+DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
70
+DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
71
+DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
72
+DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
73
+DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
74
+DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
75
+DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
76
77
DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
78
DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
79
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
33
index XXXXXXX..XXXXXXX 100644
80
index XXXXXXX..XXXXXXX 100644
34
--- a/util/memalign.c
81
--- a/target/arm/tcg/neon_helper.c
35
+++ b/util/memalign.c
82
+++ b/target/arm/tcg/neon_helper.c
36
@@ -XXX,XX +XXX,XX @@
83
@@ -XXX,XX +XXX,XX @@ void HELPER(name)(void *vd, void *vn, void *vm, uint32_t desc) \
37
*/
38
39
#include "qemu/osdep.h"
40
+#include "qemu/host-utils.h"
41
+#include "trace.h"
42
+
43
+void *qemu_try_memalign(size_t alignment, size_t size)
44
+{
45
+ void *ptr;
46
+
47
+ if (alignment < sizeof(void*)) {
48
+ alignment = sizeof(void*);
49
+ } else {
50
+ g_assert(is_power_of_2(alignment));
51
+ }
52
+
53
+ /*
54
+ * Handling of 0 allocations varies among the different
55
+ * platform APIs (for instance _aligned_malloc() will
56
+ * fail) -- ensure that we always return a valid non-NULL
57
+ * pointer that can be freed by qemu_vfree().
58
+ */
59
+ if (size == 0) {
60
+ size++;
61
+ }
62
+#if defined(CONFIG_POSIX_MEMALIGN)
63
+ int ret;
64
+ ret = posix_memalign(&ptr, alignment, size);
65
+ if (ret != 0) {
66
+ errno = ret;
67
+ ptr = NULL;
68
+ }
69
+#elif defined(CONFIG_ALIGNED_MALLOC)
70
+ ptr = _aligned_malloc(size, alignment);
71
+#elif defined(CONFIG_BSD)
72
+ ptr = valloc(size);
73
+#else
74
+ ptr = memalign(alignment, size);
75
+#endif
76
+ trace_qemu_memalign(alignment, size, ptr);
77
+ return ptr;
78
+}
79
80
void *qemu_memalign(size_t alignment, size_t size)
81
{
82
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/util/oslib-posix.c
85
+++ b/util/oslib-posix.c
86
@@ -XXX,XX +XXX,XX @@ fail_close:
87
return false;
88
}
84
}
89
85
90
-void *qemu_try_memalign(size_t alignment, size_t size)
86
#define NEON_GVEC_VOP2_ENV(name, vtype) \
91
-{
87
-void HELPER(name)(void *vd, void *vn, void *vm, void *venv, uint32_t desc) \
92
- void *ptr;
88
+void HELPER(name)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) \
93
-
89
{ \
94
- if (alignment < sizeof(void*)) {
90
intptr_t i, opr_sz = simd_oprsz(desc); \
95
- alignment = sizeof(void*);
91
vtype *d = vd, *n = vn, *m = vm; \
96
- } else {
92
- CPUARMState *env = venv; \
97
- g_assert(is_power_of_2(alignment));
93
for (i = 0; i < opr_sz / sizeof(vtype); i++) { \
98
- }
94
NEON_FN(d[i], n[i], m[i]); \
99
-
95
} \
100
- if (size == 0) {
96
@@ -XXX,XX +XXX,XX @@ void HELPER(name)(void *vd, void *vn, void *vm, void *venv, uint32_t desc) \
101
- size++;
97
}
102
- }
98
103
-#if defined(CONFIG_POSIX_MEMALIGN)
99
#define NEON_GVEC_VOP2i_ENV(name, vtype) \
104
- int ret;
100
-void HELPER(name)(void *vd, void *vn, void *venv, uint32_t desc) \
105
- ret = posix_memalign(&ptr, alignment, size);
101
+void HELPER(name)(void *vd, void *vn, CPUARMState *env, uint32_t desc) \
106
- if (ret != 0) {
102
{ \
107
- errno = ret;
103
intptr_t i, opr_sz = simd_oprsz(desc); \
108
- ptr = NULL;
104
int imm = simd_data(desc); \
109
- }
105
vtype *d = vd, *n = vn; \
110
-#elif defined(CONFIG_BSD)
106
- CPUARMState *env = venv; \
111
- ptr = valloc(size);
107
for (i = 0; i < opr_sz / sizeof(vtype); i++) { \
112
-#else
108
NEON_FN(d[i], n[i], imm); \
113
- ptr = memalign(alignment, size);
109
} \
114
-#endif
115
- trace_qemu_memalign(alignment, size, ptr);
116
- return ptr;
117
-}
118
-
119
/* alloc shared memory pages */
120
void *qemu_anon_ram_alloc(size_t size, uint64_t *alignment, bool shared,
121
bool noreserve)
122
diff --git a/util/oslib-win32.c b/util/oslib-win32.c
123
index XXXXXXX..XXXXXXX 100644
124
--- a/util/oslib-win32.c
125
+++ b/util/oslib-win32.c
126
@@ -XXX,XX +XXX,XX @@
127
/* this must come after including "trace.h" */
128
#include <shlobj.h>
129
130
-void *qemu_try_memalign(size_t alignment, size_t size)
131
-{
132
- void *ptr;
133
-
134
- if (alignment < sizeof(void *)) {
135
- alignment = sizeof(void *);
136
- } else {
137
- g_assert(is_power_of_2(alignment));
138
- }
139
- if (size == 0) {
140
- size++;
141
- }
142
- ptr = _aligned_malloc(size, alignment);
143
- trace_qemu_memalign(alignment, size, ptr);
144
- return ptr;
145
-}
146
-
147
static int get_allocation_granularity(void)
148
{
149
SYSTEM_INFO system_info;
150
--
110
--
151
2.25.1
111
2.34.1
152
112
153
113
diff view generated by jsdifflib
[PULL 17/18] target/arm: Provide cpu property for controling FEAT_LPA2
[PULL 10/19] target/arm: Use float_status in helper_fcvtx_f64_to_f32
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
There is a Linux kernel bug present until v5.12 that prevents
3
Pass float_status not env to match other functions.
4
booting with FEAT_LPA2 enabled. As a workaround for TCG, allow
5
the feature to be disabled from -cpu max.
6
7
Since this kernel bug is present in the Fedora 31 image that
8
we test in avocado, disable lpa2 on the command-line.
9
4
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20241206031952.78776-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
target/arm/cpu.h | 5 ++++-
10
target/arm/tcg/helper-a64.h | 2 +-
15
target/arm/cpu.c | 6 ++++++
11
target/arm/tcg/helper-a64.c | 3 +--
16
target/arm/cpu64.c | 24 ++++++++++++++++++++++++
12
target/arm/tcg/translate-a64.c | 2 +-
17
tests/avocado/boot_linux.py | 2 ++
13
3 files changed, 3 insertions(+), 4 deletions(-)
18
4 files changed, 36 insertions(+), 1 deletion(-)
19
14
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
17
--- a/target/arm/tcg/helper-a64.h
23
+++ b/target/arm/cpu.h
18
+++ b/target/arm/tcg/helper-a64.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
25
# define ARM_MAX_VQ 16
20
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
26
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
21
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
27
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
22
DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
28
+void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
23
-DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
29
#else
24
+DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, fpst)
30
# define ARM_MAX_VQ 1
25
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
31
static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
26
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
32
static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }
27
DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
33
+static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { }
28
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
34
#endif
35
36
typedef struct ARMVectorReg {
37
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
38
39
/*
40
* Intermediate values used during property parsing.
41
- * Once finalized, the values should be read from ID_AA64ISAR1.
42
+ * Once finalized, the values should be read from ID_AA64*.
43
*/
44
bool prop_pauth;
45
bool prop_pauth_impdef;
46
+ bool prop_lpa2;
47
48
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
49
uint32_t dcz_blocksize;
50
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
51
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/cpu.c
30
--- a/target/arm/tcg/helper-a64.c
53
+++ b/target/arm/cpu.c
31
+++ b/target/arm/tcg/helper-a64.c
54
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
32
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, float_status *fpst)
55
error_propagate(errp, local_err);
56
return;
57
}
58
+
59
+ arm_cpu_lpa2_finalize(cpu, &local_err);
60
+ if (local_err != NULL) {
61
+ error_propagate(errp, local_err);
62
+ return;
63
+ }
64
}
65
66
if (kvm_enabled()) {
67
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/cpu64.c
70
+++ b/target/arm/cpu64.c
71
@@ -XXX,XX +XXX,XX @@ void aarch64_add_pauth_properties(Object *obj)
72
}
33
}
73
}
34
}
74
35
75
+static Property arm_cpu_lpa2_property =
36
-float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
76
+ DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
37
+float32 HELPER(fcvtx_f64_to_f32)(float64 a, float_status *fpst)
77
+
78
+void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
79
+{
80
+ uint64_t t;
81
+
82
+ /*
83
+ * We only install the property for tcg -cpu max; this is the
84
+ * only situation in which the cpu field can be true.
85
+ */
86
+ if (!cpu->prop_lpa2) {
87
+ return;
88
+ }
89
+
90
+ t = cpu->isar.id_aa64mmfr0;
91
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */
92
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */
93
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */
94
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */
95
+ cpu->isar.id_aa64mmfr0 = t;
96
+}
97
+
98
static void aarch64_host_initfn(Object *obj)
99
{
38
{
100
#if defined(CONFIG_KVM)
39
float32 r;
101
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
40
- float_status *fpst = &env->vfp.fp_status;
102
aarch64_add_sve_properties(obj);
41
int old = get_float_rounding_mode(fpst);
103
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
42
104
cpu_max_set_sve_max_vq, NULL, NULL);
43
set_float_rounding_mode(float_round_to_odd, fpst);
105
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
44
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/tcg/translate-a64.c
47
+++ b/target/arm/tcg/translate-a64.c
48
@@ -XXX,XX +XXX,XX @@ static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
49
* with von Neumann rounding (round to odd)
50
*/
51
TCGv_i32 tmp = tcg_temp_new_i32();
52
- gen_helper_fcvtx_f64_to_f32(tmp, n, tcg_env);
53
+ gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_FPCR));
54
tcg_gen_extu_i32_i64(d, tmp);
106
}
55
}
107
56
108
static void aarch64_a64fx_initfn(Object *obj)
109
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
110
index XXXXXXX..XXXXXXX 100644
111
--- a/tests/avocado/boot_linux.py
112
+++ b/tests/avocado/boot_linux.py
113
@@ -XXX,XX +XXX,XX @@ def test_virt_tcg_gicv2(self):
114
"""
115
self.require_accelerator("tcg")
116
self.vm.add_args("-accel", "tcg")
117
+ self.vm.add_args("-cpu", "max,lpa2=off")
118
self.vm.add_args("-machine", "virt,gic-version=2")
119
self.add_common_args()
120
self.launch_and_wait(set_up_ssh_connection=False)
121
@@ -XXX,XX +XXX,XX @@ def test_virt_tcg_gicv3(self):
122
"""
123
self.require_accelerator("tcg")
124
self.vm.add_args("-accel", "tcg")
125
+ self.vm.add_args("-cpu", "max,lpa2=off")
126
self.vm.add_args("-machine", "virt,gic-version=3")
127
self.add_common_args()
128
self.launch_and_wait(set_up_ssh_connection=False)
129
--
57
--
130
2.25.1
58
2.34.1
59
60
diff view generated by jsdifflib
[PULL 01/18] util: Make qemu_oom_check() a static function
[PULL 11/19] target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
1
The qemu_oom_check() function, which we define in both oslib-posix.c
1
From: Richard Henderson <richard.henderson@linaro.org>
2
and oslib-win32.c, is now used only locally in that file; make it
3
static.
4
2
3
Pass float_status not env to match other functions.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20241206031952.78776-3-richard.henderson@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220226180723.1706285-3-peter.maydell@linaro.org
9
---
9
---
10
include/qemu-common.h | 2 --
10
target/arm/helper.h | 4 ++--
11
util/oslib-posix.c | 2 +-
11
target/arm/tcg/translate-a64.c | 15 ++++++++++-----
12
util/oslib-win32.c | 2 +-
12
target/arm/tcg/translate-vfp.c | 4 ++--
13
3 files changed, 2 insertions(+), 4 deletions(-)
13
target/arm/vfp_helper.c | 8 ++++----
14
4 files changed, 18 insertions(+), 13 deletions(-)
14
15
15
diff --git a/include/qemu-common.h b/include/qemu-common.h
16
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/include/qemu-common.h
18
--- a/target/arm/helper.h
18
+++ b/include/qemu-common.h
19
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env)
20
int qemu_main(int argc, char **argv, char **envp);
21
DEF_HELPER_3(vfp_cmpes, void, f32, f32, env)
21
#endif
22
DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
22
23
23
-void *qemu_oom_check(void *ptr);
24
-DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
24
-
25
-DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
25
ssize_t qemu_write_full(int fd, const void *buf, size_t count)
26
+DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst)
26
QEMU_WARN_UNUSED_RESULT;
27
+DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst)
27
28
DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
28
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
29
DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
30
31
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
30
--- a/util/oslib-posix.c
33
--- a/target/arm/tcg/translate-a64.c
31
+++ b/util/oslib-posix.c
34
+++ b/target/arm/tcg/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ fail_close:
35
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
33
return false;
36
if (fp_access_check(s)) {
37
TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn);
38
TCGv_i64 tcg_rd = tcg_temp_new_i64();
39
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
40
41
- gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env);
42
+ gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst);
43
write_fp_dreg(s, a->rd, tcg_rd);
44
}
45
return true;
46
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *a)
47
if (fp_access_check(s)) {
48
TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
49
TCGv_i32 tcg_rd = tcg_temp_new_i32();
50
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
51
52
- gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env);
53
+ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst);
54
write_fp_sreg(s, a->rd, tcg_rd);
55
}
56
return true;
57
@@ -XXX,XX +XXX,XX @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
58
static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
59
{
60
TCGv_i32 tmp = tcg_temp_new_i32();
61
- gen_helper_vfp_fcvtsd(tmp, n, tcg_env);
62
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
63
+
64
+ gen_helper_vfp_fcvtsd(tmp, n, fpst);
65
tcg_gen_extu_i32_i64(d, tmp);
34
}
66
}
35
67
36
-void *qemu_oom_check(void *ptr)
68
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
37
+static void *qemu_oom_check(void *ptr)
69
* The only instruction like this is FCVTL.
70
*/
71
int pass;
72
+ TCGv_ptr fpst;
73
74
if (!fp_access_check(s)) {
75
return true;
76
}
77
78
+ fpst = fpstatus_ptr(FPST_FPCR);
79
if (a->esz == MO_64) {
80
/* 32 -> 64 bit fp conversion */
81
TCGv_i64 tcg_res[2];
82
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
83
for (pass = 0; pass < 2; pass++) {
84
tcg_res[pass] = tcg_temp_new_i64();
85
read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32);
86
- gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env);
87
+ gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, fpst);
88
}
89
for (pass = 0; pass < 2; pass++) {
90
write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
91
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
92
/* 16 -> 32 bit fp conversion */
93
int srcelt = a->q ? 4 : 0;
94
TCGv_i32 tcg_res[4];
95
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
96
TCGv_i32 ahp = get_ahp_flag();
97
98
for (pass = 0; pass < 4; pass++) {
99
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/tcg/translate-vfp.c
102
+++ b/target/arm/tcg/translate-vfp.c
103
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
104
vm = tcg_temp_new_i32();
105
vd = tcg_temp_new_i64();
106
vfp_load_reg32(vm, a->vm);
107
- gen_helper_vfp_fcvtds(vd, vm, tcg_env);
108
+ gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR));
109
vfp_store_reg64(vd, a->vd);
110
return true;
111
}
112
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
113
vd = tcg_temp_new_i32();
114
vm = tcg_temp_new_i64();
115
vfp_load_reg64(vm, a->vm);
116
- gen_helper_vfp_fcvtsd(vd, vm, tcg_env);
117
+ gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR));
118
vfp_store_reg32(vd, a->vd);
119
return true;
120
}
121
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/arm/vfp_helper.c
124
+++ b/target/arm/vfp_helper.c
125
@@ -XXX,XX +XXX,XX @@ FLOAT_CONVS(ui, d, float64, 64, u)
126
#undef FLOAT_CONVS
127
128
/* floating point conversion */
129
-float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
130
+float64 VFP_HELPER(fcvtd, s)(float32 x, float_status *status)
38
{
131
{
39
if (ptr == NULL) {
132
- return float32_to_float64(x, &env->vfp.fp_status);
40
fprintf(stderr, "Failed to allocate memory: %s\n", strerror(errno));
133
+ return float32_to_float64(x, status);
41
diff --git a/util/oslib-win32.c b/util/oslib-win32.c
134
}
42
index XXXXXXX..XXXXXXX 100644
135
43
--- a/util/oslib-win32.c
136
-float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
44
+++ b/util/oslib-win32.c
137
+float32 VFP_HELPER(fcvts, d)(float64 x, float_status *status)
45
@@ -XXX,XX +XXX,XX @@
46
/* this must come after including "trace.h" */
47
#include <shlobj.h>
48
49
-void *qemu_oom_check(void *ptr)
50
+static void *qemu_oom_check(void *ptr)
51
{
138
{
52
if (ptr == NULL) {
139
- return float64_to_float32(x, &env->vfp.fp_status);
53
fprintf(stderr, "Failed to allocate memory: %lu\n", GetLastError());
140
+ return float64_to_float32(x, status);
141
}
142
143
uint32_t HELPER(bfcvt)(float32 x, float_status *status)
54
--
144
--
55
2.25.1
145
2.34.1
56
146
57
147
diff view generated by jsdifflib
[PULL 14/18] hw/intc/arm_gicv3: Fix missing spaces in error log messages
[PULL 12/19] target/arm: Implement fine-grained-trap handling for FEAT_XS
1
We forgot a space in some log messages, so the output ended
1
FEAT_XS introduces a set of new TLBI maintenance instructions with an
2
up looking like
2
"nXS" qualifier. These behave like the stardard ones except that
3
gicv3_dist_write: invalid guest write at offset 0000000000008000size 8
3
they do not wait for memory accesses with the XS attribute to
4
complete. They have an interaction with the fine-grained-trap
5
handling: the FGT bits that a hypervisor can use to trap TLBI
6
maintenance instructions normally trap also the nXS variants, but the
7
hypervisor can elect to not trap the nXS variants by setting
8
HCRX_EL2.FGTnXS to 1.
4
9
5
with a missing space before "size". Add the missing spaces.
10
Add support to our FGT mechanism for these TLBI bits. For each
11
TLBI-trapping FGT bit we define, for example:
12
* FGT_TLBIVAE1 -- the same value we do at present for the
13
normal variant of the insn
14
* FGT_TLBIVAE1NXS -- for the nXS qualified insn; the value of
15
this enum has an NXS bit ORed into it
16
17
In access_check_cp_reg() we can then ignore the trap bit for an
18
access where ri->fgt has the NXS bit set and HCRX_EL2.FGTnXS is 1.
6
19
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220303202341.2232284-5-peter.maydell@linaro.org
22
Message-id: 20241211144440.2700268-2-peter.maydell@linaro.org
10
---
23
---
11
hw/intc/arm_gicv3_dist.c | 4 ++--
24
target/arm/cpregs.h | 72 ++++++++++++++++++++++----------------
12
hw/intc/arm_gicv3_its.c | 4 ++--
25
target/arm/cpu-features.h | 5 +++
13
2 files changed, 4 insertions(+), 4 deletions(-)
26
target/arm/helper.c | 5 ++-
27
target/arm/tcg/op_helper.c | 11 +++++-
28
4 files changed, 61 insertions(+), 32 deletions(-)
14
29
15
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
30
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
16
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_dist.c
32
--- a/target/arm/cpregs.h
18
+++ b/hw/intc/arm_gicv3_dist.c
33
+++ b/target/arm/cpregs.h
19
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
34
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
20
if (!r) {
35
FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
21
qemu_log_mask(LOG_GUEST_ERROR,
36
FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
22
"%s: invalid guest read at offset " TARGET_FMT_plx
37
23
- "size %u\n", __func__, offset, size);
38
+FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */
24
+ " size %u\n", __func__, offset, size);
39
/* Which fine-grained trap bit register to check, if any */
25
trace_gicv3_dist_badread(offset, size, attrs.secure);
40
FIELD(FGT, TYPE, 10, 3)
26
/* The spec requires that reserved registers are RAZ/WI;
41
FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
27
* so use MEMTX_ERROR returns from leaf functions as a way to
42
@@ -XXX,XX +XXX,XX @@ FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
28
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data,
43
#define DO_REV_BIT(REG, BITNAME) \
29
if (!r) {
44
FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
30
qemu_log_mask(LOG_GUEST_ERROR,
45
31
"%s: invalid guest write at offset " TARGET_FMT_plx
46
+/*
32
- "size %u\n", __func__, offset, size);
47
+ * The FGT bits for TLBI maintenance instructions accessible at EL1 always
33
+ " size %u\n", __func__, offset, size);
48
+ * affect the "normal" TLBI insns; they affect the corresponding TLBI insns
34
trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
49
+ * with the nXS qualifier only if HCRX_EL2.FGTnXS is 0. We define e.g.
35
/* The spec requires that reserved registers are RAZ/WI;
50
+ * FGT_TLBIVAE1 to use for the normal insn, and FGT_TLBIVAE1NXS to use
36
* so use MEMTX_ERROR returns from leaf functions as a way to
51
+ * for the nXS qualified insn.
37
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
52
+ */
53
+#define DO_TLBINXS_BIT(REG, BITNAME) \
54
+ FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \
55
+ FGT_##BITNAME##NXS = FGT_##BITNAME | R_FGT_NXS_MASK
56
+
57
typedef enum FGTBit {
58
/*
59
* These bits tell us which register arrays to use:
60
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
61
DO_BIT(HFGITR, ATS1E0W),
62
DO_BIT(HFGITR, ATS1E1RP),
63
DO_BIT(HFGITR, ATS1E1WP),
64
- DO_BIT(HFGITR, TLBIVMALLE1OS),
65
- DO_BIT(HFGITR, TLBIVAE1OS),
66
- DO_BIT(HFGITR, TLBIASIDE1OS),
67
- DO_BIT(HFGITR, TLBIVAAE1OS),
68
- DO_BIT(HFGITR, TLBIVALE1OS),
69
- DO_BIT(HFGITR, TLBIVAALE1OS),
70
- DO_BIT(HFGITR, TLBIRVAE1OS),
71
- DO_BIT(HFGITR, TLBIRVAAE1OS),
72
- DO_BIT(HFGITR, TLBIRVALE1OS),
73
- DO_BIT(HFGITR, TLBIRVAALE1OS),
74
- DO_BIT(HFGITR, TLBIVMALLE1IS),
75
- DO_BIT(HFGITR, TLBIVAE1IS),
76
- DO_BIT(HFGITR, TLBIASIDE1IS),
77
- DO_BIT(HFGITR, TLBIVAAE1IS),
78
- DO_BIT(HFGITR, TLBIVALE1IS),
79
- DO_BIT(HFGITR, TLBIVAALE1IS),
80
- DO_BIT(HFGITR, TLBIRVAE1IS),
81
- DO_BIT(HFGITR, TLBIRVAAE1IS),
82
- DO_BIT(HFGITR, TLBIRVALE1IS),
83
- DO_BIT(HFGITR, TLBIRVAALE1IS),
84
- DO_BIT(HFGITR, TLBIRVAE1),
85
- DO_BIT(HFGITR, TLBIRVAAE1),
86
- DO_BIT(HFGITR, TLBIRVALE1),
87
- DO_BIT(HFGITR, TLBIRVAALE1),
88
- DO_BIT(HFGITR, TLBIVMALLE1),
89
- DO_BIT(HFGITR, TLBIVAE1),
90
- DO_BIT(HFGITR, TLBIASIDE1),
91
- DO_BIT(HFGITR, TLBIVAAE1),
92
- DO_BIT(HFGITR, TLBIVALE1),
93
- DO_BIT(HFGITR, TLBIVAALE1),
94
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1OS),
95
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1OS),
96
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1OS),
97
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1OS),
98
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1OS),
99
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1OS),
100
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1OS),
101
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1OS),
102
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1OS),
103
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1OS),
104
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1IS),
105
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1IS),
106
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1IS),
107
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1IS),
108
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1IS),
109
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1IS),
110
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1IS),
111
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1IS),
112
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1IS),
113
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1IS),
114
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1),
115
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1),
116
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1),
117
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1),
118
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1),
119
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1),
120
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1),
121
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1),
122
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1),
123
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1),
124
DO_BIT(HFGITR, CFPRCTX),
125
DO_BIT(HFGITR, DVPRCTX),
126
DO_BIT(HFGITR, CPPRCTX),
127
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
38
index XXXXXXX..XXXXXXX 100644
128
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/intc/arm_gicv3_its.c
129
--- a/target/arm/cpu-features.h
40
+++ b/hw/intc/arm_gicv3_its.c
130
+++ b/target/arm/cpu-features.h
41
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
131
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
42
if (!result) {
132
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
43
qemu_log_mask(LOG_GUEST_ERROR,
133
}
44
"%s: invalid guest read at offset " TARGET_FMT_plx
134
45
- "size %u\n", __func__, offset, size);
135
+static inline bool isar_feature_aa64_xs(const ARMISARegisters *id)
46
+ " size %u\n", __func__, offset, size);
136
+{
47
trace_gicv3_its_badread(offset, size);
137
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) != 0;
48
/*
138
+}
49
* The spec requires that reserved registers are RAZ/WI;
139
+
50
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
140
/*
51
if (!result) {
141
* These are the values from APA/API/APA3.
52
qemu_log_mask(LOG_GUEST_ERROR,
142
* In general these must be compared '>=', per the normal Arm ARM
53
"%s: invalid guest write at offset " TARGET_FMT_plx
143
diff --git a/target/arm/helper.c b/target/arm/helper.c
54
- "size %u\n", __func__, offset, size);
144
index XXXXXXX..XXXXXXX 100644
55
+ " size %u\n", __func__, offset, size);
145
--- a/target/arm/helper.c
56
trace_gicv3_its_badwrite(offset, data, size);
146
+++ b/target/arm/helper.c
57
/*
147
@@ -XXX,XX +XXX,XX @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
58
* The spec requires that reserved registers are RAZ/WI;
148
valid_mask |= HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI;
149
}
150
/* FEAT_CMOW adds CMOW */
151
-
152
if (cpu_isar_feature(aa64_cmow, cpu)) {
153
valid_mask |= HCRX_CMOW;
154
}
155
+ /* FEAT_XS adds FGTnXS, FnXS */
156
+ if (cpu_isar_feature(aa64_xs, cpu)) {
157
+ valid_mask |= HCRX_FGTNXS | HCRX_FNXS;
158
+ }
159
160
/* Clear RES0 bits. */
161
env->cp15.hcrx_el2 = value & valid_mask;
162
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
163
index XXXXXXX..XXXXXXX 100644
164
--- a/target/arm/tcg/op_helper.c
165
+++ b/target/arm/tcg/op_helper.c
166
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
167
unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
168
unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
169
bool rev = FIELD_EX32(ri->fgt, FGT, REV);
170
+ bool nxs = FIELD_EX32(ri->fgt, FGT, NXS);
171
bool trapbit;
172
173
if (ri->fgt & FGT_EXEC) {
174
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
175
trapword = env->cp15.fgt_write[idx];
176
}
177
178
- trapbit = extract64(trapword, bitpos, 1);
179
+ if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) {
180
+ /*
181
+ * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for
182
+ * TLBI maintenance insns does *not* apply to the nXS variant.
183
+ */
184
+ trapbit = 0;
185
+ } else {
186
+ trapbit = extract64(trapword, bitpos, 1);
187
+ }
188
if (trapbit != rev) {
189
res = CP_ACCESS_TRAP_EL2;
190
goto fail;
59
--
191
--
60
2.25.1
192
2.34.1
diff view generated by jsdifflib
[PULL 10/18] target/arm/translate-neon: Simplify align field check for VLD3
[PULL 13/19] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns
1
For VLD3 (single 3-element structure to one lane), there is no
1
All of the TLBI insns with an NXS variant put that variant at the
2
alignment specification and the alignment bits in the instruction
2
same encoding but with a CRn field that is one greater than for the
3
must be zero. This is bit [4] for the size=0 and size=1 cases, and
3
original TLBI insn. To avoid having to define every TLBI insn
4
bits [5:4] for the size=2 case. We do this check correctly in
4
effectively twice, once in the normal way and once in a set of cpreg
5
VLDST_single(), but we write it a bit oddly: in the 'case 3' code we
5
arrays that are only registered when FEAT_XS is present, we define a
6
check for bit 0 of a->align (bit [4] of the insn), and then we fall
6
new ARM_CP_ADD_TLB_NXS type flag for cpregs. When this flag is set
7
through to the 'case 2' code which checks bit 1 of a->align (bit [5]
7
in a cpreg struct and FEAT_XS is present,
8
of the insn) in the size 2 case. Replace this with just checking "is
8
define_one_arm_cp_reg_with_opaque() will automatically add a second
9
a->align non-zero" for VLD3, which lets us drop the fall-through and
9
cpreg to the hash table for the TLBI NXS insn with:
10
put the cases in this switch in numerical order.
10
* the crn+1 encoding
11
* an FGT field that indicates that it should honour HCR_EL2.FGTnXS
12
* a name with the "NXS" suffix
13
14
(If there are future TLBI NXS insns that don't use this same
15
encoding convention, it is also possible to define them manually.)
11
16
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20241211144440.2700268-3-peter.maydell@linaro.org
15
Message-id: 20220303113741.2156877-3-peter.maydell@linaro.org
16
---
20
---
17
target/arm/translate-neon.c | 10 +++++-----
21
target/arm/cpregs.h | 8 ++++++++
18
1 file changed, 5 insertions(+), 5 deletions(-)
22
target/arm/helper.c | 25 +++++++++++++++++++++++++
23
2 files changed, 33 insertions(+)
19
24
20
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
25
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
21
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/translate-neon.c
27
--- a/target/arm/cpregs.h
23
+++ b/target/arm/translate-neon.c
28
+++ b/target/arm/cpregs.h
24
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
29
@@ -XXX,XX +XXX,XX @@ enum {
25
return false;
30
* equivalent EL1 register when FEAT_NV2 is enabled.
26
}
31
*/
27
break;
32
ARM_CP_NV2_REDIRECT = 1 << 20,
28
- case 3:
33
+ /*
29
- if ((a->align & 1) != 0) {
34
+ * Flag: this is a TLBI insn which (when FEAT_XS is present) also has
30
- return false;
35
+ * an NXS variant at the same encoding except that crn is 1 greater,
31
- }
36
+ * so when registering this cpreg automatically also register one
32
- /* fall through */
37
+ * for the TLBI NXS variant. (For QEMU the NXS variant behaves
33
case 2:
38
+ * identically to the normal one, other than FGT trapping handling.)
34
if (a->size == 2 && (a->align & 2) != 0) {
39
+ */
35
return false;
40
+ ARM_CP_ADD_TLBI_NXS = 1 << 21,
36
}
41
};
37
break;
42
38
+ case 3:
43
/*
39
+ if (a->align != 0) {
44
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
+ return false;
45
index XXXXXXX..XXXXXXX 100644
41
+ }
46
--- a/target/arm/helper.c
42
+ break;
47
+++ b/target/arm/helper.c
43
case 4:
48
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
44
if (a->size == 2 && a->align == 3) {
49
if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
45
return false;
50
continue;
51
}
52
+ if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
53
+ cpu_isar_feature(aa64_xs, cpu)) {
54
+ /*
55
+ * This is a TLBI insn which has an NXS variant. The
56
+ * NXS variant is at the same encoding except that
57
+ * crn is +1, and has the same behaviour except for
58
+ * fine-grained trapping. Add the NXS insn here and
59
+ * then fall through to add the normal register.
60
+ * add_cpreg_to_hashtable() copies the cpreg struct
61
+ * and name that it is passed, so it's OK to use
62
+ * a local struct here.
63
+ */
64
+ ARMCPRegInfo nxs_ri = *r;
65
+ g_autofree char *name = g_strdup_printf("%sNXS", r->name);
66
+
67
+ assert(state == ARM_CP_STATE_AA64);
68
+ assert(nxs_ri.crn < 0xf);
69
+ nxs_ri.crn++;
70
+ if (nxs_ri.fgt) {
71
+ nxs_ri.fgt |= R_FGT_NXS_MASK;
72
+ }
73
+ add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state,
74
+ ARM_CP_SECSTATE_NS,
75
+ crm, opc1, opc2, name);
76
+ }
77
if (state == ARM_CP_STATE_AA32) {
78
/*
79
* Under AArch32 CP registers can be common
46
--
80
--
47
2.25.1
81
2.34.1
diff view generated by jsdifflib
[PULL 13/18] hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps
[PULL 14/19] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns
1
The GICv3 has some registers that support byte accesses, and some
1
Add the ARM_CP_ADD_TLBI_NXS to the TLBI insns with an NXS variant.
2
that support 8-byte accesses. Our TCG implementation implements all
2
This is every AArch64 TLBI encoding except for the four FEAT_RME TLBI
3
of this, switching on the 'size' argument and handling the registers
3
insns.
4
that must support reads of that size while logging an error for
5
attempted accesses to registers that do not support that size access.
6
However we forgot to tell the core memory subsystem about this by
7
specifying the .impl and .valid fields in the MemoryRegionOps struct,
8
so the core was happily simulating 8 byte accesses by combining two 4
9
byte accesses. This doesn't have much guest-visible effect, since
10
there aren't many 8 byte registers and they all support being written
11
in two 4 byte parts.
12
13
Set the .impl and .valid fields to say that all sizes from 1 to 8
14
bytes are both valid and implemented by the device.
15
4
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20220303202341.2232284-4-peter.maydell@linaro.org
7
Message-id: 20241211144440.2700268-4-peter.maydell@linaro.org
19
---
8
---
20
hw/intc/arm_gicv3.c | 8 ++++++++
9
target/arm/tcg/tlb-insns.c | 202 +++++++++++++++++++++++--------------
21
1 file changed, 8 insertions(+)
10
1 file changed, 124 insertions(+), 78 deletions(-)
22
11
23
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
12
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
24
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/intc/arm_gicv3.c
14
--- a/target/arm/tcg/tlb-insns.c
26
+++ b/hw/intc/arm_gicv3.c
15
+++ b/target/arm/tcg/tlb-insns.c
27
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps gic_ops[] = {
16
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbi_v8_cp_reginfo[] = {
28
.read_with_attrs = gicv3_dist_read,
17
/* AArch64 TLBI operations */
29
.write_with_attrs = gicv3_dist_write,
18
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
30
.endianness = DEVICE_NATIVE_ENDIAN,
19
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
31
+ .valid.min_access_size = 1,
20
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
32
+ .valid.max_access_size = 8,
21
+ .access = PL1_W, .accessfn = access_ttlbis,
33
+ .impl.min_access_size = 1,
22
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
34
+ .impl.max_access_size = 8,
23
.fgt = FGT_TLBIVMALLE1IS,
35
},
24
.writefn = tlbi_aa64_vmalle1is_write },
36
{
25
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
37
.read_with_attrs = gicv3_redist_read,
26
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
38
.write_with_attrs = gicv3_redist_write,
27
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
39
.endianness = DEVICE_NATIVE_ENDIAN,
28
+ .access = PL1_W, .accessfn = access_ttlbis,
40
+ .valid.min_access_size = 1,
29
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
41
+ .valid.max_access_size = 8,
30
.fgt = FGT_TLBIVAE1IS,
42
+ .impl.min_access_size = 1,
31
.writefn = tlbi_aa64_vae1is_write },
43
+ .impl.max_access_size = 8,
32
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
44
}
33
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
34
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
35
+ .access = PL1_W, .accessfn = access_ttlbis,
36
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
37
.fgt = FGT_TLBIASIDE1IS,
38
.writefn = tlbi_aa64_vmalle1is_write },
39
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
40
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
41
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
42
+ .access = PL1_W, .accessfn = access_ttlbis,
43
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
44
.fgt = FGT_TLBIVAAE1IS,
45
.writefn = tlbi_aa64_vae1is_write },
46
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
47
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
48
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
49
+ .access = PL1_W, .accessfn = access_ttlbis,
50
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
51
.fgt = FGT_TLBIVALE1IS,
52
.writefn = tlbi_aa64_vae1is_write },
53
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
54
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
55
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
56
+ .access = PL1_W, .accessfn = access_ttlbis,
57
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
58
.fgt = FGT_TLBIVAALE1IS,
59
.writefn = tlbi_aa64_vae1is_write },
60
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
61
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
62
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
63
+ .access = PL1_W, .accessfn = access_ttlb,
64
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
65
.fgt = FGT_TLBIVMALLE1,
66
.writefn = tlbi_aa64_vmalle1_write },
67
{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
68
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
69
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
70
+ .access = PL1_W, .accessfn = access_ttlb,
71
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
72
.fgt = FGT_TLBIVAE1,
73
.writefn = tlbi_aa64_vae1_write },
74
{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
75
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
76
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
77
+ .access = PL1_W, .accessfn = access_ttlb,
78
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
79
.fgt = FGT_TLBIASIDE1,
80
.writefn = tlbi_aa64_vmalle1_write },
81
{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
82
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
83
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
84
+ .access = PL1_W, .accessfn = access_ttlb,
85
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
86
.fgt = FGT_TLBIVAAE1,
87
.writefn = tlbi_aa64_vae1_write },
88
{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
89
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
90
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
91
+ .access = PL1_W, .accessfn = access_ttlb,
92
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
93
.fgt = FGT_TLBIVALE1,
94
.writefn = tlbi_aa64_vae1_write },
95
{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
96
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
97
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
98
+ .access = PL1_W, .accessfn = access_ttlb,
99
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
100
.fgt = FGT_TLBIVAALE1,
101
.writefn = tlbi_aa64_vae1_write },
102
{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
103
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
104
- .access = PL2_W, .type = ARM_CP_NO_RAW,
105
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
106
.writefn = tlbi_aa64_ipas2e1is_write },
107
{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
108
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
109
- .access = PL2_W, .type = ARM_CP_NO_RAW,
110
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
111
.writefn = tlbi_aa64_ipas2e1is_write },
112
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
113
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
114
- .access = PL2_W, .type = ARM_CP_NO_RAW,
115
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
116
.writefn = tlbi_aa64_alle1is_write },
117
{ .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
118
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
119
- .access = PL2_W, .type = ARM_CP_NO_RAW,
120
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
121
.writefn = tlbi_aa64_alle1is_write },
122
{ .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
123
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
124
- .access = PL2_W, .type = ARM_CP_NO_RAW,
125
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
126
.writefn = tlbi_aa64_ipas2e1_write },
127
{ .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
128
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
129
- .access = PL2_W, .type = ARM_CP_NO_RAW,
130
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
131
.writefn = tlbi_aa64_ipas2e1_write },
132
{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
134
- .access = PL2_W, .type = ARM_CP_NO_RAW,
135
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
136
.writefn = tlbi_aa64_alle1_write },
137
{ .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
138
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
139
- .access = PL2_W, .type = ARM_CP_NO_RAW,
140
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
141
.writefn = tlbi_aa64_alle1is_write },
45
};
142
};
46
143
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbi_el2_cp_reginfo[] = {
145
.writefn = tlbimva_hyp_is_write },
146
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
147
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
148
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
149
+ .access = PL2_W,
150
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
151
.writefn = tlbi_aa64_alle2_write },
152
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
153
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
154
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
155
+ .access = PL2_W,
156
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
157
.writefn = tlbi_aa64_vae2_write },
158
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
159
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
160
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
161
+ .access = PL2_W,
162
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
163
.writefn = tlbi_aa64_vae2_write },
164
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
165
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
166
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
167
+ .access = PL2_W,
168
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
169
.writefn = tlbi_aa64_alle2is_write },
170
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
172
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
173
+ .access = PL2_W,
174
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
175
.writefn = tlbi_aa64_vae2is_write },
176
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
177
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
178
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
179
+ .access = PL2_W,
180
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
181
.writefn = tlbi_aa64_vae2is_write },
182
};
183
184
static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = {
185
{ .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
186
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
187
- .access = PL3_W, .type = ARM_CP_NO_RAW,
188
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
189
.writefn = tlbi_aa64_alle3is_write },
190
{ .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
191
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
192
- .access = PL3_W, .type = ARM_CP_NO_RAW,
193
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
194
.writefn = tlbi_aa64_vae3is_write },
195
{ .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
196
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
197
- .access = PL3_W, .type = ARM_CP_NO_RAW,
198
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
199
.writefn = tlbi_aa64_vae3is_write },
200
{ .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
201
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
202
- .access = PL3_W, .type = ARM_CP_NO_RAW,
203
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
204
.writefn = tlbi_aa64_alle3_write },
205
{ .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
206
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
207
- .access = PL3_W, .type = ARM_CP_NO_RAW,
208
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
209
.writefn = tlbi_aa64_vae3_write },
210
{ .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
211
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
212
- .access = PL3_W, .type = ARM_CP_NO_RAW,
213
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
214
.writefn = tlbi_aa64_vae3_write },
215
};
216
217
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
218
static const ARMCPRegInfo tlbirange_reginfo[] = {
219
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
220
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
221
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
222
+ .access = PL1_W, .accessfn = access_ttlbis,
223
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
224
.fgt = FGT_TLBIRVAE1IS,
225
.writefn = tlbi_aa64_rvae1is_write },
226
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
227
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
228
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
229
+ .access = PL1_W, .accessfn = access_ttlbis,
230
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
231
.fgt = FGT_TLBIRVAAE1IS,
232
.writefn = tlbi_aa64_rvae1is_write },
233
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
234
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
235
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
236
+ .access = PL1_W, .accessfn = access_ttlbis,
237
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
238
.fgt = FGT_TLBIRVALE1IS,
239
.writefn = tlbi_aa64_rvae1is_write },
240
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
241
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
242
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
243
+ .access = PL1_W, .accessfn = access_ttlbis,
244
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
245
.fgt = FGT_TLBIRVAALE1IS,
246
.writefn = tlbi_aa64_rvae1is_write },
247
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
248
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
249
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
250
+ .access = PL1_W, .accessfn = access_ttlbos,
251
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
252
.fgt = FGT_TLBIRVAE1OS,
253
.writefn = tlbi_aa64_rvae1is_write },
254
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
255
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
256
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
257
+ .access = PL1_W, .accessfn = access_ttlbos,
258
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
259
.fgt = FGT_TLBIRVAAE1OS,
260
.writefn = tlbi_aa64_rvae1is_write },
261
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
262
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
263
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
264
+ .access = PL1_W, .accessfn = access_ttlbos,
265
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
266
.fgt = FGT_TLBIRVALE1OS,
267
.writefn = tlbi_aa64_rvae1is_write },
268
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
269
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
270
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
271
+ .access = PL1_W, .accessfn = access_ttlbos,
272
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
273
.fgt = FGT_TLBIRVAALE1OS,
274
.writefn = tlbi_aa64_rvae1is_write },
275
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
277
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
278
+ .access = PL1_W, .accessfn = access_ttlb,
279
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
280
.fgt = FGT_TLBIRVAE1,
281
.writefn = tlbi_aa64_rvae1_write },
282
{ .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
283
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
284
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
285
+ .access = PL1_W, .accessfn = access_ttlb,
286
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
287
.fgt = FGT_TLBIRVAAE1,
288
.writefn = tlbi_aa64_rvae1_write },
289
{ .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
290
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
291
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
292
+ .access = PL1_W, .accessfn = access_ttlb,
293
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
294
.fgt = FGT_TLBIRVALE1,
295
.writefn = tlbi_aa64_rvae1_write },
296
{ .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
297
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
298
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
299
+ .access = PL1_W, .accessfn = access_ttlb,
300
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
301
.fgt = FGT_TLBIRVAALE1,
302
.writefn = tlbi_aa64_rvae1_write },
303
{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
304
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
305
- .access = PL2_W, .type = ARM_CP_NO_RAW,
306
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
307
.writefn = tlbi_aa64_ripas2e1is_write },
308
{ .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64,
309
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6,
310
- .access = PL2_W, .type = ARM_CP_NO_RAW,
311
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
312
.writefn = tlbi_aa64_ripas2e1is_write },
313
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
314
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
315
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
316
+ .access = PL2_W,
317
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
318
.writefn = tlbi_aa64_rvae2is_write },
319
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
320
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
321
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
322
+ .access = PL2_W,
323
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
324
.writefn = tlbi_aa64_rvae2is_write },
325
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
327
- .access = PL2_W, .type = ARM_CP_NO_RAW,
328
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
329
.writefn = tlbi_aa64_ripas2e1_write },
330
{ .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
331
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6,
332
- .access = PL2_W, .type = ARM_CP_NO_RAW,
333
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
334
.writefn = tlbi_aa64_ripas2e1_write },
335
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
336
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
337
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
338
+ .access = PL2_W,
339
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
340
.writefn = tlbi_aa64_rvae2is_write },
341
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
342
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
343
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
344
+ .access = PL2_W,
345
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
346
.writefn = tlbi_aa64_rvae2is_write },
347
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
348
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
349
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
350
+ .access = PL2_W,
351
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
352
.writefn = tlbi_aa64_rvae2_write },
353
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
354
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
355
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
356
+ .access = PL2_W,
357
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
358
.writefn = tlbi_aa64_rvae2_write },
359
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
360
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
361
- .access = PL3_W, .type = ARM_CP_NO_RAW,
362
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
363
.writefn = tlbi_aa64_rvae3is_write },
364
{ .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64,
365
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5,
366
- .access = PL3_W, .type = ARM_CP_NO_RAW,
367
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
368
.writefn = tlbi_aa64_rvae3is_write },
369
{ .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64,
370
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1,
371
- .access = PL3_W, .type = ARM_CP_NO_RAW,
372
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
373
.writefn = tlbi_aa64_rvae3is_write },
374
{ .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64,
375
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5,
376
- .access = PL3_W, .type = ARM_CP_NO_RAW,
377
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
378
.writefn = tlbi_aa64_rvae3is_write },
379
{ .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64,
380
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1,
381
- .access = PL3_W, .type = ARM_CP_NO_RAW,
382
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
383
.writefn = tlbi_aa64_rvae3_write },
384
{ .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64,
385
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
386
- .access = PL3_W, .type = ARM_CP_NO_RAW,
387
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
388
.writefn = tlbi_aa64_rvae3_write },
389
};
390
391
static const ARMCPRegInfo tlbios_reginfo[] = {
392
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
393
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
394
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
395
+ .access = PL1_W, .accessfn = access_ttlbos,
396
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
397
.fgt = FGT_TLBIVMALLE1OS,
398
.writefn = tlbi_aa64_vmalle1is_write },
399
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
400
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
401
.fgt = FGT_TLBIVAE1OS,
402
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
403
+ .access = PL1_W, .accessfn = access_ttlbos,
404
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
405
.writefn = tlbi_aa64_vae1is_write },
406
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
407
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
408
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
409
+ .access = PL1_W, .accessfn = access_ttlbos,
410
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
411
.fgt = FGT_TLBIASIDE1OS,
412
.writefn = tlbi_aa64_vmalle1is_write },
413
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
414
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
415
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
416
+ .access = PL1_W, .accessfn = access_ttlbos,
417
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
418
.fgt = FGT_TLBIVAAE1OS,
419
.writefn = tlbi_aa64_vae1is_write },
420
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
421
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
422
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
423
+ .access = PL1_W, .accessfn = access_ttlbos,
424
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
425
.fgt = FGT_TLBIVALE1OS,
426
.writefn = tlbi_aa64_vae1is_write },
427
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
428
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
429
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
430
+ .access = PL1_W, .accessfn = access_ttlbos,
431
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
432
.fgt = FGT_TLBIVAALE1OS,
433
.writefn = tlbi_aa64_vae1is_write },
434
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
435
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
436
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
437
+ .access = PL2_W,
438
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
439
.writefn = tlbi_aa64_alle2is_write },
440
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
441
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
442
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
443
+ .access = PL2_W,
444
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
445
.writefn = tlbi_aa64_vae2is_write },
446
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
447
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
448
- .access = PL2_W, .type = ARM_CP_NO_RAW,
449
+ .access = PL2_W,
450
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
451
.writefn = tlbi_aa64_alle1is_write },
452
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
453
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
454
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
455
+ .access = PL2_W,
456
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
457
.writefn = tlbi_aa64_vae2is_write },
458
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
459
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
460
- .access = PL2_W, .type = ARM_CP_NO_RAW,
461
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
462
.writefn = tlbi_aa64_alle1is_write },
463
{ .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64,
464
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0,
465
- .access = PL2_W, .type = ARM_CP_NOP },
466
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
467
{ .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64,
468
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3,
469
- .access = PL2_W, .type = ARM_CP_NOP },
470
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
471
{ .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64,
472
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4,
473
- .access = PL2_W, .type = ARM_CP_NOP },
474
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
475
{ .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64,
476
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7,
477
- .access = PL2_W, .type = ARM_CP_NOP },
478
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
479
{ .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64,
480
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0,
481
- .access = PL3_W, .type = ARM_CP_NO_RAW,
482
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
483
.writefn = tlbi_aa64_alle3is_write },
484
{ .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64,
485
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1,
486
- .access = PL3_W, .type = ARM_CP_NO_RAW,
487
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
488
.writefn = tlbi_aa64_vae3is_write },
489
{ .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64,
490
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
491
- .access = PL3_W, .type = ARM_CP_NO_RAW,
492
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
493
.writefn = tlbi_aa64_vae3is_write },
494
};
495
47
--
496
--
48
2.25.1
497
2.34.1
diff view generated by jsdifflib
[PULL 15/18] hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event
[PULL 15/19] target/arm: Add decodetree entry for DSB nXS variant
1
The trace_gicv3_icv_hppir_read trace event takes an integer value
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
2
which it uses to form the register name, which should be either
3
ICV_HPPIR0 or ICV_HPPIR1. We were passing in the 'grp' variable for
4
this, but that is either GICV3_G0 or GICV3_G1NS, which happen to be 0
5
and 2, which meant that tracing for the ICV_HPPIR1 register was
6
incorrectly printed as ICV_HPPIR2.
7
2
8
Use the same approach we do for all the other similar trace events,
3
The DSB nXS variant is always both a reads and writes request type.
9
and pass in 'ri->crm == 8 ? 0 : 1', deriving the index value
4
Ignore the domain field like we do in plain DSB and perform a full
10
directly from the ARMCPRegInfo struct.
5
system barrier operation.
11
6
7
The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.
8
9
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220303202341.2232284-6-peter.maydell@linaro.org
12
Message-id: 20241211144440.2700268-5-peter.maydell@linaro.org
13
[PMM: added missing "UNDEF unless feature present" check]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
15
---
16
hw/intc/arm_gicv3_cpuif.c | 3 ++-
16
target/arm/tcg/a64.decode | 3 +++
17
1 file changed, 2 insertions(+), 1 deletion(-)
17
target/arm/tcg/translate-a64.c | 9 +++++++++
18
2 files changed, 12 insertions(+)
18
19
19
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
20
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
20
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/intc/arm_gicv3_cpuif.c
22
--- a/target/arm/tcg/a64.decode
22
+++ b/hw/intc/arm_gicv3_cpuif.c
23
+++ b/target/arm/tcg/a64.decode
23
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri)
24
@@ -XXX,XX +XXX,XX @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5
24
}
25
25
}
26
CLREX 1101 0101 0000 0011 0011 ---- 010 11111
26
27
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
27
- trace_gicv3_icv_hppir_read(grp, gicv3_redist_affid(cs), value);
28
+# For the DSB nXS variant, types always equals MBReqTypes_All and we ignore the
28
+ trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1,
29
+# domain bits.
29
+ gicv3_redist_affid(cs), value);
30
+DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111
30
return value;
31
ISB 1101 0101 0000 0011 0011 ---- 110 11111
32
SB 1101 0101 0000 0011 0011 0000 111 11111
33
34
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/tcg/translate-a64.c
37
+++ b/target/arm/tcg/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a)
39
return true;
31
}
40
}
32
41
42
+static bool trans_DSB_nXS(DisasContext *s, arg_DSB_nXS *a)
43
+{
44
+ if (!dc_isar_feature(aa64_xs, s)) {
45
+ return false;
46
+ }
47
+ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
48
+ return true;
49
+}
50
+
51
static bool trans_ISB(DisasContext *s, arg_ISB *a)
52
{
53
/*
33
--
54
--
34
2.25.1
55
2.34.1
diff view generated by jsdifflib
[PULL 09/18] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
[PULL 16/19] target/arm: Enable FEAT_XS for the max cpu
1
For VLD1/VST1 (single element to one lane) we are only accessing one
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
2
register, and so the 'stride' is meaningless. The bits that would
3
specify stride (insn bit [4] for size=1, bit [6] for size=2) are
4
specified to be zero in the encoding (which would correspond to a
5
stride of 1 for VLD2/VLD3/VLD4 etc), and we must UNDEF if they are
6
not.
7
2
8
We failed to make this check, which meant that we would incorrectly
3
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
9
handle some instruction patterns as loads or stores instead of
10
UNDEFing them. Enforce that stride == 1 for the nregs == 1 case.
11
4
12
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/890
5
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Tested-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241211144440.2700268-6-peter.maydell@linaro.org
16
Message-id: 20220303113741.2156877-2-peter.maydell@linaro.org
9
[PMM: Add entry for FEAT_XS to documentation]
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
---
11
---
18
target/arm/translate-neon.c | 3 +++
12
docs/system/arm/emulation.rst | 1 +
19
1 file changed, 3 insertions(+)
13
target/arm/tcg/cpu64.c | 1 +
14
2 files changed, 2 insertions(+)
20
15
21
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
22
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/translate-neon.c
18
--- a/docs/system/arm/emulation.rst
24
+++ b/target/arm/translate-neon.c
19
+++ b/docs/system/arm/emulation.rst
25
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
26
/* Catch the UNDEF cases. This is unavoidably a bit messy. */
21
- FEAT_VMID16 (16-bit VMID)
27
switch (nregs) {
22
- FEAT_WFxT (WFE and WFI instructions with timeout)
28
case 1:
23
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
29
+ if (a->stride != 1) {
24
+- FEAT_XS (XS attribute)
30
+ return false;
25
31
+ }
26
For information on the specifics of these extensions, please refer
32
if (((a->align & (1 << a->size)) != 0) ||
27
to the `Arm Architecture Reference Manual for A-profile architecture
33
(a->size == 2 && (a->align == 1 || a->align == 2))) {
28
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
34
return false;
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/tcg/cpu64.c
31
+++ b/target/arm/tcg/cpu64.c
32
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
33
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */
34
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
35
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
36
+ t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
37
cpu->isar.id_aa64isar1 = t;
38
39
t = cpu->isar.id_aa64isar2;
35
--
40
--
36
2.25.1
41
2.34.1
diff view generated by jsdifflib
[PULL 08/18] osdep: Move memalign-related functions to their own header
[PULL 17/19] tests/tcg/aarch64: add system test for FEAT_XS
1
Move the various memalign-related functions out of osdep.h and into
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
2
their own header, which we include only where they are used.
3
While we're doing this, add some brief documentation comments.
4
2
3
Add system test to make sure FEAT_XS is enabled for max cpu emulation
4
and that QEMU doesn't crash when encountering an NXS instruction
5
variant.
6
7
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241211144440.2700268-7-peter.maydell@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
[PMM: In ISAR field test, mask with 0xf, not 0xff; use < rather
8
Message-id: 20220226180723.1706285-10-peter.maydell@linaro.org
11
than an equality test to follow the standard ID register field
12
check guidelines]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
14
---
10
include/qemu/memalign.h | 61 ++++++++++++++++++++++++++++++++++
15
tests/tcg/aarch64/system/feat-xs.c | 27 +++++++++++++++++++++++++++
11
include/qemu/osdep.h | 18 ----------
16
1 file changed, 27 insertions(+)
12
block/blkverify.c | 1 +
17
create mode 100644 tests/tcg/aarch64/system/feat-xs.c
13
block/block-copy.c | 1 +
14
block/commit.c | 1 +
15
block/crypto.c | 1 +
16
block/dmg.c | 1 +
17
block/export/fuse.c | 1 +
18
block/file-posix.c | 1 +
19
block/io.c | 1 +
20
block/mirror.c | 1 +
21
block/nvme.c | 1 +
22
block/parallels-ext.c | 1 +
23
block/parallels.c | 1 +
24
block/qcow.c | 1 +
25
block/qcow2-cache.c | 1 +
26
block/qcow2-cluster.c | 1 +
27
block/qcow2-refcount.c | 1 +
28
block/qcow2-snapshot.c | 1 +
29
block/qcow2.c | 1 +
30
block/qed-l2-cache.c | 1 +
31
block/qed-table.c | 1 +
32
block/qed.c | 1 +
33
block/quorum.c | 1 +
34
block/raw-format.c | 1 +
35
block/vdi.c | 1 +
36
block/vhdx-log.c | 1 +
37
block/vhdx.c | 1 +
38
block/vmdk.c | 1 +
39
block/vpc.c | 1 +
40
block/win32-aio.c | 1 +
41
hw/block/dataplane/xen-block.c | 1 +
42
hw/block/fdc.c | 1 +
43
hw/ide/core.c | 1 +
44
hw/ppc/spapr.c | 1 +
45
hw/ppc/spapr_softmmu.c | 1 +
46
hw/scsi/scsi-disk.c | 1 +
47
hw/tpm/tpm_ppi.c | 2 +-
48
nbd/server.c | 1 +
49
net/l2tpv3.c | 2 +-
50
plugins/loader.c | 1 +
51
qemu-img.c | 1 +
52
qemu-io-cmds.c | 1 +
53
qom/object.c | 1 +
54
softmmu/physmem.c | 1 +
55
target/i386/hvf/hvf.c | 1 +
56
target/i386/kvm/kvm.c | 1 +
57
tcg/region.c | 1 +
58
tests/bench/atomic_add-bench.c | 1 +
59
tests/bench/qht-bench.c | 1 +
60
util/atomic64.c | 1 +
61
util/memalign.c | 1 +
62
util/qht.c | 1 +
63
53 files changed, 112 insertions(+), 20 deletions(-)
64
create mode 100644 include/qemu/memalign.h
65
18
66
diff --git a/include/qemu/memalign.h b/include/qemu/memalign.h
19
diff --git a/tests/tcg/aarch64/system/feat-xs.c b/tests/tcg/aarch64/system/feat-xs.c
67
new file mode 100644
20
new file mode 100644
68
index XXXXXXX..XXXXXXX
21
index XXXXXXX..XXXXXXX
69
--- /dev/null
22
--- /dev/null
70
+++ b/include/qemu/memalign.h
23
+++ b/tests/tcg/aarch64/system/feat-xs.c
71
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
72
+/*
25
+/*
73
+ * Allocation and free functions for aligned memory
26
+ * FEAT_XS Test
74
+ *
27
+ *
75
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
28
+ * Copyright (c) 2024 Linaro Ltd
76
+ * See the COPYING file in the top-level directory.
29
+ *
30
+ * SPDX-License-Identifier: GPL-2.0-or-later
77
+ */
31
+ */
78
+
32
+
79
+#ifndef QEMU_MEMALIGN_H
33
+#include <minilib.h>
80
+#define QEMU_MEMALIGN_H
34
+#include <stdint.h>
81
+
35
+
82
+/**
36
+int main(void)
83
+ * qemu_try_memalign: Allocate aligned memory
84
+ * @alignment: required alignment, in bytes
85
+ * @size: size of allocation, in bytes
86
+ *
87
+ * Allocate memory on an aligned boundary (i.e. the returned
88
+ * address will be an exact multiple of @alignment).
89
+ * @alignment must be a power of 2, or the function will assert().
90
+ * On success, returns allocated memory; on failure, returns NULL.
91
+ *
92
+ * The memory allocated through this function must be freed via
93
+ * qemu_vfree() (and not via free()).
94
+ */
95
+void *qemu_try_memalign(size_t alignment, size_t size);
96
+/**
97
+ * qemu_memalign: Allocate aligned memory, without failing
98
+ * @alignment: required alignment, in bytes
99
+ * @size: size of allocation, in bytes
100
+ *
101
+ * Allocate memory in the same way as qemu_try_memalign(), but
102
+ * abort() with an error message if the memory allocation fails.
103
+ *
104
+ * The memory allocated through this function must be freed via
105
+ * qemu_vfree() (and not via free()).
106
+ */
107
+void *qemu_memalign(size_t alignment, size_t size);
108
+/**
109
+ * qemu_vfree: Free memory allocated through qemu_memalign
110
+ * @ptr: memory to free
111
+ *
112
+ * This function must be used to free memory allocated via qemu_memalign()
113
+ * or qemu_try_memalign(). (Using the wrong free function will cause
114
+ * subtle bugs on Windows hosts.)
115
+ */
116
+void qemu_vfree(void *ptr);
117
+/*
118
+ * It's an analog of GLIB's g_autoptr_cleanup_generic_gfree(), used to define
119
+ * g_autofree macro.
120
+ */
121
+static inline void qemu_cleanup_generic_vfree(void *p)
122
+{
37
+{
123
+ void **pp = (void **)p;
38
+ uint64_t isar1;
124
+ qemu_vfree(*pp);
39
+
40
+ asm volatile ("mrs %0, id_aa64isar1_el1" : "=r"(isar1));
41
+ if (((isar1 >> 56) & 0xf) < 1) {
42
+ ml_printf("FEAT_XS not supported by CPU");
43
+ return 1;
44
+ }
45
+ /* VMALLE1NXS */
46
+ asm volatile (".inst 0xd508971f");
47
+ /* VMALLE1OSNXS */
48
+ asm volatile (".inst 0xd508911f");
49
+
50
+ return 0;
125
+}
51
+}
126
+
127
+/*
128
+ * Analog of g_autofree, but qemu_vfree is called on cleanup instead of g_free.
129
+ */
130
+#define QEMU_AUTO_VFREE __attribute__((cleanup(qemu_cleanup_generic_vfree)))
131
+
132
+#endif
133
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
134
index XXXXXXX..XXXXXXX 100644
135
--- a/include/qemu/osdep.h
136
+++ b/include/qemu/osdep.h
137
@@ -XXX,XX +XXX,XX @@ extern "C" {
138
#endif
139
140
int qemu_daemon(int nochdir, int noclose);
141
-void *qemu_try_memalign(size_t alignment, size_t size);
142
-void *qemu_memalign(size_t alignment, size_t size);
143
void *qemu_anon_ram_alloc(size_t size, uint64_t *align, bool shared,
144
bool noreserve);
145
-void qemu_vfree(void *ptr);
146
void qemu_anon_ram_free(void *ptr, size_t size);
147
148
-/*
149
- * It's an analog of GLIB's g_autoptr_cleanup_generic_gfree(), used to define
150
- * g_autofree macro.
151
- */
152
-static inline void qemu_cleanup_generic_vfree(void *p)
153
-{
154
- void **pp = (void **)p;
155
- qemu_vfree(*pp);
156
-}
157
-
158
-/*
159
- * Analog of g_autofree, but qemu_vfree is called on cleanup instead of g_free.
160
- */
161
-#define QEMU_AUTO_VFREE __attribute__((cleanup(qemu_cleanup_generic_vfree)))
162
-
163
#ifdef _WIN32
164
#define HAVE_CHARDEV_SERIAL 1
165
#elif defined(__linux__) || defined(__sun__) || defined(__FreeBSD__) \
166
diff --git a/block/blkverify.c b/block/blkverify.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/block/blkverify.c
169
+++ b/block/blkverify.c
170
@@ -XXX,XX +XXX,XX @@
171
#include "qemu/cutils.h"
172
#include "qemu/module.h"
173
#include "qemu/option.h"
174
+#include "qemu/memalign.h"
175
176
typedef struct {
177
BdrvChild *test_file;
178
diff --git a/block/block-copy.c b/block/block-copy.c
179
index XXXXXXX..XXXXXXX 100644
180
--- a/block/block-copy.c
181
+++ b/block/block-copy.c
182
@@ -XXX,XX +XXX,XX @@
183
#include "qemu/coroutine.h"
184
#include "block/aio_task.h"
185
#include "qemu/error-report.h"
186
+#include "qemu/memalign.h"
187
188
#define BLOCK_COPY_MAX_COPY_RANGE (16 * MiB)
189
#define BLOCK_COPY_MAX_BUFFER (1 * MiB)
190
diff --git a/block/commit.c b/block/commit.c
191
index XXXXXXX..XXXXXXX 100644
192
--- a/block/commit.c
193
+++ b/block/commit.c
194
@@ -XXX,XX +XXX,XX @@
195
#include "qapi/error.h"
196
#include "qapi/qmp/qerror.h"
197
#include "qemu/ratelimit.h"
198
+#include "qemu/memalign.h"
199
#include "sysemu/block-backend.h"
200
201
enum {
202
diff --git a/block/crypto.c b/block/crypto.c
203
index XXXXXXX..XXXXXXX 100644
204
--- a/block/crypto.c
205
+++ b/block/crypto.c
206
@@ -XXX,XX +XXX,XX @@
207
#include "qemu/module.h"
208
#include "qemu/option.h"
209
#include "qemu/cutils.h"
210
+#include "qemu/memalign.h"
211
#include "crypto.h"
212
213
typedef struct BlockCrypto BlockCrypto;
214
diff --git a/block/dmg.c b/block/dmg.c
215
index XXXXXXX..XXXXXXX 100644
216
--- a/block/dmg.c
217
+++ b/block/dmg.c
218
@@ -XXX,XX +XXX,XX @@
219
#include "qemu/bswap.h"
220
#include "qemu/error-report.h"
221
#include "qemu/module.h"
222
+#include "qemu/memalign.h"
223
#include "dmg.h"
224
225
int (*dmg_uncompress_bz2)(char *next_in, unsigned int avail_in,
226
diff --git a/block/export/fuse.c b/block/export/fuse.c
227
index XXXXXXX..XXXXXXX 100644
228
--- a/block/export/fuse.c
229
+++ b/block/export/fuse.c
230
@@ -XXX,XX +XXX,XX @@
231
#define FUSE_USE_VERSION 31
232
233
#include "qemu/osdep.h"
234
+#include "qemu/memalign.h"
235
#include "block/aio.h"
236
#include "block/block.h"
237
#include "block/export.h"
238
diff --git a/block/file-posix.c b/block/file-posix.c
239
index XXXXXXX..XXXXXXX 100644
240
--- a/block/file-posix.c
241
+++ b/block/file-posix.c
242
@@ -XXX,XX +XXX,XX @@
243
#include "qemu/module.h"
244
#include "qemu/option.h"
245
#include "qemu/units.h"
246
+#include "qemu/memalign.h"
247
#include "trace.h"
248
#include "block/thread-pool.h"
249
#include "qemu/iov.h"
250
diff --git a/block/io.c b/block/io.c
251
index XXXXXXX..XXXXXXX 100644
252
--- a/block/io.c
253
+++ b/block/io.c
254
@@ -XXX,XX +XXX,XX @@
255
#include "block/coroutines.h"
256
#include "block/write-threshold.h"
257
#include "qemu/cutils.h"
258
+#include "qemu/memalign.h"
259
#include "qapi/error.h"
260
#include "qemu/error-report.h"
261
#include "qemu/main-loop.h"
262
diff --git a/block/mirror.c b/block/mirror.c
263
index XXXXXXX..XXXXXXX 100644
264
--- a/block/mirror.c
265
+++ b/block/mirror.c
266
@@ -XXX,XX +XXX,XX @@
267
#include "qapi/qmp/qerror.h"
268
#include "qemu/ratelimit.h"
269
#include "qemu/bitmap.h"
270
+#include "qemu/memalign.h"
271
272
#define MAX_IN_FLIGHT 16
273
#define MAX_IO_BYTES (1 << 20) /* 1 Mb */
274
diff --git a/block/nvme.c b/block/nvme.c
275
index XXXXXXX..XXXXXXX 100644
276
--- a/block/nvme.c
277
+++ b/block/nvme.c
278
@@ -XXX,XX +XXX,XX @@
279
#include "qemu/module.h"
280
#include "qemu/cutils.h"
281
#include "qemu/option.h"
282
+#include "qemu/memalign.h"
283
#include "qemu/vfio-helpers.h"
284
#include "block/block_int.h"
285
#include "sysemu/replay.h"
286
diff --git a/block/parallels-ext.c b/block/parallels-ext.c
287
index XXXXXXX..XXXXXXX 100644
288
--- a/block/parallels-ext.c
289
+++ b/block/parallels-ext.c
290
@@ -XXX,XX +XXX,XX @@
291
#include "parallels.h"
292
#include "crypto/hash.h"
293
#include "qemu/uuid.h"
294
+#include "qemu/memalign.h"
295
296
#define PARALLELS_FORMAT_EXTENSION_MAGIC 0xAB234CEF23DCEA87ULL
297
298
diff --git a/block/parallels.c b/block/parallels.c
299
index XXXXXXX..XXXXXXX 100644
300
--- a/block/parallels.c
301
+++ b/block/parallels.c
302
@@ -XXX,XX +XXX,XX @@
303
#include "qapi/qapi-visit-block-core.h"
304
#include "qemu/bswap.h"
305
#include "qemu/bitmap.h"
306
+#include "qemu/memalign.h"
307
#include "migration/blocker.h"
308
#include "parallels.h"
309
310
diff --git a/block/qcow.c b/block/qcow.c
311
index XXXXXXX..XXXXXXX 100644
312
--- a/block/qcow.c
313
+++ b/block/qcow.c
314
@@ -XXX,XX +XXX,XX @@
315
#include "qemu/option.h"
316
#include "qemu/bswap.h"
317
#include "qemu/cutils.h"
318
+#include "qemu/memalign.h"
319
#include <zlib.h>
320
#include "qapi/qmp/qdict.h"
321
#include "qapi/qmp/qstring.h"
322
diff --git a/block/qcow2-cache.c b/block/qcow2-cache.c
323
index XXXXXXX..XXXXXXX 100644
324
--- a/block/qcow2-cache.c
325
+++ b/block/qcow2-cache.c
326
@@ -XXX,XX +XXX,XX @@
327
*/
328
329
#include "qemu/osdep.h"
330
+#include "qemu/memalign.h"
331
#include "qcow2.h"
332
#include "trace.h"
333
334
diff --git a/block/qcow2-cluster.c b/block/qcow2-cluster.c
335
index XXXXXXX..XXXXXXX 100644
336
--- a/block/qcow2-cluster.c
337
+++ b/block/qcow2-cluster.c
338
@@ -XXX,XX +XXX,XX @@
339
#include "qapi/error.h"
340
#include "qcow2.h"
341
#include "qemu/bswap.h"
342
+#include "qemu/memalign.h"
343
#include "trace.h"
344
345
int qcow2_shrink_l1_table(BlockDriverState *bs, uint64_t exact_size)
346
diff --git a/block/qcow2-refcount.c b/block/qcow2-refcount.c
347
index XXXXXXX..XXXXXXX 100644
348
--- a/block/qcow2-refcount.c
349
+++ b/block/qcow2-refcount.c
350
@@ -XXX,XX +XXX,XX @@
351
#include "qemu/range.h"
352
#include "qemu/bswap.h"
353
#include "qemu/cutils.h"
354
+#include "qemu/memalign.h"
355
#include "trace.h"
356
357
static int64_t alloc_clusters_noref(BlockDriverState *bs, uint64_t size,
358
diff --git a/block/qcow2-snapshot.c b/block/qcow2-snapshot.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/block/qcow2-snapshot.c
361
+++ b/block/qcow2-snapshot.c
362
@@ -XXX,XX +XXX,XX @@
363
#include "qemu/bswap.h"
364
#include "qemu/error-report.h"
365
#include "qemu/cutils.h"
366
+#include "qemu/memalign.h"
367
368
static void qcow2_free_single_snapshot(BlockDriverState *bs, int i)
369
{
370
diff --git a/block/qcow2.c b/block/qcow2.c
371
index XXXXXXX..XXXXXXX 100644
372
--- a/block/qcow2.c
373
+++ b/block/qcow2.c
374
@@ -XXX,XX +XXX,XX @@
375
#include "qemu/option_int.h"
376
#include "qemu/cutils.h"
377
#include "qemu/bswap.h"
378
+#include "qemu/memalign.h"
379
#include "qapi/qobject-input-visitor.h"
380
#include "qapi/qapi-visit-block-core.h"
381
#include "crypto.h"
382
diff --git a/block/qed-l2-cache.c b/block/qed-l2-cache.c
383
index XXXXXXX..XXXXXXX 100644
384
--- a/block/qed-l2-cache.c
385
+++ b/block/qed-l2-cache.c
386
@@ -XXX,XX +XXX,XX @@
387
*/
388
389
#include "qemu/osdep.h"
390
+#include "qemu/memalign.h"
391
#include "trace.h"
392
#include "qed.h"
393
394
diff --git a/block/qed-table.c b/block/qed-table.c
395
index XXXXXXX..XXXXXXX 100644
396
--- a/block/qed-table.c
397
+++ b/block/qed-table.c
398
@@ -XXX,XX +XXX,XX @@
399
#include "qemu/sockets.h" /* for EINPROGRESS on Windows */
400
#include "qed.h"
401
#include "qemu/bswap.h"
402
+#include "qemu/memalign.h"
403
404
/* Called with table_lock held. */
405
static int coroutine_fn qed_read_table(BDRVQEDState *s, uint64_t offset,
406
diff --git a/block/qed.c b/block/qed.c
407
index XXXXXXX..XXXXXXX 100644
408
--- a/block/qed.c
409
+++ b/block/qed.c
410
@@ -XXX,XX +XXX,XX @@
411
#include "qemu/main-loop.h"
412
#include "qemu/module.h"
413
#include "qemu/option.h"
414
+#include "qemu/memalign.h"
415
#include "trace.h"
416
#include "qed.h"
417
#include "sysemu/block-backend.h"
418
diff --git a/block/quorum.c b/block/quorum.c
419
index XXXXXXX..XXXXXXX 100644
420
--- a/block/quorum.c
421
+++ b/block/quorum.c
422
@@ -XXX,XX +XXX,XX @@
423
#include "qemu/cutils.h"
424
#include "qemu/module.h"
425
#include "qemu/option.h"
426
+#include "qemu/memalign.h"
427
#include "block/block_int.h"
428
#include "block/coroutines.h"
429
#include "block/qdict.h"
430
diff --git a/block/raw-format.c b/block/raw-format.c
431
index XXXXXXX..XXXXXXX 100644
432
--- a/block/raw-format.c
433
+++ b/block/raw-format.c
434
@@ -XXX,XX +XXX,XX @@
435
#include "qapi/error.h"
436
#include "qemu/module.h"
437
#include "qemu/option.h"
438
+#include "qemu/memalign.h"
439
440
typedef struct BDRVRawState {
441
uint64_t offset;
442
diff --git a/block/vdi.c b/block/vdi.c
443
index XXXXXXX..XXXXXXX 100644
444
--- a/block/vdi.c
445
+++ b/block/vdi.c
446
@@ -XXX,XX +XXX,XX @@
447
#include "qemu/coroutine.h"
448
#include "qemu/cutils.h"
449
#include "qemu/uuid.h"
450
+#include "qemu/memalign.h"
451
452
/* Code configuration options. */
453
454
diff --git a/block/vhdx-log.c b/block/vhdx-log.c
455
index XXXXXXX..XXXXXXX 100644
456
--- a/block/vhdx-log.c
457
+++ b/block/vhdx-log.c
458
@@ -XXX,XX +XXX,XX @@
459
#include "block/block_int.h"
460
#include "qemu/error-report.h"
461
#include "qemu/bswap.h"
462
+#include "qemu/memalign.h"
463
#include "vhdx.h"
464
465
466
diff --git a/block/vhdx.c b/block/vhdx.c
467
index XXXXXXX..XXXXXXX 100644
468
--- a/block/vhdx.c
469
+++ b/block/vhdx.c
470
@@ -XXX,XX +XXX,XX @@
471
#include "qemu/crc32c.h"
472
#include "qemu/bswap.h"
473
#include "qemu/error-report.h"
474
+#include "qemu/memalign.h"
475
#include "vhdx.h"
476
#include "migration/blocker.h"
477
#include "qemu/uuid.h"
478
diff --git a/block/vmdk.c b/block/vmdk.c
479
index XXXXXXX..XXXXXXX 100644
480
--- a/block/vmdk.c
481
+++ b/block/vmdk.c
482
@@ -XXX,XX +XXX,XX @@
483
#include "qemu/module.h"
484
#include "qemu/option.h"
485
#include "qemu/bswap.h"
486
+#include "qemu/memalign.h"
487
#include "migration/blocker.h"
488
#include "qemu/cutils.h"
489
#include <zlib.h>
490
diff --git a/block/vpc.c b/block/vpc.c
491
index XXXXXXX..XXXXXXX 100644
492
--- a/block/vpc.c
493
+++ b/block/vpc.c
494
@@ -XXX,XX +XXX,XX @@
495
#include "migration/blocker.h"
496
#include "qemu/bswap.h"
497
#include "qemu/uuid.h"
498
+#include "qemu/memalign.h"
499
#include "qapi/qmp/qdict.h"
500
#include "qapi/qobject-input-visitor.h"
501
#include "qapi/qapi-visit-block-core.h"
502
diff --git a/block/win32-aio.c b/block/win32-aio.c
503
index XXXXXXX..XXXXXXX 100644
504
--- a/block/win32-aio.c
505
+++ b/block/win32-aio.c
506
@@ -XXX,XX +XXX,XX @@
507
#include "block/raw-aio.h"
508
#include "qemu/event_notifier.h"
509
#include "qemu/iov.h"
510
+#include "qemu/memalign.h"
511
#include <windows.h>
512
#include <winioctl.h>
513
514
diff --git a/hw/block/dataplane/xen-block.c b/hw/block/dataplane/xen-block.c
515
index XXXXXXX..XXXXXXX 100644
516
--- a/hw/block/dataplane/xen-block.c
517
+++ b/hw/block/dataplane/xen-block.c
518
@@ -XXX,XX +XXX,XX @@
519
#include "qemu/osdep.h"
520
#include "qemu/error-report.h"
521
#include "qemu/main-loop.h"
522
+#include "qemu/memalign.h"
523
#include "qapi/error.h"
524
#include "hw/xen/xen_common.h"
525
#include "hw/block/xen_blkif.h"
526
diff --git a/hw/block/fdc.c b/hw/block/fdc.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/hw/block/fdc.c
529
+++ b/hw/block/fdc.c
530
@@ -XXX,XX +XXX,XX @@
531
#include "qapi/error.h"
532
#include "qemu/error-report.h"
533
#include "qemu/timer.h"
534
+#include "qemu/memalign.h"
535
#include "hw/irq.h"
536
#include "hw/isa/isa.h"
537
#include "hw/qdev-properties.h"
538
diff --git a/hw/ide/core.c b/hw/ide/core.c
539
index XXXXXXX..XXXXXXX 100644
540
--- a/hw/ide/core.c
541
+++ b/hw/ide/core.c
542
@@ -XXX,XX +XXX,XX @@
543
#include "qemu/main-loop.h"
544
#include "qemu/timer.h"
545
#include "qemu/hw-version.h"
546
+#include "qemu/memalign.h"
547
#include "sysemu/sysemu.h"
548
#include "sysemu/blockdev.h"
549
#include "sysemu/dma.h"
550
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
551
index XXXXXXX..XXXXXXX 100644
552
--- a/hw/ppc/spapr.c
553
+++ b/hw/ppc/spapr.c
554
@@ -XXX,XX +XXX,XX @@
555
#include "qemu/osdep.h"
556
#include "qemu-common.h"
557
#include "qemu/datadir.h"
558
+#include "qemu/memalign.h"
559
#include "qapi/error.h"
560
#include "qapi/qapi-events-machine.h"
561
#include "qapi/qapi-events-qdev.h"
562
diff --git a/hw/ppc/spapr_softmmu.c b/hw/ppc/spapr_softmmu.c
563
index XXXXXXX..XXXXXXX 100644
564
--- a/hw/ppc/spapr_softmmu.c
565
+++ b/hw/ppc/spapr_softmmu.c
566
@@ -XXX,XX +XXX,XX @@
567
#include "qemu/osdep.h"
568
#include "qemu/cutils.h"
569
+#include "qemu/memalign.h"
570
#include "cpu.h"
571
#include "helper_regs.h"
572
#include "hw/ppc/spapr.h"
573
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
574
index XXXXXXX..XXXXXXX 100644
575
--- a/hw/scsi/scsi-disk.c
576
+++ b/hw/scsi/scsi-disk.c
577
@@ -XXX,XX +XXX,XX @@
578
#include "qemu/main-loop.h"
579
#include "qemu/module.h"
580
#include "qemu/hw-version.h"
581
+#include "qemu/memalign.h"
582
#include "hw/scsi/scsi.h"
583
#include "migration/qemu-file-types.h"
584
#include "migration/vmstate.h"
585
diff --git a/hw/tpm/tpm_ppi.c b/hw/tpm/tpm_ppi.c
586
index XXXXXXX..XXXXXXX 100644
587
--- a/hw/tpm/tpm_ppi.c
588
+++ b/hw/tpm/tpm_ppi.c
589
@@ -XXX,XX +XXX,XX @@
590
*/
591
592
#include "qemu/osdep.h"
593
-
594
+#include "qemu/memalign.h"
595
#include "qapi/error.h"
596
#include "sysemu/memory_mapping.h"
597
#include "migration/vmstate.h"
598
diff --git a/nbd/server.c b/nbd/server.c
599
index XXXXXXX..XXXXXXX 100644
600
--- a/nbd/server.c
601
+++ b/nbd/server.c
602
@@ -XXX,XX +XXX,XX @@
603
#include "trace.h"
604
#include "nbd-internal.h"
605
#include "qemu/units.h"
606
+#include "qemu/memalign.h"
607
608
#define NBD_META_ID_BASE_ALLOCATION 0
609
#define NBD_META_ID_ALLOCATION_DEPTH 1
610
diff --git a/net/l2tpv3.c b/net/l2tpv3.c
611
index XXXXXXX..XXXXXXX 100644
612
--- a/net/l2tpv3.c
613
+++ b/net/l2tpv3.c
614
@@ -XXX,XX +XXX,XX @@
615
#include "qemu/sockets.h"
616
#include "qemu/iov.h"
617
#include "qemu/main-loop.h"
618
-
619
+#include "qemu/memalign.h"
620
621
/* The buffer size needs to be investigated for optimum numbers and
622
* optimum means of paging in on different systems. This size is
623
diff --git a/plugins/loader.c b/plugins/loader.c
624
index XXXXXXX..XXXXXXX 100644
625
--- a/plugins/loader.c
626
+++ b/plugins/loader.c
627
@@ -XXX,XX +XXX,XX @@
628
#include "qemu/cacheinfo.h"
629
#include "qemu/xxhash.h"
630
#include "qemu/plugin.h"
631
+#include "qemu/memalign.h"
632
#include "hw/core/cpu.h"
633
#include "exec/exec-all.h"
634
#ifndef CONFIG_USER_ONLY
635
diff --git a/qemu-img.c b/qemu-img.c
636
index XXXXXXX..XXXXXXX 100644
637
--- a/qemu-img.c
638
+++ b/qemu-img.c
639
@@ -XXX,XX +XXX,XX @@
640
#include "qemu/module.h"
641
#include "qemu/sockets.h"
642
#include "qemu/units.h"
643
+#include "qemu/memalign.h"
644
#include "qom/object_interfaces.h"
645
#include "sysemu/block-backend.h"
646
#include "block/block_int.h"
647
diff --git a/qemu-io-cmds.c b/qemu-io-cmds.c
648
index XXXXXXX..XXXXXXX 100644
649
--- a/qemu-io-cmds.c
650
+++ b/qemu-io-cmds.c
651
@@ -XXX,XX +XXX,XX @@
652
#include "qemu/option.h"
653
#include "qemu/timer.h"
654
#include "qemu/cutils.h"
655
+#include "qemu/memalign.h"
656
657
#define CMD_NOFILE_OK 0x01
658
659
diff --git a/qom/object.c b/qom/object.c
660
index XXXXXXX..XXXXXXX 100644
661
--- a/qom/object.c
662
+++ b/qom/object.c
663
@@ -XXX,XX +XXX,XX @@
664
#include "qom/object.h"
665
#include "qom/object_interfaces.h"
666
#include "qemu/cutils.h"
667
+#include "qemu/memalign.h"
668
#include "qapi/visitor.h"
669
#include "qapi/string-input-visitor.h"
670
#include "qapi/string-output-visitor.h"
671
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
672
index XXXXXXX..XXXXXXX 100644
673
--- a/softmmu/physmem.c
674
+++ b/softmmu/physmem.c
675
@@ -XXX,XX +XXX,XX @@
676
#include "qemu/config-file.h"
677
#include "qemu/error-report.h"
678
#include "qemu/qemu-print.h"
679
+#include "qemu/memalign.h"
680
#include "exec/memory.h"
681
#include "exec/ioport.h"
682
#include "sysemu/dma.h"
683
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
684
index XXXXXXX..XXXXXXX 100644
685
--- a/target/i386/hvf/hvf.c
686
+++ b/target/i386/hvf/hvf.c
687
@@ -XXX,XX +XXX,XX @@
688
#include "qemu/osdep.h"
689
#include "qemu-common.h"
690
#include "qemu/error-report.h"
691
+#include "qemu/memalign.h"
692
693
#include "sysemu/hvf.h"
694
#include "sysemu/hvf_int.h"
695
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
696
index XXXXXXX..XXXXXXX 100644
697
--- a/target/i386/kvm/kvm.c
698
+++ b/target/i386/kvm/kvm.c
699
@@ -XXX,XX +XXX,XX @@
700
#include "qemu/main-loop.h"
701
#include "qemu/config-file.h"
702
#include "qemu/error-report.h"
703
+#include "qemu/memalign.h"
704
#include "hw/i386/x86.h"
705
#include "hw/i386/apic.h"
706
#include "hw/i386/apic_internal.h"
707
diff --git a/tcg/region.c b/tcg/region.c
708
index XXXXXXX..XXXXXXX 100644
709
--- a/tcg/region.c
710
+++ b/tcg/region.c
711
@@ -XXX,XX +XXX,XX @@
712
#include "qemu/units.h"
713
#include "qemu/madvise.h"
714
#include "qemu/mprotect.h"
715
+#include "qemu/memalign.h"
716
#include "qemu/cacheinfo.h"
717
#include "qapi/error.h"
718
#include "exec/exec-all.h"
719
diff --git a/tests/bench/atomic_add-bench.c b/tests/bench/atomic_add-bench.c
720
index XXXXXXX..XXXXXXX 100644
721
--- a/tests/bench/atomic_add-bench.c
722
+++ b/tests/bench/atomic_add-bench.c
723
@@ -XXX,XX +XXX,XX @@
724
#include "qemu/thread.h"
725
#include "qemu/host-utils.h"
726
#include "qemu/processor.h"
727
+#include "qemu/memalign.h"
728
729
struct thread_info {
730
uint64_t r;
731
diff --git a/tests/bench/qht-bench.c b/tests/bench/qht-bench.c
732
index XXXXXXX..XXXXXXX 100644
733
--- a/tests/bench/qht-bench.c
734
+++ b/tests/bench/qht-bench.c
735
@@ -XXX,XX +XXX,XX @@
736
#include "qemu/qht.h"
737
#include "qemu/rcu.h"
738
#include "qemu/xxhash.h"
739
+#include "qemu/memalign.h"
740
741
struct thread_stats {
742
size_t rd;
743
diff --git a/util/atomic64.c b/util/atomic64.c
744
index XXXXXXX..XXXXXXX 100644
745
--- a/util/atomic64.c
746
+++ b/util/atomic64.c
747
@@ -XXX,XX +XXX,XX @@
748
#include "qemu/atomic.h"
749
#include "qemu/thread.h"
750
#include "qemu/cacheinfo.h"
751
+#include "qemu/memalign.h"
752
753
#ifdef CONFIG_ATOMIC64
754
#error This file must only be compiled if !CONFIG_ATOMIC64
755
diff --git a/util/memalign.c b/util/memalign.c
756
index XXXXXXX..XXXXXXX 100644
757
--- a/util/memalign.c
758
+++ b/util/memalign.c
759
@@ -XXX,XX +XXX,XX @@
760
761
#include "qemu/osdep.h"
762
#include "qemu/host-utils.h"
763
+#include "qemu/memalign.h"
764
#include "trace.h"
765
766
void *qemu_try_memalign(size_t alignment, size_t size)
767
diff --git a/util/qht.c b/util/qht.c
768
index XXXXXXX..XXXXXXX 100644
769
--- a/util/qht.c
770
+++ b/util/qht.c
771
@@ -XXX,XX +XXX,XX @@
772
#include "qemu/qht.h"
773
#include "qemu/atomic.h"
774
#include "qemu/rcu.h"
775
+#include "qemu/memalign.h"
776
777
//#define QHT_DEBUG
778
779
--
52
--
780
2.25.1
53
2.34.1
781
782
diff view generated by jsdifflib
[PULL 11/18] hw/intc/arm_gicv3_its: Add trace events for commands
[PULL 18/19] hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
1
When debugging code that's using the ITS, it's helpful to
1
In the GICv3 ITS model, we have a common coding pattern which has a
2
see tracing of the ITS commands that the guest executes. Add
2
local C struct like "DTEntry dte", which is a C representation of an
3
suitable trace events.
3
in-guest-memory data structure, and we call a function such as
4
get_dte() to read guest memory and fill in the C struct. These
5
functions to read in the struct sometimes have cases where they will
6
leave early and not fill in the whole struct (for instance get_dte()
7
will set "dte->valid = false" and nothing else for the case where it
8
is passed an entry_addr implying that there is no L2 table entry for
9
the DTE). This then causes potential use of uninitialized memory
10
later, for instance when we call a trace event which prints all the
11
fields of the struct. Sufficiently advanced compilers may produce
12
-Wmaybe-uninitialized warnings about this, especially if LTO is
13
enabled.
4
14
15
Rather than trying to carefully separate out these trace events into
16
"only the 'valid' field is initialized" and "all fields can be
17
printed", zero-init all the structs when we define them. None of
18
these structs are large (the biggest is 24 bytes) and having
19
consistent behaviour is less likely to be buggy.
20
21
Cc: qemu-stable@nongnu.org
22
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2718
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220303202341.2232284-2-peter.maydell@linaro.org
25
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
26
Message-id: 20241213182337.3343068-1-peter.maydell@linaro.org
8
---
27
---
9
hw/intc/arm_gicv3_its.c | 28 ++++++++++++++++++++++++++--
28
hw/intc/arm_gicv3_its.c | 44 ++++++++++++++++++++---------------------
10
hw/intc/trace-events | 12 ++++++++++++
29
1 file changed, 22 insertions(+), 22 deletions(-)
11
2 files changed, 38 insertions(+), 2 deletions(-)
12
30
13
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
31
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
14
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/arm_gicv3_its.c
33
--- a/hw/intc/arm_gicv3_its.c
16
+++ b/hw/intc/arm_gicv3_its.c
34
+++ b/hw/intc/arm_gicv3_its.c
17
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd(GICv3ITSState *s, const uint64_t *cmdpkt,
35
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult lookup_vte(GICv3ITSState *s, const char *who,
36
static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite,
37
int irqlevel)
38
{
39
- CTEntry cte;
40
+ CTEntry cte = {};
41
ItsCmdResult cmdres;
42
43
cmdres = lookup_cte(s, __func__, ite->icid, &cte);
44
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite,
45
static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite,
46
int irqlevel)
47
{
48
- VTEntry vte;
49
+ VTEntry vte = {};
50
ItsCmdResult cmdres;
51
52
cmdres = lookup_vte(s, __func__, ite->vpeid, &vte);
53
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite,
54
static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid,
55
uint32_t eventid, ItsCmdType cmd)
56
{
57
- DTEntry dte;
58
- ITEntry ite;
59
+ DTEntry dte = {};
60
+ ITEntry ite = {};
61
ItsCmdResult cmdres;
62
int irqlevel;
63
64
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt,
65
uint32_t pIntid = 0;
66
uint64_t num_eventids;
67
uint16_t icid = 0;
68
- DTEntry dte;
69
- ITEntry ite;
70
+ DTEntry dte = {};
71
+ ITEntry ite = {};
18
72
19
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
73
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
20
eventid = cmdpkt[1] & EVENTID_MASK;
74
eventid = cmdpkt[1] & EVENTID_MASK;
21
+ switch (cmd) {
75
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vmapti(GICv3ITSState *s, const uint64_t *cmdpkt,
22
+ case INTERRUPT:
76
{
23
+ trace_gicv3_its_cmd_int(devid, eventid);
77
uint32_t devid, eventid, vintid, doorbell, vpeid;
24
+ break;
78
uint32_t num_eventids;
25
+ case CLEAR:
79
- DTEntry dte;
26
+ trace_gicv3_its_cmd_clear(devid, eventid);
80
- ITEntry ite;
27
+ break;
81
+ DTEntry dte = {};
28
+ case DISCARD:
82
+ ITEntry ite = {};
29
+ trace_gicv3_its_cmd_discard(devid, eventid);
83
30
+ break;
84
if (!its_feature_virtual(s)) {
31
+ default:
85
return CMD_CONTINUE;
32
+ g_assert_not_reached();
86
@@ -XXX,XX +XXX,XX @@ static bool update_cte(GICv3ITSState *s, uint16_t icid, const CTEntry *cte)
33
+ }
87
static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt)
34
return do_process_its_cmd(s, devid, eventid, cmd);
88
{
35
}
89
uint16_t icid;
36
90
- CTEntry cte;
37
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt,
91
+ CTEntry cte = {};
92
93
icid = cmdpkt[2] & ICID_MASK;
94
cte.valid = cmdpkt[2] & CMD_FIELD_VALID_MASK;
95
@@ -XXX,XX +XXX,XX @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, const DTEntry *dte)
96
static ItsCmdResult process_mapd(GICv3ITSState *s, const uint64_t *cmdpkt)
97
{
98
uint32_t devid;
99
- DTEntry dte;
100
+ DTEntry dte = {};
38
101
39
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
102
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
40
eventid = cmdpkt[1] & EVENTID_MASK;
103
dte.size = cmdpkt[1] & SIZE_MASK;
41
+ icid = cmdpkt[2] & ICID_MASK;
42
43
if (ignore_pInt) {
44
pIntid = eventid;
45
+ trace_gicv3_its_cmd_mapi(devid, eventid, icid);
46
} else {
47
pIntid = (cmdpkt[1] & pINTID_MASK) >> pINTID_SHIFT;
48
+ trace_gicv3_its_cmd_mapti(devid, eventid, icid, pIntid);
49
}
50
51
- icid = cmdpkt[2] & ICID_MASK;
52
-
53
if (devid >= s->dt.num_entries) {
54
qemu_log_mask(LOG_GUEST_ERROR,
55
"%s: invalid command attributes: devid %d>=%d",
56
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt)
57
} else {
58
cte.rdbase = 0;
59
}
60
+ trace_gicv3_its_cmd_mapc(icid, cte.rdbase, cte.valid);
61
62
if (icid >= s->ct.num_entries) {
63
qemu_log_mask(LOG_GUEST_ERROR, "ITS MAPC: invalid ICID 0x%d", icid);
64
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapd(GICv3ITSState *s, const uint64_t *cmdpkt)
65
dte.ittaddr = (cmdpkt[2] & ITTADDR_MASK) >> ITTADDR_SHIFT;
66
dte.valid = cmdpkt[2] & CMD_FIELD_VALID_MASK;
67
68
+ trace_gicv3_its_cmd_mapd(devid, dte.size, dte.ittaddr, dte.valid);
69
+
70
if (devid >= s->dt.num_entries) {
71
qemu_log_mask(LOG_GUEST_ERROR,
72
"ITS MAPD: invalid device ID field 0x%x >= 0x%x\n",
73
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_movall(GICv3ITSState *s, const uint64_t *cmdpkt)
74
rd1 = FIELD_EX64(cmdpkt[2], MOVALL_2, RDBASE1);
75
rd2 = FIELD_EX64(cmdpkt[3], MOVALL_3, RDBASE2);
76
77
+ trace_gicv3_its_cmd_movall(rd1, rd2);
78
+
79
if (rd1 >= s->gicv3->num_cpu) {
80
qemu_log_mask(LOG_GUEST_ERROR,
81
"%s: RDBASE1 %" PRId64
82
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt)
104
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt)
83
eventid = FIELD_EX64(cmdpkt[1], MOVI_1, EVENTID);
105
{
84
new_icid = FIELD_EX64(cmdpkt[2], MOVI_2, ICID);
106
uint32_t devid, eventid;
85
107
uint16_t new_icid;
86
+ trace_gicv3_its_cmd_movi(devid, eventid, new_icid);
108
- DTEntry dte;
87
+
109
- CTEntry old_cte, new_cte;
88
if (devid >= s->dt.num_entries) {
110
- ITEntry old_ite;
89
qemu_log_mask(LOG_GUEST_ERROR,
111
+ DTEntry dte = {};
90
"%s: invalid command attributes: devid %d>=%d",
112
+ CTEntry old_cte = {}, new_cte = {};
91
@@ -XXX,XX +XXX,XX @@ static void process_cmdq(GICv3ITSState *s)
113
+ ITEntry old_ite = {};
92
* is already consistent by the time SYNC command is executed.
114
ItsCmdResult cmdres;
93
* Hence no further processing is required for SYNC command.
115
94
*/
116
devid = FIELD_EX64(cmdpkt[0], MOVI_0, DEVICEID);
95
+ trace_gicv3_its_cmd_sync();
117
@@ -XXX,XX +XXX,XX @@ static bool update_vte(GICv3ITSState *s, uint32_t vpeid, const VTEntry *vte)
96
break;
118
97
case GITS_CMD_MAPD:
119
static ItsCmdResult process_vmapp(GICv3ITSState *s, const uint64_t *cmdpkt)
98
result = process_mapd(s, cmdpkt);
120
{
99
@@ -XXX,XX +XXX,XX @@ static void process_cmdq(GICv3ITSState *s)
121
- VTEntry vte;
100
* need to trigger lpi priority re-calculation to be in
122
+ VTEntry vte = {};
101
* sync with LPI config table or pending table changes.
123
uint32_t vpeid;
102
*/
124
103
+ trace_gicv3_its_cmd_inv();
125
if (!its_feature_virtual(s)) {
104
for (i = 0; i < s->gicv3->num_cpu; i++) {
126
@@ -XXX,XX +XXX,XX @@ static void vmovp_callback(gpointer data, gpointer opaque)
105
gicv3_redist_update_lpi(&s->gicv3->cpu[i]);
127
*/
106
}
128
GICv3ITSState *s = data;
107
@@ -XXX,XX +XXX,XX @@ static void process_cmdq(GICv3ITSState *s)
129
VmovpCallbackData *cbdata = opaque;
108
result = process_movall(s, cmdpkt);
130
- VTEntry vte;
109
break;
131
+ VTEntry vte = {};
110
default:
132
ItsCmdResult cmdres;
111
+ trace_gicv3_its_cmd_unknown(cmd);
133
112
break;
134
cmdres = lookup_vte(s, __func__, cbdata->vpeid, &vte);
113
}
135
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vmovi(GICv3ITSState *s, const uint64_t *cmdpkt)
114
if (result == CMD_CONTINUE) {
136
{
115
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
137
uint32_t devid, eventid, vpeid, doorbell;
116
index XXXXXXX..XXXXXXX 100644
138
bool doorbell_valid;
117
--- a/hw/intc/trace-events
139
- DTEntry dte;
118
+++ b/hw/intc/trace-events
140
- ITEntry ite;
119
@@ -XXX,XX +XXX,XX @@ gicv3_its_write(uint64_t offset, uint64_t data, unsigned size) "GICv3 ITS write:
141
- VTEntry old_vte, new_vte;
120
gicv3_its_badwrite(uint64_t offset, uint64_t data, unsigned size) "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u: error"
142
+ DTEntry dte = {};
121
gicv3_its_translation_write(uint64_t offset, uint64_t data, unsigned size, uint32_t requester_id) "GICv3 ITS TRANSLATER write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u requester_id 0x%x"
143
+ ITEntry ite = {};
122
gicv3_its_process_command(uint32_t rd_offset, uint8_t cmd) "GICv3 ITS: processing command at offset 0x%x: 0x%x"
144
+ VTEntry old_vte = {}, new_vte = {};
123
+gicv3_its_cmd_int(uint32_t devid, uint32_t eventid) "GICv3 ITS: command INT DeviceID 0x%x EventID 0x%x"
145
ItsCmdResult cmdres;
124
+gicv3_its_cmd_clear(uint32_t devid, uint32_t eventid) "GICv3 ITS: command CLEAR DeviceID 0x%x EventID 0x%x"
146
125
+gicv3_its_cmd_discard(uint32_t devid, uint32_t eventid) "GICv3 ITS: command DISCARD DeviceID 0x%x EventID 0x%x"
147
if (!its_feature_virtual(s)) {
126
+gicv3_its_cmd_sync(void) "GICv3 ITS: command SYNC"
148
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vinvall(GICv3ITSState *s, const uint64_t *cmdpkt)
127
+gicv3_its_cmd_mapd(uint32_t devid, uint32_t size, uint64_t ittaddr, int valid) "GICv3 ITS: command MAPD DeviceID 0x%x Size 0x%x ITT_addr 0x%" PRIx64 " V %d"
149
static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt)
128
+gicv3_its_cmd_mapc(uint32_t icid, uint64_t rdbase, int valid) "GICv3 ITS: command MAPC ICID 0x%x RDbase 0x%" PRIx64 " V %d"
150
{
129
+gicv3_its_cmd_mapi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MAPI DeviceID 0x%x EventID 0x%x ICID 0x%x"
151
uint32_t devid, eventid;
130
+gicv3_its_cmd_mapti(uint32_t devid, uint32_t eventid, uint32_t icid, uint32_t intid) "GICv3 ITS: command MAPTI DeviceID 0x%x EventID 0x%x ICID 0x%x pINTID 0x%x"
152
- ITEntry ite;
131
+gicv3_its_cmd_inv(void) "GICv3 ITS: command INV or INVALL"
153
- DTEntry dte;
132
+gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64
154
- CTEntry cte;
133
+gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x"
155
- VTEntry vte;
134
+gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x"
156
+ ITEntry ite = {};
135
157
+ DTEntry dte = {};
136
# armv7m_nvic.c
158
+ CTEntry cte = {};
137
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
159
+ VTEntry vte = {};
160
ItsCmdResult cmdres;
161
162
devid = FIELD_EX64(cmdpkt[0], INV_0, DEVICEID);
138
--
163
--
139
2.25.1
164
2.34.1
165
166
diff view generated by jsdifflib
[PULL 16/18] ui/cocoa: Use the standard about panel
[PULL 19/19] tests/functional: update sbsa-ref firmware used in test
1
From: Akihiko Odaki <akihiko.odaki@gmail.com>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
This provides standard look and feel for the about panel and reduces
3
Update the URLs for the binaries we use for the firmware in the
4
code.
4
sbsa-ref functional tests.
5
5
6
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
6
The firmware is built using Debian 'bookworm' cross toolchain (gcc
7
Message-id: 20220227042241.1543-1-akihiko.odaki@gmail.com
7
12.2.0).
8
9
Used versions:
10
11
- Trusted Firmware v2.12.0
12
- Tianocore EDK2 stable202411
13
- Tianocore EDK2 Platforms code commit 4b3530d
14
15
This allows us to move away from "some git commit on trunk"
16
to a stable release for both TF-A and EDK2.
17
18
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
19
Message-id: 20241125125448.185504-1-marcin.juszkiewicz@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
22
---
11
ui/cocoa.m | 112 +++++++++++------------------------------------------
23
tests/functional/test_aarch64_sbsaref.py | 20 ++++++++++----------
12
1 file changed, 23 insertions(+), 89 deletions(-)
24
1 file changed, 10 insertions(+), 10 deletions(-)
13
25
14
diff --git a/ui/cocoa.m b/ui/cocoa.m
26
diff --git a/tests/functional/test_aarch64_sbsaref.py b/tests/functional/test_aarch64_sbsaref.py
15
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100755
16
--- a/ui/cocoa.m
28
--- a/tests/functional/test_aarch64_sbsaref.py
17
+++ b/ui/cocoa.m
29
+++ b/tests/functional/test_aarch64_sbsaref.py
18
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
30
@@ -XXX,XX +XXX,XX @@ def fetch_firmware(test):
19
31
20
static void cocoa_refresh(DisplayChangeListener *dcl);
32
Used components:
21
33
22
-static NSWindow *normalWindow, *about_window;
34
- - Trusted Firmware v2.11.0
23
+static NSWindow *normalWindow;
35
- - Tianocore EDK2 4d4f569924
24
static const DisplayChangeListenerOps dcl_ops = {
36
- - Tianocore EDK2-platforms 3f08401
25
.dpy_name = "cocoa",
37
+ - Trusted Firmware v2.12.0
26
.dpy_gfx_update = cocoa_update,
38
+ - Tianocore EDK2 edk2-stable202411
27
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
39
+ - Tianocore EDK2-platforms 4b3530d
28
- (BOOL)verifyQuit;
40
29
- (void)openDocumentation:(NSString *)filename;
41
"""
30
- (IBAction) do_about_menu_item: (id) sender;
42
31
-- (void)make_about_window;
43
@@ -XXX,XX +XXX,XX @@ class Aarch64SbsarefMachine(QemuSystemTest):
32
- (void)adjustSpeed:(id)sender;
44
33
@end
45
ASSET_FLASH0 = Asset(
34
46
('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/'
35
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
47
- '20240619-148232/edk2/SBSA_FLASH0.fd.xz'),
36
[pauseLabel setFont: [NSFont fontWithName: @"Helvetica" size: 90]];
48
- '0c954842a590988f526984de22e21ae0ab9cb351a0c99a8a58e928f0c7359cf7')
37
[pauseLabel setTextColor: [NSColor blackColor]];
49
+ '20241122-189881/edk2/SBSA_FLASH0.fd.xz'),
38
[pauseLabel sizeToFit];
50
+ '76eb89d42eebe324e4395329f47447cda9ac920aabcf99aca85424609c3384a5')
39
-
51
40
- [self make_about_window];
52
ASSET_FLASH1 = Asset(
41
}
53
('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/'
42
return self;
54
- '20240619-148232/edk2/SBSA_FLASH1.fd.xz'),
43
}
55
- 'c6ec39374c4d79bb9e9cdeeb6db44732d90bb4a334cec92002b3f4b9cac4b5ee')
44
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
56
+ '20241122-189881/edk2/SBSA_FLASH1.fd.xz'),
45
/* The action method for the About menu item */
57
+ 'f850f243bd8dbd49c51e061e0f79f1697546938f454aeb59ab7d93e5f0d412fc')
46
- (IBAction) do_about_menu_item: (id) sender
58
47
{
59
def test_sbsaref_edk2_firmware(self):
48
- [about_window makeKeyAndOrderFront: nil];
60
49
-}
61
@@ -XXX,XX +XXX,XX @@ def test_sbsaref_edk2_firmware(self):
50
-
62
51
-/* Create and display the about dialog */
63
# AP Trusted ROM
52
-- (void)make_about_window
64
wait_for_console_pattern(self, "Booting Trusted Firmware")
53
-{
65
- wait_for_console_pattern(self, "BL1: v2.11.0(release):")
54
- /* Make the window */
66
+ wait_for_console_pattern(self, "BL1: v2.12.0(release):")
55
- int x = 0, y = 0, about_width = 400, about_height = 200;
67
wait_for_console_pattern(self, "BL1: Booting BL2")
56
- NSRect window_rect = NSMakeRect(x, y, about_width, about_height);
68
57
- about_window = [[NSWindow alloc] initWithContentRect:window_rect
69
# Trusted Boot Firmware
58
- styleMask:NSWindowStyleMaskTitled | NSWindowStyleMaskClosable |
70
- wait_for_console_pattern(self, "BL2: v2.11.0(release)")
59
- NSWindowStyleMaskMiniaturizable
71
+ wait_for_console_pattern(self, "BL2: v2.12.0(release)")
60
- backing:NSBackingStoreBuffered
72
wait_for_console_pattern(self, "Booting BL31")
61
- defer:NO];
73
62
- [about_window setTitle: @"About"];
74
# EL3 Runtime Software
63
- [about_window setReleasedWhenClosed: NO];
75
- wait_for_console_pattern(self, "BL31: v2.11.0(release)")
64
- [about_window center];
76
+ wait_for_console_pattern(self, "BL31: v2.12.0(release)")
65
- NSView *superView = [about_window contentView];
77
66
-
78
# Non-trusted Firmware
67
- /* Create the dimensions of the picture */
79
wait_for_console_pattern(self, "UEFI firmware (version 1.0")
68
- int picture_width = 80, picture_height = 80;
69
- x = (about_width - picture_width)/2;
70
- y = about_height - picture_height - 10;
71
- NSRect picture_rect = NSMakeRect(x, y, picture_width, picture_height);
72
-
73
- /* Make the picture of QEMU */
74
- NSImageView *picture_view = [[NSImageView alloc] initWithFrame:
75
- picture_rect];
76
- char *qemu_image_path_c = get_relocated_path(CONFIG_QEMU_ICONDIR "/hicolor/512x512/apps/qemu.png");
77
- NSString *qemu_image_path = [NSString stringWithUTF8String:qemu_image_path_c];
78
- g_free(qemu_image_path_c);
79
- NSImage *qemu_image = [[NSImage alloc] initWithContentsOfFile:qemu_image_path];
80
- [picture_view setImage: qemu_image];
81
- [picture_view setImageScaling: NSImageScaleProportionallyUpOrDown];
82
- [superView addSubview: picture_view];
83
-
84
- /* Make the name label */
85
- NSBundle *bundle = [NSBundle mainBundle];
86
- if (bundle) {
87
- x = 0;
88
- y = y - 25;
89
- int name_width = about_width, name_height = 20;
90
- NSRect name_rect = NSMakeRect(x, y, name_width, name_height);
91
- NSTextField *name_label = [[NSTextField alloc] initWithFrame: name_rect];
92
- [name_label setEditable: NO];
93
- [name_label setBezeled: NO];
94
- [name_label setDrawsBackground: NO];
95
- [name_label setAlignment: NSTextAlignmentCenter];
96
- NSString *qemu_name = [[bundle executablePath] lastPathComponent];
97
- [name_label setStringValue: qemu_name];
98
- [superView addSubview: name_label];
99
+ NSAutoreleasePool *pool = [[NSAutoreleasePool alloc] init];
100
+ char *icon_path_c = get_relocated_path(CONFIG_QEMU_ICONDIR "/hicolor/512x512/apps/qemu.png");
101
+ NSString *icon_path = [NSString stringWithUTF8String:icon_path_c];
102
+ g_free(icon_path_c);
103
+ NSImage *icon = [[NSImage alloc] initWithContentsOfFile:icon_path];
104
+ NSString *version = @"QEMU emulator version " QEMU_FULL_VERSION;
105
+ NSString *copyright = @QEMU_COPYRIGHT;
106
+ NSDictionary *options;
107
+ if (icon) {
108
+ options = @{
109
+ NSAboutPanelOptionApplicationIcon : icon,
110
+ NSAboutPanelOptionApplicationVersion : version,
111
+ @"Copyright" : copyright,
112
+ };
113
+ [icon release];
114
+ } else {
115
+ options = @{
116
+ NSAboutPanelOptionApplicationVersion : version,
117
+ @"Copyright" : copyright,
118
+ };
119
}
120
-
121
- /* Set the version label's attributes */
122
- x = 0;
123
- y = 50;
124
- int version_width = about_width, version_height = 20;
125
- NSRect version_rect = NSMakeRect(x, y, version_width, version_height);
126
- NSTextField *version_label = [[NSTextField alloc] initWithFrame:
127
- version_rect];
128
- [version_label setEditable: NO];
129
- [version_label setBezeled: NO];
130
- [version_label setAlignment: NSTextAlignmentCenter];
131
- [version_label setDrawsBackground: NO];
132
-
133
- /* Create the version string*/
134
- NSString *version_string;
135
- version_string = [[NSString alloc] initWithFormat:
136
- @"QEMU emulator version %s", QEMU_FULL_VERSION];
137
- [version_label setStringValue: version_string];
138
- [superView addSubview: version_label];
139
-
140
- /* Make copyright label */
141
- x = 0;
142
- y = 35;
143
- int copyright_width = about_width, copyright_height = 20;
144
- NSRect copyright_rect = NSMakeRect(x, y, copyright_width, copyright_height);
145
- NSTextField *copyright_label = [[NSTextField alloc] initWithFrame:
146
- copyright_rect];
147
- [copyright_label setEditable: NO];
148
- [copyright_label setBezeled: NO];
149
- [copyright_label setDrawsBackground: NO];
150
- [copyright_label setAlignment: NSTextAlignmentCenter];
151
- [copyright_label setStringValue: [NSString stringWithFormat: @"%s",
152
- QEMU_COPYRIGHT]];
153
- [superView addSubview: copyright_label];
154
+ [NSApp orderFrontStandardAboutPanelWithOptions:options];
155
+ [pool release];
156
}
157
158
/* Used by the Speed menu items */
159
--
80
--
160
2.25.1
81
2.34.1
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Patchew 2.1-devel-b67e4c2

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