In the Neon VLD*/VST* "load/store single N-element structure to/from
one lane" instructions the encodings include bits to specify a
"stride" value, which specifies the separation between the Neon
registers which hold the different elements of the structure.  For
VLD1/VST1 there is only a single element and thus only one Neon
register is involved.  This means "stride" is not meaningful, and the
architecture requires that the bits that would encode it must be zero
(which is to say, must encode a stride value of 1).  We weren't
making this encoding check, so would incorrectly treat some
instruction patterns as being a VLD1/VST1 when they should UNDEF. 
(https://gitlab.com/qemu-project/qemu/-/issues/890)

Patch 1 fixes that bug.  Patch 2 is a minor cleanup of the align bits
check for VLD3/VST3 -- we had this logically correct (all the align
bits must be zero) but wrote it in a confusing way.

Richard: I tested this against your simple test case in the bug
report; if you could run it through your risu tests as well that
would be great.

thanks
-- PMM

Peter Maydell (2):
  target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
  target/arm/translate-neon: Simplify align field check for VLD3

 target/arm/translate-neon.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

-- 
2.25.1