[PULL 00/26] target-arm queue
[PULL 00/35] target-arm queue
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The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:
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The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
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Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging (2022-03-02 12:38:46 +0000)
3
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220302
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
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for you to fetch changes up to 268c11984e67867c22f53beb3c7f8b98900d66b2:
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for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
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ui/cocoa.m: Remove unnecessary NSAutoreleasePools (2022-03-02 19:27:37 +0000)
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docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
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13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
target-arm queue:
14
target-arm queue:
15
* mps3-an547: Add missing user ahb interfaces
15
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
16
* hw/arm/mps2-tz.c: Update AN547 documentation URL
16
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
17
* hw/input/tsc210x: Don't abort on bad SPI word widths
17
* Fix some errors in SVE/SME handling of MTE tags
18
* hw/i2c: flatten pca954x mux device
18
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
19
* target/arm: Support PSCI 1.1 and SMCCC 1.0
19
* hw/block/tc58128: Don't emit deprecation warning under qtest
20
* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
20
* tests/qtest: Fix handling of npcm7xx and GMAC tests
21
* tests/qtest: add qtests for npcm7xx sdhci
21
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
22
* Implement FEAT_LVA
22
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
23
* Implement FEAT_LPA
23
* Don't assert on vmload/vmsave of M-profile CPUs
24
* Implement FEAT_LPA2 (but do not enable it yet)
24
* hw/arm/smmuv3: add support for stage 1 access fault
25
* Report KVM's actual PSCI version to guest in dtb
25
* hw/arm/stellaris: QOM cleanups
26
* ui/cocoa.m: Fix updateUIInfo threading issues
26
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
27
* ui/cocoa.m: Remove unnecessary NSAutoreleasePools
27
* Improve Cortex_R52 IMPDEF sysreg modelling
28
* Allow access to SPSR_hyp from hyp mode
29
* New board model mps3-an536 (Cortex-R52)
28
30
29
----------------------------------------------------------------
31
----------------------------------------------------------------
30
Akihiko Odaki (1):
32
Luc Michel (1):
31
target/arm: Support PSCI 1.1 and SMCCC 1.0
33
hw/arm/smmuv3: add support for stage 1 access fault
32
34
33
Jimmy Brisson (1):
35
Nabih Estefan (1):
34
mps3-an547: Add missing user ahb interfaces
36
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
35
37
36
Patrick Venture (1):
38
Peter Maydell (22):
37
hw/i2c: flatten pca954x mux device
39
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
40
hw/block/tc58128: Don't emit deprecation warning under qtest
41
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
42
tests/qtest/bios-tables-test: Allow changes to virt GTDT
43
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
44
tests/qtest/bios-tables-tests: Update virt golden reference
45
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
46
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
47
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
48
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
49
target/arm: The Cortex-R52 has a read-only CBAR
50
target/arm: Add Cortex-R52 IMPDEF sysregs
51
target/arm: Allow access to SPSR_hyp from hyp mode
52
hw/misc/mps2-scc: Fix condition for CFG3 register
53
hw/misc/mps2-scc: Factor out which-board conditionals
54
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
55
hw/arm/mps3r: Initial skeleton for mps3-an536 board
56
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
57
hw/arm/mps3r: Add UARTs
58
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
59
hw/arm/mps3r: Add remaining devices
60
docs: Add documentation for the mps3-an536 board
38
61
39
Peter Maydell (5):
62
Philippe Mathieu-Daudé (5):
40
hw/arm/mps2-tz.c: Update AN547 documentation URL
63
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
41
hw/input/tsc210x: Don't abort on bad SPI word widths
64
hw/arm/stellaris: Convert ADC controller to Resettable interface
42
target/arm: Report KVM's actual PSCI version to guest in dtb
65
hw/arm/stellaris: Convert I2C controller to Resettable interface
43
ui/cocoa.m: Fix updateUIInfo threading issues
66
hw/arm/stellaris: Add missing QOM 'machine' parent
44
ui/cocoa.m: Remove unnecessary NSAutoreleasePools
67
hw/arm/stellaris: Add missing QOM 'SoC' parent
45
68
46
Richard Henderson (16):
69
Richard Henderson (6):
47
hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
70
linux-user/aarch64: Choose SYNC as the preferred MTE mode
48
target/arm: Set TCR_EL1.TSZ for user-only
71
target/arm: Fix nregs computation in do_{ld,st}_zpa
49
target/arm: Fault on invalid TCR_ELx.TxSZ
72
target/arm: Adjust and validate mtedesc sizem1
50
target/arm: Move arm_pamax out of line
73
target/arm: Split out make_svemte_desc
51
target/arm: Pass outputsize down to check_s2_mmu_setup
74
target/arm: Handle mte in do_ldrq, do_ldro
52
target/arm: Use MAKE_64BIT_MASK to compute indexmask
75
target/arm: Fix SVE/SME gross MTE suppression checks
53
target/arm: Honor TCR_ELx.{I}PS
54
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
55
target/arm: Implement FEAT_LVA
56
target/arm: Implement FEAT_LPA
57
target/arm: Extend arm_fi_to_lfsc to level -1
58
target/arm: Introduce tlbi_aa64_get_range
59
target/arm: Fix TLBIRange.base for 16k and 64k pages
60
target/arm: Validate tlbi TG matches translation granule in use
61
target/arm: Advertise all page sizes for -cpu max
62
target/arm: Implement FEAT_LPA2
63
76
64
Shengtan Mao (1):
77
MAINTAINERS | 3 +-
65
tests/qtest: add qtests for npcm7xx sdhci
78
docs/system/arm/mps2.rst | 37 +-
79
configs/devices/arm-softmmu/default.mak | 1 +
80
hw/arm/smmuv3-internal.h | 1 +
81
include/hw/arm/smmu-common.h | 1 +
82
include/hw/arm/virt.h | 2 +
83
include/hw/misc/mps2-scc.h | 1 +
84
linux-user/aarch64/target_prctl.h | 29 +-
85
target/arm/internals.h | 2 +-
86
target/arm/tcg/translate-a64.h | 2 +
87
hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++
88
hw/arm/npcm7xx.c | 1 +
89
hw/arm/smmu-common.c | 11 +
90
hw/arm/smmuv3.c | 1 +
91
hw/arm/stellaris.c | 47 ++-
92
hw/arm/virt-acpi-build.c | 20 +-
93
hw/arm/virt.c | 60 ++-
94
hw/arm/xilinx_zynq.c | 2 +
95
hw/block/tc58128.c | 4 +-
96
hw/misc/mps2-scc.c | 138 ++++++-
97
hw/pci-host/raven.c | 1 +
98
target/arm/helper.c | 14 +-
99
target/arm/tcg/cpu32.c | 109 ++++++
100
target/arm/tcg/op_helper.c | 43 ++-
101
target/arm/tcg/sme_helper.c | 8 +-
102
target/arm/tcg/sve_helper.c | 12 +-
103
target/arm/tcg/translate-sme.c | 15 +-
104
target/arm/tcg/translate-sve.c | 83 +++--
105
target/arm/tcg/translate.c | 19 +-
106
tests/qtest/npcm7xx_emc-test.c | 5 +-
107
tests/qtest/npcm_gmac-test.c | 84 +----
108
hw/arm/Kconfig | 5 +
109
hw/arm/meson.build | 1 +
110
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
111
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
112
tests/qtest/meson.build | 4 +-
113
36 files changed, 1184 insertions(+), 222 deletions(-)
114
create mode 100644 hw/arm/mps3r.c
66
115
67
Wentao_Liang (1):
68
target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
69
70
docs/system/arm/emulation.rst | 3 +
71
include/hw/registerfields.h | 48 +++++-
72
target/arm/cpu-param.h | 4 +-
73
target/arm/cpu.h | 27 ++++
74
target/arm/internals.h | 58 ++++---
75
target/arm/kvm-consts.h | 14 +-
76
hw/arm/boot.c | 11 +-
77
hw/arm/mps2-tz.c | 6 +-
78
hw/i2c/i2c_mux_pca954x.c | 77 ++-------
79
hw/input/tsc210x.c | 8 +-
80
target/arm/cpu.c | 8 +-
81
target/arm/cpu64.c | 7 +-
82
target/arm/helper.c | 332 ++++++++++++++++++++++++++++++---------
83
target/arm/hvf/hvf.c | 27 +++-
84
target/arm/kvm64.c | 14 +-
85
target/arm/psci.c | 35 ++++-
86
target/arm/translate-a64.c | 2 +-
87
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++
88
tests/qtest/meson.build | 1 +
89
ui/cocoa.m | 31 ++--
90
20 files changed, 736 insertions(+), 192 deletions(-)
91
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
diff view generated by jsdifflib
[PULL 21/26] target/arm: Validate tlbi TG matches translation granule in use
[PULL 01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
For FEAT_LPA2, we will need other ARMVAParameters, which themselves
3
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
4
depend on the translation granule in use. We might as well validate
4
connect FIQ output of the GIC CPU interfaces to the CPU.
5
that the given TG matches; the architecture "does not require that
6
the instruction invalidates any entries" if this is not true.
7
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240130152548.17855-1-philmd@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220301215958.157011-15-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/helper.c | 10 +++++++---
11
hw/arm/xilinx_zynq.c | 2 ++
14
1 file changed, 7 insertions(+), 3 deletions(-)
12
1 file changed, 2 insertions(+)
15
13
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
16
--- a/hw/arm/xilinx_zynq.c
19
+++ b/target/arm/helper.c
17
+++ b/hw/arm/xilinx_zynq.c
20
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
18
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
21
uint64_t value)
19
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
22
{
20
sysbus_connect_irq(busdev, 0,
23
unsigned int page_size_granule, page_shift, num, scale, exponent;
21
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
24
+ /* Extract one bit to represent the va selector in use. */
22
+ sysbus_connect_irq(busdev, 1,
25
+ uint64_t select = sextract64(value, 36, 1);
23
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
26
+ ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true);
24
27
TLBIRange ret = { };
25
for (n = 0; n < 64; n++) {
28
26
pic[n] = qdev_get_gpio_in(dev, n);
29
page_size_granule = extract64(value, 46, 2);
30
31
- if (page_size_granule == 0) {
32
- qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
33
+ /* The granule encoded in value must match the granule in use. */
34
+ if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) {
35
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n",
36
page_size_granule);
37
return ret;
38
}
39
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
40
41
ret.length = (num + 1) << (exponent + page_shift);
42
43
- if (regime_has_2_ranges(mmuidx)) {
44
+ if (param.select) {
45
ret.base = sextract64(value, 0, 37);
46
} else {
47
ret.base = extract64(value, 0, 37);
48
--
27
--
49
2.25.1
28
2.34.1
29
30
diff view generated by jsdifflib
[PULL 22/26] target/arm: Advertise all page sizes for -cpu max
[PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We support 16k pages, but do not advertize that in ID_AA64MMFR0.
3
The API does not generate an error for setting ASYNC | SYNC; that merely
4
constrains the selection vs the per-cpu default. For qemu linux-user,
5
choose SYNC as the default.
4
6
5
The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer
7
Cc: qemu-stable@nongnu.org
6
to the same support as stage1 lookups. This setting is deprecated, so
8
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
7
indicate support for all stage2 page sizes directly.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
11
Message-id: 20220301215958.157011-16-richard.henderson@linaro.org
11
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
13
---
14
target/arm/cpu64.c | 4 ++++
14
linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
15
1 file changed, 4 insertions(+)
15
1 file changed, 17 insertions(+), 12 deletions(-)
16
16
17
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
17
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu64.c
19
--- a/linux-user/aarch64/target_prctl.h
20
+++ b/target/arm/cpu64.c
20
+++ b/linux-user/aarch64/target_prctl.h
21
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
21
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
22
22
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
23
t = cpu->isar.id_aa64mmfr0;
23
24
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
24
if (cpu_isar_feature(aa64_mte, cpu)) {
25
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
25
- switch (arg2 & PR_MTE_TCF_MASK) {
26
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
26
- case PR_MTE_TCF_NONE:
27
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
27
- case PR_MTE_TCF_SYNC:
28
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
28
- case PR_MTE_TCF_ASYNC:
29
cpu->isar.id_aa64mmfr0 = t;
29
- break;
30
30
- default:
31
t = cpu->isar.id_aa64mmfr1;
31
- return -EINVAL;
32
- }
33
-
34
/*
35
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
36
- * Note that the syscall values are consistent with hw.
37
+ *
38
+ * The kernel has a per-cpu configuration for the sysadmin,
39
+ * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
40
+ * which qemu does not implement.
41
+ *
42
+ * Because there is no performance difference between the modes, and
43
+ * because SYNC is most useful for debugging MTE errors, choose SYNC
44
+ * as the preferred mode. With this preference, and the way the API
45
+ * uses only two bits, there is no way for the program to select
46
+ * ASYMM mode.
47
*/
48
- env->cp15.sctlr_el[1] =
49
- deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
50
+ unsigned tcf = 0;
51
+ if (arg2 & PR_MTE_TCF_SYNC) {
52
+ tcf = 1;
53
+ } else if (arg2 & PR_MTE_TCF_ASYNC) {
54
+ tcf = 2;
55
+ }
56
+ env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
57
58
/*
59
* Write PR_MTE_TAG to GCR_EL1[Exclude].
32
--
60
--
33
2.25.1
61
2.34.1
diff view generated by jsdifflib
[PULL 16/26] target/arm: Implement FEAT_LVA
[PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This feature is relatively small, as it applies only to
3
The field is encoded as [0-3], which is convenient for
4
64k pages and thus requires no additional changes to the
4
indexing our array of function pointers, but the true
5
table descriptor walking algorithm, only a change to the
5
value is [1-4]. Adjust before calling do_mem_zpa.
6
minimum TSZ (which is the inverse of the maximum virtual
7
address space size).
8
6
9
Note that this feature widens VBAR_ELx, but we already
7
Add an assert, and move the comment re passing ZT to
10
treat the register as being 64 bits wide.
8
the helper back next to the relevant code.
11
9
10
Cc: qemu-stable@nongnu.org
11
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
14
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220301215958.157011-10-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
---
17
docs/system/arm/emulation.rst | 1 +
18
target/arm/tcg/translate-sve.c | 16 ++++++++--------
18
target/arm/cpu-param.h | 2 +-
19
1 file changed, 8 insertions(+), 8 deletions(-)
19
target/arm/cpu.h | 5 +++++
20
target/arm/cpu64.c | 1 +
21
target/arm/helper.c | 9 ++++++++-
22
5 files changed, 16 insertions(+), 2 deletions(-)
23
20
24
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
21
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
25
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
26
--- a/docs/system/arm/emulation.rst
23
--- a/target/arm/tcg/translate-sve.c
27
+++ b/docs/system/arm/emulation.rst
24
+++ b/target/arm/tcg/translate-sve.c
28
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
25
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
29
- FEAT_LRCPC (Load-acquire RCpc instructions)
26
TCGv_ptr t_pg;
30
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
27
int desc = 0;
31
- FEAT_LSE (Large System Extensions)
28
32
+- FEAT_LVA (Large Virtual Address space)
29
- /*
33
- FEAT_MTE (Memory Tagging Extension)
30
- * For e.g. LD4, there are not enough arguments to pass all 4
34
- FEAT_MTE2 (Memory Tagging Extension)
31
- * registers as pointers, so encode the regno into the data field.
35
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
32
- * For consistency, do this even for LD1.
36
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
33
- */
37
index XXXXXXX..XXXXXXX 100644
34
+ assert(mte_n >= 1 && mte_n <= 4);
38
--- a/target/arm/cpu-param.h
35
if (s->mte_active[0]) {
39
+++ b/target/arm/cpu-param.h
36
int msz = dtype_msz(dtype);
40
@@ -XXX,XX +XXX,XX @@
37
41
#ifdef TARGET_AARCH64
38
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
42
# define TARGET_LONG_BITS 64
39
addr = clean_data_tbi(s, addr);
43
# define TARGET_PHYS_ADDR_SPACE_BITS 48
40
}
44
-# define TARGET_VIRT_ADDR_SPACE_BITS 48
41
45
+# define TARGET_VIRT_ADDR_SPACE_BITS 52
42
+ /*
46
#else
43
+ * For e.g. LD4, there are not enough arguments to pass all 4
47
# define TARGET_LONG_BITS 32
44
+ * registers as pointers, so encode the regno into the data field.
48
# define TARGET_PHYS_ADDR_SPACE_BITS 40
45
+ * For consistency, do this even for LD1.
49
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
46
+ */
50
index XXXXXXX..XXXXXXX 100644
47
desc = simd_desc(vsz, vsz, zt | desc);
51
--- a/target/arm/cpu.h
48
t_pg = tcg_temp_new_ptr();
52
+++ b/target/arm/cpu.h
49
53
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
50
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
54
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
51
* accessible via the instruction encoding.
52
*/
53
assert(fn != NULL);
54
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
55
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
55
}
56
}
56
57
57
+static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
58
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
58
+{
59
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
59
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
60
if (nreg == 0) {
60
+}
61
/* ST1 */
61
+
62
fn = fn_single[s->mte_active[0]][be][msz][esz];
62
static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
63
- nreg = 1;
63
{
64
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
65
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/cpu64.c
68
+++ b/target/arm/cpu64.c
69
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
70
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
71
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
72
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
73
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
74
cpu->isar.id_aa64mmfr2 = t;
75
76
t = cpu->isar.id_aa64zfr0;
77
diff --git a/target/arm/helper.c b/target/arm/helper.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/helper.c
80
+++ b/target/arm/helper.c
81
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
82
} else {
64
} else {
83
max_tsz = 39;
65
/* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
66
assert(msz == esz);
67
fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
84
}
68
}
85
- min_tsz = 16; /* TODO: ARMv8.2-LVA */
69
assert(fn != NULL);
86
+
70
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
87
+ min_tsz = 16;
71
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
88
+ if (using64k) {
72
}
89
+ if (cpu_isar_feature(aa64_lva, env_archcpu(env))) {
73
90
+ min_tsz = 12;
74
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
91
+ }
92
+ }
93
+ /* TODO: FEAT_LPA2 */
94
95
if (tsz > max_tsz) {
96
tsz = max_tsz;
97
--
75
--
98
2.25.1
76
2.34.1
diff view generated by jsdifflib
[PULL 18/26] target/arm: Extend arm_fi_to_lfsc to level -1
[PULL 04/35] target/arm: Adjust and validate mtedesc sizem1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
With FEAT_LPA2, rather than introducing translation level 4,
3
When we added SVE_MTEDESC_SHIFT, we effectively limited the
4
we introduce level -1, below the current level 0. Extend
4
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
5
arm_fi_to_lfsc to handle these faults.
5
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
6
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
6
7
7
Assert that this new translation level does not leak into
8
Cc: qemu-stable@nongnu.org
8
fault types for which it is not defined, which allows some
9
masking of fi->level to be removed.
10
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220301215958.157011-12-richard.henderson@linaro.org
11
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
14
---
16
target/arm/internals.h | 35 +++++++++++++++++++++++++++++------
15
target/arm/internals.h | 2 +-
17
1 file changed, 29 insertions(+), 6 deletions(-)
16
target/arm/tcg/translate-sve.c | 7 ++++---
17
2 files changed, 5 insertions(+), 4 deletions(-)
18
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
21
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
23
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2)
24
case ARMFault_None:
24
FIELD(MTEDESC, TCMA, 6, 2)
25
return 0;
25
FIELD(MTEDESC, WRITE, 8, 1)
26
case ARMFault_AddressSize:
26
FIELD(MTEDESC, ALIGN, 9, 3)
27
- fsc = fi->level & 3;
27
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
28
+ assert(fi->level >= -1 && fi->level <= 3);
28
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */
29
+ if (fi->level < 0) {
29
30
+ fsc = 0b101001;
30
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
31
+ } else {
31
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
32
+ fsc = fi->level;
32
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
33
+ }
33
index XXXXXXX..XXXXXXX 100644
34
break;
34
--- a/target/arm/tcg/translate-sve.c
35
case ARMFault_AccessFlag:
35
+++ b/target/arm/tcg/translate-sve.c
36
- fsc = (fi->level & 3) | (0x2 << 2);
36
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
37
+ assert(fi->level >= 0 && fi->level <= 3);
37
{
38
+ fsc = 0b001000 | fi->level;
38
unsigned vsz = vec_full_reg_size(s);
39
break;
39
TCGv_ptr t_pg;
40
case ARMFault_Permission:
40
+ uint32_t sizem1;
41
- fsc = (fi->level & 3) | (0x3 << 2);
41
int desc = 0;
42
+ assert(fi->level >= 0 && fi->level <= 3);
42
43
+ fsc = 0b001100 | fi->level;
43
assert(mte_n >= 1 && mte_n <= 4);
44
break;
44
+ sizem1 = (mte_n << dtype_msz(dtype)) - 1;
45
case ARMFault_Translation:
45
+ assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
46
- fsc = (fi->level & 3) | (0x1 << 2);
46
if (s->mte_active[0]) {
47
+ assert(fi->level >= -1 && fi->level <= 3);
47
- int msz = dtype_msz(dtype);
48
+ if (fi->level < 0) {
48
-
49
+ fsc = 0b101011;
49
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
50
+ } else {
50
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
51
+ fsc = 0b000100 | fi->level;
51
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
52
+ }
52
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
53
break;
53
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
54
case ARMFault_SyncExternal:
54
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
55
fsc = 0x10 | (fi->ea << 12);
55
desc <<= SVE_MTEDESC_SHIFT;
56
break;
56
} else {
57
case ARMFault_SyncExternalOnWalk:
57
addr = clean_data_tbi(s, addr);
58
- fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12);
59
+ assert(fi->level >= -1 && fi->level <= 3);
60
+ if (fi->level < 0) {
61
+ fsc = 0b010011;
62
+ } else {
63
+ fsc = 0b010100 | fi->level;
64
+ }
65
+ fsc |= fi->ea << 12;
66
break;
67
case ARMFault_SyncParity:
68
fsc = 0x18;
69
break;
70
case ARMFault_SyncParityOnWalk:
71
- fsc = (fi->level & 3) | (0x7 << 2);
72
+ assert(fi->level >= -1 && fi->level <= 3);
73
+ if (fi->level < 0) {
74
+ fsc = 0b011011;
75
+ } else {
76
+ fsc = 0b011100 | fi->level;
77
+ }
78
break;
79
case ARMFault_AsyncParity:
80
fsc = 0x19;
81
--
58
--
82
2.25.1
59
2.34.1
diff view generated by jsdifflib
[PULL 17/26] target/arm: Implement FEAT_LPA
[PULL 05/35] target/arm: Split out make_svemte_desc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This feature widens physical addresses (and intermediate physical
3
Share code that creates mtedesc and embeds within simd_desc.
4
addresses for 2-stage translation) from 48 to 52 bits, when using
5
64k pages. The only thing left at this point is to handle the
6
extra bits in the TTBR and in the table descriptors.
7
4
8
Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't
5
Cc: qemu-stable@nongnu.org
9
mask out the high bits when writing to those registers, so no changes
10
are required there.
11
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220301215958.157011-11-richard.henderson@linaro.org
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
11
---
17
docs/system/arm/emulation.rst | 1 +
12
target/arm/tcg/translate-a64.h | 2 ++
18
target/arm/cpu-param.h | 2 +-
13
target/arm/tcg/translate-sme.c | 15 +++--------
19
target/arm/cpu64.c | 2 +-
14
target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
20
target/arm/helper.c | 19 ++++++++++++++++---
15
3 files changed, 31 insertions(+), 33 deletions(-)
21
4 files changed, 19 insertions(+), 5 deletions(-)
22
16
23
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
24
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/system/arm/emulation.rst
19
--- a/target/arm/tcg/translate-a64.h
26
+++ b/docs/system/arm/emulation.rst
20
+++ b/target/arm/tcg/translate-a64.h
27
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
28
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
22
bool sve_access_check(DisasContext *s);
29
- FEAT_JSCVT (JavaScript conversion instructions)
23
bool sme_enabled_check(DisasContext *s);
30
- FEAT_LOR (Limited ordering regions)
24
bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
31
+- FEAT_LPA (Large Physical Address space)
25
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
32
- FEAT_LRCPC (Load-acquire RCpc instructions)
26
+ uint32_t msz, bool is_write, uint32_t data);
33
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
27
34
- FEAT_LSE (Large System Extensions)
28
/* This function corresponds to CheckStreamingSVEEnabled. */
35
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
29
static inline bool sme_sm_enabled_check(DisasContext *s)
30
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
36
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu-param.h
32
--- a/target/arm/tcg/translate-sme.c
38
+++ b/target/arm/cpu-param.h
33
+++ b/target/arm/tcg/translate-sme.c
39
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
40
35
41
#ifdef TARGET_AARCH64
36
TCGv_ptr t_za, t_pg;
42
# define TARGET_LONG_BITS 64
37
TCGv_i64 addr;
43
-# define TARGET_PHYS_ADDR_SPACE_BITS 48
38
- int svl, desc = 0;
44
+# define TARGET_PHYS_ADDR_SPACE_BITS 52
39
+ uint32_t desc;
45
# define TARGET_VIRT_ADDR_SPACE_BITS 52
40
bool be = s->be_data == MO_BE;
46
#else
41
bool mte = s->mte_active[0];
47
# define TARGET_LONG_BITS 32
42
48
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
43
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
44
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
45
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
46
47
- if (mte) {
48
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
49
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
50
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
51
- desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
52
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
53
- desc <<= SVE_MTEDESC_SHIFT;
54
- } else {
55
+ if (!mte) {
56
addr = clean_data_tbi(s, addr);
57
}
58
- svl = streaming_vec_reg_size(s);
59
- desc = simd_desc(svl, svl, desc);
60
+
61
+ desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
62
63
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
64
tcg_constant_i32(desc));
65
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
49
index XXXXXXX..XXXXXXX 100644
66
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/cpu64.c
67
--- a/target/arm/tcg/translate-sve.c
51
+++ b/target/arm/cpu64.c
68
+++ b/target/arm/tcg/translate-sve.c
52
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
69
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
53
cpu->isar.id_aa64pfr1 = t;
70
3, 2, 1, 3
54
55
t = cpu->isar.id_aa64mmfr0;
56
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
57
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
58
cpu->isar.id_aa64mmfr0 = t;
59
60
t = cpu->isar.id_aa64mmfr1;
61
diff --git a/target/arm/helper.c b/target/arm/helper.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/helper.c
64
+++ b/target/arm/helper.c
65
@@ -XXX,XX +XXX,XX @@ static const uint8_t pamax_map[] = {
66
[3] = 42,
67
[4] = 44,
68
[5] = 48,
69
+ [6] = 52,
70
};
71
};
71
72
72
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
73
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
73
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
74
- int dtype, uint32_t mte_n, bool is_write,
74
descaddr = extract64(ttbr, 0, 48);
75
- gen_helper_gvec_mem *fn)
75
76
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
76
/*
77
+ uint32_t msz, bool is_write, uint32_t data)
77
- * If the base address is out of range, raise AddressSizeFault.
78
{
78
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
79
- unsigned vsz = vec_full_reg_size(s);
79
+ *
80
- TCGv_ptr t_pg;
80
+ * Otherwise, if the base address is out of range, raise AddressSizeFault.
81
uint32_t sizem1;
81
* In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
82
- int desc = 0;
82
* but we've just cleared the bits above 47, so simplify the test.
83
+ uint32_t desc = 0;
84
85
- assert(mte_n >= 1 && mte_n <= 4);
86
- sizem1 = (mte_n << dtype_msz(dtype)) - 1;
87
+ /* Assert all of the data fits, with or without MTE enabled. */
88
+ assert(nregs >= 1 && nregs <= 4);
89
+ sizem1 = (nregs << msz) - 1;
90
assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
91
+ assert(data < 1u << SVE_MTEDESC_SHIFT);
92
+
93
if (s->mte_active[0]) {
94
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
95
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
96
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
97
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
98
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
99
desc <<= SVE_MTEDESC_SHIFT;
100
- } else {
101
+ }
102
+ return simd_desc(vsz, vsz, desc | data);
103
+}
104
+
105
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
106
+ int dtype, uint32_t nregs, bool is_write,
107
+ gen_helper_gvec_mem *fn)
108
+{
109
+ TCGv_ptr t_pg;
110
+ uint32_t desc;
111
+
112
+ if (!s->mte_active[0]) {
113
addr = clean_data_tbi(s, addr);
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
117
* registers as pointers, so encode the regno into the data field.
118
* For consistency, do this even for LD1.
83
*/
119
*/
84
- if (descaddr >> outputsize) {
120
- desc = simd_desc(vsz, vsz, zt | desc);
85
+ if (outputsize > 48) {
121
+ desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
86
+ descaddr |= extract64(ttbr, 2, 4) << 48;
122
+ dtype_msz(dtype), is_write, zt);
87
+ } else if (descaddr >> outputsize) {
123
t_pg = tcg_temp_new_ptr();
88
level = 0;
124
89
fault_type = ARMFault_AddressSize;
125
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
90
goto do_fault;
126
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
91
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
127
int scale, TCGv_i64 scalar, int msz, bool is_write,
92
}
128
gen_helper_gvec_mem_scatter *fn)
93
129
{
94
descaddr = descriptor & descaddrmask;
130
- unsigned vsz = vec_full_reg_size(s);
95
- if (descaddr >> outputsize) {
131
TCGv_ptr t_zm = tcg_temp_new_ptr();
132
TCGv_ptr t_pg = tcg_temp_new_ptr();
133
TCGv_ptr t_zt = tcg_temp_new_ptr();
134
- int desc = 0;
135
-
136
- if (s->mte_active[0]) {
137
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
138
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
139
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
140
- desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
141
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
142
- desc <<= SVE_MTEDESC_SHIFT;
143
- }
144
- desc = simd_desc(vsz, vsz, desc | scale);
145
+ uint32_t desc;
146
147
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
148
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
149
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
96
+
150
+
97
+ /*
151
+ desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
98
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
152
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
99
+ * of descriptor. Otherwise, if descaddr is out of range, raise
153
}
100
+ * AddressSizeFault.
154
101
+ */
102
+ if (outputsize > 48) {
103
+ descaddr |= extract64(descriptor, 12, 4) << 48;
104
+ } else if (descaddr >> outputsize) {
105
fault_type = ARMFault_AddressSize;
106
goto do_fault;
107
}
108
--
155
--
109
2.25.1
156
2.34.1
diff view generated by jsdifflib
[PULL 12/26] target/arm: Pass outputsize down to check_s2_mmu_setup
[PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Pass down the width of the output address from translation.
3
These functions "use the standard load helpers", but
4
For now this is still just PAMax, but a subsequent patch will
4
fail to clean_data_tbi or populate mtedesc.
5
compute the correct value from TCR_ELx.{I}PS.
6
5
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220301215958.157011-6-richard.henderson@linaro.org
9
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
10
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/helper.c | 21 ++++++++++-----------
13
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
13
1 file changed, 10 insertions(+), 11 deletions(-)
14
1 file changed, 13 insertions(+), 2 deletions(-)
14
15
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
18
--- a/target/arm/tcg/translate-sve.c
18
+++ b/target/arm/helper.c
19
+++ b/target/arm/tcg/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ do_fault:
20
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
20
* false otherwise.
21
unsigned vsz = vec_full_reg_size(s);
21
*/
22
TCGv_ptr t_pg;
22
static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
23
int poff;
23
- int inputsize, int stride)
24
+ uint32_t desc;
24
+ int inputsize, int stride, int outputsize)
25
25
{
26
/* Load the first quadword using the normal predicated load helpers. */
26
const int grainsize = stride + 3;
27
+ if (!s->mte_active[0]) {
27
int startsizecheck;
28
+ addr = clean_data_tbi(s, addr);
28
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
29
+ }
30
+
31
poff = pred_full_reg_offset(s, pg);
32
if (vsz > 16) {
33
/*
34
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
35
36
gen_helper_gvec_mem *fn
37
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
38
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
39
+ desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
40
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
41
42
/* Replicate that first quadword. */
43
if (vsz > 16) {
44
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
45
unsigned vsz_r32;
46
TCGv_ptr t_pg;
47
int poff, doff;
48
+ uint32_t desc;
49
50
if (vsz < 32) {
51
/*
52
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
29
}
53
}
30
54
31
if (is_aa64) {
55
/* Load the first octaword using the normal predicated load helpers. */
32
- CPUARMState *env = &cpu->env;
56
+ if (!s->mte_active[0]) {
33
- unsigned int pamax = arm_pamax(cpu);
57
+ addr = clean_data_tbi(s, addr);
34
-
58
+ }
35
switch (stride) {
59
36
case 13: /* 64KB Pages. */
60
poff = pred_full_reg_offset(s, pg);
37
- if (level == 0 || (level == 1 && pamax <= 42)) {
61
if (vsz > 32) {
38
+ if (level == 0 || (level == 1 && outputsize <= 42)) {
62
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
39
return false;
63
40
}
64
gen_helper_gvec_mem *fn
41
break;
65
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
42
case 11: /* 16KB Pages. */
66
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
43
- if (level == 0 || (level == 1 && pamax <= 40)) {
67
+ desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
44
+ if (level == 0 || (level == 1 && outputsize <= 40)) {
68
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
45
return false;
46
}
47
break;
48
case 9: /* 4KB Pages. */
49
- if (level == 0 && pamax <= 42) {
50
+ if (level == 0 && outputsize <= 42) {
51
return false;
52
}
53
break;
54
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
55
}
56
57
/* Inputsize checks. */
58
- if (inputsize > pamax &&
59
- (arm_el_is_aa64(env, 1) || inputsize > 40)) {
60
+ if (inputsize > outputsize &&
61
+ (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
62
/* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
63
return false;
64
}
65
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
66
target_ulong page_size;
67
uint32_t attrs;
68
int32_t stride;
69
- int addrsize, inputsize;
70
+ int addrsize, inputsize, outputsize;
71
TCR *tcr = regime_tcr(env, mmu_idx);
72
int ap, ns, xn, pxn;
73
uint32_t el = regime_el(env, mmu_idx);
74
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
75
76
addrsize = 64 - 8 * param.tbi;
77
inputsize = 64 - param.tsz;
78
+ outputsize = arm_pamax(cpu);
79
} else {
80
param = aa32_va_parameters(env, address, mmu_idx);
81
level = 1;
82
addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
83
inputsize = addrsize - param.tsz;
84
+ outputsize = 40;
85
}
86
69
87
/*
70
/*
88
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
71
* Replicate that first octaword.
89
90
/* Check that the starting level is valid. */
91
ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
92
- inputsize, stride);
93
+ inputsize, stride, outputsize);
94
if (!ok) {
95
fault_type = ARMFault_Translation;
96
goto do_fault;
97
--
72
--
98
2.25.1
73
2.34.1
diff view generated by jsdifflib
[PULL 19/26] target/arm: Introduce tlbi_aa64_get_range
[PULL 07/35] target/arm: Fix SVE/SME gross MTE suppression checks
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base,
3
The TBI and TCMA bits are located within mtedesc, not desc.
4
returning a structure containing both results. Pass in the
5
ARMMMUIdx, rather than the digested two_ranges boolean.
6
4
7
This is in preparation for FEAT_LPA2, where the interpretation
5
Cc: qemu-stable@nongnu.org
8
of 'value' depends on the effective value of DS for the regime.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20220301215958.157011-13-richard.henderson@linaro.org
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
target/arm/helper.c | 58 +++++++++++++++++++--------------------------
12
target/arm/tcg/sme_helper.c | 8 ++++----
16
1 file changed, 24 insertions(+), 34 deletions(-)
13
target/arm/tcg/sve_helper.c | 12 ++++++------
14
2 files changed, 10 insertions(+), 10 deletions(-)
17
15
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
18
--- a/target/arm/tcg/sme_helper.c
21
+++ b/target/arm/helper.c
19
+++ b/target/arm/tcg/sme_helper.c
22
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
23
}
21
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
24
22
25
#ifdef TARGET_AARCH64
23
/* Perform gross MTE suppression early. */
26
-static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
24
- if (!tbi_check(desc, bit55) ||
27
- uint64_t value)
25
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
28
-{
26
+ if (!tbi_check(mtedesc, bit55) ||
29
- unsigned int page_shift;
27
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
30
- unsigned int page_size_granule;
28
mtedesc = 0;
31
- uint64_t num;
32
- uint64_t scale;
33
- uint64_t exponent;
34
+typedef struct {
35
+ uint64_t base;
36
uint64_t length;
37
+} TLBIRange;
38
+
39
+static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
40
+ uint64_t value)
41
+{
42
+ unsigned int page_size_granule, page_shift, num, scale, exponent;
43
+ TLBIRange ret = { };
44
45
- num = extract64(value, 39, 5);
46
- scale = extract64(value, 44, 2);
47
page_size_granule = extract64(value, 46, 2);
48
49
if (page_size_granule == 0) {
50
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
51
page_size_granule);
52
- return 0;
53
+ return ret;
54
}
29
}
55
30
56
page_shift = (page_size_granule - 1) * 2 + 12;
31
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
57
-
32
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
58
+ num = extract64(value, 39, 5);
33
59
+ scale = extract64(value, 44, 2);
34
/* Perform gross MTE suppression early. */
60
exponent = (5 * scale) + 1;
35
- if (!tbi_check(desc, bit55) ||
61
- length = (num + 1) << (exponent + page_shift);
36
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
62
37
+ if (!tbi_check(mtedesc, bit55) ||
63
- return length;
38
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
64
-}
39
mtedesc = 0;
65
+ ret.length = (num + 1) << (exponent + page_shift);
66
67
-static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value,
68
- bool two_ranges)
69
-{
70
- /* TODO: ARMv8.7 FEAT_LPA2 */
71
- uint64_t pageaddr;
72
-
73
- if (two_ranges) {
74
- pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
75
+ if (regime_has_2_ranges(mmuidx)) {
76
+ ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
77
} else {
78
- pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS;
79
+ ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS;
80
}
40
}
81
41
82
- return pageaddr;
42
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
83
+ return ret;
43
index XXXXXXX..XXXXXXX 100644
84
}
44
--- a/target/arm/tcg/sve_helper.c
85
45
+++ b/target/arm/tcg/sve_helper.c
86
static void do_rvae_write(CPUARMState *env, uint64_t value,
46
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
87
int idxmap, bool synced)
47
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
88
{
48
89
ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap);
49
/* Perform gross MTE suppression early. */
90
- bool two_ranges = regime_has_2_ranges(one_idx);
50
- if (!tbi_check(desc, bit55) ||
91
- uint64_t baseaddr, length;
51
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
92
+ TLBIRange range;
52
+ if (!tbi_check(mtedesc, bit55) ||
93
int bits;
53
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
94
54
mtedesc = 0;
95
- baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges);
96
- length = tlbi_aa64_range_get_length(env, value);
97
- bits = tlbbits_for_regime(env, one_idx, baseaddr);
98
+ range = tlbi_aa64_get_range(env, one_idx, value);
99
+ bits = tlbbits_for_regime(env, one_idx, range.base);
100
101
if (synced) {
102
tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
103
- baseaddr,
104
- length,
105
+ range.base,
106
+ range.length,
107
idxmap,
108
bits);
109
} else {
110
- tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr,
111
- length, idxmap, bits);
112
+ tlb_flush_range_by_mmuidx(env_cpu(env), range.base,
113
+ range.length, idxmap, bits);
114
}
55
}
115
}
56
57
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
58
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
59
60
/* Perform gross MTE suppression early. */
61
- if (!tbi_check(desc, bit55) ||
62
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
63
+ if (!tbi_check(mtedesc, bit55) ||
64
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
65
mtedesc = 0;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
69
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
70
71
/* Perform gross MTE suppression early. */
72
- if (!tbi_check(desc, bit55) ||
73
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
74
+ if (!tbi_check(mtedesc, bit55) ||
75
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
76
mtedesc = 0;
77
}
116
78
117
--
79
--
118
2.25.1
80
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
1
The raven_io_ops MemoryRegionOps is the only one in the source tree
2
which sets .valid.unaligned to indicate that it should support
3
unaligned accesses and which does not also set .impl.unaligned to
4
indicate that its read and write functions can do the unaligned
5
handling themselves. This is a problem, because at the moment the
6
core memory system does not implement the support for handling
7
unaligned accesses by doing a series of aligned accesses and
8
combining them (system/memory.c:access_with_adjusted_size() has a
9
TODO comment noting this).
1
10
11
Fortunately raven_io_read() and raven_io_write() will correctly deal
12
with the case of being passed an unaligned address, so we can fix the
13
missing unaligned access support by setting .impl.unaligned in the
14
MemoryRegionOps struct.
15
16
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Tested-by: Cédric Le Goater <clg@redhat.com>
19
Reviewed-by: Cédric Le Goater <clg@redhat.com>
20
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
21
---
22
hw/pci-host/raven.c | 1 +
23
1 file changed, 1 insertion(+)
24
25
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/pci-host/raven.c
28
+++ b/hw/pci-host/raven.c
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
30
.write = raven_io_write,
31
.endianness = DEVICE_LITTLE_ENDIAN,
32
.impl.max_access_size = 4,
33
+ .impl.unaligned = true,
34
.valid.unaligned = true,
35
};
36
37
--
38
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
1
Suppress the deprecation warning when we're running under qtest,
2
to avoid "make check" including warning messages in its output.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
7
---
8
hw/block/tc58128.c | 4 +++-
9
1 file changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/block/tc58128.c
14
+++ b/hw/block/tc58128.c
15
@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
16
17
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
18
{
19
- warn_report_once("The TC58128 flash device is deprecated");
20
+ if (!qtest_enabled()) {
21
+ warn_report_once("The TC58128 flash device is deprecated");
22
+ }
23
init_dev(&tc58128_devs[0], zone1);
24
init_dev(&tc58128_devs[1], zone2);
25
return sh7750_register_io_device(s, &tc58128);
26
--
27
2.34.1
28
29
diff view generated by jsdifflib
[PULL 03/26] hw/input/tsc210x: Don't abort on bad SPI word widths
[PULL 10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
1
The tsc210x doesn't support anything other than 16-bit reads on the
1
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
2
SPI bus, but the guest can program the SPI controller to attempt
2
because we already get the coverage of those tests via qtests_arm,
3
them anyway. If this happens, don't abort QEMU, just log this as
3
and we don't want to use extra CI minutes testing them twice.
4
a guest error.
5
4
6
This fixes our machine_arm_n8x0.py:N8x0Machine.test_n800
5
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
7
acceptance test, which hits this assertion.
6
that change.
8
7
9
The reason we hit the assertion is because the guest kernel thinks
8
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
10
there is a TSC2005 on this SPI bus address, not a TSC210x. (The n810
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
*does* have a TSC2005 at this address.) The TSC2005 supports the
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
24-bit accesses which the guest driver makes, and the TSC210x does
11
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
13
not (that is, our TSC210x emulation is not missing support for a word
12
---
14
width the hardware can handle). It's not clear whether the problem
13
tests/qtest/meson.build | 1 -
15
here is that the guest kernel incorrectly thinks the n800 has the
14
1 file changed, 1 deletion(-)
16
same device at this SPI bus address as the n810, or that QEMU's n810
17
board model doesn't get the SPI devices right. At this late date
18
there no longer appears to be any reliable information on the web
19
about the hardware behaviour, but I am inclined to think this is a
20
guest kernel bug. In any case, we prefer not to abort QEMU for
21
guest-triggerable conditions, so logging the error is the right thing
22
to do.
23
15
24
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/736
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
27
Message-id: 20220221140750.514557-1-peter.maydell@linaro.org
28
---
29
hw/input/tsc210x.c | 8 ++++++--
30
1 file changed, 6 insertions(+), 2 deletions(-)
31
32
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
33
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/input/tsc210x.c
18
--- a/tests/qtest/meson.build
35
+++ b/hw/input/tsc210x.c
19
+++ b/tests/qtest/meson.build
36
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
37
#include "hw/hw.h"
21
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
38
#include "audio/audio.h"
22
(config_all_accel.has_key('CONFIG_TCG') and \
39
#include "qemu/timer.h"
23
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
40
+#include "qemu/log.h"
24
- (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
41
#include "sysemu/reset.h"
25
['arm-cpu-features',
42
#include "ui/console.h"
26
'numa-test',
43
#include "hw/arm/omap.h" /* For I2SCodec */
27
'boot-serial-test',
44
@@ -XXX,XX +XXX,XX @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
45
TSC210xState *s = opaque;
46
uint32_t ret = 0;
47
48
- if (len != 16)
49
- hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len);
50
+ if (len != 16) {
51
+ qemu_log_mask(LOG_GUEST_ERROR,
52
+ "%s: bad SPI word width %i\n", __func__, len);
53
+ return 0;
54
+ }
55
56
/* TODO: sequential reads etc - how do we make sure the host doesn't
57
* unintentionally read out a conversion result from a register while
58
--
28
--
59
2.25.1
29
2.34.1
60
30
61
31
diff view generated by jsdifflib
New patch
[PULL 11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
1
Allow changes to the virt GTDT -- we are going to add the IRQ
2
entry for a new timer to it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
6
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
7
---
8
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/bios-tables-test-allowed-diff.h
14
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
15
@@ -1 +1,3 @@
16
/* List of comma-separated changed AML files to ignore */
17
+"tests/data/acpi/virt/FACP",
18
+"tests/data/acpi/virt/GTDT",
19
--
20
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
1
1
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
2
non-secure EL2 virtual timer. We implemented the timer itself in the
3
CPU model, but never wired up its IRQ line to the GIC.
4
5
Wire up the IRQ line (this is always safe whether the CPU has the
6
interrupt or not, since it always creates the outbound IRQ line).
7
Report it to the guest via dtb and ACPI if the CPU has the feature.
8
9
The DTB binding is documented in the kernel's
10
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
11
and the ACPI table entries are documented in the ACPI specification
12
version 6.3 or later.
13
14
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
15
FADT table rev to show that we might be using 6.3 features.
16
17
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
18
versions prior to edk2-stable202311, for users who use the virt board
19
with 'virtualization=on' to enable EL2 emulation and are booting an
20
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
21
that EDK2 will assert on bootup:
22
23
ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
24
25
If you see that assertion you should do one of:
26
* update your EDK2 binaries to edk2-stable202311 or newer
27
* use the 'virt-8.2' versioned machine type
28
* not use 'virtualization=on'
29
30
(The versions shipped with QEMU itself have the fix.)
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
34
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
35
---
36
include/hw/arm/virt.h | 2 ++
37
hw/arm/virt-acpi-build.c | 20 ++++++++++----
38
hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------
39
3 files changed, 67 insertions(+), 15 deletions(-)
40
41
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/virt.h
44
+++ b/include/hw/arm/virt.h
45
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
46
/* Machines < 6.2 have no support for describing cpu topology to guest */
47
bool no_cpu_topology;
48
bool no_tcg_lpa2;
49
+ bool no_ns_el2_virt_timer_irq;
50
};
51
52
struct VirtMachineState {
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
54
PCIBus *bus;
55
char *oem_id;
56
char *oem_table_id;
57
+ bool ns_el2_virt_timer_irq;
58
};
59
60
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
61
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/virt-acpi-build.c
64
+++ b/hw/arm/virt-acpi-build.c
65
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
}
67
68
/*
69
- * ACPI spec, Revision 5.1
70
- * 5.2.24 Generic Timer Description Table (GTDT)
71
+ * ACPI spec, Revision 6.5
72
+ * 5.2.25 Generic Timer Description Table (GTDT)
73
*/
74
static void
75
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
76
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
77
uint32_t irqflags = vmc->claim_edge_triggered_timers ?
78
1 : /* Interrupt is Edge triggered */
79
0; /* Interrupt is Level triggered */
80
- AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
81
+ AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
82
.oem_table_id = vms->oem_table_id };
83
84
acpi_table_begin(&table, table_data);
85
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
86
build_append_int_noprefix(table_data, 0, 4);
87
/* Platform Timer Offset */
88
build_append_int_noprefix(table_data, 0, 4);
89
-
90
+ if (vms->ns_el2_virt_timer_irq) {
91
+ /* Virtual EL2 Timer GSIV */
92
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
93
+ /* Virtual EL2 Timer Flags */
94
+ build_append_int_noprefix(table_data, irqflags, 4);
95
+ } else {
96
+ build_append_int_noprefix(table_data, 0, 4);
97
+ build_append_int_noprefix(table_data, 0, 4);
98
+ }
99
acpi_table_end(linker, &table);
100
}
101
102
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
103
static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
104
VirtMachineState *vms, unsigned dsdt_tbl_offset)
105
{
106
- /* ACPI v6.0 */
107
+ /* ACPI v6.3 */
108
AcpiFadtData fadt = {
109
.rev = 6,
110
- .minor_ver = 0,
111
+ .minor_ver = 3,
112
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
113
.xdsdt_tbl_offset = &dsdt_tbl_offset,
114
};
115
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/arm/virt.c
118
+++ b/hw/arm/virt.c
119
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
120
qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
121
}
122
123
+/*
124
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
125
+ * but we don't want to advertise it to the guest in the dtb or ACPI
126
+ * table unless it's really going to do something.
127
+ */
128
+static bool ns_el2_virt_timer_present(void)
129
+{
130
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
131
+ CPUARMState *env = &cpu->env;
132
+
133
+ return arm_feature(env, ARM_FEATURE_AARCH64) &&
134
+ arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
135
+}
136
+
137
static void create_fdt(VirtMachineState *vms)
138
{
139
MachineState *ms = MACHINE(vms);
140
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
141
"arm,armv7-timer");
142
}
143
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
144
- qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
145
- GIC_FDT_IRQ_TYPE_PPI,
146
- INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
147
- GIC_FDT_IRQ_TYPE_PPI,
148
- INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
149
- GIC_FDT_IRQ_TYPE_PPI,
150
- INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
151
- GIC_FDT_IRQ_TYPE_PPI,
152
- INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
153
+ if (vms->ns_el2_virt_timer_irq) {
154
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
155
+ GIC_FDT_IRQ_TYPE_PPI,
156
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
157
+ GIC_FDT_IRQ_TYPE_PPI,
158
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
159
+ GIC_FDT_IRQ_TYPE_PPI,
160
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
161
+ GIC_FDT_IRQ_TYPE_PPI,
162
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
163
+ GIC_FDT_IRQ_TYPE_PPI,
164
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
165
+ } else {
166
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
167
+ GIC_FDT_IRQ_TYPE_PPI,
168
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
169
+ GIC_FDT_IRQ_TYPE_PPI,
170
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
171
+ GIC_FDT_IRQ_TYPE_PPI,
172
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
173
+ GIC_FDT_IRQ_TYPE_PPI,
174
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
175
+ }
176
}
177
178
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
179
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
180
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
181
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
182
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
183
+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
184
};
185
186
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
187
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
188
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
189
object_unref(cpuobj);
190
}
191
+
192
+ /* Now we've created the CPUs we can see if they have the hypvirt timer */
193
+ vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
194
+ !vmc->no_ns_el2_virt_timer_irq;
195
+
196
fdt_add_timer_nodes(vms);
197
fdt_add_cpu_nodes(vms);
198
199
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
200
201
static void virt_machine_8_2_options(MachineClass *mc)
202
{
203
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
204
+
205
virt_machine_9_0_options(mc);
206
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
207
+ /*
208
+ * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
209
+ * earlier machines. (Exposing it tickles a bug in older EDK2
210
+ * guest BIOS binaries.)
211
+ */
212
+ vmc->no_ns_el2_virt_timer_irq = true;
213
}
214
DEFINE_VIRT_MACHINE(8, 2)
215
216
--
217
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/35] tests/qtest/bios-tables-tests: Update virt golden reference
1
1
Update the virt golden reference files to say that the FACP is ACPI
2
v6.3, and the GTDT table is a revision 3 table with space for the
3
virtual EL2 timer.
4
5
Diffs from iasl:
6
7
@@ -XXX,XX +XXX,XX @@
8
/*
9
* Intel ACPI Component Architecture
10
* AML/ASL+ Disassembler version 20200925 (64-bit version)
11
* Copyright (c) 2000 - 2020 Intel Corporation
12
*
13
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
14
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
15
*
16
* ACPI Data Table [FACP]
17
*
18
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
19
*/
20
21
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
22
[004h 0004 4] Table Length : 00000114
23
[008h 0008 1] Revision : 06
24
-[009h 0009 1] Checksum : 15
25
+[009h 0009 1] Checksum : 12
26
[00Ah 0010 6] Oem ID : "BOCHS "
27
[010h 0016 8] Oem Table ID : "BXPC "
28
[018h 0024 4] Oem Revision : 00000001
29
[01Ch 0028 4] Asl Compiler ID : "BXPC"
30
[020h 0032 4] Asl Compiler Revision : 00000001
31
32
[024h 0036 4] FACS Address : 00000000
33
[028h 0040 4] DSDT Address : 00000000
34
[02Ch 0044 1] Model : 00
35
[02Dh 0045 1] PM Profile : 00 [Unspecified]
36
[02Eh 0046 2] SCI Interrupt : 0000
37
[030h 0048 4] SMI Command Port : 00000000
38
[034h 0052 1] ACPI Enable Value : 00
39
[035h 0053 1] ACPI Disable Value : 00
40
[036h 0054 1] S4BIOS Command : 00
41
[037h 0055 1] P-State Control : 00
42
@@ -XXX,XX +XXX,XX @@
43
Use APIC Physical Destination Mode (V4) : 0
44
Hardware Reduced (V5) : 1
45
Low Power S0 Idle (V5) : 0
46
47
[074h 0116 12] Reset Register : [Generic Address Structure]
48
[074h 0116 1] Space ID : 00 [SystemMemory]
49
[075h 0117 1] Bit Width : 00
50
[076h 0118 1] Bit Offset : 00
51
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
52
[078h 0120 8] Address : 0000000000000000
53
54
[080h 0128 1] Value to cause reset : 00
55
[081h 0129 2] ARM Flags (decoded below) : 0003
56
PSCI Compliant : 1
57
Must use HVC for PSCI : 1
58
59
-[083h 0131 1] FADT Minor Revision : 00
60
+[083h 0131 1] FADT Minor Revision : 03
61
[084h 0132 8] FACS Address : 0000000000000000
62
[08Ch 0140 8] DSDT Address : 0000000000000000
63
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
64
[094h 0148 1] Space ID : 00 [SystemMemory]
65
[095h 0149 1] Bit Width : 00
66
[096h 0150 1] Bit Offset : 00
67
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
68
[098h 0152 8] Address : 0000000000000000
69
70
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
71
[0A0h 0160 1] Space ID : 00 [SystemMemory]
72
[0A1h 0161 1] Bit Width : 00
73
[0A2h 0162 1] Bit Offset : 00
74
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
75
[0A4h 0164 8] Address : 0000000000000000
76
77
@@ -XXX,XX +XXX,XX @@
78
[0F5h 0245 1] Bit Width : 00
79
[0F6h 0246 1] Bit Offset : 00
80
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
81
[0F8h 0248 8] Address : 0000000000000000
82
83
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
84
[100h 0256 1] Space ID : 00 [SystemMemory]
85
[101h 0257 1] Bit Width : 00
86
[102h 0258 1] Bit Offset : 00
87
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
88
[104h 0260 8] Address : 0000000000000000
89
90
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
91
92
Raw Table Data: Length 276 (0x114)
93
94
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
95
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
96
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
97
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
98
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
99
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
100
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
101
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
102
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
103
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
104
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
105
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
106
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
107
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
108
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
109
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
110
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
111
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
112
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
113
0110: 00 00 00 00 // ....
114
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
* Intel ACPI Component Architecture
118
* AML/ASL+ Disassembler version 20200925 (64-bit version)
119
* Copyright (c) 2000 - 2020 Intel Corporation
120
*
121
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
122
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
123
*
124
* ACPI Data Table [GTDT]
125
*
126
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
127
*/
128
129
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
130
-[004h 0004 4] Table Length : 00000060
131
-[008h 0008 1] Revision : 02
132
-[009h 0009 1] Checksum : 9C
133
+[004h 0004 4] Table Length : 00000068
134
+[008h 0008 1] Revision : 03
135
+[009h 0009 1] Checksum : 93
136
[00Ah 0010 6] Oem ID : "BOCHS "
137
[010h 0016 8] Oem Table ID : "BXPC "
138
[018h 0024 4] Oem Revision : 00000001
139
[01Ch 0028 4] Asl Compiler ID : "BXPC"
140
[020h 0032 4] Asl Compiler Revision : 00000001
141
142
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
143
[02Ch 0044 4] Reserved : 00000000
144
145
[030h 0048 4] Secure EL1 Interrupt : 0000001D
146
[034h 0052 4] EL1 Flags (decoded below) : 00000000
147
Trigger Mode : 0
148
Polarity : 0
149
Always On : 0
150
151
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
152
@@ -XXX,XX +XXX,XX @@
153
154
[040h 0064 4] Virtual Timer Interrupt : 0000001B
155
[044h 0068 4] VT Flags (decoded below) : 00000000
156
Trigger Mode : 0
157
Polarity : 0
158
Always On : 0
159
160
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
161
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
162
Trigger Mode : 0
163
Polarity : 0
164
Always On : 0
165
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
166
167
[058h 0088 4] Platform Timer Count : 00000000
168
[05Ch 0092 4] Platform Timer Offset : 00000000
169
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
170
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
171
172
-Raw Table Data: Length 96 (0x60)
173
+Raw Table Data: Length 104 (0x68)
174
175
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
176
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
177
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
178
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
179
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
180
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
181
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
182
+ 0060: 00 00 00 00 00 00 00 00 // ........
183
184
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
186
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
187
---
188
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
189
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
190
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
191
3 files changed, 2 deletions(-)
192
193
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/qtest/bios-tables-test-allowed-diff.h
196
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
197
@@ -1,3 +1 @@
198
/* List of comma-separated changed AML files to ignore */
199
-"tests/data/acpi/virt/FACP",
200
-"tests/data/acpi/virt/GTDT",
201
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
202
index XXXXXXX..XXXXXXX 100644
203
GIT binary patch
204
delta 25
205
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
206
207
delta 28
208
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
209
210
diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
211
index XXXXXXX..XXXXXXX 100644
212
GIT binary patch
213
delta 25
214
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
215
216
delta 16
217
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
218
219
--
220
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
1
The patchset adding the GMAC ethernet to this SoC crossed in the
2
mail with the patchset cleaning up the NIC handling. When we
3
create the GMAC modules we must call qemu_configure_nic_device()
4
so that the user has the opportunity to use the -nic commandline
5
option to create a network backend and connect it to the GMACs.
1
6
7
Add the missing call.
8
9
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
12
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
13
---
14
hw/arm/npcm7xx.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/npcm7xx.c
20
+++ b/hw/arm/npcm7xx.c
21
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
22
for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
23
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
24
25
+ qemu_configure_nic_device(DEVICE(sbd), false, NULL);
26
/*
27
* The device exists regardless of whether it's connected to a QEMU
28
* netdev backend. So always instantiate it even if there is no
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
1
Currently QEMU will warn if there is a NIC on the board that
2
is not connected to a backend. By default the '-nic user' will
3
get used for all NICs, but if you manually connect a specific
4
NIC to a specific backend, then the other NICs on the board
5
have no backend and will be warned about:
1
6
7
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
8
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
9
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
10
11
So suppress those warnings by manually connecting every NIC
12
on the board to some backend.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
18
---
19
tests/qtest/npcm7xx_emc-test.c | 5 ++++-
20
1 file changed, 4 insertions(+), 1 deletion(-)
21
22
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/tests/qtest/npcm7xx_emc-test.c
25
+++ b/tests/qtest/npcm7xx_emc-test.c
26
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
27
* KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
28
* in the 'model' field to specify the device to match.
29
*/
30
- g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
31
+ g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
32
+ "-nic user,model=npcm7xx-emc "
33
+ "-nic user,model=npcm-gmac "
34
+ "-nic user,model=npcm-gmac",
35
test_sockets[1], module_num);
36
37
g_test_queue_destroy(packet_test_clear, test_sockets);
38
--
39
2.34.1
diff view generated by jsdifflib
[PULL 13/26] target/arm: Use MAKE_64BIT_MASK to compute indexmask
[PULL 16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
1
From: Richard Henderson <richard.henderson@linaro.org>
1
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
2
CPU, and in fact if you try to do it we will assert:
2
3
3
The macro is a bit more readable than the inlined computation.
4
#6 0x00007ffff4b95e96 in __GI___assert_fail
5
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
6
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
7
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
8
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
4
9
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
We might call pmu_counter_enabled() on an M-profile CPU (for example
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
from the migration pre/post hooks in machine.c); this should always
7
Message-id: 20220301215958.157011-7-richard.henderson@linaro.org
12
return false because these CPUs don't set ARM_FEATURE_PMU.
13
14
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
15
have done the early return for "PMU not present".
16
17
This fixes an assertion failure if you try to do a loadvm or
18
savevm for an M-profile board.
19
20
Cc: qemu-stable@nongnu.org
21
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
9
---
26
---
10
target/arm/helper.c | 4 ++--
27
target/arm/helper.c | 12 ++++++++++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
28
1 file changed, 10 insertions(+), 2 deletions(-)
12
29
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
32
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
33
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
34
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
18
level = startlevel;
35
bool enabled, prohibited = false, filtered;
36
bool secure = arm_is_secure(env);
37
int el = arm_current_el(env);
38
- uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
39
- uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
40
+ uint64_t mdcr_el2;
41
+ uint8_t hpmn;
42
43
+ /*
44
+ * We might be called for M-profile cores where MDCR_EL2 doesn't
45
+ * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
46
+ * must be before we read that value.
47
+ */
48
if (!arm_feature(env, ARM_FEATURE_PMU)) {
49
return false;
19
}
50
}
20
51
21
- indexmask_grainsize = (1ULL << (stride + 3)) - 1;
52
+ mdcr_el2 = arm_mdcr_el2_eff(env);
22
- indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
53
+ hpmn = mdcr_el2 & MDCR_HPMN;
23
+ indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3);
54
+
24
+ indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level)));
55
if (!arm_feature(env, ARM_FEATURE_EL2) ||
25
56
(counter < hpmn || counter == 31)) {
26
/* Now we can extract the actual base address from the TTBR */
57
e = env->cp15.c9_pmcr & PMCRE;
27
descaddr = extract64(ttbr, 0, 48);
28
--
58
--
29
2.25.1
59
2.34.1
30
60
31
61
diff view generated by jsdifflib
[PULL 09/26] target/arm: Set TCR_EL1.TSZ for user-only
[PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Nabih Estefan <nabihestefan@google.com>
2
2
3
Set this as the kernel would, to 48 bits, to keep the computation
3
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
4
of the address space correct for PAuth.
4
of 8xx. Also fix comments referencing this and values expecting 8xx.
5
5
6
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
7
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
[PMM: commit message tweaks]
8
Message-id: 20220301215958.157011-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/cpu.c | 3 ++-
14
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
12
1 file changed, 2 insertions(+), 1 deletion(-)
15
tests/qtest/meson.build | 3 +-
16
2 files changed, 4 insertions(+), 83 deletions(-)
13
17
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
20
--- a/tests/qtest/npcm_gmac-test.c
17
+++ b/target/arm/cpu.c
21
+++ b/tests/qtest/npcm_gmac-test.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
22
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
19
aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
23
const GMACModule *module;
20
}
24
} TestData;
21
/*
25
22
+ * Enable 48-bit address space (TODO: take reserved_va into account).
26
-/* Values extracted from hw/arm/npcm8xx.c */
23
* Enable TBI0 but not TBI1.
27
+/* Values extracted from hw/arm/npcm7xx.c */
24
* Note that this must match useronly_clean_ptr.
28
static const GMACModule gmac_module_list[] = {
25
*/
29
{
26
- env->cp15.tcr_el[1].raw_tcr = (1ULL << 37);
30
.irq = 14,
27
+ env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37);
31
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
28
32
.irq = 15,
29
/* Enable MTE */
33
.base_addr = 0xf0804000
30
if (cpu_isar_feature(aa64_mte, cpu)) {
34
},
35
- {
36
- .irq = 16,
37
- .base_addr = 0xf0806000
38
- },
39
- {
40
- .irq = 17,
41
- .base_addr = 0xf0808000
42
- }
43
};
44
45
/* Returns the index of the GMAC module. */
46
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
47
return qtest_readl(qts, mod->base_addr + regno);
48
}
49
50
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
51
- NPCMRegister regno)
52
-{
53
- uint32_t write_value = (regno & 0x3ffe00) >> 9;
54
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
55
- uint32_t read_offset = regno & 0x1ff;
56
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
57
-}
58
-
59
/* Check that GMAC registers are reset to default value */
60
static void test_init(gconstpointer test_data)
61
{
62
const TestData *td = test_data;
63
const GMACModule *mod = td->module;
64
- QTestState *qts = qtest_init("-machine npcm845-evb");
65
+ QTestState *qts = qtest_init("-machine npcm750-evb");
66
67
#define CHECK_REG32(regno, value) \
68
do { \
69
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
70
} while (0)
71
72
-#define CHECK_REG_PCS(regno, value) \
73
- do { \
74
- g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
75
- } while (0)
76
-
77
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
78
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
79
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
80
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
81
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
82
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
83
84
- /* TODO Add registers PCS */
85
- if (mod->base_addr == 0xf0802000) {
86
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
87
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
88
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
89
-
90
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
91
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
92
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
93
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
94
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
95
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
96
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
97
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
98
-
99
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
100
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
101
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
102
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
103
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
104
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
105
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
106
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
107
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
108
-
109
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
110
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
111
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
112
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
113
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
114
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
115
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
116
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
117
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
118
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
119
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
120
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
121
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
122
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
123
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
124
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
125
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
126
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
127
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
128
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
129
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
130
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
131
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
132
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
133
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
134
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
135
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
136
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
137
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
138
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
139
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
140
- }
141
-
142
qtest_quit(qts);
143
}
144
145
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
146
index XXXXXXX..XXXXXXX 100644
147
--- a/tests/qtest/meson.build
148
+++ b/tests/qtest/meson.build
149
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
150
'npcm7xx_sdhci-test',
151
'npcm7xx_smbus-test',
152
'npcm7xx_timer-test',
153
- 'npcm7xx_watchdog_timer-test'] + \
154
+ 'npcm7xx_watchdog_timer-test',
155
+ 'npcm_gmac-test'] + \
156
(slirp.found() ? ['npcm7xx_emc-test'] : [])
157
qtests_aspeed = \
158
['aspeed_hace-test',
31
--
159
--
32
2.25.1
160
2.34.1
diff view generated by jsdifflib
[PULL 10/26] target/arm: Fault on invalid TCR_ELx.TxSZ
[PULL 18/35] hw/arm/smmuv3: add support for stage 1 access fault
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Luc Michel <luc.michel@amd.com>
2
2
3
Without FEAT_LVA, the behaviour of programming an invalid value
3
An access fault is raised when the Access Flag is not set in the
4
is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid
4
looked-up PTE and the AFFD field is not set in the corresponding context
5
minimum value requires a Translation fault.
5
descriptor. This was already implemented for stage 2. Implement it for
6
stage 1 as well.
6
7
7
It is most self-consistent to choose to generate the fault always.
8
Signed-off-by: Luc Michel <luc.michel@amd.com>
8
9
Reviewed-by: Mostafa Saleh <smostafa@google.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Mostafa Saleh <smostafa@google.com>
11
Message-id: 20220301215958.157011-4-richard.henderson@linaro.org
12
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
13
[PMM: tweaked comment text]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
15
---
14
target/arm/internals.h | 1 +
16
hw/arm/smmuv3-internal.h | 1 +
15
target/arm/helper.c | 32 ++++++++++++++++++++++++++++----
17
include/hw/arm/smmu-common.h | 1 +
16
2 files changed, 29 insertions(+), 4 deletions(-)
18
hw/arm/smmu-common.c | 11 +++++++++++
19
hw/arm/smmuv3.c | 1 +
20
4 files changed, 14 insertions(+)
17
21
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
22
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
19
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
24
--- a/hw/arm/smmuv3-internal.h
21
+++ b/target/arm/internals.h
25
+++ b/hw/arm/smmuv3-internal.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
26
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
23
bool hpd : 1;
27
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
24
bool using16k : 1;
28
#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
25
bool using64k : 1;
29
#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
26
+ bool tsz_oob : 1; /* tsz has been clamped to legal range */
30
+#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
27
} ARMVAParameters;
31
#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
28
32
#define CD_HD(x) extract32((x)->word[1], 10 , 1)
29
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
33
#define CD_HA(x) extract32((x)->word[1], 11 , 1)
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
34
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
31
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
36
--- a/include/hw/arm/smmu-common.h
33
+++ b/target/arm/helper.c
37
+++ b/include/hw/arm/smmu-common.h
34
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
35
ARMMMUIdx mmu_idx, bool data)
39
bool disabled; /* smmu is disabled */
36
{
40
bool bypassed; /* translation is bypassed */
37
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
41
bool aborted; /* translation is aborted */
38
- bool epd, hpd, using16k, using64k;
42
+ bool affd; /* AF fault disable */
39
- int select, tsz, tbi, max_tsz;
43
uint32_t iotlb_hits; /* counts IOTLB hits */
40
+ bool epd, hpd, using16k, using64k, tsz_oob;
44
uint32_t iotlb_misses; /* counts IOTLB misses*/
41
+ int select, tsz, tbi, max_tsz, min_tsz;
45
/* Used by stage-1 only. */
42
46
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
43
if (!regime_has_2_ranges(mmu_idx)) {
47
index XXXXXXX..XXXXXXX 100644
44
select = 0;
48
--- a/hw/arm/smmu-common.c
45
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
49
+++ b/hw/arm/smmu-common.c
46
} else {
50
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
47
max_tsz = 39;
51
pte_addr, pte, iova, gpa,
48
}
52
block_size >> 20);
49
+ min_tsz = 16; /* TODO: ARMv8.2-LVA */
53
}
50
51
- tsz = MIN(tsz, max_tsz);
52
- tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
53
+ if (tsz > max_tsz) {
54
+ tsz = max_tsz;
55
+ tsz_oob = true;
56
+ } else if (tsz < min_tsz) {
57
+ tsz = min_tsz;
58
+ tsz_oob = true;
59
+ } else {
60
+ tsz_oob = false;
61
+ }
62
63
/* Present TBI as a composite with TBID. */
64
tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
65
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
66
.hpd = hpd,
67
.using16k = using16k,
68
.using64k = using64k,
69
+ .tsz_oob = tsz_oob,
70
};
71
}
72
73
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
74
param = aa64_va_parameters(env, address, mmu_idx,
75
access_type != MMU_INST_FETCH);
76
level = 0;
77
+
54
+
78
+ /*
55
+ /*
79
+ * If TxSZ is programmed to a value larger than the maximum,
56
+ * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
80
+ * or smaller than the effective minimum, it is IMPLEMENTATION
57
+ * are 0 we take an Access flag fault. (5.4. Context Descriptor)
81
+ * DEFINED whether we behave as if the field were programmed
58
+ * An Access flag fault takes priority over a Permission fault.
82
+ * within bounds, or if a level 0 Translation fault is generated.
83
+ *
84
+ * With FEAT_LVA, fault on less than minimum becomes required,
85
+ * so our choice is to always raise the fault.
86
+ */
59
+ */
87
+ if (param.tsz_oob) {
60
+ if (!PTE_AF(pte) && !cfg->affd) {
88
+ fault_type = ARMFault_Translation;
61
+ info->type = SMMU_PTW_ERR_ACCESS;
89
+ goto do_fault;
62
+ goto error;
90
+ }
63
+ }
91
+
64
+
92
addrsize = 64 - 8 * param.tbi;
65
ap = PTE_AP(pte);
93
inputsize = 64 - param.tsz;
66
if (is_permission_fault(ap, perm)) {
94
} else {
67
info->type = SMMU_PTW_ERR_PERMISSION;
68
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/smmuv3.c
71
+++ b/hw/arm/smmuv3.c
72
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
73
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
74
cfg->tbi = CD_TBI(cd);
75
cfg->asid = CD_ASID(cd);
76
+ cfg->affd = CD_AFFD(cd);
77
78
trace_smmuv3_decode_cd(cfg->oas);
79
95
--
80
--
96
2.25.1
81
2.34.1
diff view generated by jsdifflib
[PULL 05/26] target/arm: Support PSCI 1.1 and SMCCC 1.0
[PULL 19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
1
From: Akihiko Odaki <akihiko.odaki@gmail.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Support the latest PSCI on TCG and HVF. A 64-bit function called from
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
AArch32 now returns NOT_SUPPORTED, which is necessary to adhere to SMC
5
Calling Convention 1.0. It is still not compliant with SMCCC 1.3 since
6
they do not implement mandatory functions.
7
8
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
9
Message-id: 20220213035753.34577-1-akihiko.odaki@gmail.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: update MISMATCH_CHECK checks on PSCI_VERSION macros to match]
5
Message-id: 20240213155214.13619-2-philmd@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
7
---
14
target/arm/kvm-consts.h | 13 +++++++++----
8
hw/arm/stellaris.c | 6 ++++--
15
hw/arm/boot.c | 12 +++++++++---
9
1 file changed, 4 insertions(+), 2 deletions(-)
16
target/arm/cpu.c | 5 +++--
17
target/arm/hvf/hvf.c | 27 ++++++++++++++++++++++++++-
18
target/arm/kvm64.c | 2 +-
19
target/arm/psci.c | 35 ++++++++++++++++++++++++++++++++---
20
6 files changed, 80 insertions(+), 14 deletions(-)
21
10
22
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
23
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/kvm-consts.h
13
--- a/hw/arm/stellaris.c
25
+++ b/target/arm/kvm-consts.h
14
+++ b/hw/arm/stellaris.c
26
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE);
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
27
#define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4)
28
#define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5)
29
30
+#define QEMU_PSCI_1_0_FN_PSCI_FEATURES QEMU_PSCI_0_2_FN(10)
31
+
32
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND);
33
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF);
34
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON);
35
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE);
36
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND);
37
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON);
38
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE);
39
+MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES);
40
41
/* PSCI v0.2 return values used by TCG emulation of PSCI */
42
43
/* No Trusted OS migration to worry about when offlining CPUs */
44
#define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2
45
46
-/* We implement version 0.2 only */
47
-#define QEMU_PSCI_0_2_RET_VERSION_0_2 2
48
+#define QEMU_PSCI_VERSION_0_1 0x00001
49
+#define QEMU_PSCI_VERSION_0_2 0x00002
50
+#define QEMU_PSCI_VERSION_1_1 0x10001
51
52
MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
53
-MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2,
54
- (PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2)));
55
+/* We don't bother to check every possible version value */
56
+MISMATCH_CHECK(QEMU_PSCI_VERSION_0_2, PSCI_VERSION(0, 2));
57
+MISMATCH_CHECK(QEMU_PSCI_VERSION_1_1, PSCI_VERSION(1, 1));
58
59
/* PSCI return values (inclusive of all PSCI versions) */
60
#define QEMU_PSCI_RET_SUCCESS 0
61
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/boot.c
64
+++ b/hw/arm/boot.c
65
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
66
}
67
68
qemu_fdt_add_subnode(fdt, "/psci");
69
- if (armcpu->psci_version == 2) {
70
- const char comp[] = "arm,psci-0.2\0arm,psci";
71
- qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
72
+ if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 ||
73
+ armcpu->psci_version == QEMU_PSCI_VERSION_1_1) {
74
+ if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) {
75
+ const char comp[] = "arm,psci-0.2\0arm,psci";
76
+ qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
77
+ } else {
78
+ const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci";
79
+ qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
80
+ }
81
82
cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
83
if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
84
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/target/arm/cpu.c
87
+++ b/target/arm/cpu.c
88
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
89
* picky DTB consumer will also provide a helpful error message.
90
*/
91
cpu->dtb_compatible = "qemu,unknown";
92
- cpu->psci_version = 1; /* By default assume PSCI v0.1 */
93
+ cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */
94
cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
95
96
if (tcg_enabled() || hvf_enabled()) {
97
- cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */
98
+ /* TCG and HVF implement PSCI 1.1 */
99
+ cpu->psci_version = QEMU_PSCI_VERSION_1_1;
100
}
16
}
101
}
17
}
102
18
103
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
19
-static void stellaris_adc_reset(StellarisADCState *s)
104
index XXXXXXX..XXXXXXX 100644
20
+static void stellaris_adc_reset_hold(Object *obj)
105
--- a/target/arm/hvf/hvf.c
106
+++ b/target/arm/hvf/hvf.c
107
@@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu)
108
109
switch (param[0]) {
110
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
111
- ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
112
+ ret = QEMU_PSCI_VERSION_1_1;
113
break;
114
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
115
ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
116
@@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu)
117
case QEMU_PSCI_0_2_FN_MIGRATE:
118
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
119
break;
120
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
121
+ switch (param[1]) {
122
+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
123
+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
124
+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
125
+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
126
+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
127
+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
128
+ case QEMU_PSCI_0_1_FN_CPU_ON:
129
+ case QEMU_PSCI_0_2_FN_CPU_ON:
130
+ case QEMU_PSCI_0_2_FN64_CPU_ON:
131
+ case QEMU_PSCI_0_1_FN_CPU_OFF:
132
+ case QEMU_PSCI_0_2_FN_CPU_OFF:
133
+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
134
+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
135
+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
136
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
137
+ ret = 0;
138
+ break;
139
+ case QEMU_PSCI_0_1_FN_MIGRATE:
140
+ case QEMU_PSCI_0_2_FN_MIGRATE:
141
+ default:
142
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
143
+ }
144
+ break;
145
default:
146
return false;
147
}
148
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
149
index XXXXXXX..XXXXXXX 100644
150
--- a/target/arm/kvm64.c
151
+++ b/target/arm/kvm64.c
152
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
153
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
154
}
155
if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
156
- cpu->psci_version = 2;
157
+ cpu->psci_version = QEMU_PSCI_VERSION_0_2;
158
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
159
}
160
if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
161
diff --git a/target/arm/psci.c b/target/arm/psci.c
162
index XXXXXXX..XXXXXXX 100644
163
--- a/target/arm/psci.c
164
+++ b/target/arm/psci.c
165
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
166
{
21
{
167
/*
22
+ StellarisADCState *s = STELLARIS_ADC(obj);
168
* This function partially implements the logic for dispatching Power State
23
int n;
169
- * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b),
24
170
+ * Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b),
25
for (n = 0; n < 4; n++) {
171
* to the extent required for bringing up and taking down secondary cores,
26
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
172
* and for handling reset and poweroff requests.
27
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
173
* Additional information about the calling convention used is available in
28
"adc", 0x1000);
174
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
29
sysbus_init_mmio(sbd, &s->iomem);
175
}
30
- stellaris_adc_reset(s);
176
31
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
177
if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
32
}
178
- ret = QEMU_PSCI_RET_INVALID_PARAMS;
33
179
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
34
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
180
goto err;
35
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
181
}
36
{
182
37
DeviceClass *dc = DEVICE_CLASS(klass);
183
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
38
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
184
ARMCPU *target_cpu;
39
185
40
+ rc->phases.hold = stellaris_adc_reset_hold;
186
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
41
dc->vmsd = &vmstate_stellaris_adc;
187
- ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
42
}
188
+ ret = QEMU_PSCI_VERSION_1_1;
43
189
break;
190
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
191
ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
192
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
193
}
194
helper_wfi(env, 4);
195
break;
196
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
197
+ switch (param[1]) {
198
+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
199
+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
200
+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
201
+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
202
+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
203
+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
204
+ case QEMU_PSCI_0_1_FN_CPU_ON:
205
+ case QEMU_PSCI_0_2_FN_CPU_ON:
206
+ case QEMU_PSCI_0_2_FN64_CPU_ON:
207
+ case QEMU_PSCI_0_1_FN_CPU_OFF:
208
+ case QEMU_PSCI_0_2_FN_CPU_OFF:
209
+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
210
+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
211
+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
212
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
213
+ if (!(param[1] & QEMU_PSCI_0_2_64BIT) || is_a64(env)) {
214
+ ret = 0;
215
+ break;
216
+ }
217
+ /* fallthrough */
218
+ case QEMU_PSCI_0_1_FN_MIGRATE:
219
+ case QEMU_PSCI_0_2_FN_MIGRATE:
220
+ default:
221
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
222
+ break;
223
+ }
224
+ break;
225
case QEMU_PSCI_0_1_FN_MIGRATE:
226
case QEMU_PSCI_0_2_FN_MIGRATE:
227
default:
228
--
44
--
229
2.25.1
45
2.34.1
46
47
diff view generated by jsdifflib
[PULL 04/26] hw/i2c: flatten pca954x mux device
[PULL 20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
1
From: Patrick Venture <venture@google.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Previously this device created N subdevices which each owned an i2c bus.
3
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
4
Now this device simply owns the N i2c busses directly.
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
5
Message-id: 20240213155214.13619-3-philmd@linaro.org
6
Tested: Verified devices behind mux are still accessible via qmp and i2c
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
from within an arm32 SoC.
8
9
Reviewed-by: Hao Wu <wuhaotsh@google.com>
10
Signed-off-by: Patrick Venture <venture@google.com>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20220202164533.1283668-1-venture@google.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
8
---
16
hw/i2c/i2c_mux_pca954x.c | 77 +++++++---------------------------------
9
hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
17
1 file changed, 13 insertions(+), 64 deletions(-)
10
1 file changed, 22 insertions(+), 4 deletions(-)
18
11
19
diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
20
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/i2c/i2c_mux_pca954x.c
14
--- a/hw/arm/stellaris.c
22
+++ b/hw/i2c/i2c_mux_pca954x.c
15
+++ b/hw/arm/stellaris.c
23
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
24
#define PCA9548_CHANNEL_COUNT 8
17
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
25
#define PCA9546_CHANNEL_COUNT 4
26
27
-/*
28
- * struct Pca954xChannel - The i2c mux device will have N of these states
29
- * that own the i2c channel bus.
30
- * @bus: The owned channel bus.
31
- * @enabled: Is this channel active?
32
- */
33
-typedef struct Pca954xChannel {
34
- SysBusDevice parent;
35
-
36
- I2CBus *bus;
37
-
38
- bool enabled;
39
-} Pca954xChannel;
40
-
41
-#define TYPE_PCA954X_CHANNEL "pca954x-channel"
42
-#define PCA954X_CHANNEL(obj) \
43
- OBJECT_CHECK(Pca954xChannel, (obj), TYPE_PCA954X_CHANNEL)
44
-
45
/*
46
* struct Pca954xState - The pca954x state object.
47
* @control: The value written to the mux control.
48
@@ -XXX,XX +XXX,XX @@ typedef struct Pca954xState {
49
50
uint8_t control;
51
52
- /* The channel i2c buses. */
53
- Pca954xChannel channel[PCA9548_CHANNEL_COUNT];
54
+ bool enabled[PCA9548_CHANNEL_COUNT];
55
+ I2CBus *bus[PCA9548_CHANNEL_COUNT];
56
} Pca954xState;
57
58
/*
59
@@ -XXX,XX +XXX,XX @@ static bool pca954x_match(I2CSlave *candidate, uint8_t address,
60
}
61
62
for (i = 0; i < mc->nchans; i++) {
63
- if (!mux->channel[i].enabled) {
64
+ if (!mux->enabled[i]) {
65
continue;
66
}
67
68
- if (i2c_scan_bus(mux->channel[i].bus, address, broadcast,
69
+ if (i2c_scan_bus(mux->bus[i], address, broadcast,
70
current_devs)) {
71
if (!broadcast) {
72
return true;
73
@@ -XXX,XX +XXX,XX @@ static void pca954x_enable_channel(Pca954xState *s, uint8_t enable_mask)
74
*/
75
for (i = 0; i < mc->nchans; i++) {
76
if (enable_mask & (1 << i)) {
77
- s->channel[i].enabled = true;
78
+ s->enabled[i] = true;
79
} else {
80
- s->channel[i].enabled = false;
81
+ s->enabled[i] = false;
82
}
83
}
84
}
18
}
85
@@ -XXX,XX +XXX,XX @@ I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel)
19
86
Pca954xState *pca954x = PCA954X(mux);
20
-/* I2C controller. */
87
21
+/*
88
g_assert(channel < pc->nchans);
22
+ * I2C controller.
89
- return I2C_BUS(qdev_get_child_bus(DEVICE(&pca954x->channel[channel]),
23
+ * ??? For now we only implement the master interface.
90
- "i2c-bus"));
24
+ */
91
-}
25
92
-
26
#define TYPE_STELLARIS_I2C "stellaris-i2c"
93
-static void pca954x_channel_init(Object *obj)
27
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
94
-{
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
95
- Pca954xChannel *s = PCA954X_CHANNEL(obj);
29
stellaris_i2c_update(s);
96
- s->bus = i2c_init_bus(DEVICE(s), "i2c-bus");
97
-
98
- /* Start all channels as disabled. */
99
- s->enabled = false;
100
-}
101
-
102
-static void pca954x_channel_class_init(ObjectClass *klass, void *data)
103
-{
104
- DeviceClass *dc = DEVICE_CLASS(klass);
105
- dc->desc = "Pca954x Channel";
106
+ return pca954x->bus[channel];
107
}
30
}
108
31
109
static void pca9546_class_init(ObjectClass *klass, void *data)
32
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
110
@@ -XXX,XX +XXX,XX @@ static void pca9548_class_init(ObjectClass *klass, void *data)
33
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
111
s->nchans = PCA9548_CHANNEL_COUNT;
34
{
35
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
36
+
37
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
38
i2c_end_transfer(s->bus);
39
+}
40
+
41
+static void stellaris_i2c_reset_hold(Object *obj)
42
+{
43
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
44
45
s->msa = 0;
46
s->mcs = 0;
47
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
48
s->mimr = 0;
49
s->mris = 0;
50
s->mcr = 0;
51
+}
52
+
53
+static void stellaris_i2c_reset_exit(Object *obj)
54
+{
55
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
56
+
57
stellaris_i2c_update(s);
112
}
58
}
113
59
114
-static void pca954x_realize(DeviceState *dev, Error **errp)
60
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
115
-{
61
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
116
- Pca954xState *s = PCA954X(dev);
62
"i2c", 0x1000);
117
- Pca954xClass *c = PCA954X_GET_CLASS(s);
63
sysbus_init_mmio(sbd, &s->iomem);
118
- int i;
64
- /* ??? For now we only implement the master interface. */
119
-
65
- stellaris_i2c_reset(s);
120
- /* SMBus modules. Cannot fail. */
66
}
121
- for (i = 0; i < c->nchans; i++) {
67
122
- sysbus_realize(SYS_BUS_DEVICE(&s->channel[i]), &error_abort);
68
/* Analogue to Digital Converter. This is only partially implemented,
123
- }
69
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
124
-}
70
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
125
-
126
static void pca954x_init(Object *obj)
127
{
71
{
128
Pca954xState *s = PCA954X(obj);
72
DeviceClass *dc = DEVICE_CLASS(klass);
129
Pca954xClass *c = PCA954X_GET_CLASS(obj);
73
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
130
int i;
74
131
75
+ rc->phases.enter = stellaris_i2c_reset_enter;
132
- /* Only initialize the children we expect. */
76
+ rc->phases.hold = stellaris_i2c_reset_hold;
133
+ /* SMBus modules. Cannot fail. */
77
+ rc->phases.exit = stellaris_i2c_reset_exit;
134
for (i = 0; i < c->nchans; i++) {
78
dc->vmsd = &vmstate_stellaris_i2c;
135
- object_initialize_child(obj, "channel[*]", &s->channel[i],
136
- TYPE_PCA954X_CHANNEL);
137
+ g_autofree gchar *bus_name = g_strdup_printf("i2c.%d", i);
138
+
139
+ /* start all channels as disabled. */
140
+ s->enabled[i] = false;
141
+ s->bus[i] = i2c_init_bus(DEVICE(s), bus_name);
142
}
143
}
79
}
144
80
145
@@ -XXX,XX +XXX,XX @@ static void pca954x_class_init(ObjectClass *klass, void *data)
146
rc->phases.enter = pca954x_enter_reset;
147
148
dc->desc = "Pca954x i2c-mux";
149
- dc->realize = pca954x_realize;
150
151
k->write_data = pca954x_write_data;
152
k->receive_byte = pca954x_read_byte;
153
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pca954x_info[] = {
154
.parent = TYPE_PCA954X,
155
.class_init = pca9548_class_init,
156
},
157
- {
158
- .name = TYPE_PCA954X_CHANNEL,
159
- .parent = TYPE_SYS_BUS_DEVICE,
160
- .class_init = pca954x_channel_class_init,
161
- .instance_size = sizeof(Pca954xChannel),
162
- .instance_init = pca954x_channel_init,
163
- }
164
};
165
166
DEFINE_TYPES(pca954x_info)
167
--
81
--
168
2.25.1
82
2.34.1
169
83
170
84
diff view generated by jsdifflib
[PULL 01/26] mps3-an547: Add missing user ahb interfaces
[PULL 21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
1
From: Jimmy Brisson <jimmy.brisson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
With these interfaces missing, TFM would delegate peripherals 0, 1,
3
QDev objects created with qdev_new() need to manually add
4
2, 3 and 8, and qemu would ignore the delegation of interface 8, as
4
their parent relationship with object_property_add_child().
5
it thought interface 4 was eth & USB.
6
5
7
This patch corrects this behavior and allows TFM to delegate the
6
This commit plug the devices which aren't part of the SoC;
8
eth & USB peripheral to NS mode.
7
they will be plugged into a SoC container in the next one.
9
8
10
(The old QEMU behaviour was based on revision B of the AN547
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
appnote; revision C corrects this error in the documentation,
12
and this commit brings QEMU in to line with how the FPGA
13
image really behaves.)
14
15
Signed-off-by: Jimmy Brisson <jimmy.brisson@linaro.org>
16
Message-id: 20220210210227.3203883-1-jimmy.brisson@linaro.org
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
[PMM: added commit message note clarifying that the old behaviour
11
Message-id: 20240213155214.13619-4-philmd@linaro.org
19
was a docs issue, not because there were two different versions
20
of the FPGA image]
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
13
---
23
hw/arm/mps2-tz.c | 4 ++++
14
hw/arm/stellaris.c | 4 ++++
24
1 file changed, 4 insertions(+)
15
1 file changed, 4 insertions(+)
25
16
26
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
17
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
27
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/mps2-tz.c
19
--- a/hw/arm/stellaris.c
29
+++ b/hw/arm/mps2-tz.c
20
+++ b/hw/arm/stellaris.c
30
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
21
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
31
{ "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
22
&error_fatal);
32
{ "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
23
33
{ "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
24
ssddev = qdev_new("ssd0323");
34
+ { /* port 4 USER AHB interface 0 */ },
25
+ object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
35
+ { /* port 5 USER AHB interface 1 */ },
26
qdev_prop_set_uint8(ssddev, "cs", 1);
36
+ { /* port 6 USER AHB interface 2 */ },
27
qdev_realize_and_unref(ssddev, bus, &error_fatal);
37
+ { /* port 7 USER AHB interface 3 */ },
28
38
{ "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } },
29
gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
39
},
30
+ object_property_add_child(OBJECT(ms), "splitter",
40
},
31
+ OBJECT(gpio_d_splitter));
32
qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
33
qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
34
qdev_connect_gpio_out(
35
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
36
DeviceState *gpad;
37
38
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
39
+ object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
40
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
41
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
42
}
41
--
43
--
42
2.25.1
44
2.34.1
45
46
diff view generated by jsdifflib
[PULL 08/26] hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
[PULL 22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Add new macros to manipulate signed fields within the register.
3
QDev objects created with qdev_new() need to manually add
4
their parent relationship with object_property_add_child().
4
5
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Since we don't model the SoC, just use a QOM container.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
7
Message-id: 20220301215958.157011-2-richard.henderson@linaro.org
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20240213155214.13619-5-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
include/hw/registerfields.h | 48 ++++++++++++++++++++++++++++++++++++-
13
hw/arm/stellaris.c | 11 ++++++++++-
13
1 file changed, 47 insertions(+), 1 deletion(-)
14
1 file changed, 10 insertions(+), 1 deletion(-)
14
15
15
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
16
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/registerfields.h
18
--- a/hw/arm/stellaris.c
18
+++ b/include/hw/registerfields.h
19
+++ b/hw/arm/stellaris.c
19
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
20
extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
21
* 400fe000 system control
21
R_ ## reg ## _ ## field ## _LENGTH)
22
*/
22
23
23
+#define FIELD_SEX8(storage, reg, field) \
24
+ Object *soc_container;
24
+ sextract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
25
DeviceState *gpio_dev[7], *nvic;
25
+ R_ ## reg ## _ ## field ## _LENGTH)
26
qemu_irq gpio_in[7][8];
26
+#define FIELD_SEX16(storage, reg, field) \
27
qemu_irq gpio_out[7][8];
27
+ sextract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
28
+ R_ ## reg ## _ ## field ## _LENGTH)
29
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
29
+#define FIELD_SEX32(storage, reg, field) \
30
sram_size = ((board->dc0 >> 18) + 1) * 1024;
30
+ sextract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
31
31
+ R_ ## reg ## _ ## field ## _LENGTH)
32
+ soc_container = object_new("container");
32
+#define FIELD_SEX64(storage, reg, field) \
33
+ object_property_add_child(OBJECT(ms), "soc", soc_container);
33
+ sextract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
34
+ R_ ## reg ## _ ## field ## _LENGTH)
35
+
34
+
36
/* Extract a field from an array of registers */
35
/* Flash programming is done via the SCU, so pretend it is ROM. */
37
#define ARRAY_FIELD_EX32(regs, reg, field) \
36
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
38
FIELD_EX32((regs)[R_ ## reg], reg, field)
37
&error_fatal);
39
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
40
_d; })
39
* need its sysclk output.
41
#define FIELD_DP64(storage, reg, field, val) ({ \
40
*/
42
struct { \
41
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
43
- uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
42
+ object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
44
+ uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
43
45
+ } _v = { .v = val }; \
44
/*
46
+ uint64_t _d; \
45
* Most devices come preprogrammed with a MAC address in the user data.
47
+ _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
48
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
47
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
49
+ _d; })
48
50
+
49
nvic = qdev_new(TYPE_ARMV7M);
51
+#define FIELD_SDP8(storage, reg, field, val) ({ \
50
+ object_property_add_child(soc_container, "v7m", OBJECT(nvic));
52
+ struct { \
51
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
53
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
52
qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
54
+ } _v = { .v = val }; \
53
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
55
+ uint8_t _d; \
54
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
56
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
55
57
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
56
dev = qdev_new(TYPE_STELLARIS_GPTM);
58
+ _d; })
57
sbd = SYS_BUS_DEVICE(dev);
59
+#define FIELD_SDP16(storage, reg, field, val) ({ \
58
+ object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
60
+ struct { \
59
qdev_connect_clock_in(dev, "clk",
61
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
60
qdev_get_clock_out(ssys_dev, "SYSCLK"));
62
+ } _v = { .v = val }; \
61
sysbus_realize_and_unref(sbd, &error_fatal);
63
+ uint16_t _d; \
62
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
64
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
63
65
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
64
if (board->dc1 & (1 << 3)) { /* watchdog present */
66
+ _d; })
65
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
67
+#define FIELD_SDP32(storage, reg, field, val) ({ \
66
-
68
+ struct { \
67
+ object_property_add_child(soc_container, "wdg", OBJECT(dev));
69
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
68
qdev_connect_clock_in(dev, "WDOGCLK",
70
+ } _v = { .v = val }; \
69
qdev_get_clock_out(ssys_dev, "SYSCLK"));
71
+ uint32_t _d; \
70
72
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
71
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
73
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
72
SysBusDevice *sbd;
74
+ _d; })
73
75
+#define FIELD_SDP64(storage, reg, field, val) ({ \
74
dev = qdev_new("pl011_luminary");
76
+ struct { \
75
+ object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
77
+ int64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
76
sbd = SYS_BUS_DEVICE(dev);
78
} _v = { .v = val }; \
77
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
79
uint64_t _d; \
78
sysbus_realize_and_unref(sbd, &error_fatal);
80
_d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
DeviceState *enet;
81
82
enet = qdev_new("stellaris_enet");
83
+ object_property_add_child(soc_container, "enet", OBJECT(enet));
84
if (nd) {
85
qdev_set_nic_properties(enet, nd);
86
} else {
81
--
87
--
82
2.25.1
88
2.34.1
83
89
84
90
diff view generated by jsdifflib
[PULL 20/26] target/arm: Fix TLBIRange.base for 16k and 64k pages
[PULL 23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
1
From: Richard Henderson <richard.henderson@linaro.org>
1
We support two different encodings for the AArch32 IMPDEF
2
CBAR register -- older cores like the Cortex A9, A7, A15
3
have this at 4, c15, c0, 0; newer cores like the
4
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
2
5
3
The shift of the BaseADDR field depends on the translation
6
When we implemented this we picked which encoding to
4
granule in use.
7
use based on whether the CPU set ARM_FEATURE_AARCH64.
8
However this isn't right for three cases:
9
* the qemu-system-arm 'max' CPU, which is supposed to be
10
a variant on a Cortex-A57; it ought to use the same
11
encoding the A57 does and which the AArch64 'max'
12
exposes to AArch32 guest code
13
* the Cortex-R52, which is AArch32-only but has the CBAR
14
at the newer encoding (and where we incorrectly are
15
not yet setting ARM_FEATURE_CBAR_RO anyway)
16
* any possible future support for other v8 AArch32
17
only CPUs, or for supporting "boot the CPU into
18
AArch32 mode" on our existing cores like the A57 etc
5
19
6
Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE")
20
Make the decision of the encoding be based on whether
7
Reported-by: Peter Maydell <peter.maydell@linaro.org>
21
the CPU implements the ARM_FEATURE_V8 flag instead.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
This changes the behaviour only for the qemu-system-arm
10
Message-id: 20220301215958.157011-14-richard.henderson@linaro.org
24
'-cpu max'. We don't expect anybody to be relying on the
25
old behaviour because:
26
* it's not what the real hardware Cortex-A57 does
27
(and that's what our ID register claims we are)
28
* we don't implement the memory-mapped GICv3 support
29
which is the only thing that exists at the peripheral
30
base address pointed to by the register
31
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
12
---
35
---
13
target/arm/helper.c | 5 +++--
36
target/arm/helper.c | 2 +-
14
1 file changed, 3 insertions(+), 2 deletions(-)
37
1 file changed, 1 insertion(+), 1 deletion(-)
15
38
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
43
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
21
ret.length = (num + 1) << (exponent + page_shift);
44
* AArch64 cores we might need to add a specific feature flag
22
45
* to indicate cores with "flavour 2" CBAR.
23
if (regime_has_2_ranges(mmuidx)) {
46
*/
24
- ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
47
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
25
+ ret.base = sextract64(value, 0, 37);
48
+ if (arm_feature(env, ARM_FEATURE_V8)) {
26
} else {
49
/* 32 bit view is [31:18] 0...0 [43:32]. */
27
- ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS;
50
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
28
+ ret.base = extract64(value, 0, 37);
51
| extract64(cpu->reset_cbar, 32, 12);
29
}
30
+ ret.base <<= page_shift;
31
32
return ret;
33
}
34
--
52
--
35
2.25.1
53
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/35] target/arm: The Cortex-R52 has a read-only CBAR
1
The Cortex-R52 implements the Configuration Base Address Register
2
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
3
type, so that our implementation provides the register and the
4
associated qdev property.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
18
set_feature(&cpu->env, ARM_FEATURE_PMSA);
19
set_feature(&cpu->env, ARM_FEATURE_NEON);
20
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
21
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
22
cpu->midr = 0x411fd133; /* r1p3 */
23
cpu->revidr = 0x00000000;
24
cpu->reset_fpsid = 0x41034023;
25
--
26
2.34.1
diff view generated by jsdifflib
[PULL 26/26] ui/cocoa.m: Remove unnecessary NSAutoreleasePools
[PULL 25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
1
In commit 6e657e64cdc478 in 2013 we added some autorelease pools to
1
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
2
deal with complaints from macOS when we made calls into Cocoa from
2
also by enabling the AUXCR feature which defines the ACTLR
3
threads that didn't have automatically created autorelease pools.
3
and HACTLR registers. As is our usual practice, we make these
4
Later on, macOS got stricter about forbidding cross-thread Cocoa
4
simple reads-as-zero stubs for now.
5
calls, and in commit 5588840ff77800e839d8 we restructured the code to
6
avoid them. This left the autorelease pool creation in several
7
functions without any purpose; delete it.
8
9
We still need the pool in cocoa_refresh() for the clipboard related
10
code which is called directly there.
11
5
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
8
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
15
Message-id: 20220224101330.967429-3-peter.maydell@linaro.org
16
---
9
---
17
ui/cocoa.m | 6 ------
10
target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
18
1 file changed, 6 deletions(-)
11
1 file changed, 108 insertions(+)
19
12
20
diff --git a/ui/cocoa.m b/ui/cocoa.m
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
21
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
22
--- a/ui/cocoa.m
15
--- a/target/arm/tcg/cpu32.c
23
+++ b/ui/cocoa.m
16
+++ b/target/arm/tcg/cpu32.c
24
@@ -XXX,XX +XXX,XX @@ int main (int argc, char **argv) {
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
25
static void cocoa_update(DisplayChangeListener *dcl,
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
26
int x, int y, int w, int h)
19
}
20
21
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
22
+ { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
23
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
24
+ { .name = "IMP_ATCMREGIONR",
25
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
26
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
27
+ { .name = "IMP_BTCMREGIONR",
28
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
29
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
30
+ { .name = "IMP_CTCMREGIONR",
31
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
32
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ { .name = "IMP_CSCTLR",
34
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "IMP_BPCTLR",
37
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
38
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
+ { .name = "IMP_MEMPROTCLR",
40
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
41
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
+ { .name = "IMP_SLAVEPCTLR",
43
+ .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
44
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
+ { .name = "IMP_PERIPHREGIONR",
46
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
47
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
48
+ { .name = "IMP_FLASHIFREGIONR",
49
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "IMP_BUILDOPTR",
52
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
53
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "IMP_PINOPTR",
55
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
56
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ { .name = "IMP_QOSR",
58
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
59
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60
+ { .name = "IMP_BUSTIMEOUTR",
61
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
62
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
+ { .name = "IMP_INTMONR",
64
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
65
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66
+ { .name = "IMP_ICERR0",
67
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
68
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69
+ { .name = "IMP_ICERR1",
70
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
71
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
+ { .name = "IMP_DCERR0",
73
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
74
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
+ { .name = "IMP_DCERR1",
76
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
77
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78
+ { .name = "IMP_TCMERR0",
79
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
80
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
+ { .name = "IMP_TCMERR1",
82
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
83
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ { .name = "IMP_TCMSYNDR0",
85
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
86
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+ { .name = "IMP_TCMSYNDR1",
88
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
89
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
90
+ { .name = "IMP_FLASHERR0",
91
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
92
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
93
+ { .name = "IMP_FLASHERR1",
94
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
95
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
96
+ { .name = "IMP_CDBGDR0",
97
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
98
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
99
+ { .name = "IMP_CBDGBR1",
100
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
101
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
102
+ { .name = "IMP_TESTR0",
103
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
104
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
105
+ { .name = "IMP_TESTR1",
106
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
107
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
108
+ { .name = "IMP_CDBGDCI",
109
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
110
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
111
+ { .name = "IMP_CDBGDCT",
112
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
113
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
114
+ { .name = "IMP_CDBGICT",
115
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
116
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
117
+ { .name = "IMP_CDBGDCD",
118
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
119
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
120
+ { .name = "IMP_CDBGICD",
121
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
122
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
123
+};
124
+
125
+
126
static void cortex_r52_initfn(Object *obj)
27
{
127
{
28
- NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init];
128
ARMCPU *cpu = ARM_CPU(obj);
29
-
129
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
30
COCOA_DEBUG("qemu_cocoa: cocoa_update\n");
130
set_feature(&cpu->env, ARM_FEATURE_NEON);
31
131
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
32
dispatch_async(dispatch_get_main_queue(), ^{
132
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
33
@@ -XXX,XX +XXX,XX @@ static void cocoa_update(DisplayChangeListener *dcl,
133
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
34
}
134
cpu->midr = 0x411fd133; /* r1p3 */
35
[cocoaView setNeedsDisplayInRect:rect];
135
cpu->revidr = 0x00000000;
36
});
136
cpu->reset_fpsid = 0x41034023;
37
-
137
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
38
- [pool release];
138
139
cpu->pmsav7_dregion = 16;
140
cpu->pmsav8r_hdregion = 16;
141
+
142
+ define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
39
}
143
}
40
144
41
static void cocoa_switch(DisplayChangeListener *dcl,
145
static void cortex_r5f_initfn(Object *obj)
42
DisplaySurface *surface)
43
{
44
- NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init];
45
pixman_image_t *image = surface->image;
46
47
COCOA_DEBUG("qemu_cocoa: cocoa_switch\n");
48
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
49
[cocoaView updateUIInfo];
50
[cocoaView switchSurface:image];
51
});
52
- [pool release];
53
}
54
55
static void cocoa_refresh(DisplayChangeListener *dcl)
56
--
146
--
57
2.25.1
147
2.34.1
diff view generated by jsdifflib
[PULL 06/26] target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
[PULL 26/35] target/arm: Allow access to SPSR_hyp from hyp mode
1
From: Wentao_Liang <Wentao_Liang_g@163.com>
1
Architecturally, the AArch32 MSR/MRS to/from banked register
2
instructions are UNPREDICTABLE for attempts to access a banked
3
register that the guest could access in a more direct way (e.g.
4
using this insn to access r8_fiq when already in FIQ mode). QEMU has
5
chosen to UNDEF on all of these.
2
6
3
handle_simd_shift_fpint_conv() was accidentally freeing the TCG
7
However, for the case of accessing SPSR_hyp from hyp mode, it turns
4
temporary tcg_fpstatus too early, before the last use of it. Move
8
out that real hardware permits this, with the same effect as if the
5
the free down to where it belongs.
9
guest had directly written to SPSR. Further, there is some
10
guest code out there that assumes it can do this, because it
11
happens to work on hardware: an example Cortex-R52 startup code
12
fragment uses this, and it got copied into various other places,
13
including Zephyr. Zephyr was fixed to not use this:
14
https://github.com/zephyrproject-rtos/zephyr/issues/47330
15
but other examples are still out there, like the selftest
16
binary for the MPS3-AN536.
6
17
7
Signed-off-by: Wentao_Liang <Wentao_Liang_g@163.com>
18
For convenience of being able to run guest code, permit
19
this UNPREDICTABLE access instead of UNDEFing it.
20
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
[PMM: cleaned up commit message]
23
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
24
---
12
target/arm/translate-a64.c | 2 +-
25
target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
13
1 file changed, 1 insertion(+), 1 deletion(-)
26
target/arm/tcg/translate.c | 19 +++++++++++------
27
2 files changed, 43 insertions(+), 19 deletions(-)
14
28
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
16
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
31
--- a/target/arm/tcg/op_helper.c
18
+++ b/target/arm/translate-a64.c
32
+++ b/target/arm/tcg/op_helper.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
33
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
34
*/
35
int curmode = env->uncached_cpsr & CPSR_M;
36
37
- if (regno == 17) {
38
- /* ELR_Hyp: a special case because access from tgtmode is OK */
39
- if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
40
- goto undef;
41
+ if (tgtmode == ARM_CPU_MODE_HYP) {
42
+ /*
43
+ * Handle Hyp target regs first because some are special cases
44
+ * which don't want the usual "not accessible from tgtmode" check.
45
+ */
46
+ switch (regno) {
47
+ case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
48
+ if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
49
+ goto undef;
50
+ }
51
+ break;
52
+ case 13:
53
+ if (curmode != ARM_CPU_MODE_MON) {
54
+ goto undef;
55
+ }
56
+ break;
57
+ default:
58
+ g_assert_not_reached();
59
}
60
return;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
20
}
63
}
21
}
64
}
22
65
23
- tcg_temp_free_ptr(tcg_fpstatus);
66
- if (tgtmode == ARM_CPU_MODE_HYP) {
24
tcg_temp_free_i32(tcg_shift);
67
- /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
25
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
68
- if (curmode != ARM_CPU_MODE_MON) {
26
+ tcg_temp_free_ptr(tcg_fpstatus);
69
- goto undef;
27
tcg_temp_free_i32(tcg_rmode);
70
- }
28
}
71
- }
29
72
-
73
return;
74
75
undef:
76
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
77
78
switch (regno) {
79
case 16: /* SPSRs */
80
- env->banked_spsr[bank_number(tgtmode)] = value;
81
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
82
+ /* Only happens for SPSR_Hyp access in Hyp mode */
83
+ env->spsr = value;
84
+ } else {
85
+ env->banked_spsr[bank_number(tgtmode)] = value;
86
+ }
87
break;
88
case 17: /* ELR_Hyp */
89
env->elr_el[2] = value;
90
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
91
92
switch (regno) {
93
case 16: /* SPSRs */
94
- return env->banked_spsr[bank_number(tgtmode)];
95
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
96
+ /* Only happens for SPSR_Hyp access in Hyp mode */
97
+ return env->spsr;
98
+ } else {
99
+ return env->banked_spsr[bank_number(tgtmode)];
100
+ }
101
case 17: /* ELR_Hyp */
102
return env->elr_el[2];
103
case 13:
104
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/tcg/translate.c
107
+++ b/target/arm/tcg/translate.c
108
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
109
break;
110
case ARM_CPU_MODE_HYP:
111
/*
112
- * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
113
- * (and so we can forbid accesses from EL2 or below). elr_hyp
114
- * can be accessed also from Hyp mode, so forbid accesses from
115
- * EL0 or EL1.
116
+ * r13_hyp can only be accessed from Monitor mode, and so we
117
+ * can forbid accesses from EL2 or below.
118
+ * elr_hyp can be accessed also from Hyp mode, so forbid
119
+ * accesses from EL0 or EL1.
120
+ * SPSR_hyp is supposed to be in the same category as r13_hyp
121
+ * and UNPREDICTABLE if accessed from anything except Monitor
122
+ * mode. However there is some real-world code that will do
123
+ * it because at least some hardware happens to permit the
124
+ * access. (Notably a standard Cortex-R52 startup code fragment
125
+ * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
126
+ * this (incorrect) guest code to run.
127
*/
128
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
129
- (s->current_el < 3 && *regno != 17)) {
130
+ if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
131
+ || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
132
goto undef;
133
}
134
break;
30
--
135
--
31
2.25.1
136
2.34.1
diff view generated by jsdifflib
[PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
[PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
1
From: Richard Henderson <richard.henderson@linaro.org>
1
We currently guard the CFG3 register read with
2
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
3
which is clearly wrong as it is never true.
2
4
3
The original A.a revision of the AArch64 ARM required that we
5
This register is present on all board types except AN524
4
force-extend the addresses in these registers from 49 bits.
6
and AN527; correct the condition.
5
This language has been loosened via a combination of IMPLEMENTATION
6
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
7
the entire aligned address.
8
7
9
This means that we do not have to consider whether or not FEAT_LVA
8
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
10
is enabled, and decide from which bit an address might need to be
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
extended.
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
13
---
14
hw/misc/mps2-scc.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
16
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.c | 32 ++++++++++++++++++++++++--------
19
1 file changed, 24 insertions(+), 8 deletions(-)
20
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
19
--- a/hw/misc/mps2-scc.c
24
+++ b/target/arm/helper.c
20
+++ b/hw/misc/mps2-scc.c
25
@@ -XXX,XX +XXX,XX @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
21
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
26
ARMCPU *cpu = env_archcpu(env);
22
r = s->cfg2;
27
int i = ri->crm;
23
break;
28
24
case A_CFG3:
29
- /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
25
- if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
30
- * register reads and behaves as if values written are sign extended.
26
+ if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
31
+ /*
27
/* CFG3 reserved on AN524 */
32
* Bits [1:0] are RES0.
28
goto bad_offset;
33
+ *
34
+ * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
35
+ * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
36
+ * they contain the value written. It is CONSTRAINED UNPREDICTABLE
37
+ * whether the RESS bits are ignored when comparing an address.
38
+ *
39
+ * Therefore we are allowed to compare the entire register, which lets
40
+ * us avoid considering whether or not FEAT_LVA is actually enabled.
41
*/
42
- value = sextract64(value, 0, 49) & ~3ULL;
43
+ value &= ~3ULL;
44
45
raw_write(env, ri, value);
46
hw_watchpoint_update(cpu, i);
47
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
48
case 0: /* unlinked address match */
49
case 1: /* linked address match */
50
{
51
- /* Bits [63:49] are hardwired to the value of bit [48]; that is,
52
- * we behave as if the register was sign extended. Bits [1:0] are
53
- * RES0. The BAS field is used to allow setting breakpoints on 16
54
- * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
55
+ /*
56
+ * Bits [1:0] are RES0.
57
+ *
58
+ * It is IMPLEMENTATION DEFINED whether bits [63:49]
59
+ * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
60
+ * of the VA field ([48] or [52] for FEAT_LVA), or whether the
61
+ * value is read as written. It is CONSTRAINED UNPREDICTABLE
62
+ * whether the RESS bits are ignored when comparing an address.
63
+ * Therefore we are allowed to compare the entire register, which
64
+ * lets us avoid considering whether FEAT_LVA is actually enabled.
65
+ *
66
+ * The BAS field is used to allow setting breakpoints on 16-bit
67
+ * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
68
* a bp will fire if the addresses covered by the bp and the addresses
69
* covered by the insn overlap but the insn doesn't start at the
70
* start of the bp address range. We choose to require the insn and
71
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
72
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
73
*/
74
int bas = extract64(bcr, 5, 4);
75
- addr = sextract64(bvr, 0, 49) & ~3ULL;
76
+ addr = bvr & ~3ULL;
77
if (bas == 0) {
78
return;
79
}
29
}
80
--
30
--
81
2.25.1
31
2.34.1
32
33
diff view generated by jsdifflib
[PULL 11/26] target/arm: Move arm_pamax out of line
[PULL 28/35] hw/misc/mps2-scc: Factor out which-board conditionals
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The MPS SCC device has a lot of different flavours for the various
2
different MPS FPGA images, which look mostly similar but have
3
differences in how particular registers are handled. Currently we
4
deal with this with a lot of open-coded checks on scc_partno(), but
5
as we add more board types this is getting a bit hard to read.
2
6
3
We will shortly share parts of this function with other portions
7
Factor out the conditions into some functions which we can
4
of address translation.
8
give more descriptive names to.
5
9
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220301215958.157011-5-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
12
---
14
---
13
target/arm/internals.h | 19 +------------------
15
hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
14
target/arm/helper.c | 22 ++++++++++++++++++++++
16
1 file changed, 31 insertions(+), 14 deletions(-)
15
2 files changed, 23 insertions(+), 18 deletions(-)
16
17
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
18
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
20
--- a/hw/misc/mps2-scc.c
20
+++ b/target/arm/internals.h
21
+++ b/hw/misc/mps2-scc.c
21
@@ -XXX,XX +XXX,XX @@ static inline void update_spsel(CPUARMState *env, uint32_t imm)
22
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
22
* Returns the implementation defined bit-width of physical addresses.
23
return extract32(s->id, 4, 8);
23
* The ARMv8 reference manuals refer to this as PAMax().
24
*/
25
-static inline unsigned int arm_pamax(ARMCPU *cpu)
26
-{
27
- static const unsigned int pamax_map[] = {
28
- [0] = 32,
29
- [1] = 36,
30
- [2] = 40,
31
- [3] = 42,
32
- [4] = 44,
33
- [5] = 48,
34
- };
35
- unsigned int parange =
36
- FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
37
-
38
- /* id_aa64mmfr0 is a read-only register so values outside of the
39
- * supported mappings can be considered an implementation error. */
40
- assert(parange < ARRAY_SIZE(pamax_map));
41
- return pamax_map[parange];
42
-}
43
+unsigned int arm_pamax(ARMCPU *cpu);
44
45
/* Return true if extended addresses are enabled.
46
* This is always the case if our translation regime is 64 bit,
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/helper.c
50
+++ b/target/arm/helper.c
51
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
52
}
24
}
53
#endif /* !CONFIG_USER_ONLY */
25
54
26
+/* Is CFG_REG2 present? */
55
+/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
27
+static bool have_cfg2(MPS2SCC *s)
56
+unsigned int arm_pamax(ARMCPU *cpu)
57
+{
28
+{
58
+ static const unsigned int pamax_map[] = {
29
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
59
+ [0] = 32,
60
+ [1] = 36,
61
+ [2] = 40,
62
+ [3] = 42,
63
+ [4] = 44,
64
+ [5] = 48,
65
+ };
66
+ unsigned int parange =
67
+ FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
68
+
69
+ /*
70
+ * id_aa64mmfr0 is a read-only register so values outside of the
71
+ * supported mappings can be considered an implementation error.
72
+ */
73
+ assert(parange < ARRAY_SIZE(pamax_map));
74
+ return pamax_map[parange];
75
+}
30
+}
76
+
31
+
77
static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
32
+/* Is CFG_REG3 present? */
78
{
33
+static bool have_cfg3(MPS2SCC *s)
79
if (regime_has_2_ranges(mmu_idx)) {
34
+{
35
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
36
+}
37
+
38
+/* Is CFG_REG5 present? */
39
+static bool have_cfg5(MPS2SCC *s)
40
+{
41
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
42
+}
43
+
44
+/* Is CFG_REG6 present? */
45
+static bool have_cfg6(MPS2SCC *s)
46
+{
47
+ return scc_partno(s) == 0x524;
48
+}
49
+
50
/* Handle a write via the SYS_CFG channel to the specified function/device.
51
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
52
*/
53
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
54
r = s->cfg1;
55
break;
56
case A_CFG2:
57
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
58
- /* CFG2 reserved on other boards */
59
+ if (!have_cfg2(s)) {
60
goto bad_offset;
61
}
62
r = s->cfg2;
63
break;
64
case A_CFG3:
65
- if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
66
- /* CFG3 reserved on AN524 */
67
+ if (!have_cfg3(s)) {
68
goto bad_offset;
69
}
70
/* These are user-settable DIP switches on the board. We don't
71
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
72
r = s->cfg4;
73
break;
74
case A_CFG5:
75
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
76
- /* CFG5 reserved on other boards */
77
+ if (!have_cfg5(s)) {
78
goto bad_offset;
79
}
80
r = s->cfg5;
81
break;
82
case A_CFG6:
83
- if (scc_partno(s) != 0x524) {
84
- /* CFG6 reserved on other boards */
85
+ if (!have_cfg6(s)) {
86
goto bad_offset;
87
}
88
r = s->cfg6;
89
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
90
}
91
break;
92
case A_CFG2:
93
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
94
- /* CFG2 reserved on other boards */
95
+ if (!have_cfg2(s)) {
96
goto bad_offset;
97
}
98
/* AN524: QSPI Select signal */
99
s->cfg2 = value;
100
break;
101
case A_CFG5:
102
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
103
- /* CFG5 reserved on other boards */
104
+ if (!have_cfg5(s)) {
105
goto bad_offset;
106
}
107
/* AN524: ACLK frequency in Hz */
108
s->cfg5 = value;
109
break;
110
case A_CFG6:
111
- if (scc_partno(s) != 0x524) {
112
- /* CFG6 reserved on other boards */
113
+ if (!have_cfg6(s)) {
114
goto bad_offset;
115
}
116
/* AN524: Clock divider for BRAM */
80
--
117
--
81
2.25.1
118
2.34.1
82
119
83
120
diff view generated by jsdifflib
New patch
[PULL 29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
1
1
The MPS2 SCC device is broadly the same for all FPGA images, but has
2
minor differences in the behaviour of the CFG registers depending on
3
the image. In many cases we don't really care about the functionality
4
controlled by these registers and a reads-as-written or similar
5
behaviour is sufficient for the moment.
6
7
For the AN536 the required behaviour is:
8
9
* A_CFG0 has CPU reset and halt bits
10
- implement as reads-as-written for the moment
11
* A_CFG1 has flash or ATCM address 0 remap handling
12
- QEMU doesn't model this; implement as reads-as-written
13
* A_CFG2 has QSPI select (like AN524)
14
- implemented (no behaviour, as with AN524)
15
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
16
- QEMU doesn't care about these, so use the existing
17
RAZ behaviour for convenience
18
* A_CFG4 is board rev (like all other images)
19
- no change needed
20
* A_CFG5 is ACLK frq in hz (like AN524)
21
- implemented as reads-as-written, as for other boards
22
* A_CFG6 is core 0 vector table base address
23
- implemented as reads-as-written for the moment
24
* A_CFG7 is core 1 vector table base address
25
- implemented as reads-as-written for the moment
26
27
Make the changes necessary for this; leave TODO comments where
28
appropriate to indicate where we might want to come back and
29
implement things like CPU reset.
30
31
The other aspects of the device specific to this FPGA image (like the
32
values of the board ID and similar registers) will be set via the
33
device's qdev properties.
34
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
38
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
39
---
40
include/hw/misc/mps2-scc.h | 1 +
41
hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++----
42
2 files changed, 92 insertions(+), 10 deletions(-)
43
44
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/misc/mps2-scc.h
47
+++ b/include/hw/misc/mps2-scc.h
48
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
49
uint32_t cfg4;
50
uint32_t cfg5;
51
uint32_t cfg6;
52
+ uint32_t cfg7;
53
uint32_t cfgdata_rtn;
54
uint32_t cfgdata_out;
55
uint32_t cfgctrl;
56
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/mps2-scc.c
59
+++ b/hw/misc/mps2-scc.c
60
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
61
REG32(CFG4, 0x10)
62
REG32(CFG5, 0x14)
63
REG32(CFG6, 0x18)
64
+REG32(CFG7, 0x1c)
65
REG32(CFGDATA_RTN, 0xa0)
66
REG32(CFGDATA_OUT, 0xa4)
67
REG32(CFGCTRL, 0xa8)
68
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
69
/* Is CFG_REG2 present? */
70
static bool have_cfg2(MPS2SCC *s)
71
{
72
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
73
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
74
+ scc_partno(s) == 0x536;
75
}
76
77
/* Is CFG_REG3 present? */
78
static bool have_cfg3(MPS2SCC *s)
79
{
80
- return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
81
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
82
+ scc_partno(s) != 0x536;
83
}
84
85
/* Is CFG_REG5 present? */
86
static bool have_cfg5(MPS2SCC *s)
87
{
88
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
89
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
90
+ scc_partno(s) == 0x536;
91
}
92
93
/* Is CFG_REG6 present? */
94
static bool have_cfg6(MPS2SCC *s)
95
{
96
- return scc_partno(s) == 0x524;
97
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
98
+}
99
+
100
+/* Is CFG_REG7 present? */
101
+static bool have_cfg7(MPS2SCC *s)
102
+{
103
+ return scc_partno(s) == 0x536;
104
+}
105
+
106
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
107
+static bool cfg0_is_remap(MPS2SCC *s)
108
+{
109
+ return scc_partno(s) != 0x536;
110
+}
111
+
112
+/* Is CFG_REG1 driving a set of LEDs? */
113
+static bool cfg1_is_leds(MPS2SCC *s)
114
+{
115
+ return scc_partno(s) != 0x536;
116
}
117
118
/* Handle a write via the SYS_CFG channel to the specified function/device.
119
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
120
if (!have_cfg3(s)) {
121
goto bad_offset;
122
}
123
- /* These are user-settable DIP switches on the board. We don't
124
+ /*
125
+ * These are user-settable DIP switches on the board. We don't
126
* model that, so just return zeroes.
127
+ *
128
+ * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
129
+ * bits". These change which part of the DDR4 the motherboard
130
+ * configuration controller can see in its memory map (see the
131
+ * appnote section 2.4). QEMU doesn't model the MCC at all, so these
132
+ * bits are not interesting to us; read-as-zero is as good as anything
133
+ * else.
134
*/
135
r = 0;
136
break;
137
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
138
}
139
r = s->cfg6;
140
break;
141
+ case A_CFG7:
142
+ if (!have_cfg7(s)) {
143
+ goto bad_offset;
144
+ }
145
+ r = s->cfg7;
146
+ break;
147
case A_CFGDATA_RTN:
148
r = s->cfgdata_rtn;
149
break;
150
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
151
* we always reflect bit 0 in the 'remap' GPIO output line,
152
* and let the board wire it up or not as it chooses.
153
* TODO on some boards bit 1 is CPU_WAIT.
154
+ *
155
+ * TODO: on the AN536 this register controls reset and halt
156
+ * for both CPUs. For the moment we don't implement this, so the
157
+ * register just reads as written.
158
*/
159
s->cfg0 = value;
160
- qemu_set_irq(s->remap, s->cfg0 & 1);
161
+ if (cfg0_is_remap(s)) {
162
+ qemu_set_irq(s->remap, s->cfg0 & 1);
163
+ }
164
break;
165
case A_CFG1:
166
s->cfg1 = value;
167
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
168
- led_set_state(s->led[i], extract32(value, i, 1));
169
+ /*
170
+ * On most boards this register drives LEDs.
171
+ *
172
+ * TODO: for AN536 this controls whether flash and ATCM are
173
+ * enabled or disabled on reset. QEMU doesn't model this, and
174
+ * always wires up RAM in the ATCM area and ROM in the flash area.
175
+ */
176
+ if (cfg1_is_leds(s)) {
177
+ for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
178
+ led_set_state(s->led[i], extract32(value, i, 1));
179
+ }
180
}
181
break;
182
case A_CFG2:
183
if (!have_cfg2(s)) {
184
goto bad_offset;
185
}
186
- /* AN524: QSPI Select signal */
187
+ /* AN524, AN536: QSPI Select signal */
188
s->cfg2 = value;
189
break;
190
case A_CFG5:
191
if (!have_cfg5(s)) {
192
goto bad_offset;
193
}
194
- /* AN524: ACLK frequency in Hz */
195
+ /* AN524, AN536: ACLK frequency in Hz */
196
s->cfg5 = value;
197
break;
198
case A_CFG6:
199
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
200
goto bad_offset;
201
}
202
/* AN524: Clock divider for BRAM */
203
+ /* AN536: Core 0 vector table base address */
204
+ s->cfg6 = value;
205
+ break;
206
+ case A_CFG7:
207
+ if (!have_cfg7(s)) {
208
+ goto bad_offset;
209
+ }
210
+ /* AN536: Core 1 vector table base address */
211
s->cfg6 = value;
212
break;
213
case A_CFGDATA_OUT:
214
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
215
g_free(s->oscclk_reset);
216
}
217
218
+static bool cfg7_needed(void *opaque)
219
+{
220
+ MPS2SCC *s = opaque;
221
+
222
+ return have_cfg7(s);
223
+}
224
+
225
+static const VMStateDescription vmstate_cfg7 = {
226
+ .name = "mps2-scc/cfg7",
227
+ .version_id = 1,
228
+ .minimum_version_id = 1,
229
+ .needed = cfg7_needed,
230
+ .fields = (const VMStateField[]) {
231
+ VMSTATE_UINT32(cfg7, MPS2SCC),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
static const VMStateDescription mps2_scc_vmstate = {
237
.name = "mps2-scc",
238
.version_id = 3,
239
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
240
VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
241
0, vmstate_info_uint32, uint32_t),
242
VMSTATE_END_OF_LIST()
243
+ },
244
+ .subsections = (const VMStateDescription * const []) {
245
+ &vmstate_cfg7,
246
+ NULL
247
}
248
};
249
250
--
251
2.34.1
252
253
diff view generated by jsdifflib
[PULL 07/26] tests/qtest: add qtests for npcm7xx sdhci
[PULL 30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
1
From: Shengtan Mao <stmao@google.com>
1
The AN536 is another FPGA image for the MPS3 development board. Unlike
2
2
the existing FPGA images we already model, this board uses a Cortex-R
3
Reviewed-by: Hao Wu <wuhaotsh@google.com>
3
family CPU, and it does not use any equivalent to the M-profile
4
Reviewed-by: Chris Rauer <crauer@google.com>
4
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
5
Signed-off-by: Shengtan Mao <stmao@google.com>
5
It's therefore more convenient for us to model it as a completely
6
Signed-off-by: Patrick Venture <venture@google.com>
6
separate C file.
7
Message-id: 20220225174451.192304-1-wuhaotsh@google.com
7
8
This commit adds the basic skeleton of the board model, and the
9
code to create all the RAM and ROM. We assume that we're probably
10
going to want to add more images in future, so use the same
11
base class/subclass setup that mps2-tz.c uses, even though at
12
the moment there's only a single subclass.
13
14
Following commits will add the CPUs and the peripherals.
15
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
9
---
19
---
10
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++++++++
20
MAINTAINERS | 3 +-
11
tests/qtest/meson.build | 1 +
21
configs/devices/arm-softmmu/default.mak | 1 +
12
2 files changed, 216 insertions(+)
22
hw/arm/mps3r.c | 239 ++++++++++++++++++++++++
13
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
23
hw/arm/Kconfig | 5 +
14
24
hw/arm/meson.build | 1 +
15
diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c
25
5 files changed, 248 insertions(+), 1 deletion(-)
26
create mode 100644 hw/arm/mps3r.c
27
28
diff --git a/MAINTAINERS b/MAINTAINERS
29
index XXXXXXX..XXXXXXX 100644
30
--- a/MAINTAINERS
31
+++ b/MAINTAINERS
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
33
F: hw/pci-host/designware.c
34
F: include/hw/pci-host/designware.h
35
36
-MPS2
37
+MPS2 / MPS3
38
M: Peter Maydell <peter.maydell@linaro.org>
39
L: qemu-arm@nongnu.org
40
S: Maintained
41
F: hw/arm/mps2.c
42
F: hw/arm/mps2-tz.c
43
+F: hw/arm/mps3r.c
44
F: hw/misc/mps2-*.c
45
F: include/hw/misc/mps2-*.h
46
F: hw/arm/armsse.c
47
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
48
index XXXXXXX..XXXXXXX 100644
49
--- a/configs/devices/arm-softmmu/default.mak
50
+++ b/configs/devices/arm-softmmu/default.mak
51
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
52
# CONFIG_INTEGRATOR=n
53
# CONFIG_FSL_IMX31=n
54
# CONFIG_MUSICPAL=n
55
+# CONFIG_MPS3R=n
56
# CONFIG_MUSCA=n
57
# CONFIG_CHEETAH=n
58
# CONFIG_SX1=n
59
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
16
new file mode 100644
60
new file mode 100644
17
index XXXXXXX..XXXXXXX
61
index XXXXXXX..XXXXXXX
18
--- /dev/null
62
--- /dev/null
19
+++ b/tests/qtest/npcm7xx_sdhci-test.c
63
+++ b/hw/arm/mps3r.c
20
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@
21
+/*
65
+/*
22
+ * QTests for NPCM7xx SD-3.0 / MMC-4.51 Host Controller
66
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
67
+ * (For M-profile images see mps2.c and mps2tz.c.)
23
+ *
68
+ *
24
+ * Copyright (c) 2022 Google LLC
69
+ * Copyright (c) 2017 Linaro Limited
70
+ * Written by Peter Maydell
25
+ *
71
+ *
26
+ * This program is free software; you can redistribute it and/or modify it
72
+ * This program is free software; you can redistribute it and/or modify
27
+ * under the terms of the GNU General Public License as published by the
73
+ * it under the terms of the GNU General Public License version 2 or
28
+ * Free Software Foundation; either version 2 of the License, or
74
+ * (at your option) any later version.
29
+ * (at your option) any later version.
75
+ */
76
+
77
+/*
78
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
79
+ * which use the Cortex-R CPUs. We model these separately from the
80
+ * M-profile images, because on M-profile the FPGA image is based on
81
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
82
+ * the R-profile FPGA images don't have that abstraction layer.
30
+ *
83
+ *
31
+ * This program is distributed in the hope that it will be useful, but WITHOUT
84
+ * We model the following FPGA images here:
32
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
85
+ * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
33
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
86
+ *
34
+ * for more details.
87
+ * Application Note AN536:
88
+ * https://developer.arm.com/documentation/dai0536/latest/
35
+ */
89
+ */
36
+
90
+
37
+#include "qemu/osdep.h"
91
+#include "qemu/osdep.h"
38
+#include "hw/sd/npcm7xx_sdhci.h"
92
+#include "qemu/units.h"
39
+
93
+#include "qapi/error.h"
40
+#include "libqos/libqtest.h"
94
+#include "exec/address-spaces.h"
41
+#include "libqtest-single.h"
95
+#include "cpu.h"
42
+#include "libqos/sdhci-cmd.h"
96
+#include "hw/boards.h"
43
+
97
+#include "hw/arm/boot.h"
44
+#define NPCM7XX_REG_SIZE 0x100
98
+
45
+#define NPCM7XX_MMC_BA 0xF0842000
99
+/* Define the layout of RAM and ROM in a board */
46
+#define NPCM7XX_BLK_SIZE 512
100
+typedef struct RAMInfo {
47
+#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30)
101
+ const char *name;
48
+
102
+ hwaddr base;
49
+char *sd_path;
103
+ hwaddr size;
50
+
104
+ int mrindex; /* index into rams[]; -1 for the system RAM block */
51
+static QTestState *setup_sd_card(void)
105
+ int flags;
52
+{
106
+} RAMInfo;
53
+ QTestState *qts = qtest_initf(
107
+
54
+ "-machine kudo-bmc "
108
+/*
55
+ "-device sd-card,drive=drive0 "
109
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
56
+ "-drive id=drive0,if=none,file=%s,format=raw,auto-read-only=off",
110
+ * emulation of that much guest RAM, so artificially make it smaller.
57
+ sd_path);
111
+ */
58
+
112
+#if HOST_LONG_BITS == 32
59
+ qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_SWRST, SDHC_RESET_ALL);
113
+#define MPS3_DDR_SIZE (1 * GiB)
60
+ qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_CLKCON,
114
+#else
61
+ SDHC_CLOCK_SDCLK_EN | SDHC_CLOCK_INT_STABLE |
115
+#define MPS3_DDR_SIZE (3 * GiB)
62
+ SDHC_CLOCK_INT_EN);
116
+#endif
63
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD);
117
+
64
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8));
118
+/*
65
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID);
119
+ * Flag values:
66
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_SEND_RELATIVE_ADDR);
120
+ * IS_MAIN: this is the main machine RAM
67
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x45670000, 0,
121
+ * IS_ROM: this area is read-only
68
+ SDHC_SELECT_DESELECT_CARD);
122
+ */
69
+
123
+#define IS_MAIN 1
70
+ return qts;
124
+#define IS_ROM 2
71
+}
125
+
72
+
126
+#define MPS3R_RAM_MAX 9
73
+static void write_sdread(QTestState *qts, const char *msg)
127
+
74
+{
128
+typedef enum MPS3RFPGAType {
75
+ int fd, ret;
129
+ FPGA_AN536,
76
+ size_t len = strlen(msg);
130
+} MPS3RFPGAType;
77
+ char *rmsg = g_malloc(len);
131
+
78
+
132
+struct MPS3RMachineClass {
79
+ /* write message to sd */
133
+ MachineClass parent;
80
+ fd = open(sd_path, O_WRONLY);
134
+ MPS3RFPGAType fpga_type;
81
+ g_assert(fd >= 0);
135
+ const RAMInfo *raminfo;
82
+ ret = write(fd, msg, len);
136
+};
83
+ close(fd);
137
+
84
+ g_assert(ret == len);
138
+struct MPS3RMachineState {
85
+
139
+ MachineState parent;
86
+ /* read message using sdhci */
140
+ MemoryRegion ram[MPS3R_RAM_MAX];
87
+ ret = sdhci_read_cmd(qts, NPCM7XX_MMC_BA, rmsg, len);
141
+};
88
+ g_assert(ret == len);
142
+
89
+ g_assert(!memcmp(rmsg, msg, len));
143
+#define TYPE_MPS3R_MACHINE "mps3r"
90
+
144
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
91
+ g_free(rmsg);
145
+
92
+}
146
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
93
+
147
+
94
+/* Check MMC can read values from sd */
148
+static const RAMInfo an536_raminfo[] = {
95
+static void test_read_sd(void)
149
+ {
96
+{
150
+ .name = "ATCM",
97
+ QTestState *qts = setup_sd_card();
151
+ .base = 0x00000000,
98
+
152
+ .size = 0x00008000,
99
+ write_sdread(qts, "hello world");
153
+ .mrindex = 0,
100
+ write_sdread(qts, "goodbye");
154
+ }, {
101
+
155
+ /* We model the QSPI flash as simple ROM for now */
102
+ qtest_quit(qts);
156
+ .name = "QSPI",
103
+}
157
+ .base = 0x08000000,
104
+
158
+ .size = 0x00800000,
105
+static void sdwrite_read(QTestState *qts, const char *msg)
159
+ .flags = IS_ROM,
106
+{
160
+ .mrindex = 1,
107
+ int fd, ret;
161
+ }, {
108
+ size_t len = strlen(msg);
162
+ .name = "BRAM",
109
+ char *rmsg = g_malloc(len);
163
+ .base = 0x10000000,
110
+
164
+ .size = 0x00080000,
111
+ /* write message using sdhci */
165
+ .mrindex = 2,
112
+ sdhci_write_cmd(qts, NPCM7XX_MMC_BA, msg, len, NPCM7XX_BLK_SIZE);
166
+ }, {
113
+
167
+ .name = "DDR",
114
+ /* read message from sd */
168
+ .base = 0x20000000,
115
+ fd = open(sd_path, O_RDONLY);
169
+ .size = MPS3_DDR_SIZE,
116
+ g_assert(fd >= 0);
170
+ .mrindex = -1,
117
+ ret = read(fd, rmsg, len);
171
+ }, {
118
+ close(fd);
172
+ .name = "ATCM0",
119
+ g_assert(ret == len);
173
+ .base = 0xee000000,
120
+
174
+ .size = 0x00008000,
121
+ g_assert(!memcmp(rmsg, msg, len));
175
+ .mrindex = 3,
122
+
176
+ }, {
123
+ g_free(rmsg);
177
+ .name = "BTCM0",
124
+}
178
+ .base = 0xee100000,
125
+
179
+ .size = 0x00008000,
126
+/* Check MMC can write values to sd */
180
+ .mrindex = 4,
127
+static void test_write_sd(void)
181
+ }, {
128
+{
182
+ .name = "CTCM0",
129
+ QTestState *qts = setup_sd_card();
183
+ .base = 0xee200000,
130
+
184
+ .size = 0x00008000,
131
+ sdwrite_read(qts, "hello world");
185
+ .mrindex = 5,
132
+ sdwrite_read(qts, "goodbye");
186
+ }, {
133
+
187
+ .name = "ATCM1",
134
+ qtest_quit(qts);
188
+ .base = 0xee400000,
135
+}
189
+ .size = 0x00008000,
136
+
190
+ .mrindex = 6,
137
+/* Check SDHCI has correct default values. */
191
+ }, {
138
+static void test_reset(void)
192
+ .name = "BTCM1",
139
+{
193
+ .base = 0xee500000,
140
+ QTestState *qts = qtest_init("-machine kudo-bmc");
194
+ .size = 0x00008000,
141
+ uint64_t addr = NPCM7XX_MMC_BA;
195
+ .mrindex = 7,
142
+ uint64_t end_addr = addr + NPCM7XX_REG_SIZE;
196
+ }, {
143
+ uint16_t prstvals_resets[] = {NPCM7XX_PRSTVALS_0_RESET,
197
+ .name = "CTCM1",
144
+ NPCM7XX_PRSTVALS_1_RESET,
198
+ .base = 0xee600000,
145
+ 0,
199
+ .size = 0x00008000,
146
+ NPCM7XX_PRSTVALS_3_RESET,
200
+ .mrindex = 8,
147
+ 0,
201
+ }, {
148
+ 0};
202
+ .name = NULL,
149
+ int i;
203
+ }
150
+ uint32_t mask;
204
+};
151
+
205
+
152
+ while (addr < end_addr) {
206
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
153
+ switch (addr - NPCM7XX_MMC_BA) {
207
+ const RAMInfo *raminfo)
154
+ case SDHC_PRNSTS:
208
+{
155
+ /*
209
+ /* Return an initialized MemoryRegion for the RAMInfo. */
156
+ * ignores bits 20 to 24: they are changed when reading registers
210
+ MemoryRegion *ram;
157
+ */
211
+
158
+ mask = 0x1f00000;
212
+ if (raminfo->mrindex < 0) {
159
+ g_assert_cmphex(qtest_readl(qts, addr) | mask, ==,
213
+ /* Means this RAMInfo is for QEMU's "system memory" */
160
+ NPCM7XX_PRSNTS_RESET | mask);
214
+ MachineState *machine = MACHINE(mms);
161
+ addr += 4;
215
+ assert(!(raminfo->flags & IS_ROM));
162
+ break;
216
+ return machine->ram;
163
+ case SDHC_BLKGAP:
217
+ }
164
+ g_assert_cmphex(qtest_readb(qts, addr), ==, NPCM7XX_BLKGAP_RESET);
218
+
165
+ addr += 1;
219
+ assert(raminfo->mrindex < MPS3R_RAM_MAX);
166
+ break;
220
+ ram = &mms->ram[raminfo->mrindex];
167
+ case SDHC_CAPAB:
221
+
168
+ g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_CAPAB_RESET);
222
+ memory_region_init_ram(ram, NULL, raminfo->name,
169
+ addr += 8;
223
+ raminfo->size, &error_fatal);
170
+ break;
224
+ if (raminfo->flags & IS_ROM) {
171
+ case SDHC_MAXCURR:
225
+ memory_region_set_readonly(ram, true);
172
+ g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_MAXCURR_RESET);
226
+ }
173
+ addr += 8;
227
+ return ram;
174
+ break;
228
+}
175
+ case SDHC_HCVER:
229
+
176
+ g_assert_cmphex(qtest_readw(qts, addr), ==, NPCM7XX_HCVER_RESET);
230
+static void mps3r_common_init(MachineState *machine)
177
+ addr += 2;
231
+{
178
+ break;
232
+ MPS3RMachineState *mms = MPS3R_MACHINE(machine);
179
+ case NPCM7XX_PRSTVALS:
233
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
180
+ for (i = 0; i < NPCM7XX_PRSTVALS_SIZE; ++i) {
234
+ MemoryRegion *sysmem = get_system_memory();
181
+ g_assert_cmphex(qtest_readw(qts, addr + 2 * i), ==,
235
+
182
+ prstvals_resets[i]);
236
+ for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
183
+ }
237
+ MemoryRegion *mr = mr_for_raminfo(mms, ri);
184
+ addr += NPCM7XX_PRSTVALS_SIZE * 2;
238
+ memory_region_add_subregion(sysmem, ri->base, mr);
185
+ break;
239
+ }
186
+ default:
240
+}
187
+ g_assert_cmphex(qtest_readb(qts, addr), ==, 0);
241
+
188
+ addr += 1;
242
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
243
+{
244
+ /*
245
+ * Set mc->default_ram_size and default_ram_id from the
246
+ * information in mmc->raminfo.
247
+ */
248
+ MachineClass *mc = MACHINE_CLASS(mmc);
249
+ const RAMInfo *p;
250
+
251
+ for (p = mmc->raminfo; p->name; p++) {
252
+ if (p->mrindex < 0) {
253
+ /* Found the entry for "system memory" */
254
+ mc->default_ram_size = p->size;
255
+ mc->default_ram_id = p->name;
256
+ return;
189
+ }
257
+ }
190
+ }
258
+ }
191
+
259
+ g_assert_not_reached();
192
+ qtest_quit(qts);
260
+}
193
+}
261
+
194
+
262
+static void mps3r_class_init(ObjectClass *oc, void *data)
195
+static void drive_destroy(void)
263
+{
196
+{
264
+ MachineClass *mc = MACHINE_CLASS(oc);
197
+ unlink(sd_path);
265
+
198
+ g_free(sd_path);
266
+ mc->init = mps3r_common_init;
199
+}
267
+}
200
+
268
+
201
+static void drive_create(void)
269
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
202
+{
270
+{
203
+ int fd, ret;
271
+ MachineClass *mc = MACHINE_CLASS(oc);
204
+ GError *error = NULL;
272
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
205
+
273
+ static const char * const valid_cpu_types[] = {
206
+ /* Create a temporary raw image */
274
+ ARM_CPU_TYPE_NAME("cortex-r52"),
207
+ fd = g_file_open_tmp("sdhci_XXXXXX", &sd_path, &error);
275
+ NULL
208
+ if (fd == -1) {
276
+ };
209
+ fprintf(stderr, "unable to create sdhci file: %s\n", error->message);
277
+
210
+ g_error_free(error);
278
+ mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
211
+ }
279
+ mc->default_cpus = 2;
212
+ g_assert(sd_path != NULL);
280
+ mc->min_cpus = mc->default_cpus;
213
+
281
+ mc->max_cpus = mc->default_cpus;
214
+ ret = ftruncate(fd, NPCM7XX_TEST_IMAGE_SIZE);
282
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
215
+ g_assert_cmpint(ret, ==, 0);
283
+ mc->valid_cpu_types = valid_cpu_types;
216
+ g_message("%s", sd_path);
284
+ mmc->raminfo = an536_raminfo;
217
+ close(fd);
285
+ mps3r_set_default_ram_info(mmc);
218
+}
286
+}
219
+
287
+
220
+int main(int argc, char **argv)
288
+static const TypeInfo mps3r_machine_types[] = {
221
+{
289
+ {
222
+ int ret;
290
+ .name = TYPE_MPS3R_MACHINE,
223
+
291
+ .parent = TYPE_MACHINE,
224
+ drive_create();
292
+ .abstract = true,
225
+
293
+ .instance_size = sizeof(MPS3RMachineState),
226
+ g_test_init(&argc, &argv, NULL);
294
+ .class_size = sizeof(MPS3RMachineClass),
227
+
295
+ .class_init = mps3r_class_init,
228
+ qtest_add_func("npcm7xx_sdhci/reset", test_reset);
296
+ }, {
229
+ qtest_add_func("npcm7xx_sdhci/write_sd", test_write_sd);
297
+ .name = TYPE_MPS3R_AN536_MACHINE,
230
+ qtest_add_func("npcm7xx_sdhci/read_sd", test_read_sd);
298
+ .parent = TYPE_MPS3R_MACHINE,
231
+
299
+ .class_init = mps3r_an536_class_init,
232
+ ret = g_test_run();
300
+ },
233
+ drive_destroy();
301
+};
234
+ return ret;
302
+
235
+}
303
+DEFINE_TYPES(mps3r_machine_types);
236
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
304
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
237
index XXXXXXX..XXXXXXX 100644
305
index XXXXXXX..XXXXXXX 100644
238
--- a/tests/qtest/meson.build
306
--- a/hw/arm/Kconfig
239
+++ b/tests/qtest/meson.build
307
+++ b/hw/arm/Kconfig
240
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
308
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
241
'npcm7xx_gpio-test',
309
select PFLASH_CFI01
242
'npcm7xx_pwm-test',
310
select SMC91C111
243
'npcm7xx_rng-test',
311
244
+ 'npcm7xx_sdhci-test',
312
+config MPS3R
245
'npcm7xx_smbus-test',
313
+ bool
246
'npcm7xx_timer-test',
314
+ default y
247
'npcm7xx_watchdog_timer-test'] + \
315
+ depends on TCG && ARM
316
+
317
config MUSCA
318
bool
319
default y
320
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/arm/meson.build
323
+++ b/hw/arm/meson.build
324
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
325
arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
326
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
327
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
328
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
329
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
330
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
331
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
248
--
332
--
249
2.25.1
333
2.34.1
334
335
diff view generated by jsdifflib
[PULL 23/26] target/arm: Implement FEAT_LPA2
[PULL 31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Create the CPUs, the GIC, and the per-CPU RAM block for
2
the mps3-an536 board.
2
3
3
This feature widens physical addresses (and intermediate physical
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
addresses for 2-stage translation) from 48 to 52 bits, when using
5
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
5
4k or 16k pages.
6
---
7
hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
8
1 file changed, 177 insertions(+), 3 deletions(-)
6
9
7
This introduces the DS bit to TCR_ELx, which is RES0 unless the
10
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
8
page size is enabled and supports LPA2, resulting in the effective
9
value of DS for a given table walk. The DS bit changes the format
10
of the page table descriptor slightly, moving the PS field out to
11
TCR so that all pages have the same sharability and repurposing
12
those bits of the page table descriptor for the highest bits of
13
the output address.
14
15
Do not yet enable FEAT_LPA2; we need extra plumbing to avoid
16
tickling an old kernel bug.
17
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20220301215958.157011-17-richard.henderson@linaro.org
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
docs/system/arm/emulation.rst | 1 +
24
target/arm/cpu.h | 22 ++++++++
25
target/arm/internals.h | 2 +
26
target/arm/helper.c | 102 +++++++++++++++++++++++++++++-----
27
4 files changed, 112 insertions(+), 15 deletions(-)
28
29
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
30
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
31
--- a/docs/system/arm/emulation.rst
12
--- a/hw/arm/mps3r.c
32
+++ b/docs/system/arm/emulation.rst
13
+++ b/hw/arm/mps3r.c
33
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
14
@@ -XXX,XX +XXX,XX @@
34
- FEAT_JSCVT (JavaScript conversion instructions)
15
#include "qemu/osdep.h"
35
- FEAT_LOR (Limited ordering regions)
16
#include "qemu/units.h"
36
- FEAT_LPA (Large Physical Address space)
17
#include "qapi/error.h"
37
+- FEAT_LPA2 (Large Physical and virtual Address space v2)
18
+#include "qapi/qmp/qlist.h"
38
- FEAT_LRCPC (Load-acquire RCpc instructions)
19
#include "exec/address-spaces.h"
39
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
20
#include "cpu.h"
40
- FEAT_LSE (Large System Extensions)
21
#include "hw/boards.h"
41
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
+#include "hw/qdev-properties.h"
42
index XXXXXXX..XXXXXXX 100644
23
#include "hw/arm/boot.h"
43
--- a/target/arm/cpu.h
24
+#include "hw/arm/bsa.h"
44
+++ b/target/arm/cpu.h
25
+#include "hw/intc/arm_gicv3.h"
45
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
26
46
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
27
/* Define the layout of RAM and ROM in a board */
28
typedef struct RAMInfo {
29
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
30
#define IS_ROM 2
31
32
#define MPS3R_RAM_MAX 9
33
+#define MPS3R_CPU_MAX 2
34
+
35
+#define PERIPHBASE 0xf0000000
36
+#define NUM_SPIS 96
37
38
typedef enum MPS3RFPGAType {
39
FPGA_AN536,
40
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
41
MachineClass parent;
42
MPS3RFPGAType fpga_type;
43
const RAMInfo *raminfo;
44
+ hwaddr loader_start;
45
};
46
47
struct MPS3RMachineState {
48
MachineState parent;
49
+ struct arm_boot_info bootinfo;
50
MemoryRegion ram[MPS3R_RAM_MAX];
51
+ Object *cpu[MPS3R_CPU_MAX];
52
+ MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
53
+ MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
54
+ MemoryRegion cpu_ram[MPS3R_CPU_MAX];
55
+ GICv3State gic;
56
};
57
58
#define TYPE_MPS3R_MACHINE "mps3r"
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
60
return ram;
47
}
61
}
48
62
49
+static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
63
+/*
64
+ * There is no defined secondary boot protocol for Linux for the AN536,
65
+ * because real hardware has a restriction that atomic operations between
66
+ * the two CPUs do not function correctly, and so true SMP is not
67
+ * possible. Therefore for cases where the user is directly booting
68
+ * a kernel, we treat the system as essentially uniprocessor, and
69
+ * put the secondary CPU into power-off state (as if the user on the
70
+ * real hardware had configured the secondary to be halted via the
71
+ * SCC config registers).
72
+ *
73
+ * Note that the default secondary boot code would not work here anyway
74
+ * as it assumes a GICv2, and we have a GICv3.
75
+ */
76
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
77
+ const struct arm_boot_info *info)
50
+{
78
+{
51
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
79
+ /*
80
+ * Power the secondary CPU off. This means we don't need to write any
81
+ * boot code into guest memory. Note that the 'cpu' argument to this
82
+ * function is the primary CPU we passed to arm_load_kernel(), not
83
+ * the secondary. Loop around all the other CPUs, as the boot.c
84
+ * code does for the "disable secondaries if PSCI is enabled" case.
85
+ */
86
+ for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
87
+ if (cs != first_cpu) {
88
+ object_property_set_bool(OBJECT(cs), "start-powered-off", true,
89
+ &error_abort);
90
+ }
91
+ }
52
+}
92
+}
53
+
93
+
54
+static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
94
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
55
+{
96
+{
56
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
97
+ /* We don't need to do anything here because the CPU will be off */
57
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
58
+}
98
+}
59
+
99
+
60
+static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
100
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
61
+{
101
+{
62
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
102
+ MachineState *machine = MACHINE(mms);
103
+ DeviceState *gicdev;
104
+ QList *redist_region_count;
105
+
106
+ object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
107
+ gicdev = DEVICE(&mms->gic);
108
+ qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
109
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
110
+ redist_region_count = qlist_new();
111
+ qlist_append_int(redist_region_count, machine->smp.cpus);
112
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
113
+ object_property_set_link(OBJECT(&mms->gic), "sysmem",
114
+ OBJECT(sysmem), &error_fatal);
115
+ sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
116
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
118
+ /*
119
+ * Wire the outputs from each CPU's generic timer and the GICv3
120
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
121
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
122
+ */
123
+ for (int i = 0; i < machine->smp.cpus; i++) {
124
+ DeviceState *cpudev = DEVICE(mms->cpu[i]);
125
+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
126
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
127
+ int irq;
128
+ /*
129
+ * Mapping from the output timer irq lines from the CPU to the
130
+ * GIC PPI inputs used for this board. This isn't a BSA board,
131
+ * but it uses the standard convention for the PPI numbers.
132
+ */
133
+ const int timer_irq[] = {
134
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
135
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
136
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
137
+ };
138
+
139
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
140
+ qdev_connect_gpio_out(cpudev, irq,
141
+ qdev_get_gpio_in(gicdev,
142
+ intidbase + timer_irq[irq]));
143
+ }
144
+
145
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
146
+ qdev_get_gpio_in(gicdev,
147
+ intidbase + ARCH_GIC_MAINT_IRQ));
148
+
149
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
150
+ qdev_get_gpio_in(gicdev,
151
+ intidbase + VIRTUAL_PMU_IRQ));
152
+
153
+ sysbus_connect_irq(gicsbd, i,
154
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
155
+ sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
156
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
157
+ sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
158
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
159
+ sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
160
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
161
+ }
63
+}
162
+}
64
+
163
+
65
+static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
164
static void mps3r_common_init(MachineState *machine)
66
+{
67
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
68
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
69
+}
70
+
71
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
72
{
165
{
73
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
166
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
74
diff --git a/target/arm/internals.h b/target/arm/internals.h
167
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
75
index XXXXXXX..XXXXXXX 100644
168
MemoryRegion *mr = mr_for_raminfo(mms, ri);
76
--- a/target/arm/internals.h
169
memory_region_add_subregion(sysmem, ri->base, mr);
77
+++ b/target/arm/internals.h
78
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
79
typedef struct ARMVAParameters {
80
unsigned tsz : 8;
81
unsigned ps : 3;
82
+ unsigned sh : 2;
83
unsigned select : 1;
84
bool tbi : 1;
85
bool epd : 1;
86
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
87
bool using16k : 1;
88
bool using64k : 1;
89
bool tsz_oob : 1; /* tsz has been clamped to legal range */
90
+ bool ds : 1;
91
} ARMVAParameters;
92
93
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
94
diff --git a/target/arm/helper.c b/target/arm/helper.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/target/arm/helper.c
97
+++ b/target/arm/helper.c
98
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
99
} else {
100
ret.base = extract64(value, 0, 37);
101
}
170
}
102
+ if (param.ds) {
171
+
172
+ assert(machine->smp.cpus <= MPS3R_CPU_MAX);
173
+ for (int i = 0; i < machine->smp.cpus; i++) {
174
+ g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
175
+ g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
176
+ g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
177
+
103
+ /*
178
+ /*
104
+ * With DS=1, BaseADDR is always shifted 16 so that it is able
179
+ * Each CPU has some private RAM/peripherals, so create the container
105
+ * to address all 52 va bits. The input address is perforce
180
+ * which will house those, with the whole-machine system memory being
106
+ * aligned on a 64k boundary regardless of translation granule.
181
+ * used where there's no CPU-specific device. Note that we need the
182
+ * sysmem_alias aliases because we can't put one MR (the original
183
+ * 'sysmem') into more than one other MR.
107
+ */
184
+ */
108
+ page_shift = 16;
185
+ memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
186
+ sysmem_name, UINT64_MAX);
187
+ memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
188
+ alias_name, sysmem, 0, UINT64_MAX);
189
+ memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
190
+ &mms->sysmem_alias[i], -1);
191
+
192
+ mms->cpu[i] = object_new(machine->cpu_type);
193
+ object_property_set_link(mms->cpu[i], "memory",
194
+ OBJECT(&mms->cpu_sysmem[i]), &error_abort);
195
+ object_property_set_int(mms->cpu[i], "reset-cbar",
196
+ PERIPHBASE, &error_abort);
197
+ qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
198
+ object_unref(mms->cpu[i]);
199
+
200
+ /* Per-CPU RAM */
201
+ memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
202
+ 0x1000, &error_fatal);
203
+ memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
204
+ &mms->cpu_ram[i]);
109
+ }
205
+ }
110
ret.base <<= page_shift;
206
+
111
207
+ create_gic(mms, sysmem);
112
return ret;
208
+
113
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
209
+ mms->bootinfo.ram_size = machine->ram_size;
114
const int grainsize = stride + 3;
210
+ mms->bootinfo.board_id = -1;
115
int startsizecheck;
211
+ mms->bootinfo.loader_start = mmc->loader_start;
116
212
+ mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
117
- /* Negative levels are never allowed. */
213
+ mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
118
- if (level < 0) {
214
+ arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
119
+ /*
215
}
120
+ * Negative levels are usually not allowed...
216
121
+ * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
217
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
122
+ * begins with level -1. Note that previous feature tests will have
218
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
123
+ * eliminated this combination if it is not enabled.
219
/* Found the entry for "system memory" */
124
+ */
220
mc->default_ram_size = p->size;
125
+ if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
221
mc->default_ram_id = p->name;
126
return false;
222
+ mmc->loader_start = p->base;
127
}
223
return;
128
129
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
130
ARMMMUIdx mmu_idx, bool data)
131
{
132
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
133
- bool epd, hpd, using16k, using64k, tsz_oob;
134
- int select, tsz, tbi, max_tsz, min_tsz, ps;
135
+ bool epd, hpd, using16k, using64k, tsz_oob, ds;
136
+ int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
137
+ ARMCPU *cpu = env_archcpu(env);
138
139
if (!regime_has_2_ranges(mmu_idx)) {
140
select = 0;
141
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
142
hpd = extract32(tcr, 24, 1);
143
}
144
epd = false;
145
+ sh = extract32(tcr, 12, 2);
146
ps = extract32(tcr, 16, 3);
147
+ ds = extract64(tcr, 32, 1);
148
} else {
149
/*
150
* Bit 55 is always between the two regions, and is canonical for
151
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
152
if (!select) {
153
tsz = extract32(tcr, 0, 6);
154
epd = extract32(tcr, 7, 1);
155
+ sh = extract32(tcr, 12, 2);
156
using64k = extract32(tcr, 14, 1);
157
using16k = extract32(tcr, 15, 1);
158
hpd = extract64(tcr, 41, 1);
159
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
160
using64k = tg == 3;
161
tsz = extract32(tcr, 16, 6);
162
epd = extract32(tcr, 23, 1);
163
+ sh = extract32(tcr, 28, 2);
164
hpd = extract64(tcr, 42, 1);
165
}
166
ps = extract64(tcr, 32, 3);
167
+ ds = extract64(tcr, 59, 1);
168
}
169
170
- if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
171
+ if (cpu_isar_feature(aa64_st, cpu)) {
172
max_tsz = 48 - using64k;
173
} else {
174
max_tsz = 39;
175
}
176
177
+ /*
178
+ * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
179
+ * adjust the effective value of DS, as documented.
180
+ */
181
min_tsz = 16;
182
if (using64k) {
183
- if (cpu_isar_feature(aa64_lva, env_archcpu(env))) {
184
+ if (cpu_isar_feature(aa64_lva, cpu)) {
185
+ min_tsz = 12;
186
+ }
187
+ ds = false;
188
+ } else if (ds) {
189
+ switch (mmu_idx) {
190
+ case ARMMMUIdx_Stage2:
191
+ case ARMMMUIdx_Stage2_S:
192
+ if (using16k) {
193
+ ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu);
194
+ } else {
195
+ ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu);
196
+ }
197
+ break;
198
+ default:
199
+ if (using16k) {
200
+ ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu);
201
+ } else {
202
+ ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu);
203
+ }
204
+ break;
205
+ }
206
+ if (ds) {
207
min_tsz = 12;
208
}
224
}
209
}
225
}
210
- /* TODO: FEAT_LPA2 */
226
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
211
212
if (tsz > max_tsz) {
213
tsz = max_tsz;
214
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
215
return (ARMVAParameters) {
216
.tsz = tsz,
217
.ps = ps,
218
+ .sh = sh,
219
.select = select,
220
.tbi = tbi,
221
.epd = epd,
222
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
223
.using16k = using16k,
224
.using64k = using64k,
225
.tsz_oob = tsz_oob,
226
+ .ds = ds,
227
};
227
};
228
}
228
229
229
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
230
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
230
- mc->default_cpus = 2;
231
* VTCR_EL2.SL0 field (whose interpretation depends on the page size)
231
- mc->min_cpus = mc->default_cpus;
232
*/
232
- mc->max_cpus = mc->default_cpus;
233
uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
234
+ uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1);
235
uint32_t startlevel;
236
bool ok;
237
238
- if (!aarch64 || stride == 9) {
239
+ /* SL2 is RES0 unless DS=1 & 4kb granule. */
240
+ if (param.ds && stride == 9 && sl2) {
241
+ if (sl0 != 0) {
242
+ level = 0;
243
+ fault_type = ARMFault_Translation;
244
+ goto do_fault;
245
+ }
246
+ startlevel = -1;
247
+ } else if (!aarch64 || stride == 9) {
248
/* AArch32 or 4KB pages */
249
startlevel = 2 - sl0;
250
251
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
252
* for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
253
* or an AddressSize fault is raised. So for v8 we extract those SBZ
254
* bits as part of the address, which will be checked via outputsize.
255
- * For AArch64, the address field always goes up to bit 47 (with extra
256
- * bits for FEAT_LPA placed elsewhere). AArch64 implies v8.
257
+ * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
258
+ * the highest bits of a 52-bit output are placed elsewhere.
259
*/
260
- if (arm_feature(env, ARM_FEATURE_V8)) {
261
+ if (param.ds) {
262
+ descaddrmask = MAKE_64BIT_MASK(0, 50);
263
+ } else if (arm_feature(env, ARM_FEATURE_V8)) {
264
descaddrmask = MAKE_64BIT_MASK(0, 48);
265
} else {
266
descaddrmask = MAKE_64BIT_MASK(0, 40);
267
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
268
269
/*
270
* For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
271
- * of descriptor. Otherwise, if descaddr is out of range, raise
272
- * AddressSizeFault.
273
+ * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
274
+ * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
275
+ * raise AddressSizeFault.
276
*/
277
if (outputsize > 48) {
278
- descaddr |= extract64(descriptor, 12, 4) << 48;
279
+ if (param.ds) {
280
+ descaddr |= extract64(descriptor, 8, 2) << 50;
281
+ } else {
282
+ descaddr |= extract64(descriptor, 12, 4) << 48;
283
+ }
284
} else if (descaddr >> outputsize) {
285
fault_type = ARMFault_AddressSize;
286
goto do_fault;
287
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
288
assert(attrindx <= 7);
289
cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
290
}
291
- cacheattrs->shareability = extract32(attrs, 6, 2);
292
+
293
+ /*
233
+ /*
294
+ * For FEAT_LPA2 and effective DS, the SH field in the attributes
234
+ * In the real FPGA image there are always two cores, but the standard
295
+ * was re-purposed for output address bits. The SH attribute in
235
+ * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
296
+ * that case comes from TCR_ELx, which we extracted earlier.
236
+ * that the second core is held in reset and halted. Many images built for
237
+ * the board do not expect the second core to run at startup (especially
238
+ * since on the real FPGA image it is not possible to use LDREX/STREX
239
+ * in RAM between the two cores, so a true SMP setup isn't supported).
240
+ *
241
+ * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
242
+ * with the default being -smp 1. This seems a more intuitive UI for
243
+ * QEMU users than, for instance, having a machine property to allow
244
+ * the user to set the initial value of the SYSCON 0x000 register.
297
+ */
245
+ */
298
+ if (param.ds) {
246
+ mc->default_cpus = 1;
299
+ cacheattrs->shareability = param.sh;
247
+ mc->min_cpus = 1;
300
+ } else {
248
+ mc->max_cpus = 2;
301
+ cacheattrs->shareability = extract32(attrs, 6, 2);
249
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
302
+ }
250
mc->valid_cpu_types = valid_cpu_types;
303
251
mmc->raminfo = an536_raminfo;
304
*phys_ptr = descaddr;
305
*page_size_ptr = page_size;
306
--
252
--
307
2.25.1
253
2.34.1
diff view generated by jsdifflib
[PULL 25/26] ui/cocoa.m: Fix updateUIInfo threading issues
[PULL 32/35] hw/arm/mps3r: Add UARTs
1
The updateUIInfo method makes Cocoa API calls. It also calls back
1
This board has a lot of UARTs: there is one UART per CPU in the
2
into QEMU functions like dpy_set_ui_info(). To do this safely, we
2
per-CPU peripheral part of the address map, whose interrupts are
3
need to follow two rules:
3
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
4
* Cocoa API calls are made on the Cocoa UI thread
4
normal part of the peripheral space, whose interrupts are shared
5
* When calling back into QEMU we must hold the iothread lock
5
peripheral interrupts.
6
6
7
Fix the places where we got this wrong, by taking the iothread lock
7
Connect and wire them all up; this involves some OR gates where
8
while executing updateUIInfo, and moving the call in cocoa_switch()
8
multiple overflow interrupts are wired into one GIC input.
9
inside the dispatch_async block.
10
11
Some of the Cocoa UI methods which call updateUIInfo are invoked as
12
part of the initial application startup, while we're still doing the
13
little cross-thread dance described in the comment just above
14
call_qemu_main(). This meant they were calling back into the QEMU UI
15
layer before we'd actually finished initializing our display and
16
registered the DisplayChangeListener, which isn't really valid. Once
17
updateUIInfo takes the iothread lock, we no longer get away with
18
this, because during this startup phase the iothread lock is held by
19
the QEMU main-loop thread which is waiting for us to finish our
20
display initialization. So we must suppress updateUIInfo until
21
applicationDidFinishLaunching allows the QEMU main-loop thread to
22
continue.
23
9
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
26
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
12
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
27
Message-id: 20220224101330.967429-2-peter.maydell@linaro.org
28
---
13
---
29
ui/cocoa.m | 25 ++++++++++++++++++++++---
14
hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
30
1 file changed, 22 insertions(+), 3 deletions(-)
15
1 file changed, 94 insertions(+)
31
16
32
diff --git a/ui/cocoa.m b/ui/cocoa.m
17
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
33
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
34
--- a/ui/cocoa.m
19
--- a/hw/arm/mps3r.c
35
+++ b/ui/cocoa.m
20
+++ b/hw/arm/mps3r.c
36
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
21
@@ -XXX,XX +XXX,XX @@
22
#include "qapi/qmp/qlist.h"
23
#include "exec/address-spaces.h"
24
#include "cpu.h"
25
+#include "sysemu/sysemu.h"
26
#include "hw/boards.h"
27
+#include "hw/or-irq.h"
28
#include "hw/qdev-properties.h"
29
#include "hw/arm/boot.h"
30
#include "hw/arm/bsa.h"
31
+#include "hw/char/cmsdk-apb-uart.h"
32
#include "hw/intc/arm_gicv3.h"
33
34
/* Define the layout of RAM and ROM in a board */
35
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
36
37
#define MPS3R_RAM_MAX 9
38
#define MPS3R_CPU_MAX 2
39
+#define MPS3R_UART_MAX 4 /* shared UART count */
40
41
#define PERIPHBASE 0xf0000000
42
#define NUM_SPIS 96
43
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
44
MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
45
MemoryRegion cpu_ram[MPS3R_CPU_MAX];
46
GICv3State gic;
47
+ /* per-CPU UARTs followed by the shared UARTs */
48
+ CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
49
+ OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
50
+ OrIRQState uart_oflow;
51
};
52
53
#define TYPE_MPS3R_MACHINE "mps3r"
54
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
55
56
OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
57
58
+/*
59
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
60
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
61
+ * model we just roll them all into one.
62
+ */
63
+#define CLK_FRQ 50000000
64
+
65
static const RAMInfo an536_raminfo[] = {
66
{
67
.name = "ATCM",
68
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
37
}
69
}
38
}
70
}
39
71
40
-- (void) updateUIInfo
72
+/*
41
+- (void) updateUIInfoLocked
73
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
42
{
74
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
43
+ /* Must be called with the iothread lock, i.e. via updateUIInfo */
75
+ */
44
NSSize frameSize;
76
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
45
QemuUIInfo info;
77
+ hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
46
78
+ qemu_irq txoverirq, qemu_irq rxoverirq,
47
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
79
+ qemu_irq combirq)
48
dpy_set_ui_info(dcl.con, &info, TRUE);
49
}
50
51
+- (void) updateUIInfo
52
+{
80
+{
53
+ if (!allow_events) {
81
+ g_autofree char *s = g_strdup_printf("uart%d", uartno);
54
+ /*
82
+ SysBusDevice *sbd;
55
+ * Don't try to tell QEMU about UI information in the application
56
+ * startup phase -- we haven't yet registered dcl with the QEMU UI
57
+ * layer, and also trying to take the iothread lock would deadlock.
58
+ * When cocoa_display_init() does register the dcl, the UI layer
59
+ * will call cocoa_switch(), which will call updateUIInfo, so
60
+ * we don't lose any information here.
61
+ */
62
+ return;
63
+ }
64
+
83
+
65
+ with_iothread_lock(^{
84
+ assert(uartno < ARRAY_SIZE(mms->uart));
66
+ [self updateUIInfoLocked];
85
+ object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
67
+ });
86
+ TYPE_CMSDK_APB_UART);
87
+ qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
88
+ qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
89
+ sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
90
+ sysbus_realize(sbd, &error_fatal);
91
+ memory_region_add_subregion(mem, baseaddr,
92
+ sysbus_mmio_get_region(sbd, 0));
93
+ sysbus_connect_irq(sbd, 0, txirq);
94
+ sysbus_connect_irq(sbd, 1, rxirq);
95
+ sysbus_connect_irq(sbd, 2, txoverirq);
96
+ sysbus_connect_irq(sbd, 3, rxoverirq);
97
+ sysbus_connect_irq(sbd, 4, combirq);
68
+}
98
+}
69
+
99
+
70
- (void)viewDidMoveToWindow
100
static void mps3r_common_init(MachineState *machine)
71
{
101
{
72
[self updateUIInfo];
102
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
73
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
103
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
74
104
MemoryRegion *sysmem = get_system_memory();
75
COCOA_DEBUG("qemu_cocoa: cocoa_switch\n");
105
+ DeviceState *gicdev;
76
106
77
- [cocoaView updateUIInfo];
107
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
78
-
108
MemoryRegion *mr = mr_for_raminfo(mms, ri);
79
// The DisplaySurface will be freed as soon as this callback returns.
109
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
80
// We take a reference to the underlying pixman image here so it does
110
}
81
// not disappear from under our feet; the switchSurface method will
111
82
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
112
create_gic(mms, sysmem);
83
pixman_image_ref(image);
113
+ gicdev = DEVICE(&mms->gic);
84
114
+
85
dispatch_async(dispatch_get_main_queue(), ^{
115
+ /*
86
+ [cocoaView updateUIInfo];
116
+ * UARTs 0 and 1 are per-CPU; their interrupts are wired to
87
[cocoaView switchSurface:image];
117
+ * the relevant CPU's PPI 0..3, aka INTID 16..19
88
});
118
+ */
89
[pool release];
119
+ for (int i = 0; i < machine->smp.cpus; i++) {
120
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
121
+ g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
122
+ DeviceState *orgate;
123
+
124
+ /* The two overflow IRQs from the UART are ORed together into PPI 3 */
125
+ object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
126
+ TYPE_OR_IRQ);
127
+ orgate = DEVICE(&mms->cpu_uart_oflow[i]);
128
+ qdev_prop_set_uint32(orgate, "num-lines", 2);
129
+ qdev_realize(orgate, NULL, &error_fatal);
130
+ qdev_connect_gpio_out(orgate, 0,
131
+ qdev_get_gpio_in(gicdev, intidbase + 19));
132
+
133
+ create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
134
+ qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
135
+ qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
136
+ qdev_get_gpio_in(orgate, 0), /* txover */
137
+ qdev_get_gpio_in(orgate, 1), /* rxover */
138
+ qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
139
+ }
140
+ /*
141
+ * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
142
+ * together into IRQ 17
143
+ */
144
+ object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
145
+ &mms->uart_oflow, TYPE_OR_IRQ);
146
+ qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
147
+ MPS3R_UART_MAX * 2);
148
+ qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
149
+ qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
150
+ qdev_get_gpio_in(gicdev, 17));
151
+
152
+ for (int i = 0; i < MPS3R_UART_MAX; i++) {
153
+ hwaddr baseaddr = 0xe0205000 + i * 0x1000;
154
+ int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
155
+
156
+ create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
157
+ qdev_get_gpio_in(gicdev, txirq),
158
+ qdev_get_gpio_in(gicdev, rxirq),
159
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
160
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
161
+ qdev_get_gpio_in(gicdev, combirq));
162
+ }
163
164
mms->bootinfo.ram_size = machine->ram_size;
165
mms->bootinfo.board_id = -1;
90
--
166
--
91
2.25.1
167
2.34.1
168
169
diff view generated by jsdifflib
[PULL 24/26] target/arm: Report KVM's actual PSCI version to guest in dtb
[PULL 33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
1
When we're using KVM, the PSCI implementation is provided by the
1
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
2
kernel, but QEMU has to tell the guest about it via the device tree.
2
board. These are all simple devices that just need to be created and
3
Currently we look at the KVM_CAP_ARM_PSCI_0_2 capability to determine
3
wired up.
4
if the kernel is providing at least PSCI 0.2, but if the kernel
5
provides a newer version than that we will still only tell the guest
6
it has PSCI 0.2. (This is fairly harmless; it just means the guest
7
won't use newer parts of the PSCI API.)
8
9
The kernel exposes the specific PSCI version it is implementing via
10
the ONE_REG API; use this to report in the dtb that the PSCI
11
implementation is 1.0-compatible if appropriate. (The device tree
12
binding currently only distinguishes "pre-0.2", "0.2-compatible" and
13
"1.0-compatible".)
14
4
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Marc Zyngier <maz@kernel.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
7
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Reviewed-by: Andrew Jones <drjones@redhat.com>
20
Message-id: 20220224134655.1207865-1-peter.maydell@linaro.org
21
---
8
---
22
target/arm/kvm-consts.h | 1 +
9
hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
23
hw/arm/boot.c | 5 ++---
10
1 file changed, 59 insertions(+)
24
target/arm/kvm64.c | 12 ++++++++++++
25
3 files changed, 15 insertions(+), 3 deletions(-)
26
11
27
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
28
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/kvm-consts.h
14
--- a/hw/arm/mps3r.c
30
+++ b/target/arm/kvm-consts.h
15
+++ b/hw/arm/mps3r.c
31
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES);
16
@@ -XXX,XX +XXX,XX @@
32
17
#include "sysemu/sysemu.h"
33
#define QEMU_PSCI_VERSION_0_1 0x00001
18
#include "hw/boards.h"
34
#define QEMU_PSCI_VERSION_0_2 0x00002
19
#include "hw/or-irq.h"
35
+#define QEMU_PSCI_VERSION_1_0 0x10000
20
+#include "hw/qdev-clock.h"
36
#define QEMU_PSCI_VERSION_1_1 0x10001
21
#include "hw/qdev-properties.h"
37
22
#include "hw/arm/boot.h"
38
MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
23
#include "hw/arm/bsa.h"
39
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
24
#include "hw/char/cmsdk-apb-uart.h"
40
index XXXXXXX..XXXXXXX 100644
25
+#include "hw/i2c/arm_sbcon_i2c.h"
41
--- a/hw/arm/boot.c
26
#include "hw/intc/arm_gicv3.h"
42
+++ b/hw/arm/boot.c
27
+#include "hw/misc/unimp.h"
43
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
28
+#include "hw/timer/cmsdk-apb-dualtimer.h"
29
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
30
31
/* Define the layout of RAM and ROM in a board */
32
typedef struct RAMInfo {
33
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
34
CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
35
OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
36
OrIRQState uart_oflow;
37
+ CMSDKAPBWatchdog watchdog;
38
+ CMSDKAPBDualTimer dualtimer;
39
+ ArmSbconI2CState i2c[5];
40
+ Clock *clk;
41
};
42
43
#define TYPE_MPS3R_MACHINE "mps3r"
44
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
45
MemoryRegion *sysmem = get_system_memory();
46
DeviceState *gicdev;
47
48
+ mms->clk = clock_new(OBJECT(machine), "CLK");
49
+ clock_set_hz(mms->clk, CLK_FRQ);
50
+
51
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
52
MemoryRegion *mr = mr_for_raminfo(mms, ri);
53
memory_region_add_subregion(sysmem, ri->base, mr);
54
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
55
qdev_get_gpio_in(gicdev, combirq));
44
}
56
}
45
57
46
qemu_fdt_add_subnode(fdt, "/psci");
58
+ for (int i = 0; i < 4; i++) {
47
- if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 ||
59
+ /* CMSDK GPIO controllers */
48
- armcpu->psci_version == QEMU_PSCI_VERSION_1_1) {
60
+ g_autofree char *s = g_strdup_printf("gpio%d", i);
49
- if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) {
61
+ create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
50
+ if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) {
51
+ if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) {
52
const char comp[] = "arm,psci-0.2\0arm,psci";
53
qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
54
} else {
55
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/kvm64.c
58
+++ b/target/arm/kvm64.c
59
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
60
uint64_t mpidr;
61
ARMCPU *cpu = ARM_CPU(cs);
62
CPUARMState *env = &cpu->env;
63
+ uint64_t psciver;
64
65
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
66
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
67
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
68
}
69
}
70
71
+ /*
72
+ * KVM reports the exact PSCI version it is implementing via a
73
+ * special sysreg. If it is present, use its contents to determine
74
+ * what to report to the guest in the dtb (it is the PSCI version,
75
+ * in the same 15-bits major 16-bits minor format that PSCI_VERSION
76
+ * returns).
77
+ */
78
+ if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) {
79
+ cpu->psci_version = psciver;
80
+ }
62
+ }
81
+
63
+
82
/*
64
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
83
* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
65
+ TYPE_CMSDK_APB_WATCHDOG);
84
* Currently KVM has its own idea about MPIDR assignment, so we
66
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
67
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
68
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
69
+ qdev_get_gpio_in(gicdev, 0));
70
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
71
+
72
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
73
+ TYPE_CMSDK_APB_DUALTIMER);
74
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
76
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
77
+ qdev_get_gpio_in(gicdev, 3));
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
79
+ qdev_get_gpio_in(gicdev, 1));
80
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
81
+ qdev_get_gpio_in(gicdev, 2));
82
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
83
+
84
+ for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
85
+ static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
86
+ 0xe0103000, /* Audio */
87
+ 0xe0107000, /* Shield0 */
88
+ 0xe0108000, /* Shield1 */
89
+ 0xe0109000}; /* DDR4 EEPROM */
90
+ g_autofree char *s = g_strdup_printf("i2c%d", i);
91
+
92
+ object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
93
+ TYPE_ARM_SBCON_I2C);
94
+ sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
95
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
96
+ if (i != 2 && i != 3) {
97
+ /*
98
+ * internal-only bus: mark it full to avoid user-created
99
+ * i2c devices being plugged into it.
100
+ */
101
+ qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
102
+ }
103
+ }
104
+
105
mms->bootinfo.ram_size = machine->ram_size;
106
mms->bootinfo.board_id = -1;
107
mms->bootinfo.loader_start = mmc->loader_start;
85
--
108
--
86
2.25.1
109
2.34.1
110
111
diff view generated by jsdifflib
[PULL 14/26] target/arm: Honor TCR_ELx.{I}PS
[PULL 34/35] hw/arm/mps3r: Add remaining devices
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Add the remaining devices (or unimplemented-device stubs) for
2
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
3
QSPI write-config block, and ethernet.
2
4
3
This field controls the output (intermediate) physical address size
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
of the translation process. V8 requires to raise an AddressSize
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
fault if the page tables are programmed incorrectly, such that any
7
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
6
intermediate descriptor address, or the final translated address,
8
---
7
is out of range.
9
hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 74 insertions(+)
8
11
9
Add a PS field to ARMVAParameters, and properly compute outputsize
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
10
in get_phys_addr_lpae. Test the descaddr as extracted from TTBR
11
and from page table entries.
12
13
Restrict descaddrmask so that we won't raise the fault for v7.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20220301215958.157011-8-richard.henderson@linaro.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
target/arm/internals.h | 1 +
22
target/arm/helper.c | 72 ++++++++++++++++++++++++++++++++----------
23
2 files changed, 57 insertions(+), 16 deletions(-)
24
25
diff --git a/target/arm/internals.h b/target/arm/internals.h
26
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/internals.h
14
--- a/hw/arm/mps3r.c
28
+++ b/target/arm/internals.h
15
+++ b/hw/arm/mps3r.c
29
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
16
@@ -XXX,XX +XXX,XX @@
30
*/
17
#include "hw/char/cmsdk-apb-uart.h"
31
typedef struct ARMVAParameters {
18
#include "hw/i2c/arm_sbcon_i2c.h"
32
unsigned tsz : 8;
19
#include "hw/intc/arm_gicv3.h"
33
+ unsigned ps : 3;
20
+#include "hw/misc/mps2-scc.h"
34
unsigned select : 1;
21
+#include "hw/misc/mps2-fpgaio.h"
35
bool tbi : 1;
22
#include "hw/misc/unimp.h"
36
bool epd : 1;
23
+#include "hw/net/lan9118.h"
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
24
+#include "hw/rtc/pl031.h"
38
index XXXXXXX..XXXXXXX 100644
25
+#include "hw/ssi/pl022.h"
39
--- a/target/arm/helper.c
26
#include "hw/timer/cmsdk-apb-dualtimer.h"
40
+++ b/target/arm/helper.c
27
#include "hw/watchdog/cmsdk-apb-watchdog.h"
41
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
28
42
}
29
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
43
#endif /* !CONFIG_USER_ONLY */
30
CMSDKAPBWatchdog watchdog;
44
31
CMSDKAPBDualTimer dualtimer;
45
+/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
32
ArmSbconI2CState i2c[5];
46
+static const uint8_t pamax_map[] = {
33
+ PL022State spi[3];
47
+ [0] = 32,
34
+ MPS2SCC scc;
48
+ [1] = 36,
35
+ MPS2FPGAIO fpgaio;
49
+ [2] = 40,
36
+ UnimplementedDeviceState i2s_audio;
50
+ [3] = 42,
37
+ PL031State rtc;
51
+ [4] = 44,
38
Clock *clk;
52
+ [5] = 48,
39
};
40
41
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
42
}
43
};
44
45
+static const int an536_oscclk[] = {
46
+ 24000000, /* 24MHz reference for RTC and timers */
47
+ 50000000, /* 50MHz ACLK */
48
+ 50000000, /* 50MHz MCLK */
49
+ 50000000, /* 50MHz GPUCLK */
50
+ 24576000, /* 24.576MHz AUDCLK */
51
+ 23750000, /* 23.75MHz HDLCDCLK */
52
+ 100000000, /* 100MHz DDR4_REF_CLK */
53
+};
53
+};
54
+
54
+
55
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
55
static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
56
unsigned int arm_pamax(ARMCPU *cpu)
56
const RAMInfo *raminfo)
57
{
57
{
58
- static const unsigned int pamax_map[] = {
58
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
59
- [0] = 32,
59
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
60
- [1] = 36,
60
MemoryRegion *sysmem = get_system_memory();
61
- [2] = 40,
61
DeviceState *gicdev;
62
- [3] = 42,
62
+ QList *oscclk;
63
- [4] = 44,
63
64
- [5] = 48,
64
mms->clk = clock_new(OBJECT(machine), "CLK");
65
- };
65
clock_set_hz(mms->clk, CLK_FRQ);
66
unsigned int parange =
66
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
67
FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
68
69
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
70
{
71
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
72
bool epd, hpd, using16k, using64k, tsz_oob;
73
- int select, tsz, tbi, max_tsz, min_tsz;
74
+ int select, tsz, tbi, max_tsz, min_tsz, ps;
75
76
if (!regime_has_2_ranges(mmu_idx)) {
77
select = 0;
78
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
79
hpd = extract32(tcr, 24, 1);
80
}
67
}
81
epd = false;
82
+ ps = extract32(tcr, 16, 3);
83
} else {
84
/*
85
* Bit 55 is always between the two regions, and is canonical for
86
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
87
epd = extract32(tcr, 23, 1);
88
hpd = extract64(tcr, 42, 1);
89
}
90
+ ps = extract64(tcr, 32, 3);
91
}
68
}
92
69
93
if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
70
+ for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
94
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
71
+ g_autofree char *s = g_strdup_printf("spi%d", i);
95
72
+ hwaddr baseaddr = 0xe0104000 + i * 0x1000;
96
return (ARMVAParameters) {
97
.tsz = tsz,
98
+ .ps = ps,
99
.select = select,
100
.tbi = tbi,
101
.epd = epd,
102
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
103
104
/* TODO: This code does not support shareability levels. */
105
if (aarch64) {
106
+ int ps;
107
+
73
+
108
param = aa64_va_parameters(env, address, mmu_idx,
74
+ object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
109
access_type != MMU_INST_FETCH);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
110
level = 0;
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
111
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
77
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
112
78
+ qdev_get_gpio_in(gicdev, 22 + i));
113
addrsize = 64 - 8 * param.tbi;
79
+ }
114
inputsize = 64 - param.tsz;
115
- outputsize = arm_pamax(cpu);
116
+
80
+
117
+ /*
81
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
118
+ * Bound PS by PARANGE to find the effective output address size.
82
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
119
+ * ID_AA64MMFR0 is a read-only register so values outside of the
83
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
120
+ * supported mappings can be considered an implementation error.
84
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
121
+ */
85
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
122
+ ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
86
+ oscclk = qlist_new();
123
+ ps = MIN(ps, param.ps);
87
+ for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
124
+ assert(ps < ARRAY_SIZE(pamax_map));
88
+ qlist_append_int(oscclk, an536_oscclk[i]);
125
+ outputsize = pamax_map[ps];
89
+ }
126
} else {
90
+ qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
127
param = aa32_va_parameters(env, address, mmu_idx);
91
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
128
level = 1;
92
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
129
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
93
+
130
94
+ create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
131
/* Now we can extract the actual base address from the TTBR */
95
+
132
descaddr = extract64(ttbr, 0, 48);
96
+ object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
97
+ TYPE_MPS2_FPGAIO);
98
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
99
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
100
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
101
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
102
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
104
+
105
+ create_unimplemented_device("clcd", 0xe0209000, 0x1000);
106
+
107
+ object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
108
+ sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
109
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
110
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
111
+ qdev_get_gpio_in(gicdev, 4));
133
+
112
+
134
+ /*
113
+ /*
135
+ * If the base address is out of range, raise AddressSizeFault.
114
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
136
+ * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
115
+ * except that it doesn't support the checksum-offload feature.
137
+ * but we've just cleared the bits above 47, so simplify the test.
138
+ */
116
+ */
139
+ if (descaddr >> outputsize) {
117
+ lan9118_init(0xe0300000,
140
+ level = 0;
118
+ qdev_get_gpio_in(gicdev, 18));
141
+ fault_type = ARMFault_AddressSize;
142
+ goto do_fault;
143
+ }
144
+
119
+
145
/*
120
+ create_unimplemented_device("usb", 0xe0301000, 0x1000);
146
* We rely on this masking to clear the RES0 bits at the bottom of the TTBR
121
+ create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
147
* and also to mask out CnP (bit 0) which could validly be non-zero.
148
*/
149
descaddr &= ~indexmask;
150
151
- /* The address field in the descriptor goes up to bit 39 for ARMv7
152
- * but up to bit 47 for ARMv8, but we use the descaddrmask
153
- * up to bit 39 for AArch32, because we don't need other bits in that case
154
- * to construct next descriptor address (anyway they should be all zeroes).
155
+ /*
156
+ * For AArch32, the address field in the descriptor goes up to bit 39
157
+ * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
158
+ * or an AddressSize fault is raised. So for v8 we extract those SBZ
159
+ * bits as part of the address, which will be checked via outputsize.
160
+ * For AArch64, the address field always goes up to bit 47 (with extra
161
+ * bits for FEAT_LPA placed elsewhere). AArch64 implies v8.
162
*/
163
- descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
164
- ~indexmask_grainsize;
165
+ if (arm_feature(env, ARM_FEATURE_V8)) {
166
+ descaddrmask = MAKE_64BIT_MASK(0, 48);
167
+ } else {
168
+ descaddrmask = MAKE_64BIT_MASK(0, 40);
169
+ }
170
+ descaddrmask &= ~indexmask_grainsize;
171
172
/* Secure accesses start with the page table in secure memory and
173
* can be downgraded to non-secure at any step. Non-secure accesses
174
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
175
/* Invalid, or the Reserved level 3 encoding */
176
goto do_fault;
177
}
178
+
122
+
179
descaddr = descriptor & descaddrmask;
123
mms->bootinfo.ram_size = machine->ram_size;
180
+ if (descaddr >> outputsize) {
124
mms->bootinfo.board_id = -1;
181
+ fault_type = ARMFault_AddressSize;
125
mms->bootinfo.loader_start = mmc->loader_start;
182
+ goto do_fault;
183
+ }
184
185
if ((descriptor & 2) && (level < 3)) {
186
/* Table entry. The top five bits are attributes which may
187
--
126
--
188
2.25.1
127
2.34.1
189
128
190
129
diff view generated by jsdifflib
[PULL 02/26] hw/arm/mps2-tz.c: Update AN547 documentation URL
[PULL 35/35] docs: Add documentation for the mps3-an536 board
1
The AN547 application note URL has changed: update our comment
1
Add documentation for the mps3-an536 board type.
2
accordingly. (Rev B is still downloadable from the old URL,
3
but there is a new Rev C of the document now.)
4
2
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
8
Message-id: 20220221094144.426191-1-peter.maydell@linaro.org
9
---
6
---
10
hw/arm/mps2-tz.c | 2 +-
7
docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
11
1 file changed, 1 insertion(+), 1 deletion(-)
8
1 file changed, 34 insertions(+), 3 deletions(-)
12
9
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
10
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/mps2-tz.c
12
--- a/docs/system/arm/mps2.rst
16
+++ b/hw/arm/mps2-tz.c
13
+++ b/docs/system/arm/mps2.rst
17
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
18
* Application Note AN524:
15
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
19
* https://developer.arm.com/documentation/dai0524/latest/
16
-=========================================================================================================================================================
20
* Application Note AN547:
17
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
21
- * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf
18
+=========================================================================================================================================================================
22
+ * https://developer.arm.com/documentation/dai0547/latest/
19
23
*
20
-These board models all use Arm M-profile CPUs.
24
* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
21
+These board models use Arm M-profile or R-profile CPUs.
25
* (ARM ECM0601256) for the details of some of the device layout:
22
23
The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
24
bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
25
@@ -XXX,XX +XXX,XX @@ FPGA image.
26
27
QEMU models the following FPGA images:
28
29
+FPGA images using M-profile CPUs:
30
+
31
``mps2-an385``
32
Cortex-M3 as documented in Arm Application Note AN385
33
``mps2-an386``
34
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
35
``mps3-an547``
36
Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
37
38
+FPGA images using R-profile CPUs:
39
+
40
+``mps3-an536``
41
+ Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
42
+
43
Differences between QEMU and real hardware:
44
45
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
46
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
47
flash, but only as simple ROM, so attempting to rewrite the flash
48
from the guest will fail
49
- QEMU does not model the USB controller in MPS3 boards
50
+- AN536 does not support runtime control of CPU reset and halt via
51
+ the SCC CFG_REG0 register.
52
+- AN536 does not support enabling or disabling the flash and ATCM
53
+ interfaces via the SCC CFG_REG1 register.
54
+- AN536 does not support setting of the initial vector table
55
+ base address via the SCC CFG_REG6 and CFG_REG7 register config,
56
+ and does not provide a mechanism for specifying these values at
57
+ startup, so all guest images must be built to start from TCM
58
+ (i.e. to expect the interrupt vector base at 0 from reset).
59
+- AN536 defaults to only creating a single CPU; this is the equivalent
60
+ of the way the real FPGA image usually runs with the second Cortex-R52
61
+ held in halt via the initial SCC CFG_REG0 register setting. You can
62
+ create the second CPU with ``-smp 2``; both CPUs will then start
63
+ execution immediately on startup.
64
+
65
+Note that for the AN536 the first UART is accessible only by
66
+CPU0, and the second UART is accessible only by CPU1. The
67
+first UART accessible shared between both CPUs is the third
68
+UART. Guest software might therefore be built to use either
69
+the first UART or the third UART; if you don't see any output
70
+from the UART you are looking at, try one of the others.
71
+(Even if the AN536 machine is started with a single CPU and so
72
+no "CPU1-only UART", the UART numbering remains the same,
73
+with the third UART being the first of the shared ones.)
74
75
Machine-specific options
76
""""""""""""""""""""""""
26
--
77
--
27
2.25.1
78
2.34.1
28
79
29
80
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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