[PULL 0/3] tcg patch queue
[PULL v2 00/47] tcg patch queue
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The following changes since commit 00483d386901173e84c7965f9f0d678791a75e01:
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v2: Fix bsd-user signal.c Werror.
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I've conformed that it merges well with Warner's bsd-user pull.
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Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into staging (2022-02-28 11:27:16 +0000)
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r~
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The following changes since commit da1034094d375afe9e3d8ec8980550ea0f06f7e0:
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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-10-03 07:43:44 -0400)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220228
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231004
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for you to fetch changes up to 2ccf40f00e3f29d85d4ff48a9a98870059002290:
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for you to fetch changes up to 79de3960ae1e322835112755d99187ee9b63a270:
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tcg/tci: Use tcg_out_ldst in tcg_out_st (2022-02-28 08:04:10 -1000)
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tcg/loongarch64: Fix buid error (2023-10-04 11:03:54 -0700)
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19
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----------------------------------------------------------------
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----------------------------------------------------------------
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Fix typecode generation for tcg helpers
21
accel: Introduce AccelClass::cpu_common_[un]realize
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Fix single stepping into interrupt handlers
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accel: Target agnostic code movement
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Fix out-of-range offsets for stores in TCI
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accel/tcg: Cleanups to use CPUState instead of CPUArchState
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accel/tcg: Move CPUNegativeOffsetState into CPUState
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tcg: Split out tcg init functions to tcg/startup.h
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linux-user/hppa: Fix struct target_sigcontext layout
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build: Remove --enable-gprof
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----------------------------------------------------------------
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----------------------------------------------------------------
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Luc Michel (1):
30
Anton Johansson (9):
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accel/tcg/cpu-exec: Fix precise single-stepping after interrupt
31
target/arm: Replace TARGET_PAGE_ENTRY_EXTRA
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32
accel/tcg: Modify tlb_*() to use CPUState
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Richard Henderson (2):
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accel/tcg: Modify probe_access_internal() to use CPUState
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tcg: Remove dh_alias indirection for dh_typecode
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accel/tcg: Modify memory access functions to use CPUState
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tcg/tci: Use tcg_out_ldst in tcg_out_st
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accel/tcg: Modify atomic_mmu_lookup() to use CPUState
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accel/tcg: Use CPUState in atomicity helpers
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include/exec/helper-head.h | 19 ++++++++++---------
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accel/tcg: Remove env_tlb()
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target/hppa/helper.h | 2 ++
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accel/tcg: Unify user and softmmu do_[st|ld]*_mmu()
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target/i386/ops_sse_header.h | 3 +++
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accel/tcg: move ld/st helpers to ldst_common.c.inc
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target/m68k/helper.h | 1 +
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target/ppc/helper.h | 3 +++
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Philippe Mathieu-Daudé (19):
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accel/tcg/cpu-exec.c | 8 ++++++--
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accel: Rename accel_cpu_realizefn() -> accel_cpu_realize()
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tcg/tci/tcg-target.c.inc | 5 ++---
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accel: Rename AccelCPUClass::cpu_realizefn() -> cpu_target_realize()
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7 files changed, 27 insertions(+), 14 deletions(-)
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accel: Rename accel_cpu_realize() -> accel_cpu_common_realize()
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accel: Introduce accel_cpu_common_unrealize() stub
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accel: Declare AccelClass::cpu_common_[un]realize() handlers
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accel/tcg: Have tcg_exec_realizefn() return a boolean
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accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG
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exec: Make EXCP_FOO definitions target agnostic
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exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h'
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accel/tcg: Restrict dump_exec_info() declaration
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accel: Make accel-blocker.o target agnostic
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accel: Rename accel-common.c -> accel-target.c
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exec: Rename cpu.c -> cpu-target.c
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exec: Rename target specific page-vary.c -> page-vary-target.c
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accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h'
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accel/tcg: Make monitor.c a target-agnostic unit
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accel/tcg: Make icount.o a target agnostic unit
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accel/tcg: Make cpu-exec-common.c a target agnostic unit
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tests/avocado: Re-enable MIPS Malta tests (GitLab issue #1884 fixed)
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Richard Henderson (18):
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accel/tcg: Move CPUTLB definitions from cpu-defs.h
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qom: Propagate alignment through type system
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target/arm: Remove size and alignment for cpu subclasses
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target/*: Add instance_align to all cpu base classes
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accel/tcg: Validate placement of CPUNegativeOffsetState
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accel/tcg: Move CPUNegativeOffsetState into CPUState
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accel/tcg: Remove CPUState.icount_decr_ptr
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accel/tcg: Move can_do_io to CPUNegativeOffsetState
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accel/tcg: Remove cpu_neg()
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tcg: Rename cpu_env to tcg_env
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accel/tcg: Replace CPUState.env_ptr with cpu_env()
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accel/tcg: Remove cpu_set_cpustate_pointers
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accel/tcg: Remove env_neg()
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tcg: Remove TCGContext.tlb_fast_offset
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tcg: Remove argument to tcg_prologue_init
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tcg: Split out tcg init functions to tcg/startup.h
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linux-user/hppa: Fix struct target_sigcontext layout
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build: Remove --enable-gprof
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gaosong (1):
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tcg/loongarch64: Fix buid error
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MAINTAINERS | 7 +-
86
docs/about/deprecated.rst | 14 -
87
meson.build | 18 +-
88
accel/tcg/atomic_template.h | 20 +-
89
accel/tcg/internal-common.h | 28 +
90
accel/tcg/{internal.h => internal-target.h} | 21 +-
91
bsd-user/bsd-proc.h | 3 -
92
include/exec/cpu-all.h | 67 +-
93
include/exec/cpu-common.h | 39 +
94
include/exec/cpu-defs.h | 138 ---
95
include/exec/cpu_ldst.h | 8 +-
96
include/exec/exec-all.h | 32 +-
97
include/hw/core/accel-cpu.h | 2 +-
98
include/hw/core/cpu.h | 171 ++-
99
include/qemu/accel.h | 12 +-
100
include/tcg/startup.h | 58 +
101
include/tcg/tcg.h | 6 +-
102
target/alpha/cpu.h | 1 -
103
target/arm/common-semi-target.h | 2 +-
104
target/arm/cpu-param.h | 12 -
105
target/arm/cpu.h | 1 -
106
target/arm/tcg/translate-a32.h | 2 +-
107
target/arm/tcg/translate-a64.h | 4 +-
108
target/arm/tcg/translate.h | 16 +-
109
target/avr/cpu.h | 1 -
110
target/cris/cpu.h | 1 -
111
target/hexagon/cpu.h | 2 +-
112
target/hexagon/gen_tcg.h | 120 +-
113
target/hexagon/gen_tcg_hvx.h | 20 +-
114
target/hexagon/macros.h | 8 +-
115
target/hppa/cpu.h | 1 -
116
target/i386/cpu.h | 1 -
117
target/loongarch/cpu.h | 1 -
118
target/m68k/cpu.h | 1 -
119
target/microblaze/cpu.h | 6 +-
120
target/mips/cpu.h | 4 +-
121
target/mips/tcg/translate.h | 6 +-
122
target/nios2/cpu.h | 1 -
123
target/openrisc/cpu.h | 1 -
124
target/ppc/cpu.h | 1 -
125
target/riscv/cpu.h | 2 +-
126
target/rx/cpu.h | 1 -
127
target/s390x/cpu.h | 1 -
128
target/sh4/cpu.h | 1 -
129
target/sparc/cpu.h | 1 -
130
target/tricore/cpu.h | 1 -
131
target/xtensa/cpu.h | 3 +-
132
accel/{accel-common.c => accel-target.c} | 27 +-
133
accel/dummy-cpus.c | 2 +-
134
accel/hvf/hvf-accel-ops.c | 2 +-
135
accel/kvm/kvm-accel-ops.c | 2 +-
136
accel/tcg/cpu-exec-common.c | 5 +-
137
accel/tcg/cpu-exec.c | 31 +-
138
accel/tcg/cputlb.c | 787 +++++-------
139
softmmu/icount.c => accel/tcg/icount-common.c | 7 +-
140
accel/tcg/monitor.c | 2 +-
141
accel/tcg/plugin-gen.c | 10 +-
142
accel/tcg/tb-maint.c | 3 +-
143
accel/tcg/tcg-accel-ops-icount.c | 8 +-
144
accel/tcg/tcg-accel-ops-mttcg.c | 4 +-
145
accel/tcg/tcg-accel-ops-rr.c | 6 +-
146
accel/tcg/tcg-accel-ops.c | 2 +-
147
accel/tcg/tcg-all.c | 8 +-
148
accel/tcg/translate-all.c | 15 +-
149
accel/tcg/translator.c | 24 +-
150
accel/tcg/user-exec.c | 279 +----
151
bsd-user/main.c | 6 +-
152
bsd-user/signal.c | 14 +-
153
cpus-common.c => cpu-common.c | 0
154
cpu.c => cpu-target.c | 13 +-
155
gdbstub/gdbstub.c | 4 +-
156
gdbstub/user-target.c | 2 +-
157
hw/core/cpu-common.c | 6 +-
158
hw/i386/kvm/clock.c | 2 +-
159
hw/intc/mips_gic.c | 2 +-
160
hw/intc/riscv_aclint.c | 12 +-
161
hw/intc/riscv_imsic.c | 2 +-
162
hw/ppc/e500.c | 4 +-
163
hw/ppc/spapr.c | 2 +-
164
linux-user/elfload.c | 4 +-
165
linux-user/exit.c | 6 -
166
linux-user/hppa/signal.c | 2 +-
167
linux-user/i386/cpu_loop.c | 2 +-
168
linux-user/main.c | 8 +-
169
linux-user/signal.c | 20 +-
170
linux-user/syscall.c | 2 +-
171
monitor/hmp-cmds-target.c | 2 +-
172
page-vary.c => page-vary-target.c | 0
173
qom/object.c | 14 +
174
semihosting/arm-compat-semi.c | 6 +-
175
semihosting/syscalls.c | 28 +-
176
softmmu/watchpoint.c | 2 +-
177
target/alpha/cpu.c | 3 +-
178
target/alpha/translate.c | 146 +--
179
target/arm/cpu.c | 12 +-
180
target/arm/cpu64.c | 4 -
181
target/arm/helper.c | 2 +-
182
target/arm/ptw.c | 4 +-
183
target/arm/tcg/mte_helper.c | 2 +-
184
target/arm/tcg/sve_helper.c | 2 +-
185
target/arm/tcg/tlb_helper.c | 4 +-
186
target/arm/tcg/translate-a64.c | 384 +++---
187
target/arm/tcg/translate-m-nocp.c | 24 +-
188
target/arm/tcg/translate-mve.c | 52 +-
189
target/arm/tcg/translate-neon.c | 78 +-
190
target/arm/tcg/translate-sme.c | 8 +-
191
target/arm/tcg/translate-sve.c | 172 +--
192
target/arm/tcg/translate-vfp.c | 56 +-
193
target/arm/tcg/translate.c | 234 ++--
194
target/avr/cpu.c | 3 +-
195
target/avr/translate.c | 66 +-
196
target/cris/cpu.c | 3 +-
197
target/cris/translate.c | 72 +-
198
target/hexagon/cpu.c | 4 +-
199
target/hexagon/genptr.c | 36 +-
200
target/hexagon/idef-parser/parser-helpers.c | 2 +-
201
target/hexagon/translate.c | 52 +-
202
target/hppa/cpu.c | 2 +-
203
target/hppa/mem_helper.c | 2 +-
204
target/hppa/translate.c | 161 ++-
205
target/i386/cpu.c | 2 +-
206
target/i386/hvf/hvf-cpu.c | 2 +-
207
target/i386/kvm/kvm-cpu.c | 4 +-
208
target/i386/nvmm/nvmm-all.c | 14 +-
209
target/i386/tcg/sysemu/excp_helper.c | 2 +-
210
target/i386/tcg/tcg-cpu.c | 4 +-
211
target/i386/tcg/translate.c | 584 ++++-----
212
target/i386/whpx/whpx-all.c | 26 +-
213
target/loongarch/cpu.c | 9 +-
214
target/loongarch/translate.c | 22 +-
215
target/m68k/cpu.c | 9 +-
216
target/m68k/translate.c | 306 ++---
217
target/microblaze/cpu.c | 2 +-
218
target/microblaze/translate.c | 52 +-
219
target/mips/cpu.c | 2 +-
220
target/mips/tcg/lcsr_translate.c | 6 +-
221
target/mips/tcg/msa_translate.c | 34 +-
222
target/mips/tcg/mxu_translate.c | 4 +-
223
target/mips/tcg/sysemu/mips-semi.c | 4 +-
224
target/mips/tcg/translate.c | 1288 ++++++++++----------
225
target/mips/tcg/vr54xx_translate.c | 2 +-
226
target/nios2/cpu.c | 5 +-
227
target/nios2/translate.c | 52 +-
228
target/openrisc/cpu.c | 7 +-
229
target/openrisc/translate.c | 86 +-
230
target/ppc/cpu_init.c | 1 -
231
target/ppc/excp_helper.c | 10 +-
232
target/ppc/translate.c | 366 +++---
233
target/riscv/cpu.c | 8 +-
234
target/riscv/translate.c | 56 +-
235
target/rx/cpu.c | 5 +-
236
target/rx/translate.c | 58 +-
237
target/s390x/cpu.c | 2 -
238
target/s390x/tcg/translate.c | 426 +++----
239
target/sh4/cpu.c | 3 +-
240
target/sh4/op_helper.c | 2 +-
241
target/sh4/translate.c | 128 +-
242
target/sparc/cpu.c | 3 +-
243
target/sparc/translate.c | 332 ++---
244
target/tricore/cpu.c | 10 +-
245
target/tricore/translate.c | 230 ++--
246
target/xtensa/cpu.c | 2 +-
247
target/xtensa/translate.c | 192 +--
248
tcg/tcg-op-gvec.c | 300 ++---
249
tcg/tcg-op-ldst.c | 22 +-
250
tcg/tcg-op.c | 2 +-
251
tcg/tcg.c | 23 +-
252
accel/tcg/ldst_atomicity.c.inc | 88 +-
253
accel/tcg/ldst_common.c.inc | 225 ++++
254
target/cris/translate_v10.c.inc | 28 +-
255
target/i386/tcg/decode-new.c.inc | 4 +-
256
target/i386/tcg/emit.c.inc | 262 ++--
257
target/loongarch/insn_trans/trans_atomic.c.inc | 4 +-
258
target/loongarch/insn_trans/trans_branch.c.inc | 2 +-
259
target/loongarch/insn_trans/trans_extra.c.inc | 10 +-
260
target/loongarch/insn_trans/trans_farith.c.inc | 6 +-
261
target/loongarch/insn_trans/trans_fcmp.c.inc | 8 +-
262
target/loongarch/insn_trans/trans_fmemory.c.inc | 8 +-
263
target/loongarch/insn_trans/trans_fmov.c.inc | 20 +-
264
target/loongarch/insn_trans/trans_memory.c.inc | 8 +-
265
target/loongarch/insn_trans/trans_privileged.c.inc | 52 +-
266
target/loongarch/insn_trans/trans_vec.c.inc | 24 +-
267
target/mips/tcg/micromips_translate.c.inc | 12 +-
268
target/mips/tcg/nanomips_translate.c.inc | 200 +--
269
target/ppc/power8-pmu-regs.c.inc | 8 +-
270
target/ppc/translate/branch-impl.c.inc | 2 +-
271
target/ppc/translate/dfp-impl.c.inc | 22 +-
272
target/ppc/translate/fixedpoint-impl.c.inc | 2 +-
273
target/ppc/translate/fp-impl.c.inc | 50 +-
274
target/ppc/translate/processor-ctrl-impl.c.inc | 8 +-
275
target/ppc/translate/spe-impl.c.inc | 30 +-
276
target/ppc/translate/storage-ctrl-impl.c.inc | 26 +-
277
target/ppc/translate/vmx-impl.c.inc | 34 +-
278
target/ppc/translate/vsx-impl.c.inc | 54 +-
279
target/riscv/insn_trans/trans_privileged.c.inc | 8 +-
280
target/riscv/insn_trans/trans_rvbf16.c.inc | 10 +-
281
target/riscv/insn_trans/trans_rvd.c.inc | 48 +-
282
target/riscv/insn_trans/trans_rvf.c.inc | 46 +-
283
target/riscv/insn_trans/trans_rvh.c.inc | 8 +-
284
target/riscv/insn_trans/trans_rvi.c.inc | 16 +-
285
target/riscv/insn_trans/trans_rvm.c.inc | 16 +-
286
target/riscv/insn_trans/trans_rvv.c.inc | 130 +-
287
target/riscv/insn_trans/trans_rvvk.c.inc | 30 +-
288
target/riscv/insn_trans/trans_rvzce.c.inc | 2 +-
289
target/riscv/insn_trans/trans_rvzfa.c.inc | 38 +-
290
target/riscv/insn_trans/trans_rvzfh.c.inc | 54 +-
291
target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 +-
292
target/riscv/insn_trans/trans_svinval.c.inc | 6 +-
293
target/riscv/insn_trans/trans_xthead.c.inc | 2 +-
294
target/s390x/tcg/translate_vx.c.inc | 104 +-
295
tcg/aarch64/tcg-target.c.inc | 2 +-
296
tcg/arm/tcg-target.c.inc | 2 +-
297
tcg/loongarch64/tcg-target.c.inc | 68 +-
298
accel/meson.build | 4 +-
299
accel/tcg/meson.build | 8 +-
300
meson_options.txt | 3 -
301
scripts/meson-buildoptions.sh | 3 -
302
softmmu/meson.build | 4 -
303
target/hexagon/README | 10 +-
304
target/hexagon/gen_tcg_funcs.py | 16 +-
305
tests/avocado/boot_linux_console.py | 7 -
306
tests/avocado/machine_mips_malta.py | 6 -
307
tests/avocado/replay_kernel.py | 7 -
308
tests/avocado/tuxrun_baselines.py | 4 -
309
tests/qemu-iotests/meson.build | 2 +-
310
225 files changed, 5101 insertions(+), 5323 deletions(-)
311
create mode 100644 accel/tcg/internal-common.h
312
rename accel/tcg/{internal.h => internal-target.h} (89%)
313
create mode 100644 include/tcg/startup.h
314
rename accel/{accel-common.c => accel-target.c} (86%)
315
rename softmmu/icount.c => accel/tcg/icount-common.c (99%)
316
rename cpus-common.c => cpu-common.c (100%)
317
rename cpu.c => cpu-target.c (97%)
318
rename page-vary.c => page-vary-target.c (100%)
319
diff view generated by jsdifflib
[PULL 1/3] tcg: Remove dh_alias indirection for dh_typecode
Deleted patch
1
The dh_alias redirect is intended to handle TCG types as distinguished
2
from C types. TCG does not distinguish signed int from unsigned int,
3
because they are the same size. However, we need to retain this
4
distinction for dh_typecode, lest we fail to extend abi types properly
5
for the host call parameters.
6
1
7
This bug was detected when running the 'arm' emulator on an s390
8
system. The s390 uses TCG_TARGET_EXTEND_ARGS which triggers code
9
in tcg_gen_callN to extend 32 bit values to 64 bits; the incorrect
10
sign data in the typemask for each argument caused the values to be
11
extended as unsigned values.
12
13
This simple program exhibits the problem:
14
15
    static volatile int num = -9;
16
    static volatile int den = -5;
17
    int main(void)
18
    {
19
        int quo = num / den;
20
        printf("num %d den %d quo %d\n", num, den, quo);
21
        exit(0);
22
    }
23
24
When run on the broken qemu, this results in:
25
26
    num -9 den -5 quo 0
27
28
The correct result is:
29
30
    num -9 den -5 quo 1
31
32
Fixes: 7319d83a735 ("tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode")
33
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/876
34
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
35
Reported-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
36
Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
37
Tested-by: Keith Packard <keithp@keithp.com>
38
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
39
---
40
include/exec/helper-head.h | 19 ++++++++++---------
41
target/hppa/helper.h | 2 ++
42
target/i386/ops_sse_header.h | 3 +++
43
target/m68k/helper.h | 1 +
44
target/ppc/helper.h | 3 +++
45
5 files changed, 19 insertions(+), 9 deletions(-)
46
47
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/include/exec/helper-head.h
50
+++ b/include/exec/helper-head.h
51
@@ -XXX,XX +XXX,XX @@
52
# ifdef TARGET_LONG_BITS
53
# if TARGET_LONG_BITS == 32
54
# define dh_alias_tl i32
55
+# define dh_typecode_tl dh_typecode_i32
56
# else
57
# define dh_alias_tl i64
58
+# define dh_typecode_tl dh_typecode_i64
59
# endif
60
# endif
61
-# define dh_alias_env ptr
62
# define dh_ctype_tl target_ulong
63
+# define dh_alias_env ptr
64
# define dh_ctype_env CPUArchState *
65
+# define dh_typecode_env dh_typecode_ptr
66
#endif
67
68
/* We can't use glue() here because it falls foul of C preprocessor
69
@@ -XXX,XX +XXX,XX @@
70
#define dh_typecode_i64 4
71
#define dh_typecode_s64 5
72
#define dh_typecode_ptr 6
73
-#define dh_typecode(t) glue(dh_typecode_, dh_alias(t))
74
+#define dh_typecode_int dh_typecode_s32
75
+#define dh_typecode_f16 dh_typecode_i32
76
+#define dh_typecode_f32 dh_typecode_i32
77
+#define dh_typecode_f64 dh_typecode_i64
78
+#define dh_typecode_cptr dh_typecode_ptr
79
+#define dh_typecode(t) dh_typecode_##t
80
81
#define dh_callflag_i32 0
82
-#define dh_callflag_s32 0
83
-#define dh_callflag_int 0
84
#define dh_callflag_i64 0
85
-#define dh_callflag_s64 0
86
-#define dh_callflag_f16 0
87
-#define dh_callflag_f32 0
88
-#define dh_callflag_f64 0
89
#define dh_callflag_ptr 0
90
-#define dh_callflag_cptr dh_callflag_ptr
91
#define dh_callflag_void 0
92
#define dh_callflag_noreturn TCG_CALL_NO_RETURN
93
#define dh_callflag(t) glue(dh_callflag_, dh_alias(t))
94
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/target/hppa/helper.h
97
+++ b/target/hppa/helper.h
98
@@ -XXX,XX +XXX,XX @@
99
#if TARGET_REGISTER_BITS == 64
100
# define dh_alias_tr i64
101
+# define dh_typecode_tr dh_typecode_i64
102
#else
103
# define dh_alias_tr i32
104
+# define dh_typecode_tr dh_typecode_i32
105
#endif
106
#define dh_ctype_tr target_ureg
107
108
diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/i386/ops_sse_header.h
111
+++ b/target/i386/ops_sse_header.h
112
@@ -XXX,XX +XXX,XX @@
113
#define dh_ctype_Reg Reg *
114
#define dh_ctype_ZMMReg ZMMReg *
115
#define dh_ctype_MMXReg MMXReg *
116
+#define dh_typecode_Reg dh_typecode_ptr
117
+#define dh_typecode_ZMMReg dh_typecode_ptr
118
+#define dh_typecode_MMXReg dh_typecode_ptr
119
120
DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
121
DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg)
122
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
123
index XXXXXXX..XXXXXXX 100644
124
--- a/target/m68k/helper.h
125
+++ b/target/m68k/helper.h
126
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32)
127
128
#define dh_alias_fp ptr
129
#define dh_ctype_fp FPReg *
130
+#define dh_typecode_fp dh_typecode_ptr
131
132
DEF_HELPER_3(exts32, void, env, fp, s32)
133
DEF_HELPER_3(extf32, void, env, fp, f32)
134
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
135
index XXXXXXX..XXXXXXX 100644
136
--- a/target/ppc/helper.h
137
+++ b/target/ppc/helper.h
138
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
139
140
#define dh_alias_avr ptr
141
#define dh_ctype_avr ppc_avr_t *
142
+#define dh_typecode_avr dh_typecode_ptr
143
144
#define dh_alias_vsr ptr
145
#define dh_ctype_vsr ppc_vsr_t *
146
+#define dh_typecode_vsr dh_typecode_ptr
147
148
DEF_HELPER_3(vavgub, void, avr, avr, avr)
149
DEF_HELPER_3(vavguh, void, avr, avr, avr)
150
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(store_dbatu, void, env, i32, tl)
151
152
#define dh_alias_fprp ptr
153
#define dh_ctype_fprp ppc_fprp_t *
154
+#define dh_typecode_fprp dh_typecode_ptr
155
156
DEF_HELPER_4(DADD, void, env, fprp, fprp, fprp)
157
DEF_HELPER_4(DADDQ, void, env, fprp, fprp, fprp)
158
--
159
2.25.1
160
161
diff view generated by jsdifflib
[PULL 2/3] accel/tcg/cpu-exec: Fix precise single-stepping after interrupt
Deleted patch
1
From: Luc Michel <lmichel@kalray.eu>
2
1
3
In some cases, cpu->exit_request can be false after handling the
4
interrupt, leading to another TB being executed instead of returning
5
to the main loop.
6
7
Fix this by returning true unconditionally when in single-step mode.
8
9
Fixes: ba3c35d9c402 ("tcg/cpu-exec: precise single-stepping after an interrupt")
10
Signed-off-by: Luc Michel <lmichel@kalray.eu>
11
Message-Id: <20220214132656.11397-1-lmichel@kalray.eu>
12
[rth: Unlock iothread mutex; simplify indentation]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
---
15
accel/tcg/cpu-exec.c | 8 ++++++--
16
1 file changed, 6 insertions(+), 2 deletions(-)
17
18
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/accel/tcg/cpu-exec.c
21
+++ b/accel/tcg/cpu-exec.c
22
@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
23
* raised when single-stepping so that GDB doesn't miss the
24
* next instruction.
25
*/
26
- cpu->exception_index =
27
- (cpu->singlestep_enabled ? EXCP_DEBUG : -1);
28
+ if (unlikely(cpu->singlestep_enabled)) {
29
+ cpu->exception_index = EXCP_DEBUG;
30
+ qemu_mutex_unlock_iothread();
31
+ return true;
32
+ }
33
+ cpu->exception_index = -1;
34
*last_tb = NULL;
35
}
36
/* The target hook may have updated the 'cpu->interrupt_request';
37
--
38
2.25.1
diff view generated by jsdifflib
[PULL 3/3] tcg/tci: Use tcg_out_ldst in tcg_out_st
Deleted patch
1
The tcg_out_ldst helper will handle out-of-range offsets.
2
We haven't actually encountered any, since we haven't run
3
across the assert within tcg_out_op_rrs, but an out-of-range
4
offset would not be impossible in future.
5
1
6
Fixes: 65089889183 ("tcg/tci: Change encoding to uint32_t units")
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
tcg/tci/tcg-target.c.inc | 5 ++---
11
1 file changed, 2 insertions(+), 3 deletions(-)
12
13
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tcg/tci/tcg-target.c.inc
16
+++ b/tcg/tci/tcg-target.c.inc
17
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
18
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
19
intptr_t offset)
20
{
21
- stack_bounds_check(base, offset);
22
switch (type) {
23
case TCG_TYPE_I32:
24
- tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset);
25
+ tcg_out_ldst(s, INDEX_op_st_i32, val, base, offset);
26
break;
27
#if TCG_TARGET_REG_BITS == 64
28
case TCG_TYPE_I64:
29
- tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset);
30
+ tcg_out_ldst(s, INDEX_op_st_i64, val, base, offset);
31
break;
32
#endif
33
default:
34
--
35
2.25.1
36
37
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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