| 1 | The following changes since commit 00483d386901173e84c7965f9f0d678791a75e01: | 1 | V2 fixes an error in patch 22 wrt MacOS. |
|---|---|---|---|
| 2 | It's a shame we don't have public CI for that. | ||
| 2 | 3 | ||
| 3 | Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into staging (2022-02-28 11:27:16 +0000) | 4 | |
| 5 | r~ | ||
| 6 | |||
| 7 | |||
| 8 | The following changes since commit 894fc4fd670aaf04a67dc7507739f914ff4bacf2: | ||
| 9 | |||
| 10 | Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-06-11 09:21:48 +0100) | ||
| 4 | 11 | ||
| 5 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 6 | 13 | ||
| 7 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220228 | 14 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210613 |
| 8 | 15 | ||
| 9 | for you to fetch changes up to 2ccf40f00e3f29d85d4ff48a9a98870059002290: | 16 | for you to fetch changes up to a5a8b84772e13066c6c45f480cc5b5312bbde08e: |
| 10 | 17 | ||
| 11 | tcg/tci: Use tcg_out_ldst in tcg_out_st (2022-02-28 08:04:10 -1000) | 18 | docs/devel: Explain in more detail the TB chaining mechanisms (2021-06-13 17:42:40 -0700) |
| 12 | 19 | ||
| 13 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 14 | Fix typecode generation for tcg helpers | 21 | Clean up code_gen_buffer allocation. |
| 15 | Fix single stepping into interrupt handlers | 22 | Add tcg_remove_ops_after. |
| 16 | Fix out-of-range offsets for stores in TCI | 23 | Fix tcg_constant_* documentation. |
| 24 | Improve TB chaining documentation. | ||
| 25 | Fix float32_exp2. | ||
| 26 | Fix arm tcg_out_op function signature. | ||
| 17 | 27 | ||
| 18 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
| 19 | Luc Michel (1): | 29 | Jose R. Ziviani (1): |
| 20 | accel/tcg/cpu-exec: Fix precise single-stepping after interrupt | 30 | tcg/arm: Fix tcg_out_op function signature |
| 21 | 31 | ||
| 22 | Richard Henderson (2): | 32 | Luis Pires (1): |
| 23 | tcg: Remove dh_alias indirection for dh_typecode | 33 | docs/devel: Explain in more detail the TB chaining mechanisms |
| 24 | tcg/tci: Use tcg_out_ldst in tcg_out_st | ||
| 25 | 34 | ||
| 26 | include/exec/helper-head.h | 19 ++++++++++--------- | 35 | Richard Henderson (32): |
| 27 | target/hppa/helper.h | 2 ++ | 36 | meson: Split out tcg/meson.build |
| 28 | target/i386/ops_sse_header.h | 3 +++ | 37 | meson: Split out fpu/meson.build |
| 29 | target/m68k/helper.h | 1 + | 38 | tcg: Re-order tcg_region_init vs tcg_prologue_init |
| 30 | target/ppc/helper.h | 3 +++ | 39 | tcg: Remove error return from tcg_region_initial_alloc__locked |
| 31 | accel/tcg/cpu-exec.c | 8 ++++++-- | 40 | tcg: Split out tcg_region_initial_alloc |
| 32 | tcg/tci/tcg-target.c.inc | 5 ++--- | 41 | tcg: Split out tcg_region_prologue_set |
| 33 | 7 files changed, 27 insertions(+), 14 deletions(-) | 42 | tcg: Split out region.c |
| 43 | accel/tcg: Inline cpu_gen_init | ||
| 44 | accel/tcg: Move alloc_code_gen_buffer to tcg/region.c | ||
| 45 | accel/tcg: Rename tcg_init to tcg_init_machine | ||
| 46 | tcg: Create tcg_init | ||
| 47 | accel/tcg: Merge tcg_exec_init into tcg_init_machine | ||
| 48 | accel/tcg: Use MiB in tcg_init_machine | ||
| 49 | accel/tcg: Pass down max_cpus to tcg_init | ||
| 50 | tcg: Introduce tcg_max_ctxs | ||
| 51 | tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.h | ||
| 52 | tcg: Replace region.end with region.total_size | ||
| 53 | tcg: Rename region.start to region.after_prologue | ||
| 54 | tcg: Tidy tcg_n_regions | ||
| 55 | tcg: Tidy split_cross_256mb | ||
| 56 | tcg: Move in_code_gen_buffer and tests to region.c | ||
| 57 | tcg: Allocate code_gen_buffer into struct tcg_region_state | ||
| 58 | tcg: Return the map protection from alloc_code_gen_buffer | ||
| 59 | tcg: Sink qemu_madvise call to common code | ||
| 60 | util/osdep: Add qemu_mprotect_rw | ||
| 61 | tcg: Round the tb_size default from qemu_get_host_physmem | ||
| 62 | tcg: Merge buffer protection and guard page protection | ||
| 63 | tcg: When allocating for !splitwx, begin with PROT_NONE | ||
| 64 | tcg: Move tcg_init_ctx and tcg_ctx from accel/tcg/ | ||
| 65 | tcg: Introduce tcg_remove_ops_after | ||
| 66 | tcg: Fix documentation for tcg_constant_* vs tcg_temp_free_* | ||
| 67 | softfloat: Fix tp init in float32_exp2 | ||
| 68 | |||
| 69 | docs/devel/tcg.rst | 101 ++++- | ||
| 70 | meson.build | 12 +- | ||
| 71 | accel/tcg/internal.h | 2 + | ||
| 72 | include/qemu/osdep.h | 1 + | ||
| 73 | include/sysemu/tcg.h | 2 - | ||
| 74 | include/tcg/tcg.h | 28 +- | ||
| 75 | tcg/aarch64/tcg-target.h | 1 + | ||
| 76 | tcg/arm/tcg-target.h | 1 + | ||
| 77 | tcg/i386/tcg-target.h | 2 + | ||
| 78 | tcg/mips/tcg-target.h | 6 + | ||
| 79 | tcg/ppc/tcg-target.h | 2 + | ||
| 80 | tcg/riscv/tcg-target.h | 1 + | ||
| 81 | tcg/s390/tcg-target.h | 3 + | ||
| 82 | tcg/sparc/tcg-target.h | 1 + | ||
| 83 | tcg/tcg-internal.h | 40 ++ | ||
| 84 | tcg/tci/tcg-target.h | 1 + | ||
| 85 | accel/tcg/tcg-all.c | 32 +- | ||
| 86 | accel/tcg/translate-all.c | 439 +------------------- | ||
| 87 | bsd-user/main.c | 3 +- | ||
| 88 | fpu/softfloat.c | 2 +- | ||
| 89 | linux-user/main.c | 1 - | ||
| 90 | tcg/region.c | 999 ++++++++++++++++++++++++++++++++++++++++++++++ | ||
| 91 | tcg/tcg.c | 649 +++--------------------------- | ||
| 92 | util/osdep.c | 9 + | ||
| 93 | tcg/arm/tcg-target.c.inc | 3 +- | ||
| 94 | fpu/meson.build | 1 + | ||
| 95 | tcg/meson.build | 14 + | ||
| 96 | 27 files changed, 1266 insertions(+), 1090 deletions(-) | ||
| 97 | create mode 100644 tcg/tcg-internal.h | ||
| 98 | create mode 100644 tcg/region.c | ||
| 99 | create mode 100644 fpu/meson.build | ||
| 100 | create mode 100644 tcg/meson.build | ||
| 101 | diff view generated by jsdifflib |
| 1 | The dh_alias redirect is intended to handle TCG types as distinguished | 1 | Do not mess around with setting values within tcg_init_ctx. |
|---|---|---|---|
| 2 | from C types. TCG does not distinguish signed int from unsigned int, | 2 | Put the values into 'region' directly, which is where they |
| 3 | because they are the same size. However, we need to retain this | 3 | will live for the lifetime of the program. |
| 4 | distinction for dh_typecode, lest we fail to extend abi types properly | ||
| 5 | for the host call parameters. | ||
| 6 | 4 | ||
| 7 | This bug was detected when running the 'arm' emulator on an s390 | ||
| 8 | system. The s390 uses TCG_TARGET_EXTEND_ARGS which triggers code | ||
| 9 | in tcg_gen_callN to extend 32 bit values to 64 bits; the incorrect | ||
| 10 | sign data in the typemask for each argument caused the values to be | ||
| 11 | extended as unsigned values. | ||
| 12 | |||
| 13 | This simple program exhibits the problem: | ||
| 14 | |||
| 15 | static volatile int num = -9; | ||
| 16 | static volatile int den = -5; | ||
| 17 | int main(void) | ||
| 18 | { | ||
| 19 | int quo = num / den; | ||
| 20 | printf("num %d den %d quo %d\n", num, den, quo); | ||
| 21 | exit(0); | ||
| 22 | } | ||
| 23 | |||
| 24 | When run on the broken qemu, this results in: | ||
| 25 | |||
| 26 | num -9 den -5 quo 0 | ||
| 27 | |||
| 28 | The correct result is: | ||
| 29 | |||
| 30 | num -9 den -5 quo 1 | ||
| 31 | |||
| 32 | Fixes: 7319d83a735 ("tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode") | ||
| 33 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/876 | ||
| 34 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
| 35 | Reported-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> | 6 | Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> |
| 36 | Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> | ||
| 37 | Tested-by: Keith Packard <keithp@keithp.com> | ||
| 38 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 39 | --- | 8 | --- |
| 40 | include/exec/helper-head.h | 19 ++++++++++--------- | 9 | tcg/region.c | 64 ++++++++++++++++++++++------------------------------ |
| 41 | target/hppa/helper.h | 2 ++ | 10 | 1 file changed, 27 insertions(+), 37 deletions(-) |
| 42 | target/i386/ops_sse_header.h | 3 +++ | ||
| 43 | target/m68k/helper.h | 1 + | ||
| 44 | target/ppc/helper.h | 3 +++ | ||
| 45 | 5 files changed, 19 insertions(+), 9 deletions(-) | ||
| 46 | 11 | ||
| 47 | diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h | 12 | diff --git a/tcg/region.c b/tcg/region.c |
| 48 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 49 | --- a/include/exec/helper-head.h | 14 | --- a/tcg/region.c |
| 50 | +++ b/include/exec/helper-head.h | 15 | +++ b/tcg/region.c |
| 51 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static size_t tree_size; |
| 52 | # ifdef TARGET_LONG_BITS | 17 | |
| 53 | # if TARGET_LONG_BITS == 32 | 18 | bool in_code_gen_buffer(const void *p) |
| 54 | # define dh_alias_tl i32 | 19 | { |
| 55 | +# define dh_typecode_tl dh_typecode_i32 | 20 | - const TCGContext *s = &tcg_init_ctx; |
| 56 | # else | 21 | /* |
| 57 | # define dh_alias_tl i64 | 22 | * Much like it is valid to have a pointer to the byte past the |
| 58 | +# define dh_typecode_tl dh_typecode_i64 | 23 | * end of an array (so long as you don't dereference it), allow |
| 59 | # endif | 24 | * a pointer to the byte past the end of the code gen buffer. |
| 60 | # endif | 25 | */ |
| 61 | -# define dh_alias_env ptr | 26 | - return (size_t)(p - s->code_gen_buffer) <= s->code_gen_buffer_size; |
| 62 | # define dh_ctype_tl target_ulong | 27 | + return (size_t)(p - region.start_aligned) <= region.total_size; |
| 63 | +# define dh_alias_env ptr | 28 | } |
| 64 | # define dh_ctype_env CPUArchState * | 29 | |
| 65 | +# define dh_typecode_env dh_typecode_ptr | 30 | #ifdef CONFIG_DEBUG_TCG |
| 31 | @@ -XXX,XX +XXX,XX @@ static bool alloc_code_gen_buffer(size_t tb_size, int splitwx, Error **errp) | ||
| 32 | } | ||
| 33 | qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); | ||
| 34 | |||
| 35 | - tcg_ctx->code_gen_buffer = buf; | ||
| 36 | - tcg_ctx->code_gen_buffer_size = size; | ||
| 37 | + region.start_aligned = buf; | ||
| 38 | + region.total_size = size; | ||
| 39 | return true; | ||
| 40 | } | ||
| 41 | #elif defined(_WIN32) | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) | ||
| 43 | return false; | ||
| 44 | } | ||
| 45 | |||
| 46 | - tcg_ctx->code_gen_buffer = buf; | ||
| 47 | - tcg_ctx->code_gen_buffer_size = size; | ||
| 48 | + region.start_aligned = buf; | ||
| 49 | + region.total_size = size; | ||
| 50 | return true; | ||
| 51 | } | ||
| 52 | #else | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static bool alloc_code_gen_buffer_anon(size_t size, int prot, | ||
| 54 | /* Request large pages for the buffer. */ | ||
| 55 | qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); | ||
| 56 | |||
| 57 | - tcg_ctx->code_gen_buffer = buf; | ||
| 58 | - tcg_ctx->code_gen_buffer_size = size; | ||
| 59 | + region.start_aligned = buf; | ||
| 60 | + region.total_size = size; | ||
| 61 | return true; | ||
| 62 | } | ||
| 63 | |||
| 64 | @@ -XXX,XX +XXX,XX @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) | ||
| 65 | return false; | ||
| 66 | } | ||
| 67 | /* The size of the mapping may have been adjusted. */ | ||
| 68 | - size = tcg_ctx->code_gen_buffer_size; | ||
| 69 | - buf_rx = tcg_ctx->code_gen_buffer; | ||
| 70 | + buf_rx = region.start_aligned; | ||
| 71 | + size = region.total_size; | ||
| 66 | #endif | 72 | #endif |
| 67 | 73 | ||
| 68 | /* We can't use glue() here because it falls foul of C preprocessor | 74 | buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); |
| 69 | @@ -XXX,XX +XXX,XX @@ | 75 | @@ -XXX,XX +XXX,XX @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) |
| 70 | #define dh_typecode_i64 4 | ||
| 71 | #define dh_typecode_s64 5 | ||
| 72 | #define dh_typecode_ptr 6 | ||
| 73 | -#define dh_typecode(t) glue(dh_typecode_, dh_alias(t)) | ||
| 74 | +#define dh_typecode_int dh_typecode_s32 | ||
| 75 | +#define dh_typecode_f16 dh_typecode_i32 | ||
| 76 | +#define dh_typecode_f32 dh_typecode_i32 | ||
| 77 | +#define dh_typecode_f64 dh_typecode_i64 | ||
| 78 | +#define dh_typecode_cptr dh_typecode_ptr | ||
| 79 | +#define dh_typecode(t) dh_typecode_##t | ||
| 80 | |||
| 81 | #define dh_callflag_i32 0 | ||
| 82 | -#define dh_callflag_s32 0 | ||
| 83 | -#define dh_callflag_int 0 | ||
| 84 | #define dh_callflag_i64 0 | ||
| 85 | -#define dh_callflag_s64 0 | ||
| 86 | -#define dh_callflag_f16 0 | ||
| 87 | -#define dh_callflag_f32 0 | ||
| 88 | -#define dh_callflag_f64 0 | ||
| 89 | #define dh_callflag_ptr 0 | ||
| 90 | -#define dh_callflag_cptr dh_callflag_ptr | ||
| 91 | #define dh_callflag_void 0 | ||
| 92 | #define dh_callflag_noreturn TCG_CALL_NO_RETURN | ||
| 93 | #define dh_callflag(t) glue(dh_callflag_, dh_alias(t)) | ||
| 94 | diff --git a/target/hppa/helper.h b/target/hppa/helper.h | ||
| 95 | index XXXXXXX..XXXXXXX 100644 | ||
| 96 | --- a/target/hppa/helper.h | ||
| 97 | +++ b/target/hppa/helper.h | ||
| 98 | @@ -XXX,XX +XXX,XX @@ | ||
| 99 | #if TARGET_REGISTER_BITS == 64 | ||
| 100 | # define dh_alias_tr i64 | ||
| 101 | +# define dh_typecode_tr dh_typecode_i64 | ||
| 102 | #else | ||
| 103 | # define dh_alias_tr i32 | ||
| 104 | +# define dh_typecode_tr dh_typecode_i32 | ||
| 105 | #endif | 76 | #endif |
| 106 | #define dh_ctype_tr target_ureg | 77 | |
| 107 | 78 | close(fd); | |
| 108 | diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h | 79 | - tcg_ctx->code_gen_buffer = buf_rw; |
| 109 | index XXXXXXX..XXXXXXX 100644 | 80 | - tcg_ctx->code_gen_buffer_size = size; |
| 110 | --- a/target/i386/ops_sse_header.h | 81 | + region.start_aligned = buf_rw; |
| 111 | +++ b/target/i386/ops_sse_header.h | 82 | + region.total_size = size; |
| 112 | @@ -XXX,XX +XXX,XX @@ | 83 | tcg_splitwx_diff = buf_rx - buf_rw; |
| 113 | #define dh_ctype_Reg Reg * | 84 | |
| 114 | #define dh_ctype_ZMMReg ZMMReg * | 85 | /* Request large pages for the buffer and the splitwx. */ |
| 115 | #define dh_ctype_MMXReg MMXReg * | 86 | @@ -XXX,XX +XXX,XX @@ static bool alloc_code_gen_buffer_splitwx_vmremap(size_t size, Error **errp) |
| 116 | +#define dh_typecode_Reg dh_typecode_ptr | 87 | return false; |
| 117 | +#define dh_typecode_ZMMReg dh_typecode_ptr | 88 | } |
| 118 | +#define dh_typecode_MMXReg dh_typecode_ptr | 89 | |
| 119 | 90 | - buf_rw = (mach_vm_address_t)tcg_ctx->code_gen_buffer; | |
| 120 | DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg) | 91 | + buf_rw = (mach_vm_address_t)region.start_aligned; |
| 121 | DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg) | 92 | buf_rx = 0; |
| 122 | diff --git a/target/m68k/helper.h b/target/m68k/helper.h | 93 | ret = mach_vm_remap(mach_task_self(), |
| 123 | index XXXXXXX..XXXXXXX 100644 | 94 | &buf_rx, |
| 124 | --- a/target/m68k/helper.h | 95 | @@ -XXX,XX +XXX,XX @@ static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) |
| 125 | +++ b/target/m68k/helper.h | 96 | */ |
| 126 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) | 97 | void tcg_region_init(size_t tb_size, int splitwx, unsigned max_cpus) |
| 127 | 98 | { | |
| 128 | #define dh_alias_fp ptr | 99 | - void *buf, *aligned, *end; |
| 129 | #define dh_ctype_fp FPReg * | 100 | - size_t total_size; |
| 130 | +#define dh_typecode_fp dh_typecode_ptr | 101 | size_t page_size; |
| 131 | 102 | size_t region_size; | |
| 132 | DEF_HELPER_3(exts32, void, env, fp, s32) | 103 | - size_t n_regions; |
| 133 | DEF_HELPER_3(extf32, void, env, fp, f32) | 104 | size_t i; |
| 134 | diff --git a/target/ppc/helper.h b/target/ppc/helper.h | 105 | bool ok; |
| 135 | index XXXXXXX..XXXXXXX 100644 | 106 | |
| 136 | --- a/target/ppc/helper.h | 107 | @@ -XXX,XX +XXX,XX @@ void tcg_region_init(size_t tb_size, int splitwx, unsigned max_cpus) |
| 137 | +++ b/target/ppc/helper.h | 108 | splitwx, &error_fatal); |
| 138 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64) | 109 | assert(ok); |
| 139 | 110 | ||
| 140 | #define dh_alias_avr ptr | 111 | - buf = tcg_init_ctx.code_gen_buffer; |
| 141 | #define dh_ctype_avr ppc_avr_t * | 112 | - total_size = tcg_init_ctx.code_gen_buffer_size; |
| 142 | +#define dh_typecode_avr dh_typecode_ptr | 113 | - page_size = qemu_real_host_page_size; |
| 143 | 114 | - n_regions = tcg_n_regions(total_size, max_cpus); | |
| 144 | #define dh_alias_vsr ptr | 115 | - |
| 145 | #define dh_ctype_vsr ppc_vsr_t * | 116 | - /* The first region will be 'aligned - buf' bytes larger than the others */ |
| 146 | +#define dh_typecode_vsr dh_typecode_ptr | 117 | - aligned = QEMU_ALIGN_PTR_UP(buf, page_size); |
| 147 | 118 | - g_assert(aligned < tcg_init_ctx.code_gen_buffer + total_size); | |
| 148 | DEF_HELPER_3(vavgub, void, avr, avr, avr) | 119 | - |
| 149 | DEF_HELPER_3(vavguh, void, avr, avr, avr) | 120 | /* |
| 150 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(store_dbatu, void, env, i32, tl) | 121 | * Make region_size a multiple of page_size, using aligned as the start. |
| 151 | 122 | * As a result of this we might end up with a few extra pages at the end of | |
| 152 | #define dh_alias_fprp ptr | 123 | * the buffer; we will assign those to the last region. |
| 153 | #define dh_ctype_fprp ppc_fprp_t * | 124 | */ |
| 154 | +#define dh_typecode_fprp dh_typecode_ptr | 125 | - region_size = (total_size - (aligned - buf)) / n_regions; |
| 155 | 126 | + region.n = tcg_n_regions(region.total_size, max_cpus); | |
| 156 | DEF_HELPER_4(DADD, void, env, fprp, fprp, fprp) | 127 | + page_size = qemu_real_host_page_size; |
| 157 | DEF_HELPER_4(DADDQ, void, env, fprp, fprp, fprp) | 128 | + region_size = region.total_size / region.n; |
| 129 | region_size = QEMU_ALIGN_DOWN(region_size, page_size); | ||
| 130 | |||
| 131 | /* A region must have at least 2 pages; one code, one guard */ | ||
| 132 | g_assert(region_size >= 2 * page_size); | ||
| 133 | + region.stride = region_size; | ||
| 134 | + | ||
| 135 | + /* Reserve space for guard pages. */ | ||
| 136 | + region.size = region_size - page_size; | ||
| 137 | + region.total_size -= page_size; | ||
| 138 | + | ||
| 139 | + /* | ||
| 140 | + * The first region will be smaller than the others, via the prologue, | ||
| 141 | + * which has yet to be allocated. For now, the first region begins at | ||
| 142 | + * the page boundary. | ||
| 143 | + */ | ||
| 144 | + region.after_prologue = region.start_aligned; | ||
| 145 | |||
| 146 | /* init the region struct */ | ||
| 147 | qemu_mutex_init(®ion.lock); | ||
| 148 | - region.n = n_regions; | ||
| 149 | - region.size = region_size - page_size; | ||
| 150 | - region.stride = region_size; | ||
| 151 | - region.after_prologue = buf; | ||
| 152 | - region.start_aligned = aligned; | ||
| 153 | - /* page-align the end, since its last page will be a guard page */ | ||
| 154 | - end = QEMU_ALIGN_PTR_DOWN(buf + total_size, page_size); | ||
| 155 | - /* account for that last guard page */ | ||
| 156 | - end -= page_size; | ||
| 157 | - total_size = end - aligned; | ||
| 158 | - region.total_size = total_size; | ||
| 159 | |||
| 160 | /* | ||
| 161 | * Set guard pages in the rw buffer, as that's the one into which | ||
| 158 | -- | 162 | -- |
| 159 | 2.25.1 | 163 | 2.25.1 |
| 160 | 164 | ||
| 161 | 165 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Luc Michel <lmichel@kalray.eu> | ||
| 2 | 1 | ||
| 3 | In some cases, cpu->exit_request can be false after handling the | ||
| 4 | interrupt, leading to another TB being executed instead of returning | ||
| 5 | to the main loop. | ||
| 6 | |||
| 7 | Fix this by returning true unconditionally when in single-step mode. | ||
| 8 | |||
| 9 | Fixes: ba3c35d9c402 ("tcg/cpu-exec: precise single-stepping after an interrupt") | ||
| 10 | Signed-off-by: Luc Michel <lmichel@kalray.eu> | ||
| 11 | Message-Id: <20220214132656.11397-1-lmichel@kalray.eu> | ||
| 12 | [rth: Unlock iothread mutex; simplify indentation] | ||
| 13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | --- | ||
| 15 | accel/tcg/cpu-exec.c | 8 ++++++-- | ||
| 16 | 1 file changed, 6 insertions(+), 2 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/accel/tcg/cpu-exec.c | ||
| 21 | +++ b/accel/tcg/cpu-exec.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_interrupt(CPUState *cpu, | ||
| 23 | * raised when single-stepping so that GDB doesn't miss the | ||
| 24 | * next instruction. | ||
| 25 | */ | ||
| 26 | - cpu->exception_index = | ||
| 27 | - (cpu->singlestep_enabled ? EXCP_DEBUG : -1); | ||
| 28 | + if (unlikely(cpu->singlestep_enabled)) { | ||
| 29 | + cpu->exception_index = EXCP_DEBUG; | ||
| 30 | + qemu_mutex_unlock_iothread(); | ||
| 31 | + return true; | ||
| 32 | + } | ||
| 33 | + cpu->exception_index = -1; | ||
| 34 | *last_tb = NULL; | ||
| 35 | } | ||
| 36 | /* The target hook may have updated the 'cpu->interrupt_request'; | ||
| 37 | -- | ||
| 38 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The tcg_out_ldst helper will handle out-of-range offsets. | ||
| 2 | We haven't actually encountered any, since we haven't run | ||
| 3 | across the assert within tcg_out_op_rrs, but an out-of-range | ||
| 4 | offset would not be impossible in future. | ||
| 5 | 1 | ||
| 6 | Fixes: 65089889183 ("tcg/tci: Change encoding to uint32_t units") | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | --- | ||
| 10 | tcg/tci/tcg-target.c.inc | 5 ++--- | ||
| 11 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/tcg/tci/tcg-target.c.inc | ||
| 16 | +++ b/tcg/tci/tcg-target.c.inc | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
| 18 | static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base, | ||
| 19 | intptr_t offset) | ||
| 20 | { | ||
| 21 | - stack_bounds_check(base, offset); | ||
| 22 | switch (type) { | ||
| 23 | case TCG_TYPE_I32: | ||
| 24 | - tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset); | ||
| 25 | + tcg_out_ldst(s, INDEX_op_st_i32, val, base, offset); | ||
| 26 | break; | ||
| 27 | #if TCG_TARGET_REG_BITS == 64 | ||
| 28 | case TCG_TYPE_I64: | ||
| 29 | - tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset); | ||
| 30 | + tcg_out_ldst(s, INDEX_op_st_i64, val, base, offset); | ||
| 31 | break; | ||
| 32 | #endif | ||
| 33 | default: | ||
| 34 | -- | ||
| 35 | 2.25.1 | ||
| 36 | |||
| 37 | diff view generated by jsdifflib |