Series comparison

-[PULL 0/7] aspeed queue
+[PULL 00/12] aspeed queue
-The following changes since commit c13b8e9973635f34f3ce4356af27a311c993729c:
+The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:
-  Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220216' into staging (2022-02-16 09:57:11 +0000)
+  Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)
 are available in the Git repository at:
-  https://github.com/legoater/qemu/ tags/pull-aspeed-20220227
+  https://github.com/legoater/qemu/ tags/pull-aspeed-20231025
-for you to fetch changes up to 3671342a38f21316a2bda62e7d607bbaedd60fd8:
+for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:
-  aspeed/sdmc: Add trace events (2022-02-26 18:40:51 +0100)
+  hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)
 ----------------------------------------------------------------
 aspeed queue:
-* Removal of the swift-bmc machine
+* Update of Andrew's email
-* New Secure Boot Controller model
+* Split of AspeedSoCState per 2400/2600/10x0
 * Improvements on the rainier machine
 * Various small cleanups
 ----------------------------------------------------------------
-Cédric Le Goater (3):
+Andrew Jeffery (1):
-      aspeed: Introduce a create_pca9552() helper
+      MAINTAINERS: aspeed: Update Andrew's email address
       aspeed/smc: Add an address mask on segment registers
       aspeed/sdmc: Add trace events
-Joel Stanley (4):
+Philippe Mathieu-Daudé (11):
-      arm: Remove swift-bmc machine
+      hw/arm/aspeed: Extract code common to all boards to a common file
-      ast2600: Add Secure Boot Controller model
+      hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
-      aspeed: rainier: Add i2c LED devices
+      hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
-      aspeed: rainier: Add strap values taken from hardware
+      hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
       hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
       hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
       hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
       hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
       hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
       hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
       hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
- docs/about/deprecated.rst       |   7 --
+ MAINTAINERS                               |   2 +-
- docs/about/removed-features.rst |   5 ++
+ include/hw/arm/aspeed_soc.h               |  35 +++++-
- docs/system/arm/aspeed.rst      |   1 -
+ hw/arm/aspeed.c                           | 101 +++++++--------
- include/hw/arm/aspeed_soc.h     |   3 +
+ hw/arm/aspeed_ast10x0.c                   |  53 ++++----
- include/hw/misc/aspeed_sbc.h    |  32 +++++++++
+ hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------
- include/hw/ssi/aspeed_smc.h     |   1 +
+ hw/arm/aspeed_ast2600.c                   |  75 ++++++------
- hw/arm/aspeed.c                 |  98 ++++++++--------------------
+ hw/arm/aspeed_soc_common.c                | 154 +++++++++++++++++++++++
- hw/arm/aspeed_ast2600.c         |   9 +++
+ hw/arm/fby35.c                            |  27 ++--
- hw/misc/aspeed_sbc.c            | 141 ++++++++++++++++++++++++++++++++++++++++
+ hw/arm/meson.build                        |   3 +-
- hw/misc/aspeed_sdmc.c           |   2 +
+files changed, 363 insertions(+), 284 deletions(-)
- hw/ssi/aspeed_smc.c             |  11 ++++
+ rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)
- hw/misc/meson.build             |   1 +
+ create mode 100644 hw/arm/aspeed_soc_common.c
- hw/misc/trace-events            |   4 ++
 files changed, 236 insertions(+), 79 deletions(-)
  create mode 100644 include/hw/misc/aspeed_sbc.h
  create mode 100644 hw/misc/aspeed_sbc.c

-New patch
+[PULL 01/12] MAINTAINERS: aspeed: Update Andrew's email address
+From: Andrew Jeffery <andrew@codeconstruct.com.au>
+I've changed employers, have company email that deals with patch-based
+workflows without too much of a headache, and am trying to steer some
+content out of my personal mail.
+Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
+---
+ MAINTAINERS | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: docs/system/arm/emcraft-sf2.rst
+ ASPEED BMCs
+ M: Cédric Le Goater <clg@kaod.org>
+ M: Peter Maydell <peter.maydell@linaro.org>
+-R: Andrew Jeffery <andrew@aj.id.au>
++R: Andrew Jeffery <andrew@codeconstruct.com.au>
+ R: Joel Stanley <joel@jms.id.au>
+ L: qemu-arm@nongnu.org
+ S: Maintained
+--
+.41.0

-New patch
+[PULL 02/12] hw/arm/aspeed: Extract code common to all boards to a common file
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 aspeed_soc.c contains definitions specific to the AST2400
 and AST2500 SoCs, but also some definitions for other AST
 SoCs: move them to a common file.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
  hw/arm/aspeed_soc.c        |  96 -------------------------------
  hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
  hw/arm/meson.build         |   1 +
 files changed, 115 insertions(+), 96 deletions(-)
  create mode 100644 hw/arm/aspeed_soc_common.c
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc.c
 +++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)
  };
  type_init(aspeed_soc_register_types);
 -
 -qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
 -{
 -    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
 -}
 -
 -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    SerialMM *smm;
 -
 -    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 -        smm = &s->uart[i];
 -
 -        /* Chardev property is set by the machine. */
 -        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
 -        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
 -        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
 -        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
 -        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
 -            return false;
 -        }
 -
 -        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
 -        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
 -    }
 -
 -    return true;
 -}
 -
 -void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    int i = dev - ASPEED_DEV_UART1;
 -
 -    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
 -    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 -}
 -
 -/*
 - * SDMC should be realized first to get correct RAM size and max size
 - * values
 - */
 -bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    ram_addr_t ram_size, max_ram_size;
 -
 -    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
 -                                        &error_abort);
 -    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
 -                                            &error_abort);
 -
 -    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
 -                       max_ram_size);
 -    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
 -
 -    /*
 -     * Add a memory region beyond the RAM region to let firmwares scan
 -     * the address space with load/store and guess how much RAM the
 -     * SoC has.
 -     */
 -    if (ram_size < max_ram_size) {
 -        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
 -
 -        qdev_prop_set_string(dev, "name", "ram-empty");
 -        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
 -        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
 -            return false;
 -        }
 -
 -        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
 -                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
 -    }
 -
 -    memory_region_add_subregion(s->memory,
 -                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
 -    return true;
 -}
 -
 -void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
 -{
 -    memory_region_add_subregion(s->memory, addr,
 -                                sysbus_mmio_get_region(dev, n));
 -}
 -
 -void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 -                                   const char *name, hwaddr addr, uint64_t size)
 -{
 -    qdev_prop_set_string(DEVICE(dev), "name", name);
 -    qdev_prop_set_uint64(DEVICE(dev), "size", size);
 -    sysbus_realize(dev, &error_abort);
 -
 -    memory_region_add_subregion_overlap(s->memory, addr,
 -                                        sysbus_mmio_get_region(dev, 0), -1000);
 -}
 diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ASPEED SoC family
 + *
 + * Andrew Jeffery <andrew@aj.id.au>
 + * Jeremy Kerr <jk@ozlabs.org>
 + *
 + * Copyright 2016 IBM Corp.
 + *
 + * This code is licensed under the GPL version 2 or later.  See
 + * the COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "hw/misc/unimp.h"
 +#include "hw/arm/aspeed_soc.h"
 +#include "hw/char/serial.h"
 +
 +
 +qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
 +{
 +    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
 +}
 +
 +bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
 +{
 +    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 +    SerialMM *smm;
 +
 +    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 +        smm = &s->uart[i];
 +
 +        /* Chardev property is set by the machine. */
 +        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
 +        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
 +        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
 +        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
 +        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
 +            return false;
 +        }
 +
 +        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
 +        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
 +    }
 +
 +    return true;
 +}
 +
 +void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
 +{
 +    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 +    int i = dev - ASPEED_DEV_UART1;
 +
 +    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
 +    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 +}
 +
 +/*
 + * SDMC should be realized first to get correct RAM size and max size
 + * values
 + */
 +bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
 +{
 +    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 +    ram_addr_t ram_size, max_ram_size;
 +
 +    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
 +                                        &error_abort);
 +    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
 +                                            &error_abort);
 +
 +    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
 +                       max_ram_size);
 +    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
 +
 +    /*
 +     * Add a memory region beyond the RAM region to let firmwares scan
 +     * the address space with load/store and guess how much RAM the
 +     * SoC has.
 +     */
 +    if (ram_size < max_ram_size) {
 +        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
 +
 +        qdev_prop_set_string(dev, "name", "ram-empty");
 +        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
 +        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
 +            return false;
 +        }
 +
 +        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
 +                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
 +    }
 +
 +    memory_region_add_subregion(s->memory,
 +                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
 +    return true;
 +}
 +
 +void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
 +{
 +    memory_region_add_subregion(s->memory, addr,
 +                                sysbus_mmio_get_region(dev, n));
 +}
 +
 +void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 +                                   const char *name, hwaddr addr, uint64_t size)
 +{
 +    qdev_prop_set_string(DEVICE(dev), "name", name);
 +    qdev_prop_set_uint64(DEVICE(dev), "size", size);
 +    sysbus_realize(dev, &error_abort);
 +
 +    memory_region_add_subregion_overlap(s->memory, addr,
 +                                        sysbus_mmio_get_region(dev, 0), -1000);
 +}
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
  arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
    'aspeed_soc.c',
    'aspeed.c',
 +  'aspeed_soc_common.c',
    'aspeed_ast2600.c',
    'aspeed_ast10x0.c',
    'aspeed_eeprom.c',
 --
 .41.0

-New patch
+[PULL 03/12] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
+---
+ hw/arm/aspeed_soc.c | 6 +++---
+file changed, 3 insertions(+), 3 deletions(-)
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/aspeed_soc.c
++++ b/hw/arm/aspeed_soc.c
+@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
+     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
+ }
+-static void aspeed_soc_init(Object *obj)
++static void aspeed_ast2400_soc_init(Object *obj)
+ {
+     AspeedSoCState *s = ASPEED_SOC(obj);
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
+ static const TypeInfo aspeed_soc_ast2400_type_info = {
+     .name           = "ast2400-a1",
+     .parent         = TYPE_ASPEED_SOC,
+-    .instance_init  = aspeed_soc_init,
++    .instance_init  = aspeed_ast2400_soc_init,
+     .instance_size  = sizeof(AspeedSoCState),
+     .class_init     = aspeed_soc_ast2400_class_init,
+ };
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
+ static const TypeInfo aspeed_soc_ast2500_type_info = {
+     .name           = "ast2500-a1",
+     .parent         = TYPE_ASPEED_SOC,
+-    .instance_init  = aspeed_soc_init,
++    .instance_init  = aspeed_ast2400_soc_init,
+     .instance_size  = sizeof(AspeedSoCState),
+     .class_init     = aspeed_soc_ast2500_class_init,
+ };
+--
+.41.0

-New patch
+[PULL 04/12] hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Keep aspeed_soc_class_init() generic, set the realize handler
+to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
+---
+ hw/arm/aspeed_soc.c | 15 +++++++++++----
+file changed, 11 insertions(+), 4 deletions(-)
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/aspeed_soc.c
++++ b/hw/arm/aspeed_soc.c
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
+     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
+ }
+-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
++static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
+ {
+     int i;
+     AspeedSoCState *s = ASPEED_SOC(dev);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+ {
+     DeviceClass *dc = DEVICE_CLASS(oc);
+-    dc->realize = aspeed_soc_realize;
+-    /* Reason: Uses serial_hds and nd_table in realize() directly */
+-    dc->user_creatable = false;
+     device_class_set_props(dc, aspeed_soc_properties);
+ }
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = {
+ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
+ {
+     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
++    DeviceClass *dc = DEVICE_CLASS(oc);
++
++    dc->realize = aspeed_ast2400_soc_realize;
++    /* Reason: Uses serial_hds and nd_table in realize() directly */
++    dc->user_creatable = false;
+     sc->name         = "ast2400-a1";
+     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
+ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
+ {
+     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
++    DeviceClass *dc = DEVICE_CLASS(oc);
++
++    dc->realize = aspeed_ast2400_soc_realize;
++    /* Reason: Uses serial_hds and nd_table in realize() directly */
++    dc->user_creatable = false;
+     sc->name         = "ast2500-a1";
+     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
+--
+.41.0

-[PULL 4/7] aspeed: rainier: Add strap values taken from hardware
+[PULL 05/12] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
-From: Joel Stanley <joel@jms.id.au>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-When time permits, we should introduce defines for the HW strapping
+We want to derivate the big AspeedSoCState object in some more
-registers to cleanly decode the values.
+SoC-specific ones. Since the object size will vary, allocate it
+dynamically.
-SCU500 = 0x00422016
-  Disable ARM JTAG trusted world debug: 0x1
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-  Disable ARM JTAG debug: 0x1
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
   VGA Memory Size: 0x1 [16MB]
   Cortex M3: 0x1 [Disabled]
   Boot device: 0x1 [eMMC]
   Reserved: 0x1
 SCU510 = 0x80000848
   Secure Boot Enable: 0x1
   Enable boot SPI or eMMC ABR (second boot): 0x1
   Enable LPC mode: 0x1 [LPC]
   Disable LPC SuperIO 0x2e/0x4e: 0x1
 Signed-off-by: Joel Stanley <joel@jms.id.au>
 [ clg: rewrote the commit log ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed.c | 4 ++--
+ hw/arm/aspeed.c | 101 +++++++++++++++++++++++++-----------------------
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 52 insertions(+), 49 deletions(-)
 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed.c
 +++ b/hw/arm/aspeed.c
 @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
- #define TACOMA_BMC_HW_STRAP2  0x00000040
+     MachineState parent_obj;
+     /* Public */
- /* Rainier hardware value: (QEMU prototype) */
--#define RAINIER_BMC_HW_STRAP1 0x00000000
+-    AspeedSoCState soc;
--#define RAINIER_BMC_HW_STRAP2 0x00000000
++    AspeedSoCState *soc;
-+#define RAINIER_BMC_HW_STRAP1 0x00422016
+     MemoryRegion boot_rom;
-+#define RAINIER_BMC_HW_STRAP2 0x80000848
+     bool mmio_exec;
+     uint32_t uart_chosen;
- /* Fuji hardware value */
+@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
- #define FUJI_BMC_HW_STRAP1    0x00000000
+ static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
                                      uint64_t rom_size)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
                             &error_abort);
@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
  static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
  {
      AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
 -    AspeedSoCState *s = &bmc->soc;
 +    AspeedSoCState *s = bmc->soc;
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
      int i;
      NICInfo *nd = &nd_table[0];
 -    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 -
 -    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 +    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
 +    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
 +    object_unref(OBJECT(bmc->soc));
 +    sc = ASPEED_SOC_GET_CLASS(bmc->soc);
      /*
       * This will error out if the RAM size is not supported by the
       * memory controller of the SoC.
       */
 -    object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 +    object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
                               &error_fatal);
      for (i = 0; i < sc->macs_num; i++) {
          if ((amc->macs_mask & (1 << i)) && nd->used) {
              qemu_check_nic_model(nd, TYPE_FTGMAC100);
 -            qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 +            qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
              nd++;
          }
      }
 -    object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 +    object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
                              &error_abort);
 -    object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 +    object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
                              &error_abort);
 -    object_property_set_link(OBJECT(&bmc->soc), "memory",
 +    object_property_set_link(OBJECT(bmc->soc), "memory",
                               OBJECT(get_system_memory()), &error_abort);
 -    object_property_set_link(OBJECT(&bmc->soc), "dram",
 +    object_property_set_link(OBJECT(bmc->soc), "dram",
                               OBJECT(machine->ram), &error_abort);
      if (machine->kernel_filename) {
          /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
           * that runs to unlock the SCU. In this case set the default to
           * be unlocked as the kernel expects
           */
 -        object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 +        object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
                                  ASPEED_SCU_PROT_KEY, &error_abort);
      }
      connect_serial_hds_to_uarts(bmc);
 -    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 +    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
      if (defaults_enabled()) {
 -        aspeed_board_init_flashes(&bmc->soc.fmc,
 +        aspeed_board_init_flashes(&bmc->soc->fmc,
                                bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                                amc->num_cs, 0);
 -        aspeed_board_init_flashes(&bmc->soc.spi[0],
 +        aspeed_board_init_flashes(&bmc->soc->spi[0],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
 , amc->num_cs);
      }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
          amc->i2c_init(bmc);
      }
 -    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 -        sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 +    for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
 +        sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
                             drive_get(IF_SD, 0, i));
      }
 -    if (bmc->soc.emmc.num_slots) {
 -        sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 -                           drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 +    if (bmc->soc->emmc.num_slots) {
 +        sdhci_attach_drive(&bmc->soc->emmc.slots[0],
 +                           drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
      }
      if (!bmc->mmio_exec) {
 -        DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
 +        DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
          BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
          if (fmc0) {
 -            uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
 +            uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
              aspeed_install_boot_rom(bmc, fmc0, rom_size);
          }
      }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
  static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      DeviceState *dev;
      uint8_t *eeprom_buf = g_malloc0(32 * 1024);
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
  static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /*
       * The quanta-q71l platform expects tmp75s which are compatible with
@@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
  static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
  static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
  static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
      at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
  static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
       * good enough */
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
  static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
      at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
  static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* bus 2 : */
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
          {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
          {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
      };
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      DeviceState *dev;
      LEDState *led;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
  static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      DeviceState *dev;
      dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
  static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *i2c_mux;
      /* The at24c256 */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
  static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *i2c_mux;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
  static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[144] = {};
      for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
  static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[13] = {};
      for (int i = 0; i < 13; i++) {
          if ((i == 8) || (i == 11)) {
@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
  static void fby35_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[16];
      for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
  static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
  }
  static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *therm_mux, *cpuvr_mux;
      /* Create the generic DC-SCM hardware */
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
  static void fby35_reset(MachineState *state, ShutdownCause reason)
  {
      AspeedMachineState *bmc = ASPEED_MACHINE(state);
 -    AspeedGPIOState *gpio = &bmc->soc.gpio;
 +    AspeedGPIOState *gpio = &bmc->soc->gpio;
      qemu_devices_reset(reason);
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
      sysclk = clock_new(OBJECT(machine), "SYSCLK");
      clock_set_hz(sysclk, SYSCLK_FRQ);
 -    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 -    qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
 +    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
 +    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
 +    object_unref(OBJECT(bmc->soc));
 +    qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
 -    object_property_set_link(OBJECT(&bmc->soc), "memory",
 +    object_property_set_link(OBJECT(bmc->soc), "memory",
                               OBJECT(get_system_memory()), &error_abort);
      connect_serial_hds_to_uarts(bmc);
 -    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 +    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 -    aspeed_board_init_flashes(&bmc->soc.fmc,
 +    aspeed_board_init_flashes(&bmc->soc->fmc,
                                bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                                amc->num_cs,
 );
 -    aspeed_board_init_flashes(&bmc->soc.spi[0],
 +    aspeed_board_init_flashes(&bmc->soc->spi[0],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
                                amc->num_cs, amc->num_cs);
 -    aspeed_board_init_flashes(&bmc->soc.spi[1],
 +    aspeed_board_init_flashes(&bmc->soc->spi[1],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
                                amc->num_cs, (amc->num_cs * 2));
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
  static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* U10 24C08 connects to SDA/SCL Group 1 by default */
      uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 --
-.34.1
+.41.0

-New patch
+[PULL 06/12] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
+In few commits we'll add more fields, but to keep
+review process simple, don't add any yet.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Cédric Le Goater <clg@kaod.org>
+---
+ include/hw/arm/aspeed_soc.h |  7 +++++++
+ hw/arm/aspeed_ast10x0.c     | 26 +++++++++++++-------------
+files changed, 20 insertions(+), 13 deletions(-)
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/aspeed_soc.h
++++ b/include/hw/arm/aspeed_soc.h
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
+ #define TYPE_ASPEED_SOC "aspeed-soc"
+ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
++struct Aspeed10x0SoCState {
++    AspeedSoCState parent;
++};
++
++#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
++OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
++
+ struct AspeedSoCClass {
+     DeviceClass parent_class;
+diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/aspeed_ast10x0.c
++++ b/hw/arm/aspeed_ast10x0.c
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
+     sc->get_irq = aspeed_soc_ast1030_get_irq;
+ }
+-static const TypeInfo aspeed_soc_ast1030_type_info = {
+-    .name          = "ast1030-a1",
+-    .parent        = TYPE_ASPEED_SOC,
+-    .instance_size = sizeof(AspeedSoCState),
+-    .instance_init = aspeed_soc_ast1030_init,
+-    .class_init    = aspeed_soc_ast1030_class_init,
+-    .class_size    = sizeof(AspeedSoCClass),
++static const TypeInfo aspeed_soc_ast10x0_types[] = {
++    {
++        .name           = TYPE_ASPEED10X0_SOC,
++        .parent         = TYPE_ASPEED_SOC,
++        .instance_size  = sizeof(Aspeed10x0SoCState),
++        .abstract       = true,
++    }, {
++        .name           = "ast1030-a1",
++        .parent         = TYPE_ASPEED10X0_SOC,
++        .instance_init  = aspeed_soc_ast1030_init,
++        .class_init     = aspeed_soc_ast1030_class_init,
++    },
+ };
+-static void aspeed_soc_register_types(void)
+-{
+-    type_register_static(&aspeed_soc_ast1030_type_info);
+-}
+-
+-type_init(aspeed_soc_register_types)
++DEFINE_TYPES(aspeed_soc_ast10x0_types)
+--
+.41.0

-[PULL 1/7] arm: Remove swift-bmc machine
+[PULL 07/12] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
-From: Joel Stanley <joel@jms.id.au>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-It was scheduled for removal in 7.0.
+TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
 In few commits we'll add more fields, but to keep
 review process simple, don't add any yet.
-Signed-off-by: Joel Stanley <joel@jms.id.au>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- docs/about/deprecated.rst       |  7 ----
+ include/hw/arm/aspeed_soc.h |  7 +++++++
- docs/about/removed-features.rst |  5 +++
+ hw/arm/aspeed_ast2600.c     | 26 +++++++++++++-------------
- docs/system/arm/aspeed.rst      |  1 -
+files changed, 20 insertions(+), 13 deletions(-)
  hw/arm/aspeed.c                 | 64 ---------------------------------
 files changed, 5 insertions(+), 72 deletions(-)
-diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/about/deprecated.rst
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/docs/about/deprecated.rst
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ Use the more generic event ``DEVICE_UNPLUG_GUEST_ERROR`` instead.
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
- System emulator machines
+ #define TYPE_ASPEED_SOC "aspeed-soc"
- ------------------------
+ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
--Aspeed ``swift-bmc`` machine (since 6.1)
++struct Aspeed2600SoCState {
--''''''''''''''''''''''''''''''''''''''''
++    AspeedSoCState parent;
--
++};
--This machine is deprecated because we have enough AST2500 based OpenPOWER
++
--machines. It can be easily replaced by the ``witherspoon-bmc`` or the
++#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
--``romulus-bmc`` machines.
++OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
--
++
- PPC 405 ``taihu`` machine (since 7.0)
+ struct Aspeed10x0SoCState {
- '''''''''''''''''''''''''''''''''''''
+     AspeedSoCState parent;
+ };
-diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
+diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/about/removed-features.rst
+--- a/hw/arm/aspeed_ast2600.c
-+++ b/docs/about/removed-features.rst
++++ b/hw/arm/aspeed_ast2600.c
-@@ -XXX,XX +XXX,XX @@ The Raspberry Pi machines come in various models (A, A+, B, B+). To be able
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
- to distinguish which model QEMU is implementing, the ``raspi2`` and ``raspi3``
+     sc->get_irq      = aspeed_soc_ast2600_get_irq;
  machines have been renamed ``raspi2b`` and ``raspi3b``.
 +Aspeed ``swift-bmc`` machine (removed in 7.0)
 +'''''''''''''''''''''''''''''''''''''''''''''
 +
 +This machine was removed because it was unused. Alternative AST2500 based
 +OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``.
  linux-user mode CPUs
  --------------------
 diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/aspeed.rst
 +++ b/docs/system/arm/aspeed.rst
@@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines :
  - ``romulus-bmc``          OpenPOWER Romulus POWER9 BMC
  - ``witherspoon-bmc``      OpenPOWER Witherspoon POWER9 BMC
  - ``sonorapass-bmc``       OCP SonoraPass BMC
 -- ``swift-bmc``            OpenPOWER Swift BMC POWER9 (to be removed in v7.0)
  - ``fp5280g2-bmc``         Inspur FP5280G2 BMC
  - ``g220a-bmc``            Bytedance G220A BMC
 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed.c
 +++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
          SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
          SCU_AST2500_HW_STRAP_RESERVED1)
 -/* Swift hardware value: 0xF11AD206 */
 -#define SWIFT_BMC_HW_STRAP1 (                                           \
 -        AST2500_HW_STRAP1_DEFAULTS |                                    \
 -        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 -        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 -        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 -        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 -        SCU_H_PLL_BYPASS_EN |                                           \
 -        SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
 -        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
 -
  #define G220A_BMC_HW_STRAP1 (                                      \
          SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
          SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
  }
--static void swift_bmc_i2c_init(AspeedMachineState *bmc)
+-static const TypeInfo aspeed_soc_ast2600_type_info = {
 -    .name           = "ast2600-a3",
 -    .parent         = TYPE_ASPEED_SOC,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .instance_init  = aspeed_soc_ast2600_init,
 -    .class_init     = aspeed_soc_ast2600_class_init,
 -    .class_size     = sizeof(AspeedSoCClass),
 +static const TypeInfo aspeed_soc_ast2600_types[] = {
 +    {
 +        .name           = TYPE_ASPEED2600_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_size  = sizeof(Aspeed2600SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast2600-a3",
 +        .parent         = TYPE_ASPEED2600_SOC,
 +        .instance_init  = aspeed_soc_ast2600_init,
 +        .class_init     = aspeed_soc_ast2600_class_init,
 +    },
  };
 -static void aspeed_soc_register_types(void)
 -{
--    AspeedSoCState *soc = &bmc->soc;
+-    type_register_static(&aspeed_soc_ast2600_type_info);
 -
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
 -
 -    /* The swift board expects a TMP275 but a TMP105 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
 -    /* The swift board expects a pca9551 but a pca9552 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
 -
 -    /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
 -
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
 -    /* The swift board expects a pca9539 but a pca9552 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
 -
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
 -    /* The swift board expects a pca9539 but a pca9552 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
 -                     0x74);
 -
 -    /* The swift board expects a TMP275 but a TMP105 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
 -}
 -
  static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
  {
      AspeedSoCState *soc = &bmc->soc;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
          aspeed_soc_num_cpus(amc->soc_name);
  };
 -static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
 -{
 -    MachineClass *mc = MACHINE_CLASS(oc);
 -    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
 -
 -    mc->desc       = "OpenPOWER Swift BMC (ARM1176)";
 -    amc->soc_name  = "ast2500-a1";
 -    amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
 -    amc->fmc_model = "mx66l1g45g";
 -    amc->spi_model = "mx66l1g45g";
 -    amc->num_cs    = 2;
 -    amc->i2c_init  = swift_bmc_i2c_init;
 -    mc->default_ram_size       = 512 * MiB;
 -    mc->default_cpus = mc->min_cpus = mc->max_cpus =
 -        aspeed_soc_num_cpus(amc->soc_name);
 -
 -    mc->deprecation_reason = "redundant system. Please use a similar "
 -        "OpenPOWER BMC, Witherspoon or Romulus.";
 -};
 -
- static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
+-type_init(aspeed_soc_register_types)
- {
++DEFINE_TYPES(aspeed_soc_ast2600_types)
      MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
          .name          = MACHINE_TYPE_NAME("romulus-bmc"),
          .parent        = TYPE_ASPEED_MACHINE,
          .class_init    = aspeed_machine_romulus_class_init,
 -    }, {
 -        .name          = MACHINE_TYPE_NAME("swift-bmc"),
 -        .parent        = TYPE_ASPEED_MACHINE,
 -        .class_init    = aspeed_machine_swift_class_init,
      }, {
          .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
          .parent        = TYPE_ASPEED_MACHINE,
 --
-.34.1
+.41.0

-[PULL 2/7] ast2600: Add Secure Boot Controller model
+[PULL 08/12] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
-From: Joel Stanley <joel@jms.id.au>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Just a stub that indicates the system has booted in secure boot mode.
+TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
-Used for testing the driver:
+In few commits we'll add more fields, but to keep
 review process simple, don't add any yet.
- https://lore.kernel.org/all/20211019080608.283324-1-joel@jms.id.au/
+TYPE_ASPEED_SOC is common to various Aspeed SoCs,
 define it in aspeed_soc_common.c.
-Signed-off-by: Joel Stanley <joel@jms.id.au>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-[ clg: - Fixed typo
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
        - Adjusted Copyright dates ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h  |   3 +
+ include/hw/arm/aspeed_soc.h |  7 +++++
- include/hw/misc/aspeed_sbc.h |  32 ++++++++
+ hw/arm/aspeed_soc.c         | 61 +++++++++++--------------------------
- hw/arm/aspeed_ast2600.c      |   9 +++
+ hw/arm/aspeed_soc_common.c  | 29 ++++++++++++++++++
- hw/misc/aspeed_sbc.c         | 141 +++++++++++++++++++++++++++++++++++
+files changed, 53 insertions(+), 44 deletions(-)
  hw/misc/meson.build          |   1 +
 files changed, 186 insertions(+)
  create mode 100644 include/hw/misc/aspeed_sbc.h
  create mode 100644 hw/misc/aspeed_sbc.c
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/aspeed_soc.h
 +++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/misc/aspeed_i3c.h"
- #include "hw/ssi/aspeed_smc.h"
- #include "hw/misc/aspeed_hace.h"
-+#include "hw/misc/aspeed_sbc.h"
- #include "hw/watchdog/wdt_aspeed.h"
- #include "hw/net/ftgmac100.h"
- #include "target/arm/cpu.h"
 @@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
-     AspeedSMCState fmc;
+ #define TYPE_ASPEED_SOC "aspeed-soc"
-     AspeedSMCState spi[ASPEED_SPIS_NUM];
+ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
-     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
-+    AspeedSBCState sbc;
++struct Aspeed2400SoCState {
-     AspeedSDMCState sdmc;
++    AspeedSoCState parent;
      AspeedWDTState wdt[ASPEED_WDTS_NUM];
      FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
@@ -XXX,XX +XXX,XX @@ enum {
      ASPEED_DEV_SDMC,
      ASPEED_DEV_SCU,
      ASPEED_DEV_ADC,
 +    ASPEED_DEV_SBC,
      ASPEED_DEV_VIDEO,
      ASPEED_DEV_SRAM,
      ASPEED_DEV_SDHCI,
 diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/aspeed_sbc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ASPEED Secure Boot Controller
 + *
 + * Copyright (C) 2021-2022 IBM Corp.
 + *
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + */
 +
 +#ifndef ASPEED_SBC_H
 +#define ASPEED_SBC_H
 +
 +#include "hw/sysbus.h"
 +
 +#define TYPE_ASPEED_SBC "aspeed.sbc"
 +#define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
 +OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
 +
 +#define ASPEED_SBC_NR_REGS (0x93c >> 2)
 +
 +struct AspeedSBCState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    uint32_t regs[ASPEED_SBC_NR_REGS];
 +};
 +
-+struct AspeedSBCClass {
++#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
-+    SysBusDeviceClass parent_class;
++OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
 +
  struct Aspeed2600SoCState {
      AspeedSoCState parent;
  };
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc.c
 +++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
                         aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
  }
 -static Property aspeed_soc_properties[] = {
 -    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
 -                     MemoryRegion *),
 -    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
 -                     MemoryRegion *),
 -    DEFINE_PROP_END_OF_LIST(),
 -};
 -
 -static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 -{
 -    DeviceClass *dc = DEVICE_CLASS(oc);
 -
 -    device_class_set_props(dc, aspeed_soc_properties);
 -}
 -
 -static const TypeInfo aspeed_soc_type_info = {
 -    .name           = TYPE_ASPEED_SOC,
 -    .parent         = TYPE_DEVICE,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_size     = sizeof(AspeedSoCClass),
 -    .class_init     = aspeed_soc_class_init,
 -    .abstract       = true,
 -};
  static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
  {
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
      sc->get_irq      = aspeed_soc_ast2400_get_irq;
  }
 -static const TypeInfo aspeed_soc_ast2400_type_info = {
 -    .name           = "ast2400-a1",
 -    .parent         = TYPE_ASPEED_SOC,
 -    .instance_init  = aspeed_ast2400_soc_init,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_init     = aspeed_soc_ast2400_class_init,
 -};
 -
  static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
  {
      AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
      sc->get_irq      = aspeed_soc_ast2400_get_irq;
  }
 -static const TypeInfo aspeed_soc_ast2500_type_info = {
 -    .name           = "ast2500-a1",
 -    .parent         = TYPE_ASPEED_SOC,
 -    .instance_init  = aspeed_ast2400_soc_init,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_init     = aspeed_soc_ast2500_class_init,
 -};
 -static void aspeed_soc_register_types(void)
 -{
 -    type_register_static(&aspeed_soc_type_info);
 -    type_register_static(&aspeed_soc_ast2400_type_info);
 -    type_register_static(&aspeed_soc_ast2500_type_info);
 +static const TypeInfo aspeed_soc_ast2400_types[] = {
 +    {
 +        .name           = TYPE_ASPEED2400_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_init  = aspeed_ast2400_soc_init,
 +        .instance_size  = sizeof(Aspeed2400SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast2400-a1",
 +        .parent         = TYPE_ASPEED2400_SOC,
 +        .class_init     = aspeed_soc_ast2400_class_init,
 +    }, {
 +        .name           = "ast2500-a1",
 +        .parent         = TYPE_ASPEED2400_SOC,
 +        .class_init     = aspeed_soc_ast2500_class_init,
 +    },
  };
 -type_init(aspeed_soc_register_types);
 +DEFINE_TYPES(aspeed_soc_ast2400_types)
 diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc_common.c
 +++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "qapi/error.h"
 +#include "hw/qdev-properties.h"
  #include "hw/misc/unimp.h"
  #include "hw/arm/aspeed_soc.h"
  #include "hw/char/serial.h"
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
      memory_region_add_subregion_overlap(s->memory, addr,
                                          sysbus_mmio_get_region(dev, 0), -1000);
  }
 +
 +static Property aspeed_soc_properties[] = {
 +    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
 +                     MemoryRegion *),
 +    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
 +                     MemoryRegion *),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
-+#endif /* _ASPEED_SBC_H_ */
++static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
++{
-index XXXXXXX..XXXXXXX 100644
++    DeviceClass *dc = DEVICE_CLASS(oc);
 --- a/hw/arm/aspeed_ast2600.c
 +++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
      [ASPEED_DEV_XDMA]      = 0x1E6E7000,
      [ASPEED_DEV_ADC]       = 0x1E6E9000,
      [ASPEED_DEV_DP]        = 0x1E6EB000,
 +    [ASPEED_DEV_SBC]       = 0x1E6F2000,
      [ASPEED_DEV_VIDEO]     = 0x1E700000,
      [ASPEED_DEV_SDHCI]     = 0x1E740000,
      [ASPEED_DEV_EMMC]      = 0x1E750000,
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      object_initialize_child(obj, "hace", &s->hace, typename);
      object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
 +
-+    object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
++    device_class_set_props(dc, aspeed_soc_properties);
  }
  /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
          /* The AST2600 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
      }
 +
 +    /* Secure Boot Controller */
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
 +        return;
 +    }
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
  }
  static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
 diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/aspeed_sbc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ASPEED Secure Boot Controller
 + *
 + * Copyright (C) 2021-2022 IBM Corp.
 + *
 + * Joel Stanley <joel@jms.id.au>
 + *
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "qemu/error-report.h"
 +#include "hw/misc/aspeed_sbc.h"
 +#include "qapi/error.h"
 +#include "migration/vmstate.h"
 +
 +#define R_PROT          (0x000 / 4)
 +#define R_STATUS        (0x014 / 4)
 +
 +static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
 +{
 +    AspeedSBCState *s = ASPEED_SBC(opaque);
 +
 +    addr >>= 2;
 +
 +    if (addr >= ASPEED_SBC_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, addr << 2);
 +        return 0;
 +    }
 +
 +    return s->regs[addr];
 +}
 +
-+static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data,
++static const TypeInfo aspeed_soc_types[] = {
-+                              unsigned int size)
++    {
-+{
++        .name           = TYPE_ASPEED_SOC,
-+    AspeedSBCState *s = ASPEED_SBC(opaque);
++        .parent         = TYPE_DEVICE,
-+
++        .instance_size  = sizeof(AspeedSoCState),
-+    addr >>= 2;
++        .class_size     = sizeof(AspeedSoCClass),
-+
++        .class_init     = aspeed_soc_class_init,
-+    if (addr >= ASPEED_SBC_NR_REGS) {
++        .abstract       = true,
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, addr << 2);
 +        return;
 +    }
 +
 +    switch (addr) {
 +    case R_STATUS:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: write to read only register 0x%" HWADDR_PRIx "\n",
 +                      __func__, addr << 2);
 +        return;
 +    default:
 +        break;
 +    }
 +
 +    s->regs[addr] = data;
 +}
 +
 +static const MemoryRegionOps aspeed_sbc_ops = {
 +    .read = aspeed_sbc_read,
 +    .write = aspeed_sbc_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 1,
 +        .max_access_size = 4,
 +    },
 +};
 +
-+static void aspeed_sbc_reset(DeviceState *dev)
++DEFINE_TYPES(aspeed_soc_types)
 +{
 +    struct AspeedSBCState *s = ASPEED_SBC(dev);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    /* Set secure boot enabled, and boot from emmc/spi */
 +    s->regs[R_STATUS] = 1 << 6 | 1 << 5;
 +}
 +
 +static void aspeed_sbc_realize(DeviceState *dev, Error **errp)
 +{
 +    AspeedSBCState *s = ASPEED_SBC(dev);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sbc_ops, s,
 +            TYPE_ASPEED_SBC, 0x1000);
 +
 +    sysbus_init_mmio(sbd, &s->iomem);
 +}
 +
 +static const VMStateDescription vmstate_aspeed_sbc = {
 +    .name = TYPE_ASPEED_SBC,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, AspeedSBCState, ASPEED_SBC_NR_REGS),
 +        VMSTATE_END_OF_LIST(),
 +    }
 +};
 +
 +static void aspeed_sbc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = aspeed_sbc_realize;
 +    dc->reset = aspeed_sbc_reset;
 +    dc->vmsd = &vmstate_aspeed_sbc;
 +}
 +
 +static const TypeInfo aspeed_sbc_info = {
 +    .name = TYPE_ASPEED_SBC,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(AspeedSBCState),
 +    .class_init = aspeed_sbc_class_init,
 +    .class_size = sizeof(AspeedSBCClass)
 +};
 +
 +static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "AST2600 Secure Boot Controller";
 +}
 +
 +static const TypeInfo aspeed_ast2600_sbc_info = {
 +    .name = TYPE_ASPEED_AST2600_SBC,
 +    .parent = TYPE_ASPEED_SBC,
 +    .class_init = aspeed_ast2600_sbc_class_init,
 +};
 +
 +static void aspeed_sbc_register_types(void)
 +{
 +    type_register_static(&aspeed_ast2600_sbc_info);
 +    type_register_static(&aspeed_sbc_info);
 +}
 +
 +type_init(aspeed_sbc_register_types);
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
    'aspeed_i3c.c',
    'aspeed_lpc.c',
    'aspeed_scu.c',
 +  'aspeed_sbc.c',
    'aspeed_sdmc.c',
    'aspeed_xdma.c'))
 --
-.34.1
+.41.0

-[PULL 5/7] aspeed: Introduce a create_pca9552() helper
+[PULL 09/12] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
-This unifies the way we create the pca9552 devices on the different boards.
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed.c | 49 +++++++++++++++++++++++++++----------------------
+ hw/arm/aspeed_soc_common.c | 11 +++++++++++
-file changed, 27 insertions(+), 22 deletions(-)
+file changed, 11 insertions(+)
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
+diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
+--- a/hw/arm/aspeed_soc_common.c
-+++ b/hw/arm/aspeed.c
++++ b/hw/arm/aspeed_soc_common.c
-@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
+@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
+                                         sysbus_mmio_get_region(dev, 0), -1000);
  }
-+static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
++static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 +{
-+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
++    AspeedSoCState *s = ASPEED_SOC(dev);
-+                            TYPE_PCA9552, addr);
++
 +    if (!s->memory) {
 +        error_setg(errp, "'memory' link is not set");
 +        return;
 +    }
 +}
 +
- static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
+ static Property aspeed_soc_properties[] = {
      DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
                       MemoryRegion *),
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
  {
-     AspeedSoCState *soc = &bmc->soc;
+     DeviceClass *dc = DEVICE_CLASS(oc);
-@@ -XXX,XX +XXX,XX @@ static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
-     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
++    dc->realize = aspeed_soc_realize;
-                           eeprom4_54);
+     device_class_set_props(dc, aspeed_soc_properties);
      /* PCA9539 @ 0x76, but PCA9552 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
 +    create_pca9552(soc, 4, 0x76);
      /* PCA9539 @ 0x77, but PCA9552 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
 +    create_pca9552(soc, 4, 0x77);
      /* bus 6 : */
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
      uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
      smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
                            eeprom8_56);
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
 +    create_pca9552(soc, 8, 0x60);
 +    create_pca9552(soc, 8, 0x61);
      /* bus 8 : adc128d818 @ 0x1d */
      /* bus 8 : adc128d818 @ 0x1f */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
      /* It expects a pca9555 but a pca9552 is compatible */
 -    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552,
 -                     0x20);
 +    create_pca9552(soc, 8, 0x30);
  }
- static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x61);
-+    create_pca9552(soc, 3, 0x61);
-     /* The rainier expects a TMP275 but a TMP105 is compatible */
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x60);
-+    create_pca9552(soc, 4, 0x60);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
-x48);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
-x49);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x60);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x61);
-+    create_pca9552(soc, 5, 0x60);
-+    create_pca9552(soc, 5, 0x61);
-     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
-                                       "pca9546", 0x70);
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x30);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x31);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x32);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x33);
-+    create_pca9552(soc, 7, 0x30);
-+    create_pca9552(soc, 7, 0x31);
-+    create_pca9552(soc, 7, 0x32);
-+    create_pca9552(soc, 7, 0x33);
-     /* Bus 7: TODO max31785@52 */
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
-+    create_pca9552(soc, 7, 0x60);
-+    create_pca9552(soc, 7, 0x61);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
-     /* Bus 7: TODO si7021-a20@20 */
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-x4a);
-     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
-     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
-+    create_pca9552(soc, 8, 0x60);
-+    create_pca9552(soc, 8, 0x61);
-     /* Bus 8: ucd90320@11 */
-     /* Bus 8: ucd90320@b */
-     /* Bus 8: ucd90320@c */
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-                                       "pca9546", 0x70);
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "pca9552", 0x60);
-+    create_pca9552(soc, 11, 0x60);
-     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), "pca9552", 0x60);
-+    create_pca9552(soc, 13, 0x60);
-     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 14), "pca9552", 0x60);
-+    create_pca9552(soc, 14, 0x60);
-     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
--    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "pca9552", 0x60);
-+    create_pca9552(soc, 15, 0x60);
- }
- static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 --
-.34.1
+.41.0

-[PULL 7/7] aspeed/sdmc: Add trace events
+[PULL 10/12] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
-This is useful to analyze changes in the U-Boot RAM driver when SDRAM
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 training is performed.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+The v7-M core is specific to the Aspeed 10x0 series,
 remove it from the common AspeedSoCState.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/misc/aspeed_sdmc.c | 2 ++
+ include/hw/arm/aspeed_soc.h |  5 ++---
- hw/misc/trace-events  | 4 ++++
+ hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
-files changed, 6 insertions(+)
+ hw/arm/fby35.c              | 13 ++++++++-----
 files changed, 25 insertions(+), 20 deletions(-)
-diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/aspeed_sdmc.c
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/hw/misc/aspeed_sdmc.c
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
+@@ -XXX,XX +XXX,XX @@
-         return 0;
+ #define ASPEED_JTAG_NUM  2
  struct AspeedSoCState {
 -    /*< private >*/
      DeviceState parent;
 -    /*< public >*/
      ARMCPU cpu[ASPEED_CPUS_NUM];
      A15MPPrivState     a7mpcore;
 -    ARMv7MState        armv7m;
      MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
  struct Aspeed10x0SoCState {
      AspeedSoCState parent;
 +
 +    ARMv7MState armv7m;
  };
  #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast10x0.c
 +++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
  static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
 +    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
  }
  static void aspeed_soc_ast1030_init(Object *obj)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      char socname[8];
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
          g_assert_not_reached();
      }
-+    trace_aspeed_sdmc_read(addr, s->regs[addr]);
+-    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
-     return s->regs[addr];
++    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
      s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
  static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
      AspeedSoCState *s = ASPEED_SOC(dev_soc);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      DeviceState *armv7m;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 x40000);
      /* AST1030 CPU Core */
 -    armv7m = DEVICE(&s->armv7m);
 +    armv7m = DEVICE(&a->armv7m);
      qdev_prop_set_uint32(armv7m, "num-irq", 256);
      qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
      qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
 -    object_property_set_link(OBJECT(&s->armv7m), "memory",
 +    object_property_set_link(OBJECT(&a->armv7m), "memory",
                               OBJECT(s->memory), &error_abort);
 -    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
 +    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
      /* Internal SRAM */
      sram_name = g_strdup_printf("aspeed.sram.%d",
 -                                CPU(s->armv7m.cpu)->cpu_index);
 +                                CPU(a->armv7m.cpu)->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err != NULL) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
      for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
 -        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
 +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I2C] + i);
          /* The AST1030 I2C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
      for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
 -        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
 +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I3C] + i);
          /* The AST1030 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
       * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
       */
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
      /* UART */
 diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fby35.c
 +++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
      Clock *bic_sysclk;
      AspeedSoCState bmc;
 -    AspeedSoCState bic;
 +    Aspeed10x0SoCState bic;
      bool mmio_exec;
  };
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
  static void fby35_bic_init(Fby35State *s)
  {
 +    AspeedSoCState *soc;
 +
      s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
      clock_set_hz(s->bic_sysclk, 200000000ULL);
      object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
 +    soc = ASPEED_SOC(&s->bic);
      memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
                         UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)
      qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
      object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                               &error_abort);
 -    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
 +    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
      qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
 -    aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
 -    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
 -    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
 +    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
 +    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
 +    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
  }
-@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
+ static void fby35_init(MachineState *machine)
          return;
      }
 +    trace_aspeed_sdmc_write(addr, data);
      asc->write(s, addr, data);
  }
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64
  aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
  aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
 +# aspeed_sdmc.c
 +aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
 +aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
 +
  # bcm2835_property.c
  bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu"
 --
-.34.1
+.41.0

-[PULL 3/7] aspeed: rainier: Add i2c LED devices
+[PULL 11/12] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
-From: Joel Stanley <joel@jms.id.au>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-This helps quieten booting the current Rainier kernel.
+The v7-A cluster is specific to the Aspeed 2600 series,
+remove it from the common AspeedSoCState.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Joel Stanley <joel@jms.id.au>
+The ARM cores belong to the MP cluster, but the array
 is currently used by TYPE_ASPEED2600_SOC. We'll clean
 that soon, but for now keep it in Aspeed2600SoCState.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed.c | 15 +++++++++++++++
+ include/hw/arm/aspeed_soc.h |  4 ++-
-file changed, 15 insertions(+)
+ hw/arm/aspeed_ast2600.c     | 49 ++++++++++++++++++++-----------------
+ hw/arm/fby35.c              | 14 ++++++-----
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
+files changed, 37 insertions(+), 30 deletions(-)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/hw/arm/aspeed.c
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
+     DeviceState parent;
-     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
+     ARMCPU cpu[ASPEED_CPUS_NUM];
-+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x61);
+-    A15MPPrivState     a7mpcore;
      MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
  struct Aspeed2600SoCState {
      AspeedSoCState parent;
 +
-     /* The rainier expects a TMP275 but a TMP105 is compatible */
++    A15MPPrivState a7mpcore;
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
++    ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
-x48);
+ };
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
+index XXXXXXX..XXXXXXX 100644
-+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x60);
+--- a/hw/arm/aspeed_ast2600.c
++++ b/hw/arm/aspeed_ast2600.c
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
-x48);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
+ static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
-x49);
+ {
-+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x60);
++    Aspeed2600SoCState *a = ASPEED2600_SOC(s);
-+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x61);
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
-                                       "pca9546", 0x70);
+-    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
-     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
++    return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
      aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
      aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x30);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x31);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x32);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x33);
      /* Bus 7: TODO max31785@52 */
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
      /* Bus 7: TODO si7021-a20@20 */
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 x4a);
      aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
      aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
      /* Bus 8: ucd90320@11 */
      /* Bus 8: ucd90320@b */
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
                                        "pca9546", 0x70);
      aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
      aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "pca9552", 0x60);
      aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), "pca9552", 0x60);
      aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 14), "pca9552", 0x60);
      aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
 +    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "pca9552", 0x60);
  }
- static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
+ static void aspeed_soc_ast2600_init(Object *obj)
  {
 +    Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      }
      for (i = 0; i < sc->num_cpus; i++) {
 -        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
 +        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
      }
      snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                                "hw-prot-key");
 -    object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
 +    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
                              TYPE_A15MPCORE_PRIV);
      object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu)
  static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
  {
      int i;
 +    Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
      AspeedSoCState *s = ASPEED_SOC(dev);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      /* CPU */
      for (i = 0; i < sc->num_cpus; i++) {
          if (sc->num_cpus > 1) {
 -            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
 +            object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
                                      ASPEED_A7MPCORE_ADDR, &error_abort);
          }
 -        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
 +        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                  aspeed_calc_affinity(i), &error_abort);
 -        object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
 +        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                  &error_abort);
 -        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
 +        object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
                                  &error_abort);
 -        object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
 +        object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
                                  &error_abort);
 -        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
 +        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                   OBJECT(s->memory), &error_abort);
 -        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
 +        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
              return;
          }
      }
      /* A7MPCORE */
 -    object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
 +    object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
                              &error_abort);
 -    object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
 +    object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
                              ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
                              &error_abort);
 -    sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
 -    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
 +    sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
 +    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
      for (i = 0; i < sc->num_cpus; i++) {
 -        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
 -        DeviceState  *d   = DEVICE(&s->cpu[i]);
 +        SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
 +        DeviceState  *d   = DEVICE(&a->cpu[i]);
          irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
          sysbus_connect_irq(sbd, i, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      /* SRAM */
 -    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
 +    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
      for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
 -        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_I2C] + i);
          /* The AST2600 I2C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
       * offset 0.
       */
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
      /* HACE */
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
      for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
 -        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_I3C] + i);
          /* The AST2600 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
 diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fby35.c
 +++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
      MemoryRegion bic_memory;
      Clock *bic_sysclk;
 -    AspeedSoCState bmc;
 +    Aspeed2600SoCState bmc;
      Aspeed10x0SoCState bic;
      bool mmio_exec;
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
  static void fby35_bmc_init(Fby35State *s)
  {
 +    AspeedSoCState *soc;
 +
      object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
 +    soc = ASPEED_SOC(&s->bmc);
      memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
                         UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
                              &error_abort);
      object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
                              &error_abort);
 -    aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
 +    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
      qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
 -    aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
 +    aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
      /* Install first FMC flash content as a boot rom. */
      if (!s->mmio_exec) {
          DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
          if (mtd0) {
 -            AspeedSoCState *bmc = &s->bmc;
 -            uint64_t rom_size = memory_region_size(&bmc->spi_boot);
 +            uint64_t rom_size = memory_region_size(&soc->spi_boot);
              memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
                                     rom_size, &error_abort);
 -            memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
 +            memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
                                                  &s->bmc_boot_rom, 1);
              fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
 --
-.34.1
+.41.0

-[PULL 6/7] aspeed/smc: Add an address mask on segment registers
+[PULL 12/12] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
-Only a limited set of bits are used for decoding the Start and End
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 addresses of the mapping window of a flash device.
+The ARM array and VIC peripheral are only used by the
+series, remove them from the common AspeedSoCState.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/ssi/aspeed_smc.h |  1 +
+ include/hw/arm/aspeed_soc.h               |  5 +++--
- hw/ssi/aspeed_smc.c         | 11 +++++++++++
+ hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
-files changed, 12 insertions(+)
+ hw/arm/meson.build                        |  2 +-
 files changed, 19 insertions(+), 15 deletions(-)
  rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)
-diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/ssi/aspeed_smc.h
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/include/hw/ssi/aspeed_smc.h
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ struct AspeedSMCClass {
+@@ -XXX,XX +XXX,XX @@
-     uint8_t max_peripherals;
+ struct AspeedSoCState {
-     const uint32_t *resets;
+     DeviceState parent;
-     const AspeedSegments *segments;
-+    uint32_t segment_addr_mask;
+-    ARMCPU cpu[ASPEED_CPUS_NUM];
-     hwaddr flash_window_base;
+     MemoryRegion *memory;
-     uint32_t flash_window_size;
+     MemoryRegion *dram_mr;
-     uint32_t features;
+     MemoryRegion dram_container;
-diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
+     MemoryRegion sram;
      MemoryRegion spi_boot_container;
      MemoryRegion spi_boot;
 -    AspeedVICState vic;
      AspeedRtcState rtc;
      AspeedTimerCtrlState timerctrl;
      AspeedI2CState i2c;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
  struct Aspeed2400SoCState {
      AspeedSoCState parent;
 +
 +    ARMCPU cpu[ASPEED_CPUS_NUM];
 +    AspeedVICState vic;
  };
  #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_ast2400.c
 similarity index 95%
 rename from hw/arm/aspeed_soc.c
 rename to hw/arm/aspeed_ast2400.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/aspeed_smc.c
+--- a/hw/arm/aspeed_soc.c
-+++ b/hw/ssi/aspeed_smc.c
++++ b/hw/arm/aspeed_ast2400.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
-     memory_region_set_enabled(&fl->mmio, !!seg.size);
-     memory_region_transaction_commit();
+ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
+ {
-+    if (asc->segment_addr_mask) {
++    Aspeed2400SoCState *a = ASPEED2400_SOC(s);
-+        regval &= asc->segment_addr_mask;
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-+    }
-+
+-    return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
-     s->regs[R_SEG_ADDR0 + cs] = regval;
++    return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
  }
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data)
+ static void aspeed_ast2400_soc_init(Object *obj)
-     asc->conf_enable_w0    = CONF_ENABLE_W0;
+ {
-     asc->max_peripherals   = 5;
++    Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
-     asc->segments          = aspeed_2400_fmc_segments;
+     AspeedSoCState *s = ASPEED_SOC(obj);
-+    asc->segment_addr_mask = 0xffff0000;
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-     asc->resets            = aspeed_2400_fmc_resets;
+     int i;
-     asc->flash_window_base = 0x20000000;
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
-     asc->flash_window_size = 0x10000000;
+     }
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data)
-     asc->conf_enable_w0    = CONF_ENABLE_W0;
+     for (i = 0; i < sc->num_cpus; i++) {
-     asc->max_peripherals   = 3;
+-        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
-     asc->segments          = aspeed_2500_fmc_segments;
++        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
-+    asc->segment_addr_mask = 0xffff0000;
+     }
-     asc->resets            = aspeed_2500_fmc_resets;
-     asc->flash_window_base = 0x20000000;
+     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
-     asc->flash_window_size = 0x10000000;
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data)
+     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
-     asc->conf_enable_w0    = CONF_ENABLE_W0;
+                               "hw-prot-key");
-     asc->max_peripherals   = 2;
-     asc->segments          = aspeed_2500_spi1_segments;
+-    object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
-+    asc->segment_addr_mask = 0xffff0000;
++    object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
-     asc->flash_window_base = 0x30000000;
-     asc->flash_window_size = 0x8000000;
+     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
-     asc->features          = 0x0;
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data)
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
-     asc->conf_enable_w0    = CONF_ENABLE_W0;
+ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
-     asc->max_peripherals   = 2;
+ {
-     asc->segments          = aspeed_2500_spi2_segments;
+     int i;
-+    asc->segment_addr_mask = 0xffff0000;
++    Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
-     asc->flash_window_base = 0x38000000;
+     AspeedSoCState *s = ASPEED_SOC(dev);
-     asc->flash_window_size = 0x8000000;
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-     asc->features          = 0x0;
+     Error *err = NULL;
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data)
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
-     asc->conf_enable_w0    = CONF_ENABLE_W0;
-     asc->max_peripherals   = 3;
+     /* CPU */
-     asc->segments          = aspeed_2600_fmc_segments;
+     for (i = 0; i < sc->num_cpus; i++) {
-+    asc->segment_addr_mask = 0x0ff00ff0;
+-        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
-     asc->resets            = aspeed_2600_fmc_resets;
++        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
-     asc->flash_window_base = 0x20000000;
+                                  OBJECT(s->memory), &error_abort);
-     asc->flash_window_size = 0x10000000;
+-        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data)
++        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
-     asc->conf_enable_w0    = CONF_ENABLE_W0;
+             return;
-     asc->max_peripherals   = 2;
+         }
-     asc->segments          = aspeed_2600_spi1_segments;
+     }
-+    asc->segment_addr_mask = 0x0ff00ff0;
-     asc->flash_window_base = 0x30000000;
+     /* SRAM */
-     asc->flash_window_size = 0x10000000;
+-    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
-     asc->features          = ASPEED_SMC_FEATURE_DMA |
++    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data)
+     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
-     asc->conf_enable_w0    = CONF_ENABLE_W0;
+     if (err) {
-     asc->max_peripherals   = 3;
+         error_propagate(errp, err);
-     asc->segments          = aspeed_2600_spi2_segments;
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
-+    asc->segment_addr_mask = 0x0ff00ff0;
+     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
-     asc->flash_window_base = 0x50000000;
-     asc->flash_window_size = 0x10000000;
+     /* VIC */
-     asc->features          = ASPEED_SMC_FEATURE_DMA |
+-    if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
          return;
      }
 -    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
 -    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 -                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 -    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 -                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 +    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
 +                       qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
 +                       qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
      /* RTC */
      if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'
  arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
  arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
  arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
 -  'aspeed_soc.c',
    'aspeed.c',
    'aspeed_soc_common.c',
 +  'aspeed_ast2400.c',
    'aspeed_ast2600.c',
    'aspeed_ast10x0.c',
    'aspeed_eeprom.c',
 --
-.34.1
+.41.0

The following changes since commit c13b8e9973635f34f3ce4356af27a311c993729c:

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220216' into staging (2022-02-16 09:57:11 +0000)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20220227

for you to fetch changes up to 3671342a38f21316a2bda62e7d607bbaedd60fd8:

aspeed/sdmc: Add trace events (2022-02-26 18:40:51 +0100)

----------------------------------------------------------------
aspeed queue:

* Removal of the swift-bmc machine
* New Secure Boot Controller model
* Improvements on the rainier machine
* Various small cleanups

----------------------------------------------------------------
Cédric Le Goater (3):
      aspeed: Introduce a create_pca9552() helper
      aspeed/smc: Add an address mask on segment registers
      aspeed/sdmc: Add trace events

Joel Stanley (4):
      arm: Remove swift-bmc machine
      ast2600: Add Secure Boot Controller model
      aspeed: rainier: Add i2c LED devices
      aspeed: rainier: Add strap values taken from hardware

docs/about/deprecated.rst       |   7 --
 docs/about/removed-features.rst |   5 ++
 docs/system/arm/aspeed.rst      |   1 -
 include/hw/arm/aspeed_soc.h     |   3 +
 include/hw/misc/aspeed_sbc.h    |  32 +++++++++
 include/hw/ssi/aspeed_smc.h     |   1 +
 hw/arm/aspeed.c                 |  98 ++++++++--------------------
 hw/arm/aspeed_ast2600.c         |   9 +++
 hw/misc/aspeed_sbc.c            | 141 ++++++++++++++++++++++++++++++++++++++++
 hw/misc/aspeed_sdmc.c           |   2 +
 hw/ssi/aspeed_smc.c             |  11 ++++
 hw/misc/meson.build             |   1 +
 hw/misc/trace-events            |   4 ++
 13 files changed, 236 insertions(+), 79 deletions(-)
 create mode 100644 include/hw/misc/aspeed_sbc.h
 create mode 100644 hw/misc/aspeed_sbc.c

From: Joel Stanley <joel@jms.id.au>

It was scheduled for removal in 7.0.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 docs/about/deprecated.rst       |  7 ----
 docs/about/removed-features.rst |  5 +++
 docs/system/arm/aspeed.rst      |  1 -
 hw/arm/aspeed.c                 | 64 ---------------------------------
 4 files changed, 5 insertions(+), 72 deletions(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ Use the more generic event ``DEVICE_UNPLUG_GUEST_ERROR`` instead.
 System emulator machines
 ------------------------
 
-Aspeed ``swift-bmc`` machine (since 6.1)
-''''''''''''''''''''''''''''''''''''''''
-
-This machine is deprecated because we have enough AST2500 based OpenPOWER
-machines. It can be easily replaced by the ``witherspoon-bmc`` or the
-``romulus-bmc`` machines.
-
 PPC 405 ``taihu`` machine (since 7.0)
 '''''''''''''''''''''''''''''''''''''
 
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -XXX,XX +XXX,XX @@ The Raspberry Pi machines come in various models (A, A+, B, B+). To be able
 to distinguish which model QEMU is implementing, the ``raspi2`` and ``raspi3``
 machines have been renamed ``raspi2b`` and ``raspi3b``.
 
+Aspeed ``swift-bmc`` machine (removed in 7.0)
+'''''''''''''''''''''''''''''''''''''''''''''
+
+This machine was removed because it was unused. Alternative AST2500 based
+OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``.
 
 linux-user mode CPUs
 --------------------
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines :
 - ``romulus-bmc``          OpenPOWER Romulus POWER9 BMC
 - ``witherspoon-bmc``      OpenPOWER Witherspoon POWER9 BMC
 - ``sonorapass-bmc``       OCP SonoraPass BMC
-- ``swift-bmc``            OpenPOWER Swift BMC POWER9 (to be removed in v7.0)
 - ``fp5280g2-bmc``         Inspur FP5280G2 BMC
 - ``g220a-bmc``            Bytedance G220A BMC
 
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
         SCU_AST2500_HW_STRAP_RESERVED1)
 
-/* Swift hardware value: 0xF11AD206 */
-#define SWIFT_BMC_HW_STRAP1 (                                           \
-        AST2500_HW_STRAP1_DEFAULTS |                                    \
-        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
-        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
-        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
-        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
-        SCU_H_PLL_BYPASS_EN |                                           \
-        SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
-        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
-
 #define G220A_BMC_HW_STRAP1 (                                      \
         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 }
 
-static void swift_bmc_i2c_init(AspeedMachineState *bmc)
-{
-    AspeedSoCState *soc = &bmc->soc;
-
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
-
-    /* The swift board expects a TMP275 but a TMP105 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
-    /* The swift board expects a pca9551 but a pca9552 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
-
-    /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
-
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
-    /* The swift board expects a pca9539 but a pca9552 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
-
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
-    /* The swift board expects a pca9539 but a pca9552 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
-                     0x74);
-
-    /* The swift board expects a TMP275 but a TMP105 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
-}
-
 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = &bmc->soc;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
         aspeed_soc_num_cpus(amc->soc_name);
 };
 
-static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
-{
-    MachineClass *mc = MACHINE_CLASS(oc);
-    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
-    mc->desc       = "OpenPOWER Swift BMC (ARM1176)";
-    amc->soc_name  = "ast2500-a1";
-    amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
-    amc->fmc_model = "mx66l1g45g";
-    amc->spi_model = "mx66l1g45g";
-    amc->num_cs    = 2;
-    amc->i2c_init  = swift_bmc_i2c_init;
-    mc->default_ram_size       = 512 * MiB;
-    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-        aspeed_soc_num_cpus(amc->soc_name);
-
-    mc->deprecation_reason = "redundant system. Please use a similar "
-        "OpenPOWER BMC, Witherspoon or Romulus.";
-};
-
 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_romulus_class_init,
-    }, {
-        .name          = MACHINE_TYPE_NAME("swift-bmc"),
-        .parent        = TYPE_ASPEED_MACHINE,
-        .class_init    = aspeed_machine_swift_class_init,
     }, {
         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
-- 
2.34.1

From: Joel Stanley <joel@jms.id.au>

Just a stub that indicates the system has booted in secure boot mode.
Used for testing the driver:

https://lore.kernel.org/all/20211019080608.283324-1-joel@jms.id.au/

Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: - Fixed typo
       - Adjusted Copyright dates ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h  |   3 +
 include/hw/misc/aspeed_sbc.h |  32 ++++++++
 hw/arm/aspeed_ast2600.c      |   9 +++
 hw/misc/aspeed_sbc.c         | 141 +++++++++++++++++++++++++++++++++++
 hw/misc/meson.build          |   1 +
 5 files changed, 186 insertions(+)
 create mode 100644 include/hw/misc/aspeed_sbc.h
 create mode 100644 hw/misc/aspeed_sbc.c

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/aspeed_i3c.h"
 #include "hw/ssi/aspeed_smc.h"
 #include "hw/misc/aspeed_hace.h"
+#include "hw/misc/aspeed_sbc.h"
 #include "hw/watchdog/wdt_aspeed.h"
 #include "hw/net/ftgmac100.h"
 #include "target/arm/cpu.h"
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
     AspeedSMCState fmc;
     AspeedSMCState spi[ASPEED_SPIS_NUM];
     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
+    AspeedSBCState sbc;
     AspeedSDMCState sdmc;
     AspeedWDTState wdt[ASPEED_WDTS_NUM];
     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
@@ -XXX,XX +XXX,XX @@ enum {
     ASPEED_DEV_SDMC,
     ASPEED_DEV_SCU,
     ASPEED_DEV_ADC,
+    ASPEED_DEV_SBC,
     ASPEED_DEV_VIDEO,
     ASPEED_DEV_SRAM,
     ASPEED_DEV_SDHCI,
diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/aspeed_sbc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED Secure Boot Controller
+ *
+ * Copyright (C) 2021-2022 IBM Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef ASPEED_SBC_H
+#define ASPEED_SBC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_SBC "aspeed.sbc"
+#define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
+OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
+
+#define ASPEED_SBC_NR_REGS (0x93c >> 2)
+
+struct AspeedSBCState {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    uint32_t regs[ASPEED_SBC_NR_REGS];
+};
+
+struct AspeedSBCClass {
+    SysBusDeviceClass parent_class;
+};
+
+#endif /* _ASPEED_SBC_H_ */
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
     [ASPEED_DEV_XDMA]      = 0x1E6E7000,
     [ASPEED_DEV_ADC]       = 0x1E6E9000,
     [ASPEED_DEV_DP]        = 0x1E6EB000,
+    [ASPEED_DEV_SBC]       = 0x1E6F2000,
     [ASPEED_DEV_VIDEO]     = 0x1E700000,
     [ASPEED_DEV_SDHCI]     = 0x1E740000,
     [ASPEED_DEV_EMMC]      = 0x1E750000,
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     object_initialize_child(obj, "hace", &s->hace, typename);
 
     object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
+
+    object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
         /* The AST2600 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
     }
+
+    /* Secure Boot Controller */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
 }
 
 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/aspeed_sbc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED Secure Boot Controller
+ *
+ * Copyright (C) 2021-2022 IBM Corp.
+ *
+ * Joel Stanley <joel@jms.id.au>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/misc/aspeed_sbc.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+
+#define R_PROT          (0x000 / 4)
+#define R_STATUS        (0x014 / 4)
+
+static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    AspeedSBCState *s = ASPEED_SBC(opaque);
+
+    addr >>= 2;
+
+    if (addr >= ASPEED_SBC_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr << 2);
+        return 0;
+    }
+
+    return s->regs[addr];
+}
+
+static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data,
+                              unsigned int size)
+{
+    AspeedSBCState *s = ASPEED_SBC(opaque);
+
+    addr >>= 2;
+
+    if (addr >= ASPEED_SBC_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr << 2);
+        return;
+    }
+
+    switch (addr) {
+    case R_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to read only register 0x%" HWADDR_PRIx "\n",
+                      __func__, addr << 2);
+        return;
+    default:
+        break;
+    }
+
+    s->regs[addr] = data;
+}
+
+static const MemoryRegionOps aspeed_sbc_ops = {
+    .read = aspeed_sbc_read,
+    .write = aspeed_sbc_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 4,
+    },
+};
+
+static void aspeed_sbc_reset(DeviceState *dev)
+{
+    struct AspeedSBCState *s = ASPEED_SBC(dev);
+
+    memset(s->regs, 0, sizeof(s->regs));
+
+    /* Set secure boot enabled, and boot from emmc/spi */
+    s->regs[R_STATUS] = 1 << 6 | 1 << 5;
+}
+
+static void aspeed_sbc_realize(DeviceState *dev, Error **errp)
+{
+    AspeedSBCState *s = ASPEED_SBC(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sbc_ops, s,
+            TYPE_ASPEED_SBC, 0x1000);
+
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_aspeed_sbc = {
+    .name = TYPE_ASPEED_SBC,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, AspeedSBCState, ASPEED_SBC_NR_REGS),
+        VMSTATE_END_OF_LIST(),
+    }
+};
+
+static void aspeed_sbc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = aspeed_sbc_realize;
+    dc->reset = aspeed_sbc_reset;
+    dc->vmsd = &vmstate_aspeed_sbc;
+}
+
+static const TypeInfo aspeed_sbc_info = {
+    .name = TYPE_ASPEED_SBC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(AspeedSBCState),
+    .class_init = aspeed_sbc_class_init,
+    .class_size = sizeof(AspeedSBCClass)
+};
+
+static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "AST2600 Secure Boot Controller";
+}
+
+static const TypeInfo aspeed_ast2600_sbc_info = {
+    .name = TYPE_ASPEED_AST2600_SBC,
+    .parent = TYPE_ASPEED_SBC,
+    .class_init = aspeed_ast2600_sbc_class_init,
+};
+
+static void aspeed_sbc_register_types(void)
+{
+    type_register_static(&aspeed_ast2600_sbc_info);
+    type_register_static(&aspeed_sbc_info);
+}
+
+type_init(aspeed_sbc_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_i3c.c',
   'aspeed_lpc.c',
   'aspeed_scu.c',
+  'aspeed_sbc.c',
   'aspeed_sdmc.c',
   'aspeed_xdma.c'))
 
-- 
2.34.1

From: Joel Stanley <joel@jms.id.au>

This helps quieten booting the current Rainier kernel.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x61);
+
     /* The rainier expects a TMP275 but a TMP105 is compatible */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
                      0x48);
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x60);
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
                      0x48);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
                      0x49);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x60);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x61);
     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
                                       "pca9546", 0x70);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x30);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x31);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x32);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x33);
     /* Bus 7: TODO max31785@52 */
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
     /* Bus 7: TODO si7021-a20@20 */
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
                      0x4a);
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
     /* Bus 8: ucd90320@11 */
     /* Bus 8: ucd90320@b */
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
                                       "pca9546", 0x70);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "pca9552", 0x60);
 
 
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), "pca9552", 0x60);
 
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 14), "pca9552", 0x60);
 
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "pca9552", 0x60);
 }
 
 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
-- 
2.34.1

From: Joel Stanley <joel@jms.id.au>

When time permits, we should introduce defines for the HW strapping
registers to cleanly decode the values.

SCU500 = 0x00422016
  Disable ARM JTAG trusted world debug: 0x1
  Disable ARM JTAG debug: 0x1
  VGA Memory Size: 0x1 [16MB]
  Cortex M3: 0x1 [Disabled]
  Boot device: 0x1 [eMMC]
  Reserved: 0x1

SCU510 = 0x80000848
  Secure Boot Enable: 0x1
  Enable boot SPI or eMMC ABR (second boot): 0x1
  Enable LPC mode: 0x1 [LPC]
  Disable LPC SuperIO 0x2e/0x4e: 0x1

Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: rewrote the commit log ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
 #define TACOMA_BMC_HW_STRAP2  0x00000040
 
 /* Rainier hardware value: (QEMU prototype) */
-#define RAINIER_BMC_HW_STRAP1 0x00000000
-#define RAINIER_BMC_HW_STRAP2 0x00000000
+#define RAINIER_BMC_HW_STRAP1 0x00422016
+#define RAINIER_BMC_HW_STRAP2 0x80000848
 
 /* Fuji hardware value */
 #define FUJI_BMC_HW_STRAP1    0x00000000
-- 
2.34.1

This unifies the way we create the pca9552 devices on the different boards.

Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 49 +++++++++++++++++++++++++++----------------------
 1 file changed, 27 insertions(+), 22 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 }
 
+static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
+{
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
+                            TYPE_PCA9552, addr);
+}
+
 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = &bmc->soc;
@@ -XXX,XX +XXX,XX @@ static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
                           eeprom4_54);
     /* PCA9539 @ 0x76, but PCA9552 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
+    create_pca9552(soc, 4, 0x76);
     /* PCA9539 @ 0x77, but PCA9552 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
+    create_pca9552(soc, 4, 0x77);
 
     /* bus 6 : */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
     uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
                           eeprom8_56);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
+    create_pca9552(soc, 8, 0x60);
+    create_pca9552(soc, 8, 0x61);
     /* bus 8 : adc128d818 @ 0x1d */
     /* bus 8 : adc128d818 @ 0x1f */
 
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
 
     /* It expects a pca9555 but a pca9552 is compatible */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552,
-                     0x20);
+    create_pca9552(soc, 8, 0x30);
 }
 
 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x61);
+    create_pca9552(soc, 3, 0x61);
 
     /* The rainier expects a TMP275 but a TMP105 is compatible */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x60);
+    create_pca9552(soc, 4, 0x60);
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
                      0x48);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
                      0x49);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x60);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x61);
+    create_pca9552(soc, 5, 0x60);
+    create_pca9552(soc, 5, 0x61);
     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
                                       "pca9546", 0x70);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x30);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x31);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x32);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x33);
+    create_pca9552(soc, 7, 0x30);
+    create_pca9552(soc, 7, 0x31);
+    create_pca9552(soc, 7, 0x32);
+    create_pca9552(soc, 7, 0x33);
     /* Bus 7: TODO max31785@52 */
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
+    create_pca9552(soc, 7, 0x60);
+    create_pca9552(soc, 7, 0x61);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
     /* Bus 7: TODO si7021-a20@20 */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
                      0x4a);
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
+    create_pca9552(soc, 8, 0x60);
+    create_pca9552(soc, 8, 0x61);
     /* Bus 8: ucd90320@11 */
     /* Bus 8: ucd90320@b */
     /* Bus 8: ucd90320@c */
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
                                       "pca9546", 0x70);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "pca9552", 0x60);
+    create_pca9552(soc, 11, 0x60);
 
 
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), "pca9552", 0x60);
+    create_pca9552(soc, 13, 0x60);
 
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 14), "pca9552", 0x60);
+    create_pca9552(soc, 14, 0x60);
 
     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
-    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "pca9552", 0x60);
+    create_pca9552(soc, 15, 0x60);
 }
 
 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
-- 
2.34.1

Only a limited set of bits are used for decoding the Start and End
addresses of the mapping window of a flash device.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ssi/aspeed_smc.h |  1 +
 hw/ssi/aspeed_smc.c         | 11 +++++++++++
 2 files changed, 12 insertions(+)

diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSMCClass {
     uint8_t max_peripherals;
     const uint32_t *resets;
     const AspeedSegments *segments;
+    uint32_t segment_addr_mask;
     hwaddr flash_window_base;
     uint32_t flash_window_size;
     uint32_t features;
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
     memory_region_set_enabled(&fl->mmio, !!seg.size);
     memory_region_transaction_commit();
 
+    if (asc->segment_addr_mask) {
+        regval &= asc->segment_addr_mask;
+    }
+
     s->regs[R_SEG_ADDR0 + cs] = regval;
 }
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data)
     asc->conf_enable_w0    = CONF_ENABLE_W0;
     asc->max_peripherals   = 5;
     asc->segments          = aspeed_2400_fmc_segments;
+    asc->segment_addr_mask = 0xffff0000;
     asc->resets            = aspeed_2400_fmc_resets;
     asc->flash_window_base = 0x20000000;
     asc->flash_window_size = 0x10000000;
@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data)
     asc->conf_enable_w0    = CONF_ENABLE_W0;
     asc->max_peripherals   = 3;
     asc->segments          = aspeed_2500_fmc_segments;
+    asc->segment_addr_mask = 0xffff0000;
     asc->resets            = aspeed_2500_fmc_resets;
     asc->flash_window_base = 0x20000000;
     asc->flash_window_size = 0x10000000;
@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data)
     asc->conf_enable_w0    = CONF_ENABLE_W0;
     asc->max_peripherals   = 2;
     asc->segments          = aspeed_2500_spi1_segments;
+    asc->segment_addr_mask = 0xffff0000;
     asc->flash_window_base = 0x30000000;
     asc->flash_window_size = 0x8000000;
     asc->features          = 0x0;
@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data)
     asc->conf_enable_w0    = CONF_ENABLE_W0;
     asc->max_peripherals   = 2;
     asc->segments          = aspeed_2500_spi2_segments;
+    asc->segment_addr_mask = 0xffff0000;
     asc->flash_window_base = 0x38000000;
     asc->flash_window_size = 0x8000000;
     asc->features          = 0x0;
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data)
     asc->conf_enable_w0    = CONF_ENABLE_W0;
     asc->max_peripherals   = 3;
     asc->segments          = aspeed_2600_fmc_segments;
+    asc->segment_addr_mask = 0x0ff00ff0;
     asc->resets            = aspeed_2600_fmc_resets;
     asc->flash_window_base = 0x20000000;
     asc->flash_window_size = 0x10000000;
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data)
     asc->conf_enable_w0    = CONF_ENABLE_W0;
     asc->max_peripherals   = 2;
     asc->segments          = aspeed_2600_spi1_segments;
+    asc->segment_addr_mask = 0x0ff00ff0;
     asc->flash_window_base = 0x30000000;
     asc->flash_window_size = 0x10000000;
     asc->features          = ASPEED_SMC_FEATURE_DMA |
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data)
     asc->conf_enable_w0    = CONF_ENABLE_W0;
     asc->max_peripherals   = 3;
     asc->segments          = aspeed_2600_spi2_segments;
+    asc->segment_addr_mask = 0x0ff00ff0;
     asc->flash_window_base = 0x50000000;
     asc->flash_window_size = 0x10000000;
     asc->features          = ASPEED_SMC_FEATURE_DMA |
-- 
2.34.1

This is useful to analyze changes in the U-Boot RAM driver when SDRAM
training is performed.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/misc/aspeed_sdmc.c | 2 ++
 hw/misc/trace-events  | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
         return 0;
     }
 
+    trace_aspeed_sdmc_read(addr, s->regs[addr]);
     return s->regs[addr];
 }
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
         return;
     }
 
+    trace_aspeed_sdmc_write(addr, data);
     asc->write(s, addr, data);
 }
 
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64
 aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
 aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
 
+# aspeed_sdmc.c
+aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
+aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
+
 # bcm2835_property.c
 bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu"
 
-- 
2.34.1

The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:

Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20231025

for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:

hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)

----------------------------------------------------------------
aspeed queue:

* Update of Andrew's email
* Split of AspeedSoCState per 2400/2600/10x0

----------------------------------------------------------------
Andrew Jeffery (1):
      MAINTAINERS: aspeed: Update Andrew's email address

Philippe Mathieu-Daudé (11):
      hw/arm/aspeed: Extract code common to all boards to a common file
      hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
      hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
      hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
      hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
      hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
      hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
      hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
      hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
      hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
      hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState

MAINTAINERS                               |   2 +-
 include/hw/arm/aspeed_soc.h               |  35 +++++-
 hw/arm/aspeed.c                           | 101 +++++++--------
 hw/arm/aspeed_ast10x0.c                   |  53 ++++----
 hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------
 hw/arm/aspeed_ast2600.c                   |  75 ++++++------
 hw/arm/aspeed_soc_common.c                | 154 +++++++++++++++++++++++
 hw/arm/fby35.c                            |  27 ++--
 hw/arm/meson.build                        |   3 +-
 9 files changed, 363 insertions(+), 284 deletions(-)
 rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)
 create mode 100644 hw/arm/aspeed_soc_common.c

From: Philippe Mathieu-Daudé <philmd@linaro.org>

aspeed_soc.c contains definitions specific to the AST2400
and AST2500 SoCs, but also some definitions for other AST
SoCs: move them to a common file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_soc.c        |  96 -------------------------------
 hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
 hw/arm/meson.build         |   1 +
 3 files changed, 115 insertions(+), 96 deletions(-)
 create mode 100644 hw/arm/aspeed_soc_common.c

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)
 };
 
 type_init(aspeed_soc_register_types);
-
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-{
-    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-}
-
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    SerialMM *smm;
-
-    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
-        smm = &s->uart[i];
-
-        /* Chardev property is set by the machine. */
-        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
-        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
-        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
-        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
-        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
-            return false;
-        }
-
-        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
-        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
-    }
-
-    return true;
-}
-
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    int i = dev - ASPEED_DEV_UART1;
-
-    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
-    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
-}
-
-/*
- * SDMC should be realized first to get correct RAM size and max size
- * values
- */
-bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    ram_addr_t ram_size, max_ram_size;
-
-    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
-                                        &error_abort);
-    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
-                                            &error_abort);
-
-    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
-                       max_ram_size);
-    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
-
-    /*
-     * Add a memory region beyond the RAM region to let firmwares scan
-     * the address space with load/store and guess how much RAM the
-     * SoC has.
-     */
-    if (ram_size < max_ram_size) {
-        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-
-        qdev_prop_set_string(dev, "name", "ram-empty");
-        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
-        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
-            return false;
-        }
-
-        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
-                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
-    }
-
-    memory_region_add_subregion(s->memory,
-                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
-    return true;
-}
-
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
-{
-    memory_region_add_subregion(s->memory, addr,
-                                sysbus_mmio_get_region(dev, n));
-}
-
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
-                                   const char *name, hwaddr addr, uint64_t size)
-{
-    qdev_prop_set_string(DEVICE(dev), "name", name);
-    qdev_prop_set_uint64(DEVICE(dev), "size", size);
-    sysbus_realize(dev, &error_abort);
-
-    memory_region_add_subregion_overlap(s->memory, addr,
-                                        sysbus_mmio_get_region(dev, 0), -1000);
-}
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED SoC family
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ * Jeremy Kerr <jk@ozlabs.org>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/char/serial.h"
+
+
+qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
+{
+    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
+}
+
+bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    SerialMM *smm;
+
+    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+        smm = &s->uart[i];
+
+        /* Chardev property is set by the machine. */
+        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
+        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
+        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
+        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
+        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
+            return false;
+        }
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
+        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
+    }
+
+    return true;
+}
+
+void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    int i = dev - ASPEED_DEV_UART1;
+
+    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
+    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+}
+
+/*
+ * SDMC should be realized first to get correct RAM size and max size
+ * values
+ */
+bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    ram_addr_t ram_size, max_ram_size;
+
+    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
+                                        &error_abort);
+    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
+                                            &error_abort);
+
+    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
+                       max_ram_size);
+    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
+
+    /*
+     * Add a memory region beyond the RAM region to let firmwares scan
+     * the address space with load/store and guess how much RAM the
+     * SoC has.
+     */
+    if (ram_size < max_ram_size) {
+        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
+
+        qdev_prop_set_string(dev, "name", "ram-empty");
+        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
+        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
+            return false;
+        }
+
+        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
+                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
+    }
+
+    memory_region_add_subregion(s->memory,
+                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
+    return true;
+}
+
+void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
+{
+    memory_region_add_subregion(s->memory, addr,
+                                sysbus_mmio_get_region(dev, n));
+}
+
+void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+                                   const char *name, hwaddr addr, uint64_t size)
+{
+    qdev_prop_set_string(DEVICE(dev), "name", name);
+    qdev_prop_set_uint64(DEVICE(dev), "size", size);
+    sysbus_realize(dev, &error_abort);
+
+    memory_region_add_subregion_overlap(s->memory, addr,
+                                        sysbus_mmio_get_region(dev, 0), -1000);
+}
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
 arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_soc.c',
   'aspeed.c',
+  'aspeed_soc_common.c',
   'aspeed_ast2600.c',
   'aspeed_ast10x0.c',
   'aspeed_eeprom.c',
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
 }
 
-static void aspeed_soc_init(Object *obj)
+static void aspeed_ast2400_soc_init(Object *obj)
 {
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 static const TypeInfo aspeed_soc_ast2400_type_info = {
     .name           = "ast2400-a1",
     .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_soc_init,
+    .instance_init  = aspeed_ast2400_soc_init,
     .instance_size  = sizeof(AspeedSoCState),
     .class_init     = aspeed_soc_ast2400_class_init,
 };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 static const TypeInfo aspeed_soc_ast2500_type_info = {
     .name           = "ast2500-a1",
     .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_soc_init,
+    .instance_init  = aspeed_ast2400_soc_init,
     .instance_size  = sizeof(AspeedSoCState),
     .class_init     = aspeed_soc_ast2500_class_init,
 };
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Keep aspeed_soc_class_init() generic, set the realize handler
to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
 }
 
-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
 {
     int i;
     AspeedSoCState *s = ASPEED_SOC(dev);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
-    dc->realize = aspeed_soc_realize;
-    /* Reason: Uses serial_hds and nd_table in realize() directly */
-    dc->user_creatable = false;
     device_class_set_props(dc, aspeed_soc_properties);
 }
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = {
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = aspeed_ast2400_soc_realize;
+    /* Reason: Uses serial_hds and nd_table in realize() directly */
+    dc->user_creatable = false;
 
     sc->name         = "ast2400-a1";
     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = aspeed_ast2400_soc_realize;
+    /* Reason: Uses serial_hds and nd_table in realize() directly */
+    dc->user_creatable = false;
 
     sc->name         = "ast2500-a1";
     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

We want to derivate the big AspeedSoCState object in some more
SoC-specific ones. Since the object size will vary, allocate it
dynamically.

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
     MachineState parent_obj;
     /* Public */
 
-    AspeedSoCState soc;
+    AspeedSoCState *soc;
     MemoryRegion boot_rom;
     bool mmio_exec;
     uint32_t uart_chosen;
@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
                                     uint64_t rom_size)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
                            &error_abort);
@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 {
     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
-    AspeedSoCState *s = &bmc->soc;
+    AspeedSoCState *s = bmc->soc;
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
     int i;
     NICInfo *nd = &nd_table[0];
 
-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-
-    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+    object_unref(OBJECT(bmc->soc));
+    sc = ASPEED_SOC_GET_CLASS(bmc->soc);
 
     /*
      * This will error out if the RAM size is not supported by the
      * memory controller of the SoC.
      */
-    object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
+    object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
                              &error_fatal);
 
     for (i = 0; i < sc->macs_num; i++) {
         if ((amc->macs_mask & (1 << i)) && nd->used) {
             qemu_check_nic_model(nd, TYPE_FTGMAC100);
-            qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
+            qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
             nd++;
         }
     }
 
-    object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
+    object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
                             &error_abort);
-    object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
+    object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
                             &error_abort);
-    object_property_set_link(OBJECT(&bmc->soc), "memory",
+    object_property_set_link(OBJECT(bmc->soc), "memory",
                              OBJECT(get_system_memory()), &error_abort);
-    object_property_set_link(OBJECT(&bmc->soc), "dram",
+    object_property_set_link(OBJECT(bmc->soc), "dram",
                              OBJECT(machine->ram), &error_abort);
     if (machine->kernel_filename) {
         /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
          * that runs to unlock the SCU. In this case set the default to
          * be unlocked as the kernel expects
          */
-        object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
+        object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
                                 ASPEED_SCU_PROT_KEY, &error_abort);
     }
     connect_serial_hds_to_uarts(bmc);
-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 
     if (defaults_enabled()) {
-        aspeed_board_init_flashes(&bmc->soc.fmc,
+        aspeed_board_init_flashes(&bmc->soc->fmc,
                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                               amc->num_cs, 0);
-        aspeed_board_init_flashes(&bmc->soc.spi[0],
+        aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               1, amc->num_cs);
     }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
         amc->i2c_init(bmc);
     }
 
-    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
-        sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
+    for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
+        sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
                            drive_get(IF_SD, 0, i));
     }
 
-    if (bmc->soc.emmc.num_slots) {
-        sdhci_attach_drive(&bmc->soc.emmc.slots[0],
-                           drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
+    if (bmc->soc->emmc.num_slots) {
+        sdhci_attach_drive(&bmc->soc->emmc.slots[0],
+                           drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
     }
 
     if (!bmc->mmio_exec) {
-        DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
+        DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
         BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
 
         if (fmc0) {
-            uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
+            uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
             aspeed_install_boot_rom(bmc, fmc0, rom_size);
         }
     }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
 
 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     DeviceState *dev;
     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /*
      * The quanta-q71l platform expects tmp75s which are compatible with
@@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 
 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 
 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
      * good enough */
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 
 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* bus 2 : */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
     };
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
     DeviceState *dev;
     LEDState *led;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     DeviceState *dev;
 
     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *i2c_mux;
 
     /* The at24c256 */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *i2c_mux;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 
 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[144] = {};
 
     for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[13] = {};
     for (int i = 0; i < 13; i++) {
         if ((i == 8) || (i == 11)) {
@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void fby35_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[16];
 
     for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
 
 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 }
 
 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *therm_mux, *cpuvr_mux;
 
     /* Create the generic DC-SCM hardware */
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
 static void fby35_reset(MachineState *state, ShutdownCause reason)
 {
     AspeedMachineState *bmc = ASPEED_MACHINE(state);
-    AspeedGPIOState *gpio = &bmc->soc.gpio;
+    AspeedGPIOState *gpio = &bmc->soc->gpio;
 
     qemu_devices_reset(reason);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
     clock_set_hz(sysclk, SYSCLK_FRQ);
 
-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-    qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+    object_unref(OBJECT(bmc->soc));
+    qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
 
-    object_property_set_link(OBJECT(&bmc->soc), "memory",
+    object_property_set_link(OBJECT(bmc->soc), "memory",
                              OBJECT(get_system_memory()), &error_abort);
     connect_serial_hds_to_uarts(bmc);
-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&bmc->soc.fmc,
+    aspeed_board_init_flashes(&bmc->soc->fmc,
                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                               amc->num_cs,
                               0);
 
-    aspeed_board_init_flashes(&bmc->soc.spi[0],
+    aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               amc->num_cs, amc->num_cs);
 
-    aspeed_board_init_flashes(&bmc->soc.spi[1],
+    aspeed_board_init_flashes(&bmc->soc->spi[1],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               amc->num_cs, (amc->num_cs * 2));
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
 
 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* U10 24C08 connects to SDA/SCL Group 1 by default */
     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++++
 hw/arm/aspeed_ast10x0.c     | 26 +++++++++++++-------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed10x0SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
+
 struct AspeedSoCClass {
     DeviceClass parent_class;
 
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
     sc->get_irq = aspeed_soc_ast1030_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast1030_type_info = {
-    .name          = "ast1030-a1",
-    .parent        = TYPE_ASPEED_SOC,
-    .instance_size = sizeof(AspeedSoCState),
-    .instance_init = aspeed_soc_ast1030_init,
-    .class_init    = aspeed_soc_ast1030_class_init,
-    .class_size    = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast10x0_types[] = {
+    {
+        .name           = TYPE_ASPEED10X0_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_size  = sizeof(Aspeed10x0SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast1030-a1",
+        .parent         = TYPE_ASPEED10X0_SOC,
+        .instance_init  = aspeed_soc_ast1030_init,
+        .class_init     = aspeed_soc_ast1030_class_init,
+    },
 };
 
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_ast1030_type_info);
-}
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast10x0_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++++
 hw/arm/aspeed_ast2600.c     | 26 +++++++++++++-------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed2600SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
+
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
 };
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2600_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2600_type_info = {
-    .name           = "ast2600-a3",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_size  = sizeof(AspeedSoCState),
-    .instance_init  = aspeed_soc_ast2600_init,
-    .class_init     = aspeed_soc_ast2600_class_init,
-    .class_size     = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast2600_types[] = {
+    {
+        .name           = TYPE_ASPEED2600_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_size  = sizeof(Aspeed2600SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast2600-a3",
+        .parent         = TYPE_ASPEED2600_SOC,
+        .instance_init  = aspeed_soc_ast2600_init,
+        .class_init     = aspeed_soc_ast2600_class_init,
+    },
 };
 
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_ast2600_type_info);
-};
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast2600_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

TYPE_ASPEED_SOC is common to various Aspeed SoCs,
define it in aspeed_soc_common.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++
 hw/arm/aspeed_soc.c         | 61 +++++++++++--------------------------
 hw/arm/aspeed_soc_common.c  | 29 ++++++++++++++++++
 3 files changed, 53 insertions(+), 44 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed2400SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
+
 struct Aspeed2600SoCState {
     AspeedSoCState parent;
 };
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
                        aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
 }
-static Property aspeed_soc_properties[] = {
-    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(oc);
-
-    device_class_set_props(dc, aspeed_soc_properties);
-}
-
-static const TypeInfo aspeed_soc_type_info = {
-    .name           = TYPE_ASPEED_SOC,
-    .parent         = TYPE_DEVICE,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_size     = sizeof(AspeedSoCClass),
-    .class_init     = aspeed_soc_class_init,
-    .abstract       = true,
-};
 
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2400_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2400_type_info = {
-    .name           = "ast2400-a1",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_ast2400_soc_init,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_init     = aspeed_soc_ast2400_class_init,
-};
-
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2400_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2500_type_info = {
-    .name           = "ast2500-a1",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_ast2400_soc_init,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_init     = aspeed_soc_ast2500_class_init,
-};
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_type_info);
-    type_register_static(&aspeed_soc_ast2400_type_info);
-    type_register_static(&aspeed_soc_ast2500_type_info);
+static const TypeInfo aspeed_soc_ast2400_types[] = {
+    {
+        .name           = TYPE_ASPEED2400_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_init  = aspeed_ast2400_soc_init,
+        .instance_size  = sizeof(Aspeed2400SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast2400-a1",
+        .parent         = TYPE_ASPEED2400_SOC,
+        .class_init     = aspeed_soc_ast2400_class_init,
+    }, {
+        .name           = "ast2500-a1",
+        .parent         = TYPE_ASPEED2400_SOC,
+        .class_init     = aspeed_soc_ast2500_class_init,
+    },
 };
 
-type_init(aspeed_soc_register_types);
+DEFINE_TYPES(aspeed_soc_ast2400_types)
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "hw/qdev-properties.h"
 #include "hw/misc/unimp.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/char/serial.h"
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
     memory_region_add_subregion_overlap(s->memory, addr,
                                         sysbus_mmio_get_region(dev, 0), -1000);
 }
+
+static Property aspeed_soc_properties[] = {
+    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    device_class_set_props(dc, aspeed_soc_properties);
+}
+
+static const TypeInfo aspeed_soc_types[] = {
+    {
+        .name           = TYPE_ASPEED_SOC,
+        .parent         = TYPE_DEVICE,
+        .instance_size  = sizeof(AspeedSoCState),
+        .class_size     = sizeof(AspeedSoCClass),
+        .class_init     = aspeed_soc_class_init,
+        .abstract       = true,
+    },
+};
+
+DEFINE_TYPES(aspeed_soc_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
                                         sysbus_mmio_get_region(dev, 0), -1000);
 }
 
+static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+{
+    AspeedSoCState *s = ASPEED_SOC(dev);
+
+    if (!s->memory) {
+        error_setg(errp, "'memory' link is not set");
+        return;
+    }
+}
+
 static Property aspeed_soc_properties[] = {
     DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
                      MemoryRegion *),
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
+    dc->realize = aspeed_soc_realize;
     device_class_set_props(dc, aspeed_soc_properties);
 }
 
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-M core is specific to the Aspeed 10x0 series,
remove it from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  5 ++---
 hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
 hw/arm/fby35.c              | 13 ++++++++-----
 3 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #define ASPEED_JTAG_NUM  2
 
 struct AspeedSoCState {
-    /*< private >*/
     DeviceState parent;
 
-    /*< public >*/
     ARMCPU cpu[ASPEED_CPUS_NUM];
     A15MPPrivState     a7mpcore;
-    ARMv7MState        armv7m;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
+
+    ARMv7MState armv7m;
 };
 
 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
 
 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 
-    return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
 }
 
 static void aspeed_soc_ast1030_init(Object *obj)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     char socname[8];
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
         g_assert_not_reached();
     }
 
-    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
 
     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
 
 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
     AspeedSoCState *s = ASPEED_SOC(dev_soc);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     DeviceState *armv7m;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
                                   0x40000);
 
     /* AST1030 CPU Core */
-    armv7m = DEVICE(&s->armv7m);
+    armv7m = DEVICE(&a->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 256);
     qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
-    object_property_set_link(OBJECT(&s->armv7m), "memory",
+    object_property_set_link(OBJECT(&a->armv7m), "memory",
                              OBJECT(s->memory), &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
 
     /* Internal SRAM */
     sram_name = g_strdup_printf("aspeed.sram.%d",
-                                CPU(s->armv7m.cpu)->cpu_index);
+                                CPU(a->armv7m.cpu)->cpu_index);
     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
     if (err != NULL) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                         sc->irqmap[ASPEED_DEV_I2C] + i);
         /* The AST1030 I2C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                         sc->irqmap[ASPEED_DEV_I3C] + i);
         /* The AST1030 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
      */
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
 
     /* UART */
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
     Clock *bic_sysclk;
 
     AspeedSoCState bmc;
-    AspeedSoCState bic;
+    Aspeed10x0SoCState bic;
 
     bool mmio_exec;
 };
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
 
 static void fby35_bic_init(Fby35State *s)
 {
+    AspeedSoCState *soc;
+
     s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
     clock_set_hz(s->bic_sysclk, 200000000ULL);
 
     object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
+    soc = ASPEED_SOC(&s->bic);
 
     memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
                        UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)
     qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
     object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                              &error_abort);
-    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
     qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
-    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
-    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
+    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
+    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
+    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
 }
 
 static void fby35_init(MachineState *machine)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-A cluster is specific to the Aspeed 2600 series,
remove it from the common AspeedSoCState.

The ARM cores belong to the MP cluster, but the array
is currently used by TYPE_ASPEED2600_SOC. We'll clean
that soon, but for now keep it in Aspeed2600SoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  4 ++-
 hw/arm/aspeed_ast2600.c     | 49 ++++++++++++++++++++-----------------
 hw/arm/fby35.c              | 14 ++++++-----
 3 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
     DeviceState parent;
 
     ARMCPU cpu[ASPEED_CPUS_NUM];
-    A15MPPrivState     a7mpcore;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
 
 struct Aspeed2600SoCState {
     AspeedSoCState parent;
+
+    A15MPPrivState a7mpcore;
+    ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
 };
 
 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
 
 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
 {
+    Aspeed2600SoCState *a = ASPEED2600_SOC(s);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 
-    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
 }
 
 static void aspeed_soc_ast2600_init(Object *obj)
 {
+    Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     }
 
     for (i = 0; i < sc->num_cpus; i++) {
-        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
     }
 
     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                               "hw-prot-key");
 
-    object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
                             TYPE_A15MPCORE_PRIV);
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu)
 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
 {
     int i;
+    Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
     AspeedSoCState *s = ASPEED_SOC(dev);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     /* CPU */
     for (i = 0; i < sc->num_cpus; i++) {
         if (sc->num_cpus > 1) {
-            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+            object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
                                     ASPEED_A7MPCORE_ADDR, &error_abort);
         }
-        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
+        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                 aspeed_calc_affinity(i), &error_abort);
 
-        object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
+        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                 &error_abort);
-        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+        object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
                                 &error_abort);
-        object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
+        object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
                                 &error_abort);
-        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
+        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                  OBJECT(s->memory), &error_abort);
 
-        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
             return;
         }
     }
 
     /* A7MPCORE */
-    object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
+    object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
+    object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
                             ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
                             &error_abort);
 
-    sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
+    sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
 
     for (i = 0; i < sc->num_cpus; i++) {
-        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
-        DeviceState  *d   = DEVICE(&s->cpu[i]);
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
+        DeviceState  *d   = DEVICE(&a->cpu[i]);
 
         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
         sysbus_connect_irq(sbd, i, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
 
     /* SRAM */
-    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
     if (err) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                sc->irqmap[ASPEED_DEV_I2C] + i);
         /* The AST2600 I2C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      * offset 0.
      */
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
 
     /* HACE */
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                sc->irqmap[ASPEED_DEV_I3C] + i);
         /* The AST2600 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
     MemoryRegion bic_memory;
     Clock *bic_sysclk;
 
-    AspeedSoCState bmc;
+    Aspeed2600SoCState bmc;
     Aspeed10x0SoCState bic;
 
     bool mmio_exec;
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
 
 static void fby35_bmc_init(Fby35State *s)
 {
+    AspeedSoCState *soc;
+
     object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
+    soc = ASPEED_SOC(&s->bmc);
 
     memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
                        UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
                             &error_abort);
     object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
                             &error_abort);
-    aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
     qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
+    aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
 
     /* Install first FMC flash content as a boot rom. */
     if (!s->mmio_exec) {
         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
 
         if (mtd0) {
-            AspeedSoCState *bmc = &s->bmc;
-            uint64_t rom_size = memory_region_size(&bmc->spi_boot);
+            uint64_t rom_size = memory_region_size(&soc->spi_boot);
 
             memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
                                    rom_size, &error_abort);
-            memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
+            memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
                                                 &s->bmc_boot_rom, 1);
 
             fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The ARM array and VIC peripheral are only used by the
2400 series, remove them from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h               |  5 +++--
 hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
 hw/arm/meson.build                        |  2 +-
 3 files changed, 19 insertions(+), 15 deletions(-)
 rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)