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  3. [PATCH v6 0/4] s390x: Add partial z15 support and tests
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[PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15

David Miller posted 4 patches 3 years, 11 months ago
Maintainers: Thomas Huth <thuth@redhat.com>, Cornelia Huck <cohuck@redhat.com>, David Hildenbrand <david@redhat.com>, Christian Borntraeger <borntraeger@linux.ibm.com>, Eric Farman <farman@linux.ibm.com>, Halil Pasic <pasic@linux.ibm.com>, Richard Henderson <richard.henderson@linaro.org>
There is a newer version of this series
[PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15
Posted by David Miller 3 years, 11 months ago 
Signed-off-by: David Miller <dmiller423@gmail.com>
---
 tests/tcg/s390x/mie3-compl.c | 21 +++++++++++----------
 tests/tcg/s390x/mie3-mvcrl.c |  2 +-
 tests/tcg/s390x/mie3-sel.c   |  6 +++---
 3 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
index 98281ee683..31820e4a2a 100644
--- a/tests/tcg/s390x/mie3-compl.c
+++ b/tests/tcg/s390x/mie3-compl.c
@@ -14,25 +14,26 @@
 #define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \
 { uint64_t res = 0; F_PRO; ASM; return res; }
 
+
 /* AND WITH COMPLEMENT */
-FbinOp(_ncrk,  asm("ncrk  %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_ncgrk, asm("ncgrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_ncrk,  asm(".insn rrf, 0xB9F50000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_ncgrk, asm(".insn rrf, 0xB9E50000, %%r0, %%r3, %%r2, 0\n" F_EPI))
 
 /* NAND */
-FbinOp(_nnrk,  asm("nnrk  %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_nngrk, asm("nngrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nnrk,  asm(".insn rrf, 0xB9740000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_nngrk, asm(".insn rrf, 0xB9640000, %%r0, %%r3, %%r2, 0\n" F_EPI))
 
 /* NOT XOR */
-FbinOp(_nxrk,  asm("nxrk  %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_nxgrk, asm("nxgrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nxrk,  asm(".insn rrf, 0xB9770000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_nxgrk, asm(".insn rrf, 0xB9670000, %%r0, %%r3, %%r2, 0\n" F_EPI))
 
 /* NOR */
-FbinOp(_nork,  asm("nork  %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_nogrk, asm("nogrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nork,  asm(".insn rrf, 0xB9760000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_nogrk, asm(".insn rrf, 0xB9660000, %%r0, %%r3, %%r2, 0\n" F_EPI))
 
 /* OR WITH COMPLEMENT */
-FbinOp(_ocrk,  asm("ocrk  %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_ocgrk, asm("ocgrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_ocrk,  asm(".insn rrf, 0xB9750000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_ocgrk, asm(".insn rrf, 0xB9650000, %%r0, %%r3, %%r2, 0\n" F_EPI))
 
 
 int main(int argc, char *argv[])
diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3-mvcrl.c
index 81cf3ad702..f0be83b197 100644
--- a/tests/tcg/s390x/mie3-mvcrl.c
+++ b/tests/tcg/s390x/mie3-mvcrl.c
@@ -6,7 +6,7 @@ static inline void mvcrl_8(const char *dst, const char *src)
 {
     asm volatile (
     "llill %%r0, 8\n"
-    "mvcrl 0(%[dst]), 0(%[src])\n"
+    ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])"
     : : [dst] "d" (dst), [src] "d" (src)
     : "memory");
 }
diff --git a/tests/tcg/s390x/mie3-sel.c b/tests/tcg/s390x/mie3-sel.c
index d6b7b0933b..32d434b01a 100644
--- a/tests/tcg/s390x/mie3-sel.c
+++ b/tests/tcg/s390x/mie3-sel.c
@@ -19,9 +19,9 @@
 { uint64_t res = 0; F_PRO ; ASM ; return res; }
 
 
-Fi3 (_selre,     asm("selre    %%r0, %%r3, %%r2\n" F_EPI))
-Fi3 (_selgrz,    asm("selgrz   %%r0, %%r3, %%r2\n" F_EPI))
-Fi3 (_selfhrnz,  asm("selfhrnz %%r0, %%r3, %%r2\n" F_EPI))
+Fi3 (_selre,     asm(".insn rrf, 0xB9F00000, %%r0, %%r3, %%r2, 8\n" F_EPI))
+Fi3 (_selgrz,    asm(".insn rrf, 0xB9E30000, %%r0, %%r3, %%r2, 8\n" F_EPI))
+Fi3 (_selfhrnz,  asm(".insn rrf, 0xB9C00000, %%r0, %%r3, %%r2, 7\n" F_EPI))
 
 
 int main(int argc, char *argv[])
-- 
2.32.0
Re: [PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15
Posted by Thomas Huth 3 years, 11 months ago 
On 18/02/2022 00.17, David Miller wrote:
> Signed-off-by: David Miller <dmiller423@gmail.com>
> ---
>   tests/tcg/s390x/mie3-compl.c | 21 +++++++++++----------
>   tests/tcg/s390x/mie3-mvcrl.c |  2 +-
>   tests/tcg/s390x/mie3-sel.c   |  6 +++---
>   3 files changed, 15 insertions(+), 14 deletions(-)
> 
> diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
> index 98281ee683..31820e4a2a 100644
> --- a/tests/tcg/s390x/mie3-compl.c
> +++ b/tests/tcg/s390x/mie3-compl.c
> @@ -14,25 +14,26 @@
>   #define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \
>   { uint64_t res = 0; F_PRO; ASM; return res; }
>   
> +
>   /* AND WITH COMPLEMENT */
> -FbinOp(_ncrk,  asm("ncrk  %%r0, %%r3, %%r2\n" F_EPI))
> -FbinOp(_ncgrk, asm("ncgrk %%r0, %%r3, %%r2\n" F_EPI))
> +FbinOp(_ncrk,  asm(".insn rrf, 0xB9F50000, %%r0, %%r3, %%r2, 0\n" F_EPI))
> +FbinOp(_ncgrk, asm(".insn rrf, 0xB9E50000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>   
>   /* NAND */
> -FbinOp(_nnrk,  asm("nnrk  %%r0, %%r3, %%r2\n" F_EPI))
> -FbinOp(_nngrk, asm("nngrk %%r0, %%r3, %%r2\n" F_EPI))
> +FbinOp(_nnrk,  asm(".insn rrf, 0xB9740000, %%r0, %%r3, %%r2, 0\n" F_EPI))
> +FbinOp(_nngrk, asm(".insn rrf, 0xB9640000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>   
>   /* NOT XOR */
> -FbinOp(_nxrk,  asm("nxrk  %%r0, %%r3, %%r2\n" F_EPI))
> -FbinOp(_nxgrk, asm("nxgrk %%r0, %%r3, %%r2\n" F_EPI))
> +FbinOp(_nxrk,  asm(".insn rrf, 0xB9770000, %%r0, %%r3, %%r2, 0\n" F_EPI))
> +FbinOp(_nxgrk, asm(".insn rrf, 0xB9670000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>   
>   /* NOR */
> -FbinOp(_nork,  asm("nork  %%r0, %%r3, %%r2\n" F_EPI))
> -FbinOp(_nogrk, asm("nogrk %%r0, %%r3, %%r2\n" F_EPI))
> +FbinOp(_nork,  asm(".insn rrf, 0xB9760000, %%r0, %%r3, %%r2, 0\n" F_EPI))
> +FbinOp(_nogrk, asm(".insn rrf, 0xB9660000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>   
>   /* OR WITH COMPLEMENT */
> -FbinOp(_ocrk,  asm("ocrk  %%r0, %%r3, %%r2\n" F_EPI))
> -FbinOp(_ocgrk, asm("ocgrk %%r0, %%r3, %%r2\n" F_EPI))
> +FbinOp(_ocrk,  asm(".insn rrf, 0xB9750000, %%r0, %%r3, %%r2, 0\n" F_EPI))
> +FbinOp(_ocgrk, asm(".insn rrf, 0xB9650000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>   
>   
>   int main(int argc, char *argv[])
> diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3-mvcrl.c
> index 81cf3ad702..f0be83b197 100644
> --- a/tests/tcg/s390x/mie3-mvcrl.c
> +++ b/tests/tcg/s390x/mie3-mvcrl.c
> @@ -6,7 +6,7 @@ static inline void mvcrl_8(const char *dst, const char *src)
>   {
>       asm volatile (
>       "llill %%r0, 8\n"
> -    "mvcrl 0(%[dst]), 0(%[src])\n"
> +    ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])"
>       : : [dst] "d" (dst), [src] "d" (src)
>       : "memory");
>   }
> diff --git a/tests/tcg/s390x/mie3-sel.c b/tests/tcg/s390x/mie3-sel.c
> index d6b7b0933b..32d434b01a 100644
> --- a/tests/tcg/s390x/mie3-sel.c
> +++ b/tests/tcg/s390x/mie3-sel.c
> @@ -19,9 +19,9 @@
>   { uint64_t res = 0; F_PRO ; ASM ; return res; }
>   
>   
> -Fi3 (_selre,     asm("selre    %%r0, %%r3, %%r2\n" F_EPI))
> -Fi3 (_selgrz,    asm("selgrz   %%r0, %%r3, %%r2\n" F_EPI))
> -Fi3 (_selfhrnz,  asm("selfhrnz %%r0, %%r3, %%r2\n" F_EPI))
> +Fi3 (_selre,     asm(".insn rrf, 0xB9F00000, %%r0, %%r3, %%r2, 8\n" F_EPI))
> +Fi3 (_selgrz,    asm(".insn rrf, 0xB9E30000, %%r0, %%r3, %%r2, 8\n" F_EPI))
> +Fi3 (_selfhrnz,  asm(".insn rrf, 0xB9C00000, %%r0, %%r3, %%r2, 7\n" F_EPI))
>   
>   
>   int main(int argc, char *argv[])

Reviewed-by: Thomas Huth <thuth@redhat.com>

... maybe best to squash this into the previous patch, though (I can do that 
when picking up the patch if you agree - no need to resend for this).
Re: [PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15
Posted by David Hildenbrand 3 years, 11 months ago 
On 23.02.22 11:44, Thomas Huth wrote:
> On 18/02/2022 00.17, David Miller wrote:
>> Signed-off-by: David Miller <dmiller423@gmail.com>
>> ---
>>   tests/tcg/s390x/mie3-compl.c | 21 +++++++++++----------
>>   tests/tcg/s390x/mie3-mvcrl.c |  2 +-
>>   tests/tcg/s390x/mie3-sel.c   |  6 +++---
>>   3 files changed, 15 insertions(+), 14 deletions(-)
>>
>> diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
>> index 98281ee683..31820e4a2a 100644
>> --- a/tests/tcg/s390x/mie3-compl.c
>> +++ b/tests/tcg/s390x/mie3-compl.c
>> @@ -14,25 +14,26 @@
>>   #define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \
>>   { uint64_t res = 0; F_PRO; ASM; return res; }
>>   
>> +
>>   /* AND WITH COMPLEMENT */
>> -FbinOp(_ncrk,  asm("ncrk  %%r0, %%r3, %%r2\n" F_EPI))
>> -FbinOp(_ncgrk, asm("ncgrk %%r0, %%r3, %%r2\n" F_EPI))
>> +FbinOp(_ncrk,  asm(".insn rrf, 0xB9F50000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>> +FbinOp(_ncgrk, asm(".insn rrf, 0xB9E50000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>>   
>>   /* NAND */
>> -FbinOp(_nnrk,  asm("nnrk  %%r0, %%r3, %%r2\n" F_EPI))
>> -FbinOp(_nngrk, asm("nngrk %%r0, %%r3, %%r2\n" F_EPI))
>> +FbinOp(_nnrk,  asm(".insn rrf, 0xB9740000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>> +FbinOp(_nngrk, asm(".insn rrf, 0xB9640000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>>   
>>   /* NOT XOR */
>> -FbinOp(_nxrk,  asm("nxrk  %%r0, %%r3, %%r2\n" F_EPI))
>> -FbinOp(_nxgrk, asm("nxgrk %%r0, %%r3, %%r2\n" F_EPI))
>> +FbinOp(_nxrk,  asm(".insn rrf, 0xB9770000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>> +FbinOp(_nxgrk, asm(".insn rrf, 0xB9670000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>>   
>>   /* NOR */
>> -FbinOp(_nork,  asm("nork  %%r0, %%r3, %%r2\n" F_EPI))
>> -FbinOp(_nogrk, asm("nogrk %%r0, %%r3, %%r2\n" F_EPI))
>> +FbinOp(_nork,  asm(".insn rrf, 0xB9760000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>> +FbinOp(_nogrk, asm(".insn rrf, 0xB9660000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>>   
>>   /* OR WITH COMPLEMENT */
>> -FbinOp(_ocrk,  asm("ocrk  %%r0, %%r3, %%r2\n" F_EPI))
>> -FbinOp(_ocgrk, asm("ocgrk %%r0, %%r3, %%r2\n" F_EPI))
>> +FbinOp(_ocrk,  asm(".insn rrf, 0xB9750000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>> +FbinOp(_ocgrk, asm(".insn rrf, 0xB9650000, %%r0, %%r3, %%r2, 0\n" F_EPI))
>>   
>>   
>>   int main(int argc, char *argv[])
>> diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3-mvcrl.c
>> index 81cf3ad702..f0be83b197 100644
>> --- a/tests/tcg/s390x/mie3-mvcrl.c
>> +++ b/tests/tcg/s390x/mie3-mvcrl.c
>> @@ -6,7 +6,7 @@ static inline void mvcrl_8(const char *dst, const char *src)
>>   {
>>       asm volatile (
>>       "llill %%r0, 8\n"
>> -    "mvcrl 0(%[dst]), 0(%[src])\n"
>> +    ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])"
>>       : : [dst] "d" (dst), [src] "d" (src)
>>       : "memory");
>>   }
>> diff --git a/tests/tcg/s390x/mie3-sel.c b/tests/tcg/s390x/mie3-sel.c
>> index d6b7b0933b..32d434b01a 100644
>> --- a/tests/tcg/s390x/mie3-sel.c
>> +++ b/tests/tcg/s390x/mie3-sel.c
>> @@ -19,9 +19,9 @@
>>   { uint64_t res = 0; F_PRO ; ASM ; return res; }
>>   
>>   
>> -Fi3 (_selre,     asm("selre    %%r0, %%r3, %%r2\n" F_EPI))
>> -Fi3 (_selgrz,    asm("selgrz   %%r0, %%r3, %%r2\n" F_EPI))
>> -Fi3 (_selfhrnz,  asm("selfhrnz %%r0, %%r3, %%r2\n" F_EPI))
>> +Fi3 (_selre,     asm(".insn rrf, 0xB9F00000, %%r0, %%r3, %%r2, 8\n" F_EPI))
>> +Fi3 (_selgrz,    asm(".insn rrf, 0xB9E30000, %%r0, %%r3, %%r2, 8\n" F_EPI))
>> +Fi3 (_selfhrnz,  asm(".insn rrf, 0xB9C00000, %%r0, %%r3, %%r2, 7\n" F_EPI))
>>   
>>   
>>   int main(int argc, char *argv[])
> 
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> 
> ... maybe best to squash this into the previous patch, though (I can do that 
> when picking up the patch if you agree - no need to resend for this).
> 

Do we need this with my debian11 container change?

-- 
Thanks,

David / dhildenb
Re: [PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15
Posted by Thomas Huth 3 years, 11 months ago 
On 23/02/2022 11.54, David Hildenbrand wrote:
> On 23.02.22 11:44, Thomas Huth wrote:
>> On 18/02/2022 00.17, David Miller wrote:
>>> Signed-off-by: David Miller <dmiller423@gmail.com>
>>> ---
>>>    tests/tcg/s390x/mie3-compl.c | 21 +++++++++++----------
>>>    tests/tcg/s390x/mie3-mvcrl.c |  2 +-
>>>    tests/tcg/s390x/mie3-sel.c   |  6 +++---
>>>    3 files changed, 15 insertions(+), 14 deletions(-)
...
>>
>> Reviewed-by: Thomas Huth <thuth@redhat.com>
>>
>> ... maybe best to squash this into the previous patch, though (I can do that
>> when picking up the patch if you agree - no need to resend for this).
>>
> 
> Do we need this with my debian11 container change?

I just tried without, but this breaks on s390x hosts with older compilers, 
where the TCG tests are run without a container:

https://app.travis-ci.com/github/huth/qemu/jobs/560854945#L12875

Since Ubuntu 20.04 is still a supported s390x build system for QEMU, I 
assume it's best if we squash the .insn patch?

  Thomas
Re: [PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15
Posted by David Hildenbrand 3 years, 11 months ago 
On 23.02.22 12:49, Thomas Huth wrote:
> On 23/02/2022 11.54, David Hildenbrand wrote:
>> On 23.02.22 11:44, Thomas Huth wrote:
>>> On 18/02/2022 00.17, David Miller wrote:
>>>> Signed-off-by: David Miller <dmiller423@gmail.com>
>>>> ---
>>>>    tests/tcg/s390x/mie3-compl.c | 21 +++++++++++----------
>>>>    tests/tcg/s390x/mie3-mvcrl.c |  2 +-
>>>>    tests/tcg/s390x/mie3-sel.c   |  6 +++---
>>>>    3 files changed, 15 insertions(+), 14 deletions(-)
> ...
>>>
>>> Reviewed-by: Thomas Huth <thuth@redhat.com>
>>>
>>> ... maybe best to squash this into the previous patch, though (I can do that
>>> when picking up the patch if you agree - no need to resend for this).
>>>
>>
>> Do we need this with my debian11 container change?
> 
> I just tried without, but this breaks on s390x hosts with older compilers, 
> where the TCG tests are run without a container:
> 
> https://app.travis-ci.com/github/huth/qemu/jobs/560854945#L12875
> 
> Since Ubuntu 20.04 is still a supported s390x build system for QEMU, I 
> assume it's best if we squash the .insn patch?

But then, the "-march=z15 -m64" in the previous patch is also unsafe.

-- 
Thanks,

David / dhildenb
Re: [PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15
Posted by Thomas Huth 3 years, 11 months ago 
On 23/02/2022 12.51, David Hildenbrand wrote:
> On 23.02.22 12:49, Thomas Huth wrote:
>> On 23/02/2022 11.54, David Hildenbrand wrote:
>>> On 23.02.22 11:44, Thomas Huth wrote:
>>>> On 18/02/2022 00.17, David Miller wrote:
>>>>> Signed-off-by: David Miller <dmiller423@gmail.com>
>>>>> ---
>>>>>     tests/tcg/s390x/mie3-compl.c | 21 +++++++++++----------
>>>>>     tests/tcg/s390x/mie3-mvcrl.c |  2 +-
>>>>>     tests/tcg/s390x/mie3-sel.c   |  6 +++---
>>>>>     3 files changed, 15 insertions(+), 14 deletions(-)
>> ...
>>>>
>>>> Reviewed-by: Thomas Huth <thuth@redhat.com>
>>>>
>>>> ... maybe best to squash this into the previous patch, though (I can do that
>>>> when picking up the patch if you agree - no need to resend for this).
>>>>
>>>
>>> Do we need this with my debian11 container change?
>>
>> I just tried without, but this breaks on s390x hosts with older compilers,
>> where the TCG tests are run without a container:
>>
>> https://app.travis-ci.com/github/huth/qemu/jobs/560854945#L12875
>>
>> Since Ubuntu 20.04 is still a supported s390x build system for QEMU, I
>> assume it's best if we squash the .insn patch?
> 
> But then, the "-march=z15 -m64" in the previous patch is also unsafe.

Yes, that change has to be dropped, too.

  Thomas

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