The RISC-V base cache management operation ISA extension has been
ratified [1]. This patchset adds support for the defined instructions.

As the exception behavior of these instructions depend on the PMP
configuration, the first patch introduces a new API to probe the access
of an address range with a specified size with optional nonfaulting
behavior.

The Zicbo[m,z,p] patch should be straight-forward and has been reviewed
in previous versions of this patchset.

The series is rebsed on top of github-alistair23/riscv-to-apply.next plus
the Priv v1.12 series from github-atishp04/priv_1_12_support_v3.

[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions

v4:
- Add patch to add probe_access_range_flags() interface
- Rename cbozelen -> cboz_blocksize
- Introduce cbom_blocksize
- Remove RISCV_CPU() calls from trans_*()
- Use probe_access_range_flags() to improve exception behavior

v3:
- Enable by default (like zb*)
- Rename flags Zicbo* -> zicbo* (like zb*)
- Rename ext_zicbo* -> ext_icbo* (like ext_icsr)
- Rename trans_zicbo.c.inc -> trans_rvzicbo.c.inc (like all others)
- Simplify prefetch instruction support to a single comment
- Rebase on top of github-alistair23/riscv-to-apply.next plus the
  Priv v1.12 series from github-atishp04/priv_1_12_support_v3

v2:
- Fix overlapping instruction encoding with LQ instructions
- Drop CSR related changes and rebase on Priv 1.12 patchset

Christoph Muellner (2):
  accel/tcg: Add probe_access_range_flags interface
  target/riscv: Enable Zicbo[m,z,p] instructions

 accel/tcg/cputlb.c                          | 17 +++-
 accel/tcg/user-exec.c                       | 15 +++-
 include/exec/exec-all.h                     | 24 +++++
 target/riscv/cpu.c                          |  4 +
 target/riscv/cpu.h                          |  4 +
 target/riscv/helper.h                       |  5 ++
 target/riscv/insn32.decode                  | 16 +++-
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 57 ++++++++++++
 target/riscv/op_helper.c                    | 97 +++++++++++++++++++++
 target/riscv/translate.c                    |  1 +
 10 files changed, 232 insertions(+), 8 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc

-- 
2.35.1

Hi Christoph,

On Wed, Feb 16, 2022 at 04:48:37PM +0100, Christoph Muellner wrote:
> The RISC-V base cache management operation ISA extension has been
> ratified [1]. This patchset adds support for the defined instructions.
> 
> As the exception behavior of these instructions depend on the PMP
> configuration, the first patch introduces a new API to probe the access
> of an address range with a specified size with optional nonfaulting
> behavior.
> 
> The Zicbo[m,z,p] patch should be straight-forward and has been reviewed
> in previous versions of this patchset.

I have not seen any v5 yet, unless I have missed. Are you planning to
send one?
fwiw, I rebased them on top of v7.2.0 and tested that it works.

-- 
Regards
Sudip

Hi,

FYI I grabbed these patches, rebased using Alistair's riscv-to-apply.next, and I
plan to re-send them as v5 in the next few days (maintaining Christoph's authorship,
of course).

I'll see if I can implement some of the suggestions made in the v4 one year ago as
well. To keep the original patches intact I'll do that in separated patches.


Thanks,


Daniel

On 1/24/23 15:04, Sudip Mukherjee wrote:
> Hi Christoph,
> 
> On Wed, Feb 16, 2022 at 04:48:37PM +0100, Christoph Muellner wrote:
>> The RISC-V base cache management operation ISA extension has been
>> ratified [1]. This patchset adds support for the defined instructions.
>>
>> As the exception behavior of these instructions depend on the PMP
>> configuration, the first patch introduces a new API to probe the access
>> of an address range with a specified size with optional nonfaulting
>> behavior.
>>
>> The Zicbo[m,z,p] patch should be straight-forward and has been reviewed
>> in previous versions of this patchset.
> 
> I have not seen any v5 yet, unless I have missed. Are you planning to
> send one?
> fwiw, I rebased them on top of v7.2.0 and tested that it works.
>