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[PATCH 7/9] target/ppc: Add powerpc_reset_excp_state helper

Nicholas Piggin posted 9 patches 3 years, 11 months ago
Maintainers: David Gibson <david@gibson.dropbear.id.au>, Daniel Henrique Barboza <danielhb413@gmail.com>, BALATON Zoltan <balaton@eik.bme.hu>, Greg Kurz <groug@kaod.org>, "Cédric Le Goater" <clg@kaod.org>
There is a newer version of this series
[PATCH 7/9] target/ppc: Add powerpc_reset_excp_state helper
Posted by Nicholas Piggin 3 years, 11 months ago 
This moves the logic to reset the QEMU exception state into its own
function.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/excp_helper.c | 41 ++++++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6b6ec71bc2..778eb4f3b0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -360,12 +360,20 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr,
 }
 #endif
 
-static void powerpc_set_excp_state(PowerPCCPU *cpu,
-                                          target_ulong vector, target_ulong msr)
+static void powerpc_reset_excp_state(PowerPCCPU *cpu)
 {
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
 
+    /* Reset exception state */
+    cs->exception_index = POWERPC_EXCP_NONE;
+    env->error_code = 0;
+}
+
+static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, target_ulong msr)
+{
+    CPUPPCState *env = &cpu->env;
+
     assert((msr & env->msr_mask) == msr);
 
     /*
@@ -376,21 +384,20 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
      * will prevent setting of the HV bit which some exceptions might need
      * to do.
      */
+    env->nip = vector;
     env->msr = msr;
     hreg_compute_hflags(env);
-    env->nip = vector;
-    /* Reset exception state */
-    cs->exception_index = POWERPC_EXCP_NONE;
-    env->error_code = 0;
 
-    /* Reset the reservation */
-    env->reserve_addr = -1;
+    powerpc_reset_excp_state(cpu);
 
     /*
      * Any interrupt is context synchronizing, check if TCG TLB needs
      * a delayed flush on ppc64
      */
     check_tlb_flush(env, false);
+
+    /* Reset the reservation */
+    env->reserve_addr = -1;
 }
 
 static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
@@ -471,8 +478,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
         case POWERPC_EXCP_FP:
             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
                 trace_ppc_excp_fp_ignore();
-                cs->exception_index = POWERPC_EXCP_NONE;
-                env->error_code = 0;
+                powerpc_reset_excp_state(cpu);
                 return;
             }
             env->spr[SPR_40x_ESR] = ESR_FP;
@@ -609,8 +615,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
         case POWERPC_EXCP_FP:
             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
                 trace_ppc_excp_fp_ignore();
-                cs->exception_index = POWERPC_EXCP_NONE;
-                env->error_code = 0;
+                powerpc_reset_excp_state(cpu);
                 return;
             }
 
@@ -783,8 +788,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
         case POWERPC_EXCP_FP:
             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
                 trace_ppc_excp_fp_ignore();
-                cs->exception_index = POWERPC_EXCP_NONE;
-                env->error_code = 0;
+                powerpc_reset_excp_state(cpu);
                 return;
             }
 
@@ -969,8 +973,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
         case POWERPC_EXCP_FP:
             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
                 trace_ppc_excp_fp_ignore();
-                cs->exception_index = POWERPC_EXCP_NONE;
-                env->error_code = 0;
+                powerpc_reset_excp_state(cpu);
                 return;
             }
 
@@ -1168,8 +1171,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
         case POWERPC_EXCP_FP:
             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
                 trace_ppc_excp_fp_ignore();
-                cs->exception_index = POWERPC_EXCP_NONE;
-                env->error_code = 0;
+                powerpc_reset_excp_state(cpu);
                 return;
             }
 
@@ -1406,8 +1408,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
         case POWERPC_EXCP_FP:
             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
                 trace_ppc_excp_fp_ignore();
-                cs->exception_index = POWERPC_EXCP_NONE;
-                env->error_code = 0;
+                powerpc_reset_excp_state(cpu);
                 return;
             }
 
-- 
2.23.0
Re: [PATCH 7/9] target/ppc: Add powerpc_reset_excp_state helper
Posted by Cédric Le Goater 3 years, 11 months ago 
On 2/15/22 04:16, Nicholas Piggin wrote:
> This moves the logic to reset the QEMU exception state into its own
> function.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>


Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.


> ---
>   target/ppc/excp_helper.c | 41 ++++++++++++++++++++--------------------
>   1 file changed, 21 insertions(+), 20 deletions(-)
> 
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 6b6ec71bc2..778eb4f3b0 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -360,12 +360,20 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr,
>   }
>   #endif
>   
> -static void powerpc_set_excp_state(PowerPCCPU *cpu,
> -                                          target_ulong vector, target_ulong msr)
> +static void powerpc_reset_excp_state(PowerPCCPU *cpu)
>   {
>       CPUState *cs = CPU(cpu);
>       CPUPPCState *env = &cpu->env;
>   
> +    /* Reset exception state */
> +    cs->exception_index = POWERPC_EXCP_NONE;
> +    env->error_code = 0;
> +}
> +
> +static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, target_ulong msr)
> +{
> +    CPUPPCState *env = &cpu->env;
> +
>       assert((msr & env->msr_mask) == msr);
>   
>       /*
> @@ -376,21 +384,20 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
>        * will prevent setting of the HV bit which some exceptions might need
>        * to do.
>        */
> +    env->nip = vector;
>       env->msr = msr;
>       hreg_compute_hflags(env);
> -    env->nip = vector;
> -    /* Reset exception state */
> -    cs->exception_index = POWERPC_EXCP_NONE;
> -    env->error_code = 0;
>   
> -    /* Reset the reservation */
> -    env->reserve_addr = -1;
> +    powerpc_reset_excp_state(cpu);
>   
>       /*
>        * Any interrupt is context synchronizing, check if TCG TLB needs
>        * a delayed flush on ppc64
>        */
>       check_tlb_flush(env, false);
> +
> +    /* Reset the reservation */
> +    env->reserve_addr = -1;
>   }
>   
>   static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> @@ -471,8 +478,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>           case POWERPC_EXCP_FP:
>               if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
>                   trace_ppc_excp_fp_ignore();
> -                cs->exception_index = POWERPC_EXCP_NONE;
> -                env->error_code = 0;
> +                powerpc_reset_excp_state(cpu);
>                   return;
>               }
>               env->spr[SPR_40x_ESR] = ESR_FP;
> @@ -609,8 +615,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>           case POWERPC_EXCP_FP:
>               if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
>                   trace_ppc_excp_fp_ignore();
> -                cs->exception_index = POWERPC_EXCP_NONE;
> -                env->error_code = 0;
> +                powerpc_reset_excp_state(cpu);
>                   return;
>               }
>   
> @@ -783,8 +788,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
>           case POWERPC_EXCP_FP:
>               if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
>                   trace_ppc_excp_fp_ignore();
> -                cs->exception_index = POWERPC_EXCP_NONE;
> -                env->error_code = 0;
> +                powerpc_reset_excp_state(cpu);
>                   return;
>               }
>   
> @@ -969,8 +973,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>           case POWERPC_EXCP_FP:
>               if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
>                   trace_ppc_excp_fp_ignore();
> -                cs->exception_index = POWERPC_EXCP_NONE;
> -                env->error_code = 0;
> +                powerpc_reset_excp_state(cpu);
>                   return;
>               }
>   
> @@ -1168,8 +1171,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
>           case POWERPC_EXCP_FP:
>               if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
>                   trace_ppc_excp_fp_ignore();
> -                cs->exception_index = POWERPC_EXCP_NONE;
> -                env->error_code = 0;
> +                powerpc_reset_excp_state(cpu);
>                   return;
>               }
>   
> @@ -1406,8 +1408,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
>           case POWERPC_EXCP_FP:
>               if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
>                   trace_ppc_excp_fp_ignore();
> -                cs->exception_index = POWERPC_EXCP_NONE;
> -                env->error_code = 0;
> +                powerpc_reset_excp_state(cpu);
>                   return;
>               }
>   
>

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